NOT gate
========

This is an NOT gate

.. symbolator:: not.sim.v

.. verilog-diagram:: not.sim.v
   :type: netlistsvg
   :module: NOT

|

.. no-license:: not.sim.v
   :language: verilog
   :caption: not.sim.v

The gate model generated by V2X

.. literalinclude:: not.model.xml
   :language: xml
   :caption: not.model.xml

The gate pb_type generated by V2X

.. literalinclude:: not.pb_type.xml
   :language: xml
   :caption: not.pb_type.xml