tests/vtr/full-adder/README.md

# Full Adder Example

An example of the classical combinational ["full adder"](https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder) circuit.

This is shown in `Figure 41 - Full Adder` of the
["Combinational block"](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block)
section in the
[Primitive Block Timing Modeling Tutorial](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#)
of the
[Verilog to Routing documentation](https://docs.verilogtorouting.org)
and reproduced below;

> ![Figure 41 from Verilog to Routing Documentation](full-adder.svg)
> *Fig. 41 Full Adder*

## Detection of combinational connections

 - [ ] output has combinational connection with input

## Blackbox detection

 - [ ] model of the leaf `pb_type` is generated
 - [ ] leaf `pb_type` XML is generated

## Timings

 - [ ] all the timings defined for wires with attributes should be included in `pb_type` XML