This test features a Litex design with a Linux capable VexRiscv CPU. The firmware is compiled into the bitstream and the ROM and SRAM memories are instantiated and initialized on the FPGA. DDR3 memory is used as the main_ram.
In order to run one of them enter the specific directory and run make. Once the bitstream is generated and loaded to the board, we should see the test result on the terminal connected to one of the serial ports.
The HDL code is generated from litex-buildenv
The buildenv project can also generate all necessary software for running Linux on the system. Follow the buildenv's Linux guide to see how to generate and run the software. Since this test targets the Arty A7-35T board make sure to export the following variables before building the software:
export CPU=vexriscv export CPU_VARIANT=linux export PLATFORM=arty export FIRMWARE=linux
To create baselitex_arty100t.v, copy from baselitex_arty.v and then make the following edits:
(* LOC="PLLE2_ADV_X1Y1" *) to instance PLLE2_ADV.(* LOC="IDELAYCTRL_X1Y0" *) to (* LOC="IDELAYCTRL_X1Y1" *) on instance IDELAYCTRL.