Merge pull request #2349 from umarcor/dependabot
ci: add dependabot config file
diff --git a/.github/check-status/Dockerfile b/.github/check-status/Dockerfile
index d4ebead..97822f4 100644
--- a/.github/check-status/Dockerfile
+++ b/.github/check-status/Dockerfile
@@ -1,6 +1,6 @@
FROM python:alpine
-RUN apk add git && pip install PyGithub git+https://github.com/SymbiFlow/symbiflow-tools-data-manager#egg=stdm --progress-bar off
+RUN apk update && apk add git gcc libc-dev libffi-dev && pip install PyGithub git+https://github.com/SymbiFlow/symbiflow-tools-data-manager#egg=stdm --progress-bar off
COPY check-status.py /check-status.py
COPY entrypoint.sh /entrypoint.sh
diff --git a/.gitmodules b/.gitmodules
index 424270b..4d64ff1 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -58,9 +58,6 @@
[submodule "third_party/pythondata-software-compiler_rt"]
path = third_party/pythondata-software-compiler_rt
url = https://github.com/litex-hub/pythondata-software-compiler_rt
-[submodule "third_party/qlfpga-symbiflow-plugins"]
- path = third_party/qlfpga-symbiflow-plugins
- url = https://github.com/QuickLogic-Corp/qlfpga-symbiflow-plugins.git
[submodule "third_party/qlf-fasm"]
path = third_party/qlf-fasm
url = https://github.com/QuickLogic-Corp/ql_fasm.git
diff --git a/common/cmake/devices.cmake b/common/cmake/devices.cmake
index 1f9c14d..b1218e1 100644
--- a/common/cmake/devices.cmake
+++ b/common/cmake/devices.cmake
@@ -1608,7 +1608,7 @@
PINMAP_FILE=${PINMAP}
PYTHON3=${PYTHON3}
${ADD_FPGA_TARGET_DEFINES}
- ${QUIET_CMD} ${YOSYS} -p "${COMPLETE_YOSYS_SYNTH_SCRIPT}" -l ${OUT_JSON_SYNTH}.log ${SOURCE_FILES}
+ ${QUIET_CMD} ${YOSYS} -r ${TOP} -p "${COMPLETE_YOSYS_SYNTH_SCRIPT}" -l ${OUT_JSON_SYNTH}.log ${SOURCE_FILES}
COMMAND
${CMAKE_COMMAND} -E touch ${OUT_FASM_EXTRA}
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
@@ -2703,7 +2703,9 @@
get_target_property_required(PYTHON3 env PYTHON3)
get_target_property_required(QUIET_CMD env QUIET_CMD)
+ set(NAME ${GENERATE_PINMAP_NAME})
set(BOARD ${GENERATE_PINMAP_BOARD})
+ set(TOP ${GENERATE_PINMAP_TOP})
get_target_property_required(DEVICE ${BOARD} DEVICE)
get_target_property_required(PACKAGE ${BOARD} PACKAGE)
get_target_property_required(PINMAP_FILE ${BOARD} PINMAP)
@@ -2720,8 +2722,8 @@
endforeach()
add_custom_command(
- OUTPUT ${GENERATE_PINMAP_NAME}.json
- COMMAND ${QUIET_CMD} ${YOSYS} -p \"proc $<SEMICOLON> write_json ${CMAKE_CURRENT_BINARY_DIR}/${GENERATE_PINMAP_NAME}.json\" -l ${CMAKE_CURRENT_BINARY_DIR}/${GENERATE_PINMAP_NAME}.json.log ${SOURCE_FILES}
+ OUTPUT ${NAME}.json
+ COMMAND ${QUIET_CMD} ${YOSYS} -r ${TOP} -p \"proc $<SEMICOLON> write_json ${CMAKE_CURRENT_BINARY_DIR}/${NAME}.json\" -l ${CMAKE_CURRENT_BINARY_DIR}/${NAME}.json.log ${SOURCE_FILES}
DEPENDS
${QUIET_CMD}
${YOSYS}
@@ -2730,16 +2732,16 @@
)
add_custom_command(
- OUTPUT ${GENERATE_PINMAP_NAME}
+ OUTPUT ${NAME}
COMMAND ${PYTHON3} ${CREATE_PINMAP}
- --design_json ${CMAKE_CURRENT_BINARY_DIR}/${GENERATE_PINMAP_NAME}.json
+ --design_json ${CMAKE_CURRENT_BINARY_DIR}/${NAME}.json
--pinmap_csv ${PINMAP}
- --module ${GENERATE_PINMAP_TOP} > ${CMAKE_CURRENT_BINARY_DIR}/${GENERATE_PINMAP_NAME}
+ --module ${TOP} > ${CMAKE_CURRENT_BINARY_DIR}/${NAME}
DEPENDS
${PYTHON3}
${CREATE_PINMAP}
${PINMAP} ${PINMAP_TARGET}
- ${GENERATE_PINMAP_NAME}.json
+ ${NAME}.json
)
add_file_target(FILE ${GENERATE_PINMAP_NAME} GENERATED)
diff --git a/conda_lock.yml b/conda_lock.yml
index 0da6223..a53a319 100644
--- a/conda_lock.yml
+++ b/conda_lock.yml
@@ -5,24 +5,24 @@
dependencies:
- _libgcc_mutex=0.1=main
- _openmp_mutex=4.5=1_gnu
- - binutils-riscv64-elf=2.34=20211006_163223
+ - binutils-riscv64-elf=2.34=20220104_202018
- bison=3.7.5=h2531618_1
- bzip2=1.0.8=h7b6447c_0
- - c-ares=1.17.1=h27cfd23_0
+ - c-ares=1.18.1=h7f8727e_0
- ca-certificates=2021.10.26=h06a4308_2
- capnproto=0.8.0=20210316_201220
- capnproto-java=0.1.5_0012_g44a8c1e=20201104_165332
- - certifi=2021.10.8=py37h06a4308_0
+ - certifi=2021.10.8=py37h06a4308_2
- cloog=0.18.0=0
- - cmake=3.19.6=h973ab73_0
- - cython=0.29.24=py37hdbfa776_0
+ - cmake=3.22.1=h1fce559_0
+ - cython=0.29.25=py37hdbfa776_0
- expat=2.4.1=h2531618_2
- flake8=3.9.2=pyhd3eb1b0_0
- flex=2.6.4=ha10e3a4_1
- gcc-riscv64-elf-newlib=9.2.0=20201119_154229
- gcc-riscv64-elf-nostdc=9.2.0=20210923_213204
- gmp=6.2.1=h2531618_2
- - gperftools=2.9.1_3_gc259412=20211122_104637
+ - gperftools=2.9.1_6_ge80652b=20220114_081711
- icestorm=0.0_0719_g792cef0=20201120_145821
- icu=58.2=he6710b0_3
- importlib-metadata=4.8.2=py37h06a4308_0
@@ -30,11 +30,11 @@
- iverilog=s20150603_0957_gad862020=20201120_145821
- krb5=1.19.2=hac12032_0
- ld_impl_linux-64=2.35.1=h7274673_9
- - libcurl=7.78.0=h0b77cf5_0
+ - libcurl=7.80.0=h0b77cf5_0
- libedit=3.1.20210910=h7f8727e_0
- libev=4.33=h7f8727e_1
- libffi=3.3=he6710b0_2
- - libftdi=1.3=20210923_083448
+ - libftdi=1.3=20220104_201921
- libgcc-ng=9.3.0=h5101ec6_17
- libgomp=9.3.0=h5101ec6_17
- libiconv=1.15=h63c8f33_5
@@ -42,7 +42,7 @@
- libssh2=1.9.0=h1ba5d50_1
- libstdcxx-ng=9.3.0=hd4cf53a_17
- libunwind=1.5.0=h295c915_1
- - libusb=1.0.20=20210923_083448
+ - libusb=1.0.20=20220104_201921
- libuuid=1.0.3=h7f8727e_2
- libuv=1.40.0=h7b6447c_0
- libxml2=2.9.12=h03d6c58_0
@@ -56,57 +56,57 @@
- nodejs=10.13.0=he6710b0_0
- openjdk=8.0.152=h7b6447c_3
- openocd=0.10.0_1514_ga8edbd020=20201119_154304
- - openssl=1.1.1l=h7f8727e_0
+ - openssl=1.1.1m=h7f8727e_0
- packaging=21.3=pyhd3eb1b0_0
- pcre=8.45=h295c915_0
- perl=5.26.2=h14c3975_0
- pip=21.2.2=py37h06a4308_0
- pkg-config=0.29.2=h1bed415_8
- - prjxray-db=0.0_253_gcd41f08=20211122_104637
- - prjxray-tools=0.1_2934_g60168e9b=20211122_104637
+ - prjxray-db=0.0_257_g0a0adde=20220114_081711
+ - prjxray-tools=0.1_2942_g5349556b=20220114_081711
- pycodestyle=2.7.0=pyhd3eb1b0_0
- pyflakes=2.3.1=pyhd3eb1b0_0
- pyparsing=3.0.4=pyhd3eb1b0_0
- python=3.7.11=h12debd9_0
- - readline=8.1=h27cfd23_0
+ - readline=8.1.2=h7f8727e_1
- rhash=1.4.1=h3c74f83_1
- setuptools=58.0.4=py37h06a4308_0
- - sqlite=3.36.0=hc218d9a_0
- - surelog=0.0_3778_gffd348877=20211122_104637_py37
+ - sqlite=3.37.0=hc218d9a_0
+ - surelog=0.0_4027_g84b7eb870=20220114_081711_py37
- swig=4.0.2=h295c915_4
- - symbiflow-yosys-plugins=1.0.0_7_511_g6c4141c=20211122_104637
+ - symbiflow-yosys-plugins=1.0.0_7_599_gdb3a9c7=20220114_081711
- tbb=2020.3=hfd86e86_0
- tk=8.6.11=h1ccaba5_0
- typing_extensions=3.10.0.2=pyh06a4308_0
- - vtr-optimized=8.0.0_4986_gf92cfebaf=20211122_104637
- - wheel=0.37.0=pyhd3eb1b0_1
+ - vtr-optimized=8.0.0_5105_g116f30cb8=20220114_081711
+ - wheel=0.37.1=pyhd3eb1b0_0
- xz=5.2.5=h7b6447c_0
- - yosys=0.11_48_g113c94384=20211122_104637_py37
+ - yosys=0.13_4_g61324cf55=20220114_081711_py37
- zachjs-sv2v=0.0.5_0025_ge9f9696=20201120_205532
- - zipp=3.6.0=pyhd3eb1b0_0
- - zlib=1.2.11=h7b6447c_3
- - zstd=1.4.9=haebb681_0
+ - zipp=3.7.0=pyhd3eb1b0_0
+ - zlib=1.2.11=h7f8727e_4
+ - zstd=1.5.0=ha4553b6_1
- pip:
- Arpeggio==1.10.2
- - attrs==21.2.0
+ - attrs==21.4.0
- cairocffi==1.3.0
- CairoSVG==2.5.2
- certifi==2021.10.8
- cffi==1.15.0
- chardet==4.0.0
- - charset-normalizer==2.0.9
+ - charset-normalizer==2.0.10
- colorama==0.4.4
- - cryptography==36.0.0
+ - cryptography==36.0.1
- cssselect2==0.4.1
- cycler==0.11.0
- defusedxml==0.7.1
- edalize @ git+https://github.com/lowRISC/edalize.git@23e1beab41508e13c565125e5edcadb86b0032f6
- fasm==0.0.2.post80
- fasm-utils @ git+https://github.com/QuickLogic-Corp/quicklogic-fasm-utils@3d6a375ddb6b55aaa5a59d99e44a207d4c18709f
- - fonttools==4.28.3
+ - fonttools==4.28.5
- fusesoc @ git+https://github.com/lowRISC/fusesoc.git@14dfc825ced58fe1fb343662fa80fc4fbd0fdc50
- gitdb==4.0.9
- - GitPython==3.1.24
+ - GitPython==3.1.26
- hilbertcurve==1.0.5
- idna==3.3
- importlib-resources==5.4.0
@@ -115,41 +115,40 @@
- intervaltree==3.1.0
- Jinja2==3.0.3
- jsonmerge==1.8.0
- - jsonschema==4.2.1
+ - jsonschema==4.4.0
- kiwisolver==1.3.2
- - lxml==4.6.4
+ - lxml==4.7.1
- Mako==1.1.6
- MarkupSafe==2.0.1
- - matplotlib==3.5.0
+ - matplotlib==3.5.1
- mccabe==0.6.1
- - numpy==1.21.4
+ - numpy==1.21.5
- okonomiyaki==1.3.2
- parameterized==0.8.1
- pdfminer.six==20211012
- - Pillow==8.4.0
+ - Pillow==9.0.0
- pluggy==1.0.0
- ply==3.11
- - progressbar2==3.55.0
+ - progressbar2==4.0.0
- py==1.11.0
- pycapnp==1.0.0b1
- pycparser==2.21
- pyjson==1.3.0
- pyjson5==1.6.0
- - pyrsistent==0.18.0
+ - pyrsistent==0.18.1
- pyserial==3.5
- pytest==6.2.5
- python-constraint==1.4.0
- python-dateutil==2.8.2
- python-fpga-interchange @ git+https://github.com/SymbiFlow/python-fpga-interchange.git@b13ee55ebce358a488fe9087f3b4f1bf087a0f24
- python-sat==0.1.7.dev15
- - python-utils==2.5.6
+ - python-utils==3.1.0
- pyusb==1.2.1
- PyYAML==6.0
- quicklogic-fasm @ git+https://github.com/QuickLogic-Corp/quicklogic-fasm.git@57b6e60574a9d483dc94710d0d3ff42a62b4ec41
- - requests==2.26.0
+ - requests==2.27.1
- rr-graph @ git+https://github.com/SymbiFlow/symbiflow-rr-graph.git@f0c41b77ad25b3afc438f4a7bff4c2297f6587d5
- scipy==1.7.3
- - setuptools-scm==6.3.2
- simplejson==3.17.6
- simplesat==0.8.2
- six==1.16.0
@@ -162,9 +161,8 @@
- tinyfpgab==1.1.0
- tinyprog==1.0.21
- toml==0.10.2
- - tomli==1.2.2
- tqdm==4.62.3
- - urllib3==1.26.7
+ - urllib3==1.26.8
- webencodings==0.5.1
- yapf==0.26.0
- zipfile2==0.0.12
diff --git a/environment.yml b/environment.yml
index a8437be..2713ff2 100644
--- a/environment.yml
+++ b/environment.yml
@@ -14,6 +14,7 @@
- litex-hub::vtr-optimized
- litex-hub::yosys
- litex-hub::symbiflow-yosys-plugins
+ - litex-hub::surelog
- litex-hub::zachjs-sv2v=0.0.5_0025_ge9f9696=20201120_205532
- cmake
- make
diff --git a/quicklogic/CMakeLists.txt b/quicklogic/CMakeLists.txt
index 1ccdc8b..85d26f9 100644
--- a/quicklogic/CMakeLists.txt
+++ b/quicklogic/CMakeLists.txt
@@ -1,6 +1,9 @@
-set(QLF_FPGA_DATABASE_DIR ${symbiflow-arch-defs_SOURCE_DIR}/third_party/qlfpga-symbiflow-plugins)
-
add_subdirectory(common)
+add_quicklogic_plugins()
+
+set(QLF_FPGA_DATABASE_DIR ${symbiflow-arch-defs_BINARY_DIR}/quicklogic/third_party/qlfpga-symbiflow-plugins)
+set(QLF_FPGA_PLUGINS_DIR ${symbiflow-arch-defs_SOURCE_DIR}/quicklogic/third_party/qlfpga-symbiflow-plugins)
+
add_subdirectory(qlf_k4n8)
add_subdirectory(pp3)
diff --git a/quicklogic/common/cmake/CMakeLists.txt b/quicklogic/common/cmake/CMakeLists.txt
index 3855944..052fc33 100644
--- a/quicklogic/common/cmake/CMakeLists.txt
+++ b/quicklogic/common/cmake/CMakeLists.txt
@@ -6,3 +6,4 @@
include(quicklogic_toolchain_test.cmake)
include(quicklogic_jlink.cmake)
include(quicklogic_openocd.cmake)
+include(quicklogic_env.cmake)
diff --git a/quicklogic/common/cmake/quicklogic_env.cmake b/quicklogic/common/cmake/quicklogic_env.cmake
new file mode 100644
index 0000000..1ce5504
--- /dev/null
+++ b/quicklogic/common/cmake/quicklogic_env.cmake
@@ -0,0 +1,85 @@
+function(ADD_QUICKLOGIC_PLUGINS)
+ set(QLFPGA_LATEST_URL https://storage.googleapis.com/symbiflow-arch-defs-install/qlfpga_symbiflow_plugins/qlf_k4n8/latest)
+
+ set(QLFPGA_LATEST_REL latest)
+ set(QLFPGA_REPACKING_RULES_REL repacking_rules.json)
+ set(QLFPGA_FASM_DB_TAR_GZ_REL fasm_database.tar.gz)
+ set(QLFPGA_FASM_DB_REL fasm_database)
+ set(QLFPGA_FAST_VPR_ARCH_REL fast/vpr_arch/UMC22nm_vpr.xml)
+ set(QLFPGA_FAST_VPR_RR_GRAPH_REL fast/vpr_rr_graph/UMC22nm_vpr.bin.gz)
+ set(QLFPGA_SLOW_VPR_ARCH_REL slow/vpr_arch/UMC22nm_vpr.xml)
+ set(QLFPGA_SLOW_VPR_RR_GRAPH_REL slow/vpr_rr_graph/UMC22nm_vpr.bin.gz)
+
+ set(QLFPGA_BASE_DIR third_party/qlfpga-symbiflow-plugins/qlf_k4n8)
+
+ set(QLFPGA_LATEST ${QLFPGA_BASE_DIR}/${QLFPGA_LATEST_REL})
+ set(QLFPGA_REPACKING_RULES ${QLFPGA_BASE_DIR}/${QLFPGA_REPACKING_RULES_REL})
+ set(QLFPGA_FASM_DB_TAR_GZ ${QLFPGA_BASE_DIR}/${QLFPGA_FASM_DB_TAR_GZ_REL})
+ set(QLFPGA_FASM_DB ${QLFPGA_BASE_DIR}/${QLFPGA_FASM_DB_REL})
+ set(QLFPGA_FAST_VPR_ARCH ${QLFPGA_BASE_DIR}/${QLFPGA_FAST_VPR_ARCH_REL})
+ set(QLFPGA_FAST_VPR_RR_GRAPH ${QLFPGA_BASE_DIR}/${QLFPGA_FAST_VPR_RR_GRAPH_REL})
+ set(QLFPGA_SLOW_VPR_ARCH ${QLFPGA_BASE_DIR}/${QLFPGA_SLOW_VPR_ARCH_REL})
+ set(QLFPGA_SLOW_VPR_RR_GRAPH ${QLFPGA_BASE_DIR}/${QLFPGA_SLOW_VPR_RR_GRAPH_REL})
+
+ # File with pointer to the latest version of qlfpga plugins
+ add_custom_command(
+ OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${QLFPGA_LATEST}
+ COMMAND
+ ${CMAKE_COMMAND} -E make_directory
+ ${QLFPGA_BASE_DIR}
+ COMMAND bash -c
+ 'wget ${QLFPGA_LATEST_URL} -O ${QLFPGA_LATEST}'
+ COMMENT "Generating ${QLFPGA_LATEST}"
+ )
+ add_file_target(FILE ${QLFPGA_LATEST} GENERATED)
+
+ fetch_qlfpga(${QLFPGA_REPACKING_RULES} ${QLFPGA_REPACKING_RULES_REL})
+ fetch_qlfpga(${QLFPGA_FASM_DB_TAR_GZ} ${QLFPGA_FASM_DB_TAR_GZ_REL})
+ fetch_qlfpga(${QLFPGA_FAST_VPR_ARCH} ${QLFPGA_FAST_VPR_ARCH_REL})
+ fetch_qlfpga(${QLFPGA_FAST_VPR_RR_GRAPH} ${QLFPGA_FAST_VPR_RR_GRAPH_REL})
+ fetch_qlfpga(${QLFPGA_SLOW_VPR_ARCH} ${QLFPGA_SLOW_VPR_ARCH_REL})
+ fetch_qlfpga(${QLFPGA_SLOW_VPR_RR_GRAPH} ${QLFPGA_SLOW_VPR_RR_GRAPH_REL})
+
+ get_file_target(QLFPGA_FASM_DB_TAR_GZ_TARGET ${QLFPGA_FASM_DB_TAR_GZ})
+ add_custom_command(
+ OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${QLFPGA_FASM_DB}
+ COMMAND bash -c 'tar -xf ${QLFPGA_FASM_DB_TAR_GZ} -C ${QLFPGA_BASE_DIR}'
+ DEPENDS ${QLFPGA_FASM_DB_TAR_GZ_TARGET}
+ COMMENT "Generating ${QLFPGA_FASM_DB}"
+ )
+ add_file_target(FILE ${QLFPGA_FASM_DB} GENERATED)
+
+ set(QLFPGA_PLUGINS_FILES
+ ${QLFPGA_REPACKING_RULES}
+ ${QLFPGA_FASM_DB}
+ ${QLFPGA_FAST_VPR_ARCH}
+ ${QLFPGA_FAST_VPR_RR_GRAPH}
+ ${QLFPGA_SLOW_VPR_ARCH}
+ ${QLFPGA_SLOW_VPR_RR_GRAPH}
+ )
+
+ set(QLFPGA_PLUGINS_DEPS )
+ foreach(FILE_NAME ${QLFPGA_PLUGINS_FILES})
+ get_file_target(FILE_TARGET ${FILE_NAME})
+ list(APPEND QLFPGA_PLUGINS_DEPS ${FILE_TARGET})
+ endforeach()
+
+ add_custom_target(qlfpga_plugins
+ DEPENDS ${QLFPGA_PLUGINS_DEPS}
+ )
+endfunction()
+
+function(FETCH_QLFPGA FILE_PATH FILE_REL_PATH)
+
+ get_filename_component(FILE_DIRECTORY ${FILE_PATH} DIRECTORY)
+ get_file_target(QLFPGA_LATEST_TARGET ${QLFPGA_LATEST})
+
+ add_custom_command(
+ OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${FILE_PATH}
+ COMMAND ${CMAKE_COMMAND} -E make_directory ${FILE_DIRECTORY}
+ COMMAND bash -c 'wget `cat ${QLFPGA_LATEST}`/${FILE_REL_PATH} -O ${FILE_PATH}'
+ DEPENDS ${QLFPGA_LATEST_TARGET}
+ COMMENT "Generating ${FILE_PATH}"
+ )
+ add_file_target(FILE ${FILE_PATH} GENERATED)
+endfunction()
diff --git a/quicklogic/common/cmake/quicklogic_install.cmake b/quicklogic/common/cmake/quicklogic_install.cmake
index 7fc3229..016c415 100644
--- a/quicklogic/common/cmake/quicklogic_install.cmake
+++ b/quicklogic/common/cmake/quicklogic_install.cmake
@@ -218,8 +218,10 @@
if(NOT "${DEVICE}" STREQUAL "ql-pp3e" AND NOT "${DEVICE}" STREQUAL "ql-eos-s3")
# install lib files
- install(DIRECTORY ${QLF_FPGA_DATABASE_DIR}/${FAMILY}/lib/
- DESTINATION "share/symbiflow/arch/${DEVICE}_${PACKAGE}/lib")
+ if(EXISTS "${QLF_FPGA_DATABASE_DIR}/${FAMILY}/lib" AND IS_DIRECTORY "${QLF_FPGA_DATABASE_DIR}/${FAMILY}/lib")
+ install(DIRECTORY ${QLF_FPGA_DATABASE_DIR}/${FAMILY}/lib/
+ DESTINATION "share/symbiflow/arch/${DEVICE}_${PACKAGE}/lib")
+ endif()
else()
message(status ": workaround: skipping lib install for ${DEVICE} device")
endif()
diff --git a/quicklogic/common/cmake/quicklogic_qlf_arch.cmake b/quicklogic/common/cmake/quicklogic_qlf_arch.cmake
index 7a6c5e0..3e70152 100644
--- a/quicklogic/common/cmake/quicklogic_qlf_arch.cmake
+++ b/quicklogic/common/cmake/quicklogic_qlf_arch.cmake
@@ -37,6 +37,14 @@
set(SDC_PATCH_TOOL ${symbiflow-arch-defs_SOURCE_DIR}/quicklogic/common/utils/process_sdc_constraints.py)
+ set(ARCH_DIR ${QLF_FPGA_PLUGINS_DIR}/${ARCH})
+ set(ARCH_DIR_REL ${QLF_FPGA_DATABASE_DIR}/${ARCH})
+ set(QLFPGA_FASM_DATABASE_LOC ${ARCH_DIR}/fasm_database)
+ set(QLFPGA_FASM_DATABASE_LOC_REL ${ARCH_DIR_REL}/fasm_database)
+
+ set(FASM_TO_BIT_DEPS "")
+ append_file_dependency(FASM_TO_BIT_DEPS ${QLFPGA_FASM_DATABASE_LOC})
+
# Define the architecture
define_arch(
FAMILY ${FAMILY}
@@ -96,18 +104,19 @@
FASM_TO_BIT_CMD "${CMAKE_COMMAND} -E env \
PYTHONPATH=${symbiflow-arch-defs_BINARY_DIR}/env/conda/lib/python3.7/site-packages \
\${QUIET_CMD} \${FASM_TO_BIT} \
- --db-root ${QLF_FPGA_DATABASE_DIR}/${ARCH}/fasm_database \
+ --db-root ${QLFPGA_FASM_DATABASE_LOC_REL} \
--assemble \
--format 4byte \
\${OUT_FASM} \
\${OUT_BITSTREAM} "
+ FASM_TO_BIT_DEPS ${FASM_TO_BIT_DEPS}
BIN_EXTENSION bin
BIT_TO_BIN ${QLF_FASM}
BIT_TO_BIN_CMD "${CMAKE_COMMAND} -E env \
PYTHONPATH=${symbiflow-arch-defs_BINARY_DIR}/env/conda/lib/python3.7/site-packages \
\${QUIET_CMD} \${FASM_TO_BIT} \
- --db-root ${QLF_FPGA_DATABASE_DIR}/${ARCH}/fasm_database \
+ --db-root ${QLFPGA_FASM_DATABASE_LOC_REL} \
--assemble \
--format txt \
\${OUT_FASM} \
@@ -117,7 +126,7 @@
BIT_TO_FASM_CMD "${CMAKE_COMMAND} -E env \
PYTHONPATH=${symbiflow-arch-defs_BINARY_DIR}/env/conda/lib/python3.7/site-packages \
\${QUIET_CMD} \${BIT_TO_FASM} \
- --db-root ${QLF_FPGA_DATABASE_DIR}/${ARCH}/fasm_database \
+ --db-root ${QLFPGA_FASM_DATABASE_LOC_REL} \
--disassemble \
--format 4byte \
\${OUT_BITSTREAM} \
diff --git a/quicklogic/common/cmake/quicklogic_qlf_device.cmake b/quicklogic/common/cmake/quicklogic_qlf_device.cmake
index 38ba61b..88f3d34 100644
--- a/quicklogic/common/cmake/quicklogic_qlf_device.cmake
+++ b/quicklogic/common/cmake/quicklogic_qlf_device.cmake
@@ -49,14 +49,23 @@
# .......................................................
- # Copy VPR arch XML
set(ARCH_XML_NAME ${DEVICE}.arch.xml)
+ # If there is a file target then depend on it
+ get_file_target(ARCH_XML_TARGET ${ARCH_XML})
+ if (TARGET "${ARCH_XML_TARGET}")
+ set(ARCH_XML_DEP ${ARCH_XML_TARGET})
+ get_file_location(ARCH_XML ${ARCH_XML})
+ else ()
+ set(ARCH_XML_DEP ${ARCH_XML})
+ endif ()
+
+ # Copy VPR arch XML
add_custom_command(
OUTPUT
${CMAKE_CURRENT_BINARY_DIR}/${ARCH_XML_NAME}
DEPENDS
- ${ARCH_XML}
+ ${ARCH_XML_DEP}
COMMAND
${CMAKE_COMMAND} -E copy
${ARCH_XML}
@@ -69,6 +78,15 @@
set(RR_GRAPH_FOR_DEVICE ${DEVICE}.rr_graph.bin)
+ # If there is a file target then depend on it
+ get_file_target(RR_GRAPH_TARGET ${RR_GRAPH})
+ if (TARGET "${RR_GRAPH_TARGET}")
+ set(RR_GRAPH_DEP ${RR_GRAPH_TARGET})
+ get_file_location(RR_GRAPH ${RR_GRAPH})
+ else ()
+ set(RR_GRAPH_DEP ${RR_GRAPH})
+ endif ()
+
# If the routing graph is compressed uncompress it
if ("${RR_GRAPH}" MATCHES ".*\\.gz$")
@@ -76,7 +94,7 @@
OUTPUT
${CMAKE_CURRENT_BINARY_DIR}/${RR_GRAPH_FOR_DEVICE}
DEPENDS
- ${RR_GRAPH}
+ ${RR_GRAPH_DEP}
COMMAND
${CMAKE_COMMAND} -E copy
${RR_GRAPH}
@@ -92,7 +110,7 @@
OUTPUT
${CMAKE_CURRENT_BINARY_DIR}/${RR_GRAPH_FOR_DEVICE}
DEPENDS
- ${RR_GRAPH}
+ ${RR_GRAPH_DEP}
COMMAND
${CMAKE_COMMAND} -E copy
${RR_GRAPH}
@@ -105,14 +123,23 @@
# .......................................................
- # Copy repacking rules
set(REPACKING_RULES_NAME ${DEVICE}.repacking_rules.json)
+ # If there is a file target then depend on it
+ get_file_target(REPACKING_RULES_TARGET ${REPACKING_RULES})
+ if (TARGET "${REPACKING_RULES_TARGET}")
+ set(REPACKING_RULES_DEP ${REPACKING_RULES_TARGET})
+ get_file_location(REPACKING_RULES ${REPACKING_RULES})
+ else ()
+ set(REPACKING_RULES_DEP ${REPACKING_RULES})
+ endif ()
+
+ # Copy repacking rules
add_custom_command(
OUTPUT
${CMAKE_CURRENT_BINARY_DIR}/${REPACKING_RULES_NAME}
DEPENDS
- ${ARCH_XML}
+ ${REPACKING_RULES_DEP}
COMMAND
${CMAKE_COMMAND} -E copy
${REPACKING_RULES}
diff --git a/quicklogic/common/utils/CMakeLists.txt b/quicklogic/common/utils/CMakeLists.txt
index 80c5711..876d8c8 100644
--- a/quicklogic/common/utils/CMakeLists.txt
+++ b/quicklogic/common/utils/CMakeLists.txt
@@ -6,6 +6,7 @@
${CMAKE_COMMAND} -E env
PYTHONPATH=${symbiflow-arch-defs_SOURCE_DIR}/utils:${symbiflow-arch-defs_SOURCE_DIR}/quicklogic/common/utils:$PYTHONPATH
${PYTHON3} -m pytest --doctest-modules -vv
+ DEPENDS qlfpga_plugins
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
diff --git a/quicklogic/common/utils/repacker/tests/lut_padding/test_lut_padding.py b/quicklogic/common/utils/repacker/tests/lut_padding/test_lut_padding.py
index 0cc903a..b916c32 100644
--- a/quicklogic/common/utils/repacker/tests/lut_padding/test_lut_padding.py
+++ b/quicklogic/common/utils/repacker/tests/lut_padding/test_lut_padding.py
@@ -28,8 +28,8 @@
basedir = os.path.dirname(__file__)
qlfpga_plugins = os.path.join(
- basedir, "..", "..", "..", "..", "..", "..", "third_party",
- "qlfpga-symbiflow-plugins"
+ basedir, "..", "..", "..", "..", "..", "..", "build", "quicklogic",
+ "third_party", "qlfpga-symbiflow-plugins"
)
vpr_arch = os.path.join(
diff --git a/quicklogic/qlf_k4n8/devices/umc22/CMakeLists.txt b/quicklogic/qlf_k4n8/devices/umc22/CMakeLists.txt
index 3ea76a8..9cea234 100644
--- a/quicklogic/qlf_k4n8/devices/umc22/CMakeLists.txt
+++ b/quicklogic/qlf_k4n8/devices/umc22/CMakeLists.txt
@@ -1,31 +1,37 @@
set(ARCH qlf_k4n8)
-set(ARCH_DIR ${QLF_FPGA_DATABASE_DIR}/${ARCH})
-
+set(ARCH_DIR ${QLF_FPGA_PLUGINS_DIR}/${ARCH})
set(FAST_CORNER_ARCH_DIR ${ARCH_DIR}/fast)
+set(SLOW_CORNER_ARCH_DIR ${ARCH_DIR}/slow)
+
+set(QLFPGA_REPACKING_RULES_LOC ${ARCH_DIR}/repacking_rules.json)
+set(QLFPGA_FAST_ARCH_XML_LOC ${FAST_CORNER_ARCH_DIR}/vpr_arch/UMC22nm_vpr.xml)
+set(QLFPGA_FAST_RR_GRAPH_LOC ${FAST_CORNER_ARCH_DIR}/vpr_rr_graph/UMC22nm_vpr.bin.gz)
+set(QLFPGA_SLOW_ARCH_XML_LOC ${SLOW_CORNER_ARCH_DIR}/vpr_arch/UMC22nm_vpr.xml)
+set(QLFPGA_SLOW_RR_GRAPH_LOC ${SLOW_CORNER_ARCH_DIR}/vpr_rr_graph/UMC22nm_vpr.bin.gz)
+
quicklogic_define_qlf_device (
NAME ${ARCH}_umc22_fast
ARCH ${ARCH}
FAMILY ${ARCH}
LAYOUT 24x24
- ARCH_XML ${FAST_CORNER_ARCH_DIR}/vpr_arch/UMC22nm_vpr.xml
- RR_GRAPH ${FAST_CORNER_ARCH_DIR}/vpr_rr_graph/UMC22nm_vpr.bin.gz
+ ARCH_XML ${QLFPGA_FAST_ARCH_XML_LOC}
+ RR_GRAPH ${QLFPGA_FAST_RR_GRAPH_LOC}
- REPACKING_RULES ${ARCH_DIR}/repacking_rules.json
+ REPACKING_RULES ${QLFPGA_REPACKING_RULES_LOC}
ROUTE_CHAN_WIDTH 60
)
-set(SLOW_CORNER_ARCH_DIR ${ARCH_DIR}/slow)
quicklogic_define_qlf_device (
NAME ${ARCH}_umc22_slow
ARCH ${ARCH}
FAMILY ${ARCH}
LAYOUT 24x24
- ARCH_XML ${SLOW_CORNER_ARCH_DIR}/vpr_arch/UMC22nm_vpr.xml
- RR_GRAPH ${SLOW_CORNER_ARCH_DIR}/vpr_rr_graph/UMC22nm_vpr.bin.gz
+ ARCH_XML ${QLFPGA_SLOW_ARCH_XML_LOC}
+ RR_GRAPH ${QLFPGA_SLOW_RR_GRAPH_LOC}
- REPACKING_RULES ${ARCH_DIR}/repacking_rules.json
+ REPACKING_RULES ${QLFPGA_REPACKING_RULES_LOC}
ROUTE_CHAN_WIDTH 60
)
diff --git a/quicklogic/qlf_k4n8/tests/synth_flow/rgb2ycrcb/CMakeLists.txt b/quicklogic/qlf_k4n8/tests/synth_flow/rgb2ycrcb/CMakeLists.txt
index 45c050c..a56c98e 100644
--- a/quicklogic/qlf_k4n8/tests/synth_flow/rgb2ycrcb/CMakeLists.txt
+++ b/quicklogic/qlf_k4n8/tests/synth_flow/rgb2ycrcb/CMakeLists.txt
@@ -3,7 +3,7 @@
add_fpga_target(
NAME rgb2ycrcb_test-umc22-no-adder
- TOP rgb2ycrcb
+ TOP top
BOARD qlf_k4n8-qlf_k4n8_umc22_slow_board
SOURCES ${CURR_DIR}/rgb2ycrcb.v
EXPLICIT_ADD_FILE_TARGET
@@ -12,7 +12,7 @@
add_fpga_target(
NAME rgb2ycrcb_test-umc22-adder
- TOP rgb2ycrcb
+ TOP top
BOARD qlf_k4n8-qlf_k4n8_umc22_slow_board
SOURCES ${CURR_DIR}/rgb2ycrcb.v
EXPLICIT_ADD_FILE_TARGET
diff --git a/third_party/qlfpga-symbiflow-plugins b/third_party/qlfpga-symbiflow-plugins
deleted file mode 160000
index a598aa2..0000000
--- a/third_party/qlfpga-symbiflow-plugins
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit a598aa2d3c5157d33d6a7aa2abab609f592ea1a8
diff --git a/xc/common/primitives/slicem/slicem.pb_type.xml b/xc/common/primitives/slicem/slicem.pb_type.xml
index fc3b280..35c114b 100644
--- a/xc/common/primitives/slicem/slicem.pb_type.xml
+++ b/xc/common/primitives/slicem/slicem.pb_type.xml
@@ -400,6 +400,25 @@
</metadata>
</pb_type>
+ <pb_type name="BDI1MUX_ROUTING" num_pb="1">
+ <input name="DI" num_pins="1"/>
+ <input name="STUB" num_pins="1"/>
+ <input name="BI" num_pins="1"/>
+ <output name="DI1" num_pins="1"/>
+ <mode name="default">
+ <interconnect>
+ <mux input="BDI1MUX_ROUTING.DI BDI1MUX_ROUTING.STUB BDI1MUX_ROUTING.BI" name="BDI1MUX" output="BDI1MUX_ROUTING.DI1">
+ <metadata>
+ <meta name="fasm_mux">
+ BDI1MUX_ROUTING.DI = BLUT.DI1MUX.DI_CMC31
+ BDI1MUX_ROUTING.STUB = BLUT.DI1MUX.DI_CMC31
+ BDI1MUX_ROUTING.BI = BLUT.DI1MUX.BI
+ </meta>
+ </metadata>
+ </mux>
+ </interconnect>
+ </mode>
+ </pb_type>
<interconnect>
<!-- The DLUT must be in RAM-mode for any of the RAM's to work.
As a corollary, a DRAM requires the clock, so only turn on the
@@ -510,19 +529,19 @@
</metadata>
<pack_pattern in_port="DI64_STUB[0].DO" name="DRAM_DP" out_port="C_DRAM.DI1" />
</mux>
- <mux name="BDI1MUX" input="SLICEM_MODES.DI DI64_STUB[1].DO SLICEM_MODES.BI" output="B_DRAM.DI1">
+
+ <!-- To enforce that AD1MUX gets the BDI input from the output of the BDI1MUX as specified
+ in the Series7 arcitecture, a "routing" pb type is used to correctly drive the BDI pin
+ -->
+ <direct input="SLICEM_MODES.DI" name="BDI1MUX_ROUTING.DI" output="BDI1MUX_ROUTING.DI"/>
+ <direct input="DI64_STUB[1].DO" name="BDI1MUX_ROUTING.DO" output="BDI1MUX_ROUTING.STUB"/>
+ <direct input="SLICEM_MODES.BI" name="BDI1MUX_ROUTING.BI" output="BDI1MUX_ROUTING.BI"/>
+ <direct input="BDI1MUX_ROUTING.DI1" name="BDI1MUX_ROUTING.DI1" output="B_DRAM.DI1"/>
+
+ <mux name="ADI1MUX" input="BDI1MUX_ROUTING.DI1 DI64_STUB[2].DO SLICEM_MODES.BI SLICEM_MODES.AI" output="A_DRAM.DI1">
<metadata>
<meta name="fasm_mux">
- SLICEM_MODES.DI = BLUT.DI1MUX.DI_CMC31
- DI64_STUB[1].DO = BLUT.DI1MUX.DI_CMC31
- SLICEM_MODES.BI = BLUT.DI1MUX.BI
- </meta>
- </metadata>
- </mux>
- <mux name="ADI1MUX" input="SLICEM_MODES.DI DI64_STUB[2].DO SLICEM_MODES.BI SLICEM_MODES.AI" output="A_DRAM.DI1">
- <metadata>
- <meta name="fasm_mux">
- SLICEM_MODES.DI = ALUT.DI1MUX.BDI1_BMC31,BLUT.DI1MUX.DI_CMC31
+ BDI1MUX_ROUTING.DI1 = ALUT.DI1MUX.BDI1_BMC31,BLUT.DI1MUX.DI_CMC31
DI64_STUB[2].DO = ALUT.DI1MUX.BDI1_BMC31
SLICEM_MODES.BI = ALUT.DI1MUX.BDI1_BMC31,BLUT.DI1MUX.BI
SLICEM_MODES.AI = ALUT.DI1MUX.AI
diff --git a/xc/xc7/techmap/cells_map.v b/xc/xc7/techmap/cells_map.v
index 51554c7..563fc06 100644
--- a/xc/xc7/techmap/cells_map.v
+++ b/xc/xc7/techmap/cells_map.v
@@ -29,6 +29,25 @@
endmodule
+module FD (output reg Q, input C, D);
+
+parameter [0:0] INIT = 1'b0;
+
+wire CE_SIG;
+wire SR_SIG;
+
+CESR_MUX cesr_mux(
+ .CE(1'b1),
+ .SR(1'b0),
+ .CE_OUT(CE_SIG),
+ .SR_OUT(SR_SIG)
+);
+
+FDRE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
+ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .R(SR_SIG));
+
+endmodule
+
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
diff --git a/xc/xc7/tests/install_test/CMakeLists.txt b/xc/xc7/tests/install_test/CMakeLists.txt
index e1ae7b2..117a15d 100644
--- a/xc/xc7/tests/install_test/CMakeLists.txt
+++ b/xc/xc7/tests/install_test/CMakeLists.txt
@@ -2,7 +2,7 @@
get_target_property_required(XC7FRAMES2BIT env XC7FRAMES2BIT)
-function(add_binary_test test_name part_name device board)
+function(add_binary_test test_name part_name device board surelog_cmd)
add_test(NAME ${test_name}
COMMAND ${CMAKE_COMMAND} -E env
PATH=${INSTALLATION_DIR_BIN}:$ENV{PATH}
@@ -10,11 +10,15 @@
PYTHONPATH=${PRJXRAY_DIR}:${PRJXRAY_DIR}/third_party/fasm
DATABASE_DIR=${PRJXRAY_DB_DIR}
FRAMES2BIT=${XC7FRAMES2BIT}
+ SURELOG_CMD=${surelog_cmd}
make PARTNAME=${part_name} DEVICE=${device} BOARD=${board}
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
endfunction()
-add_binary_test(binary_toolchain_test_xc7_50t xc7a35tcpg236-1 xc7a50t_test basys3)
-add_binary_test(binary_toolchain_test_xc7_100t xc7a100tcsg324-1 xc7a100t_test arty-100t)
-add_binary_test(binary_toolchain_test_xc7_200t xc7a200tsbg484-1 xc7a200t_test nexys_video)
+add_binary_test(binary_toolchain_test_xc7_50t xc7a35tcpg236-1 xc7a50t_test basys3 "")
+add_binary_test(binary_toolchain_test_xc7_100t xc7a100tcsg324-1 xc7a100t_test arty-100t "")
+add_binary_test(binary_toolchain_test_xc7_200t xc7a200tsbg484-1 xc7a200t_test nexys_video "")
+add_binary_test(binary_toolchain_test_xc7_50t_surelog xc7a35tcpg236-1 xc7a50t_test basys3 "-parse -DSYNTHESIS")
+add_binary_test(binary_toolchain_test_xc7_100t_surelog xc7a100tcsg324-1 xc7a100t_test arty-100t "-parse -DSYNTHESIS")
+add_binary_test(binary_toolchain_test_xc7_200t_surelog xc7a200tsbg484-1 xc7a200t_test nexys_video "-parse -DSYNTHESIS")
diff --git a/xc/xc7/tests/install_test/Makefile b/xc/xc7/tests/install_test/Makefile
index 564d1b7..82eacd1 100644
--- a/xc/xc7/tests/install_test/Makefile
+++ b/xc/xc7/tests/install_test/Makefile
@@ -10,13 +10,19 @@
BUILDDIR:=build_${BOARD}
ADDITIONAL_VPR_OPTIONS="--seed 1024"
+# Determine if we should use uhdm-plugin to read sources
+ifneq (${SURELOG_CMD},)
+ SURELOG_OPT := -s ${SURELOG_CMD}
+ BUILDDIR = build_${BOARD}_surelog
+endif
+
all: ${BUILDDIR}/${TOP}.bit
${BUILDDIR}:
mkdir ${BUILDDIR}
${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
- cd ${BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC}
+ cd ${BUILDDIR} && symbiflow_synth -t ${TOP} ${SURELOG_OPT} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC}
${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
cd ${BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} -a ${ADDITIONAL_VPR_OPTIONS}
diff --git a/xc/xc7/toolchain_wrappers/symbiflow_synth b/xc/xc7/toolchain_wrappers/symbiflow_synth
index 11996f5..5d2e4b8 100755
--- a/xc/xc7/toolchain_wrappers/symbiflow_synth
+++ b/xc/xc7/toolchain_wrappers/symbiflow_synth
@@ -18,12 +18,14 @@
TOP=top
DEVICE="*"
PART=""
+SURELOG_CMD=()
VERILOGLIST=0
XDCLIST=0
TOPNAME=0
DEVICENAME=0
PARTNAME=0
+SURELOG=0
for arg in $@; do
echo $arg
@@ -35,6 +37,7 @@
TOPNAME=1
DEVICENAME=0
PARTNAME=0
+ SURELOG=0
;;
-x|--xdc)
VERILOGLIST=0
@@ -42,6 +45,7 @@
TOPNAME=0
DEVICENAME=0
PARTNAME=0
+ SURELOG=0
;;
-v|--verilog)
VERILOGLIST=1
@@ -49,6 +53,7 @@
TOPNAME=0
DEVICENAME=0
PARTNAME=0
+ SURELOG=0
;;
-d|--device)
VERILOGLIST=0
@@ -56,6 +61,7 @@
TOPNAME=0
DEVICENAME=1
PARTNAME=0
+ SURELOG=0
;;
-p|--part)
VERILOGLIST=0
@@ -63,6 +69,15 @@
TOPNAME=0
DEVICENAME=0
PARTNAME=1
+ SURELOG=0
+ ;;
+ -s|--surelog)
+ VERILOGLIST=0
+ XDCLIST=0
+ TOPNAME=0
+ DEVICENAME=0
+ PARTNAME=0
+ SURELOG=1
;;
*)
if [ $VERILOGLIST -eq 1 ]; then
@@ -75,9 +90,11 @@
DEVICE=$arg
elif [ $PARTNAME -eq 1 ]; then
PART=$arg
+ elif [ $SURELOG -eq 1 ]; then
+ SURELOG_CMD+=($arg)
else
echo "Usage: synth [-t|--top <top module name> -v|--verilog <Verilog files list> [-x|--xdc <XDC files list>]"
- echo " [-d|--device <device type (e.g. artix7)>] [-p|--part <part name>]"
+ echo " [-d|--device <device type (e.g. artix7)>] [-p|--part <part name>] [-s|--surelog] <parameters to surelog>"
echo "note: device and part parameters are required if xdc is passed"
exit 1
fi
@@ -104,7 +121,10 @@
export OUT_FASM_EXTRA=${TOP}_fasm_extra.fasm
export PYTHON3=${PYTHON3:=$(which python3)}
LOG=${TOP}_synth.log
-
+if [ -z "$SURELOG_CMD" ]; then
yosys -p "tcl ${SYNTH_TCL_PATH}" -l $LOG ${VERILOG_FILES[*]}
+else
+yosys -p "plugin -i uhdm" -p "read_verilog_with_uhdm ${SURELOG_CMD[*]} ${VERILOG_FILES[*]}" -p "tcl ${SYNTH_TCL_PATH}" -l $LOG
+fi
python3 ${SPLIT_INOUTS} -i ${OUT_JSON} -o ${SYNTH_JSON}
yosys -p "read_json $SYNTH_JSON; tcl ${CONV_TCL_PATH}"
diff --git a/xc/xc7/yosys/synth.tcl b/xc/xc7/yosys/synth.tcl
index 00a547b..6944fab 100644
--- a/xc/xc7/yosys/synth.tcl
+++ b/xc/xc7/yosys/synth.tcl
@@ -30,8 +30,11 @@
# Overwrite some models (e.g. IBUF with more parameters)
read_verilog -lib $::env(TECHMAP_PATH)/iobs.v
- # Re-targetting FD to FDREs
- techmap -map $::env(TECHMAP_PATH)/retarget.v
+ # TODO: This should eventually end up in upstream Yosys
+ # as models such as FD are not currently supported
+ # as being used in old FPGAs (e.g. Spartan6)
+ # Read in unsupported models
+ read_verilog -lib $::env(TECHMAP_PATH)/retarget.v
if { [info exists ::env(TOP)] && $::env(TOP) != "" } {
hierarchy -check -top $::env(TOP)
