Tile Level Flip Flop Configuration

• # PosClk -- Flip flop uses positive edge clock (no actual value, so just uses a comment).

• NegClk -- Flip flop uses negative edge clock.

• Use a clock enable signal -- Any signal connected to the CEN input, otherwise CEN == 1.

  • When a CEN input in use, the flip flop type name has E in it's name.

• Use a set/reset signal -- Any signal connected to the S_R input, otherwise S_R == 0.

  • When a S_R input in use, the flip flop type name has either a S or R in the name.

Cell Level Flip Flop Configuration

• enable_dff / DffEnable - Use the flip flip -- Cell Level

Set/Reset Signal

Set or Reset

• Set_NoReset - When S_R == 1, flip flop value is forced to 1'b1
• # Reset - When S_R == 1, flip flop value is forced to 1'b0

Set/Reset Asynchronous

• AsyncSetReset - When set, the S_R is asynchronous to the clock.
• # SyncSetReset - When set, the S_R is synchronous to the clock
  • Synchronous set/reset flip flops have an extra S in the name.

Naming

Lattice Naming

DFF (N) (E) (S1) (R|S2)

• N -- Negative clock
• E -- Clock enable signal used.
• S1 -- Synchronous Set/Reset signal used.
• R -- When Set/Reset signal asserted, value is set to zero.
• S2 -- When Set/Reset signal asserted, value is set to one.

Yosys Internal Naming

$_DFF (E) (SR) _ N|P1 (N|P)2 (N0|N1|P0|P1)3 _

• E - Clock enable signal used.
• SR - Both Set and Reset signals.
• N1 - Negative edge clock.
• P1 - Positive edge clock.
• N2 - Negative level clock enable.
• P2 - Positive level clock enable.
• N03 - Negative level reset signal (on negative level, force contents to zero).
• P03 - Positive level reset signal (on positive level, force contents to zero).
• N13 - Negative level set signal (on negative level, force contents to one).
• P13 - Positive level set signal (on positive level, force contents to one).

Flip Flop Configuration Table