<!-- set: ai sw=1 ts=1 sta et -->
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
 <models>
  <xi:include href="../../tiles/ff-large/ff-large.model.xml" xpointer="xpointer(models/child::node())" />
 </models>

 <!-- Layout of the FPGA, we are using 4x4 -->
 <layout>
   <xi:include href="../layouts/all.xml" xpointer="xpointer(layout/child::node())" />
 </layout>

 <complexblocklist>
  <xi:include href="../../../vpr/ibuf/ibuf.pb_type.xml"/>
  <xi:include href="../../../vpr/obuf/obuf.pb_type.xml"/>
  <xi:include href="../../tiles/ff-large/ff-large.pb_type.xml"/>
 </complexblocklist>

 <xi:include href="../routing/unidir-s4.xml" xpointer="xpointer(architecture/child::node())" />
</architecture>