<!-- set: ai sw=1 ts=1 sta et -->
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
 <models>
  <xi:include href="../../tiles/ff1/ff1.model.xml" xpointer="xpointer(models/child::node())" />
 </models>

 <!-- Layout of the FPGA, we are using 4x4 -->
 <layout>
  <fixed_layout name="2x4" width="8" height="6">

   <col type="EMPTY"   startx="0" priority="10" />
   <col type="VPR_PAD" startx="1" priority="10" />
   <col type="EMPTY"   startx="2" priority="10" />

   <col type="FF1"     startx="3" priority="10" />
   <col type="FF1"     startx="4" priority="10" />

   <col type="EMPTY"   startx="5" priority="10" />
   <col type="VPR_PAD" startx="6" priority="10" />
   <col type="EMPTY"   startx="7" priority="10" />

   <row type="EMPTY"   starty="0" priority="11" />
   <row type="EMPTY"   starty="5" priority="11" />

  </fixed_layout>
 </layout>

 <device>
    <sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000" />
    <area grid_logic_tile_area="14813.392"/>
    <connection_block input_switch_name="1"/>
    <switch_block type="wilton" fs="3"/>
    <chan_width_distr>
      <x distr="uniform" peak="1.000000"/>
      <y distr="uniform" peak="1.000000"/>
    </chan_width_distr>
 </device>

 <complexblocklist>
  <xi:include href="../../../vpr/pad/pad.pb_type.xml"/>
  <xi:include href="../../tiles/ff1/ff1.pb_type.xml"/>
 </complexblocklist>

 <xi:include href="../routing/bidir-s4.xml" xpointer="xpointer(architecture/child::node())" />

</architecture>