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foss-fpga-tools / symbiflow-arch-defs / refs/heads/bot-conda-lock-update / . / xilinx / xc7 / tests / ddr / scripts
tree: d8b983bd45ba8f4ed9518d01f77611fdf19fa65a [path history] [tgz]
  1. arty.py
  2. csr.csv
  3. README.md
  4. sdram_init.py
  5. test_sdram.py
xilinx/xc7/tests/ddr/scripts/README.md

UART-DDR test

The test_sdram.py script performs a calibration step with the DDR and calculates what are the correct bitslip and delay values to be assigned.

Prerequisites

To be able to perform the test, make sure to clone the litex repository, as it contains the RemoteClient library to be able to correctly run the test. If you do not have the litex dependency on your machine, do the following:

git clone https://github.com/enjoy-digital/litex.git

To test the design, do the following:

  1. Open a new terminal and open a litex server (Note that X in the ttyUSBX needs to be replaced with the enabled device on your local machine):
lxserver --uart --uart-port=/dev/ttyUSBX
  1. On the previous terminal start the client script:
./test_sdram.py