build(deps): bump third_party/litex from `95b310e` to `67e8d77`

Bumps [third_party/litex](https://github.com/enjoy-digital/litex) from `95b310e` to `67e8d77`.
- [Release notes](https://github.com/enjoy-digital/litex/releases)
- [Commits](https://github.com/enjoy-digital/litex/compare/95b310ee0f0d9e78e00eb32b71324b25265da4f4...67e8d774211f5c8bc682168abd27f8c9b7bb7ca2)

---
updated-dependencies:
- dependency-name: third_party/litex
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
1 file changed
tree: 9524a40c0b0b3c1608016d302b0679769a864d73
  1. .github/
  2. common/
  3. docs/
  4. lattice/
  5. library/
  6. packaging/
  7. quicklogic/
  8. testarch/
  9. tests/
  10. third_party/
  11. utils/
  12. vpr/
  13. xilinx/
  14. .excludes
  15. .git-blame-ignore-revs
  16. .gitattributes
  17. .gitignore
  18. .gitmodules
  19. .readthedocs.yml
  20. .style.yapf
  21. CMakeLists.txt
  22. conda_lock.yml
  23. COPYING
  24. environment.yml
  25. Makefile
  26. pylintrc
  27. README.md
  28. requirements.txt
  29. tox.ini
README.md

F4PGA Architecture Definitions

This repository is focused on the development of architecture support in F4PGA. Start with the Examples (for Users) if you are looking to use the tools.

This repo contains documentation of various FPGA architectures, it is currently concentrating on:

It includes:

  • Black box part definitions
  • Verilog To Routing architecture definitions
  • Documentation for humans
  • Verilog simulations

The aim is to gather useful documentation (both human and machine readable) about the primitives and routing infrastructure for these architectures. We hope this enables growth in the open source FPGA tools space.