third_party/netlistsvg Tool for generating nice logic diagrams from Verilog code.
third_party/icestorm Bitstream and timing database + tools for the Lattice iCE40.
third_party/prjxray Tools for the Xilinx Series 7 parts.
third_party/prjxray-db Bitstream and timing database for the Xilinx Series 7 parts.
yosys Verilog parsing and synthesis.
vtr Place and route tool.
iverilog Very correct FOSS Verilog Simulator
verilator Fast FOSS Verilog Simulator
sphinx Tool for generating nice looking documentation.
breathe Tool for allowing Doxygen and Sphinx integration.
doxygen-verilog Allows using Doxygen style comments inside Verilog files.
symbolator Tool for generating symbol diagrams from Verilog (and VHDL) code.
wavedrom Tool for generating waveform / timing diagrams.
The Continuous Integration system builds and uploads the various architecture data files. A set of latest architecture build artifact links is generated and uploaded to a dedicated GCS bucket.
To run examples provided, please make sure these resources are available: