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<ul class="simple">
<li><p><a class="reference external" href="https://f4pga.readthedocs.io/projects/prjxray/en/latest/index.html" title="(in Project X-Ray v0.0-3807-g72e6371b)"><span class="xref std std-doc">Project X-Ray ➚</span></a> for Xilinx 7-Series</p></li>
<li><p><a class="reference external" href="http://bygone.clairexen.net/icestorm/">Project IceStorm ➚</a> for Lattice iCE40</p></li>
-<li><p><span class="xref std std-doc">Project Trellis ➚</span> for Lattice ECP5 FPGAs</p></li>
+<li><p><a class="reference external" href="https://prjtrellis.readthedocs.io/en/latest/index.html" title="(in Project Trellis)"><span class="xref std std-doc">Project Trellis ➚</span></a> for Lattice ECP5 FPGAs</p></li>
</ul>
<p>More information can be found at <a class="reference external" href="https://f4pga.readthedocs.io/projects/arch-defs/en/latest/index.html" title="(in F4PGA Architecture Definitions vlatest)"><span class="xref std std-doc">F4PGA Architecture Definitions ➚</span></a> and <a class="reference external" href="https://fpga-interchange-schema.readthedocs.io/index.html" title="(in FPGA Interchange Format v0.0-99-gc985b46)"><span class="xref std std-doc">FPGA Interchange ➚</span></a>.</p>
<p>To prepare a working bitstream for a particular FPGA chip, the toolchain goes through the following stages:</p>
