)]}'
{
  "id": "580e1b7700ed597303d17478638b8e844b89d4d2",
  "repo": "symbiflow-docs",
  "revision": "aefaa81f23c22eea7a7038c42c4cf1a0191f0395",
  "path": "f4pga/utils/quicklogic/pp3/verilogmodule.py"
}
