)]}'
{
  "id": "b6d91f47a9e3fb86fc7bec3715d173a08fd2031b",
  "entries": [
    {
      "mode": 16384,
      "type": "tree",
      "id": "6580b80f677e31133860dbf4abd3eb206cbf8578",
      "name": "constraints"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "6e9e9ddd2632b2bd58ece28eebb0a662faaf7cf2",
      "name": "requirements.txt"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "d0d2ec74b3f9d9af12a69ec2eba386360474df28",
      "name": "test_wrappers.py"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "a528830f1042e0e7d6483990b306fd6f9c7923de",
      "name": "verilog"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "afb786b7f8c07e77dae39f3701abb38cf8ec1d4d",
      "name": "vhdl"
    }
  ]
}