)]}'
{
  "icestorm": {
    "name": "third_party/icestorm",
    "clone_url": "https://foss-fpga-tools.googlesource.com/third_party/icestorm"
  },
  "nextpnr": {
    "name": "third_party/nextpnr",
    "clone_url": "https://foss-fpga-tools.googlesource.com/third_party/nextpnr"
  },
  "Surelog": {
    "name": "third_party/Surelog",
    "clone_url": "https://foss-fpga-tools.googlesource.com/third_party/Surelog"
  },
  "verible": {
    "name": "third_party/verible",
    "clone_url": "https://foss-fpga-tools.googlesource.com/third_party/verible",
    "description": "Verible provides a SystemVerilog parser, style-linter, and formatter.",
    "mirrored_from_url": "https://github.com/google/verible.git"
  },
  "vtr-verilog-to-routing": {
    "name": "third_party/vtr-verilog-to-routing",
    "clone_url": "https://foss-fpga-tools.googlesource.com/third_party/vtr-verilog-to-routing"
  },
  "yosys": {
    "name": "third_party/yosys",
    "clone_url": "https://foss-fpga-tools.googlesource.com/third_party/yosys"
  }
}