diff --git a/grammar/SV3_1aPpParser.g4 b/grammar/SV3_1aPpParser.g4
index 03ca770..a44ab53 100644
--- a/grammar/SV3_1aPpParser.g4
+++ b/grammar/SV3_1aPpParser.g4
@@ -31,12 +31,12 @@
             | endcelldefine_directive_one_line
             | default_nettype_directive_one_line
             | undef_directive
-            | ifdef_directive_one_line 
-            | ifndef_directive_one_line
-            | else_directive_one_line 
-            | elsif_directive_one_line
-	    | elseif_directive_one_line
-            | endif_directive_one_line 
+            | ifdef_directive
+            | ifndef_directive
+            | else_directive 
+            | elsif_directive
+	    | elseif_directive
+            | endif_directive
             | include_directive_one_line
             | include_directive
             | resetall_directive_one_line
@@ -139,36 +139,19 @@
 
 undef_directive : TICK_UNDEF Spaces (Simple_identifier | Escaped_identifier | macro_instance);
 
-ifdef_directive_one_line : ifdef_directive Spaces* (
-                              (One_line_comment | CR )
-                            | (description* ((else_directive | elseif_directive | elsif_directive )? description+)* endif_directive)
-                           );
-
 ifdef_directive : TICK_IFDEF Spaces (Simple_identifier | Escaped_identifier | macro_instance) ;
 ifdef_directive_in_macro_body : TICK_IFDEF Spaces (identifier_in_macro_body | Escaped_identifier | macro_instance) ;
 
-ifndef_directive_one_line : ifndef_directive Spaces* (
-                              (One_line_comment | CR )
-                            | (description* ((else_directive | elseif_directive | elsif_directive )? description+)* endif_directive)
-                           );
-
 ifndef_directive : TICK_IFNDEF Spaces (Simple_identifier | Escaped_identifier | macro_instance);
 ifndef_directive_in_macro_body : TICK_IFNDEF Spaces (identifier_in_macro_body | Escaped_identifier | macro_instance);
 
-elsif_directive_one_line : elsif_directive Spaces* (One_line_comment | CR ) ;
 elsif_directive : TICK_ELSIF Spaces (Simple_identifier | Escaped_identifier | macro_instance);
 elsif_directive_in_macro_body : TICK_ELSIF Spaces (identifier_in_macro_body | Escaped_identifier | macro_instance);
 
-elseif_directive_one_line : elseif_directive Spaces* (One_line_comment | CR ) ;
 elseif_directive : TICK_ELSEIF Spaces (Simple_identifier | Escaped_identifier | macro_instance);
 elseif_directive_in_macro_body : TICK_ELSEIF Spaces (identifier_in_macro_body | Escaped_identifier | macro_instance);
 
-else_directive_one_line : else_directive Spaces* (One_line_comment | CR );
 else_directive : TICK_ELSE;
-
-endif_directive_one_line : TICK_ENDIF Spaces* One_line_comment 
-	 	         | TICK_ENDIF Spaces* CR
-	    	         | TICK_ENDIF EOF;
 			 
 endif_directive : TICK_ENDIF Spaces* One_line_comment
 		| TICK_ENDIF ;
diff --git a/src/SourceCompile/Compiler.cpp b/src/SourceCompile/Compiler.cpp
index 9a5d4de..0fb79f5 100644
--- a/src/SourceCompile/Compiler.cpp
+++ b/src/SourceCompile/Compiler.cpp
@@ -589,6 +589,10 @@
     std::string msg = "Preprocessing took " +
                       StringUtils::to_string(tmr.elapsed_rounded()) + "s\n";
     std::cout << msg << std::endl;
+    for (unsigned int i = 0; i < m_compilers.size(); i++) {
+      msg += m_compilers[i]->getPreprocessor()->getProfileInfo();
+    }
+    std::cout << msg << std::endl;
     profile += msg;
     tmr.reset();
   }
diff --git a/src/SourceCompile/PreprocessFile.cpp b/src/SourceCompile/PreprocessFile.cpp
index 70eba8d..2b1ab9d 100644
--- a/src/SourceCompile/PreprocessFile.cpp
+++ b/src/SourceCompile/PreprocessFile.cpp
@@ -47,12 +47,13 @@
 #include "antlr4-runtime.h"
 #include "atn/ParserATNSimulator.h"
 #include "Parser.h"
+#include "SourceCompile/SV3_1aPpTreeShapeListener.h"
+#include "Utils/Timer.h"
+
 std::string PreprocessFile::MacroNotDefined = "SURELOG_MACRO_NOT_DEFINED";
 std::string PreprocessFile::PP__Line__Marking = "SURELOG__LINE__MARKING";
 std::string PreprocessFile::PP__File__Marking = "SURELOG__FILE__MARKING";
 
-#include "SourceCompile/SV3_1aPpTreeShapeListener.h"
-
 void PreprocessFile::setDebug(int level) {
   switch (level) {
     case 0:
@@ -278,6 +279,7 @@
 }
 
 bool PreprocessFile::preprocess() {
+  Timer tmr;
   PPCache cache(this);
   if (cache.restore()) {
     m_usingCachedVersion = true;
@@ -354,6 +356,12 @@
         new CommonTokenStream(m_antlrParserHandler->m_pplexer);
     m_antlrParserHandler->m_pptokens->fill();
 
+    if (getCompileSourceFile()->getCommandLineParser()->profile()) {
+      // m_profileInfo += "Tokenizer: " + std::to_string (tmr.elapsed_rounded ())
+      // + " " + fileName + "\n";
+      tmr.reset();
+    }
+    
     if (m_debugPPTokens) {
       std::cout << "PP TOKENS: " << std::endl;
       for (auto token : m_antlrParserHandler->m_pptokens->getTokens()) {
@@ -371,6 +379,14 @@
     try {
       m_antlrParserHandler->m_pptree =
           m_antlrParserHandler->m_ppparser->source_text();
+
+      if (getCompileSourceFile()->getCommandLineParser()->profile()) {
+        m_profileInfo +=
+                "PP SSL Parsing: " + StringUtils::to_string(tmr.elapsed_rounded()) +
+                " " + fileName + "\n";
+        tmr.reset();
+      }
+      
     } catch (ParseCancellationException& pex) {
       m_antlrParserHandler->m_pptokens->reset();
       m_antlrParserHandler->m_ppparser->reset();
@@ -383,6 +399,13 @@
           ->setPredictionMode(atn::PredictionMode::LL);
       m_antlrParserHandler->m_pptree =
           m_antlrParserHandler->m_ppparser->source_text();
+
+      if (getCompileSourceFile()->getCommandLineParser()->profile()) {
+        m_profileInfo +=
+                "PP LL  Parsing: " + StringUtils::to_string(tmr.elapsed_rounded()) +
+                " " + fileName + "\n";
+        tmr.reset();
+      }
     }
 
     if (m_debugPPTree)
diff --git a/src/SourceCompile/PreprocessFile.h b/src/SourceCompile/PreprocessFile.h
index 113f19d..6e4a9ce 100644
--- a/src/SourceCompile/PreprocessFile.h
+++ b/src/SourceCompile/PreprocessFile.h
@@ -279,7 +279,7 @@
   void saveCache();
   void collectIncludedFiles(std::set<PreprocessFile*>& included);
   bool usingCachedVersion() { return m_usingCachedVersion; }
-
+  std::string getProfileInfo() { return m_profileInfo; }
  private:
   std::pair<bool, std::string> evaluateMacro_(
       const std::string name, std::vector<std::string>& arguments,
@@ -305,6 +305,7 @@
   std::vector<IncludeFileInfo> m_includeFileInfo;
   unsigned int m_embeddedMacroCallLine;
   SymbolId m_embeddedMacroCallFile;
+  std::string m_profileInfo;
 };
 
 };  // namespace SURELOG
diff --git a/src/SourceCompile/SV3_1aPpTreeShapeListener.h b/src/SourceCompile/SV3_1aPpTreeShapeListener.h
index 6669bc6..a30a9dc 100644
--- a/src/SourceCompile/SV3_1aPpTreeShapeListener.h
+++ b/src/SourceCompile/SV3_1aPpTreeShapeListener.h
@@ -277,33 +277,7 @@
             setCurrentBranchActivity();
         }
         //void exitEndif_directive(SV3_1aPpParser::Endif_directiveContext * /*ctx*/)  { }
-
-        void enterEndif_directive_one_line(SV3_1aPpParser::Endif_directive_one_lineContext * ctx) {
-            PreprocessFile::IfElseStack& stack = m_pp->getStack();
-            if (stack.size()) {
-                bool unroll = true;
-                while (unroll) {
-                    PreprocessFile::IfElseItem& item = stack.back();
-                    switch (item.m_type) {
-                        case PreprocessFile::IfElseItem::IFDEF:
-                        case PreprocessFile::IfElseItem::IFNDEF:
-                            //std::cout << "STACK SIZE: " << m_pp->getStack ().size () << std::endl;
-                            m_inActiveBranch = item.m_previousActiveState; 
-                            stack.pop_back();
-                            unroll = false;
-                            break;
-                        case PreprocessFile::IfElseItem::ELSIF:
-                        case PreprocessFile::IfElseItem::ELSE:
-                            stack.pop_back();
-                            break;
-                        default:
-                            break;
-                    }
-                }
-            }
-            setCurrentBranchActivity();
-        }
-        
+      
         void enterResetall_directive(SV3_1aPpParser::Resetall_directiveContext *ctx) {
             if (m_pp->getCompilationUnit()->isInDesignElement())
             {
@@ -744,10 +718,6 @@
         }
         //void exitEndconfig(SV3_1aPpParser::EndconfigContext * /*ctx*/);
 
-        //void enterElseif_directive_one_line(SV3_1aPpParser::Elseif_directive_one_lineContext * /*ctx*/) {
-        // }
-        //void exitElseif_directive_one_line(SV3_1aPpParser::Elseif_directive_one_lineContext * /*ctx*/) {}
-
         void enterElseif_directive(SV3_1aPpParser::Elseif_directiveContext *ctx) {
            logError(ErrorDefinition::PP_ILLEGAL_DIRECTIVE_ELSEIF, ctx, "");
         }
diff --git a/src/parser/SV3_1aPpParser.cpp b/src/parser/SV3_1aPpParser.cpp
index e7947b1..b3fae3a 100644
--- a/src/parser/SV3_1aPpParser.cpp
+++ b/src/parser/SV3_1aPpParser.cpp
@@ -72,7 +72,7 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(287);
+    setState(275);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while ((((_la & ~ 0x3fULL) == 0) &&
@@ -169,9 +169,9 @@
       | (1ULL << (SV3_1aPpParser::SQUARE_CLOSE - 64))
       | (1ULL << (SV3_1aPpParser::Special - 64))
       | (1ULL << (SV3_1aPpParser::ANY - 64)))) != 0)) {
-      setState(284);
+      setState(272);
       description();
-      setState(289);
+      setState(277);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
@@ -228,28 +228,28 @@
   return getRuleContext<SV3_1aPpParser::Undef_directiveContext>(0);
 }
 
-SV3_1aPpParser::Ifdef_directive_one_lineContext* SV3_1aPpParser::DescriptionContext::ifdef_directive_one_line() {
-  return getRuleContext<SV3_1aPpParser::Ifdef_directive_one_lineContext>(0);
+SV3_1aPpParser::Ifdef_directiveContext* SV3_1aPpParser::DescriptionContext::ifdef_directive() {
+  return getRuleContext<SV3_1aPpParser::Ifdef_directiveContext>(0);
 }
 
-SV3_1aPpParser::Ifndef_directive_one_lineContext* SV3_1aPpParser::DescriptionContext::ifndef_directive_one_line() {
-  return getRuleContext<SV3_1aPpParser::Ifndef_directive_one_lineContext>(0);
+SV3_1aPpParser::Ifndef_directiveContext* SV3_1aPpParser::DescriptionContext::ifndef_directive() {
+  return getRuleContext<SV3_1aPpParser::Ifndef_directiveContext>(0);
 }
 
-SV3_1aPpParser::Else_directive_one_lineContext* SV3_1aPpParser::DescriptionContext::else_directive_one_line() {
-  return getRuleContext<SV3_1aPpParser::Else_directive_one_lineContext>(0);
+SV3_1aPpParser::Else_directiveContext* SV3_1aPpParser::DescriptionContext::else_directive() {
+  return getRuleContext<SV3_1aPpParser::Else_directiveContext>(0);
 }
 
-SV3_1aPpParser::Elsif_directive_one_lineContext* SV3_1aPpParser::DescriptionContext::elsif_directive_one_line() {
-  return getRuleContext<SV3_1aPpParser::Elsif_directive_one_lineContext>(0);
+SV3_1aPpParser::Elsif_directiveContext* SV3_1aPpParser::DescriptionContext::elsif_directive() {
+  return getRuleContext<SV3_1aPpParser::Elsif_directiveContext>(0);
 }
 
-SV3_1aPpParser::Elseif_directive_one_lineContext* SV3_1aPpParser::DescriptionContext::elseif_directive_one_line() {
-  return getRuleContext<SV3_1aPpParser::Elseif_directive_one_lineContext>(0);
+SV3_1aPpParser::Elseif_directiveContext* SV3_1aPpParser::DescriptionContext::elseif_directive() {
+  return getRuleContext<SV3_1aPpParser::Elseif_directiveContext>(0);
 }
 
-SV3_1aPpParser::Endif_directive_one_lineContext* SV3_1aPpParser::DescriptionContext::endif_directive_one_line() {
-  return getRuleContext<SV3_1aPpParser::Endif_directive_one_lineContext>(0);
+SV3_1aPpParser::Endif_directiveContext* SV3_1aPpParser::DescriptionContext::endif_directive() {
+  return getRuleContext<SV3_1aPpParser::Endif_directiveContext>(0);
 }
 
 SV3_1aPpParser::Include_directive_one_lineContext* SV3_1aPpParser::DescriptionContext::include_directive_one_line() {
@@ -509,516 +509,516 @@
     exitRule();
   });
   try {
-    setState(363);
+    setState(351);
     _errHandler->sync(this);
     switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 1, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(290);
+      setState(278);
       unterminated_string();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(291);
+      setState(279);
       string();
       break;
     }
 
     case 3: {
       enterOuterAlt(_localctx, 3);
-      setState(292);
+      setState(280);
       number();
       break;
     }
 
     case 4: {
       enterOuterAlt(_localctx, 4);
-      setState(293);
+      setState(281);
       macro_definition();
       break;
     }
 
     case 5: {
       enterOuterAlt(_localctx, 5);
-      setState(294);
+      setState(282);
       comments();
       break;
     }
 
     case 6: {
       enterOuterAlt(_localctx, 6);
-      setState(295);
+      setState(283);
       celldefine_directive_one_line();
       break;
     }
 
     case 7: {
       enterOuterAlt(_localctx, 7);
-      setState(296);
+      setState(284);
       endcelldefine_directive_one_line();
       break;
     }
 
     case 8: {
       enterOuterAlt(_localctx, 8);
-      setState(297);
+      setState(285);
       default_nettype_directive_one_line();
       break;
     }
 
     case 9: {
       enterOuterAlt(_localctx, 9);
-      setState(298);
+      setState(286);
       undef_directive();
       break;
     }
 
     case 10: {
       enterOuterAlt(_localctx, 10);
-      setState(299);
-      ifdef_directive_one_line();
+      setState(287);
+      ifdef_directive();
       break;
     }
 
     case 11: {
       enterOuterAlt(_localctx, 11);
-      setState(300);
-      ifndef_directive_one_line();
+      setState(288);
+      ifndef_directive();
       break;
     }
 
     case 12: {
       enterOuterAlt(_localctx, 12);
-      setState(301);
-      else_directive_one_line();
+      setState(289);
+      else_directive();
       break;
     }
 
     case 13: {
       enterOuterAlt(_localctx, 13);
-      setState(302);
-      elsif_directive_one_line();
+      setState(290);
+      elsif_directive();
       break;
     }
 
     case 14: {
       enterOuterAlt(_localctx, 14);
-      setState(303);
-      elseif_directive_one_line();
+      setState(291);
+      elseif_directive();
       break;
     }
 
     case 15: {
       enterOuterAlt(_localctx, 15);
-      setState(304);
-      endif_directive_one_line();
+      setState(292);
+      endif_directive();
       break;
     }
 
     case 16: {
       enterOuterAlt(_localctx, 16);
-      setState(305);
+      setState(293);
       include_directive_one_line();
       break;
     }
 
     case 17: {
       enterOuterAlt(_localctx, 17);
-      setState(306);
+      setState(294);
       include_directive();
       break;
     }
 
     case 18: {
       enterOuterAlt(_localctx, 18);
-      setState(307);
+      setState(295);
       resetall_directive_one_line();
       break;
     }
 
     case 19: {
       enterOuterAlt(_localctx, 19);
-      setState(308);
+      setState(296);
       begin_keywords_directive_one_line();
       break;
     }
 
     case 20: {
       enterOuterAlt(_localctx, 20);
-      setState(309);
+      setState(297);
       begin_keywords_directive();
       break;
     }
 
     case 21: {
       enterOuterAlt(_localctx, 21);
-      setState(310);
+      setState(298);
       end_keywords_directive_one_line();
       break;
     }
 
     case 22: {
       enterOuterAlt(_localctx, 22);
-      setState(311);
+      setState(299);
       timescale_directive_one_line();
       break;
     }
 
     case 23: {
       enterOuterAlt(_localctx, 23);
-      setState(312);
+      setState(300);
       unconnected_drive_directive_one_line();
       break;
     }
 
     case 24: {
       enterOuterAlt(_localctx, 24);
-      setState(313);
+      setState(301);
       nounconnected_drive_directive_one_line();
       break;
     }
 
     case 25: {
       enterOuterAlt(_localctx, 25);
-      setState(314);
+      setState(302);
       line_directive_one_line();
       break;
     }
 
     case 26: {
       enterOuterAlt(_localctx, 26);
-      setState(315);
+      setState(303);
       default_decay_time_directive_one_line();
       break;
     }
 
     case 27: {
       enterOuterAlt(_localctx, 27);
-      setState(316);
+      setState(304);
       default_trireg_strenght_directive_one_line();
       break;
     }
 
     case 28: {
       enterOuterAlt(_localctx, 28);
-      setState(317);
+      setState(305);
       delay_mode_distributed_directive_one_line();
       break;
     }
 
     case 29: {
       enterOuterAlt(_localctx, 29);
-      setState(318);
+      setState(306);
       delay_mode_path_directive_one_line();
       break;
     }
 
     case 30: {
       enterOuterAlt(_localctx, 30);
-      setState(319);
+      setState(307);
       delay_mode_unit_directive_one_line();
       break;
     }
 
     case 31: {
       enterOuterAlt(_localctx, 31);
-      setState(320);
+      setState(308);
       delay_mode_zero_directive_one_line();
       break;
     }
 
     case 32: {
       enterOuterAlt(_localctx, 32);
-      setState(321);
+      setState(309);
       protect_directive_one_line();
       break;
     }
 
     case 33: {
       enterOuterAlt(_localctx, 33);
-      setState(322);
+      setState(310);
       endprotect_directive_one_line();
       break;
     }
 
     case 34: {
       enterOuterAlt(_localctx, 34);
-      setState(323);
+      setState(311);
       protected_directive_one_line();
       break;
     }
 
     case 35: {
       enterOuterAlt(_localctx, 35);
-      setState(324);
+      setState(312);
       endprotected_directive_one_line();
       break;
     }
 
     case 36: {
       enterOuterAlt(_localctx, 36);
-      setState(325);
+      setState(313);
       expand_vectornets_directive_one_line();
       break;
     }
 
     case 37: {
       enterOuterAlt(_localctx, 37);
-      setState(326);
+      setState(314);
       noexpand_vectornets_directive_one_line();
       break;
     }
 
     case 38: {
       enterOuterAlt(_localctx, 38);
-      setState(327);
+      setState(315);
       autoexpand_vectornets_directive_one_line();
       break;
     }
 
     case 39: {
       enterOuterAlt(_localctx, 39);
-      setState(328);
+      setState(316);
       remove_gatename_directive_one_line();
       break;
     }
 
     case 40: {
       enterOuterAlt(_localctx, 40);
-      setState(329);
+      setState(317);
       noremove_gatenames_directive_one_line();
       break;
     }
 
     case 41: {
       enterOuterAlt(_localctx, 41);
-      setState(330);
+      setState(318);
       remove_netname_directive_one_line();
       break;
     }
 
     case 42: {
       enterOuterAlt(_localctx, 42);
-      setState(331);
+      setState(319);
       noremove_netnames_directive_one_line();
       break;
     }
 
     case 43: {
       enterOuterAlt(_localctx, 43);
-      setState(332);
+      setState(320);
       accelerate_directive_one_line();
       break;
     }
 
     case 44: {
       enterOuterAlt(_localctx, 44);
-      setState(333);
+      setState(321);
       noaccelerate_directive_one_line();
       break;
     }
 
     case 45: {
       enterOuterAlt(_localctx, 45);
-      setState(334);
+      setState(322);
       undefineall_directive();
       break;
     }
 
     case 46: {
       enterOuterAlt(_localctx, 46);
-      setState(335);
+      setState(323);
       uselib_directive_one_line();
       break;
     }
 
     case 47: {
       enterOuterAlt(_localctx, 47);
-      setState(336);
+      setState(324);
       disable_portfaults_directive_one_line();
       break;
     }
 
     case 48: {
       enterOuterAlt(_localctx, 48);
-      setState(337);
+      setState(325);
       enable_portfaults_directive_one_line();
       break;
     }
 
     case 49: {
       enterOuterAlt(_localctx, 49);
-      setState(338);
+      setState(326);
       nosuppress_faults_directive_one_line();
       break;
     }
 
     case 50: {
       enterOuterAlt(_localctx, 50);
-      setState(339);
+      setState(327);
       suppress_faults_directive_one_line();
       break;
     }
 
     case 51: {
       enterOuterAlt(_localctx, 51);
-      setState(340);
+      setState(328);
       signed_directive_one_line();
       break;
     }
 
     case 52: {
       enterOuterAlt(_localctx, 52);
-      setState(341);
+      setState(329);
       unsigned_directive_one_line();
       break;
     }
 
     case 53: {
       enterOuterAlt(_localctx, 53);
-      setState(342);
+      setState(330);
       pragma_directive_one_line();
       break;
     }
 
     case 54: {
       enterOuterAlt(_localctx, 54);
-      setState(343);
+      setState(331);
       sv_file_directive();
       break;
     }
 
     case 55: {
       enterOuterAlt(_localctx, 55);
-      setState(344);
+      setState(332);
       sv_line_directive();
       break;
     }
 
     case 56: {
       enterOuterAlt(_localctx, 56);
-      setState(345);
+      setState(333);
       macro_instance();
       break;
     }
 
     case 57: {
       enterOuterAlt(_localctx, 57);
-      setState(346);
+      setState(334);
       module();
       break;
     }
 
     case 58: {
       enterOuterAlt(_localctx, 58);
-      setState(347);
+      setState(335);
       endmodule();
       break;
     }
 
     case 59: {
       enterOuterAlt(_localctx, 59);
-      setState(348);
+      setState(336);
       sv_interface();
       break;
     }
 
     case 60: {
       enterOuterAlt(_localctx, 60);
-      setState(349);
+      setState(337);
       endinterface();
       break;
     }
 
     case 61: {
       enterOuterAlt(_localctx, 61);
-      setState(350);
+      setState(338);
       program();
       break;
     }
 
     case 62: {
       enterOuterAlt(_localctx, 62);
-      setState(351);
+      setState(339);
       endprogram();
       break;
     }
 
     case 63: {
       enterOuterAlt(_localctx, 63);
-      setState(352);
+      setState(340);
       primitive();
       break;
     }
 
     case 64: {
       enterOuterAlt(_localctx, 64);
-      setState(353);
+      setState(341);
       endprimitive();
       break;
     }
 
     case 65: {
       enterOuterAlt(_localctx, 65);
-      setState(354);
+      setState(342);
       sv_package();
       break;
     }
 
     case 66: {
       enterOuterAlt(_localctx, 66);
-      setState(355);
+      setState(343);
       endpackage();
       break;
     }
 
     case 67: {
       enterOuterAlt(_localctx, 67);
-      setState(356);
+      setState(344);
       checker();
       break;
     }
 
     case 68: {
       enterOuterAlt(_localctx, 68);
-      setState(357);
+      setState(345);
       endchecker();
       break;
     }
 
     case 69: {
       enterOuterAlt(_localctx, 69);
-      setState(358);
+      setState(346);
       config();
       break;
     }
 
     case 70: {
       enterOuterAlt(_localctx, 70);
-      setState(359);
+      setState(347);
       endconfig();
       break;
     }
 
     case 71: {
       enterOuterAlt(_localctx, 71);
-      setState(360);
+      setState(348);
       text_blob();
       break;
     }
 
     case 72: {
       enterOuterAlt(_localctx, 72);
-      setState(361);
+      setState(349);
       escaped_identifier();
       break;
     }
 
     case 73: {
       enterOuterAlt(_localctx, 73);
-      setState(362);
+      setState(350);
       pound_delay();
       break;
     }
@@ -1123,13 +1123,13 @@
     exitRule();
   });
   try {
-    setState(377);
+    setState(365);
     _errHandler->sync(this);
     switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 3, _ctx)) {
     case 1: {
       _localctx = dynamic_cast<Macro_instanceContext *>(_tracker.createInstance<SV3_1aPpParser::MacroInstanceWithArgsContext>(_localctx));
       enterOuterAlt(_localctx, 1);
-      setState(365);
+      setState(353);
       _la = _input->LA(1);
       if (!(_la == SV3_1aPpParser::Macro_identifier
 
@@ -1140,21 +1140,21 @@
         _errHandler->reportMatch(this);
         consume();
       }
-      setState(369);
+      setState(357);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while (_la == SV3_1aPpParser::Spaces) {
-        setState(366);
+        setState(354);
         match(SV3_1aPpParser::Spaces);
-        setState(371);
+        setState(359);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(372);
+      setState(360);
       match(SV3_1aPpParser::PARENS_OPEN);
-      setState(373);
+      setState(361);
       macro_actual_args();
-      setState(374);
+      setState(362);
       match(SV3_1aPpParser::PARENS_CLOSE);
       break;
     }
@@ -1162,7 +1162,7 @@
     case 2: {
       _localctx = dynamic_cast<Macro_instanceContext *>(_tracker.createInstance<SV3_1aPpParser::MacroInstanceNoArgsContext>(_localctx));
       enterOuterAlt(_localctx, 2);
-      setState(376);
+      setState(364);
       _la = _input->LA(1);
       if (!(_la == SV3_1aPpParser::Macro_identifier
 
@@ -1237,9 +1237,9 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(379);
+    setState(367);
     match(SV3_1aPpParser::DOUBLE_QUOTE);
-    setState(383);
+    setState(371);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (((((_la - 70) & ~ 0x3fULL) == 0) &&
@@ -1263,13 +1263,13 @@
       | (1ULL << (SV3_1aPpParser::SQUARE_CLOSE - 70))
       | (1ULL << (SV3_1aPpParser::Special - 70))
       | (1ULL << (SV3_1aPpParser::ANY - 70)))) != 0)) {
-      setState(380);
+      setState(368);
       string_blob();
-      setState(385);
+      setState(373);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(386);
+    setState(374);
     match(SV3_1aPpParser::CR);
    
   }
@@ -1331,7 +1331,7 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(391);
+    setState(379);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while ((((_la & ~ 0x3fULL) == 0) &&
@@ -1355,19 +1355,19 @@
       | (1ULL << (SV3_1aPpParser::SQUARE_OPEN - 67))
       | (1ULL << (SV3_1aPpParser::Special - 67))
       | (1ULL << (SV3_1aPpParser::ANY - 67)))) != 0)) {
-      setState(388);
+      setState(376);
       macro_arg();
-      setState(393);
+      setState(381);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(403);
+    setState(391);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::COMMA) {
-      setState(394);
+      setState(382);
       match(SV3_1aPpParser::COMMA);
-      setState(398);
+      setState(386);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while ((((_la & ~ 0x3fULL) == 0) &&
@@ -1391,13 +1391,13 @@
         | (1ULL << (SV3_1aPpParser::SQUARE_OPEN - 67))
         | (1ULL << (SV3_1aPpParser::Special - 67))
         | (1ULL << (SV3_1aPpParser::ANY - 67)))) != 0)) {
-        setState(395);
+        setState(383);
         macro_arg();
-        setState(400);
+        setState(388);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(405);
+      setState(393);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
@@ -1453,7 +1453,7 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(406);
+    setState(394);
     _la = _input->LA(1);
     if (!(_la == SV3_1aPpParser::One_line_comment
 
@@ -1511,7 +1511,7 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(408);
+    setState(396);
     match(SV3_1aPpParser::Number);
    
   }
@@ -1560,7 +1560,7 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(410);
+    setState(398);
     match(SV3_1aPpParser::Pound_delay);
    
   }
@@ -1624,40 +1624,40 @@
     exitRule();
   });
   try {
-    setState(417);
+    setState(405);
     _errHandler->sync(this);
     switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 8, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(412);
+      setState(400);
       define_directive();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(413);
+      setState(401);
       multiline_args_macro_definition();
       break;
     }
 
     case 3: {
       enterOuterAlt(_localctx, 3);
-      setState(414);
+      setState(402);
       simple_no_args_macro_definition();
       break;
     }
 
     case 4: {
       enterOuterAlt(_localctx, 4);
-      setState(415);
+      setState(403);
       multiline_no_args_macro_definition();
       break;
     }
 
     case 5: {
       enterOuterAlt(_localctx, 5);
-      setState(416);
+      setState(404);
       simple_args_macro_definition();
       break;
     }
@@ -1723,19 +1723,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(419);
+    setState(407);
     include_directive();
-    setState(423);
+    setState(411);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(420);
+      setState(408);
       match(SV3_1aPpParser::Spaces);
-      setState(425);
+      setState(413);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(426);
+    setState(414);
     match(SV3_1aPpParser::CR);
    
   }
@@ -1804,34 +1804,34 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(428);
+    setState(416);
     match(SV3_1aPpParser::TICK_INCLUDE);
-    setState(429);
+    setState(417);
     match(SV3_1aPpParser::Spaces);
-    setState(434);
+    setState(422);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::String: {
-        setState(430);
+        setState(418);
         match(SV3_1aPpParser::String);
         break;
       }
 
       case SV3_1aPpParser::Simple_identifier: {
-        setState(431);
+        setState(419);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(432);
+        setState(420);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(433);
+        setState(421);
         macro_instance();
         break;
       }
@@ -1899,19 +1899,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(436);
+    setState(424);
     line_directive();
-    setState(440);
+    setState(428);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(437);
+      setState(425);
       match(SV3_1aPpParser::Spaces);
-      setState(442);
+      setState(430);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(443);
+    setState(431);
     match(SV3_1aPpParser::CR);
    
   }
@@ -1980,17 +1980,17 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(445);
+    setState(433);
     match(SV3_1aPpParser::TICK_LINE);
-    setState(446);
+    setState(434);
     match(SV3_1aPpParser::Spaces);
-    setState(447);
+    setState(435);
     number();
-    setState(448);
+    setState(436);
     match(SV3_1aPpParser::String);
-    setState(449);
+    setState(437);
     match(SV3_1aPpParser::Spaces);
-    setState(450);
+    setState(438);
     number();
    
   }
@@ -2052,19 +2052,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(452);
+    setState(440);
     default_nettype_directive();
-    setState(456);
+    setState(444);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(453);
+      setState(441);
       match(SV3_1aPpParser::Spaces);
-      setState(458);
+      setState(446);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(459);
+    setState(447);
     match(SV3_1aPpParser::CR);
    
   }
@@ -2121,11 +2121,11 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(461);
+    setState(449);
     match(SV3_1aPpParser::TICK_DEFAULT_NETTYPE);
-    setState(462);
+    setState(450);
     match(SV3_1aPpParser::Spaces);
-    setState(463);
+    setState(451);
     match(SV3_1aPpParser::Simple_identifier);
    
   }
@@ -2174,7 +2174,7 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(465);
+    setState(453);
     match(SV3_1aPpParser::TICK_FILE__);
    
   }
@@ -2223,7 +2223,7 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(467);
+    setState(455);
     match(SV3_1aPpParser::TICK_LINE__);
    
   }
@@ -2285,19 +2285,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(469);
+    setState(457);
     timescale_directive();
-    setState(473);
+    setState(461);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(470);
+      setState(458);
       match(SV3_1aPpParser::Spaces);
-      setState(475);
+      setState(463);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(476);
+    setState(464);
     match(SV3_1aPpParser::CR);
    
   }
@@ -2350,9 +2350,9 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(478);
+    setState(466);
     match(SV3_1aPpParser::TICK_TIMESCALE);
-    setState(479);
+    setState(467);
     match(SV3_1aPpParser::TIMESCALE);
    
   }
@@ -2417,28 +2417,28 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(481);
+    setState(469);
     match(SV3_1aPpParser::TICK_UNDEF);
-    setState(482);
+    setState(470);
     match(SV3_1aPpParser::Spaces);
-    setState(486);
+    setState(474);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
-        setState(483);
+        setState(471);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(484);
+        setState(472);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(485);
+        setState(473);
         macro_instance();
         break;
       }
@@ -2457,207 +2457,6 @@
   return _localctx;
 }
 
-//----------------- Ifdef_directive_one_lineContext ------------------------------------------------------------------
-
-SV3_1aPpParser::Ifdef_directive_one_lineContext::Ifdef_directive_one_lineContext(ParserRuleContext *parent, size_t invokingState)
-  : ParserRuleContext(parent, invokingState) {
-}
-
-SV3_1aPpParser::Ifdef_directiveContext* SV3_1aPpParser::Ifdef_directive_one_lineContext::ifdef_directive() {
-  return getRuleContext<SV3_1aPpParser::Ifdef_directiveContext>(0);
-}
-
-std::vector<tree::TerminalNode *> SV3_1aPpParser::Ifdef_directive_one_lineContext::Spaces() {
-  return getTokens(SV3_1aPpParser::Spaces);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Ifdef_directive_one_lineContext::Spaces(size_t i) {
-  return getToken(SV3_1aPpParser::Spaces, i);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Ifdef_directive_one_lineContext::One_line_comment() {
-  return getToken(SV3_1aPpParser::One_line_comment, 0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Ifdef_directive_one_lineContext::CR() {
-  return getToken(SV3_1aPpParser::CR, 0);
-}
-
-SV3_1aPpParser::Endif_directiveContext* SV3_1aPpParser::Ifdef_directive_one_lineContext::endif_directive() {
-  return getRuleContext<SV3_1aPpParser::Endif_directiveContext>(0);
-}
-
-std::vector<SV3_1aPpParser::DescriptionContext *> SV3_1aPpParser::Ifdef_directive_one_lineContext::description() {
-  return getRuleContexts<SV3_1aPpParser::DescriptionContext>();
-}
-
-SV3_1aPpParser::DescriptionContext* SV3_1aPpParser::Ifdef_directive_one_lineContext::description(size_t i) {
-  return getRuleContext<SV3_1aPpParser::DescriptionContext>(i);
-}
-
-std::vector<SV3_1aPpParser::Else_directiveContext *> SV3_1aPpParser::Ifdef_directive_one_lineContext::else_directive() {
-  return getRuleContexts<SV3_1aPpParser::Else_directiveContext>();
-}
-
-SV3_1aPpParser::Else_directiveContext* SV3_1aPpParser::Ifdef_directive_one_lineContext::else_directive(size_t i) {
-  return getRuleContext<SV3_1aPpParser::Else_directiveContext>(i);
-}
-
-std::vector<SV3_1aPpParser::Elseif_directiveContext *> SV3_1aPpParser::Ifdef_directive_one_lineContext::elseif_directive() {
-  return getRuleContexts<SV3_1aPpParser::Elseif_directiveContext>();
-}
-
-SV3_1aPpParser::Elseif_directiveContext* SV3_1aPpParser::Ifdef_directive_one_lineContext::elseif_directive(size_t i) {
-  return getRuleContext<SV3_1aPpParser::Elseif_directiveContext>(i);
-}
-
-std::vector<SV3_1aPpParser::Elsif_directiveContext *> SV3_1aPpParser::Ifdef_directive_one_lineContext::elsif_directive() {
-  return getRuleContexts<SV3_1aPpParser::Elsif_directiveContext>();
-}
-
-SV3_1aPpParser::Elsif_directiveContext* SV3_1aPpParser::Ifdef_directive_one_lineContext::elsif_directive(size_t i) {
-  return getRuleContext<SV3_1aPpParser::Elsif_directiveContext>(i);
-}
-
-
-size_t SV3_1aPpParser::Ifdef_directive_one_lineContext::getRuleIndex() const {
-  return SV3_1aPpParser::RuleIfdef_directive_one_line;
-}
-
-void SV3_1aPpParser::Ifdef_directive_one_lineContext::enterRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->enterIfdef_directive_one_line(this);
-}
-
-void SV3_1aPpParser::Ifdef_directive_one_lineContext::exitRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->exitIfdef_directive_one_line(this);
-}
-
-SV3_1aPpParser::Ifdef_directive_one_lineContext* SV3_1aPpParser::ifdef_directive_one_line() {
-  Ifdef_directive_one_lineContext *_localctx = _tracker.createInstance<Ifdef_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 40, SV3_1aPpParser::RuleIfdef_directive_one_line);
-  size_t _la = 0;
-
-  auto onExit = finally([=] {
-    exitRule();
-  });
-  try {
-    size_t alt;
-    enterOuterAlt(_localctx, 1);
-    setState(488);
-    ifdef_directive();
-    setState(492);
-    _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 15, _ctx);
-    while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
-      if (alt == 1) {
-        setState(489);
-        match(SV3_1aPpParser::Spaces); 
-      }
-      setState(494);
-      _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 15, _ctx);
-    }
-    setState(518);
-    _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 20, _ctx)) {
-    case 1: {
-      setState(495);
-      _la = _input->LA(1);
-      if (!(_la == SV3_1aPpParser::One_line_comment || _la == SV3_1aPpParser::CR)) {
-      _errHandler->recoverInline(this);
-      }
-      else {
-        _errHandler->reportMatch(this);
-        consume();
-      }
-      break;
-    }
-
-    case 2: {
-      setState(499);
-      _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 16, _ctx);
-      while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
-        if (alt == 1) {
-          setState(496);
-          description(); 
-        }
-        setState(501);
-        _errHandler->sync(this);
-        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 16, _ctx);
-      }
-      setState(514);
-      _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 19, _ctx);
-      while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
-        if (alt == 1) {
-          setState(505);
-          _errHandler->sync(this);
-
-          switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 17, _ctx)) {
-          case 1: {
-            setState(502);
-            else_directive();
-            break;
-          }
-
-          case 2: {
-            setState(503);
-            elseif_directive();
-            break;
-          }
-
-          case 3: {
-            setState(504);
-            elsif_directive();
-            break;
-          }
-
-          }
-          setState(508); 
-          _errHandler->sync(this);
-          alt = 1;
-          do {
-            switch (alt) {
-              case 1: {
-                    setState(507);
-                    description();
-                    break;
-                  }
-
-            default:
-              throw NoViableAltException(this);
-            }
-            setState(510); 
-            _errHandler->sync(this);
-            alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 18, _ctx);
-          } while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER); 
-        }
-        setState(516);
-        _errHandler->sync(this);
-        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 19, _ctx);
-      }
-      setState(517);
-      endif_directive();
-      break;
-    }
-
-    }
-   
-  }
-  catch (RecognitionException &e) {
-    _errHandler->reportError(this, e);
-    _localctx->exception = std::current_exception();
-    _errHandler->recover(this, _localctx->exception);
-  }
-
-  return _localctx;
-}
-
 //----------------- Ifdef_directiveContext ------------------------------------------------------------------
 
 SV3_1aPpParser::Ifdef_directiveContext::Ifdef_directiveContext(ParserRuleContext *parent, size_t invokingState)
@@ -2703,35 +2502,35 @@
 
 SV3_1aPpParser::Ifdef_directiveContext* SV3_1aPpParser::ifdef_directive() {
   Ifdef_directiveContext *_localctx = _tracker.createInstance<Ifdef_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 42, SV3_1aPpParser::RuleIfdef_directive);
+  enterRule(_localctx, 40, SV3_1aPpParser::RuleIfdef_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(520);
+    setState(476);
     match(SV3_1aPpParser::TICK_IFDEF);
-    setState(521);
+    setState(477);
     match(SV3_1aPpParser::Spaces);
-    setState(525);
+    setState(481);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
-        setState(522);
+        setState(478);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(523);
+        setState(479);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(524);
+        setState(480);
         macro_instance();
         break;
       }
@@ -2795,36 +2594,36 @@
 
 SV3_1aPpParser::Ifdef_directive_in_macro_bodyContext* SV3_1aPpParser::ifdef_directive_in_macro_body() {
   Ifdef_directive_in_macro_bodyContext *_localctx = _tracker.createInstance<Ifdef_directive_in_macro_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 44, SV3_1aPpParser::RuleIfdef_directive_in_macro_body);
+  enterRule(_localctx, 42, SV3_1aPpParser::RuleIfdef_directive_in_macro_body);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(527);
+    setState(483);
     match(SV3_1aPpParser::TICK_IFDEF);
-    setState(528);
+    setState(484);
     match(SV3_1aPpParser::Spaces);
-    setState(532);
+    setState(488);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::EOF:
       case SV3_1aPpParser::Simple_identifier: {
-        setState(529);
+        setState(485);
         identifier_in_macro_body();
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(530);
+        setState(486);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(531);
+        setState(487);
         macro_instance();
         break;
       }
@@ -2843,207 +2642,6 @@
   return _localctx;
 }
 
-//----------------- Ifndef_directive_one_lineContext ------------------------------------------------------------------
-
-SV3_1aPpParser::Ifndef_directive_one_lineContext::Ifndef_directive_one_lineContext(ParserRuleContext *parent, size_t invokingState)
-  : ParserRuleContext(parent, invokingState) {
-}
-
-SV3_1aPpParser::Ifndef_directiveContext* SV3_1aPpParser::Ifndef_directive_one_lineContext::ifndef_directive() {
-  return getRuleContext<SV3_1aPpParser::Ifndef_directiveContext>(0);
-}
-
-std::vector<tree::TerminalNode *> SV3_1aPpParser::Ifndef_directive_one_lineContext::Spaces() {
-  return getTokens(SV3_1aPpParser::Spaces);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Ifndef_directive_one_lineContext::Spaces(size_t i) {
-  return getToken(SV3_1aPpParser::Spaces, i);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Ifndef_directive_one_lineContext::One_line_comment() {
-  return getToken(SV3_1aPpParser::One_line_comment, 0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Ifndef_directive_one_lineContext::CR() {
-  return getToken(SV3_1aPpParser::CR, 0);
-}
-
-SV3_1aPpParser::Endif_directiveContext* SV3_1aPpParser::Ifndef_directive_one_lineContext::endif_directive() {
-  return getRuleContext<SV3_1aPpParser::Endif_directiveContext>(0);
-}
-
-std::vector<SV3_1aPpParser::DescriptionContext *> SV3_1aPpParser::Ifndef_directive_one_lineContext::description() {
-  return getRuleContexts<SV3_1aPpParser::DescriptionContext>();
-}
-
-SV3_1aPpParser::DescriptionContext* SV3_1aPpParser::Ifndef_directive_one_lineContext::description(size_t i) {
-  return getRuleContext<SV3_1aPpParser::DescriptionContext>(i);
-}
-
-std::vector<SV3_1aPpParser::Else_directiveContext *> SV3_1aPpParser::Ifndef_directive_one_lineContext::else_directive() {
-  return getRuleContexts<SV3_1aPpParser::Else_directiveContext>();
-}
-
-SV3_1aPpParser::Else_directiveContext* SV3_1aPpParser::Ifndef_directive_one_lineContext::else_directive(size_t i) {
-  return getRuleContext<SV3_1aPpParser::Else_directiveContext>(i);
-}
-
-std::vector<SV3_1aPpParser::Elseif_directiveContext *> SV3_1aPpParser::Ifndef_directive_one_lineContext::elseif_directive() {
-  return getRuleContexts<SV3_1aPpParser::Elseif_directiveContext>();
-}
-
-SV3_1aPpParser::Elseif_directiveContext* SV3_1aPpParser::Ifndef_directive_one_lineContext::elseif_directive(size_t i) {
-  return getRuleContext<SV3_1aPpParser::Elseif_directiveContext>(i);
-}
-
-std::vector<SV3_1aPpParser::Elsif_directiveContext *> SV3_1aPpParser::Ifndef_directive_one_lineContext::elsif_directive() {
-  return getRuleContexts<SV3_1aPpParser::Elsif_directiveContext>();
-}
-
-SV3_1aPpParser::Elsif_directiveContext* SV3_1aPpParser::Ifndef_directive_one_lineContext::elsif_directive(size_t i) {
-  return getRuleContext<SV3_1aPpParser::Elsif_directiveContext>(i);
-}
-
-
-size_t SV3_1aPpParser::Ifndef_directive_one_lineContext::getRuleIndex() const {
-  return SV3_1aPpParser::RuleIfndef_directive_one_line;
-}
-
-void SV3_1aPpParser::Ifndef_directive_one_lineContext::enterRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->enterIfndef_directive_one_line(this);
-}
-
-void SV3_1aPpParser::Ifndef_directive_one_lineContext::exitRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->exitIfndef_directive_one_line(this);
-}
-
-SV3_1aPpParser::Ifndef_directive_one_lineContext* SV3_1aPpParser::ifndef_directive_one_line() {
-  Ifndef_directive_one_lineContext *_localctx = _tracker.createInstance<Ifndef_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 46, SV3_1aPpParser::RuleIfndef_directive_one_line);
-  size_t _la = 0;
-
-  auto onExit = finally([=] {
-    exitRule();
-  });
-  try {
-    size_t alt;
-    enterOuterAlt(_localctx, 1);
-    setState(534);
-    ifndef_directive();
-    setState(538);
-    _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 23, _ctx);
-    while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
-      if (alt == 1) {
-        setState(535);
-        match(SV3_1aPpParser::Spaces); 
-      }
-      setState(540);
-      _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 23, _ctx);
-    }
-    setState(564);
-    _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 28, _ctx)) {
-    case 1: {
-      setState(541);
-      _la = _input->LA(1);
-      if (!(_la == SV3_1aPpParser::One_line_comment || _la == SV3_1aPpParser::CR)) {
-      _errHandler->recoverInline(this);
-      }
-      else {
-        _errHandler->reportMatch(this);
-        consume();
-      }
-      break;
-    }
-
-    case 2: {
-      setState(545);
-      _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 24, _ctx);
-      while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
-        if (alt == 1) {
-          setState(542);
-          description(); 
-        }
-        setState(547);
-        _errHandler->sync(this);
-        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 24, _ctx);
-      }
-      setState(560);
-      _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 27, _ctx);
-      while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
-        if (alt == 1) {
-          setState(551);
-          _errHandler->sync(this);
-
-          switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 25, _ctx)) {
-          case 1: {
-            setState(548);
-            else_directive();
-            break;
-          }
-
-          case 2: {
-            setState(549);
-            elseif_directive();
-            break;
-          }
-
-          case 3: {
-            setState(550);
-            elsif_directive();
-            break;
-          }
-
-          }
-          setState(554); 
-          _errHandler->sync(this);
-          alt = 1;
-          do {
-            switch (alt) {
-              case 1: {
-                    setState(553);
-                    description();
-                    break;
-                  }
-
-            default:
-              throw NoViableAltException(this);
-            }
-            setState(556); 
-            _errHandler->sync(this);
-            alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 26, _ctx);
-          } while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER); 
-        }
-        setState(562);
-        _errHandler->sync(this);
-        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 27, _ctx);
-      }
-      setState(563);
-      endif_directive();
-      break;
-    }
-
-    }
-   
-  }
-  catch (RecognitionException &e) {
-    _errHandler->reportError(this, e);
-    _localctx->exception = std::current_exception();
-    _errHandler->recover(this, _localctx->exception);
-  }
-
-  return _localctx;
-}
-
 //----------------- Ifndef_directiveContext ------------------------------------------------------------------
 
 SV3_1aPpParser::Ifndef_directiveContext::Ifndef_directiveContext(ParserRuleContext *parent, size_t invokingState)
@@ -3089,35 +2687,35 @@
 
 SV3_1aPpParser::Ifndef_directiveContext* SV3_1aPpParser::ifndef_directive() {
   Ifndef_directiveContext *_localctx = _tracker.createInstance<Ifndef_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 48, SV3_1aPpParser::RuleIfndef_directive);
+  enterRule(_localctx, 44, SV3_1aPpParser::RuleIfndef_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(566);
+    setState(490);
     match(SV3_1aPpParser::TICK_IFNDEF);
-    setState(567);
+    setState(491);
     match(SV3_1aPpParser::Spaces);
-    setState(571);
+    setState(495);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
-        setState(568);
+        setState(492);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(569);
+        setState(493);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(570);
+        setState(494);
         macro_instance();
         break;
       }
@@ -3181,36 +2779,36 @@
 
 SV3_1aPpParser::Ifndef_directive_in_macro_bodyContext* SV3_1aPpParser::ifndef_directive_in_macro_body() {
   Ifndef_directive_in_macro_bodyContext *_localctx = _tracker.createInstance<Ifndef_directive_in_macro_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 50, SV3_1aPpParser::RuleIfndef_directive_in_macro_body);
+  enterRule(_localctx, 46, SV3_1aPpParser::RuleIfndef_directive_in_macro_body);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(573);
+    setState(497);
     match(SV3_1aPpParser::TICK_IFNDEF);
-    setState(574);
+    setState(498);
     match(SV3_1aPpParser::Spaces);
-    setState(578);
+    setState(502);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::EOF:
       case SV3_1aPpParser::Simple_identifier: {
-        setState(575);
+        setState(499);
         identifier_in_macro_body();
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(576);
+        setState(500);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(577);
+        setState(501);
         macro_instance();
         break;
       }
@@ -3229,91 +2827,6 @@
   return _localctx;
 }
 
-//----------------- Elsif_directive_one_lineContext ------------------------------------------------------------------
-
-SV3_1aPpParser::Elsif_directive_one_lineContext::Elsif_directive_one_lineContext(ParserRuleContext *parent, size_t invokingState)
-  : ParserRuleContext(parent, invokingState) {
-}
-
-SV3_1aPpParser::Elsif_directiveContext* SV3_1aPpParser::Elsif_directive_one_lineContext::elsif_directive() {
-  return getRuleContext<SV3_1aPpParser::Elsif_directiveContext>(0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Elsif_directive_one_lineContext::One_line_comment() {
-  return getToken(SV3_1aPpParser::One_line_comment, 0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Elsif_directive_one_lineContext::CR() {
-  return getToken(SV3_1aPpParser::CR, 0);
-}
-
-std::vector<tree::TerminalNode *> SV3_1aPpParser::Elsif_directive_one_lineContext::Spaces() {
-  return getTokens(SV3_1aPpParser::Spaces);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Elsif_directive_one_lineContext::Spaces(size_t i) {
-  return getToken(SV3_1aPpParser::Spaces, i);
-}
-
-
-size_t SV3_1aPpParser::Elsif_directive_one_lineContext::getRuleIndex() const {
-  return SV3_1aPpParser::RuleElsif_directive_one_line;
-}
-
-void SV3_1aPpParser::Elsif_directive_one_lineContext::enterRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->enterElsif_directive_one_line(this);
-}
-
-void SV3_1aPpParser::Elsif_directive_one_lineContext::exitRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->exitElsif_directive_one_line(this);
-}
-
-SV3_1aPpParser::Elsif_directive_one_lineContext* SV3_1aPpParser::elsif_directive_one_line() {
-  Elsif_directive_one_lineContext *_localctx = _tracker.createInstance<Elsif_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 52, SV3_1aPpParser::RuleElsif_directive_one_line);
-  size_t _la = 0;
-
-  auto onExit = finally([=] {
-    exitRule();
-  });
-  try {
-    enterOuterAlt(_localctx, 1);
-    setState(580);
-    elsif_directive();
-    setState(584);
-    _errHandler->sync(this);
-    _la = _input->LA(1);
-    while (_la == SV3_1aPpParser::Spaces) {
-      setState(581);
-      match(SV3_1aPpParser::Spaces);
-      setState(586);
-      _errHandler->sync(this);
-      _la = _input->LA(1);
-    }
-    setState(587);
-    _la = _input->LA(1);
-    if (!(_la == SV3_1aPpParser::One_line_comment || _la == SV3_1aPpParser::CR)) {
-    _errHandler->recoverInline(this);
-    }
-    else {
-      _errHandler->reportMatch(this);
-      consume();
-    }
-   
-  }
-  catch (RecognitionException &e) {
-    _errHandler->reportError(this, e);
-    _localctx->exception = std::current_exception();
-    _errHandler->recover(this, _localctx->exception);
-  }
-
-  return _localctx;
-}
-
 //----------------- Elsif_directiveContext ------------------------------------------------------------------
 
 SV3_1aPpParser::Elsif_directiveContext::Elsif_directiveContext(ParserRuleContext *parent, size_t invokingState)
@@ -3359,35 +2872,35 @@
 
 SV3_1aPpParser::Elsif_directiveContext* SV3_1aPpParser::elsif_directive() {
   Elsif_directiveContext *_localctx = _tracker.createInstance<Elsif_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 54, SV3_1aPpParser::RuleElsif_directive);
+  enterRule(_localctx, 48, SV3_1aPpParser::RuleElsif_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(589);
+    setState(504);
     match(SV3_1aPpParser::TICK_ELSIF);
-    setState(590);
+    setState(505);
     match(SV3_1aPpParser::Spaces);
-    setState(594);
+    setState(509);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
-        setState(591);
+        setState(506);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(592);
+        setState(507);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(593);
+        setState(508);
         macro_instance();
         break;
       }
@@ -3451,36 +2964,36 @@
 
 SV3_1aPpParser::Elsif_directive_in_macro_bodyContext* SV3_1aPpParser::elsif_directive_in_macro_body() {
   Elsif_directive_in_macro_bodyContext *_localctx = _tracker.createInstance<Elsif_directive_in_macro_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 56, SV3_1aPpParser::RuleElsif_directive_in_macro_body);
+  enterRule(_localctx, 50, SV3_1aPpParser::RuleElsif_directive_in_macro_body);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(596);
+    setState(511);
     match(SV3_1aPpParser::TICK_ELSIF);
-    setState(597);
+    setState(512);
     match(SV3_1aPpParser::Spaces);
-    setState(601);
+    setState(516);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::EOF:
       case SV3_1aPpParser::Simple_identifier: {
-        setState(598);
+        setState(513);
         identifier_in_macro_body();
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(599);
+        setState(514);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(600);
+        setState(515);
         macro_instance();
         break;
       }
@@ -3499,91 +3012,6 @@
   return _localctx;
 }
 
-//----------------- Elseif_directive_one_lineContext ------------------------------------------------------------------
-
-SV3_1aPpParser::Elseif_directive_one_lineContext::Elseif_directive_one_lineContext(ParserRuleContext *parent, size_t invokingState)
-  : ParserRuleContext(parent, invokingState) {
-}
-
-SV3_1aPpParser::Elseif_directiveContext* SV3_1aPpParser::Elseif_directive_one_lineContext::elseif_directive() {
-  return getRuleContext<SV3_1aPpParser::Elseif_directiveContext>(0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Elseif_directive_one_lineContext::One_line_comment() {
-  return getToken(SV3_1aPpParser::One_line_comment, 0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Elseif_directive_one_lineContext::CR() {
-  return getToken(SV3_1aPpParser::CR, 0);
-}
-
-std::vector<tree::TerminalNode *> SV3_1aPpParser::Elseif_directive_one_lineContext::Spaces() {
-  return getTokens(SV3_1aPpParser::Spaces);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Elseif_directive_one_lineContext::Spaces(size_t i) {
-  return getToken(SV3_1aPpParser::Spaces, i);
-}
-
-
-size_t SV3_1aPpParser::Elseif_directive_one_lineContext::getRuleIndex() const {
-  return SV3_1aPpParser::RuleElseif_directive_one_line;
-}
-
-void SV3_1aPpParser::Elseif_directive_one_lineContext::enterRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->enterElseif_directive_one_line(this);
-}
-
-void SV3_1aPpParser::Elseif_directive_one_lineContext::exitRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->exitElseif_directive_one_line(this);
-}
-
-SV3_1aPpParser::Elseif_directive_one_lineContext* SV3_1aPpParser::elseif_directive_one_line() {
-  Elseif_directive_one_lineContext *_localctx = _tracker.createInstance<Elseif_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 58, SV3_1aPpParser::RuleElseif_directive_one_line);
-  size_t _la = 0;
-
-  auto onExit = finally([=] {
-    exitRule();
-  });
-  try {
-    enterOuterAlt(_localctx, 1);
-    setState(603);
-    elseif_directive();
-    setState(607);
-    _errHandler->sync(this);
-    _la = _input->LA(1);
-    while (_la == SV3_1aPpParser::Spaces) {
-      setState(604);
-      match(SV3_1aPpParser::Spaces);
-      setState(609);
-      _errHandler->sync(this);
-      _la = _input->LA(1);
-    }
-    setState(610);
-    _la = _input->LA(1);
-    if (!(_la == SV3_1aPpParser::One_line_comment || _la == SV3_1aPpParser::CR)) {
-    _errHandler->recoverInline(this);
-    }
-    else {
-      _errHandler->reportMatch(this);
-      consume();
-    }
-   
-  }
-  catch (RecognitionException &e) {
-    _errHandler->reportError(this, e);
-    _localctx->exception = std::current_exception();
-    _errHandler->recover(this, _localctx->exception);
-  }
-
-  return _localctx;
-}
-
 //----------------- Elseif_directiveContext ------------------------------------------------------------------
 
 SV3_1aPpParser::Elseif_directiveContext::Elseif_directiveContext(ParserRuleContext *parent, size_t invokingState)
@@ -3629,35 +3057,35 @@
 
 SV3_1aPpParser::Elseif_directiveContext* SV3_1aPpParser::elseif_directive() {
   Elseif_directiveContext *_localctx = _tracker.createInstance<Elseif_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 60, SV3_1aPpParser::RuleElseif_directive);
+  enterRule(_localctx, 52, SV3_1aPpParser::RuleElseif_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(612);
+    setState(518);
     match(SV3_1aPpParser::TICK_ELSEIF);
-    setState(613);
+    setState(519);
     match(SV3_1aPpParser::Spaces);
-    setState(617);
+    setState(523);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
-        setState(614);
+        setState(520);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(615);
+        setState(521);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(616);
+        setState(522);
         macro_instance();
         break;
       }
@@ -3721,36 +3149,36 @@
 
 SV3_1aPpParser::Elseif_directive_in_macro_bodyContext* SV3_1aPpParser::elseif_directive_in_macro_body() {
   Elseif_directive_in_macro_bodyContext *_localctx = _tracker.createInstance<Elseif_directive_in_macro_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 62, SV3_1aPpParser::RuleElseif_directive_in_macro_body);
+  enterRule(_localctx, 54, SV3_1aPpParser::RuleElseif_directive_in_macro_body);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(619);
+    setState(525);
     match(SV3_1aPpParser::TICK_ELSEIF);
-    setState(620);
+    setState(526);
     match(SV3_1aPpParser::Spaces);
-    setState(624);
+    setState(530);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::EOF:
       case SV3_1aPpParser::Simple_identifier: {
-        setState(621);
+        setState(527);
         identifier_in_macro_body();
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
-        setState(622);
+        setState(528);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
-        setState(623);
+        setState(529);
         macro_instance();
         break;
       }
@@ -3769,91 +3197,6 @@
   return _localctx;
 }
 
-//----------------- Else_directive_one_lineContext ------------------------------------------------------------------
-
-SV3_1aPpParser::Else_directive_one_lineContext::Else_directive_one_lineContext(ParserRuleContext *parent, size_t invokingState)
-  : ParserRuleContext(parent, invokingState) {
-}
-
-SV3_1aPpParser::Else_directiveContext* SV3_1aPpParser::Else_directive_one_lineContext::else_directive() {
-  return getRuleContext<SV3_1aPpParser::Else_directiveContext>(0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Else_directive_one_lineContext::One_line_comment() {
-  return getToken(SV3_1aPpParser::One_line_comment, 0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Else_directive_one_lineContext::CR() {
-  return getToken(SV3_1aPpParser::CR, 0);
-}
-
-std::vector<tree::TerminalNode *> SV3_1aPpParser::Else_directive_one_lineContext::Spaces() {
-  return getTokens(SV3_1aPpParser::Spaces);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Else_directive_one_lineContext::Spaces(size_t i) {
-  return getToken(SV3_1aPpParser::Spaces, i);
-}
-
-
-size_t SV3_1aPpParser::Else_directive_one_lineContext::getRuleIndex() const {
-  return SV3_1aPpParser::RuleElse_directive_one_line;
-}
-
-void SV3_1aPpParser::Else_directive_one_lineContext::enterRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->enterElse_directive_one_line(this);
-}
-
-void SV3_1aPpParser::Else_directive_one_lineContext::exitRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->exitElse_directive_one_line(this);
-}
-
-SV3_1aPpParser::Else_directive_one_lineContext* SV3_1aPpParser::else_directive_one_line() {
-  Else_directive_one_lineContext *_localctx = _tracker.createInstance<Else_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 64, SV3_1aPpParser::RuleElse_directive_one_line);
-  size_t _la = 0;
-
-  auto onExit = finally([=] {
-    exitRule();
-  });
-  try {
-    enterOuterAlt(_localctx, 1);
-    setState(626);
-    else_directive();
-    setState(630);
-    _errHandler->sync(this);
-    _la = _input->LA(1);
-    while (_la == SV3_1aPpParser::Spaces) {
-      setState(627);
-      match(SV3_1aPpParser::Spaces);
-      setState(632);
-      _errHandler->sync(this);
-      _la = _input->LA(1);
-    }
-    setState(633);
-    _la = _input->LA(1);
-    if (!(_la == SV3_1aPpParser::One_line_comment || _la == SV3_1aPpParser::CR)) {
-    _errHandler->recoverInline(this);
-    }
-    else {
-      _errHandler->reportMatch(this);
-      consume();
-    }
-   
-  }
-  catch (RecognitionException &e) {
-    _errHandler->reportError(this, e);
-    _localctx->exception = std::current_exception();
-    _errHandler->recover(this, _localctx->exception);
-  }
-
-  return _localctx;
-}
-
 //----------------- Else_directiveContext ------------------------------------------------------------------
 
 SV3_1aPpParser::Else_directiveContext::Else_directiveContext(ParserRuleContext *parent, size_t invokingState)
@@ -3883,14 +3226,14 @@
 
 SV3_1aPpParser::Else_directiveContext* SV3_1aPpParser::else_directive() {
   Else_directiveContext *_localctx = _tracker.createInstance<Else_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 66, SV3_1aPpParser::RuleElse_directive);
+  enterRule(_localctx, 56, SV3_1aPpParser::RuleElse_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(635);
+    setState(532);
     match(SV3_1aPpParser::TICK_ELSE);
    
   }
@@ -3903,124 +3246,6 @@
   return _localctx;
 }
 
-//----------------- Endif_directive_one_lineContext ------------------------------------------------------------------
-
-SV3_1aPpParser::Endif_directive_one_lineContext::Endif_directive_one_lineContext(ParserRuleContext *parent, size_t invokingState)
-  : ParserRuleContext(parent, invokingState) {
-}
-
-tree::TerminalNode* SV3_1aPpParser::Endif_directive_one_lineContext::TICK_ENDIF() {
-  return getToken(SV3_1aPpParser::TICK_ENDIF, 0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Endif_directive_one_lineContext::One_line_comment() {
-  return getToken(SV3_1aPpParser::One_line_comment, 0);
-}
-
-std::vector<tree::TerminalNode *> SV3_1aPpParser::Endif_directive_one_lineContext::Spaces() {
-  return getTokens(SV3_1aPpParser::Spaces);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Endif_directive_one_lineContext::Spaces(size_t i) {
-  return getToken(SV3_1aPpParser::Spaces, i);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Endif_directive_one_lineContext::CR() {
-  return getToken(SV3_1aPpParser::CR, 0);
-}
-
-tree::TerminalNode* SV3_1aPpParser::Endif_directive_one_lineContext::EOF() {
-  return getToken(SV3_1aPpParser::EOF, 0);
-}
-
-
-size_t SV3_1aPpParser::Endif_directive_one_lineContext::getRuleIndex() const {
-  return SV3_1aPpParser::RuleEndif_directive_one_line;
-}
-
-void SV3_1aPpParser::Endif_directive_one_lineContext::enterRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->enterEndif_directive_one_line(this);
-}
-
-void SV3_1aPpParser::Endif_directive_one_lineContext::exitRule(tree::ParseTreeListener *listener) {
-  auto parserListener = dynamic_cast<SV3_1aPpParserListener *>(listener);
-  if (parserListener != nullptr)
-    parserListener->exitEndif_directive_one_line(this);
-}
-
-SV3_1aPpParser::Endif_directive_one_lineContext* SV3_1aPpParser::endif_directive_one_line() {
-  Endif_directive_one_lineContext *_localctx = _tracker.createInstance<Endif_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 68, SV3_1aPpParser::RuleEndif_directive_one_line);
-  size_t _la = 0;
-
-  auto onExit = finally([=] {
-    exitRule();
-  });
-  try {
-    setState(655);
-    _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 40, _ctx)) {
-    case 1: {
-      enterOuterAlt(_localctx, 1);
-      setState(637);
-      match(SV3_1aPpParser::TICK_ENDIF);
-      setState(641);
-      _errHandler->sync(this);
-      _la = _input->LA(1);
-      while (_la == SV3_1aPpParser::Spaces) {
-        setState(638);
-        match(SV3_1aPpParser::Spaces);
-        setState(643);
-        _errHandler->sync(this);
-        _la = _input->LA(1);
-      }
-      setState(644);
-      match(SV3_1aPpParser::One_line_comment);
-      break;
-    }
-
-    case 2: {
-      enterOuterAlt(_localctx, 2);
-      setState(645);
-      match(SV3_1aPpParser::TICK_ENDIF);
-      setState(649);
-      _errHandler->sync(this);
-      _la = _input->LA(1);
-      while (_la == SV3_1aPpParser::Spaces) {
-        setState(646);
-        match(SV3_1aPpParser::Spaces);
-        setState(651);
-        _errHandler->sync(this);
-        _la = _input->LA(1);
-      }
-      setState(652);
-      match(SV3_1aPpParser::CR);
-      break;
-    }
-
-    case 3: {
-      enterOuterAlt(_localctx, 3);
-      setState(653);
-      match(SV3_1aPpParser::TICK_ENDIF);
-      setState(654);
-      match(SV3_1aPpParser::EOF);
-      break;
-    }
-
-    }
-   
-  }
-  catch (RecognitionException &e) {
-    _errHandler->reportError(this, e);
-    _localctx->exception = std::current_exception();
-    _errHandler->recover(this, _localctx->exception);
-  }
-
-  return _localctx;
-}
-
 //----------------- Endif_directiveContext ------------------------------------------------------------------
 
 SV3_1aPpParser::Endif_directiveContext::Endif_directiveContext(ParserRuleContext *parent, size_t invokingState)
@@ -4062,38 +3287,38 @@
 
 SV3_1aPpParser::Endif_directiveContext* SV3_1aPpParser::endif_directive() {
   Endif_directiveContext *_localctx = _tracker.createInstance<Endif_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 70, SV3_1aPpParser::RuleEndif_directive);
+  enterRule(_localctx, 58, SV3_1aPpParser::RuleEndif_directive);
   size_t _la = 0;
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(666);
+    setState(543);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 42, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 24, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(657);
+      setState(534);
       match(SV3_1aPpParser::TICK_ENDIF);
-      setState(661);
+      setState(538);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while (_la == SV3_1aPpParser::Spaces) {
-        setState(658);
+        setState(535);
         match(SV3_1aPpParser::Spaces);
-        setState(663);
+        setState(540);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(664);
+      setState(541);
       match(SV3_1aPpParser::One_line_comment);
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(665);
+      setState(542);
       match(SV3_1aPpParser::TICK_ENDIF);
       break;
     }
@@ -4151,7 +3376,7 @@
 
 SV3_1aPpParser::Resetall_directive_one_lineContext* SV3_1aPpParser::resetall_directive_one_line() {
   Resetall_directive_one_lineContext *_localctx = _tracker.createInstance<Resetall_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 72, SV3_1aPpParser::RuleResetall_directive_one_line);
+  enterRule(_localctx, 60, SV3_1aPpParser::RuleResetall_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -4159,19 +3384,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(668);
+    setState(545);
     resetall_directive();
-    setState(672);
+    setState(549);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(669);
+      setState(546);
       match(SV3_1aPpParser::Spaces);
-      setState(674);
+      setState(551);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(675);
+    setState(552);
     match(SV3_1aPpParser::CR);
    
   }
@@ -4213,14 +3438,14 @@
 
 SV3_1aPpParser::Resetall_directiveContext* SV3_1aPpParser::resetall_directive() {
   Resetall_directiveContext *_localctx = _tracker.createInstance<Resetall_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 74, SV3_1aPpParser::RuleResetall_directive);
+  enterRule(_localctx, 62, SV3_1aPpParser::RuleResetall_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(677);
+    setState(554);
     match(SV3_1aPpParser::TICK_RESETALL);
    
   }
@@ -4274,7 +3499,7 @@
 
 SV3_1aPpParser::Begin_keywords_directive_one_lineContext* SV3_1aPpParser::begin_keywords_directive_one_line() {
   Begin_keywords_directive_one_lineContext *_localctx = _tracker.createInstance<Begin_keywords_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 76, SV3_1aPpParser::RuleBegin_keywords_directive_one_line);
+  enterRule(_localctx, 64, SV3_1aPpParser::RuleBegin_keywords_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -4282,19 +3507,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(679);
+    setState(556);
     begin_keywords_directive();
-    setState(683);
+    setState(560);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(680);
+      setState(557);
       match(SV3_1aPpParser::Spaces);
-      setState(685);
+      setState(562);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(686);
+    setState(563);
     match(SV3_1aPpParser::CR);
    
   }
@@ -4344,18 +3569,18 @@
 
 SV3_1aPpParser::Begin_keywords_directiveContext* SV3_1aPpParser::begin_keywords_directive() {
   Begin_keywords_directiveContext *_localctx = _tracker.createInstance<Begin_keywords_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 78, SV3_1aPpParser::RuleBegin_keywords_directive);
+  enterRule(_localctx, 66, SV3_1aPpParser::RuleBegin_keywords_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(688);
+    setState(565);
     match(SV3_1aPpParser::TICK_BEGIN_KEYWORDS);
-    setState(689);
+    setState(566);
     match(SV3_1aPpParser::Spaces);
-    setState(690);
+    setState(567);
     match(SV3_1aPpParser::String);
    
   }
@@ -4409,7 +3634,7 @@
 
 SV3_1aPpParser::End_keywords_directive_one_lineContext* SV3_1aPpParser::end_keywords_directive_one_line() {
   End_keywords_directive_one_lineContext *_localctx = _tracker.createInstance<End_keywords_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 80, SV3_1aPpParser::RuleEnd_keywords_directive_one_line);
+  enterRule(_localctx, 68, SV3_1aPpParser::RuleEnd_keywords_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -4417,19 +3642,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(692);
+    setState(569);
     end_keywords_directive();
-    setState(696);
+    setState(573);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(693);
+      setState(570);
       match(SV3_1aPpParser::Spaces);
-      setState(698);
+      setState(575);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(699);
+    setState(576);
     match(SV3_1aPpParser::CR);
    
   }
@@ -4471,14 +3696,14 @@
 
 SV3_1aPpParser::End_keywords_directiveContext* SV3_1aPpParser::end_keywords_directive() {
   End_keywords_directiveContext *_localctx = _tracker.createInstance<End_keywords_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 82, SV3_1aPpParser::RuleEnd_keywords_directive);
+  enterRule(_localctx, 70, SV3_1aPpParser::RuleEnd_keywords_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(701);
+    setState(578);
     match(SV3_1aPpParser::TICK_END_KEYWORDS);
    
   }
@@ -4532,7 +3757,7 @@
 
 SV3_1aPpParser::Pragma_directive_one_lineContext* SV3_1aPpParser::pragma_directive_one_line() {
   Pragma_directive_one_lineContext *_localctx = _tracker.createInstance<Pragma_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 84, SV3_1aPpParser::RulePragma_directive_one_line);
+  enterRule(_localctx, 72, SV3_1aPpParser::RulePragma_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -4540,19 +3765,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(703);
+    setState(580);
     pragma_directive();
-    setState(707);
+    setState(584);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(704);
+      setState(581);
       match(SV3_1aPpParser::Spaces);
-      setState(709);
+      setState(586);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(710);
+    setState(587);
     match(SV3_1aPpParser::CR);
    
   }
@@ -4618,7 +3843,7 @@
 
 SV3_1aPpParser::Pragma_directiveContext* SV3_1aPpParser::pragma_directive() {
   Pragma_directiveContext *_localctx = _tracker.createInstance<Pragma_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 86, SV3_1aPpParser::RulePragma_directive);
+  enterRule(_localctx, 74, SV3_1aPpParser::RulePragma_directive);
 
   auto onExit = finally([=] {
     exitRule();
@@ -4626,37 +3851,37 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(712);
+    setState(589);
     match(SV3_1aPpParser::TICK_PRAGMA);
-    setState(713);
+    setState(590);
     match(SV3_1aPpParser::Spaces);
-    setState(714);
+    setState(591);
     match(SV3_1aPpParser::Simple_identifier);
-    setState(725);
+    setState(602);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 48, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 30, _ctx);
     while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1) {
-        setState(715);
+        setState(592);
         pragma_expression();
-        setState(720);
+        setState(597);
         _errHandler->sync(this);
-        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 47, _ctx);
+        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 29, _ctx);
         while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
           if (alt == 1) {
-            setState(716);
+            setState(593);
             match(SV3_1aPpParser::Special);
-            setState(717);
+            setState(594);
             pragma_expression(); 
           }
-          setState(722);
+          setState(599);
           _errHandler->sync(this);
-          alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 47, _ctx);
+          alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 29, _ctx);
         } 
       }
-      setState(727);
+      setState(604);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 48, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 30, _ctx);
     }
    
   }
@@ -4710,7 +3935,7 @@
 
 SV3_1aPpParser::Celldefine_directive_one_lineContext* SV3_1aPpParser::celldefine_directive_one_line() {
   Celldefine_directive_one_lineContext *_localctx = _tracker.createInstance<Celldefine_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 88, SV3_1aPpParser::RuleCelldefine_directive_one_line);
+  enterRule(_localctx, 76, SV3_1aPpParser::RuleCelldefine_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -4718,19 +3943,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(728);
+    setState(605);
     celldefine_directive();
-    setState(732);
+    setState(609);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(729);
+      setState(606);
       match(SV3_1aPpParser::Spaces);
-      setState(734);
+      setState(611);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(735);
+    setState(612);
     match(SV3_1aPpParser::CR);
    
   }
@@ -4772,14 +3997,14 @@
 
 SV3_1aPpParser::Celldefine_directiveContext* SV3_1aPpParser::celldefine_directive() {
   Celldefine_directiveContext *_localctx = _tracker.createInstance<Celldefine_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 90, SV3_1aPpParser::RuleCelldefine_directive);
+  enterRule(_localctx, 78, SV3_1aPpParser::RuleCelldefine_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(737);
+    setState(614);
     match(SV3_1aPpParser::TICK_CELLDEFINE);
    
   }
@@ -4833,7 +4058,7 @@
 
 SV3_1aPpParser::Endcelldefine_directive_one_lineContext* SV3_1aPpParser::endcelldefine_directive_one_line() {
   Endcelldefine_directive_one_lineContext *_localctx = _tracker.createInstance<Endcelldefine_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 92, SV3_1aPpParser::RuleEndcelldefine_directive_one_line);
+  enterRule(_localctx, 80, SV3_1aPpParser::RuleEndcelldefine_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -4841,19 +4066,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(739);
+    setState(616);
     endcelldefine_directive();
-    setState(743);
+    setState(620);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(740);
+      setState(617);
       match(SV3_1aPpParser::Spaces);
-      setState(745);
+      setState(622);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(746);
+    setState(623);
     match(SV3_1aPpParser::CR);
    
   }
@@ -4895,14 +4120,14 @@
 
 SV3_1aPpParser::Endcelldefine_directiveContext* SV3_1aPpParser::endcelldefine_directive() {
   Endcelldefine_directiveContext *_localctx = _tracker.createInstance<Endcelldefine_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 94, SV3_1aPpParser::RuleEndcelldefine_directive);
+  enterRule(_localctx, 82, SV3_1aPpParser::RuleEndcelldefine_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(748);
+    setState(625);
     match(SV3_1aPpParser::TICK_ENDCELLDEFINE);
    
   }
@@ -4956,7 +4181,7 @@
 
 SV3_1aPpParser::Protect_directive_one_lineContext* SV3_1aPpParser::protect_directive_one_line() {
   Protect_directive_one_lineContext *_localctx = _tracker.createInstance<Protect_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 96, SV3_1aPpParser::RuleProtect_directive_one_line);
+  enterRule(_localctx, 84, SV3_1aPpParser::RuleProtect_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -4964,19 +4189,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(750);
+    setState(627);
     protect_directive();
-    setState(754);
+    setState(631);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(751);
+      setState(628);
       match(SV3_1aPpParser::Spaces);
-      setState(756);
+      setState(633);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(757);
+    setState(634);
     match(SV3_1aPpParser::CR);
    
   }
@@ -5018,14 +4243,14 @@
 
 SV3_1aPpParser::Protect_directiveContext* SV3_1aPpParser::protect_directive() {
   Protect_directiveContext *_localctx = _tracker.createInstance<Protect_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 98, SV3_1aPpParser::RuleProtect_directive);
+  enterRule(_localctx, 86, SV3_1aPpParser::RuleProtect_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(759);
+    setState(636);
     match(SV3_1aPpParser::TICK_PROTECT);
    
   }
@@ -5079,7 +4304,7 @@
 
 SV3_1aPpParser::Endprotect_directive_one_lineContext* SV3_1aPpParser::endprotect_directive_one_line() {
   Endprotect_directive_one_lineContext *_localctx = _tracker.createInstance<Endprotect_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 100, SV3_1aPpParser::RuleEndprotect_directive_one_line);
+  enterRule(_localctx, 88, SV3_1aPpParser::RuleEndprotect_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -5087,19 +4312,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(761);
+    setState(638);
     endprotect_directive();
-    setState(765);
+    setState(642);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(762);
+      setState(639);
       match(SV3_1aPpParser::Spaces);
-      setState(767);
+      setState(644);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(768);
+    setState(645);
     match(SV3_1aPpParser::CR);
    
   }
@@ -5141,14 +4366,14 @@
 
 SV3_1aPpParser::Endprotect_directiveContext* SV3_1aPpParser::endprotect_directive() {
   Endprotect_directiveContext *_localctx = _tracker.createInstance<Endprotect_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 102, SV3_1aPpParser::RuleEndprotect_directive);
+  enterRule(_localctx, 90, SV3_1aPpParser::RuleEndprotect_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(770);
+    setState(647);
     match(SV3_1aPpParser::TICK_ENDPROTECT);
    
   }
@@ -5202,7 +4427,7 @@
 
 SV3_1aPpParser::Protected_directive_one_lineContext* SV3_1aPpParser::protected_directive_one_line() {
   Protected_directive_one_lineContext *_localctx = _tracker.createInstance<Protected_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 104, SV3_1aPpParser::RuleProtected_directive_one_line);
+  enterRule(_localctx, 92, SV3_1aPpParser::RuleProtected_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -5210,19 +4435,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(772);
+    setState(649);
     protected_directive();
-    setState(776);
+    setState(653);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(773);
+      setState(650);
       match(SV3_1aPpParser::Spaces);
-      setState(778);
+      setState(655);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(779);
+    setState(656);
     match(SV3_1aPpParser::CR);
    
   }
@@ -5264,14 +4489,14 @@
 
 SV3_1aPpParser::Protected_directiveContext* SV3_1aPpParser::protected_directive() {
   Protected_directiveContext *_localctx = _tracker.createInstance<Protected_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 106, SV3_1aPpParser::RuleProtected_directive);
+  enterRule(_localctx, 94, SV3_1aPpParser::RuleProtected_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(781);
+    setState(658);
     match(SV3_1aPpParser::TICK_PROTECTED);
    
   }
@@ -5325,7 +4550,7 @@
 
 SV3_1aPpParser::Endprotected_directive_one_lineContext* SV3_1aPpParser::endprotected_directive_one_line() {
   Endprotected_directive_one_lineContext *_localctx = _tracker.createInstance<Endprotected_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 108, SV3_1aPpParser::RuleEndprotected_directive_one_line);
+  enterRule(_localctx, 96, SV3_1aPpParser::RuleEndprotected_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -5333,19 +4558,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(783);
+    setState(660);
     endprotected_directive();
-    setState(787);
+    setState(664);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(784);
+      setState(661);
       match(SV3_1aPpParser::Spaces);
-      setState(789);
+      setState(666);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(790);
+    setState(667);
     match(SV3_1aPpParser::CR);
    
   }
@@ -5387,14 +4612,14 @@
 
 SV3_1aPpParser::Endprotected_directiveContext* SV3_1aPpParser::endprotected_directive() {
   Endprotected_directiveContext *_localctx = _tracker.createInstance<Endprotected_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 110, SV3_1aPpParser::RuleEndprotected_directive);
+  enterRule(_localctx, 98, SV3_1aPpParser::RuleEndprotected_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(792);
+    setState(669);
     match(SV3_1aPpParser::TICK_ENDPROTECTED);
    
   }
@@ -5448,7 +4673,7 @@
 
 SV3_1aPpParser::Expand_vectornets_directive_one_lineContext* SV3_1aPpParser::expand_vectornets_directive_one_line() {
   Expand_vectornets_directive_one_lineContext *_localctx = _tracker.createInstance<Expand_vectornets_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 112, SV3_1aPpParser::RuleExpand_vectornets_directive_one_line);
+  enterRule(_localctx, 100, SV3_1aPpParser::RuleExpand_vectornets_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -5456,19 +4681,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(794);
+    setState(671);
     expand_vectornets_directive();
-    setState(798);
+    setState(675);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(795);
+      setState(672);
       match(SV3_1aPpParser::Spaces);
-      setState(800);
+      setState(677);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(801);
+    setState(678);
     match(SV3_1aPpParser::CR);
    
   }
@@ -5510,14 +4735,14 @@
 
 SV3_1aPpParser::Expand_vectornets_directiveContext* SV3_1aPpParser::expand_vectornets_directive() {
   Expand_vectornets_directiveContext *_localctx = _tracker.createInstance<Expand_vectornets_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 114, SV3_1aPpParser::RuleExpand_vectornets_directive);
+  enterRule(_localctx, 102, SV3_1aPpParser::RuleExpand_vectornets_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(803);
+    setState(680);
     match(SV3_1aPpParser::TICK_EXPAND_VECTORNETS);
    
   }
@@ -5571,7 +4796,7 @@
 
 SV3_1aPpParser::Noexpand_vectornets_directive_one_lineContext* SV3_1aPpParser::noexpand_vectornets_directive_one_line() {
   Noexpand_vectornets_directive_one_lineContext *_localctx = _tracker.createInstance<Noexpand_vectornets_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 116, SV3_1aPpParser::RuleNoexpand_vectornets_directive_one_line);
+  enterRule(_localctx, 104, SV3_1aPpParser::RuleNoexpand_vectornets_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -5579,19 +4804,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(805);
+    setState(682);
     noexpand_vectornets_directive();
-    setState(809);
+    setState(686);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(806);
+      setState(683);
       match(SV3_1aPpParser::Spaces);
-      setState(811);
+      setState(688);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(812);
+    setState(689);
     match(SV3_1aPpParser::CR);
    
   }
@@ -5633,14 +4858,14 @@
 
 SV3_1aPpParser::Noexpand_vectornets_directiveContext* SV3_1aPpParser::noexpand_vectornets_directive() {
   Noexpand_vectornets_directiveContext *_localctx = _tracker.createInstance<Noexpand_vectornets_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 118, SV3_1aPpParser::RuleNoexpand_vectornets_directive);
+  enterRule(_localctx, 106, SV3_1aPpParser::RuleNoexpand_vectornets_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(814);
+    setState(691);
     match(SV3_1aPpParser::TICK_NOEXPAND_VECTORNETS);
    
   }
@@ -5694,7 +4919,7 @@
 
 SV3_1aPpParser::Autoexpand_vectornets_directive_one_lineContext* SV3_1aPpParser::autoexpand_vectornets_directive_one_line() {
   Autoexpand_vectornets_directive_one_lineContext *_localctx = _tracker.createInstance<Autoexpand_vectornets_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 120, SV3_1aPpParser::RuleAutoexpand_vectornets_directive_one_line);
+  enterRule(_localctx, 108, SV3_1aPpParser::RuleAutoexpand_vectornets_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -5702,19 +4927,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(816);
+    setState(693);
     autoexpand_vectornets_directive();
-    setState(820);
+    setState(697);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(817);
+      setState(694);
       match(SV3_1aPpParser::Spaces);
-      setState(822);
+      setState(699);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(823);
+    setState(700);
     match(SV3_1aPpParser::CR);
    
   }
@@ -5756,14 +4981,14 @@
 
 SV3_1aPpParser::Autoexpand_vectornets_directiveContext* SV3_1aPpParser::autoexpand_vectornets_directive() {
   Autoexpand_vectornets_directiveContext *_localctx = _tracker.createInstance<Autoexpand_vectornets_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 122, SV3_1aPpParser::RuleAutoexpand_vectornets_directive);
+  enterRule(_localctx, 110, SV3_1aPpParser::RuleAutoexpand_vectornets_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(825);
+    setState(702);
     match(SV3_1aPpParser::TICK_AUTOEXPAND_VECTORNETS);
    
   }
@@ -5809,16 +5034,16 @@
 
 SV3_1aPpParser::Uselib_directive_one_lineContext* SV3_1aPpParser::uselib_directive_one_line() {
   Uselib_directive_one_lineContext *_localctx = _tracker.createInstance<Uselib_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 124, SV3_1aPpParser::RuleUselib_directive_one_line);
+  enterRule(_localctx, 112, SV3_1aPpParser::RuleUselib_directive_one_line);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(827);
+    setState(704);
     uselib_directive();
-    setState(828);
+    setState(705);
     match(SV3_1aPpParser::CR);
    
   }
@@ -5868,7 +5093,7 @@
 
 SV3_1aPpParser::Uselib_directiveContext* SV3_1aPpParser::uselib_directive() {
   Uselib_directiveContext *_localctx = _tracker.createInstance<Uselib_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 126, SV3_1aPpParser::RuleUselib_directive);
+  enterRule(_localctx, 114, SV3_1aPpParser::RuleUselib_directive);
 
   auto onExit = finally([=] {
     exitRule();
@@ -5876,15 +5101,15 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(830);
+    setState(707);
     match(SV3_1aPpParser::TICK_USELIB);
-    setState(832); 
+    setState(709); 
     _errHandler->sync(this);
     alt = 1;
     do {
       switch (alt) {
         case 1: {
-              setState(831);
+              setState(708);
               text_blob();
               break;
             }
@@ -5892,9 +5117,9 @@
       default:
         throw NoViableAltException(this);
       }
-      setState(834); 
+      setState(711); 
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 58, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 40, _ctx);
     } while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER);
    
   }
@@ -5948,7 +5173,7 @@
 
 SV3_1aPpParser::Disable_portfaults_directive_one_lineContext* SV3_1aPpParser::disable_portfaults_directive_one_line() {
   Disable_portfaults_directive_one_lineContext *_localctx = _tracker.createInstance<Disable_portfaults_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 128, SV3_1aPpParser::RuleDisable_portfaults_directive_one_line);
+  enterRule(_localctx, 116, SV3_1aPpParser::RuleDisable_portfaults_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -5956,19 +5181,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(836);
+    setState(713);
     disable_portfaults_directive();
-    setState(840);
+    setState(717);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(837);
+      setState(714);
       match(SV3_1aPpParser::Spaces);
-      setState(842);
+      setState(719);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(843);
+    setState(720);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6010,14 +5235,14 @@
 
 SV3_1aPpParser::Disable_portfaults_directiveContext* SV3_1aPpParser::disable_portfaults_directive() {
   Disable_portfaults_directiveContext *_localctx = _tracker.createInstance<Disable_portfaults_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 130, SV3_1aPpParser::RuleDisable_portfaults_directive);
+  enterRule(_localctx, 118, SV3_1aPpParser::RuleDisable_portfaults_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(845);
+    setState(722);
     match(SV3_1aPpParser::TICK_DISABLE_PORTFAULTS);
    
   }
@@ -6071,7 +5296,7 @@
 
 SV3_1aPpParser::Enable_portfaults_directive_one_lineContext* SV3_1aPpParser::enable_portfaults_directive_one_line() {
   Enable_portfaults_directive_one_lineContext *_localctx = _tracker.createInstance<Enable_portfaults_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 132, SV3_1aPpParser::RuleEnable_portfaults_directive_one_line);
+  enterRule(_localctx, 120, SV3_1aPpParser::RuleEnable_portfaults_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -6079,19 +5304,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(847);
+    setState(724);
     enable_portfaults_directive();
-    setState(851);
+    setState(728);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(848);
+      setState(725);
       match(SV3_1aPpParser::Spaces);
-      setState(853);
+      setState(730);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(854);
+    setState(731);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6133,14 +5358,14 @@
 
 SV3_1aPpParser::Enable_portfaults_directiveContext* SV3_1aPpParser::enable_portfaults_directive() {
   Enable_portfaults_directiveContext *_localctx = _tracker.createInstance<Enable_portfaults_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 134, SV3_1aPpParser::RuleEnable_portfaults_directive);
+  enterRule(_localctx, 122, SV3_1aPpParser::RuleEnable_portfaults_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(856);
+    setState(733);
     match(SV3_1aPpParser::TICK_ENABLE_PORTFAULTS);
    
   }
@@ -6194,7 +5419,7 @@
 
 SV3_1aPpParser::Nosuppress_faults_directive_one_lineContext* SV3_1aPpParser::nosuppress_faults_directive_one_line() {
   Nosuppress_faults_directive_one_lineContext *_localctx = _tracker.createInstance<Nosuppress_faults_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 136, SV3_1aPpParser::RuleNosuppress_faults_directive_one_line);
+  enterRule(_localctx, 124, SV3_1aPpParser::RuleNosuppress_faults_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -6202,19 +5427,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(858);
+    setState(735);
     nosuppress_faults_directive();
-    setState(862);
+    setState(739);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(859);
+      setState(736);
       match(SV3_1aPpParser::Spaces);
-      setState(864);
+      setState(741);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(865);
+    setState(742);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6256,14 +5481,14 @@
 
 SV3_1aPpParser::Nosuppress_faults_directiveContext* SV3_1aPpParser::nosuppress_faults_directive() {
   Nosuppress_faults_directiveContext *_localctx = _tracker.createInstance<Nosuppress_faults_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 138, SV3_1aPpParser::RuleNosuppress_faults_directive);
+  enterRule(_localctx, 126, SV3_1aPpParser::RuleNosuppress_faults_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(867);
+    setState(744);
     match(SV3_1aPpParser::TICK_NOSUPPRESS_FAULTS);
    
   }
@@ -6317,7 +5542,7 @@
 
 SV3_1aPpParser::Suppress_faults_directive_one_lineContext* SV3_1aPpParser::suppress_faults_directive_one_line() {
   Suppress_faults_directive_one_lineContext *_localctx = _tracker.createInstance<Suppress_faults_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 140, SV3_1aPpParser::RuleSuppress_faults_directive_one_line);
+  enterRule(_localctx, 128, SV3_1aPpParser::RuleSuppress_faults_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -6325,19 +5550,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(869);
+    setState(746);
     suppress_faults_directive();
-    setState(873);
+    setState(750);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(870);
+      setState(747);
       match(SV3_1aPpParser::Spaces);
-      setState(875);
+      setState(752);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(876);
+    setState(753);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6379,14 +5604,14 @@
 
 SV3_1aPpParser::Suppress_faults_directiveContext* SV3_1aPpParser::suppress_faults_directive() {
   Suppress_faults_directiveContext *_localctx = _tracker.createInstance<Suppress_faults_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 142, SV3_1aPpParser::RuleSuppress_faults_directive);
+  enterRule(_localctx, 130, SV3_1aPpParser::RuleSuppress_faults_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(878);
+    setState(755);
     match(SV3_1aPpParser::TICK_SUPPRESS_FAULTS);
    
   }
@@ -6440,7 +5665,7 @@
 
 SV3_1aPpParser::Signed_directive_one_lineContext* SV3_1aPpParser::signed_directive_one_line() {
   Signed_directive_one_lineContext *_localctx = _tracker.createInstance<Signed_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 144, SV3_1aPpParser::RuleSigned_directive_one_line);
+  enterRule(_localctx, 132, SV3_1aPpParser::RuleSigned_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -6448,19 +5673,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(880);
+    setState(757);
     signed_directive();
-    setState(884);
+    setState(761);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(881);
+      setState(758);
       match(SV3_1aPpParser::Spaces);
-      setState(886);
+      setState(763);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(887);
+    setState(764);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6502,14 +5727,14 @@
 
 SV3_1aPpParser::Signed_directiveContext* SV3_1aPpParser::signed_directive() {
   Signed_directiveContext *_localctx = _tracker.createInstance<Signed_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 146, SV3_1aPpParser::RuleSigned_directive);
+  enterRule(_localctx, 134, SV3_1aPpParser::RuleSigned_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(889);
+    setState(766);
     match(SV3_1aPpParser::TICK_SIGNED);
    
   }
@@ -6563,7 +5788,7 @@
 
 SV3_1aPpParser::Unsigned_directive_one_lineContext* SV3_1aPpParser::unsigned_directive_one_line() {
   Unsigned_directive_one_lineContext *_localctx = _tracker.createInstance<Unsigned_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 148, SV3_1aPpParser::RuleUnsigned_directive_one_line);
+  enterRule(_localctx, 136, SV3_1aPpParser::RuleUnsigned_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -6571,19 +5796,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(891);
+    setState(768);
     unsigned_directive();
-    setState(895);
+    setState(772);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(892);
+      setState(769);
       match(SV3_1aPpParser::Spaces);
-      setState(897);
+      setState(774);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(898);
+    setState(775);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6625,14 +5850,14 @@
 
 SV3_1aPpParser::Unsigned_directiveContext* SV3_1aPpParser::unsigned_directive() {
   Unsigned_directiveContext *_localctx = _tracker.createInstance<Unsigned_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 150, SV3_1aPpParser::RuleUnsigned_directive);
+  enterRule(_localctx, 138, SV3_1aPpParser::RuleUnsigned_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(900);
+    setState(777);
     match(SV3_1aPpParser::TICK_UNSIGNED);
    
   }
@@ -6686,7 +5911,7 @@
 
 SV3_1aPpParser::Remove_gatename_directive_one_lineContext* SV3_1aPpParser::remove_gatename_directive_one_line() {
   Remove_gatename_directive_one_lineContext *_localctx = _tracker.createInstance<Remove_gatename_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 152, SV3_1aPpParser::RuleRemove_gatename_directive_one_line);
+  enterRule(_localctx, 140, SV3_1aPpParser::RuleRemove_gatename_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -6694,19 +5919,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(902);
+    setState(779);
     remove_gatename_directive();
-    setState(906);
+    setState(783);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(903);
+      setState(780);
       match(SV3_1aPpParser::Spaces);
-      setState(908);
+      setState(785);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(909);
+    setState(786);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6748,14 +5973,14 @@
 
 SV3_1aPpParser::Remove_gatename_directiveContext* SV3_1aPpParser::remove_gatename_directive() {
   Remove_gatename_directiveContext *_localctx = _tracker.createInstance<Remove_gatename_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 154, SV3_1aPpParser::RuleRemove_gatename_directive);
+  enterRule(_localctx, 142, SV3_1aPpParser::RuleRemove_gatename_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(911);
+    setState(788);
     match(SV3_1aPpParser::TICK_REMOVE_GATENAME);
    
   }
@@ -6809,7 +6034,7 @@
 
 SV3_1aPpParser::Noremove_gatenames_directive_one_lineContext* SV3_1aPpParser::noremove_gatenames_directive_one_line() {
   Noremove_gatenames_directive_one_lineContext *_localctx = _tracker.createInstance<Noremove_gatenames_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 156, SV3_1aPpParser::RuleNoremove_gatenames_directive_one_line);
+  enterRule(_localctx, 144, SV3_1aPpParser::RuleNoremove_gatenames_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -6817,19 +6042,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(913);
+    setState(790);
     noremove_gatenames_directive();
-    setState(917);
+    setState(794);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(914);
+      setState(791);
       match(SV3_1aPpParser::Spaces);
-      setState(919);
+      setState(796);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(920);
+    setState(797);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6871,14 +6096,14 @@
 
 SV3_1aPpParser::Noremove_gatenames_directiveContext* SV3_1aPpParser::noremove_gatenames_directive() {
   Noremove_gatenames_directiveContext *_localctx = _tracker.createInstance<Noremove_gatenames_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 158, SV3_1aPpParser::RuleNoremove_gatenames_directive);
+  enterRule(_localctx, 146, SV3_1aPpParser::RuleNoremove_gatenames_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(922);
+    setState(799);
     match(SV3_1aPpParser::TICK_NOREMOVE_GATENAMES);
    
   }
@@ -6932,7 +6157,7 @@
 
 SV3_1aPpParser::Remove_netname_directive_one_lineContext* SV3_1aPpParser::remove_netname_directive_one_line() {
   Remove_netname_directive_one_lineContext *_localctx = _tracker.createInstance<Remove_netname_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 160, SV3_1aPpParser::RuleRemove_netname_directive_one_line);
+  enterRule(_localctx, 148, SV3_1aPpParser::RuleRemove_netname_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -6940,19 +6165,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(924);
+    setState(801);
     remove_netname_directive();
-    setState(928);
+    setState(805);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(925);
+      setState(802);
       match(SV3_1aPpParser::Spaces);
-      setState(930);
+      setState(807);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(931);
+    setState(808);
     match(SV3_1aPpParser::CR);
    
   }
@@ -6994,14 +6219,14 @@
 
 SV3_1aPpParser::Remove_netname_directiveContext* SV3_1aPpParser::remove_netname_directive() {
   Remove_netname_directiveContext *_localctx = _tracker.createInstance<Remove_netname_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 162, SV3_1aPpParser::RuleRemove_netname_directive);
+  enterRule(_localctx, 150, SV3_1aPpParser::RuleRemove_netname_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(933);
+    setState(810);
     match(SV3_1aPpParser::TICK_REMOVE_NETNAME);
    
   }
@@ -7055,7 +6280,7 @@
 
 SV3_1aPpParser::Noremove_netnames_directive_one_lineContext* SV3_1aPpParser::noremove_netnames_directive_one_line() {
   Noremove_netnames_directive_one_lineContext *_localctx = _tracker.createInstance<Noremove_netnames_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 164, SV3_1aPpParser::RuleNoremove_netnames_directive_one_line);
+  enterRule(_localctx, 152, SV3_1aPpParser::RuleNoremove_netnames_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -7063,19 +6288,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(935);
+    setState(812);
     noremove_netnames_directive();
-    setState(939);
+    setState(816);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(936);
+      setState(813);
       match(SV3_1aPpParser::Spaces);
-      setState(941);
+      setState(818);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(942);
+    setState(819);
     match(SV3_1aPpParser::CR);
    
   }
@@ -7117,14 +6342,14 @@
 
 SV3_1aPpParser::Noremove_netnames_directiveContext* SV3_1aPpParser::noremove_netnames_directive() {
   Noremove_netnames_directiveContext *_localctx = _tracker.createInstance<Noremove_netnames_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 166, SV3_1aPpParser::RuleNoremove_netnames_directive);
+  enterRule(_localctx, 154, SV3_1aPpParser::RuleNoremove_netnames_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(944);
+    setState(821);
     match(SV3_1aPpParser::TICK_NOREMOVE_NETNAMES);
    
   }
@@ -7178,7 +6403,7 @@
 
 SV3_1aPpParser::Accelerate_directive_one_lineContext* SV3_1aPpParser::accelerate_directive_one_line() {
   Accelerate_directive_one_lineContext *_localctx = _tracker.createInstance<Accelerate_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 168, SV3_1aPpParser::RuleAccelerate_directive_one_line);
+  enterRule(_localctx, 156, SV3_1aPpParser::RuleAccelerate_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -7186,19 +6411,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(946);
+    setState(823);
     accelerate_directive();
-    setState(950);
+    setState(827);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(947);
+      setState(824);
       match(SV3_1aPpParser::Spaces);
-      setState(952);
+      setState(829);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(953);
+    setState(830);
     match(SV3_1aPpParser::CR);
    
   }
@@ -7240,14 +6465,14 @@
 
 SV3_1aPpParser::Accelerate_directiveContext* SV3_1aPpParser::accelerate_directive() {
   Accelerate_directiveContext *_localctx = _tracker.createInstance<Accelerate_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 170, SV3_1aPpParser::RuleAccelerate_directive);
+  enterRule(_localctx, 158, SV3_1aPpParser::RuleAccelerate_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(955);
+    setState(832);
     match(SV3_1aPpParser::TICK_ACCELERATE);
    
   }
@@ -7301,7 +6526,7 @@
 
 SV3_1aPpParser::Noaccelerate_directive_one_lineContext* SV3_1aPpParser::noaccelerate_directive_one_line() {
   Noaccelerate_directive_one_lineContext *_localctx = _tracker.createInstance<Noaccelerate_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 172, SV3_1aPpParser::RuleNoaccelerate_directive_one_line);
+  enterRule(_localctx, 160, SV3_1aPpParser::RuleNoaccelerate_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -7309,19 +6534,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(957);
+    setState(834);
     noaccelerate_directive();
-    setState(961);
+    setState(838);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(958);
+      setState(835);
       match(SV3_1aPpParser::Spaces);
-      setState(963);
+      setState(840);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(964);
+    setState(841);
     match(SV3_1aPpParser::CR);
    
   }
@@ -7363,14 +6588,14 @@
 
 SV3_1aPpParser::Noaccelerate_directiveContext* SV3_1aPpParser::noaccelerate_directive() {
   Noaccelerate_directiveContext *_localctx = _tracker.createInstance<Noaccelerate_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 174, SV3_1aPpParser::RuleNoaccelerate_directive);
+  enterRule(_localctx, 162, SV3_1aPpParser::RuleNoaccelerate_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(966);
+    setState(843);
     match(SV3_1aPpParser::TICK_NOACCELERATE);
    
   }
@@ -7424,7 +6649,7 @@
 
 SV3_1aPpParser::Default_trireg_strenght_directive_one_lineContext* SV3_1aPpParser::default_trireg_strenght_directive_one_line() {
   Default_trireg_strenght_directive_one_lineContext *_localctx = _tracker.createInstance<Default_trireg_strenght_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 176, SV3_1aPpParser::RuleDefault_trireg_strenght_directive_one_line);
+  enterRule(_localctx, 164, SV3_1aPpParser::RuleDefault_trireg_strenght_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -7432,19 +6657,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(968);
+    setState(845);
     default_trireg_strenght_directive();
-    setState(972);
+    setState(849);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(969);
+      setState(846);
       match(SV3_1aPpParser::Spaces);
-      setState(974);
+      setState(851);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(975);
+    setState(852);
     match(SV3_1aPpParser::CR);
    
   }
@@ -7494,18 +6719,18 @@
 
 SV3_1aPpParser::Default_trireg_strenght_directiveContext* SV3_1aPpParser::default_trireg_strenght_directive() {
   Default_trireg_strenght_directiveContext *_localctx = _tracker.createInstance<Default_trireg_strenght_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 178, SV3_1aPpParser::RuleDefault_trireg_strenght_directive);
+  enterRule(_localctx, 166, SV3_1aPpParser::RuleDefault_trireg_strenght_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(977);
+    setState(854);
     match(SV3_1aPpParser::TICK_DEFAULT_TRIREG_STRENGTH);
-    setState(978);
+    setState(855);
     match(SV3_1aPpParser::Spaces);
-    setState(979);
+    setState(856);
     number();
    
   }
@@ -7559,7 +6784,7 @@
 
 SV3_1aPpParser::Default_decay_time_directive_one_lineContext* SV3_1aPpParser::default_decay_time_directive_one_line() {
   Default_decay_time_directive_one_lineContext *_localctx = _tracker.createInstance<Default_decay_time_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 180, SV3_1aPpParser::RuleDefault_decay_time_directive_one_line);
+  enterRule(_localctx, 168, SV3_1aPpParser::RuleDefault_decay_time_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -7567,19 +6792,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(981);
+    setState(858);
     default_decay_time_directive();
-    setState(985);
+    setState(862);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(982);
+      setState(859);
       match(SV3_1aPpParser::Spaces);
-      setState(987);
+      setState(864);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(988);
+    setState(865);
     match(SV3_1aPpParser::CR);
    
   }
@@ -7637,34 +6862,34 @@
 
 SV3_1aPpParser::Default_decay_time_directiveContext* SV3_1aPpParser::default_decay_time_directive() {
   Default_decay_time_directiveContext *_localctx = _tracker.createInstance<Default_decay_time_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 182, SV3_1aPpParser::RuleDefault_decay_time_directive);
+  enterRule(_localctx, 170, SV3_1aPpParser::RuleDefault_decay_time_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(990);
+    setState(867);
     match(SV3_1aPpParser::TICK_DEFAULT_DECAY_TIME);
-    setState(991);
+    setState(868);
     match(SV3_1aPpParser::Spaces);
-    setState(995);
+    setState(872);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Number: {
-        setState(992);
+        setState(869);
         number();
         break;
       }
 
       case SV3_1aPpParser::Simple_identifier: {
-        setState(993);
+        setState(870);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Fixed_point_number: {
-        setState(994);
+        setState(871);
         match(SV3_1aPpParser::Fixed_point_number);
         break;
       }
@@ -7724,7 +6949,7 @@
 
 SV3_1aPpParser::Unconnected_drive_directive_one_lineContext* SV3_1aPpParser::unconnected_drive_directive_one_line() {
   Unconnected_drive_directive_one_lineContext *_localctx = _tracker.createInstance<Unconnected_drive_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 184, SV3_1aPpParser::RuleUnconnected_drive_directive_one_line);
+  enterRule(_localctx, 172, SV3_1aPpParser::RuleUnconnected_drive_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -7732,19 +6957,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(997);
+    setState(874);
     unconnected_drive_directive();
-    setState(1001);
+    setState(878);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(998);
+      setState(875);
       match(SV3_1aPpParser::Spaces);
-      setState(1003);
+      setState(880);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1004);
+    setState(881);
     match(SV3_1aPpParser::CR);
    
   }
@@ -7794,18 +7019,18 @@
 
 SV3_1aPpParser::Unconnected_drive_directiveContext* SV3_1aPpParser::unconnected_drive_directive() {
   Unconnected_drive_directiveContext *_localctx = _tracker.createInstance<Unconnected_drive_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 186, SV3_1aPpParser::RuleUnconnected_drive_directive);
+  enterRule(_localctx, 174, SV3_1aPpParser::RuleUnconnected_drive_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1006);
+    setState(883);
     match(SV3_1aPpParser::TICK_UNCONNECTED_DRIVE);
-    setState(1007);
+    setState(884);
     match(SV3_1aPpParser::Spaces);
-    setState(1008);
+    setState(885);
     match(SV3_1aPpParser::Simple_identifier);
    
   }
@@ -7859,7 +7084,7 @@
 
 SV3_1aPpParser::Nounconnected_drive_directive_one_lineContext* SV3_1aPpParser::nounconnected_drive_directive_one_line() {
   Nounconnected_drive_directive_one_lineContext *_localctx = _tracker.createInstance<Nounconnected_drive_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 188, SV3_1aPpParser::RuleNounconnected_drive_directive_one_line);
+  enterRule(_localctx, 176, SV3_1aPpParser::RuleNounconnected_drive_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -7867,19 +7092,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1010);
+    setState(887);
     nounconnected_drive_directive();
-    setState(1014);
+    setState(891);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(1011);
+      setState(888);
       match(SV3_1aPpParser::Spaces);
-      setState(1016);
+      setState(893);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1017);
+    setState(894);
     match(SV3_1aPpParser::CR);
    
   }
@@ -7921,14 +7146,14 @@
 
 SV3_1aPpParser::Nounconnected_drive_directiveContext* SV3_1aPpParser::nounconnected_drive_directive() {
   Nounconnected_drive_directiveContext *_localctx = _tracker.createInstance<Nounconnected_drive_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 190, SV3_1aPpParser::RuleNounconnected_drive_directive);
+  enterRule(_localctx, 178, SV3_1aPpParser::RuleNounconnected_drive_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1019);
+    setState(896);
     match(SV3_1aPpParser::TICK_NOUNCONNECTED_DRIVE);
    
   }
@@ -7982,7 +7207,7 @@
 
 SV3_1aPpParser::Delay_mode_distributed_directive_one_lineContext* SV3_1aPpParser::delay_mode_distributed_directive_one_line() {
   Delay_mode_distributed_directive_one_lineContext *_localctx = _tracker.createInstance<Delay_mode_distributed_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 192, SV3_1aPpParser::RuleDelay_mode_distributed_directive_one_line);
+  enterRule(_localctx, 180, SV3_1aPpParser::RuleDelay_mode_distributed_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -7990,19 +7215,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1021);
+    setState(898);
     delay_mode_distributed_directive();
-    setState(1025);
+    setState(902);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(1022);
+      setState(899);
       match(SV3_1aPpParser::Spaces);
-      setState(1027);
+      setState(904);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1028);
+    setState(905);
     match(SV3_1aPpParser::CR);
    
   }
@@ -8044,14 +7269,14 @@
 
 SV3_1aPpParser::Delay_mode_distributed_directiveContext* SV3_1aPpParser::delay_mode_distributed_directive() {
   Delay_mode_distributed_directiveContext *_localctx = _tracker.createInstance<Delay_mode_distributed_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 194, SV3_1aPpParser::RuleDelay_mode_distributed_directive);
+  enterRule(_localctx, 182, SV3_1aPpParser::RuleDelay_mode_distributed_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1030);
+    setState(907);
     match(SV3_1aPpParser::TICK_DELAY_MODE_DISTRIBUTED);
    
   }
@@ -8105,7 +7330,7 @@
 
 SV3_1aPpParser::Delay_mode_path_directive_one_lineContext* SV3_1aPpParser::delay_mode_path_directive_one_line() {
   Delay_mode_path_directive_one_lineContext *_localctx = _tracker.createInstance<Delay_mode_path_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 196, SV3_1aPpParser::RuleDelay_mode_path_directive_one_line);
+  enterRule(_localctx, 184, SV3_1aPpParser::RuleDelay_mode_path_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -8113,19 +7338,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1032);
+    setState(909);
     delay_mode_path_directive();
-    setState(1036);
+    setState(913);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(1033);
+      setState(910);
       match(SV3_1aPpParser::Spaces);
-      setState(1038);
+      setState(915);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1039);
+    setState(916);
     match(SV3_1aPpParser::CR);
    
   }
@@ -8167,14 +7392,14 @@
 
 SV3_1aPpParser::Delay_mode_path_directiveContext* SV3_1aPpParser::delay_mode_path_directive() {
   Delay_mode_path_directiveContext *_localctx = _tracker.createInstance<Delay_mode_path_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 198, SV3_1aPpParser::RuleDelay_mode_path_directive);
+  enterRule(_localctx, 186, SV3_1aPpParser::RuleDelay_mode_path_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1041);
+    setState(918);
     match(SV3_1aPpParser::TICK_DELAY_MODE_PATH);
    
   }
@@ -8228,7 +7453,7 @@
 
 SV3_1aPpParser::Delay_mode_unit_directive_one_lineContext* SV3_1aPpParser::delay_mode_unit_directive_one_line() {
   Delay_mode_unit_directive_one_lineContext *_localctx = _tracker.createInstance<Delay_mode_unit_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 200, SV3_1aPpParser::RuleDelay_mode_unit_directive_one_line);
+  enterRule(_localctx, 188, SV3_1aPpParser::RuleDelay_mode_unit_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -8236,19 +7461,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1043);
+    setState(920);
     delay_mode_unit_directive();
-    setState(1047);
+    setState(924);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(1044);
+      setState(921);
       match(SV3_1aPpParser::Spaces);
-      setState(1049);
+      setState(926);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1050);
+    setState(927);
     match(SV3_1aPpParser::CR);
    
   }
@@ -8290,14 +7515,14 @@
 
 SV3_1aPpParser::Delay_mode_unit_directiveContext* SV3_1aPpParser::delay_mode_unit_directive() {
   Delay_mode_unit_directiveContext *_localctx = _tracker.createInstance<Delay_mode_unit_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 202, SV3_1aPpParser::RuleDelay_mode_unit_directive);
+  enterRule(_localctx, 190, SV3_1aPpParser::RuleDelay_mode_unit_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1052);
+    setState(929);
     match(SV3_1aPpParser::TICK_DELAY_MODE_UNIT);
    
   }
@@ -8351,7 +7576,7 @@
 
 SV3_1aPpParser::Delay_mode_zero_directive_one_lineContext* SV3_1aPpParser::delay_mode_zero_directive_one_line() {
   Delay_mode_zero_directive_one_lineContext *_localctx = _tracker.createInstance<Delay_mode_zero_directive_one_lineContext>(_ctx, getState());
-  enterRule(_localctx, 204, SV3_1aPpParser::RuleDelay_mode_zero_directive_one_line);
+  enterRule(_localctx, 192, SV3_1aPpParser::RuleDelay_mode_zero_directive_one_line);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -8359,19 +7584,19 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1054);
+    setState(931);
     delay_mode_zero_directive();
-    setState(1058);
+    setState(935);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(1055);
+      setState(932);
       match(SV3_1aPpParser::Spaces);
-      setState(1060);
+      setState(937);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1061);
+    setState(938);
     match(SV3_1aPpParser::CR);
    
   }
@@ -8413,14 +7638,14 @@
 
 SV3_1aPpParser::Delay_mode_zero_directiveContext* SV3_1aPpParser::delay_mode_zero_directive() {
   Delay_mode_zero_directiveContext *_localctx = _tracker.createInstance<Delay_mode_zero_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 206, SV3_1aPpParser::RuleDelay_mode_zero_directive);
+  enterRule(_localctx, 194, SV3_1aPpParser::RuleDelay_mode_zero_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1063);
+    setState(940);
     match(SV3_1aPpParser::TICK_DELAY_MODE_ZERO);
    
   }
@@ -8462,14 +7687,14 @@
 
 SV3_1aPpParser::Undefineall_directiveContext* SV3_1aPpParser::undefineall_directive() {
   Undefineall_directiveContext *_localctx = _tracker.createInstance<Undefineall_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 208, SV3_1aPpParser::RuleUndefineall_directive);
+  enterRule(_localctx, 196, SV3_1aPpParser::RuleUndefineall_directive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1065);
+    setState(942);
     match(SV3_1aPpParser::TICK_UNDEFINEALL);
    
   }
@@ -8511,14 +7736,14 @@
 
 SV3_1aPpParser::ModuleContext* SV3_1aPpParser::module() {
   ModuleContext *_localctx = _tracker.createInstance<ModuleContext>(_ctx, getState());
-  enterRule(_localctx, 210, SV3_1aPpParser::RuleModule);
+  enterRule(_localctx, 198, SV3_1aPpParser::RuleModule);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1067);
+    setState(944);
     match(SV3_1aPpParser::MODULE);
    
   }
@@ -8560,14 +7785,14 @@
 
 SV3_1aPpParser::EndmoduleContext* SV3_1aPpParser::endmodule() {
   EndmoduleContext *_localctx = _tracker.createInstance<EndmoduleContext>(_ctx, getState());
-  enterRule(_localctx, 212, SV3_1aPpParser::RuleEndmodule);
+  enterRule(_localctx, 200, SV3_1aPpParser::RuleEndmodule);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1069);
+    setState(946);
     match(SV3_1aPpParser::ENDMODULE);
    
   }
@@ -8609,14 +7834,14 @@
 
 SV3_1aPpParser::Sv_interfaceContext* SV3_1aPpParser::sv_interface() {
   Sv_interfaceContext *_localctx = _tracker.createInstance<Sv_interfaceContext>(_ctx, getState());
-  enterRule(_localctx, 214, SV3_1aPpParser::RuleSv_interface);
+  enterRule(_localctx, 202, SV3_1aPpParser::RuleSv_interface);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1071);
+    setState(948);
     match(SV3_1aPpParser::INTERFACE);
    
   }
@@ -8658,14 +7883,14 @@
 
 SV3_1aPpParser::EndinterfaceContext* SV3_1aPpParser::endinterface() {
   EndinterfaceContext *_localctx = _tracker.createInstance<EndinterfaceContext>(_ctx, getState());
-  enterRule(_localctx, 216, SV3_1aPpParser::RuleEndinterface);
+  enterRule(_localctx, 204, SV3_1aPpParser::RuleEndinterface);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1073);
+    setState(950);
     match(SV3_1aPpParser::ENDINTERFACE);
    
   }
@@ -8707,14 +7932,14 @@
 
 SV3_1aPpParser::ProgramContext* SV3_1aPpParser::program() {
   ProgramContext *_localctx = _tracker.createInstance<ProgramContext>(_ctx, getState());
-  enterRule(_localctx, 218, SV3_1aPpParser::RuleProgram);
+  enterRule(_localctx, 206, SV3_1aPpParser::RuleProgram);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1075);
+    setState(952);
     match(SV3_1aPpParser::PROGRAM);
    
   }
@@ -8756,14 +7981,14 @@
 
 SV3_1aPpParser::EndprogramContext* SV3_1aPpParser::endprogram() {
   EndprogramContext *_localctx = _tracker.createInstance<EndprogramContext>(_ctx, getState());
-  enterRule(_localctx, 220, SV3_1aPpParser::RuleEndprogram);
+  enterRule(_localctx, 208, SV3_1aPpParser::RuleEndprogram);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1077);
+    setState(954);
     match(SV3_1aPpParser::ENDPROGRAM);
    
   }
@@ -8805,14 +8030,14 @@
 
 SV3_1aPpParser::PrimitiveContext* SV3_1aPpParser::primitive() {
   PrimitiveContext *_localctx = _tracker.createInstance<PrimitiveContext>(_ctx, getState());
-  enterRule(_localctx, 222, SV3_1aPpParser::RulePrimitive);
+  enterRule(_localctx, 210, SV3_1aPpParser::RulePrimitive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1079);
+    setState(956);
     match(SV3_1aPpParser::PRIMITIVE);
    
   }
@@ -8854,14 +8079,14 @@
 
 SV3_1aPpParser::EndprimitiveContext* SV3_1aPpParser::endprimitive() {
   EndprimitiveContext *_localctx = _tracker.createInstance<EndprimitiveContext>(_ctx, getState());
-  enterRule(_localctx, 224, SV3_1aPpParser::RuleEndprimitive);
+  enterRule(_localctx, 212, SV3_1aPpParser::RuleEndprimitive);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1081);
+    setState(958);
     match(SV3_1aPpParser::ENDPRIMITIVE);
    
   }
@@ -8903,14 +8128,14 @@
 
 SV3_1aPpParser::Sv_packageContext* SV3_1aPpParser::sv_package() {
   Sv_packageContext *_localctx = _tracker.createInstance<Sv_packageContext>(_ctx, getState());
-  enterRule(_localctx, 226, SV3_1aPpParser::RuleSv_package);
+  enterRule(_localctx, 214, SV3_1aPpParser::RuleSv_package);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1083);
+    setState(960);
     match(SV3_1aPpParser::PACKAGE);
    
   }
@@ -8952,14 +8177,14 @@
 
 SV3_1aPpParser::EndpackageContext* SV3_1aPpParser::endpackage() {
   EndpackageContext *_localctx = _tracker.createInstance<EndpackageContext>(_ctx, getState());
-  enterRule(_localctx, 228, SV3_1aPpParser::RuleEndpackage);
+  enterRule(_localctx, 216, SV3_1aPpParser::RuleEndpackage);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1085);
+    setState(962);
     match(SV3_1aPpParser::ENDPACKAGE);
    
   }
@@ -9001,14 +8226,14 @@
 
 SV3_1aPpParser::CheckerContext* SV3_1aPpParser::checker() {
   CheckerContext *_localctx = _tracker.createInstance<CheckerContext>(_ctx, getState());
-  enterRule(_localctx, 230, SV3_1aPpParser::RuleChecker);
+  enterRule(_localctx, 218, SV3_1aPpParser::RuleChecker);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1087);
+    setState(964);
     match(SV3_1aPpParser::CHECKER);
    
   }
@@ -9050,14 +8275,14 @@
 
 SV3_1aPpParser::EndcheckerContext* SV3_1aPpParser::endchecker() {
   EndcheckerContext *_localctx = _tracker.createInstance<EndcheckerContext>(_ctx, getState());
-  enterRule(_localctx, 232, SV3_1aPpParser::RuleEndchecker);
+  enterRule(_localctx, 220, SV3_1aPpParser::RuleEndchecker);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1089);
+    setState(966);
     match(SV3_1aPpParser::ENDCHECKER);
    
   }
@@ -9099,14 +8324,14 @@
 
 SV3_1aPpParser::ConfigContext* SV3_1aPpParser::config() {
   ConfigContext *_localctx = _tracker.createInstance<ConfigContext>(_ctx, getState());
-  enterRule(_localctx, 234, SV3_1aPpParser::RuleConfig);
+  enterRule(_localctx, 222, SV3_1aPpParser::RuleConfig);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1091);
+    setState(968);
     match(SV3_1aPpParser::CONFIG);
    
   }
@@ -9148,14 +8373,14 @@
 
 SV3_1aPpParser::EndconfigContext* SV3_1aPpParser::endconfig() {
   EndconfigContext *_localctx = _tracker.createInstance<EndconfigContext>(_ctx, getState());
-  enterRule(_localctx, 236, SV3_1aPpParser::RuleEndconfig);
+  enterRule(_localctx, 224, SV3_1aPpParser::RuleEndconfig);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1093);
+    setState(970);
     match(SV3_1aPpParser::ENDCONFIG);
    
   }
@@ -9217,7 +8442,7 @@
 
 SV3_1aPpParser::Define_directiveContext* SV3_1aPpParser::define_directive() {
   Define_directiveContext *_localctx = _tracker.createInstance<Define_directiveContext>(_ctx, getState());
-  enterRule(_localctx, 238, SV3_1aPpParser::RuleDefine_directive);
+  enterRule(_localctx, 226, SV3_1aPpParser::RuleDefine_directive);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -9225,11 +8450,11 @@
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1095);
+    setState(972);
     match(SV3_1aPpParser::TICK_DEFINE);
-    setState(1096);
+    setState(973);
     match(SV3_1aPpParser::Spaces);
-    setState(1097);
+    setState(974);
     _la = _input->LA(1);
     if (!(_la == SV3_1aPpParser::Simple_identifier
 
@@ -9240,17 +8465,17 @@
       _errHandler->reportMatch(this);
       consume();
     }
-    setState(1101);
+    setState(978);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(1098);
+      setState(975);
       match(SV3_1aPpParser::Spaces);
-      setState(1103);
+      setState(980);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1104);
+    setState(981);
     match(SV3_1aPpParser::CR);
    
   }
@@ -9312,7 +8537,7 @@
 
 SV3_1aPpParser::Multiline_no_args_macro_definitionContext* SV3_1aPpParser::multiline_no_args_macro_definition() {
   Multiline_no_args_macro_definitionContext *_localctx = _tracker.createInstance<Multiline_no_args_macro_definitionContext>(_ctx, getState());
-  enterRule(_localctx, 240, SV3_1aPpParser::RuleMultiline_no_args_macro_definition);
+  enterRule(_localctx, 228, SV3_1aPpParser::RuleMultiline_no_args_macro_definition);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -9321,11 +8546,11 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(1106);
+    setState(983);
     match(SV3_1aPpParser::TICK_DEFINE);
-    setState(1107);
+    setState(984);
     match(SV3_1aPpParser::Spaces);
-    setState(1108);
+    setState(985);
     _la = _input->LA(1);
     if (!(_la == SV3_1aPpParser::Simple_identifier
 
@@ -9336,19 +8561,19 @@
       _errHandler->reportMatch(this);
       consume();
     }
-    setState(1112);
+    setState(989);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 81, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 63, _ctx);
     while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1) {
-        setState(1109);
+        setState(986);
         match(SV3_1aPpParser::Spaces); 
       }
-      setState(1114);
+      setState(991);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 81, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 63, _ctx);
     }
-    setState(1115);
+    setState(992);
     escaped_macro_definition_body();
    
   }
@@ -9414,7 +8639,7 @@
 
 SV3_1aPpParser::Multiline_args_macro_definitionContext* SV3_1aPpParser::multiline_args_macro_definition() {
   Multiline_args_macro_definitionContext *_localctx = _tracker.createInstance<Multiline_args_macro_definitionContext>(_ctx, getState());
-  enterRule(_localctx, 242, SV3_1aPpParser::RuleMultiline_args_macro_definition);
+  enterRule(_localctx, 230, SV3_1aPpParser::RuleMultiline_args_macro_definition);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -9423,11 +8648,11 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(1117);
+    setState(994);
     match(SV3_1aPpParser::TICK_DEFINE);
-    setState(1118);
+    setState(995);
     match(SV3_1aPpParser::Spaces);
-    setState(1119);
+    setState(996);
     _la = _input->LA(1);
     if (!(_la == SV3_1aPpParser::Simple_identifier
 
@@ -9438,21 +8663,21 @@
       _errHandler->reportMatch(this);
       consume();
     }
-    setState(1120);
+    setState(997);
     macro_arguments();
-    setState(1124);
+    setState(1001);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 82, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 64, _ctx);
     while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1) {
-        setState(1121);
+        setState(998);
         match(SV3_1aPpParser::Spaces); 
       }
-      setState(1126);
+      setState(1003);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 82, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 64, _ctx);
     }
-    setState(1127);
+    setState(1004);
     escaped_macro_definition_body();
    
   }
@@ -9522,23 +8747,23 @@
 
 SV3_1aPpParser::Simple_no_args_macro_definitionContext* SV3_1aPpParser::simple_no_args_macro_definition() {
   Simple_no_args_macro_definitionContext *_localctx = _tracker.createInstance<Simple_no_args_macro_definitionContext>(_ctx, getState());
-  enterRule(_localctx, 244, SV3_1aPpParser::RuleSimple_no_args_macro_definition);
+  enterRule(_localctx, 232, SV3_1aPpParser::RuleSimple_no_args_macro_definition);
   size_t _la = 0;
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1146);
+    setState(1023);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 84, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 66, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(1129);
+      setState(1006);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1130);
+      setState(1007);
       match(SV3_1aPpParser::Spaces);
-      setState(1131);
+      setState(1008);
       _la = _input->LA(1);
       if (!(_la == SV3_1aPpParser::Simple_identifier
 
@@ -9549,11 +8774,11 @@
         _errHandler->reportMatch(this);
         consume();
       }
-      setState(1132);
+      setState(1009);
       match(SV3_1aPpParser::Spaces);
-      setState(1133);
+      setState(1010);
       simple_macro_definition_body();
-      setState(1134);
+      setState(1011);
       _la = _input->LA(1);
       if (!(_la == SV3_1aPpParser::One_line_comment || _la == SV3_1aPpParser::CR)) {
       _errHandler->recoverInline(this);
@@ -9567,11 +8792,11 @@
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(1136);
+      setState(1013);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1137);
+      setState(1014);
       match(SV3_1aPpParser::Spaces);
-      setState(1138);
+      setState(1015);
       _la = _input->LA(1);
       if (!(_la == SV3_1aPpParser::Simple_identifier
 
@@ -9582,17 +8807,17 @@
         _errHandler->reportMatch(this);
         consume();
       }
-      setState(1142);
+      setState(1019);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while (_la == SV3_1aPpParser::Spaces) {
-        setState(1139);
+        setState(1016);
         match(SV3_1aPpParser::Spaces);
-        setState(1144);
+        setState(1021);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(1145);
+      setState(1022);
       match(SV3_1aPpParser::CR);
       break;
     }
@@ -9670,23 +8895,23 @@
 
 SV3_1aPpParser::Simple_args_macro_definitionContext* SV3_1aPpParser::simple_args_macro_definition() {
   Simple_args_macro_definitionContext *_localctx = _tracker.createInstance<Simple_args_macro_definitionContext>(_ctx, getState());
-  enterRule(_localctx, 246, SV3_1aPpParser::RuleSimple_args_macro_definition);
+  enterRule(_localctx, 234, SV3_1aPpParser::RuleSimple_args_macro_definition);
   size_t _la = 0;
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1168);
+    setState(1045);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 86, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 68, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(1148);
+      setState(1025);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1149);
+      setState(1026);
       match(SV3_1aPpParser::Spaces);
-      setState(1150);
+      setState(1027);
       _la = _input->LA(1);
       if (!(_la == SV3_1aPpParser::Simple_identifier
 
@@ -9697,13 +8922,13 @@
         _errHandler->reportMatch(this);
         consume();
       }
-      setState(1151);
+      setState(1028);
       macro_arguments();
-      setState(1152);
+      setState(1029);
       match(SV3_1aPpParser::Spaces);
-      setState(1153);
+      setState(1030);
       simple_macro_definition_body();
-      setState(1154);
+      setState(1031);
       _la = _input->LA(1);
       if (!(_la == SV3_1aPpParser::One_line_comment || _la == SV3_1aPpParser::CR)) {
       _errHandler->recoverInline(this);
@@ -9717,11 +8942,11 @@
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(1156);
+      setState(1033);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1157);
+      setState(1034);
       match(SV3_1aPpParser::Spaces);
-      setState(1158);
+      setState(1035);
       _la = _input->LA(1);
       if (!(_la == SV3_1aPpParser::Simple_identifier
 
@@ -9732,19 +8957,19 @@
         _errHandler->reportMatch(this);
         consume();
       }
-      setState(1159);
+      setState(1036);
       macro_arguments();
-      setState(1163);
+      setState(1040);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while (_la == SV3_1aPpParser::Spaces) {
-        setState(1160);
+        setState(1037);
         match(SV3_1aPpParser::Spaces);
-        setState(1165);
+        setState(1042);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(1166);
+      setState(1043);
       match(SV3_1aPpParser::CR);
       break;
     }
@@ -9802,7 +9027,7 @@
 
 SV3_1aPpParser::Identifier_in_macro_bodyContext* SV3_1aPpParser::identifier_in_macro_body() {
   Identifier_in_macro_bodyContext *_localctx = _tracker.createInstance<Identifier_in_macro_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 248, SV3_1aPpParser::RuleIdentifier_in_macro_body);
+  enterRule(_localctx, 236, SV3_1aPpParser::RuleIdentifier_in_macro_body);
 
   auto onExit = finally([=] {
     exitRule();
@@ -9810,28 +9035,28 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(1176);
+    setState(1053);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 88, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 70, _ctx);
     while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1) {
-        setState(1170);
+        setState(1047);
         match(SV3_1aPpParser::Simple_identifier);
-        setState(1172);
+        setState(1049);
         _errHandler->sync(this);
 
-        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 87, _ctx)) {
+        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 69, _ctx)) {
         case 1: {
-          setState(1171);
+          setState(1048);
           match(SV3_1aPpParser::TICK_TICK);
           break;
         }
 
         } 
       }
-      setState(1178);
+      setState(1055);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 88, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 70, _ctx);
     }
    
   }
@@ -9897,34 +9122,34 @@
 
 SV3_1aPpParser::Simple_no_args_macro_definition_in_macro_bodyContext* SV3_1aPpParser::simple_no_args_macro_definition_in_macro_body() {
   Simple_no_args_macro_definition_in_macro_bodyContext *_localctx = _tracker.createInstance<Simple_no_args_macro_definition_in_macro_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 250, SV3_1aPpParser::RuleSimple_no_args_macro_definition_in_macro_body);
+  enterRule(_localctx, 238, SV3_1aPpParser::RuleSimple_no_args_macro_definition_in_macro_body);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     size_t alt;
-    setState(1207);
+    setState(1084);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 93, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 75, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(1179);
+      setState(1056);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1180);
+      setState(1057);
       match(SV3_1aPpParser::Spaces);
-      setState(1183);
+      setState(1060);
       _errHandler->sync(this);
       switch (_input->LA(1)) {
         case SV3_1aPpParser::Simple_identifier:
         case SV3_1aPpParser::Spaces: {
-          setState(1181);
+          setState(1058);
           identifier_in_macro_body();
           break;
         }
 
         case SV3_1aPpParser::Escaped_identifier: {
-          setState(1182);
+          setState(1059);
           match(SV3_1aPpParser::Escaped_identifier);
           break;
         }
@@ -9932,68 +9157,68 @@
       default:
         throw NoViableAltException(this);
       }
-      setState(1185);
+      setState(1062);
       match(SV3_1aPpParser::Spaces);
-      setState(1186);
+      setState(1063);
       simple_macro_definition_body_in_macro_body();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(1187);
+      setState(1064);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1188);
+      setState(1065);
       match(SV3_1aPpParser::Spaces);
-      setState(1191);
+      setState(1068);
       _errHandler->sync(this);
-      switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 90, _ctx)) {
+      switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 72, _ctx)) {
       case 1: {
-        setState(1189);
+        setState(1066);
         identifier_in_macro_body();
         break;
       }
 
       case 2: {
-        setState(1190);
+        setState(1067);
         match(SV3_1aPpParser::Escaped_identifier);
         break;
       }
 
       }
-      setState(1196);
+      setState(1073);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 91, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 73, _ctx);
       while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
         if (alt == 1) {
-          setState(1193);
+          setState(1070);
           match(SV3_1aPpParser::Spaces); 
         }
-        setState(1198);
+        setState(1075);
         _errHandler->sync(this);
-        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 91, _ctx);
+        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 73, _ctx);
       }
       break;
     }
 
     case 3: {
       enterOuterAlt(_localctx, 3);
-      setState(1199);
+      setState(1076);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1200);
+      setState(1077);
       match(SV3_1aPpParser::Spaces);
-      setState(1203);
+      setState(1080);
       _errHandler->sync(this);
       switch (_input->LA(1)) {
         case SV3_1aPpParser::TICK_VARIABLE:
         case SV3_1aPpParser::Simple_identifier: {
-          setState(1201);
+          setState(1078);
           identifier_in_macro_body();
           break;
         }
 
         case SV3_1aPpParser::Escaped_identifier: {
-          setState(1202);
+          setState(1079);
           match(SV3_1aPpParser::Escaped_identifier);
           break;
         }
@@ -10001,9 +9226,9 @@
       default:
         throw NoViableAltException(this);
       }
-      setState(1205);
+      setState(1082);
       match(SV3_1aPpParser::TICK_VARIABLE);
-      setState(1206);
+      setState(1083);
       simple_macro_definition_body_in_macro_body();
       break;
     }
@@ -10073,33 +9298,33 @@
 
 SV3_1aPpParser::Simple_args_macro_definition_in_macro_bodyContext* SV3_1aPpParser::simple_args_macro_definition_in_macro_body() {
   Simple_args_macro_definition_in_macro_bodyContext *_localctx = _tracker.createInstance<Simple_args_macro_definition_in_macro_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 252, SV3_1aPpParser::RuleSimple_args_macro_definition_in_macro_body);
+  enterRule(_localctx, 240, SV3_1aPpParser::RuleSimple_args_macro_definition_in_macro_body);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1226);
+    setState(1103);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 96, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 78, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(1209);
+      setState(1086);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1210);
+      setState(1087);
       match(SV3_1aPpParser::Spaces);
-      setState(1213);
+      setState(1090);
       _errHandler->sync(this);
       switch (_input->LA(1)) {
         case SV3_1aPpParser::Simple_identifier:
         case SV3_1aPpParser::PARENS_OPEN: {
-          setState(1211);
+          setState(1088);
           identifier_in_macro_body();
           break;
         }
 
         case SV3_1aPpParser::Escaped_identifier: {
-          setState(1212);
+          setState(1089);
           match(SV3_1aPpParser::Escaped_identifier);
           break;
         }
@@ -10107,33 +9332,33 @@
       default:
         throw NoViableAltException(this);
       }
-      setState(1215);
+      setState(1092);
       macro_arguments();
-      setState(1216);
+      setState(1093);
       match(SV3_1aPpParser::Spaces);
-      setState(1217);
+      setState(1094);
       simple_macro_definition_body_in_macro_body();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(1219);
+      setState(1096);
       match(SV3_1aPpParser::TICK_DEFINE);
-      setState(1220);
+      setState(1097);
       match(SV3_1aPpParser::Spaces);
-      setState(1223);
+      setState(1100);
       _errHandler->sync(this);
       switch (_input->LA(1)) {
         case SV3_1aPpParser::Simple_identifier:
         case SV3_1aPpParser::PARENS_OPEN: {
-          setState(1221);
+          setState(1098);
           identifier_in_macro_body();
           break;
         }
 
         case SV3_1aPpParser::Escaped_identifier: {
-          setState(1222);
+          setState(1099);
           match(SV3_1aPpParser::Escaped_identifier);
           break;
         }
@@ -10141,7 +9366,7 @@
       default:
         throw NoViableAltException(this);
       }
-      setState(1225);
+      setState(1102);
       macro_arguments();
       break;
     }
@@ -10431,445 +9656,445 @@
 
 SV3_1aPpParser::Directive_in_macroContext* SV3_1aPpParser::directive_in_macro() {
   Directive_in_macroContext *_localctx = _tracker.createInstance<Directive_in_macroContext>(_ctx, getState());
-  enterRule(_localctx, 254, SV3_1aPpParser::RuleDirective_in_macro);
+  enterRule(_localctx, 242, SV3_1aPpParser::RuleDirective_in_macro);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1290);
+    setState(1167);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 97, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 79, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(1228);
+      setState(1105);
       celldefine_directive();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(1229);
+      setState(1106);
       endcelldefine_directive();
       break;
     }
 
     case 3: {
       enterOuterAlt(_localctx, 3);
-      setState(1230);
+      setState(1107);
       default_nettype_directive();
       break;
     }
 
     case 4: {
       enterOuterAlt(_localctx, 4);
-      setState(1231);
+      setState(1108);
       undef_directive();
       break;
     }
 
     case 5: {
       enterOuterAlt(_localctx, 5);
-      setState(1232);
+      setState(1109);
       ifdef_directive();
       break;
     }
 
     case 6: {
       enterOuterAlt(_localctx, 6);
-      setState(1233);
+      setState(1110);
       ifndef_directive();
       break;
     }
 
     case 7: {
       enterOuterAlt(_localctx, 7);
-      setState(1234);
+      setState(1111);
       else_directive();
       break;
     }
 
     case 8: {
       enterOuterAlt(_localctx, 8);
-      setState(1235);
+      setState(1112);
       elsif_directive();
       break;
     }
 
     case 9: {
       enterOuterAlt(_localctx, 9);
-      setState(1236);
+      setState(1113);
       elseif_directive();
       break;
     }
 
     case 10: {
       enterOuterAlt(_localctx, 10);
-      setState(1237);
+      setState(1114);
       endif_directive();
       break;
     }
 
     case 11: {
       enterOuterAlt(_localctx, 11);
-      setState(1238);
+      setState(1115);
       include_directive();
       break;
     }
 
     case 12: {
       enterOuterAlt(_localctx, 12);
-      setState(1239);
+      setState(1116);
       resetall_directive();
       break;
     }
 
     case 13: {
       enterOuterAlt(_localctx, 13);
-      setState(1240);
+      setState(1117);
       timescale_directive();
       break;
     }
 
     case 14: {
       enterOuterAlt(_localctx, 14);
-      setState(1241);
+      setState(1118);
       unconnected_drive_directive();
       break;
     }
 
     case 15: {
       enterOuterAlt(_localctx, 15);
-      setState(1242);
+      setState(1119);
       nounconnected_drive_directive();
       break;
     }
 
     case 16: {
       enterOuterAlt(_localctx, 16);
-      setState(1243);
+      setState(1120);
       line_directive();
       break;
     }
 
     case 17: {
       enterOuterAlt(_localctx, 17);
-      setState(1244);
+      setState(1121);
       default_decay_time_directive();
       break;
     }
 
     case 18: {
       enterOuterAlt(_localctx, 18);
-      setState(1245);
+      setState(1122);
       default_trireg_strenght_directive();
       break;
     }
 
     case 19: {
       enterOuterAlt(_localctx, 19);
-      setState(1246);
+      setState(1123);
       delay_mode_distributed_directive();
       break;
     }
 
     case 20: {
       enterOuterAlt(_localctx, 20);
-      setState(1247);
+      setState(1124);
       delay_mode_path_directive();
       break;
     }
 
     case 21: {
       enterOuterAlt(_localctx, 21);
-      setState(1248);
+      setState(1125);
       delay_mode_unit_directive();
       break;
     }
 
     case 22: {
       enterOuterAlt(_localctx, 22);
-      setState(1249);
+      setState(1126);
       delay_mode_zero_directive();
       break;
     }
 
     case 23: {
       enterOuterAlt(_localctx, 23);
-      setState(1250);
+      setState(1127);
       protect_directive();
       break;
     }
 
     case 24: {
       enterOuterAlt(_localctx, 24);
-      setState(1251);
+      setState(1128);
       endprotect_directive();
       break;
     }
 
     case 25: {
       enterOuterAlt(_localctx, 25);
-      setState(1252);
+      setState(1129);
       protected_directive();
       break;
     }
 
     case 26: {
       enterOuterAlt(_localctx, 26);
-      setState(1253);
+      setState(1130);
       endprotected_directive();
       break;
     }
 
     case 27: {
       enterOuterAlt(_localctx, 27);
-      setState(1254);
+      setState(1131);
       expand_vectornets_directive();
       break;
     }
 
     case 28: {
       enterOuterAlt(_localctx, 28);
-      setState(1255);
+      setState(1132);
       noexpand_vectornets_directive();
       break;
     }
 
     case 29: {
       enterOuterAlt(_localctx, 29);
-      setState(1256);
+      setState(1133);
       autoexpand_vectornets_directive();
       break;
     }
 
     case 30: {
       enterOuterAlt(_localctx, 30);
-      setState(1257);
+      setState(1134);
       remove_gatename_directive();
       break;
     }
 
     case 31: {
       enterOuterAlt(_localctx, 31);
-      setState(1258);
+      setState(1135);
       noremove_gatenames_directive();
       break;
     }
 
     case 32: {
       enterOuterAlt(_localctx, 32);
-      setState(1259);
+      setState(1136);
       remove_netname_directive();
       break;
     }
 
     case 33: {
       enterOuterAlt(_localctx, 33);
-      setState(1260);
+      setState(1137);
       noremove_netnames_directive();
       break;
     }
 
     case 34: {
       enterOuterAlt(_localctx, 34);
-      setState(1261);
+      setState(1138);
       accelerate_directive();
       break;
     }
 
     case 35: {
       enterOuterAlt(_localctx, 35);
-      setState(1262);
+      setState(1139);
       noaccelerate_directive();
       break;
     }
 
     case 36: {
       enterOuterAlt(_localctx, 36);
-      setState(1263);
+      setState(1140);
       undefineall_directive();
       break;
     }
 
     case 37: {
       enterOuterAlt(_localctx, 37);
-      setState(1264);
+      setState(1141);
       uselib_directive();
       break;
     }
 
     case 38: {
       enterOuterAlt(_localctx, 38);
-      setState(1265);
+      setState(1142);
       disable_portfaults_directive();
       break;
     }
 
     case 39: {
       enterOuterAlt(_localctx, 39);
-      setState(1266);
+      setState(1143);
       enable_portfaults_directive();
       break;
     }
 
     case 40: {
       enterOuterAlt(_localctx, 40);
-      setState(1267);
+      setState(1144);
       nosuppress_faults_directive();
       break;
     }
 
     case 41: {
       enterOuterAlt(_localctx, 41);
-      setState(1268);
+      setState(1145);
       suppress_faults_directive();
       break;
     }
 
     case 42: {
       enterOuterAlt(_localctx, 42);
-      setState(1269);
+      setState(1146);
       signed_directive();
       break;
     }
 
     case 43: {
       enterOuterAlt(_localctx, 43);
-      setState(1270);
+      setState(1147);
       unsigned_directive();
       break;
     }
 
     case 44: {
       enterOuterAlt(_localctx, 44);
-      setState(1271);
+      setState(1148);
       sv_file_directive();
       break;
     }
 
     case 45: {
       enterOuterAlt(_localctx, 45);
-      setState(1272);
+      setState(1149);
       sv_line_directive();
       break;
     }
 
     case 46: {
       enterOuterAlt(_localctx, 46);
-      setState(1273);
+      setState(1150);
       sv_package();
       break;
     }
 
     case 47: {
       enterOuterAlt(_localctx, 47);
-      setState(1274);
+      setState(1151);
       endpackage();
       break;
     }
 
     case 48: {
       enterOuterAlt(_localctx, 48);
-      setState(1275);
+      setState(1152);
       module();
       break;
     }
 
     case 49: {
       enterOuterAlt(_localctx, 49);
-      setState(1276);
+      setState(1153);
       endmodule();
       break;
     }
 
     case 50: {
       enterOuterAlt(_localctx, 50);
-      setState(1277);
+      setState(1154);
       sv_interface();
       break;
     }
 
     case 51: {
       enterOuterAlt(_localctx, 51);
-      setState(1278);
+      setState(1155);
       endinterface();
       break;
     }
 
     case 52: {
       enterOuterAlt(_localctx, 52);
-      setState(1279);
+      setState(1156);
       program();
       break;
     }
 
     case 53: {
       enterOuterAlt(_localctx, 53);
-      setState(1280);
+      setState(1157);
       endprogram();
       break;
     }
 
     case 54: {
       enterOuterAlt(_localctx, 54);
-      setState(1281);
+      setState(1158);
       primitive();
       break;
     }
 
     case 55: {
       enterOuterAlt(_localctx, 55);
-      setState(1282);
+      setState(1159);
       endprimitive();
       break;
     }
 
     case 56: {
       enterOuterAlt(_localctx, 56);
-      setState(1283);
+      setState(1160);
       checker();
       break;
     }
 
     case 57: {
       enterOuterAlt(_localctx, 57);
-      setState(1284);
+      setState(1161);
       endchecker();
       break;
     }
 
     case 58: {
       enterOuterAlt(_localctx, 58);
-      setState(1285);
+      setState(1162);
       config();
       break;
     }
 
     case 59: {
       enterOuterAlt(_localctx, 59);
-      setState(1286);
+      setState(1163);
       endconfig();
       break;
     }
 
     case 60: {
       enterOuterAlt(_localctx, 60);
-      setState(1287);
+      setState(1164);
       simple_args_macro_definition_in_macro_body();
       break;
     }
 
     case 61: {
       enterOuterAlt(_localctx, 61);
-      setState(1288);
+      setState(1165);
       simple_no_args_macro_definition_in_macro_body();
       break;
     }
 
     case 62: {
       enterOuterAlt(_localctx, 62);
-      setState(1289);
+      setState(1166);
       pound_delay();
       break;
     }
@@ -10959,7 +10184,7 @@
 
 SV3_1aPpParser::Macro_argumentsContext* SV3_1aPpParser::macro_arguments() {
   Macro_argumentsContext *_localctx = _tracker.createInstance<Macro_argumentsContext>(_ctx, getState());
-  enterRule(_localctx, 256, SV3_1aPpParser::RuleMacro_arguments);
+  enterRule(_localctx, 244, SV3_1aPpParser::RuleMacro_arguments);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -10968,106 +10193,106 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(1292);
+    setState(1169);
     match(SV3_1aPpParser::PARENS_OPEN);
-    setState(1345);
+    setState(1222);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Simple_identifier) {
-      setState(1293);
+      setState(1170);
       match(SV3_1aPpParser::Simple_identifier);
-      setState(1297);
+      setState(1174);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while (_la == SV3_1aPpParser::Spaces) {
-        setState(1294);
+        setState(1171);
         match(SV3_1aPpParser::Spaces);
-        setState(1299);
+        setState(1176);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(1309);
+      setState(1186);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while (_la == SV3_1aPpParser::EQUAL_OP) {
-        setState(1300);
+        setState(1177);
         match(SV3_1aPpParser::EQUAL_OP);
-        setState(1304);
+        setState(1181);
         _errHandler->sync(this);
-        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 99, _ctx);
+        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 81, _ctx);
         while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
           if (alt == 1) {
-            setState(1301);
+            setState(1178);
             default_value(); 
           }
-          setState(1306);
+          setState(1183);
           _errHandler->sync(this);
-          alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 99, _ctx);
+          alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 81, _ctx);
         }
-        setState(1311);
+        setState(1188);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(1340);
+      setState(1217);
       _errHandler->sync(this);
       _la = _input->LA(1);
       while (_la == SV3_1aPpParser::COMMA) {
-        setState(1312);
+        setState(1189);
         match(SV3_1aPpParser::COMMA);
-        setState(1316);
+        setState(1193);
         _errHandler->sync(this);
         _la = _input->LA(1);
         while (_la == SV3_1aPpParser::Spaces) {
-          setState(1313);
+          setState(1190);
           match(SV3_1aPpParser::Spaces);
-          setState(1318);
+          setState(1195);
           _errHandler->sync(this);
           _la = _input->LA(1);
         }
 
-        setState(1319);
+        setState(1196);
         match(SV3_1aPpParser::Simple_identifier);
-        setState(1323);
+        setState(1200);
         _errHandler->sync(this);
         _la = _input->LA(1);
         while (_la == SV3_1aPpParser::Spaces) {
-          setState(1320);
+          setState(1197);
           match(SV3_1aPpParser::Spaces);
-          setState(1325);
+          setState(1202);
           _errHandler->sync(this);
           _la = _input->LA(1);
         }
-        setState(1335);
+        setState(1212);
         _errHandler->sync(this);
         _la = _input->LA(1);
         while (_la == SV3_1aPpParser::EQUAL_OP) {
-          setState(1326);
+          setState(1203);
           match(SV3_1aPpParser::EQUAL_OP);
-          setState(1330);
+          setState(1207);
           _errHandler->sync(this);
-          alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 103, _ctx);
+          alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 85, _ctx);
           while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
             if (alt == 1) {
-              setState(1327);
+              setState(1204);
               default_value(); 
             }
-            setState(1332);
+            setState(1209);
             _errHandler->sync(this);
-            alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 103, _ctx);
+            alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 85, _ctx);
           }
-          setState(1337);
+          setState(1214);
           _errHandler->sync(this);
           _la = _input->LA(1);
         }
-        setState(1342);
+        setState(1219);
         _errHandler->sync(this);
         _la = _input->LA(1);
       }
-      setState(1347);
+      setState(1224);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1348);
+    setState(1225);
     match(SV3_1aPpParser::PARENS_CLOSE);
    
   }
@@ -11113,25 +10338,25 @@
 
 SV3_1aPpParser::Escaped_macro_definition_bodyContext* SV3_1aPpParser::escaped_macro_definition_body() {
   Escaped_macro_definition_bodyContext *_localctx = _tracker.createInstance<Escaped_macro_definition_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 258, SV3_1aPpParser::RuleEscaped_macro_definition_body);
+  enterRule(_localctx, 246, SV3_1aPpParser::RuleEscaped_macro_definition_body);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1352);
+    setState(1229);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 107, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 89, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(1350);
+      setState(1227);
       escaped_macro_definition_body_alt1();
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(1351);
+      setState(1228);
       escaped_macro_definition_body_alt2();
       break;
     }
@@ -11405,7 +10630,7 @@
 
 SV3_1aPpParser::Escaped_macro_definition_body_alt1Context* SV3_1aPpParser::escaped_macro_definition_body_alt1() {
   Escaped_macro_definition_body_alt1Context *_localctx = _tracker.createInstance<Escaped_macro_definition_body_alt1Context>(_ctx, getState());
-  enterRule(_localctx, 260, SV3_1aPpParser::RuleEscaped_macro_definition_body_alt1);
+  enterRule(_localctx, 248, SV3_1aPpParser::RuleEscaped_macro_definition_body_alt1);
   size_t _la = 0;
 
   auto onExit = finally([=] {
@@ -11414,201 +10639,201 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(1384);
+    setState(1261);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 109, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 91, _ctx);
     while (alt != 1 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1 + 1) {
-        setState(1382);
+        setState(1259);
         _errHandler->sync(this);
-        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 108, _ctx)) {
+        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 90, _ctx)) {
         case 1: {
-          setState(1354);
+          setState(1231);
           unterminated_string();
           break;
         }
 
         case 2: {
-          setState(1355);
+          setState(1232);
           match(SV3_1aPpParser::Macro_identifier);
           break;
         }
 
         case 3: {
-          setState(1356);
+          setState(1233);
           match(SV3_1aPpParser::Macro_Escaped_identifier);
           break;
         }
 
         case 4: {
-          setState(1357);
+          setState(1234);
           escaped_identifier();
           break;
         }
 
         case 5: {
-          setState(1358);
+          setState(1235);
           match(SV3_1aPpParser::Simple_identifier);
           break;
         }
 
         case 6: {
-          setState(1359);
+          setState(1236);
           number();
           break;
         }
 
         case 7: {
-          setState(1360);
+          setState(1237);
           match(SV3_1aPpParser::TEXT_CR);
           break;
         }
 
         case 8: {
-          setState(1361);
+          setState(1238);
           pound_delay();
           break;
         }
 
         case 9: {
-          setState(1362);
+          setState(1239);
           match(SV3_1aPpParser::ESCAPED_CR);
           break;
         }
 
         case 10: {
-          setState(1363);
+          setState(1240);
           match(SV3_1aPpParser::PARENS_OPEN);
           break;
         }
 
         case 11: {
-          setState(1364);
+          setState(1241);
           match(SV3_1aPpParser::PARENS_CLOSE);
           break;
         }
 
         case 12: {
-          setState(1365);
+          setState(1242);
           match(SV3_1aPpParser::COMMA);
           break;
         }
 
         case 13: {
-          setState(1366);
+          setState(1243);
           match(SV3_1aPpParser::EQUAL_OP);
           break;
         }
 
         case 14: {
-          setState(1367);
+          setState(1244);
           match(SV3_1aPpParser::DOUBLE_QUOTE);
           break;
         }
 
         case 15: {
-          setState(1368);
+          setState(1245);
           match(SV3_1aPpParser::TICK_VARIABLE);
           break;
         }
 
         case 16: {
-          setState(1369);
+          setState(1246);
           directive_in_macro();
           break;
         }
 
         case 17: {
-          setState(1370);
+          setState(1247);
           match(SV3_1aPpParser::Spaces);
           break;
         }
 
         case 18: {
-          setState(1371);
+          setState(1248);
           match(SV3_1aPpParser::Fixed_point_number);
           break;
         }
 
         case 19: {
-          setState(1372);
+          setState(1249);
           match(SV3_1aPpParser::String);
           break;
         }
 
         case 20: {
-          setState(1373);
+          setState(1250);
           comments();
           break;
         }
 
         case 21: {
-          setState(1374);
+          setState(1251);
           match(SV3_1aPpParser::TICK_QUOTE);
           break;
         }
 
         case 22: {
-          setState(1375);
+          setState(1252);
           match(SV3_1aPpParser::TICK_BACKSLASH_TICK_QUOTE);
           break;
         }
 
         case 23: {
-          setState(1376);
+          setState(1253);
           match(SV3_1aPpParser::TICK_TICK);
           break;
         }
 
         case 24: {
-          setState(1377);
+          setState(1254);
           match(SV3_1aPpParser::Special);
           break;
         }
 
         case 25: {
-          setState(1378);
+          setState(1255);
           match(SV3_1aPpParser::CURLY_OPEN);
           break;
         }
 
         case 26: {
-          setState(1379);
+          setState(1256);
           match(SV3_1aPpParser::CURLY_CLOSE);
           break;
         }
 
         case 27: {
-          setState(1380);
+          setState(1257);
           match(SV3_1aPpParser::SQUARE_OPEN);
           break;
         }
 
         case 28: {
-          setState(1381);
+          setState(1258);
           match(SV3_1aPpParser::SQUARE_CLOSE);
           break;
         }
 
         } 
       }
-      setState(1386);
+      setState(1263);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 109, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 91, _ctx);
     }
-    setState(1387);
+    setState(1264);
     match(SV3_1aPpParser::ESCAPED_CR);
-    setState(1391);
+    setState(1268);
     _errHandler->sync(this);
     _la = _input->LA(1);
     while (_la == SV3_1aPpParser::Spaces) {
-      setState(1388);
+      setState(1265);
       match(SV3_1aPpParser::Spaces);
-      setState(1393);
+      setState(1270);
       _errHandler->sync(this);
       _la = _input->LA(1);
     }
-    setState(1394);
+    setState(1271);
     _la = _input->LA(1);
     if (!(_la == SV3_1aPpParser::EOF || _la == SV3_1aPpParser::CR)) {
     _errHandler->recoverInline(this);
@@ -11885,7 +11110,7 @@
 
 SV3_1aPpParser::Escaped_macro_definition_body_alt2Context* SV3_1aPpParser::escaped_macro_definition_body_alt2() {
   Escaped_macro_definition_body_alt2Context *_localctx = _tracker.createInstance<Escaped_macro_definition_body_alt2Context>(_ctx, getState());
-  enterRule(_localctx, 262, SV3_1aPpParser::RuleEscaped_macro_definition_body_alt2);
+  enterRule(_localctx, 250, SV3_1aPpParser::RuleEscaped_macro_definition_body_alt2);
 
   auto onExit = finally([=] {
     exitRule();
@@ -11893,211 +11118,211 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(1426);
+    setState(1303);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 112, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 94, _ctx);
     while (alt != 1 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1 + 1) {
-        setState(1424);
+        setState(1301);
         _errHandler->sync(this);
-        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 111, _ctx)) {
+        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 93, _ctx)) {
         case 1: {
-          setState(1396);
+          setState(1273);
           unterminated_string();
           break;
         }
 
         case 2: {
-          setState(1397);
+          setState(1274);
           match(SV3_1aPpParser::Macro_identifier);
           break;
         }
 
         case 3: {
-          setState(1398);
+          setState(1275);
           match(SV3_1aPpParser::Macro_Escaped_identifier);
           break;
         }
 
         case 4: {
-          setState(1399);
+          setState(1276);
           escaped_identifier();
           break;
         }
 
         case 5: {
-          setState(1400);
+          setState(1277);
           match(SV3_1aPpParser::Simple_identifier);
           break;
         }
 
         case 6: {
-          setState(1401);
+          setState(1278);
           number();
           break;
         }
 
         case 7: {
-          setState(1402);
+          setState(1279);
           match(SV3_1aPpParser::TEXT_CR);
           break;
         }
 
         case 8: {
-          setState(1403);
+          setState(1280);
           pound_delay();
           break;
         }
 
         case 9: {
-          setState(1404);
+          setState(1281);
           match(SV3_1aPpParser::ESCAPED_CR);
           break;
         }
 
         case 10: {
-          setState(1405);
+          setState(1282);
           match(SV3_1aPpParser::PARENS_OPEN);
           break;
         }
 
         case 11: {
-          setState(1406);
+          setState(1283);
           match(SV3_1aPpParser::PARENS_CLOSE);
           break;
         }
 
         case 12: {
-          setState(1407);
+          setState(1284);
           match(SV3_1aPpParser::COMMA);
           break;
         }
 
         case 13: {
-          setState(1408);
+          setState(1285);
           match(SV3_1aPpParser::EQUAL_OP);
           break;
         }
 
         case 14: {
-          setState(1409);
+          setState(1286);
           match(SV3_1aPpParser::DOUBLE_QUOTE);
           break;
         }
 
         case 15: {
-          setState(1410);
+          setState(1287);
           match(SV3_1aPpParser::TICK_VARIABLE);
           break;
         }
 
         case 16: {
-          setState(1411);
+          setState(1288);
           directive_in_macro();
           break;
         }
 
         case 17: {
-          setState(1412);
+          setState(1289);
           match(SV3_1aPpParser::Spaces);
           break;
         }
 
         case 18: {
-          setState(1413);
+          setState(1290);
           match(SV3_1aPpParser::Fixed_point_number);
           break;
         }
 
         case 19: {
-          setState(1414);
+          setState(1291);
           match(SV3_1aPpParser::String);
           break;
         }
 
         case 20: {
-          setState(1415);
+          setState(1292);
           comments();
           break;
         }
 
         case 21: {
-          setState(1416);
+          setState(1293);
           match(SV3_1aPpParser::TICK_QUOTE);
           break;
         }
 
         case 22: {
-          setState(1417);
+          setState(1294);
           match(SV3_1aPpParser::TICK_BACKSLASH_TICK_QUOTE);
           break;
         }
 
         case 23: {
-          setState(1418);
+          setState(1295);
           match(SV3_1aPpParser::TICK_TICK);
           break;
         }
 
         case 24: {
-          setState(1419);
+          setState(1296);
           match(SV3_1aPpParser::Special);
           break;
         }
 
         case 25: {
-          setState(1420);
+          setState(1297);
           match(SV3_1aPpParser::CURLY_OPEN);
           break;
         }
 
         case 26: {
-          setState(1421);
+          setState(1298);
           match(SV3_1aPpParser::CURLY_CLOSE);
           break;
         }
 
         case 27: {
-          setState(1422);
+          setState(1299);
           match(SV3_1aPpParser::SQUARE_OPEN);
           break;
         }
 
         case 28: {
-          setState(1423);
+          setState(1300);
           match(SV3_1aPpParser::SQUARE_CLOSE);
           break;
         }
 
         } 
       }
-      setState(1428);
+      setState(1305);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 112, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 94, _ctx);
     }
-    setState(1437);
+    setState(1314);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::CR: {
-        setState(1429);
+        setState(1306);
         match(SV3_1aPpParser::CR);
-        setState(1433);
+        setState(1310);
         _errHandler->sync(this);
-        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 113, _ctx);
+        alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 95, _ctx);
         while (alt != 2 && alt != atn::ATN::INVALID_ALT_NUMBER) {
           if (alt == 1) {
-            setState(1430);
+            setState(1307);
             match(SV3_1aPpParser::Spaces); 
           }
-          setState(1435);
+          setState(1312);
           _errHandler->sync(this);
-          alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 113, _ctx);
+          alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 95, _ctx);
         }
         break;
       }
 
       case SV3_1aPpParser::EOF: {
-        setState(1436);
+        setState(1313);
         match(SV3_1aPpParser::EOF);
         break;
       }
@@ -12365,7 +11590,7 @@
 
 SV3_1aPpParser::Simple_macro_definition_bodyContext* SV3_1aPpParser::simple_macro_definition_body() {
   Simple_macro_definition_bodyContext *_localctx = _tracker.createInstance<Simple_macro_definition_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 264, SV3_1aPpParser::RuleSimple_macro_definition_body);
+  enterRule(_localctx, 252, SV3_1aPpParser::RuleSimple_macro_definition_body);
 
   auto onExit = finally([=] {
     exitRule();
@@ -12373,187 +11598,187 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(1469);
+    setState(1346);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 116, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 98, _ctx);
     while (alt != 1 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1 + 1) {
-        setState(1467);
+        setState(1344);
         _errHandler->sync(this);
-        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 115, _ctx)) {
+        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 97, _ctx)) {
         case 1: {
-          setState(1439);
+          setState(1316);
           unterminated_string();
           break;
         }
 
         case 2: {
-          setState(1440);
+          setState(1317);
           match(SV3_1aPpParser::Macro_identifier);
           break;
         }
 
         case 3: {
-          setState(1441);
+          setState(1318);
           match(SV3_1aPpParser::Macro_Escaped_identifier);
           break;
         }
 
         case 4: {
-          setState(1442);
+          setState(1319);
           escaped_identifier();
           break;
         }
 
         case 5: {
-          setState(1443);
+          setState(1320);
           match(SV3_1aPpParser::Simple_identifier);
           break;
         }
 
         case 6: {
-          setState(1444);
+          setState(1321);
           number();
           break;
         }
 
         case 7: {
-          setState(1445);
+          setState(1322);
           pound_delay();
           break;
         }
 
         case 8: {
-          setState(1446);
+          setState(1323);
           match(SV3_1aPpParser::TEXT_CR);
           break;
         }
 
         case 9: {
-          setState(1447);
+          setState(1324);
           match(SV3_1aPpParser::PARENS_OPEN);
           break;
         }
 
         case 10: {
-          setState(1448);
+          setState(1325);
           match(SV3_1aPpParser::PARENS_CLOSE);
           break;
         }
 
         case 11: {
-          setState(1449);
+          setState(1326);
           match(SV3_1aPpParser::COMMA);
           break;
         }
 
         case 12: {
-          setState(1450);
+          setState(1327);
           match(SV3_1aPpParser::EQUAL_OP);
           break;
         }
 
         case 13: {
-          setState(1451);
+          setState(1328);
           match(SV3_1aPpParser::DOUBLE_QUOTE);
           break;
         }
 
         case 14: {
-          setState(1452);
+          setState(1329);
           match(SV3_1aPpParser::TICK_VARIABLE);
           break;
         }
 
         case 15: {
-          setState(1453);
+          setState(1330);
           match(SV3_1aPpParser::Spaces);
           break;
         }
 
         case 16: {
-          setState(1454);
+          setState(1331);
           match(SV3_1aPpParser::Fixed_point_number);
           break;
         }
 
         case 17: {
-          setState(1455);
+          setState(1332);
           match(SV3_1aPpParser::String);
           break;
         }
 
         case 18: {
-          setState(1456);
+          setState(1333);
           comments();
           break;
         }
 
         case 19: {
-          setState(1457);
+          setState(1334);
           match(SV3_1aPpParser::TICK_QUOTE);
           break;
         }
 
         case 20: {
-          setState(1458);
+          setState(1335);
           match(SV3_1aPpParser::TICK_BACKSLASH_TICK_QUOTE);
           break;
         }
 
         case 21: {
-          setState(1459);
+          setState(1336);
           match(SV3_1aPpParser::TICK_TICK);
           break;
         }
 
         case 22: {
-          setState(1460);
+          setState(1337);
           match(SV3_1aPpParser::Special);
           break;
         }
 
         case 23: {
-          setState(1461);
+          setState(1338);
           match(SV3_1aPpParser::CURLY_OPEN);
           break;
         }
 
         case 24: {
-          setState(1462);
+          setState(1339);
           match(SV3_1aPpParser::CURLY_CLOSE);
           break;
         }
 
         case 25: {
-          setState(1463);
+          setState(1340);
           match(SV3_1aPpParser::SQUARE_OPEN);
           break;
         }
 
         case 26: {
-          setState(1464);
+          setState(1341);
           match(SV3_1aPpParser::SQUARE_CLOSE);
           break;
         }
 
         case 27: {
-          setState(1465);
+          setState(1342);
           match(SV3_1aPpParser::TICK_INCLUDE);
           break;
         }
 
         case 28: {
-          setState(1466);
+          setState(1343);
           directive_in_macro();
           break;
         }
 
         } 
       }
-      setState(1471);
+      setState(1348);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 116, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 98, _ctx);
     }
    
   }
@@ -12799,7 +12024,7 @@
 
 SV3_1aPpParser::Simple_macro_definition_body_in_macro_bodyContext* SV3_1aPpParser::simple_macro_definition_body_in_macro_body() {
   Simple_macro_definition_body_in_macro_bodyContext *_localctx = _tracker.createInstance<Simple_macro_definition_body_in_macro_bodyContext>(_ctx, getState());
-  enterRule(_localctx, 266, SV3_1aPpParser::RuleSimple_macro_definition_body_in_macro_body);
+  enterRule(_localctx, 254, SV3_1aPpParser::RuleSimple_macro_definition_body_in_macro_body);
 
   auto onExit = finally([=] {
     exitRule();
@@ -12807,175 +12032,175 @@
   try {
     size_t alt;
     enterOuterAlt(_localctx, 1);
-    setState(1500);
+    setState(1377);
     _errHandler->sync(this);
-    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 118, _ctx);
+    alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 100, _ctx);
     while (alt != 1 && alt != atn::ATN::INVALID_ALT_NUMBER) {
       if (alt == 1 + 1) {
-        setState(1498);
+        setState(1375);
         _errHandler->sync(this);
-        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 117, _ctx)) {
+        switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 99, _ctx)) {
         case 1: {
-          setState(1472);
+          setState(1349);
           unterminated_string();
           break;
         }
 
         case 2: {
-          setState(1473);
+          setState(1350);
           match(SV3_1aPpParser::Macro_identifier);
           break;
         }
 
         case 3: {
-          setState(1474);
+          setState(1351);
           match(SV3_1aPpParser::Macro_Escaped_identifier);
           break;
         }
 
         case 4: {
-          setState(1475);
+          setState(1352);
           escaped_identifier();
           break;
         }
 
         case 5: {
-          setState(1476);
+          setState(1353);
           match(SV3_1aPpParser::Simple_identifier);
           break;
         }
 
         case 6: {
-          setState(1477);
+          setState(1354);
           number();
           break;
         }
 
         case 7: {
-          setState(1478);
+          setState(1355);
           pound_delay();
           break;
         }
 
         case 8: {
-          setState(1479);
+          setState(1356);
           match(SV3_1aPpParser::TEXT_CR);
           break;
         }
 
         case 9: {
-          setState(1480);
+          setState(1357);
           match(SV3_1aPpParser::PARENS_OPEN);
           break;
         }
 
         case 10: {
-          setState(1481);
+          setState(1358);
           match(SV3_1aPpParser::PARENS_CLOSE);
           break;
         }
 
         case 11: {
-          setState(1482);
+          setState(1359);
           match(SV3_1aPpParser::COMMA);
           break;
         }
 
         case 12: {
-          setState(1483);
+          setState(1360);
           match(SV3_1aPpParser::EQUAL_OP);
           break;
         }
 
         case 13: {
-          setState(1484);
+          setState(1361);
           match(SV3_1aPpParser::DOUBLE_QUOTE);
           break;
         }
 
         case 14: {
-          setState(1485);
+          setState(1362);
           match(SV3_1aPpParser::TICK_VARIABLE);
           break;
         }
 
         case 15: {
-          setState(1486);
+          setState(1363);
           match(SV3_1aPpParser::Spaces);
           break;
         }
 
         case 16: {
-          setState(1487);
+          setState(1364);
           match(SV3_1aPpParser::Fixed_point_number);
           break;
         }
 
         case 17: {
-          setState(1488);
+          setState(1365);
           match(SV3_1aPpParser::String);
           break;
         }
 
         case 18: {
-          setState(1489);
+          setState(1366);
           comments();
           break;
         }
 
         case 19: {
-          setState(1490);
+          setState(1367);
           match(SV3_1aPpParser::TICK_QUOTE);
           break;
         }
 
         case 20: {
-          setState(1491);
+          setState(1368);
           match(SV3_1aPpParser::TICK_BACKSLASH_TICK_QUOTE);
           break;
         }
 
         case 21: {
-          setState(1492);
+          setState(1369);
           match(SV3_1aPpParser::TICK_TICK);
           break;
         }
 
         case 22: {
-          setState(1493);
+          setState(1370);
           match(SV3_1aPpParser::Special);
           break;
         }
 
         case 23: {
-          setState(1494);
+          setState(1371);
           match(SV3_1aPpParser::CURLY_OPEN);
           break;
         }
 
         case 24: {
-          setState(1495);
+          setState(1372);
           match(SV3_1aPpParser::CURLY_CLOSE);
           break;
         }
 
         case 25: {
-          setState(1496);
+          setState(1373);
           match(SV3_1aPpParser::SQUARE_OPEN);
           break;
         }
 
         case 26: {
-          setState(1497);
+          setState(1374);
           match(SV3_1aPpParser::SQUARE_CLOSE);
           break;
         }
 
         } 
       }
-      setState(1502);
+      setState(1379);
       _errHandler->sync(this);
-      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 118, _ctx);
+      alt = getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 100, _ctx);
     }
    
   }
@@ -13085,137 +12310,137 @@
 
 SV3_1aPpParser::Pragma_expressionContext* SV3_1aPpParser::pragma_expression() {
   Pragma_expressionContext *_localctx = _tracker.createInstance<Pragma_expressionContext>(_ctx, getState());
-  enterRule(_localctx, 268, SV3_1aPpParser::RulePragma_expression);
+  enterRule(_localctx, 256, SV3_1aPpParser::RulePragma_expression);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1521);
+    setState(1398);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
         enterOuterAlt(_localctx, 1);
-        setState(1503);
+        setState(1380);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Number: {
         enterOuterAlt(_localctx, 2);
-        setState(1504);
+        setState(1381);
         number();
         break;
       }
 
       case SV3_1aPpParser::Spaces: {
         enterOuterAlt(_localctx, 3);
-        setState(1505);
+        setState(1382);
         match(SV3_1aPpParser::Spaces);
         break;
       }
 
       case SV3_1aPpParser::Fixed_point_number: {
         enterOuterAlt(_localctx, 4);
-        setState(1506);
+        setState(1383);
         match(SV3_1aPpParser::Fixed_point_number);
         break;
       }
 
       case SV3_1aPpParser::String: {
         enterOuterAlt(_localctx, 5);
-        setState(1507);
+        setState(1384);
         match(SV3_1aPpParser::String);
         break;
       }
 
       case SV3_1aPpParser::Special: {
         enterOuterAlt(_localctx, 6);
-        setState(1508);
+        setState(1385);
         match(SV3_1aPpParser::Special);
         break;
       }
 
       case SV3_1aPpParser::CURLY_OPEN: {
         enterOuterAlt(_localctx, 7);
-        setState(1509);
+        setState(1386);
         match(SV3_1aPpParser::CURLY_OPEN);
         break;
       }
 
       case SV3_1aPpParser::CURLY_CLOSE: {
         enterOuterAlt(_localctx, 8);
-        setState(1510);
+        setState(1387);
         match(SV3_1aPpParser::CURLY_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_OPEN: {
         enterOuterAlt(_localctx, 9);
-        setState(1511);
+        setState(1388);
         match(SV3_1aPpParser::SQUARE_OPEN);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_CLOSE: {
         enterOuterAlt(_localctx, 10);
-        setState(1512);
+        setState(1389);
         match(SV3_1aPpParser::SQUARE_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::PARENS_OPEN: {
         enterOuterAlt(_localctx, 11);
-        setState(1513);
+        setState(1390);
         match(SV3_1aPpParser::PARENS_OPEN);
         break;
       }
 
       case SV3_1aPpParser::PARENS_CLOSE: {
         enterOuterAlt(_localctx, 12);
-        setState(1514);
+        setState(1391);
         match(SV3_1aPpParser::PARENS_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::COMMA: {
         enterOuterAlt(_localctx, 13);
-        setState(1515);
+        setState(1392);
         match(SV3_1aPpParser::COMMA);
         break;
       }
 
       case SV3_1aPpParser::EQUAL_OP: {
         enterOuterAlt(_localctx, 14);
-        setState(1516);
+        setState(1393);
         match(SV3_1aPpParser::EQUAL_OP);
         break;
       }
 
       case SV3_1aPpParser::DOUBLE_QUOTE: {
         enterOuterAlt(_localctx, 15);
-        setState(1517);
+        setState(1394);
         match(SV3_1aPpParser::DOUBLE_QUOTE);
         break;
       }
 
       case SV3_1aPpParser::ANY: {
         enterOuterAlt(_localctx, 16);
-        setState(1518);
+        setState(1395);
         match(SV3_1aPpParser::ANY);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
         enterOuterAlt(_localctx, 17);
-        setState(1519);
+        setState(1396);
         escaped_identifier();
         break;
       }
 
       case SV3_1aPpParser::Pound_delay: {
         enterOuterAlt(_localctx, 18);
-        setState(1520);
+        setState(1397);
         pound_delay();
         break;
       }
@@ -13327,130 +12552,130 @@
 
 SV3_1aPpParser::Macro_argContext* SV3_1aPpParser::macro_arg() {
   Macro_argContext *_localctx = _tracker.createInstance<Macro_argContext>(_ctx, getState());
-  enterRule(_localctx, 270, SV3_1aPpParser::RuleMacro_arg);
+  enterRule(_localctx, 258, SV3_1aPpParser::RuleMacro_arg);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1540);
+    setState(1417);
     _errHandler->sync(this);
-    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 120, _ctx)) {
+    switch (getInterpreter<atn::ParserATNSimulator>()->adaptivePredict(_input, 102, _ctx)) {
     case 1: {
       enterOuterAlt(_localctx, 1);
-      setState(1523);
+      setState(1400);
       match(SV3_1aPpParser::Simple_identifier);
       break;
     }
 
     case 2: {
       enterOuterAlt(_localctx, 2);
-      setState(1524);
+      setState(1401);
       number();
       break;
     }
 
     case 3: {
       enterOuterAlt(_localctx, 3);
-      setState(1525);
+      setState(1402);
       match(SV3_1aPpParser::Spaces);
       break;
     }
 
     case 4: {
       enterOuterAlt(_localctx, 4);
-      setState(1526);
+      setState(1403);
       match(SV3_1aPpParser::Fixed_point_number);
       break;
     }
 
     case 5: {
       enterOuterAlt(_localctx, 5);
-      setState(1527);
+      setState(1404);
       match(SV3_1aPpParser::String);
       break;
     }
 
     case 6: {
       enterOuterAlt(_localctx, 6);
-      setState(1528);
+      setState(1405);
       match(SV3_1aPpParser::Special);
       break;
     }
 
     case 7: {
       enterOuterAlt(_localctx, 7);
-      setState(1529);
+      setState(1406);
       paired_parens();
       break;
     }
 
     case 8: {
       enterOuterAlt(_localctx, 8);
-      setState(1530);
+      setState(1407);
       match(SV3_1aPpParser::EQUAL_OP);
       break;
     }
 
     case 9: {
       enterOuterAlt(_localctx, 9);
-      setState(1531);
+      setState(1408);
       match(SV3_1aPpParser::DOUBLE_QUOTE);
       break;
     }
 
     case 10: {
       enterOuterAlt(_localctx, 10);
-      setState(1532);
+      setState(1409);
       macro_instance();
       break;
     }
 
     case 11: {
       enterOuterAlt(_localctx, 11);
-      setState(1533);
+      setState(1410);
       match(SV3_1aPpParser::CR);
       break;
     }
 
     case 12: {
       enterOuterAlt(_localctx, 12);
-      setState(1534);
+      setState(1411);
       match(SV3_1aPpParser::TEXT_CR);
       break;
     }
 
     case 13: {
       enterOuterAlt(_localctx, 13);
-      setState(1535);
+      setState(1412);
       match(SV3_1aPpParser::ANY);
       break;
     }
 
     case 14: {
       enterOuterAlt(_localctx, 14);
-      setState(1536);
+      setState(1413);
       escaped_identifier();
       break;
     }
 
     case 15: {
       enterOuterAlt(_localctx, 15);
-      setState(1537);
+      setState(1414);
       simple_args_macro_definition_in_macro_body();
       break;
     }
 
     case 16: {
       enterOuterAlt(_localctx, 16);
-      setState(1538);
+      setState(1415);
       simple_no_args_macro_definition_in_macro_body();
       break;
     }
 
     case 17: {
       enterOuterAlt(_localctx, 17);
-      setState(1539);
+      setState(1416);
       comments();
       break;
     }
@@ -13644,21 +12869,21 @@
 
 SV3_1aPpParser::Paired_parensContext* SV3_1aPpParser::paired_parens() {
   Paired_parensContext *_localctx = _tracker.createInstance<Paired_parensContext>(_ctx, getState());
-  enterRule(_localctx, 272, SV3_1aPpParser::RulePaired_parens);
+  enterRule(_localctx, 260, SV3_1aPpParser::RulePaired_parens);
   size_t _la = 0;
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1609);
+    setState(1486);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::PARENS_OPEN: {
         enterOuterAlt(_localctx, 1);
-        setState(1542);
+        setState(1419);
         match(SV3_1aPpParser::PARENS_OPEN);
-        setState(1561);
+        setState(1438);
         _errHandler->sync(this);
         _la = _input->LA(1);
         while (_la == SV3_1aPpParser::One_line_comment
@@ -13682,84 +12907,84 @@
           | (1ULL << (SV3_1aPpParser::SQUARE_OPEN - 67))
           | (1ULL << (SV3_1aPpParser::Special - 67))
           | (1ULL << (SV3_1aPpParser::ANY - 67)))) != 0)) {
-          setState(1559);
+          setState(1436);
           _errHandler->sync(this);
           switch (_input->LA(1)) {
             case SV3_1aPpParser::Simple_identifier: {
-              setState(1543);
+              setState(1420);
               match(SV3_1aPpParser::Simple_identifier);
               break;
             }
 
             case SV3_1aPpParser::Number: {
-              setState(1544);
+              setState(1421);
               number();
               break;
             }
 
             case SV3_1aPpParser::Spaces: {
-              setState(1545);
+              setState(1422);
               match(SV3_1aPpParser::Spaces);
               break;
             }
 
             case SV3_1aPpParser::Fixed_point_number: {
-              setState(1546);
+              setState(1423);
               match(SV3_1aPpParser::Fixed_point_number);
               break;
             }
 
             case SV3_1aPpParser::String: {
-              setState(1547);
+              setState(1424);
               match(SV3_1aPpParser::String);
               break;
             }
 
             case SV3_1aPpParser::Special: {
-              setState(1548);
+              setState(1425);
               match(SV3_1aPpParser::Special);
               break;
             }
 
             case SV3_1aPpParser::COMMA: {
-              setState(1549);
+              setState(1426);
               match(SV3_1aPpParser::COMMA);
               break;
             }
 
             case SV3_1aPpParser::EQUAL_OP: {
-              setState(1550);
+              setState(1427);
               match(SV3_1aPpParser::EQUAL_OP);
               break;
             }
 
             case SV3_1aPpParser::DOUBLE_QUOTE: {
-              setState(1551);
+              setState(1428);
               match(SV3_1aPpParser::DOUBLE_QUOTE);
               break;
             }
 
             case SV3_1aPpParser::Macro_identifier:
             case SV3_1aPpParser::Macro_Escaped_identifier: {
-              setState(1552);
+              setState(1429);
               macro_instance();
               break;
             }
 
             case SV3_1aPpParser::TEXT_CR: {
-              setState(1553);
+              setState(1430);
               match(SV3_1aPpParser::TEXT_CR);
               break;
             }
 
             case SV3_1aPpParser::CR: {
-              setState(1554);
+              setState(1431);
               match(SV3_1aPpParser::CR);
               break;
             }
 
             case SV3_1aPpParser::ANY: {
-              setState(1555);
+              setState(1432);
               match(SV3_1aPpParser::ANY);
               break;
             }
@@ -13767,20 +12992,20 @@
             case SV3_1aPpParser::PARENS_OPEN:
             case SV3_1aPpParser::CURLY_OPEN:
             case SV3_1aPpParser::SQUARE_OPEN: {
-              setState(1556);
+              setState(1433);
               paired_parens();
               break;
             }
 
             case SV3_1aPpParser::Escaped_identifier: {
-              setState(1557);
+              setState(1434);
               escaped_identifier();
               break;
             }
 
             case SV3_1aPpParser::One_line_comment:
             case SV3_1aPpParser::Block_comment: {
-              setState(1558);
+              setState(1435);
               comments();
               break;
             }
@@ -13788,20 +13013,20 @@
           default:
             throw NoViableAltException(this);
           }
-          setState(1563);
+          setState(1440);
           _errHandler->sync(this);
           _la = _input->LA(1);
         }
-        setState(1564);
+        setState(1441);
         match(SV3_1aPpParser::PARENS_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::CURLY_OPEN: {
         enterOuterAlt(_localctx, 2);
-        setState(1565);
+        setState(1442);
         match(SV3_1aPpParser::CURLY_OPEN);
-        setState(1583);
+        setState(1460);
         _errHandler->sync(this);
         _la = _input->LA(1);
         while (_la == SV3_1aPpParser::One_line_comment
@@ -13824,78 +13049,78 @@
           | (1ULL << (SV3_1aPpParser::SQUARE_OPEN - 67))
           | (1ULL << (SV3_1aPpParser::Special - 67))
           | (1ULL << (SV3_1aPpParser::ANY - 67)))) != 0)) {
-          setState(1581);
+          setState(1458);
           _errHandler->sync(this);
           switch (_input->LA(1)) {
             case SV3_1aPpParser::Simple_identifier: {
-              setState(1566);
+              setState(1443);
               match(SV3_1aPpParser::Simple_identifier);
               break;
             }
 
             case SV3_1aPpParser::Number: {
-              setState(1567);
+              setState(1444);
               number();
               break;
             }
 
             case SV3_1aPpParser::Spaces: {
-              setState(1568);
+              setState(1445);
               match(SV3_1aPpParser::Spaces);
               break;
             }
 
             case SV3_1aPpParser::Fixed_point_number: {
-              setState(1569);
+              setState(1446);
               match(SV3_1aPpParser::Fixed_point_number);
               break;
             }
 
             case SV3_1aPpParser::String: {
-              setState(1570);
+              setState(1447);
               match(SV3_1aPpParser::String);
               break;
             }
 
             case SV3_1aPpParser::Special: {
-              setState(1571);
+              setState(1448);
               match(SV3_1aPpParser::Special);
               break;
             }
 
             case SV3_1aPpParser::COMMA: {
-              setState(1572);
+              setState(1449);
               match(SV3_1aPpParser::COMMA);
               break;
             }
 
             case SV3_1aPpParser::EQUAL_OP: {
-              setState(1573);
+              setState(1450);
               match(SV3_1aPpParser::EQUAL_OP);
               break;
             }
 
             case SV3_1aPpParser::DOUBLE_QUOTE: {
-              setState(1574);
+              setState(1451);
               match(SV3_1aPpParser::DOUBLE_QUOTE);
               break;
             }
 
             case SV3_1aPpParser::Macro_identifier:
             case SV3_1aPpParser::Macro_Escaped_identifier: {
-              setState(1575);
+              setState(1452);
               macro_instance();
               break;
             }
 
             case SV3_1aPpParser::CR: {
-              setState(1576);
+              setState(1453);
               match(SV3_1aPpParser::CR);
               break;
             }
 
             case SV3_1aPpParser::ANY: {
-              setState(1577);
+              setState(1454);
               match(SV3_1aPpParser::ANY);
               break;
             }
@@ -13903,20 +13128,20 @@
             case SV3_1aPpParser::PARENS_OPEN:
             case SV3_1aPpParser::CURLY_OPEN:
             case SV3_1aPpParser::SQUARE_OPEN: {
-              setState(1578);
+              setState(1455);
               paired_parens();
               break;
             }
 
             case SV3_1aPpParser::Escaped_identifier: {
-              setState(1579);
+              setState(1456);
               escaped_identifier();
               break;
             }
 
             case SV3_1aPpParser::One_line_comment:
             case SV3_1aPpParser::Block_comment: {
-              setState(1580);
+              setState(1457);
               comments();
               break;
             }
@@ -13924,20 +13149,20 @@
           default:
             throw NoViableAltException(this);
           }
-          setState(1585);
+          setState(1462);
           _errHandler->sync(this);
           _la = _input->LA(1);
         }
-        setState(1586);
+        setState(1463);
         match(SV3_1aPpParser::CURLY_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_OPEN: {
         enterOuterAlt(_localctx, 3);
-        setState(1587);
+        setState(1464);
         match(SV3_1aPpParser::SQUARE_OPEN);
-        setState(1605);
+        setState(1482);
         _errHandler->sync(this);
         _la = _input->LA(1);
         while (_la == SV3_1aPpParser::One_line_comment
@@ -13960,78 +13185,78 @@
           | (1ULL << (SV3_1aPpParser::SQUARE_OPEN - 67))
           | (1ULL << (SV3_1aPpParser::Special - 67))
           | (1ULL << (SV3_1aPpParser::ANY - 67)))) != 0)) {
-          setState(1603);
+          setState(1480);
           _errHandler->sync(this);
           switch (_input->LA(1)) {
             case SV3_1aPpParser::Simple_identifier: {
-              setState(1588);
+              setState(1465);
               match(SV3_1aPpParser::Simple_identifier);
               break;
             }
 
             case SV3_1aPpParser::Number: {
-              setState(1589);
+              setState(1466);
               number();
               break;
             }
 
             case SV3_1aPpParser::Spaces: {
-              setState(1590);
+              setState(1467);
               match(SV3_1aPpParser::Spaces);
               break;
             }
 
             case SV3_1aPpParser::Fixed_point_number: {
-              setState(1591);
+              setState(1468);
               match(SV3_1aPpParser::Fixed_point_number);
               break;
             }
 
             case SV3_1aPpParser::String: {
-              setState(1592);
+              setState(1469);
               match(SV3_1aPpParser::String);
               break;
             }
 
             case SV3_1aPpParser::Special: {
-              setState(1593);
+              setState(1470);
               match(SV3_1aPpParser::Special);
               break;
             }
 
             case SV3_1aPpParser::COMMA: {
-              setState(1594);
+              setState(1471);
               match(SV3_1aPpParser::COMMA);
               break;
             }
 
             case SV3_1aPpParser::EQUAL_OP: {
-              setState(1595);
+              setState(1472);
               match(SV3_1aPpParser::EQUAL_OP);
               break;
             }
 
             case SV3_1aPpParser::DOUBLE_QUOTE: {
-              setState(1596);
+              setState(1473);
               match(SV3_1aPpParser::DOUBLE_QUOTE);
               break;
             }
 
             case SV3_1aPpParser::Macro_identifier:
             case SV3_1aPpParser::Macro_Escaped_identifier: {
-              setState(1597);
+              setState(1474);
               macro_instance();
               break;
             }
 
             case SV3_1aPpParser::CR: {
-              setState(1598);
+              setState(1475);
               match(SV3_1aPpParser::CR);
               break;
             }
 
             case SV3_1aPpParser::ANY: {
-              setState(1599);
+              setState(1476);
               match(SV3_1aPpParser::ANY);
               break;
             }
@@ -14039,20 +13264,20 @@
             case SV3_1aPpParser::PARENS_OPEN:
             case SV3_1aPpParser::CURLY_OPEN:
             case SV3_1aPpParser::SQUARE_OPEN: {
-              setState(1600);
+              setState(1477);
               paired_parens();
               break;
             }
 
             case SV3_1aPpParser::Escaped_identifier: {
-              setState(1601);
+              setState(1478);
               escaped_identifier();
               break;
             }
 
             case SV3_1aPpParser::One_line_comment:
             case SV3_1aPpParser::Block_comment: {
-              setState(1602);
+              setState(1479);
               comments();
               break;
             }
@@ -14060,11 +13285,11 @@
           default:
             throw NoViableAltException(this);
           }
-          setState(1607);
+          setState(1484);
           _errHandler->sync(this);
           _la = _input->LA(1);
         }
-        setState(1608);
+        setState(1485);
         match(SV3_1aPpParser::SQUARE_CLOSE);
         break;
       }
@@ -14208,186 +13433,186 @@
 
 SV3_1aPpParser::Text_blobContext* SV3_1aPpParser::text_blob() {
   Text_blobContext *_localctx = _tracker.createInstance<Text_blobContext>(_ctx, getState());
-  enterRule(_localctx, 274, SV3_1aPpParser::RuleText_blob);
+  enterRule(_localctx, 262, SV3_1aPpParser::RuleText_blob);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1636);
+    setState(1513);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
         enterOuterAlt(_localctx, 1);
-        setState(1611);
+        setState(1488);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Number: {
         enterOuterAlt(_localctx, 2);
-        setState(1612);
+        setState(1489);
         number();
         break;
       }
 
       case SV3_1aPpParser::CR: {
         enterOuterAlt(_localctx, 3);
-        setState(1613);
+        setState(1490);
         match(SV3_1aPpParser::CR);
         break;
       }
 
       case SV3_1aPpParser::Spaces: {
         enterOuterAlt(_localctx, 4);
-        setState(1614);
+        setState(1491);
         match(SV3_1aPpParser::Spaces);
         break;
       }
 
       case SV3_1aPpParser::Fixed_point_number: {
         enterOuterAlt(_localctx, 5);
-        setState(1615);
+        setState(1492);
         match(SV3_1aPpParser::Fixed_point_number);
         break;
       }
 
       case SV3_1aPpParser::ESCAPED_CR: {
         enterOuterAlt(_localctx, 6);
-        setState(1616);
+        setState(1493);
         match(SV3_1aPpParser::ESCAPED_CR);
         break;
       }
 
       case SV3_1aPpParser::String: {
         enterOuterAlt(_localctx, 7);
-        setState(1617);
+        setState(1494);
         match(SV3_1aPpParser::String);
         break;
       }
 
       case SV3_1aPpParser::PARENS_OPEN: {
         enterOuterAlt(_localctx, 8);
-        setState(1618);
+        setState(1495);
         match(SV3_1aPpParser::PARENS_OPEN);
         break;
       }
 
       case SV3_1aPpParser::PARENS_CLOSE: {
         enterOuterAlt(_localctx, 9);
-        setState(1619);
+        setState(1496);
         match(SV3_1aPpParser::PARENS_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::COMMA: {
         enterOuterAlt(_localctx, 10);
-        setState(1620);
+        setState(1497);
         match(SV3_1aPpParser::COMMA);
         break;
       }
 
       case SV3_1aPpParser::EQUAL_OP: {
         enterOuterAlt(_localctx, 11);
-        setState(1621);
+        setState(1498);
         match(SV3_1aPpParser::EQUAL_OP);
         break;
       }
 
       case SV3_1aPpParser::DOUBLE_QUOTE: {
         enterOuterAlt(_localctx, 12);
-        setState(1622);
+        setState(1499);
         match(SV3_1aPpParser::DOUBLE_QUOTE);
         break;
       }
 
       case SV3_1aPpParser::Special: {
         enterOuterAlt(_localctx, 13);
-        setState(1623);
+        setState(1500);
         match(SV3_1aPpParser::Special);
         break;
       }
 
       case SV3_1aPpParser::CURLY_OPEN: {
         enterOuterAlt(_localctx, 14);
-        setState(1624);
+        setState(1501);
         match(SV3_1aPpParser::CURLY_OPEN);
         break;
       }
 
       case SV3_1aPpParser::CURLY_CLOSE: {
         enterOuterAlt(_localctx, 15);
-        setState(1625);
+        setState(1502);
         match(SV3_1aPpParser::CURLY_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_OPEN: {
         enterOuterAlt(_localctx, 16);
-        setState(1626);
+        setState(1503);
         match(SV3_1aPpParser::SQUARE_OPEN);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_CLOSE: {
         enterOuterAlt(_localctx, 17);
-        setState(1627);
+        setState(1504);
         match(SV3_1aPpParser::SQUARE_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::TICK_TICK: {
         enterOuterAlt(_localctx, 18);
-        setState(1628);
+        setState(1505);
         match(SV3_1aPpParser::TICK_TICK);
         break;
       }
 
       case SV3_1aPpParser::TICK_VARIABLE: {
         enterOuterAlt(_localctx, 19);
-        setState(1629);
+        setState(1506);
         match(SV3_1aPpParser::TICK_VARIABLE);
         break;
       }
 
       case SV3_1aPpParser::TIMESCALE: {
         enterOuterAlt(_localctx, 20);
-        setState(1630);
+        setState(1507);
         match(SV3_1aPpParser::TIMESCALE);
         break;
       }
 
       case SV3_1aPpParser::ANY: {
         enterOuterAlt(_localctx, 21);
-        setState(1631);
+        setState(1508);
         match(SV3_1aPpParser::ANY);
         break;
       }
 
       case SV3_1aPpParser::Pound_delay: {
         enterOuterAlt(_localctx, 22);
-        setState(1632);
+        setState(1509);
         pound_delay();
         break;
       }
 
       case SV3_1aPpParser::TICK_QUOTE: {
         enterOuterAlt(_localctx, 23);
-        setState(1633);
+        setState(1510);
         match(SV3_1aPpParser::TICK_QUOTE);
         break;
       }
 
       case SV3_1aPpParser::TICK_BACKSLASH_TICK_QUOTE: {
         enterOuterAlt(_localctx, 24);
-        setState(1634);
+        setState(1511);
         match(SV3_1aPpParser::TICK_BACKSLASH_TICK_QUOTE);
         break;
       }
 
       case SV3_1aPpParser::TEXT_CR: {
         enterOuterAlt(_localctx, 25);
-        setState(1635);
+        setState(1512);
         match(SV3_1aPpParser::TEXT_CR);
         break;
       }
@@ -14435,14 +13660,14 @@
 
 SV3_1aPpParser::StringContext* SV3_1aPpParser::string() {
   StringContext *_localctx = _tracker.createInstance<StringContext>(_ctx, getState());
-  enterRule(_localctx, 276, SV3_1aPpParser::RuleString);
+  enterRule(_localctx, 264, SV3_1aPpParser::RuleString);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1638);
+    setState(1515);
     match(SV3_1aPpParser::String);
    
   }
@@ -14484,14 +13709,14 @@
 
 SV3_1aPpParser::Escaped_identifierContext* SV3_1aPpParser::escaped_identifier() {
   Escaped_identifierContext *_localctx = _tracker.createInstance<Escaped_identifierContext>(_ctx, getState());
-  enterRule(_localctx, 278, SV3_1aPpParser::RuleEscaped_identifier);
+  enterRule(_localctx, 266, SV3_1aPpParser::RuleEscaped_identifier);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
     enterOuterAlt(_localctx, 1);
-    setState(1640);
+    setState(1517);
     match(SV3_1aPpParser::Escaped_identifier);
    
   }
@@ -14581,95 +13806,95 @@
 
 SV3_1aPpParser::Default_valueContext* SV3_1aPpParser::default_value() {
   Default_valueContext *_localctx = _tracker.createInstance<Default_valueContext>(_ctx, getState());
-  enterRule(_localctx, 280, SV3_1aPpParser::RuleDefault_value);
+  enterRule(_localctx, 268, SV3_1aPpParser::RuleDefault_value);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1655);
+    setState(1532);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
         enterOuterAlt(_localctx, 1);
-        setState(1642);
+        setState(1519);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Number: {
         enterOuterAlt(_localctx, 2);
-        setState(1643);
+        setState(1520);
         number();
         break;
       }
 
       case SV3_1aPpParser::Spaces: {
         enterOuterAlt(_localctx, 3);
-        setState(1644);
+        setState(1521);
         match(SV3_1aPpParser::Spaces);
         break;
       }
 
       case SV3_1aPpParser::Fixed_point_number: {
         enterOuterAlt(_localctx, 4);
-        setState(1645);
+        setState(1522);
         match(SV3_1aPpParser::Fixed_point_number);
         break;
       }
 
       case SV3_1aPpParser::String: {
         enterOuterAlt(_localctx, 5);
-        setState(1646);
+        setState(1523);
         match(SV3_1aPpParser::String);
         break;
       }
 
       case SV3_1aPpParser::Special: {
         enterOuterAlt(_localctx, 6);
-        setState(1647);
+        setState(1524);
         match(SV3_1aPpParser::Special);
         break;
       }
 
       case SV3_1aPpParser::CURLY_OPEN: {
         enterOuterAlt(_localctx, 7);
-        setState(1648);
+        setState(1525);
         match(SV3_1aPpParser::CURLY_OPEN);
         break;
       }
 
       case SV3_1aPpParser::CURLY_CLOSE: {
         enterOuterAlt(_localctx, 8);
-        setState(1649);
+        setState(1526);
         match(SV3_1aPpParser::CURLY_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_OPEN: {
         enterOuterAlt(_localctx, 9);
-        setState(1650);
+        setState(1527);
         match(SV3_1aPpParser::SQUARE_OPEN);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_CLOSE: {
         enterOuterAlt(_localctx, 10);
-        setState(1651);
+        setState(1528);
         match(SV3_1aPpParser::SQUARE_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::ANY: {
         enterOuterAlt(_localctx, 11);
-        setState(1652);
+        setState(1529);
         match(SV3_1aPpParser::ANY);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
         enterOuterAlt(_localctx, 12);
-        setState(1653);
+        setState(1530);
         escaped_identifier();
         break;
       }
@@ -14677,7 +13902,7 @@
       case SV3_1aPpParser::Macro_identifier:
       case SV3_1aPpParser::Macro_Escaped_identifier: {
         enterOuterAlt(_localctx, 13);
-        setState(1654);
+        setState(1531);
         macro_instance();
         break;
       }
@@ -14801,151 +14026,151 @@
 
 SV3_1aPpParser::String_blobContext* SV3_1aPpParser::string_blob() {
   String_blobContext *_localctx = _tracker.createInstance<String_blobContext>(_ctx, getState());
-  enterRule(_localctx, 282, SV3_1aPpParser::RuleString_blob);
+  enterRule(_localctx, 270, SV3_1aPpParser::RuleString_blob);
 
   auto onExit = finally([=] {
     exitRule();
   });
   try {
-    setState(1677);
+    setState(1554);
     _errHandler->sync(this);
     switch (_input->LA(1)) {
       case SV3_1aPpParser::Simple_identifier: {
         enterOuterAlt(_localctx, 1);
-        setState(1657);
+        setState(1534);
         match(SV3_1aPpParser::Simple_identifier);
         break;
       }
 
       case SV3_1aPpParser::Number: {
         enterOuterAlt(_localctx, 2);
-        setState(1658);
+        setState(1535);
         number();
         break;
       }
 
       case SV3_1aPpParser::Spaces: {
         enterOuterAlt(_localctx, 3);
-        setState(1659);
+        setState(1536);
         match(SV3_1aPpParser::Spaces);
         break;
       }
 
       case SV3_1aPpParser::Fixed_point_number: {
         enterOuterAlt(_localctx, 4);
-        setState(1660);
+        setState(1537);
         match(SV3_1aPpParser::Fixed_point_number);
         break;
       }
 
       case SV3_1aPpParser::ESCAPED_CR: {
         enterOuterAlt(_localctx, 5);
-        setState(1661);
+        setState(1538);
         match(SV3_1aPpParser::ESCAPED_CR);
         break;
       }
 
       case SV3_1aPpParser::PARENS_OPEN: {
         enterOuterAlt(_localctx, 6);
-        setState(1662);
+        setState(1539);
         match(SV3_1aPpParser::PARENS_OPEN);
         break;
       }
 
       case SV3_1aPpParser::PARENS_CLOSE: {
         enterOuterAlt(_localctx, 7);
-        setState(1663);
+        setState(1540);
         match(SV3_1aPpParser::PARENS_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::COMMA: {
         enterOuterAlt(_localctx, 8);
-        setState(1664);
+        setState(1541);
         match(SV3_1aPpParser::COMMA);
         break;
       }
 
       case SV3_1aPpParser::EQUAL_OP: {
         enterOuterAlt(_localctx, 9);
-        setState(1665);
+        setState(1542);
         match(SV3_1aPpParser::EQUAL_OP);
         break;
       }
 
       case SV3_1aPpParser::DOUBLE_QUOTE: {
         enterOuterAlt(_localctx, 10);
-        setState(1666);
+        setState(1543);
         match(SV3_1aPpParser::DOUBLE_QUOTE);
         break;
       }
 
       case SV3_1aPpParser::Special: {
         enterOuterAlt(_localctx, 11);
-        setState(1667);
+        setState(1544);
         match(SV3_1aPpParser::Special);
         break;
       }
 
       case SV3_1aPpParser::CURLY_OPEN: {
         enterOuterAlt(_localctx, 12);
-        setState(1668);
+        setState(1545);
         match(SV3_1aPpParser::CURLY_OPEN);
         break;
       }
 
       case SV3_1aPpParser::CURLY_CLOSE: {
         enterOuterAlt(_localctx, 13);
-        setState(1669);
+        setState(1546);
         match(SV3_1aPpParser::CURLY_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_OPEN: {
         enterOuterAlt(_localctx, 14);
-        setState(1670);
+        setState(1547);
         match(SV3_1aPpParser::SQUARE_OPEN);
         break;
       }
 
       case SV3_1aPpParser::SQUARE_CLOSE: {
         enterOuterAlt(_localctx, 15);
-        setState(1671);
+        setState(1548);
         match(SV3_1aPpParser::SQUARE_CLOSE);
         break;
       }
 
       case SV3_1aPpParser::ANY: {
         enterOuterAlt(_localctx, 16);
-        setState(1672);
+        setState(1549);
         match(SV3_1aPpParser::ANY);
         break;
       }
 
       case SV3_1aPpParser::Escaped_identifier: {
         enterOuterAlt(_localctx, 17);
-        setState(1673);
+        setState(1550);
         escaped_identifier();
         break;
       }
 
       case SV3_1aPpParser::TIMESCALE: {
         enterOuterAlt(_localctx, 18);
-        setState(1674);
+        setState(1551);
         match(SV3_1aPpParser::TIMESCALE);
         break;
       }
 
       case SV3_1aPpParser::Pound_delay: {
         enterOuterAlt(_localctx, 19);
-        setState(1675);
+        setState(1552);
         pound_delay();
         break;
       }
 
       case SV3_1aPpParser::TEXT_CR: {
         enterOuterAlt(_localctx, 20);
-        setState(1676);
+        setState(1553);
         match(SV3_1aPpParser::TEXT_CR);
         break;
       }
@@ -14978,19 +14203,17 @@
   "include_directive_one_line", "include_directive", "line_directive_one_line", 
   "line_directive", "default_nettype_directive_one_line", "default_nettype_directive", 
   "sv_file_directive", "sv_line_directive", "timescale_directive_one_line", 
-  "timescale_directive", "undef_directive", "ifdef_directive_one_line", 
-  "ifdef_directive", "ifdef_directive_in_macro_body", "ifndef_directive_one_line", 
-  "ifndef_directive", "ifndef_directive_in_macro_body", "elsif_directive_one_line", 
-  "elsif_directive", "elsif_directive_in_macro_body", "elseif_directive_one_line", 
-  "elseif_directive", "elseif_directive_in_macro_body", "else_directive_one_line", 
-  "else_directive", "endif_directive_one_line", "endif_directive", "resetall_directive_one_line", 
-  "resetall_directive", "begin_keywords_directive_one_line", "begin_keywords_directive", 
-  "end_keywords_directive_one_line", "end_keywords_directive", "pragma_directive_one_line", 
-  "pragma_directive", "celldefine_directive_one_line", "celldefine_directive", 
-  "endcelldefine_directive_one_line", "endcelldefine_directive", "protect_directive_one_line", 
-  "protect_directive", "endprotect_directive_one_line", "endprotect_directive", 
-  "protected_directive_one_line", "protected_directive", "endprotected_directive_one_line", 
-  "endprotected_directive", "expand_vectornets_directive_one_line", "expand_vectornets_directive", 
+  "timescale_directive", "undef_directive", "ifdef_directive", "ifdef_directive_in_macro_body", 
+  "ifndef_directive", "ifndef_directive_in_macro_body", "elsif_directive", 
+  "elsif_directive_in_macro_body", "elseif_directive", "elseif_directive_in_macro_body", 
+  "else_directive", "endif_directive", "resetall_directive_one_line", "resetall_directive", 
+  "begin_keywords_directive_one_line", "begin_keywords_directive", "end_keywords_directive_one_line", 
+  "end_keywords_directive", "pragma_directive_one_line", "pragma_directive", 
+  "celldefine_directive_one_line", "celldefine_directive", "endcelldefine_directive_one_line", 
+  "endcelldefine_directive", "protect_directive_one_line", "protect_directive", 
+  "endprotect_directive_one_line", "endprotect_directive", "protected_directive_one_line", 
+  "protected_directive", "endprotected_directive_one_line", "endprotected_directive", 
+  "expand_vectornets_directive_one_line", "expand_vectornets_directive", 
   "noexpand_vectornets_directive_one_line", "noexpand_vectornets_directive", 
   "autoexpand_vectornets_directive_one_line", "autoexpand_vectornets_directive", 
   "uselib_directive_one_line", "uselib_directive", "disable_portfaults_directive_one_line", 
@@ -15087,7 +14310,7 @@
 
   _serializedATN = {
     0x3, 0x608b, 0xa72a, 0x8133, 0xb9ed, 0x417c, 0x3be7, 0x7786, 0x5964, 
-    0x3, 0x5f, 0x692, 0x4, 0x2, 0x9, 0x2, 0x4, 0x3, 0x9, 0x3, 0x4, 0x4, 
+    0x3, 0x5f, 0x617, 0x4, 0x2, 0x9, 0x2, 0x4, 0x3, 0x9, 0x3, 0x4, 0x4, 
     0x9, 0x4, 0x4, 0x5, 0x9, 0x5, 0x4, 0x6, 0x9, 0x6, 0x4, 0x7, 0x9, 0x7, 
     0x4, 0x8, 0x9, 0x8, 0x4, 0x9, 0x9, 0x9, 0x4, 0xa, 0x9, 0xa, 0x4, 0xb, 
     0x9, 0xb, 0x4, 0xc, 0x9, 0xc, 0x4, 0xd, 0x9, 0xd, 0x4, 0xe, 0x9, 0xe, 
@@ -15128,10 +14351,8 @@
     0x9, 0x7d, 0x4, 0x7e, 0x9, 0x7e, 0x4, 0x7f, 0x9, 0x7f, 0x4, 0x80, 0x9, 
     0x80, 0x4, 0x81, 0x9, 0x81, 0x4, 0x82, 0x9, 0x82, 0x4, 0x83, 0x9, 0x83, 
     0x4, 0x84, 0x9, 0x84, 0x4, 0x85, 0x9, 0x85, 0x4, 0x86, 0x9, 0x86, 0x4, 
-    0x87, 0x9, 0x87, 0x4, 0x88, 0x9, 0x88, 0x4, 0x89, 0x9, 0x89, 0x4, 0x8a, 
-    0x9, 0x8a, 0x4, 0x8b, 0x9, 0x8b, 0x4, 0x8c, 0x9, 0x8c, 0x4, 0x8d, 0x9, 
-    0x8d, 0x4, 0x8e, 0x9, 0x8e, 0x4, 0x8f, 0x9, 0x8f, 0x3, 0x2, 0x7, 0x2, 
-    0x120, 0xa, 0x2, 0xc, 0x2, 0xe, 0x2, 0x123, 0xb, 0x2, 0x3, 0x3, 0x3, 
+    0x87, 0x9, 0x87, 0x4, 0x88, 0x9, 0x88, 0x4, 0x89, 0x9, 0x89, 0x3, 0x2, 
+    0x7, 0x2, 0x114, 0xa, 0x2, 0xc, 0x2, 0xe, 0x2, 0x117, 0xb, 0x2, 0x3, 
     0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 
     0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 
     0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 
@@ -15142,1272 +14363,1179 @@
     0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 
     0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 
     0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 
-    0x3, 0x3, 0x3, 0x5, 0x3, 0x16e, 0xa, 0x3, 0x3, 0x4, 0x3, 0x4, 0x7, 0x4, 
-    0x172, 0xa, 0x4, 0xc, 0x4, 0xe, 0x4, 0x175, 0xb, 0x4, 0x3, 0x4, 0x3, 
-    0x4, 0x3, 0x4, 0x3, 0x4, 0x3, 0x4, 0x5, 0x4, 0x17c, 0xa, 0x4, 0x3, 0x5, 
-    0x3, 0x5, 0x7, 0x5, 0x180, 0xa, 0x5, 0xc, 0x5, 0xe, 0x5, 0x183, 0xb, 
-    0x5, 0x3, 0x5, 0x3, 0x5, 0x3, 0x6, 0x7, 0x6, 0x188, 0xa, 0x6, 0xc, 0x6, 
-    0xe, 0x6, 0x18b, 0xb, 0x6, 0x3, 0x6, 0x3, 0x6, 0x7, 0x6, 0x18f, 0xa, 
-    0x6, 0xc, 0x6, 0xe, 0x6, 0x192, 0xb, 0x6, 0x7, 0x6, 0x194, 0xa, 0x6, 
-    0xc, 0x6, 0xe, 0x6, 0x197, 0xb, 0x6, 0x3, 0x7, 0x3, 0x7, 0x3, 0x8, 0x3, 
-    0x8, 0x3, 0x9, 0x3, 0x9, 0x3, 0xa, 0x3, 0xa, 0x3, 0xa, 0x3, 0xa, 0x3, 
-    0xa, 0x5, 0xa, 0x1a4, 0xa, 0xa, 0x3, 0xb, 0x3, 0xb, 0x7, 0xb, 0x1a8, 
-    0xa, 0xb, 0xc, 0xb, 0xe, 0xb, 0x1ab, 0xb, 0xb, 0x3, 0xb, 0x3, 0xb, 0x3, 
-    0xc, 0x3, 0xc, 0x3, 0xc, 0x3, 0xc, 0x3, 0xc, 0x3, 0xc, 0x5, 0xc, 0x1b5, 
-    0xa, 0xc, 0x3, 0xd, 0x3, 0xd, 0x7, 0xd, 0x1b9, 0xa, 0xd, 0xc, 0xd, 0xe, 
-    0xd, 0x1bc, 0xb, 0xd, 0x3, 0xd, 0x3, 0xd, 0x3, 0xe, 0x3, 0xe, 0x3, 0xe, 
+    0x3, 0x3, 0x3, 0x3, 0x3, 0x5, 0x3, 0x162, 0xa, 0x3, 0x3, 0x4, 0x3, 0x4, 
+    0x7, 0x4, 0x166, 0xa, 0x4, 0xc, 0x4, 0xe, 0x4, 0x169, 0xb, 0x4, 0x3, 
+    0x4, 0x3, 0x4, 0x3, 0x4, 0x3, 0x4, 0x3, 0x4, 0x5, 0x4, 0x170, 0xa, 0x4, 
+    0x3, 0x5, 0x3, 0x5, 0x7, 0x5, 0x174, 0xa, 0x5, 0xc, 0x5, 0xe, 0x5, 0x177, 
+    0xb, 0x5, 0x3, 0x5, 0x3, 0x5, 0x3, 0x6, 0x7, 0x6, 0x17c, 0xa, 0x6, 0xc, 
+    0x6, 0xe, 0x6, 0x17f, 0xb, 0x6, 0x3, 0x6, 0x3, 0x6, 0x7, 0x6, 0x183, 
+    0xa, 0x6, 0xc, 0x6, 0xe, 0x6, 0x186, 0xb, 0x6, 0x7, 0x6, 0x188, 0xa, 
+    0x6, 0xc, 0x6, 0xe, 0x6, 0x18b, 0xb, 0x6, 0x3, 0x7, 0x3, 0x7, 0x3, 0x8, 
+    0x3, 0x8, 0x3, 0x9, 0x3, 0x9, 0x3, 0xa, 0x3, 0xa, 0x3, 0xa, 0x3, 0xa, 
+    0x3, 0xa, 0x5, 0xa, 0x198, 0xa, 0xa, 0x3, 0xb, 0x3, 0xb, 0x7, 0xb, 0x19c, 
+    0xa, 0xb, 0xc, 0xb, 0xe, 0xb, 0x19f, 0xb, 0xb, 0x3, 0xb, 0x3, 0xb, 0x3, 
+    0xc, 0x3, 0xc, 0x3, 0xc, 0x3, 0xc, 0x3, 0xc, 0x3, 0xc, 0x5, 0xc, 0x1a9, 
+    0xa, 0xc, 0x3, 0xd, 0x3, 0xd, 0x7, 0xd, 0x1ad, 0xa, 0xd, 0xc, 0xd, 0xe, 
+    0xd, 0x1b0, 0xb, 0xd, 0x3, 0xd, 0x3, 0xd, 0x3, 0xe, 0x3, 0xe, 0x3, 0xe, 
     0x3, 0xe, 0x3, 0xe, 0x3, 0xe, 0x3, 0xe, 0x3, 0xf, 0x3, 0xf, 0x7, 0xf, 
-    0x1c9, 0xa, 0xf, 0xc, 0xf, 0xe, 0xf, 0x1cc, 0xb, 0xf, 0x3, 0xf, 0x3, 
+    0x1bd, 0xa, 0xf, 0xc, 0xf, 0xe, 0xf, 0x1c0, 0xb, 0xf, 0x3, 0xf, 0x3, 
     0xf, 0x3, 0x10, 0x3, 0x10, 0x3, 0x10, 0x3, 0x10, 0x3, 0x11, 0x3, 0x11, 
-    0x3, 0x12, 0x3, 0x12, 0x3, 0x13, 0x3, 0x13, 0x7, 0x13, 0x1da, 0xa, 0x13, 
-    0xc, 0x13, 0xe, 0x13, 0x1dd, 0xb, 0x13, 0x3, 0x13, 0x3, 0x13, 0x3, 0x14, 
+    0x3, 0x12, 0x3, 0x12, 0x3, 0x13, 0x3, 0x13, 0x7, 0x13, 0x1ce, 0xa, 0x13, 
+    0xc, 0x13, 0xe, 0x13, 0x1d1, 0xb, 0x13, 0x3, 0x13, 0x3, 0x13, 0x3, 0x14, 
     0x3, 0x14, 0x3, 0x14, 0x3, 0x15, 0x3, 0x15, 0x3, 0x15, 0x3, 0x15, 0x3, 
-    0x15, 0x5, 0x15, 0x1e9, 0xa, 0x15, 0x3, 0x16, 0x3, 0x16, 0x7, 0x16, 
-    0x1ed, 0xa, 0x16, 0xc, 0x16, 0xe, 0x16, 0x1f0, 0xb, 0x16, 0x3, 0x16, 
-    0x3, 0x16, 0x7, 0x16, 0x1f4, 0xa, 0x16, 0xc, 0x16, 0xe, 0x16, 0x1f7, 
-    0xb, 0x16, 0x3, 0x16, 0x3, 0x16, 0x3, 0x16, 0x5, 0x16, 0x1fc, 0xa, 0x16, 
-    0x3, 0x16, 0x6, 0x16, 0x1ff, 0xa, 0x16, 0xd, 0x16, 0xe, 0x16, 0x200, 
-    0x7, 0x16, 0x203, 0xa, 0x16, 0xc, 0x16, 0xe, 0x16, 0x206, 0xb, 0x16, 
-    0x3, 0x16, 0x5, 0x16, 0x209, 0xa, 0x16, 0x3, 0x17, 0x3, 0x17, 0x3, 0x17, 
-    0x3, 0x17, 0x3, 0x17, 0x5, 0x17, 0x210, 0xa, 0x17, 0x3, 0x18, 0x3, 0x18, 
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+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5d4, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5d5, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5d6, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5d7, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5d8, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5d9, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5da, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5db, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5dc, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5dd, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5de, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5df, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e0, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e1, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e2, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e3, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e4, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e5, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e6, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e7, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e8, 0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5e9, 
+    0x3, 0x2, 0x2, 0x2, 0x5eb, 0x5ea, 0x3, 0x2, 0x2, 0x2, 0x5ec, 0x109, 
+    0x3, 0x2, 0x2, 0x2, 0x5ed, 0x5ee, 0x7, 0x47, 0x2, 0x2, 0x5ee, 0x10b, 
+    0x3, 0x2, 0x2, 0x2, 0x5ef, 0x5f0, 0x7, 0x59, 0x2, 0x2, 0x5f0, 0x10d, 
+    0x3, 0x2, 0x2, 0x2, 0x5f1, 0x5ff, 0x7, 0x48, 0x2, 0x2, 0x5f2, 0x5ff, 
+    0x5, 0xe, 0x8, 0x2, 0x5f3, 0x5ff, 0x7, 0x49, 0x2, 0x2, 0x5f4, 0x5ff, 
+    0x7, 0x4d, 0x2, 0x2, 0x5f5, 0x5ff, 0x7, 0x47, 0x2, 0x2, 0x5f6, 0x5ff, 
+    0x7, 0x5e, 0x2, 0x2, 0x5f7, 0x5ff, 0x7, 0x5a, 0x2, 0x2, 0x5f8, 0x5ff, 
+    0x7, 0x5b, 0x2, 0x2, 0x5f9, 0x5ff, 0x7, 0x5c, 0x2, 0x2, 0x5fa, 0x5ff, 
+    0x7, 0x5d, 0x2, 0x2, 0x5fb, 0x5ff, 0x7, 0x5f, 0x2, 0x2, 0x5fc, 0x5ff, 
+    0x5, 0x10c, 0x87, 0x2, 0x5fd, 0x5ff, 0x5, 0x6, 0x4, 0x2, 0x5fe, 0x5f1, 
+    0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5f2, 0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5f3, 
+    0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5f4, 0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5f5, 
+    0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5f6, 0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5f7, 
+    0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5f8, 0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5f9, 
+    0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5fa, 0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5fb, 
+    0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5fc, 0x3, 0x2, 0x2, 0x2, 0x5fe, 0x5fd, 
+    0x3, 0x2, 0x2, 0x2, 0x5ff, 0x10f, 0x3, 0x2, 0x2, 0x2, 0x600, 0x615, 
+    0x7, 0x48, 0x2, 0x2, 0x601, 0x615, 0x5, 0xe, 0x8, 0x2, 0x602, 0x615, 
+    0x7, 0x49, 0x2, 0x2, 0x603, 0x615, 0x7, 0x4d, 0x2, 0x2, 0x604, 0x615, 
+    0x7, 0x4f, 0x2, 0x2, 0x605, 0x615, 0x7, 0x54, 0x2, 0x2, 0x606, 0x615, 
+    0x7, 0x55, 0x2, 0x2, 0x607, 0x615, 0x7, 0x56, 0x2, 0x2, 0x608, 0x615, 
+    0x7, 0x57, 0x2, 0x2, 0x609, 0x615, 0x7, 0x58, 0x2, 0x2, 0x60a, 0x615, 
+    0x7, 0x5e, 0x2, 0x2, 0x60b, 0x615, 0x7, 0x5a, 0x2, 0x2, 0x60c, 0x615, 
+    0x7, 0x5b, 0x2, 0x2, 0x60d, 0x615, 0x7, 0x5c, 0x2, 0x2, 0x60e, 0x615, 
+    0x7, 0x5d, 0x2, 0x2, 0x60f, 0x615, 0x7, 0x5f, 0x2, 0x2, 0x610, 0x615, 
+    0x5, 0x10c, 0x87, 0x2, 0x611, 0x615, 0x7, 0x4b, 0x2, 0x2, 0x612, 0x615, 
+    0x5, 0x10, 0x9, 0x2, 0x613, 0x615, 0x7, 0x4e, 0x2, 0x2, 0x614, 0x600, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x601, 0x3, 0x2, 0x2, 0x2, 0x614, 0x602, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x603, 0x3, 0x2, 0x2, 0x2, 0x614, 0x604, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x605, 0x3, 0x2, 0x2, 0x2, 0x614, 0x606, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x607, 0x3, 0x2, 0x2, 0x2, 0x614, 0x608, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x609, 0x3, 0x2, 0x2, 0x2, 0x614, 0x60a, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x60b, 0x3, 0x2, 0x2, 0x2, 0x614, 0x60c, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x60d, 0x3, 0x2, 0x2, 0x2, 0x614, 0x60e, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x60f, 0x3, 0x2, 0x2, 0x2, 0x614, 0x610, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x611, 0x3, 0x2, 0x2, 0x2, 0x614, 0x612, 
+    0x3, 0x2, 0x2, 0x2, 0x614, 0x613, 0x3, 0x2, 0x2, 0x2, 0x615, 0x111, 
+    0x3, 0x2, 0x2, 0x2, 0x73, 0x115, 0x161, 0x167, 0x16f, 0x175, 0x17d, 
+    0x184, 0x189, 0x197, 0x19d, 0x1a8, 0x1ae, 0x1be, 0x1cf, 0x1dc, 0x1e3, 
+    0x1ea, 0x1f1, 0x1f8, 0x1ff, 0x206, 0x20d, 0x214, 0x21c, 0x221, 0x227, 
+    0x232, 0x23f, 0x24a, 0x257, 0x25c, 0x263, 0x26e, 0x279, 0x284, 0x28f, 
+    0x29a, 0x2a5, 0x2b0, 0x2bb, 0x2c9, 0x2cf, 0x2da, 0x2e5, 0x2f0, 0x2fb, 
+    0x306, 0x311, 0x31c, 0x327, 0x332, 0x33d, 0x348, 0x353, 0x360, 0x36a, 
+    0x370, 0x37d, 0x388, 0x393, 0x39e, 0x3a9, 0x3d4, 0x3df, 0x3eb, 0x3fd, 
+    0x401, 0x412, 0x417, 0x41b, 0x41f, 0x426, 0x42e, 0x433, 0x43a, 0x43e, 
+    0x444, 0x44e, 0x451, 0x491, 0x498, 0x49f, 0x4a4, 0x4ab, 0x4b2, 0x4b9, 
+    0x4be, 0x4c3, 0x4c8, 0x4cf, 0x4ed, 0x4ef, 0x4f6, 0x517, 0x519, 0x520, 
+    0x524, 0x542, 0x544, 0x561, 0x563, 0x578, 0x58b, 0x59e, 0x5a0, 0x5b4, 
+    0x5b6, 0x5ca, 0x5cc, 0x5d0, 0x5eb, 0x5fe, 0x614, 
   };
 
   atn::ATNDeserializer deserializer;
diff --git a/src/parser/SV3_1aPpParser.h b/src/parser/SV3_1aPpParser.h
index 4e7fd4d..03bd477 100644
--- a/src/parser/SV3_1aPpParser.h
+++ b/src/parser/SV3_1aPpParser.h
@@ -45,59 +45,56 @@
     RuleLine_directive_one_line = 11, RuleLine_directive = 12, RuleDefault_nettype_directive_one_line = 13, 
     RuleDefault_nettype_directive = 14, RuleSv_file_directive = 15, RuleSv_line_directive = 16, 
     RuleTimescale_directive_one_line = 17, RuleTimescale_directive = 18, 
-    RuleUndef_directive = 19, RuleIfdef_directive_one_line = 20, RuleIfdef_directive = 21, 
-    RuleIfdef_directive_in_macro_body = 22, RuleIfndef_directive_one_line = 23, 
-    RuleIfndef_directive = 24, RuleIfndef_directive_in_macro_body = 25, 
-    RuleElsif_directive_one_line = 26, RuleElsif_directive = 27, RuleElsif_directive_in_macro_body = 28, 
-    RuleElseif_directive_one_line = 29, RuleElseif_directive = 30, RuleElseif_directive_in_macro_body = 31, 
-    RuleElse_directive_one_line = 32, RuleElse_directive = 33, RuleEndif_directive_one_line = 34, 
-    RuleEndif_directive = 35, RuleResetall_directive_one_line = 36, RuleResetall_directive = 37, 
-    RuleBegin_keywords_directive_one_line = 38, RuleBegin_keywords_directive = 39, 
-    RuleEnd_keywords_directive_one_line = 40, RuleEnd_keywords_directive = 41, 
-    RulePragma_directive_one_line = 42, RulePragma_directive = 43, RuleCelldefine_directive_one_line = 44, 
-    RuleCelldefine_directive = 45, RuleEndcelldefine_directive_one_line = 46, 
-    RuleEndcelldefine_directive = 47, RuleProtect_directive_one_line = 48, 
-    RuleProtect_directive = 49, RuleEndprotect_directive_one_line = 50, 
-    RuleEndprotect_directive = 51, RuleProtected_directive_one_line = 52, 
-    RuleProtected_directive = 53, RuleEndprotected_directive_one_line = 54, 
-    RuleEndprotected_directive = 55, RuleExpand_vectornets_directive_one_line = 56, 
-    RuleExpand_vectornets_directive = 57, RuleNoexpand_vectornets_directive_one_line = 58, 
-    RuleNoexpand_vectornets_directive = 59, RuleAutoexpand_vectornets_directive_one_line = 60, 
-    RuleAutoexpand_vectornets_directive = 61, RuleUselib_directive_one_line = 62, 
-    RuleUselib_directive = 63, RuleDisable_portfaults_directive_one_line = 64, 
-    RuleDisable_portfaults_directive = 65, RuleEnable_portfaults_directive_one_line = 66, 
-    RuleEnable_portfaults_directive = 67, RuleNosuppress_faults_directive_one_line = 68, 
-    RuleNosuppress_faults_directive = 69, RuleSuppress_faults_directive_one_line = 70, 
-    RuleSuppress_faults_directive = 71, RuleSigned_directive_one_line = 72, 
-    RuleSigned_directive = 73, RuleUnsigned_directive_one_line = 74, RuleUnsigned_directive = 75, 
-    RuleRemove_gatename_directive_one_line = 76, RuleRemove_gatename_directive = 77, 
-    RuleNoremove_gatenames_directive_one_line = 78, RuleNoremove_gatenames_directive = 79, 
-    RuleRemove_netname_directive_one_line = 80, RuleRemove_netname_directive = 81, 
-    RuleNoremove_netnames_directive_one_line = 82, RuleNoremove_netnames_directive = 83, 
-    RuleAccelerate_directive_one_line = 84, RuleAccelerate_directive = 85, 
-    RuleNoaccelerate_directive_one_line = 86, RuleNoaccelerate_directive = 87, 
-    RuleDefault_trireg_strenght_directive_one_line = 88, RuleDefault_trireg_strenght_directive = 89, 
-    RuleDefault_decay_time_directive_one_line = 90, RuleDefault_decay_time_directive = 91, 
-    RuleUnconnected_drive_directive_one_line = 92, RuleUnconnected_drive_directive = 93, 
-    RuleNounconnected_drive_directive_one_line = 94, RuleNounconnected_drive_directive = 95, 
-    RuleDelay_mode_distributed_directive_one_line = 96, RuleDelay_mode_distributed_directive = 97, 
-    RuleDelay_mode_path_directive_one_line = 98, RuleDelay_mode_path_directive = 99, 
-    RuleDelay_mode_unit_directive_one_line = 100, RuleDelay_mode_unit_directive = 101, 
-    RuleDelay_mode_zero_directive_one_line = 102, RuleDelay_mode_zero_directive = 103, 
-    RuleUndefineall_directive = 104, RuleModule = 105, RuleEndmodule = 106, 
-    RuleSv_interface = 107, RuleEndinterface = 108, RuleProgram = 109, RuleEndprogram = 110, 
-    RulePrimitive = 111, RuleEndprimitive = 112, RuleSv_package = 113, RuleEndpackage = 114, 
-    RuleChecker = 115, RuleEndchecker = 116, RuleConfig = 117, RuleEndconfig = 118, 
-    RuleDefine_directive = 119, RuleMultiline_no_args_macro_definition = 120, 
-    RuleMultiline_args_macro_definition = 121, RuleSimple_no_args_macro_definition = 122, 
-    RuleSimple_args_macro_definition = 123, RuleIdentifier_in_macro_body = 124, 
-    RuleSimple_no_args_macro_definition_in_macro_body = 125, RuleSimple_args_macro_definition_in_macro_body = 126, 
-    RuleDirective_in_macro = 127, RuleMacro_arguments = 128, RuleEscaped_macro_definition_body = 129, 
-    RuleEscaped_macro_definition_body_alt1 = 130, RuleEscaped_macro_definition_body_alt2 = 131, 
-    RuleSimple_macro_definition_body = 132, RuleSimple_macro_definition_body_in_macro_body = 133, 
-    RulePragma_expression = 134, RuleMacro_arg = 135, RulePaired_parens = 136, 
-    RuleText_blob = 137, RuleString = 138, RuleEscaped_identifier = 139, 
-    RuleDefault_value = 140, RuleString_blob = 141
+    RuleUndef_directive = 19, RuleIfdef_directive = 20, RuleIfdef_directive_in_macro_body = 21, 
+    RuleIfndef_directive = 22, RuleIfndef_directive_in_macro_body = 23, 
+    RuleElsif_directive = 24, RuleElsif_directive_in_macro_body = 25, RuleElseif_directive = 26, 
+    RuleElseif_directive_in_macro_body = 27, RuleElse_directive = 28, RuleEndif_directive = 29, 
+    RuleResetall_directive_one_line = 30, RuleResetall_directive = 31, RuleBegin_keywords_directive_one_line = 32, 
+    RuleBegin_keywords_directive = 33, RuleEnd_keywords_directive_one_line = 34, 
+    RuleEnd_keywords_directive = 35, RulePragma_directive_one_line = 36, 
+    RulePragma_directive = 37, RuleCelldefine_directive_one_line = 38, RuleCelldefine_directive = 39, 
+    RuleEndcelldefine_directive_one_line = 40, RuleEndcelldefine_directive = 41, 
+    RuleProtect_directive_one_line = 42, RuleProtect_directive = 43, RuleEndprotect_directive_one_line = 44, 
+    RuleEndprotect_directive = 45, RuleProtected_directive_one_line = 46, 
+    RuleProtected_directive = 47, RuleEndprotected_directive_one_line = 48, 
+    RuleEndprotected_directive = 49, RuleExpand_vectornets_directive_one_line = 50, 
+    RuleExpand_vectornets_directive = 51, RuleNoexpand_vectornets_directive_one_line = 52, 
+    RuleNoexpand_vectornets_directive = 53, RuleAutoexpand_vectornets_directive_one_line = 54, 
+    RuleAutoexpand_vectornets_directive = 55, RuleUselib_directive_one_line = 56, 
+    RuleUselib_directive = 57, RuleDisable_portfaults_directive_one_line = 58, 
+    RuleDisable_portfaults_directive = 59, RuleEnable_portfaults_directive_one_line = 60, 
+    RuleEnable_portfaults_directive = 61, RuleNosuppress_faults_directive_one_line = 62, 
+    RuleNosuppress_faults_directive = 63, RuleSuppress_faults_directive_one_line = 64, 
+    RuleSuppress_faults_directive = 65, RuleSigned_directive_one_line = 66, 
+    RuleSigned_directive = 67, RuleUnsigned_directive_one_line = 68, RuleUnsigned_directive = 69, 
+    RuleRemove_gatename_directive_one_line = 70, RuleRemove_gatename_directive = 71, 
+    RuleNoremove_gatenames_directive_one_line = 72, RuleNoremove_gatenames_directive = 73, 
+    RuleRemove_netname_directive_one_line = 74, RuleRemove_netname_directive = 75, 
+    RuleNoremove_netnames_directive_one_line = 76, RuleNoremove_netnames_directive = 77, 
+    RuleAccelerate_directive_one_line = 78, RuleAccelerate_directive = 79, 
+    RuleNoaccelerate_directive_one_line = 80, RuleNoaccelerate_directive = 81, 
+    RuleDefault_trireg_strenght_directive_one_line = 82, RuleDefault_trireg_strenght_directive = 83, 
+    RuleDefault_decay_time_directive_one_line = 84, RuleDefault_decay_time_directive = 85, 
+    RuleUnconnected_drive_directive_one_line = 86, RuleUnconnected_drive_directive = 87, 
+    RuleNounconnected_drive_directive_one_line = 88, RuleNounconnected_drive_directive = 89, 
+    RuleDelay_mode_distributed_directive_one_line = 90, RuleDelay_mode_distributed_directive = 91, 
+    RuleDelay_mode_path_directive_one_line = 92, RuleDelay_mode_path_directive = 93, 
+    RuleDelay_mode_unit_directive_one_line = 94, RuleDelay_mode_unit_directive = 95, 
+    RuleDelay_mode_zero_directive_one_line = 96, RuleDelay_mode_zero_directive = 97, 
+    RuleUndefineall_directive = 98, RuleModule = 99, RuleEndmodule = 100, 
+    RuleSv_interface = 101, RuleEndinterface = 102, RuleProgram = 103, RuleEndprogram = 104, 
+    RulePrimitive = 105, RuleEndprimitive = 106, RuleSv_package = 107, RuleEndpackage = 108, 
+    RuleChecker = 109, RuleEndchecker = 110, RuleConfig = 111, RuleEndconfig = 112, 
+    RuleDefine_directive = 113, RuleMultiline_no_args_macro_definition = 114, 
+    RuleMultiline_args_macro_definition = 115, RuleSimple_no_args_macro_definition = 116, 
+    RuleSimple_args_macro_definition = 117, RuleIdentifier_in_macro_body = 118, 
+    RuleSimple_no_args_macro_definition_in_macro_body = 119, RuleSimple_args_macro_definition_in_macro_body = 120, 
+    RuleDirective_in_macro = 121, RuleMacro_arguments = 122, RuleEscaped_macro_definition_body = 123, 
+    RuleEscaped_macro_definition_body_alt1 = 124, RuleEscaped_macro_definition_body_alt2 = 125, 
+    RuleSimple_macro_definition_body = 126, RuleSimple_macro_definition_body_in_macro_body = 127, 
+    RulePragma_expression = 128, RuleMacro_arg = 129, RulePaired_parens = 130, 
+    RuleText_blob = 131, RuleString = 132, RuleEscaped_identifier = 133, 
+    RuleDefault_value = 134, RuleString_blob = 135
   };
 
   SV3_1aPpParser(antlr4::TokenStream *input);
@@ -130,21 +127,15 @@
   class Timescale_directive_one_lineContext;
   class Timescale_directiveContext;
   class Undef_directiveContext;
-  class Ifdef_directive_one_lineContext;
   class Ifdef_directiveContext;
   class Ifdef_directive_in_macro_bodyContext;
-  class Ifndef_directive_one_lineContext;
   class Ifndef_directiveContext;
   class Ifndef_directive_in_macro_bodyContext;
-  class Elsif_directive_one_lineContext;
   class Elsif_directiveContext;
   class Elsif_directive_in_macro_bodyContext;
-  class Elseif_directive_one_lineContext;
   class Elseif_directiveContext;
   class Elseif_directive_in_macro_bodyContext;
-  class Else_directive_one_lineContext;
   class Else_directiveContext;
-  class Endif_directive_one_lineContext;
   class Endif_directiveContext;
   class Resetall_directive_one_lineContext;
   class Resetall_directiveContext;
@@ -280,12 +271,12 @@
     Endcelldefine_directive_one_lineContext *endcelldefine_directive_one_line();
     Default_nettype_directive_one_lineContext *default_nettype_directive_one_line();
     Undef_directiveContext *undef_directive();
-    Ifdef_directive_one_lineContext *ifdef_directive_one_line();
-    Ifndef_directive_one_lineContext *ifndef_directive_one_line();
-    Else_directive_one_lineContext *else_directive_one_line();
-    Elsif_directive_one_lineContext *elsif_directive_one_line();
-    Elseif_directive_one_lineContext *elseif_directive_one_line();
-    Endif_directive_one_lineContext *endif_directive_one_line();
+    Ifdef_directiveContext *ifdef_directive();
+    Ifndef_directiveContext *ifndef_directive();
+    Else_directiveContext *else_directive();
+    Elsif_directiveContext *elsif_directive();
+    Elseif_directiveContext *elseif_directive();
+    Endif_directiveContext *endif_directive();
     Include_directive_one_lineContext *include_directive_one_line();
     Include_directiveContext *include_directive();
     Resetall_directive_one_lineContext *resetall_directive_one_line();
@@ -653,32 +644,6 @@
 
   Undef_directiveContext* undef_directive();
 
-  class  Ifdef_directive_one_lineContext : public antlr4::ParserRuleContext {
-  public:
-    Ifdef_directive_one_lineContext(antlr4::ParserRuleContext *parent, size_t invokingState);
-    virtual size_t getRuleIndex() const override;
-    Ifdef_directiveContext *ifdef_directive();
-    std::vector<antlr4::tree::TerminalNode *> Spaces();
-    antlr4::tree::TerminalNode* Spaces(size_t i);
-    antlr4::tree::TerminalNode *One_line_comment();
-    antlr4::tree::TerminalNode *CR();
-    Endif_directiveContext *endif_directive();
-    std::vector<DescriptionContext *> description();
-    DescriptionContext* description(size_t i);
-    std::vector<Else_directiveContext *> else_directive();
-    Else_directiveContext* else_directive(size_t i);
-    std::vector<Elseif_directiveContext *> elseif_directive();
-    Elseif_directiveContext* elseif_directive(size_t i);
-    std::vector<Elsif_directiveContext *> elsif_directive();
-    Elsif_directiveContext* elsif_directive(size_t i);
-
-    virtual void enterRule(antlr4::tree::ParseTreeListener *listener) override;
-    virtual void exitRule(antlr4::tree::ParseTreeListener *listener) override;
-   
-  };
-
-  Ifdef_directive_one_lineContext* ifdef_directive_one_line();
-
   class  Ifdef_directiveContext : public antlr4::ParserRuleContext {
   public:
     Ifdef_directiveContext(antlr4::ParserRuleContext *parent, size_t invokingState);
@@ -713,32 +678,6 @@
 
   Ifdef_directive_in_macro_bodyContext* ifdef_directive_in_macro_body();
 
-  class  Ifndef_directive_one_lineContext : public antlr4::ParserRuleContext {
-  public:
-    Ifndef_directive_one_lineContext(antlr4::ParserRuleContext *parent, size_t invokingState);
-    virtual size_t getRuleIndex() const override;
-    Ifndef_directiveContext *ifndef_directive();
-    std::vector<antlr4::tree::TerminalNode *> Spaces();
-    antlr4::tree::TerminalNode* Spaces(size_t i);
-    antlr4::tree::TerminalNode *One_line_comment();
-    antlr4::tree::TerminalNode *CR();
-    Endif_directiveContext *endif_directive();
-    std::vector<DescriptionContext *> description();
-    DescriptionContext* description(size_t i);
-    std::vector<Else_directiveContext *> else_directive();
-    Else_directiveContext* else_directive(size_t i);
-    std::vector<Elseif_directiveContext *> elseif_directive();
-    Elseif_directiveContext* elseif_directive(size_t i);
-    std::vector<Elsif_directiveContext *> elsif_directive();
-    Elsif_directiveContext* elsif_directive(size_t i);
-
-    virtual void enterRule(antlr4::tree::ParseTreeListener *listener) override;
-    virtual void exitRule(antlr4::tree::ParseTreeListener *listener) override;
-   
-  };
-
-  Ifndef_directive_one_lineContext* ifndef_directive_one_line();
-
   class  Ifndef_directiveContext : public antlr4::ParserRuleContext {
   public:
     Ifndef_directiveContext(antlr4::ParserRuleContext *parent, size_t invokingState);
@@ -773,23 +712,6 @@
 
   Ifndef_directive_in_macro_bodyContext* ifndef_directive_in_macro_body();
 
-  class  Elsif_directive_one_lineContext : public antlr4::ParserRuleContext {
-  public:
-    Elsif_directive_one_lineContext(antlr4::ParserRuleContext *parent, size_t invokingState);
-    virtual size_t getRuleIndex() const override;
-    Elsif_directiveContext *elsif_directive();
-    antlr4::tree::TerminalNode *One_line_comment();
-    antlr4::tree::TerminalNode *CR();
-    std::vector<antlr4::tree::TerminalNode *> Spaces();
-    antlr4::tree::TerminalNode* Spaces(size_t i);
-
-    virtual void enterRule(antlr4::tree::ParseTreeListener *listener) override;
-    virtual void exitRule(antlr4::tree::ParseTreeListener *listener) override;
-   
-  };
-
-  Elsif_directive_one_lineContext* elsif_directive_one_line();
-
   class  Elsif_directiveContext : public antlr4::ParserRuleContext {
   public:
     Elsif_directiveContext(antlr4::ParserRuleContext *parent, size_t invokingState);
@@ -824,23 +746,6 @@
 
   Elsif_directive_in_macro_bodyContext* elsif_directive_in_macro_body();
 
-  class  Elseif_directive_one_lineContext : public antlr4::ParserRuleContext {
-  public:
-    Elseif_directive_one_lineContext(antlr4::ParserRuleContext *parent, size_t invokingState);
-    virtual size_t getRuleIndex() const override;
-    Elseif_directiveContext *elseif_directive();
-    antlr4::tree::TerminalNode *One_line_comment();
-    antlr4::tree::TerminalNode *CR();
-    std::vector<antlr4::tree::TerminalNode *> Spaces();
-    antlr4::tree::TerminalNode* Spaces(size_t i);
-
-    virtual void enterRule(antlr4::tree::ParseTreeListener *listener) override;
-    virtual void exitRule(antlr4::tree::ParseTreeListener *listener) override;
-   
-  };
-
-  Elseif_directive_one_lineContext* elseif_directive_one_line();
-
   class  Elseif_directiveContext : public antlr4::ParserRuleContext {
   public:
     Elseif_directiveContext(antlr4::ParserRuleContext *parent, size_t invokingState);
@@ -875,23 +780,6 @@
 
   Elseif_directive_in_macro_bodyContext* elseif_directive_in_macro_body();
 
-  class  Else_directive_one_lineContext : public antlr4::ParserRuleContext {
-  public:
-    Else_directive_one_lineContext(antlr4::ParserRuleContext *parent, size_t invokingState);
-    virtual size_t getRuleIndex() const override;
-    Else_directiveContext *else_directive();
-    antlr4::tree::TerminalNode *One_line_comment();
-    antlr4::tree::TerminalNode *CR();
-    std::vector<antlr4::tree::TerminalNode *> Spaces();
-    antlr4::tree::TerminalNode* Spaces(size_t i);
-
-    virtual void enterRule(antlr4::tree::ParseTreeListener *listener) override;
-    virtual void exitRule(antlr4::tree::ParseTreeListener *listener) override;
-   
-  };
-
-  Else_directive_one_lineContext* else_directive_one_line();
-
   class  Else_directiveContext : public antlr4::ParserRuleContext {
   public:
     Else_directiveContext(antlr4::ParserRuleContext *parent, size_t invokingState);
@@ -905,24 +793,6 @@
 
   Else_directiveContext* else_directive();
 
-  class  Endif_directive_one_lineContext : public antlr4::ParserRuleContext {
-  public:
-    Endif_directive_one_lineContext(antlr4::ParserRuleContext *parent, size_t invokingState);
-    virtual size_t getRuleIndex() const override;
-    antlr4::tree::TerminalNode *TICK_ENDIF();
-    antlr4::tree::TerminalNode *One_line_comment();
-    std::vector<antlr4::tree::TerminalNode *> Spaces();
-    antlr4::tree::TerminalNode* Spaces(size_t i);
-    antlr4::tree::TerminalNode *CR();
-    antlr4::tree::TerminalNode *EOF();
-
-    virtual void enterRule(antlr4::tree::ParseTreeListener *listener) override;
-    virtual void exitRule(antlr4::tree::ParseTreeListener *listener) override;
-   
-  };
-
-  Endif_directive_one_lineContext* endif_directive_one_line();
-
   class  Endif_directiveContext : public antlr4::ParserRuleContext {
   public:
     Endif_directiveContext(antlr4::ParserRuleContext *parent, size_t invokingState);
diff --git a/src/parser/SV3_1aPpParser.interp b/src/parser/SV3_1aPpParser.interp
index 8e2907a..1cecbd1 100644
--- a/src/parser/SV3_1aPpParser.interp
+++ b/src/parser/SV3_1aPpParser.interp
@@ -211,21 +211,15 @@
 timescale_directive_one_line
 timescale_directive
 undef_directive
-ifdef_directive_one_line
 ifdef_directive
 ifdef_directive_in_macro_body
-ifndef_directive_one_line
 ifndef_directive
 ifndef_directive_in_macro_body
-elsif_directive_one_line
 elsif_directive
 elsif_directive_in_macro_body
-elseif_directive_one_line
 elseif_directive
 elseif_directive_in_macro_body
-else_directive_one_line
 else_directive
-endif_directive_one_line
 endif_directive
 resetall_directive_one_line
 resetall_directive
@@ -336,4 +330,4 @@
 
 
 atn:
-[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 3, 95, 1682, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 4, 17, 9, 17, 4, 18, 9, 18, 4, 19, 9, 19, 4, 20, 9, 20, 4, 21, 9, 21, 4, 22, 9, 22, 4, 23, 9, 23, 4, 24, 9, 24, 4, 25, 9, 25, 4, 26, 9, 26, 4, 27, 9, 27, 4, 28, 9, 28, 4, 29, 9, 29, 4, 30, 9, 30, 4, 31, 9, 31, 4, 32, 9, 32, 4, 33, 9, 33, 4, 34, 9, 34, 4, 35, 9, 35, 4, 36, 9, 36, 4, 37, 9, 37, 4, 38, 9, 38, 4, 39, 9, 39, 4, 40, 9, 40, 4, 41, 9, 41, 4, 42, 9, 42, 4, 43, 9, 43, 4, 44, 9, 44, 4, 45, 9, 45, 4, 46, 9, 46, 4, 47, 9, 47, 4, 48, 9, 48, 4, 49, 9, 49, 4, 50, 9, 50, 4, 51, 9, 51, 4, 52, 9, 52, 4, 53, 9, 53, 4, 54, 9, 54, 4, 55, 9, 55, 4, 56, 9, 56, 4, 57, 9, 57, 4, 58, 9, 58, 4, 59, 9, 59, 4, 60, 9, 60, 4, 61, 9, 61, 4, 62, 9, 62, 4, 63, 9, 63, 4, 64, 9, 64, 4, 65, 9, 65, 4, 66, 9, 66, 4, 67, 9, 67, 4, 68, 9, 68, 4, 69, 9, 69, 4, 70, 9, 70, 4, 71, 9, 71, 4, 72, 9, 72, 4, 73, 9, 73, 4, 74, 9, 74, 4, 75, 9, 75, 4, 76, 9, 76, 4, 77, 9, 77, 4, 78, 9, 78, 4, 79, 9, 79, 4, 80, 9, 80, 4, 81, 9, 81, 4, 82, 9, 82, 4, 83, 9, 83, 4, 84, 9, 84, 4, 85, 9, 85, 4, 86, 9, 86, 4, 87, 9, 87, 4, 88, 9, 88, 4, 89, 9, 89, 4, 90, 9, 90, 4, 91, 9, 91, 4, 92, 9, 92, 4, 93, 9, 93, 4, 94, 9, 94, 4, 95, 9, 95, 4, 96, 9, 96, 4, 97, 9, 97, 4, 98, 9, 98, 4, 99, 9, 99, 4, 100, 9, 100, 4, 101, 9, 101, 4, 102, 9, 102, 4, 103, 9, 103, 4, 104, 9, 104, 4, 105, 9, 105, 4, 106, 9, 106, 4, 107, 9, 107, 4, 108, 9, 108, 4, 109, 9, 109, 4, 110, 9, 110, 4, 111, 9, 111, 4, 112, 9, 112, 4, 113, 9, 113, 4, 114, 9, 114, 4, 115, 9, 115, 4, 116, 9, 116, 4, 117, 9, 117, 4, 118, 9, 118, 4, 119, 9, 119, 4, 120, 9, 120, 4, 121, 9, 121, 4, 122, 9, 122, 4, 123, 9, 123, 4, 124, 9, 124, 4, 125, 9, 125, 4, 126, 9, 126, 4, 127, 9, 127, 4, 128, 9, 128, 4, 129, 9, 129, 4, 130, 9, 130, 4, 131, 9, 131, 4, 132, 9, 132, 4, 133, 9, 133, 4, 134, 9, 134, 4, 135, 9, 135, 4, 136, 9, 136, 4, 137, 9, 137, 4, 138, 9, 138, 4, 139, 9, 139, 4, 140, 9, 140, 4, 141, 9, 141, 4, 142, 9, 142, 4, 143, 9, 143, 3, 2, 7, 2, 288, 10, 2, 12, 2, 14, 2, 291, 11, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 3, 366, 10, 3, 3, 4, 3, 4, 7, 4, 370, 10, 4, 12, 4, 14, 4, 373, 11, 4, 3, 4, 3, 4, 3, 4, 3, 4, 3, 4, 5, 4, 380, 10, 4, 3, 5, 3, 5, 7, 5, 384, 10, 5, 12, 5, 14, 5, 387, 11, 5, 3, 5, 3, 5, 3, 6, 7, 6, 392, 10, 6, 12, 6, 14, 6, 395, 11, 6, 3, 6, 3, 6, 7, 6, 399, 10, 6, 12, 6, 14, 6, 402, 11, 6, 7, 6, 404, 10, 6, 12, 6, 14, 6, 407, 11, 6, 3, 7, 3, 7, 3, 8, 3, 8, 3, 9, 3, 9, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 5, 10, 420, 10, 10, 3, 11, 3, 11, 7, 11, 424, 10, 11, 12, 11, 14, 11, 427, 11, 11, 3, 11, 3, 11, 3, 12, 3, 12, 3, 12, 3, 12, 3, 12, 3, 12, 5, 12, 437, 10, 12, 3, 13, 3, 13, 7, 13, 441, 10, 13, 12, 13, 14, 13, 444, 11, 13, 3, 13, 3, 13, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 15, 3, 15, 7, 15, 457, 10, 15, 12, 15, 14, 15, 460, 11, 15, 3, 15, 3, 15, 3, 16, 3, 16, 3, 16, 3, 16, 3, 17, 3, 17, 3, 18, 3, 18, 3, 19, 3, 19, 7, 19, 474, 10, 19, 12, 19, 14, 19, 477, 11, 19, 3, 19, 3, 19, 3, 20, 3, 20, 3, 20, 3, 21, 3, 21, 3, 21, 3, 21, 3, 21, 5, 21, 489, 10, 21, 3, 22, 3, 22, 7, 22, 493, 10, 22, 12, 22, 14, 22, 496, 11, 22, 3, 22, 3, 22, 7, 22, 500, 10, 22, 12, 22, 14, 22, 503, 11, 22, 3, 22, 3, 22, 3, 22, 5, 22, 508, 10, 22, 3, 22, 6, 22, 511, 10, 22, 13, 22, 14, 22, 512, 7, 22, 515, 10, 22, 12, 22, 14, 22, 518, 11, 22, 3, 22, 5, 22, 521, 10, 22, 3, 23, 3, 23, 3, 23, 3, 23, 3, 23, 5, 23, 528, 10, 23, 3, 24, 3, 24, 3, 24, 3, 24, 3, 24, 5, 24, 535, 10, 24, 3, 25, 3, 25, 7, 25, 539, 10, 25, 12, 25, 14, 25, 542, 11, 25, 3, 25, 3, 25, 7, 25, 546, 10, 25, 12, 25, 14, 25, 549, 11, 25, 3, 25, 3, 25, 3, 25, 5, 25, 554, 10, 25, 3, 25, 6, 25, 557, 10, 25, 13, 25, 14, 25, 558, 7, 25, 561, 10, 25, 12, 25, 14, 25, 564, 11, 25, 3, 25, 5, 25, 567, 10, 25, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 5, 26, 574, 10, 26, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 5, 27, 581, 10, 27, 3, 28, 3, 28, 7, 28, 585, 10, 28, 12, 28, 14, 28, 588, 11, 28, 3, 28, 3, 28, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 5, 29, 597, 10, 29, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 5, 30, 604, 10, 30, 3, 31, 3, 31, 7, 31, 608, 10, 31, 12, 31, 14, 31, 611, 11, 31, 3, 31, 3, 31, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 5, 32, 620, 10, 32, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 5, 33, 627, 10, 33, 3, 34, 3, 34, 7, 34, 631, 10, 34, 12, 34, 14, 34, 634, 11, 34, 3, 34, 3, 34, 3, 35, 3, 35, 3, 36, 3, 36, 7, 36, 642, 10, 36, 12, 36, 14, 36, 645, 11, 36, 3, 36, 3, 36, 3, 36, 7, 36, 650, 10, 36, 12, 36, 14, 36, 653, 11, 36, 3, 36, 3, 36, 3, 36, 5, 36, 658, 10, 36, 3, 37, 3, 37, 7, 37, 662, 10, 37, 12, 37, 14, 37, 665, 11, 37, 3, 37, 3, 37, 5, 37, 669, 10, 37, 3, 38, 3, 38, 7, 38, 673, 10, 38, 12, 38, 14, 38, 676, 11, 38, 3, 38, 3, 38, 3, 39, 3, 39, 3, 40, 3, 40, 7, 40, 684, 10, 40, 12, 40, 14, 40, 687, 11, 40, 3, 40, 3, 40, 3, 41, 3, 41, 3, 41, 3, 41, 3, 42, 3, 42, 7, 42, 697, 10, 42, 12, 42, 14, 42, 700, 11, 42, 3, 42, 3, 42, 3, 43, 3, 43, 3, 44, 3, 44, 7, 44, 708, 10, 44, 12, 44, 14, 44, 711, 11, 44, 3, 44, 3, 44, 3, 45, 3, 45, 3, 45, 3, 45, 3, 45, 3, 45, 7, 45, 721, 10, 45, 12, 45, 14, 45, 724, 11, 45, 7, 45, 726, 10, 45, 12, 45, 14, 45, 729, 11, 45, 3, 46, 3, 46, 7, 46, 733, 10, 46, 12, 46, 14, 46, 736, 11, 46, 3, 46, 3, 46, 3, 47, 3, 47, 3, 48, 3, 48, 7, 48, 744, 10, 48, 12, 48, 14, 48, 747, 11, 48, 3, 48, 3, 48, 3, 49, 3, 49, 3, 50, 3, 50, 7, 50, 755, 10, 50, 12, 50, 14, 50, 758, 11, 50, 3, 50, 3, 50, 3, 51, 3, 51, 3, 52, 3, 52, 7, 52, 766, 10, 52, 12, 52, 14, 52, 769, 11, 52, 3, 52, 3, 52, 3, 53, 3, 53, 3, 54, 3, 54, 7, 54, 777, 10, 54, 12, 54, 14, 54, 780, 11, 54, 3, 54, 3, 54, 3, 55, 3, 55, 3, 56, 3, 56, 7, 56, 788, 10, 56, 12, 56, 14, 56, 791, 11, 56, 3, 56, 3, 56, 3, 57, 3, 57, 3, 58, 3, 58, 7, 58, 799, 10, 58, 12, 58, 14, 58, 802, 11, 58, 3, 58, 3, 58, 3, 59, 3, 59, 3, 60, 3, 60, 7, 60, 810, 10, 60, 12, 60, 14, 60, 813, 11, 60, 3, 60, 3, 60, 3, 61, 3, 61, 3, 62, 3, 62, 7, 62, 821, 10, 62, 12, 62, 14, 62, 824, 11, 62, 3, 62, 3, 62, 3, 63, 3, 63, 3, 64, 3, 64, 3, 64, 3, 65, 3, 65, 6, 65, 835, 10, 65, 13, 65, 14, 65, 836, 3, 66, 3, 66, 7, 66, 841, 10, 66, 12, 66, 14, 66, 844, 11, 66, 3, 66, 3, 66, 3, 67, 3, 67, 3, 68, 3, 68, 7, 68, 852, 10, 68, 12, 68, 14, 68, 855, 11, 68, 3, 68, 3, 68, 3, 69, 3, 69, 3, 70, 3, 70, 7, 70, 863, 10, 70, 12, 70, 14, 70, 866, 11, 70, 3, 70, 3, 70, 3, 71, 3, 71, 3, 72, 3, 72, 7, 72, 874, 10, 72, 12, 72, 14, 72, 877, 11, 72, 3, 72, 3, 72, 3, 73, 3, 73, 3, 74, 3, 74, 7, 74, 885, 10, 74, 12, 74, 14, 74, 888, 11, 74, 3, 74, 3, 74, 3, 75, 3, 75, 3, 76, 3, 76, 7, 76, 896, 10, 76, 12, 76, 14, 76, 899, 11, 76, 3, 76, 3, 76, 3, 77, 3, 77, 3, 78, 3, 78, 7, 78, 907, 10, 78, 12, 78, 14, 78, 910, 11, 78, 3, 78, 3, 78, 3, 79, 3, 79, 3, 80, 3, 80, 7, 80, 918, 10, 80, 12, 80, 14, 80, 921, 11, 80, 3, 80, 3, 80, 3, 81, 3, 81, 3, 82, 3, 82, 7, 82, 929, 10, 82, 12, 82, 14, 82, 932, 11, 82, 3, 82, 3, 82, 3, 83, 3, 83, 3, 84, 3, 84, 7, 84, 940, 10, 84, 12, 84, 14, 84, 943, 11, 84, 3, 84, 3, 84, 3, 85, 3, 85, 3, 86, 3, 86, 7, 86, 951, 10, 86, 12, 86, 14, 86, 954, 11, 86, 3, 86, 3, 86, 3, 87, 3, 87, 3, 88, 3, 88, 7, 88, 962, 10, 88, 12, 88, 14, 88, 965, 11, 88, 3, 88, 3, 88, 3, 89, 3, 89, 3, 90, 3, 90, 7, 90, 973, 10, 90, 12, 90, 14, 90, 976, 11, 90, 3, 90, 3, 90, 3, 91, 3, 91, 3, 91, 3, 91, 3, 92, 3, 92, 7, 92, 986, 10, 92, 12, 92, 14, 92, 989, 11, 92, 3, 92, 3, 92, 3, 93, 3, 93, 3, 93, 3, 93, 3, 93, 5, 93, 998, 10, 93, 3, 94, 3, 94, 7, 94, 1002, 10, 94, 12, 94, 14, 94, 1005, 11, 94, 3, 94, 3, 94, 3, 95, 3, 95, 3, 95, 3, 95, 3, 96, 3, 96, 7, 96, 1015, 10, 96, 12, 96, 14, 96, 1018, 11, 96, 3, 96, 3, 96, 3, 97, 3, 97, 3, 98, 3, 98, 7, 98, 1026, 10, 98, 12, 98, 14, 98, 1029, 11, 98, 3, 98, 3, 98, 3, 99, 3, 99, 3, 100, 3, 100, 7, 100, 1037, 10, 100, 12, 100, 14, 100, 1040, 11, 100, 3, 100, 3, 100, 3, 101, 3, 101, 3, 102, 3, 102, 7, 102, 1048, 10, 102, 12, 102, 14, 102, 1051, 11, 102, 3, 102, 3, 102, 3, 103, 3, 103, 3, 104, 3, 104, 7, 104, 1059, 10, 104, 12, 104, 14, 104, 1062, 11, 104, 3, 104, 3, 104, 3, 105, 3, 105, 3, 106, 3, 106, 3, 107, 3, 107, 3, 108, 3, 108, 3, 109, 3, 109, 3, 110, 3, 110, 3, 111, 3, 111, 3, 112, 3, 112, 3, 113, 3, 113, 3, 114, 3, 114, 3, 115, 3, 115, 3, 116, 3, 116, 3, 117, 3, 117, 3, 118, 3, 118, 3, 119, 3, 119, 3, 120, 3, 120, 3, 121, 3, 121, 3, 121, 3, 121, 7, 121, 1102, 10, 121, 12, 121, 14, 121, 1105, 11, 121, 3, 121, 3, 121, 3, 122, 3, 122, 3, 122, 3, 122, 7, 122, 1113, 10, 122, 12, 122, 14, 122, 1116, 11, 122, 3, 122, 3, 122, 3, 123, 3, 123, 3, 123, 3, 123, 3, 123, 7, 123, 1125, 10, 123, 12, 123, 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2, 1515, 1491, 3, 2, 2, 2, 1515, 1492, 3, 2, 2, 2, 1515, 1493, 3, 2, 2, 2, 1515, 1494, 3, 2, 2, 2, 1515, 1495, 3, 2, 2, 2, 1515, 1496, 3, 2, 2, 2, 1515, 1497, 3, 2, 2, 2, 1515, 1498, 3, 2, 2, 2, 1515, 1499, 3, 2, 2, 2, 1515, 1500, 3, 2, 2, 2, 1515, 1501, 3, 2, 2, 2, 1515, 1502, 3, 2, 2, 2, 1515, 1503, 3, 2, 2, 2, 1515, 1504, 3, 2, 2, 2, 1515, 1505, 3, 2, 2, 2, 1515, 1506, 3, 2, 2, 2, 1515, 1507, 3, 2, 2, 2, 1515, 1508, 3, 2, 2, 2, 1515, 1509, 3, 2, 2, 2, 1515, 1510, 3, 2, 2, 2, 1515, 1511, 3, 2, 2, 2, 1515, 1512, 3, 2, 2, 2, 1515, 1513, 3, 2, 2, 2, 1515, 1514, 3, 2, 2, 2, 1516, 265, 3, 2, 2, 2, 1517, 1518, 7, 71, 2, 2, 1518, 267, 3, 2, 2, 2, 1519, 1520, 7, 89, 2, 2, 1520, 269, 3, 2, 2, 2, 1521, 1535, 7, 72, 2, 2, 1522, 1535, 5, 14, 8, 2, 1523, 1535, 7, 73, 2, 2, 1524, 1535, 7, 77, 2, 2, 1525, 1535, 7, 71, 2, 2, 1526, 1535, 7, 94, 2, 2, 1527, 1535, 7, 90, 2, 2, 1528, 1535, 7, 91, 2, 2, 1529, 1535, 7, 92, 2, 2, 1530, 1535, 7, 93, 2, 2, 1531, 1535, 7, 95, 2, 2, 1532, 1535, 5, 268, 135, 2, 1533, 1535, 5, 6, 4, 2, 1534, 1521, 3, 2, 2, 2, 1534, 1522, 3, 2, 2, 2, 1534, 1523, 3, 2, 2, 2, 1534, 1524, 3, 2, 2, 2, 1534, 1525, 3, 2, 2, 2, 1534, 1526, 3, 2, 2, 2, 1534, 1527, 3, 2, 2, 2, 1534, 1528, 3, 2, 2, 2, 1534, 1529, 3, 2, 2, 2, 1534, 1530, 3, 2, 2, 2, 1534, 1531, 3, 2, 2, 2, 1534, 1532, 3, 2, 2, 2, 1534, 1533, 3, 2, 2, 2, 1535, 271, 3, 2, 2, 2, 1536, 1557, 7, 72, 2, 2, 1537, 1557, 5, 14, 8, 2, 1538, 1557, 7, 73, 2, 2, 1539, 1557, 7, 77, 2, 2, 1540, 1557, 7, 79, 2, 2, 1541, 1557, 7, 84, 2, 2, 1542, 1557, 7, 85, 2, 2, 1543, 1557, 7, 86, 2, 2, 1544, 1557, 7, 87, 2, 2, 1545, 1557, 7, 88, 2, 2, 1546, 1557, 7, 94, 2, 2, 1547, 1557, 7, 90, 2, 2, 1548, 1557, 7, 91, 2, 2, 1549, 1557, 7, 92, 2, 2, 1550, 1557, 7, 93, 2, 2, 1551, 1557, 7, 95, 2, 2, 1552, 1557, 5, 268, 135, 2, 1553, 1557, 7, 75, 2, 2, 1554, 1557, 5, 16, 9, 2, 1555, 1557, 7, 78, 2, 2, 1556, 1536, 3, 2, 2, 2, 1556, 1537, 3, 2, 2, 2, 1556, 1538, 3, 2, 2, 2, 1556, 1539, 3, 2, 2, 2, 1556, 1540, 3, 2, 2, 2, 1556, 1541, 3, 2, 2, 2, 1556, 1542, 3, 2, 2, 2, 1556, 1543, 3, 2, 2, 2, 1556, 1544, 3, 2, 2, 2, 1556, 1545, 3, 2, 2, 2, 1556, 1546, 3, 2, 2, 2, 1556, 1547, 3, 2, 2, 2, 1556, 1548, 3, 2, 2, 2, 1556, 1549, 3, 2, 2, 2, 1556, 1550, 3, 2, 2, 2, 1556, 1551, 3, 2, 2, 2, 1556, 1552, 3, 2, 2, 2, 1556, 1553, 3, 2, 2, 2, 1556, 1554, 3, 2, 2, 2, 1556, 1555, 3, 2, 2, 2, 1557, 273, 3, 2, 2, 2, 115, 277, 353, 359, 367, 373, 381, 388, 393, 407, 413, 424, 430, 446, 463, 476, 483, 490, 497, 504, 511, 518, 525, 532, 540, 545, 551, 562, 575, 586, 599, 604, 611, 622, 633, 644, 655, 666, 677, 688, 699, 713, 719, 730, 741, 752, 763, 774, 785, 796, 807, 818, 829, 840, 851, 864, 874, 880, 893, 904, 915, 926, 937, 980, 991, 1003, 1021, 1025, 1042, 1047, 1051, 1055, 1062, 1070, 1075, 1082, 1086, 1092, 1102, 1105, 1169, 1176, 1183, 1188, 1195, 1202, 1209, 1214, 1219, 1224, 1231, 1261, 1263, 1270, 1303, 1305, 1312, 1316, 1346, 1348, 1377, 1379, 1400, 1419, 1438, 1440, 1460, 1462, 1482, 1484, 1488, 1515, 1534, 1556]
\ No newline at end of file
diff --git a/src/parser/SV3_1aPpParserBaseListener.h b/src/parser/SV3_1aPpParserBaseListener.h
index b7be32c..25cb6b2 100644
--- a/src/parser/SV3_1aPpParserBaseListener.h
+++ b/src/parser/SV3_1aPpParserBaseListener.h
@@ -79,51 +79,33 @@
   virtual void enterUndef_directive(SV3_1aPpParser::Undef_directiveContext * /*ctx*/) override { }
   virtual void exitUndef_directive(SV3_1aPpParser::Undef_directiveContext * /*ctx*/) override { }
 
-  virtual void enterIfdef_directive_one_line(SV3_1aPpParser::Ifdef_directive_one_lineContext * /*ctx*/) override { }
-  virtual void exitIfdef_directive_one_line(SV3_1aPpParser::Ifdef_directive_one_lineContext * /*ctx*/) override { }
-
   virtual void enterIfdef_directive(SV3_1aPpParser::Ifdef_directiveContext * /*ctx*/) override { }
   virtual void exitIfdef_directive(SV3_1aPpParser::Ifdef_directiveContext * /*ctx*/) override { }
 
   virtual void enterIfdef_directive_in_macro_body(SV3_1aPpParser::Ifdef_directive_in_macro_bodyContext * /*ctx*/) override { }
   virtual void exitIfdef_directive_in_macro_body(SV3_1aPpParser::Ifdef_directive_in_macro_bodyContext * /*ctx*/) override { }
 
-  virtual void enterIfndef_directive_one_line(SV3_1aPpParser::Ifndef_directive_one_lineContext * /*ctx*/) override { }
-  virtual void exitIfndef_directive_one_line(SV3_1aPpParser::Ifndef_directive_one_lineContext * /*ctx*/) override { }
-
   virtual void enterIfndef_directive(SV3_1aPpParser::Ifndef_directiveContext * /*ctx*/) override { }
   virtual void exitIfndef_directive(SV3_1aPpParser::Ifndef_directiveContext * /*ctx*/) override { }
 
   virtual void enterIfndef_directive_in_macro_body(SV3_1aPpParser::Ifndef_directive_in_macro_bodyContext * /*ctx*/) override { }
   virtual void exitIfndef_directive_in_macro_body(SV3_1aPpParser::Ifndef_directive_in_macro_bodyContext * /*ctx*/) override { }
 
-  virtual void enterElsif_directive_one_line(SV3_1aPpParser::Elsif_directive_one_lineContext * /*ctx*/) override { }
-  virtual void exitElsif_directive_one_line(SV3_1aPpParser::Elsif_directive_one_lineContext * /*ctx*/) override { }
-
   virtual void enterElsif_directive(SV3_1aPpParser::Elsif_directiveContext * /*ctx*/) override { }
   virtual void exitElsif_directive(SV3_1aPpParser::Elsif_directiveContext * /*ctx*/) override { }
 
   virtual void enterElsif_directive_in_macro_body(SV3_1aPpParser::Elsif_directive_in_macro_bodyContext * /*ctx*/) override { }
   virtual void exitElsif_directive_in_macro_body(SV3_1aPpParser::Elsif_directive_in_macro_bodyContext * /*ctx*/) override { }
 
-  virtual void enterElseif_directive_one_line(SV3_1aPpParser::Elseif_directive_one_lineContext * /*ctx*/) override { }
-  virtual void exitElseif_directive_one_line(SV3_1aPpParser::Elseif_directive_one_lineContext * /*ctx*/) override { }
-
   virtual void enterElseif_directive(SV3_1aPpParser::Elseif_directiveContext * /*ctx*/) override { }
   virtual void exitElseif_directive(SV3_1aPpParser::Elseif_directiveContext * /*ctx*/) override { }
 
   virtual void enterElseif_directive_in_macro_body(SV3_1aPpParser::Elseif_directive_in_macro_bodyContext * /*ctx*/) override { }
   virtual void exitElseif_directive_in_macro_body(SV3_1aPpParser::Elseif_directive_in_macro_bodyContext * /*ctx*/) override { }
 
-  virtual void enterElse_directive_one_line(SV3_1aPpParser::Else_directive_one_lineContext * /*ctx*/) override { }
-  virtual void exitElse_directive_one_line(SV3_1aPpParser::Else_directive_one_lineContext * /*ctx*/) override { }
-
   virtual void enterElse_directive(SV3_1aPpParser::Else_directiveContext * /*ctx*/) override { }
   virtual void exitElse_directive(SV3_1aPpParser::Else_directiveContext * /*ctx*/) override { }
 
-  virtual void enterEndif_directive_one_line(SV3_1aPpParser::Endif_directive_one_lineContext * /*ctx*/) override { }
-  virtual void exitEndif_directive_one_line(SV3_1aPpParser::Endif_directive_one_lineContext * /*ctx*/) override { }
-
   virtual void enterEndif_directive(SV3_1aPpParser::Endif_directiveContext * /*ctx*/) override { }
   virtual void exitEndif_directive(SV3_1aPpParser::Endif_directiveContext * /*ctx*/) override { }
 
diff --git a/src/parser/SV3_1aPpParserListener.h b/src/parser/SV3_1aPpParserListener.h
index 3b5084a..e8b40a5 100644
--- a/src/parser/SV3_1aPpParserListener.h
+++ b/src/parser/SV3_1aPpParserListener.h
@@ -77,51 +77,33 @@
   virtual void enterUndef_directive(SV3_1aPpParser::Undef_directiveContext *ctx) = 0;
   virtual void exitUndef_directive(SV3_1aPpParser::Undef_directiveContext *ctx) = 0;
 
-  virtual void enterIfdef_directive_one_line(SV3_1aPpParser::Ifdef_directive_one_lineContext *ctx) = 0;
-  virtual void exitIfdef_directive_one_line(SV3_1aPpParser::Ifdef_directive_one_lineContext *ctx) = 0;
-
   virtual void enterIfdef_directive(SV3_1aPpParser::Ifdef_directiveContext *ctx) = 0;
   virtual void exitIfdef_directive(SV3_1aPpParser::Ifdef_directiveContext *ctx) = 0;
 
   virtual void enterIfdef_directive_in_macro_body(SV3_1aPpParser::Ifdef_directive_in_macro_bodyContext *ctx) = 0;
   virtual void exitIfdef_directive_in_macro_body(SV3_1aPpParser::Ifdef_directive_in_macro_bodyContext *ctx) = 0;
 
-  virtual void enterIfndef_directive_one_line(SV3_1aPpParser::Ifndef_directive_one_lineContext *ctx) = 0;
-  virtual void exitIfndef_directive_one_line(SV3_1aPpParser::Ifndef_directive_one_lineContext *ctx) = 0;
-
   virtual void enterIfndef_directive(SV3_1aPpParser::Ifndef_directiveContext *ctx) = 0;
   virtual void exitIfndef_directive(SV3_1aPpParser::Ifndef_directiveContext *ctx) = 0;
 
   virtual void enterIfndef_directive_in_macro_body(SV3_1aPpParser::Ifndef_directive_in_macro_bodyContext *ctx) = 0;
   virtual void exitIfndef_directive_in_macro_body(SV3_1aPpParser::Ifndef_directive_in_macro_bodyContext *ctx) = 0;
 
-  virtual void enterElsif_directive_one_line(SV3_1aPpParser::Elsif_directive_one_lineContext *ctx) = 0;
-  virtual void exitElsif_directive_one_line(SV3_1aPpParser::Elsif_directive_one_lineContext *ctx) = 0;
-
   virtual void enterElsif_directive(SV3_1aPpParser::Elsif_directiveContext *ctx) = 0;
   virtual void exitElsif_directive(SV3_1aPpParser::Elsif_directiveContext *ctx) = 0;
 
   virtual void enterElsif_directive_in_macro_body(SV3_1aPpParser::Elsif_directive_in_macro_bodyContext *ctx) = 0;
   virtual void exitElsif_directive_in_macro_body(SV3_1aPpParser::Elsif_directive_in_macro_bodyContext *ctx) = 0;
 
-  virtual void enterElseif_directive_one_line(SV3_1aPpParser::Elseif_directive_one_lineContext *ctx) = 0;
-  virtual void exitElseif_directive_one_line(SV3_1aPpParser::Elseif_directive_one_lineContext *ctx) = 0;
-
   virtual void enterElseif_directive(SV3_1aPpParser::Elseif_directiveContext *ctx) = 0;
   virtual void exitElseif_directive(SV3_1aPpParser::Elseif_directiveContext *ctx) = 0;
 
   virtual void enterElseif_directive_in_macro_body(SV3_1aPpParser::Elseif_directive_in_macro_bodyContext *ctx) = 0;
   virtual void exitElseif_directive_in_macro_body(SV3_1aPpParser::Elseif_directive_in_macro_bodyContext *ctx) = 0;
 
-  virtual void enterElse_directive_one_line(SV3_1aPpParser::Else_directive_one_lineContext *ctx) = 0;
-  virtual void exitElse_directive_one_line(SV3_1aPpParser::Else_directive_one_lineContext *ctx) = 0;
-
   virtual void enterElse_directive(SV3_1aPpParser::Else_directiveContext *ctx) = 0;
   virtual void exitElse_directive(SV3_1aPpParser::Else_directiveContext *ctx) = 0;
 
-  virtual void enterEndif_directive_one_line(SV3_1aPpParser::Endif_directive_one_lineContext *ctx) = 0;
-  virtual void exitEndif_directive_one_line(SV3_1aPpParser::Endif_directive_one_lineContext *ctx) = 0;
-
   virtual void enterEndif_directive(SV3_1aPpParser::Endif_directiveContext *ctx) = 0;
   virtual void exitEndif_directive(SV3_1aPpParser::Endif_directiveContext *ctx) = 0;
 
diff --git a/tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log b/tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log
index 1555a47..fd86a7c 100644
--- a/tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log
+++ b/tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log
@@ -13,6 +13,7 @@
 ALL FILES LOG: ../../build/tests/DiffSimpleIncludeAndMacros/slpp_all/surelog.log
 
 DIFFS:
+../../build/tests/DiffSimpleIncludeAndMacros/slpp_unit/file.lst and ../../build/tests/DiffSimpleIncludeAndMacros/slpp_all/file.lst 
 ../../build/tests/DiffSimpleIncludeAndMacros/slpp_unit/work/top_3.v and ../../build/tests/DiffSimpleIncludeAndMacros/slpp_all/work/top_3.v 
 ../../build/tests/DiffSimpleIncludeAndMacros/slpp_unit/work/top_4.v and ../../build/tests/DiffSimpleIncludeAndMacros/slpp_all/work/top_4.v 
 
diff --git a/tests/Escape/Escape.log b/tests/Escape/Escape.log
index 230e1a6..8729859 100644
--- a/tests/Escape/Escape.log
+++ b/tests/Escape/Escape.log
@@ -16,13 +16,13 @@
 
 [WARNI:PA0205] top.v:27 No timescale set for "bottom2".
 
-[WARNI:PA0205] top.v:36 No timescale set for "bottom3".
+[WARNI:PA0205] top.v:40 No timescale set for "bottom3".
 
 [WARNI:PA0205] top1.v:2 No timescale set for "my_interface".
 
 [ERROR:PA0206] top.v:27 Missing timeunit/timeprecision for "bottom2".
 
-[ERROR:PA0206] top.v:36 Missing timeunit/timeprecision for "bottom3".
+[ERROR:PA0206] top.v:40 Missing timeunit/timeprecision for "bottom3".
 
 [ERROR:PA0206] top1.v:2 Missing timeunit/timeprecision for "my_interface".
 
@@ -32,7 +32,7 @@
 
 [INFO :CP0303] top.v:27 Compile module "work@bottom2".
 
-[INFO :CP0303] top.v:36 Compile module "work@bottom3".
+[INFO :CP0303] top.v:40 Compile module "work@bottom3".
 
 [INFO :CP0303] top1.v:32 Compile module "work@middle".
 
@@ -65,14 +65,14 @@
                top.v:27 previous definition.
 
 [WARNI:EL0505] top1.v:46 Multiply defined module "work@bottom3",
-               top.v:36 previous definition.
+               top.v:40 previous definition.
 
 [WARNI:EL0505] top1.v:15 Multiply defined module "work@top",
                top.v:2 previous definition.
 
 [NOTE :EL0504] Multiple top level modules in design.
 
-[WARNI:EL0500] top.v:38 Cannot find a module definition for "work@bottom3::ddr".
+[WARNI:EL0500] top.v:42 Cannot find a module definition for "work@bottom3::ddr".
 
 [NOTE :EL0508] Nb Top level modules: 3.
 
diff --git a/tests/SimpleConstraint/SimpleConstraint.log b/tests/SimpleConstraint/SimpleConstraint.log
index 4c62824..8450750 100644
--- a/tests/SimpleConstraint/SimpleConstraint.log
+++ b/tests/SimpleConstraint/SimpleConstraint.log
@@ -6,7 +6,11 @@
 
 [INFO :PP0122] Preprocessing source file "top.sv".
 
-Preprocessing took 0.010s
+Preprocessing took 0.012s
+
+Preprocessing took 0.012s
+PP SSL Parsing: 0.002 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
+PP SSL Parsing: 0.002 top.sv
 
 [INFO :PA0201] Parsing source file "builtin.sv".
 
@@ -737,9 +741,9 @@
 n<> u<720> t<Description> p<721> c<719> l<4>
 n<> u<721> t<Source_text> p<722> c<17> l<2>
 n<> u<722> t<Top_level_rule> l<2>
-Parsing took 1.102s
-SSL Parsing: 0.040 ../../build/tests/SimpleConstraint/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
-SSL Parsing: 1.056 ../../build/tests/SimpleConstraint/slpp_all/work/top.sv
+Parsing took 1.062s
+SSL Parsing: 0.038 ../../build/tests/SimpleConstraint/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+SSL Parsing: 1.018 ../../build/tests/SimpleConstraint/slpp_all/work/top.sv
 
 [WARNI:PA0205] top.sv:4 No timescale set for "constaint_mode_ex".
 
@@ -775,13 +779,15 @@
 PROFILE
 ==============
 Scan libraries took 0.000s
-Preprocessing took 0.010s
-Parsing took 1.102s
-SSL Parsing: 0.040 ../../build/tests/SimpleConstraint/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
-SSL Parsing: 1.056 ../../build/tests/SimpleConstraint/slpp_all/work/top.sv
+Preprocessing took 0.012s
+PP SSL Parsing: 0.002 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
+PP SSL Parsing: 0.002 top.sv
+Parsing took 1.062s
+SSL Parsing: 0.038 ../../build/tests/SimpleConstraint/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+SSL Parsing: 1.018 ../../build/tests/SimpleConstraint/slpp_all/work/top.sv
 Compilation took 0.000s
 Elaboration took 0.000s
-Total time 1.112s
+Total time 1.076s
 ==============
 
 [  FATAL] : 0
diff --git a/tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log b/tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log
index 1ad1a7f..4feffa3 100644
--- a/tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log
+++ b/tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log
@@ -145,25 +145,25 @@
 
 [SYNTX:PA0207] mode.vh:27 Syntax error: mismatched input 'initial' expecting <EOF>,
 initial $display("start", "msg1"  , "msg2" , "end");
-^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top.v:33 col:0.
+^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top.v:34 col:0.
 
 [SYNTX:PA0207] mode.vh:9 Syntax error: mismatched input 'initial' expecting <EOF>,
 initial $display("start", "msg1"  , "msg2" , "end");
-^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top_1.v:33 col:0.
+^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top_1.v:34 col:0.
 
 [SYNTX:PA0207] top_2.v:45 Syntax error: token recognition error at: '"start of string\n',
 "start of string
-^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top_2.v:117 col:0.
+^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top_2.v:122 col:0.
 
 [SYNTX:PA0207] mode.vh:9 Syntax error: mismatched input 'initial' expecting <EOF>,
 initial $display("start", "msg1"  , "msg2" , "end");
-^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top_3.v:35 col:0.
+^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top_3.v:36 col:0.
 
 [ERROR:PA0203] top_3.v:6 Unknown macro "TOP".
 
 [SYNTX:PA0207] top_4.v:51 Syntax error: token recognition error at: '\',
 [a,b]+(300,400)+{500,600}+"400,600"+\escaped,here 
-                                    ^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top_4.v:122 col:36.
+                                    ^-- ../../build/tests/SimpleIncludeAndMacros/slpp_all/work/top_4.v:127 col:36.
 
 enterTop_level_rule
   File: top.v , 2
@@ -184,22 +184,22 @@
   File: top.v , 2
   Text: `timescale 10 ns / 1 ...
 enterTop_level_rule
-  File: top_1.v , 33
+  File: top_1.v , 34
   Text: initial $ display (  ...
 enterNull_rule
-  File: top_1.v , 33
+  File: top_1.v , 34
   Text:  ...
 enterSource_text
-  File: top_1.v , 33
+  File: top_1.v , 34
   Text:  ...
 enterTop_level_rule
-  File: top_2.v , 33
+  File: top_2.v , 34
   Text: initial $ display (  ...
 enterNull_rule
-  File: top_2.v , 33
+  File: top_2.v , 34
   Text:  ...
 enterSource_text
-  File: top_2.v , 33
+  File: top_2.v , 34
   Text:  ...
 enterTop_level_rule
   File: top_3.v , 3
@@ -217,13 +217,13 @@
   File: top_3.v , 3
   Text: SURELOG_MACRO_NOT_DE ...
 enterTop_level_rule
-  File: top_4.v , 33
+  File: top_4.v , 34
   Text: initial $ display (  ...
 enterNull_rule
-  File: top_4.v , 33
+  File: top_4.v , 34
   Text:  ...
 enterSource_text
-  File: top_4.v , 33
+  File: top_4.v , 34
   Text:  ...
 enterTop_level_rule
   File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 1
diff --git a/tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log b/tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log
index de4a1ee..29ffbd7 100644
--- a/tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log
+++ b/tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log
@@ -130,19 +130,19 @@
 
 [SYNTX:PA0207] mode.vh:27 Syntax error: mismatched input 'initial' expecting <EOF>,
 initial $display("start", "msg1"  , "msg2" , "end");
-^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top.v:33 col:0.
+^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top.v:34 col:0.
 
 [INFO :PA0201] Parsing source file "top_1.v".
 
 [SYNTX:PA0207] mode.vh:9 Syntax error: mismatched input 'initial' expecting <EOF>,
 initial $display("start", "msg1"  , "msg2" , "end");
-^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_1.v:33 col:0.
+^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_1.v:34 col:0.
 
 [INFO :PA0201] Parsing source file "top_2.v".
 
 [SYNTX:PA0207] top_2.v:45 Syntax error: token recognition error at: '"start of string\n',
 "start of string
-^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_2.v:117 col:0.
+^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_2.v:122 col:0.
 
 [INFO :PA0201] Parsing source file "top_3.v".
 
@@ -154,7 +154,7 @@
 
 [SYNTX:PA0207] top_4.v:51 Syntax error: token recognition error at: '\',
 [a,b]+(300,400)+{500,600}+"400,600"+\escaped,here 
-                                    ^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_4.v:122 col:36.
+                                    ^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_4.v:127 col:36.
 
 [INFO :PA0201] Parsing source file "/home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v".
 
@@ -207,22 +207,22 @@
   File: top.v , 2
   Text: `timescale 10 ns / 1 ...
 enterTop_level_rule
-  File: top_1.v , 33
+  File: top_1.v , 34
   Text: initial $ display (  ...
 enterNull_rule
-  File: top_1.v , 33
+  File: top_1.v , 34
   Text:  ...
 enterSource_text
-  File: top_1.v , 33
+  File: top_1.v , 34
   Text:  ...
 enterTop_level_rule
-  File: top_2.v , 33
+  File: top_2.v , 34
   Text: initial $ display (  ...
 enterNull_rule
-  File: top_2.v , 33
+  File: top_2.v , 34
   Text:  ...
 enterSource_text
-  File: top_2.v , 33
+  File: top_2.v , 34
   Text:  ...
 enterTop_level_rule
   File: top_3.v , 3
@@ -234,13 +234,13 @@
   File: top_3.v , 3
   Text:  ...
 enterTop_level_rule
-  File: top_4.v , 33
+  File: top_4.v , 34
   Text: initial $ display (  ...
 enterNull_rule
-  File: top_4.v , 33
+  File: top_4.v , 34
   Text:  ...
 enterSource_text
-  File: top_4.v , 33
+  File: top_4.v , 34
   Text:  ...
 enterTop_level_rule
   File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 1
diff --git a/third_party/tests/AmiqEth/AmiqEth.log b/third_party/tests/AmiqEth/AmiqEth.log
index bce01ee..71756df 100644
--- a/third_party/tests/AmiqEth/AmiqEth.log
+++ b/third_party/tests/AmiqEth/AmiqEth.log
@@ -220,29 +220,29 @@
 
 [INFO :CP0301] ovm-2.1.2/src/ovm_pkg.sv:22 Compile package "ovm_pkg".
 
-[INFO :CP0301] uvmc-2.2/src/connect/sv/ovmc_pkg.sv:38 Compile package "ovmc_pkg".
+[INFO :CP0301] uvmc-2.2/src/connect/sv/ovmc_pkg.sv:41 Compile package "ovmc_pkg".
 
-[INFO :CP0301] ./sv/amiq_eth_pkg.sv:24 Compile package "amiq_eth_pkg".
+[INFO :CP0301] ./sv/amiq_eth_pkg.sv:25 Compile package "amiq_eth_pkg".
 
-[INFO :CP0301] uvmc-2.2/src/connect/sv/uvmc_pkg.sv:36 Compile package "uvmc_pkg".
+[INFO :CP0301] uvmc-2.2/src/connect/sv/uvmc_pkg.sv:38 Compile package "uvmc_pkg".
 
-[INFO :CP0301] ./ve/sv/amiq_eth_ve_pkg.sv:31 Compile package "amiq_eth_ve_pkg".
+[INFO :CP0301] ./ve/sv/amiq_eth_ve_pkg.sv:34 Compile package "amiq_eth_ve_pkg".
 
 [INFO :CP0303] ve/sv/amiq_eth_ve_top.v:31 Compile module "work@amiq_eth_ve_top".
 
-[INFO :CP0302] ./sv/amiq_eth_packet.sv:27 Compile class "amiq_eth_pkg::amiq_eth_packet".
+[INFO :CP0302] ./sv/amiq_eth_packet.sv:28 Compile class "amiq_eth_pkg::amiq_eth_packet".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "amiq_eth_pkg::amiq_eth_packet_arp".
 
-[INFO :CP0302] ./sv/amiq_eth_packet_ether_type.sv:28 Compile class "amiq_eth_pkg::amiq_eth_packet_ether_type".
+[INFO :CP0302] ./sv/amiq_eth_packet_ether_type.sv:29 Compile class "amiq_eth_pkg::amiq_eth_packet_ether_type".
 
-[INFO :CP0302] ./sv/amiq_eth_packet_ethernet_configuration_testing.sv:24 Compile class "amiq_eth_pkg::amiq_eth_packet_ethernet_configuration_testing".
+[INFO :CP0302] ./sv/amiq_eth_packet_ethernet_configuration_testing.sv:25 Compile class "amiq_eth_pkg::amiq_eth_packet_ethernet_configuration_testing".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "amiq_eth_pkg::amiq_eth_packet_fcoe".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "amiq_eth_pkg::amiq_eth_packet_hsr_base".
 
-[INFO :CP0302] ./sv/amiq_eth_packet_hsr_standard.sv:24 Compile class "amiq_eth_pkg::amiq_eth_packet_hsr_standard".
+[INFO :CP0302] ./sv/amiq_eth_packet_hsr_standard.sv:25 Compile class "amiq_eth_pkg::amiq_eth_packet_hsr_standard".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "amiq_eth_pkg::amiq_eth_packet_ipv4".
 
@@ -250,7 +250,7 @@
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "amiq_eth_pkg::amiq_eth_packet_jumbo".
 
-[INFO :CP0302] ./sv/amiq_eth_packet_length.sv:28 Compile class "amiq_eth_pkg::amiq_eth_packet_length".
+[INFO :CP0302] ./sv/amiq_eth_packet_length.sv:29 Compile class "amiq_eth_pkg::amiq_eth_packet_length".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "amiq_eth_pkg::amiq_eth_packet_magic".
 
@@ -270,11 +270,11 @@
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "amiq_eth_pkg::amiq_eth_packet_ptp_sync_message".
 
-[INFO :CP0302] ./sv/amiq_eth_packet_snap.sv:28 Compile class "amiq_eth_pkg::amiq_eth_packet_snap".
+[INFO :CP0302] ./sv/amiq_eth_packet_snap.sv:29 Compile class "amiq_eth_pkg::amiq_eth_packet_snap".
 
-[INFO :CP0302] ./sv/amiq_eth_pcap_util.sv:27 Compile class "amiq_eth_pkg::amiq_eth_pcap_hdr_base".
+[INFO :CP0302] ./sv/amiq_eth_pcap_util.sv:28 Compile class "amiq_eth_pkg::amiq_eth_pcap_hdr_base".
 
-[INFO :CP0302] ./sv/amiq_eth_pcap_util.sv:34 Compile class "amiq_eth_pkg::amiq_eth_pcap_hdr_s".
+[INFO :CP0302] ./sv/amiq_eth_pcap_util.sv:35 Compile class "amiq_eth_pkg::amiq_eth_pcap_hdr_s".
 
 [INFO :CP0302] ./sv/amiq_eth_pcap_util.sv:196 Compile class "amiq_eth_pkg::amiq_eth_pcap_livestream".
 
@@ -306,7 +306,7 @@
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 Compile class "amiq_eth_ve_pkg::amiq_eth_ve_test_magic_packets".
 
-[INFO :CP0302] ./tests/amiq_eth_ve_test_packets.sv:24 Compile class "amiq_eth_ve_pkg::amiq_eth_ve_test_packets".
+[INFO :CP0302] ./tests/amiq_eth_ve_test_packets.sv:25 Compile class "amiq_eth_ve_pkg::amiq_eth_ve_test_packets".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 Compile class "amiq_eth_ve_pkg::amiq_eth_ve_test_pause_packets".
 
@@ -872,25 +872,25 @@
 
 [INFO :CP0302] ovm-2.1.2/src/compatibility/urm_meth_compatibility.svh:113 Compile class "ovm_pkg::urm_fifo".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:98 Compile class "ovmc_pkg::uvm_domain".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:99 Compile class "ovmc_pkg::uvm_domain".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/ovmc_pkg.sv:71 Compile class "ovmc_pkg::uvm_tlm_generic_payload".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/ovmc_pkg.sv:74 Compile class "ovmc_pkg::uvm_tlm_generic_payload".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:269 Compile class "ovmc_pkg::uvmc_base".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:271 Compile class "ovmc_pkg::uvmc_base".
 
 [INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:59 Compile class "ovmc_pkg::uvmc_converter".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:181 Compile class "ovmc_pkg::uvmc_default_converter".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:191 Compile class "ovmc_pkg::uvmc_default_converter".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:133 Compile class "ovmc_pkg::uvmc_drop_objection_info".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:135 Compile class "ovmc_pkg::uvmc_drop_objection_info".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:780 Compile class "ovmc_pkg::uvmc_tlm1".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:790 Compile class "ovmc_pkg::uvmc_tlm1".
 
 [INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:171 Compile class "ovmc_pkg::uvmc_tlm1_dispatch".
 
 [INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:608 Compile class "ovmc_pkg::uvmc_tlm1_port_proxy".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:123 Compile class "ovmc_pkg::uvmc_wait_for_phase_info".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:125 Compile class "ovmc_pkg::uvmc_wait_for_phase_info".
 
 [INFO :CP0302] uvm-1.2/src/base/uvm_resource.svh:590 Compile class "uvm_pkg::get_t".
 
@@ -1538,23 +1538,23 @@
 
 [INFO :CP0302] uvm-1.2/src/reg/uvm_vreg_field.svh:379 Compile class "uvm_pkg::uvm_vreg_field_cbs".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:117 Compile class "uvmc_pkg::uvm_domain".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:118 Compile class "uvmc_pkg::uvm_domain".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:250 Compile class "uvmc_pkg::uvmc_base".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:264 Compile class "uvmc_pkg::uvmc_base".
 
 [INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:59 Compile class "uvmc_pkg::uvmc_converter".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:181 Compile class "uvmc_pkg::uvmc_default_converter".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_common.sv:191 Compile class "uvmc_pkg::uvmc_default_converter".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:152 Compile class "uvmc_pkg::uvmc_drop_objection_info".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:154 Compile class "uvmc_pkg::uvmc_drop_objection_info".
 
 [INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm2.sv:704 Compile class "uvmc_pkg::uvmc_tlm".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:1084 Compile class "uvmc_pkg::uvmc_tlm1".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:1096 Compile class "uvmc_pkg::uvmc_tlm1".
 
 [INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:458 Compile class "uvmc_pkg::uvmc_tlm1_dispatch".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:912 Compile class "uvmc_pkg::uvmc_tlm1_port_proxy".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:914 Compile class "uvmc_pkg::uvmc_tlm1_port_proxy".
 
 [INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm2.sv:120 Compile class "uvmc_pkg::uvmc_tlm2_dispatch".
 
@@ -1568,7 +1568,7 @@
 
 [INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_tlm2.sv:544 Compile class "uvmc_pkg::uvmc_tlm_nb_target_comp".
 
-[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:142 Compile class "uvmc_pkg::uvmc_wait_for_phase_info".
+[INFO :CP0302] uvmc-2.2/src/connect/sv/uvmc_commands.sv:144 Compile class "uvmc_pkg::uvmc_wait_for_phase_info".
 
 [INFO :CP0302] builtin.sv:4 Compile class "work@mailbox".
 
@@ -1576,13 +1576,13 @@
 
 [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
 
-[ERROR:EL0514] ovm-2.1.2/src/base/ovm_comparer.svh:178 Undefined variable: OVM_PACK.
+[ERROR:EL0514] ovm-2.1.2/src/base/ovm_comparer.svh:187 Undefined variable: OVM_PACK.
 
-[ERROR:EL0514] ovm-2.1.2/src/base/ovm_comparer.svh:179 Undefined variable: OVM_UNPACK.
+[ERROR:EL0514] ovm-2.1.2/src/base/ovm_comparer.svh:188 Undefined variable: OVM_UNPACK.
 
-[ERROR:EL0514] ovm_pkg::avm_put_port:178 Undefined variable: OVM_PACK.
+[ERROR:EL0514] ovm_pkg::avm_put_port:187 Undefined variable: OVM_PACK.
 
-[ERROR:EL0514] ovm_pkg::avm_put_port:179 Undefined variable: OVM_UNPACK.
+[ERROR:EL0514] ovm_pkg::avm_put_port:188 Undefined variable: OVM_UNPACK.
 
 [INFO :EL0526] Design Elaboration...
 
@@ -1596,23 +1596,23 @@
 
 [NOTE :EL0511] Nb leaf instances: 0.
 
-[ERROR:CP0317] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:1089 Undefined type "ovm_port_base".
+[ERROR:CP0317] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:1102 Undefined type "ovm_port_base".
 
-[ERROR:CP0317] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:464 Undefined type "ovm_port_base".
+[ERROR:CP0317] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:465 Undefined type "ovm_port_base".
 
-[ERROR:CP0317] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:916 Undefined type "ovm_port_base".
+[ERROR:CP0317] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:919 Undefined type "ovm_port_base".
 
-[ERROR:CP0328] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:915 Undefined base class "ovm_port_base" extended by "uvmc_pkg::uvmc_tlm1_port_proxy".
+[ERROR:CP0328] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:918 Undefined base class "ovm_port_base" extended by "uvmc_pkg::uvmc_tlm1_port_proxy".
 
-[ERROR:CP0317] uvmc-2.2/src/connect/sv/uvmc_commands.sv:119 Undefined type "ovm_root".
+[ERROR:CP0317] uvmc-2.2/src/connect/sv/uvmc_commands.sv:120 Undefined type "ovm_root".
 
 [ERROR:CP0332] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:403 Function "write" is not defined for variable "m_imp" of type ovm_pkg::ovm_port_base,
                ovm-2.1.2/src/base/ovm_port_base.svh:164 type definition.
 
-[ERROR:CP0332] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:694 Function "write" is not defined for variable "m_imp" of type imp_t,
-               uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:464 type definition.
+[ERROR:CP0332] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:696 Function "write" is not defined for variable "m_imp" of type imp_t,
+               uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:465 type definition.
 
-[ERROR:EL0514] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:937 Undefined variable: super.
+[ERROR:EL0514] uvmc-2.2/src/connect/sv/uvmc_tlm1.sv:943 Undefined variable: super.
 
 [  FATAL] : 0
 [ SYNTAX] : 0
diff --git a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
index 5da366c..80d2a5a 100644
--- a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
+++ b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
@@ -138,41 +138,41 @@
 
 [INFO :CP0301] uvm-1.2/src/uvm_pkg.sv:27 Compile package "uvm_pkg".
 
-[INFO :CP0301] ../../UVM/svaunit/sv/svaunit_pkg.sv:22 Compile package "svaunit_pkg".
+[INFO :CP0301] ../../UVM/svaunit/sv/svaunit_pkg.sv:23 Compile package "svaunit_pkg".
 
 [INFO :CP0301] amiq_svaunit_ex_simple_pkg.sv:26 Compile package "amiq_svaunit_ex_simple_pkg".
 
-[INFO :CP0301] amiq_svaunit_ex_simple_pkg.sv:151687 Compile package "amiq_svaunit_ex_simple_pkg".
+[INFO :CP0301] amiq_svaunit_ex_simple_pkg.sv:154236 Compile package "amiq_svaunit_ex_simple_pkg".
 
-[INFO :CP0304] amiq_apb_if.sv:34 Compile interface "work@amiq_apb_if".
+[INFO :CP0304] amiq_apb_if.sv:43 Compile interface "work@amiq_apb_if".
 
 [INFO :CP0304] an_interface.sv:27 Compile interface "work@an_interface".
 
-[INFO :CP0304] another_interface.sv:23 Compile interface "work@another_interface".
+[INFO :CP0304] another_interface.sv:24 Compile interface "work@another_interface".
 
 [INFO :CP0303] apb_top.sv:29 Compile module "work@apb_top".
 
-[INFO :CP0304] ../../UVM/svaunit/sv/svaunit_vpi_interface.sv:23 Compile interface "work@svaunit_vpi_interface".
+[INFO :CP0304] ../../UVM/svaunit/sv/svaunit_vpi_interface.sv:24 Compile interface "work@svaunit_vpi_interface".
 
 [INFO :CP0303] testbench.sv:28 Compile module "work@top".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_test_head_sequence.sv:24 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_head_sequence".
+[INFO :CP0302] amiq_svaunit_ex_simple_test_head_sequence.sv:25 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_head_sequence".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:158909 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_head_sequence".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:161581 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_head_sequence".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_test_sequence.sv:24 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_sequence".
+[INFO :CP0302] amiq_svaunit_ex_simple_test_sequence.sv:25 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_sequence".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:158751 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_sequence".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:161419 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_sequence".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_suite".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:159278 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_suite".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:161958 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_suite".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_unit".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:159096 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_unit".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:161772 Compile class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_unit".
 
-[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_base.svh:23 Compile class "svaunit_pkg::svaunit_base".
+[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_base.svh:24 Compile class "svaunit_pkg::svaunit_base".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "svaunit_pkg::svaunit_base_sequence".
 
@@ -194,7 +194,7 @@
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 Compile class "svaunit_pkg::svaunit_test_suite".
 
-[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_vpi_wrapper.svh:23 Compile class "svaunit_pkg::svaunit_vpi_wrapper".
+[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_vpi_wrapper.svh:24 Compile class "svaunit_pkg::svaunit_vpi_wrapper".
 
 [INFO :CP0302] uvm-1.2/src/base/uvm_resource.svh:590 Compile class "uvm_pkg::get_t".
 
@@ -842,13 +842,13 @@
 
 [INFO :CP0302] uvm-1.2/src/reg/uvm_vreg_field.svh:379 Compile class "uvm_pkg::uvm_vreg_field_cbs".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:129094 Compile class "work@amiq_svaunit_ex_simple_test_head_sequence".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:25 Compile class "work@amiq_svaunit_ex_simple_test_head_sequence".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:128937 Compile class "work@amiq_svaunit_ex_simple_test_sequence".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:124135 Compile class "work@amiq_svaunit_ex_simple_test_sequence".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:129576 Compile class "work@amiq_svaunit_ex_simple_test_suite".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:131753 Compile class "work@amiq_svaunit_ex_simple_test_suite".
 
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:129280 Compile class "work@amiq_svaunit_ex_simple_test_unit".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:131451 Compile class "work@amiq_svaunit_ex_simple_test_unit".
 
 [INFO :CP0302] builtin.sv:4 Compile class "work@mailbox".
 
@@ -857,34 +857,34 @@
 [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
 
 [ERROR:CP0329] testbench.sv:26 Multiply defined package: "amiq_svaunit_ex_simple_pkg",
-               apb_top.sv:151687 previous definition.
+               apb_top.sv:154236 previous definition.
 
-[ERROR:CP0334] an_interface.sv:50029 Colliding compilation unit name: "another_interface",
-               an_interface.sv:7060 previous usage.
+[ERROR:CP0334] an_interface.sv:50869 Colliding compilation unit name: "another_interface",
+               an_interface.sv:29326 previous usage.
 
-[ERROR:CP0334] an_interface.sv:57131 Colliding compilation unit name: "amiq_apb_if",
-               an_interface.sv:35273 previous usage.
+[ERROR:CP0334] an_interface.sv:58099 Colliding compilation unit name: "amiq_apb_if",
+               an_interface.sv:7198 previous usage.
 
-[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:50029 Colliding compilation unit name: "another_interface",
-               amiq_svaunit_ex_simple_pkg.sv:7060 previous usage.
+[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:29535 Colliding compilation unit name: "amiq_apb_if",
+               amiq_svaunit_ex_simple_pkg.sv:7388 previous usage.
 
-[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:57131 Colliding compilation unit name: "amiq_apb_if",
-               amiq_svaunit_ex_simple_pkg.sv:35273 previous usage.
+[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:73206 Colliding compilation unit name: "another_interface",
+               amiq_svaunit_ex_simple_pkg.sv:51663 previous usage.
 
-[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:78951 Colliding compilation unit name: "another_interface",
-               amiq_svaunit_ex_simple_pkg.sv:7060 previous usage.
+[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:80436 Colliding compilation unit name: "amiq_apb_if",
+               amiq_svaunit_ex_simple_pkg.sv:7388 previous usage.
 
-[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:107164 Colliding compilation unit name: "amiq_apb_if",
-               amiq_svaunit_ex_simple_pkg.sv:35273 previous usage.
+[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:102613 Colliding compilation unit name: "another_interface",
+               amiq_svaunit_ex_simple_pkg.sv:51663 previous usage.
 
-[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:129823 Colliding compilation unit name: "another_interface",
-               amiq_svaunit_ex_simple_pkg.sv:7060 previous usage.
+[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:132006 Colliding compilation unit name: "another_interface",
+               amiq_svaunit_ex_simple_pkg.sv:51663 previous usage.
 
-[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:136925 Colliding compilation unit name: "amiq_apb_if",
-               amiq_svaunit_ex_simple_pkg.sv:35273 previous usage.
+[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:139236 Colliding compilation unit name: "amiq_apb_if",
+               amiq_svaunit_ex_simple_pkg.sv:7388 previous usage.
 
-[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:144603 Colliding compilation unit name: "an_interface",
-               amiq_svaunit_ex_simple_pkg.sv:64809 previous usage.
+[ERROR:CP0334] amiq_svaunit_ex_simple_pkg.sv:147033 Colliding compilation unit name: "an_interface",
+               amiq_svaunit_ex_simple_pkg.sv:88233 previous usage.
 
 [ERROR:CP0316] apb_top.sv:36 Undefined package "amiq_svaunit_ex_apb_test_pkg".
 
@@ -906,16 +906,16 @@
 
 [NOTE :EL0511] Nb leaf instances: 0.
 
-[WARNI:CP0319] amiq_svaunit_ex_simple_pkg.sv:158909 Multiply defined class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_head_sequence",
-               amiq_svaunit_ex_simple_test_head_sequence.sv:24 previous definition.
+[WARNI:CP0319] amiq_svaunit_ex_simple_pkg.sv:161581 Multiply defined class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_head_sequence",
+               amiq_svaunit_ex_simple_test_head_sequence.sv:25 previous definition.
 
-[WARNI:CP0319] amiq_svaunit_ex_simple_pkg.sv:158751 Multiply defined class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_sequence",
-               amiq_svaunit_ex_simple_test_sequence.sv:24 previous definition.
+[WARNI:CP0319] amiq_svaunit_ex_simple_pkg.sv:161419 Multiply defined class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_sequence",
+               amiq_svaunit_ex_simple_test_sequence.sv:25 previous definition.
 
-[WARNI:CP0319] amiq_svaunit_ex_simple_pkg.sv:159278 Multiply defined class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_suite",
+[WARNI:CP0319] amiq_svaunit_ex_simple_pkg.sv:161958 Multiply defined class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_suite",
                ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 previous definition.
 
-[WARNI:CP0319] amiq_svaunit_ex_simple_pkg.sv:159096 Multiply defined class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_unit",
+[WARNI:CP0319] amiq_svaunit_ex_simple_pkg.sv:161772 Multiply defined class "amiq_svaunit_ex_simple_pkg::amiq_svaunit_ex_simple_test_unit",
                ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 previous definition.
 
 [  FATAL] : 0
diff --git a/third_party/tests/BlackParrot/BlackParrot.log b/third_party/tests/BlackParrot/BlackParrot.log
index 048b2c7..8a57df7 100644
--- a/third_party/tests/BlackParrot/BlackParrot.log
+++ b/third_party/tests/BlackParrot/BlackParrot.log
@@ -759,7 +759,7 @@
 
 [INFO :PA0201] Parsing source file "./bp_common/src/v/bp_addr_map.v".
 
-[WARNI:PA0205] ./external/basejump_stl/bsg_noc/bsg_noc_pkg.v:3 No timescale set for "bsg_noc_pkg".
+[WARNI:PA0205] ./external/basejump_stl/bsg_noc/bsg_noc_pkg.v:4 No timescale set for "bsg_noc_pkg".
 
 [WARNI:PA0205] ./external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v:1 No timescale set for "bsg_wormhole_router_pkg".
 
@@ -1155,7 +1155,7 @@
 
 [INFO :CP0300] Compilation...
 
-[INFO :CP0301] ./external/basejump_stl/bsg_noc/bsg_noc_pkg.v:3 Compile package "bsg_noc_pkg".
+[INFO :CP0301] ./external/basejump_stl/bsg_noc/bsg_noc_pkg.v:4 Compile package "bsg_noc_pkg".
 
 [INFO :CP0301] ./external/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.v:1 Compile package "bsg_wormhole_router_pkg".
 
@@ -1555,47 +1555,47 @@
 
 [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
 
-[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:76 Multiply defined typedef "bp_lce_cce_req_type_e",
-               ./bp_common/src/include/bp_common_me_if.vh:76 previous definition.
+[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:77 Multiply defined typedef "bp_lce_cce_req_type_e",
+               ./bp_common/src/include/bp_common_me_if.vh:77 previous definition.
 
-[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:93 Multiply defined typedef "bp_lce_cce_req_non_excl_e",
-               ./bp_common/src/include/bp_common_me_if.vh:93 previous definition.
+[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:94 Multiply defined typedef "bp_lce_cce_req_non_excl_e",
+               ./bp_common/src/include/bp_common_me_if.vh:94 previous definition.
 
-[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:104 Multiply defined typedef "bp_lce_cce_lru_dirty_e",
-               ./bp_common/src/include/bp_common_me_if.vh:104 previous definition.
+[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:105 Multiply defined typedef "bp_lce_cce_lru_dirty_e",
+               ./bp_common/src/include/bp_common_me_if.vh:105 previous definition.
 
-[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:114 Multiply defined typedef "bp_lce_cce_uc_req_size_e",
-               ./bp_common/src/include/bp_common_me_if.vh:114 previous definition.
+[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:115 Multiply defined typedef "bp_lce_cce_uc_req_size_e",
+               ./bp_common/src/include/bp_common_me_if.vh:115 previous definition.
 
-[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:132 Multiply defined typedef "bp_coh_states_e",
-               ./bp_common/src/include/bp_common_me_if.vh:132 previous definition.
+[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:133 Multiply defined typedef "bp_coh_states_e",
+               ./bp_common/src/include/bp_common_me_if.vh:133 previous definition.
 
-[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:159 Multiply defined typedef "bp_lce_cmd_type_e",
-               ./bp_common/src/include/bp_common_me_if.vh:159 previous definition.
+[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:160 Multiply defined typedef "bp_lce_cmd_type_e",
+               ./bp_common/src/include/bp_common_me_if.vh:160 previous definition.
 
-[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:185 Multiply defined typedef "bp_lce_cce_resp_type_e",
-               ./bp_common/src/include/bp_common_me_if.vh:185 previous definition.
+[ERROR:CP0323] ./bp_common/src/include/bp_common_me_if.vh:186 Multiply defined typedef "bp_lce_cce_resp_type_e",
+               ./bp_common/src/include/bp_common_me_if.vh:186 previous definition.
 
-[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:299 Multiply defined typedef "bp_lce_cce_req_type_e",
-               ./bp_fe/src/include/bp_fe_icache.vh:76 previous definition.
+[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:303 Multiply defined typedef "bp_lce_cce_req_type_e",
+               ./bp_fe/src/include/bp_fe_icache.vh:77 previous definition.
 
-[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:316 Multiply defined typedef "bp_lce_cce_req_non_excl_e",
-               ./bp_fe/src/include/bp_fe_icache.vh:93 previous definition.
+[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:320 Multiply defined typedef "bp_lce_cce_req_non_excl_e",
+               ./bp_fe/src/include/bp_fe_icache.vh:94 previous definition.
 
-[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:327 Multiply defined typedef "bp_lce_cce_lru_dirty_e",
-               ./bp_fe/src/include/bp_fe_icache.vh:104 previous definition.
+[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:331 Multiply defined typedef "bp_lce_cce_lru_dirty_e",
+               ./bp_fe/src/include/bp_fe_icache.vh:105 previous definition.
 
-[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:337 Multiply defined typedef "bp_lce_cce_uc_req_size_e",
-               ./bp_fe/src/include/bp_fe_icache.vh:114 previous definition.
+[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:341 Multiply defined typedef "bp_lce_cce_uc_req_size_e",
+               ./bp_fe/src/include/bp_fe_icache.vh:115 previous definition.
 
-[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:355 Multiply defined typedef "bp_coh_states_e",
-               ./bp_fe/src/include/bp_fe_icache.vh:132 previous definition.
+[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:359 Multiply defined typedef "bp_coh_states_e",
+               ./bp_fe/src/include/bp_fe_icache.vh:133 previous definition.
 
-[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:382 Multiply defined typedef "bp_lce_cmd_type_e",
-               ./bp_fe/src/include/bp_fe_icache.vh:159 previous definition.
+[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:386 Multiply defined typedef "bp_lce_cmd_type_e",
+               ./bp_fe/src/include/bp_fe_icache.vh:160 previous definition.
 
-[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:408 Multiply defined typedef "bp_lce_cce_resp_type_e",
-               ./bp_fe/src/include/bp_fe_icache.vh:185 previous definition.
+[ERROR:CP0323] ./bp_fe/src/include/bp_fe_icache.vh:412 Multiply defined typedef "bp_lce_cce_resp_type_e",
+               ./bp_fe/src/include/bp_fe_icache.vh:186 previous definition.
 
 [NOTE :CP0309] ./bp_common/src/v/bp_addr_map.v:18 Implicit port type (wire) for "dst_cord_o",
 there are 1 more instances of this message.
diff --git a/third_party/tests/BuildOVMPkg/BuildOVMPkg.log b/third_party/tests/BuildOVMPkg/BuildOVMPkg.log
index 812810e..b88ff4b 100644
--- a/third_party/tests/BuildOVMPkg/BuildOVMPkg.log
+++ b/third_party/tests/BuildOVMPkg/BuildOVMPkg.log
@@ -235,21 +235,25 @@
 
 [INFO :PP0123] Preprocessing include file "../../UVM/ovm-2.1.2/src/compatibility/urm_meth_compatibility.svh".
 
-Preprocessing took 1.726s
+Preprocessing took 1.180s
+
+Preprocessing took 1.180s
+PP SSL Parsing: 0.002 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
+PP SSL Parsing: 0.022 ../../UVM/ovm-2.1.2/src/ovm_pkg.sv
 
 [INFO :PA0201] Parsing source file "builtin.sv".
 
 [INFO :PA0201] Parsing source file "../../UVM/ovm-2.1.2/src/ovm_pkg.sv".
 
-Parsing took 45.164s
+Parsing took 40.394s
 SSL Parsing: 0.036 ../../../build/tests/BuildOVMPkg/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
-LL  Parsing: 44.200 ../../../build/tests/BuildOVMPkg/slpp_all/work/__/__/UVM/ovm-2.1.2/src/ovm_pkg.sv
+LL  Parsing: 39.476 ../../../build/tests/BuildOVMPkg/slpp_all/work/__/__/UVM/ovm-2.1.2/src/ovm_pkg.sv
 
-[WARNI:PA0205] ../../UVM/ovm-2.1.2/src/ovm_pkg.sv:22 No timescale set for "ovm_pkg".
+[WARNI:PA0205] ../../UVM/ovm-2.1.2/src/ovm_pkg.sv:23 No timescale set for "ovm_pkg".
 
 [INFO :CP0300] Compilation...
 
-[INFO :CP0301] ../../UVM/ovm-2.1.2/src/ovm_pkg.sv:22 Compile package "ovm_pkg".
+[INFO :CP0301] ../../UVM/ovm-2.1.2/src/ovm_pkg.sv:23 Compile package "ovm_pkg".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/compatibility/avm_compatibility.svh:287 Compile class "ovm_pkg::analysis_fifo".
 
@@ -403,7 +407,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/compatibility/avm_compatibility.svh:132 Compile class "ovm_pkg::avm_transport_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_misc.svh:24 Compile class "ovm_pkg::avm_virtual_class".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_misc.svh:25 Compile class "ovm_pkg::avm_virtual_class".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/macros/ovm_phase_defines.svh:38 Compile class "ovm_pkg::build_phase".
 
@@ -413,7 +417,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/macros/ovm_phase_defines.svh:38 Compile class "ovm_pkg::connect_phase".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_handler.svh:507 Compile class "ovm_pkg::default_report_server".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_handler.svh:526 Compile class "ovm_pkg::default_report_server".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/macros/ovm_phase_defines.svh:38 Compile class "ovm_pkg::end_of_elaboration_phase".
 
@@ -423,7 +427,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/macros/ovm_phase_defines.svh:38 Compile class "ovm_pkg::import_connections_phase".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_agent.svh:39 Compile class "ovm_pkg::ovm_agent".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_agent.svh:40 Compile class "ovm_pkg::ovm_agent".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_algorithmic_comparator.svh:65 Compile class "ovm_pkg::ovm_algorithmic_comparator".
 
@@ -477,35 +481,35 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_ports.svh:267 Compile class "ovm_pkg::ovm_blocking_transport_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:78 Compile class "ovm_pkg::ovm_built_in_clone".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:81 Compile class "ovm_pkg::ovm_built_in_clone".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:41 Compile class "ovm_pkg::ovm_built_in_comp".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:42 Compile class "ovm_pkg::ovm_built_in_comp".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:59 Compile class "ovm_pkg::ovm_built_in_converter".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:60 Compile class "ovm_pkg::ovm_built_in_converter".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_pair.svh:103 Compile class "ovm_pkg::ovm_built_in_pair".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_pair.svh:104 Compile class "ovm_pkg::ovm_built_in_pair".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_callback.svh:261 Compile class "ovm_pkg::ovm_callback".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_callback.svh:58 Compile class "ovm_pkg::ovm_callbacks".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_callback.svh:59 Compile class "ovm_pkg::ovm_callbacks".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:135 Compile class "ovm_pkg::ovm_class_clone".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:138 Compile class "ovm_pkg::ovm_class_clone".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:97 Compile class "ovm_pkg::ovm_class_comp".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:100 Compile class "ovm_pkg::ovm_class_comp".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:116 Compile class "ovm_pkg::ovm_class_converter".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_policies.svh:119 Compile class "ovm_pkg::ovm_class_converter".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_pair.svh:30 Compile class "ovm_pkg::ovm_class_pair".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_pair.svh:31 Compile class "ovm_pkg::ovm_class_pair".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_comparer.svh:34 Compile class "ovm_pkg::ovm_comparer".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_component.svh:65 Compile class "ovm_pkg::ovm_component".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_registry.svh:36 Compile class "ovm_pkg::ovm_component_registry".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_registry.svh:37 Compile class "ovm_pkg::ovm_component_registry".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_config.svh:25 Compile class "ovm_pkg::ovm_config_setting".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_config.svh:26 Compile class "ovm_pkg::ovm_config_setting".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_object.svh:882 Compile class "ovm_pkg::ovm_copy_map".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_object.svh:883 Compile class "ovm_pkg::ovm_copy_map".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_driver.svh:41 Compile class "ovm_pkg::ovm_driver".
 
@@ -517,11 +521,11 @@
 
 [INFO :CP0302] builtin.sv:156 Compile class "ovm_pkg::ovm_exhaustive_sequence".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_factory.svh:73 Compile class "ovm_pkg::ovm_factory".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_factory.svh:74 Compile class "ovm_pkg::ovm_factory".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_factory.svh:727 Compile class "ovm_pkg::ovm_factory_override".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_factory.svh:29 Compile class "ovm_pkg::ovm_factory_queue_class".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_factory.svh:30 Compile class "ovm_pkg::ovm_factory_queue_class".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_exports.svh:105 Compile class "ovm_pkg::ovm_get_export".
 
@@ -535,7 +539,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_ports.svh:106 Compile class "ovm_pkg::ovm_get_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:699 Compile class "ovm_pkg::ovm_hier_printer_knobs".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:700 Compile class "ovm_pkg::ovm_hier_printer_knobs".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_in_order_comparator.svh:205 Compile class "ovm_pkg::ovm_in_order_built_in_comparator".
 
@@ -543,9 +547,9 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_in_order_comparator.svh:67 Compile class "ovm_pkg::ovm_in_order_comparator".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_config.svh:68 Compile class "ovm_pkg::ovm_int_config_setting".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_config.svh:69 Compile class "ovm_pkg::ovm_int_config_setting".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:462 Compile class "ovm_pkg::ovm_line_printer".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:463 Compile class "ovm_pkg::ovm_line_printer".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_exports.svh:237 Compile class "ovm_pkg::ovm_master_export".
 
@@ -553,7 +557,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_ports.svh:239 Compile class "ovm_pkg::ovm_master_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_monitor.svh:34 Compile class "ovm_pkg::ovm_monitor".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_monitor.svh:35 Compile class "ovm_pkg::ovm_monitor".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_exports.svh:99 Compile class "ovm_pkg::ovm_nonblocking_get_export".
 
@@ -597,19 +601,19 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_ports.svh:273 Compile class "ovm_pkg::ovm_nonblocking_transport_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_object.svh:53 Compile class "ovm_pkg::ovm_object".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_object.svh:54 Compile class "ovm_pkg::ovm_object".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_config.svh:98 Compile class "ovm_pkg::ovm_object_config_setting".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_config.svh:99 Compile class "ovm_pkg::ovm_object_config_setting".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_registry.svh:167 Compile class "ovm_pkg::ovm_object_registry".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_registry.svh:168 Compile class "ovm_pkg::ovm_object_registry".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_pool.svh:241 Compile class "ovm_pkg::ovm_object_string_pool".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_factory.svh:684 Compile class "ovm_pkg::ovm_object_wrapper".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_objection.svh:42 Compile class "ovm_pkg::ovm_objection".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_objection.svh:43 Compile class "ovm_pkg::ovm_objection".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_object.svh:908 Compile class "ovm_pkg::ovm_options_container".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_object.svh:909 Compile class "ovm_pkg::ovm_options_container".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_packer.svh:45 Compile class "ovm_pkg::ovm_packer".
 
@@ -619,7 +623,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_ports.svh:124 Compile class "ovm_pkg::ovm_peek_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_phases.sv:35 Compile class "ovm_pkg::ovm_phase".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_phases.sv:36 Compile class "ovm_pkg::ovm_phase".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_pool.svh:31 Compile class "ovm_pkg::ovm_pool".
 
@@ -629,9 +633,9 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_port_base.svh:44 Compile class "ovm_pkg::ovm_port_component_base".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:80 Compile class "ovm_pkg::ovm_printer".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:81 Compile class "ovm_pkg::ovm_printer".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:493 Compile class "ovm_pkg::ovm_printer_knobs".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:494 Compile class "ovm_pkg::ovm_printer_knobs".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_push_driver.svh:38 Compile class "ovm_pkg::ovm_push_driver".
 
@@ -643,7 +647,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_ports.svh:88 Compile class "ovm_pkg::ovm_put_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_queue.svh:32 Compile class "ovm_pkg::ovm_queue".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_queue.svh:33 Compile class "ovm_pkg::ovm_queue".
 
 [INFO :CP0302] builtin.sv:44 Compile class "ovm_pkg::ovm_random_sequence".
 
@@ -651,27 +655,27 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_recorder.svh:34 Compile class "ovm_pkg::ovm_recorder".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_server.svh:374 Compile class "ovm_pkg::ovm_report_global_server".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_server.svh:375 Compile class "ovm_pkg::ovm_report_global_server".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_handler.svh:50 Compile class "ovm_pkg::ovm_report_handler".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_handler.svh:52 Compile class "ovm_pkg::ovm_report_handler".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_object.svh:78 Compile class "ovm_pkg::ovm_report_object".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_object.svh:79 Compile class "ovm_pkg::ovm_report_object".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_server.svh:37 Compile class "ovm_pkg::ovm_report_server".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_server.svh:38 Compile class "ovm_pkg::ovm_report_server".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_object.svh:552 Compile class "ovm_pkg::ovm_reporter".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_report_object.svh:553 Compile class "ovm_pkg::ovm_reporter".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_root.svh:65 Compile class "ovm_pkg::ovm_root".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_root.svh:66 Compile class "ovm_pkg::ovm_root".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_root.svh:247 Compile class "ovm_pkg::ovm_root_report_handler".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/layered_stimulus/ovm_scenario.svh:21 Compile class "ovm_pkg::ovm_scenario".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/layered_stimulus/ovm_scenario_controller.svh:27 Compile class "ovm_pkg::ovm_scenario_controller".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/layered_stimulus/ovm_scenario_controller.svh:29 Compile class "ovm_pkg::ovm_scenario_controller".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/layered_stimulus/ovm_scenario_driver.svh:26 Compile class "ovm_pkg::ovm_scenario_driver".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_misc.svh:51 Compile class "ovm_pkg::ovm_scope_stack".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_misc.svh:52 Compile class "ovm_pkg::ovm_scope_stack".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_scoreboard.svh:35 Compile class "ovm_pkg::ovm_scoreboard".
 
@@ -691,7 +695,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/sequences/ovm_sequence_base.svh:31 Compile class "ovm_pkg::ovm_sequence_base".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/sequences/ovm_sequence_item.svh:37 Compile class "ovm_pkg::ovm_sequence_item".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/sequences/ovm_sequence_item.svh:38 Compile class "ovm_pkg::ovm_sequence_item".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/sequences/ovm_sequencer.svh:36 Compile class "ovm_pkg::ovm_sequencer".
 
@@ -707,21 +711,21 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_ports.svh:260 Compile class "ovm_pkg::ovm_slave_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_object.svh:851 Compile class "ovm_pkg::ovm_status_container".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_object.svh:852 Compile class "ovm_pkg::ovm_status_container".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_config.svh:83 Compile class "ovm_pkg::ovm_string_config_setting".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_config.svh:84 Compile class "ovm_pkg::ovm_string_config_setting".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_subscriber.svh:35 Compile class "ovm_pkg::ovm_subscriber".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:356 Compile class "ovm_pkg::ovm_table_printer".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:357 Compile class "ovm_pkg::ovm_table_printer".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:731 Compile class "ovm_pkg::ovm_table_printer_knobs".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:732 Compile class "ovm_pkg::ovm_table_printer_knobs".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/methodology/ovm_test.svh:61 Compile class "ovm_pkg::ovm_test".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_objection.svh:634 Compile class "ovm_pkg::ovm_test_done_objection".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_objection.svh:635 Compile class "ovm_pkg::ovm_test_done_objection".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_transaction.svh:37 Compile class "ovm_pkg::ovm_transaction".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_transaction.svh:38 Compile class "ovm_pkg::ovm_transaction".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_exports.svh:277 Compile class "ovm_pkg::ovm_transport_export".
 
@@ -729,13 +733,13 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/tlm/ovm_ports.svh:279 Compile class "ovm_pkg::ovm_transport_port".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:410 Compile class "ovm_pkg::ovm_tree_printer".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:411 Compile class "ovm_pkg::ovm_tree_printer".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:772 Compile class "ovm_pkg::ovm_tree_printer_knobs".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_printer.svh:773 Compile class "ovm_pkg::ovm_tree_printer_knobs".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/compatibility/urm_message.svh:186 Compile class "ovm_pkg::ovm_urm_message".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/compatibility/urm_message.svh:134 Compile class "ovm_pkg::ovm_urm_message_format".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/compatibility/urm_message.svh:135 Compile class "ovm_pkg::ovm_urm_message_format".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/compatibility/urm_message.svh:309 Compile class "ovm_pkg::ovm_urm_override_operator".
 
@@ -743,7 +747,7 @@
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/compatibility/urm_message.svh:454 Compile class "ovm_pkg::ovm_urm_report_server".
 
-[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_misc.svh:39 Compile class "ovm_pkg::ovm_void".
+[INFO :CP0302] ../../UVM/ovm-2.1.2/src/base/ovm_misc.svh:40 Compile class "ovm_pkg::ovm_void".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/macros/ovm_phase_defines.svh:38 Compile class "ovm_pkg::post_new_phase".
 
@@ -809,7 +813,7 @@
 
 [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
 
-Compilation took 0.024s
+Compilation took 0.022s
 
 [INFO :EL0526] Design Elaboration...
 
@@ -821,19 +825,21 @@
 
 [NOTE :EL0511] Nb leaf instances: 0.
 
-Elaboration took 0.020s
+Elaboration took 0.018s
 
 ==============
 PROFILE
 ==============
 Scan libraries took 0.000s
-Preprocessing took 1.726s
-Parsing took 45.164s
+Preprocessing took 1.180s
+PP SSL Parsing: 0.002 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
+PP SSL Parsing: 0.022 ../../UVM/ovm-2.1.2/src/ovm_pkg.sv
+Parsing took 40.394s
 SSL Parsing: 0.036 ../../../build/tests/BuildOVMPkg/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
-LL  Parsing: 44.200 ../../../build/tests/BuildOVMPkg/slpp_all/work/__/__/UVM/ovm-2.1.2/src/ovm_pkg.sv
-Compilation took 0.024s
-Elaboration took 0.020s
-Total time 46.934s
+LL  Parsing: 39.476 ../../../build/tests/BuildOVMPkg/slpp_all/work/__/__/UVM/ovm-2.1.2/src/ovm_pkg.sv
+Compilation took 0.022s
+Elaboration took 0.018s
+Total time 41.616s
 ==============
 
 [  FATAL] : 0
diff --git a/third_party/tests/CoresSweRV/CoresSweRV.log b/third_party/tests/CoresSweRV/CoresSweRV.log
index 0f9f7ec..76df799 100644
--- a/third_party/tests/CoresSweRV/CoresSweRV.log
+++ b/third_party/tests/CoresSweRV/CoresSweRV.log
@@ -240,7 +240,7 @@
 
 [WARNI:PA0205] ./design/ifu/ifu_ic_mem.sv:90 No timescale set for "IC_DATA".
 
-[WARNI:PA0205] ./design/ifu/ifu_ic_mem.sv:285 No timescale set for "IC_TAG".
+[WARNI:PA0205] ./design/ifu/ifu_ic_mem.sv:288 No timescale set for "IC_TAG".
 
 [WARNI:PA0205] ./design/ifu/ifu_mem_ctl.sv:24 No timescale set for "ifu_mem_ctl".
 
@@ -250,7 +250,7 @@
 
 [WARNI:PA0205] ./design/dec/dec_decode_ctl.sv:17 No timescale set for "dec_decode_ctl".
 
-[WARNI:PA0205] ./design/dec/dec_decode_ctl.sv:2477 No timescale set for "dec_dec_ctl".
+[WARNI:PA0205] ./design/dec/dec_decode_ctl.sv:2479 No timescale set for "dec_dec_ctl".
 
 [WARNI:PA0205] ./design/dec/dec_gpr_ctl.sv:16 No timescale set for "dec_gpr_ctl".
 
@@ -302,35 +302,35 @@
 
 [WARNI:PA0205] ./design/lib/beh_lib.sv:19 No timescale set for "rvdff".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:40 No timescale set for "rvdffs".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:41 No timescale set for "rvdffs".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:54 No timescale set for "rvdffsc".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:55 No timescale set for "rvdffsc".
 
 [WARNI:PA0205] ./design/lib/beh_lib.sv:76 No timescale set for "clockhdr".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:95 No timescale set for "rvclkhdr".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:97 No timescale set for "rvclkhdr".
 
 [WARNI:PA0205] ./design/lib/beh_lib.sv:116 No timescale set for "rvoclkhdr".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:134 No timescale set for "rvdffe".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:135 No timescale set for "rvdffe".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:158 No timescale set for "rvsyncss".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:165 No timescale set for "rvsyncss".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:173 No timescale set for "rvlsadder".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:180 No timescale set for "rvlsadder".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:203 No timescale set for "rvbradder".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:210 No timescale set for "rvbradder".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:235 No timescale set for "rvtwoscomp".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:242 No timescale set for "rvtwoscomp".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:255 No timescale set for "rvfindfirst1".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:262 No timescale set for "rvfindfirst1".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:274 No timescale set for "rvfindfirst1hot".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:281 No timescale set for "rvfindfirst1hot".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:294 No timescale set for "rvmaskandmatch".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:301 No timescale set for "rvmaskandmatch".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:318 No timescale set for "rvbtb_tag_hash".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:325 No timescale set for "rvbtb_tag_hash".
 
-[WARNI:PA0205] ./design/lib/beh_lib.sv:346 No timescale set for "rvbtb_addr_hash".
+[WARNI:PA0205] ./design/lib/beh_lib.sv:347 No timescale set for "rvbtb_addr_hash".
 
 [WARNI:PA0205] ./design/lib/beh_lib.sv:362 No timescale set for "rvbtb_ghr_hash".
 
@@ -438,7 +438,7 @@
 
 [INFO :CP0303] ./design/ifu/ifu_ic_mem.sv:90 Compile module "work@IC_DATA".
 
-[INFO :CP0303] ./design/ifu/ifu_ic_mem.sv:285 Compile module "work@IC_TAG".
+[INFO :CP0303] ./design/ifu/ifu_ic_mem.sv:288 Compile module "work@IC_TAG".
 
 [INFO :CP0303] ./design/lib/ahb_to_axi4.sv:23 Compile module "work@ahb_to_axi4".
 
@@ -454,7 +454,7 @@
 
 [INFO :CP0303] ./design/dec/dec.sv:30 Compile module "work@dec".
 
-[INFO :CP0303] ./design/dec/dec_decode_ctl.sv:2477 Compile module "work@dec_dec_ctl".
+[INFO :CP0303] ./design/dec/dec_decode_ctl.sv:2479 Compile module "work@dec_dec_ctl".
 
 [INFO :CP0303] ./design/dec/dec_decode_ctl.sv:17 Compile module "work@dec_decode_ctl".
 
@@ -604,23 +604,23 @@
 
 [INFO :CP0303] ./design/lib/mem_lib.sv:67 Compile module "work@ram_8192x39".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:203 Compile module "work@rvbradder".
+[INFO :CP0303] ./design/lib/beh_lib.sv:210 Compile module "work@rvbradder".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:346 Compile module "work@rvbtb_addr_hash".
+[INFO :CP0303] ./design/lib/beh_lib.sv:347 Compile module "work@rvbtb_addr_hash".
 
 [INFO :CP0303] ./design/lib/beh_lib.sv:362 Compile module "work@rvbtb_ghr_hash".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:318 Compile module "work@rvbtb_tag_hash".
+[INFO :CP0303] ./design/lib/beh_lib.sv:325 Compile module "work@rvbtb_tag_hash".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:95 Compile module "work@rvclkhdr".
+[INFO :CP0303] ./design/lib/beh_lib.sv:97 Compile module "work@rvclkhdr".
 
 [INFO :CP0303] ./design/lib/beh_lib.sv:19 Compile module "work@rvdff".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:134 Compile module "work@rvdffe".
+[INFO :CP0303] ./design/lib/beh_lib.sv:135 Compile module "work@rvdffe".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:40 Compile module "work@rvdffs".
+[INFO :CP0303] ./design/lib/beh_lib.sv:41 Compile module "work@rvdffs".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:54 Compile module "work@rvdffsc".
+[INFO :CP0303] ./design/lib/beh_lib.sv:55 Compile module "work@rvdffsc".
 
 [INFO :CP0303] ./design/lib/beh_lib.sv:437 Compile module "work@rvecc_decode".
 
@@ -630,23 +630,23 @@
 
 [INFO :CP0303] ./design/lib/beh_lib.sv:401 Compile module "work@rveven_paritygen".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:255 Compile module "work@rvfindfirst1".
+[INFO :CP0303] ./design/lib/beh_lib.sv:262 Compile module "work@rvfindfirst1".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:274 Compile module "work@rvfindfirst1hot".
+[INFO :CP0303] ./design/lib/beh_lib.sv:281 Compile module "work@rvfindfirst1hot".
 
 [INFO :CP0303] ./design/dmi/rvjtag_tap.sv:16 Compile module "work@rvjtag_tap".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:173 Compile module "work@rvlsadder".
+[INFO :CP0303] ./design/lib/beh_lib.sv:180 Compile module "work@rvlsadder".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:294 Compile module "work@rvmaskandmatch".
+[INFO :CP0303] ./design/lib/beh_lib.sv:301 Compile module "work@rvmaskandmatch".
 
 [INFO :CP0303] ./design/lib/beh_lib.sv:116 Compile module "work@rvoclkhdr".
 
 [INFO :CP0303] ./design/lib/beh_lib.sv:376 Compile module "work@rvrangecheck".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:158 Compile module "work@rvsyncss".
+[INFO :CP0303] ./design/lib/beh_lib.sv:165 Compile module "work@rvsyncss".
 
-[INFO :CP0303] ./design/lib/beh_lib.sv:235 Compile module "work@rvtwoscomp".
+[INFO :CP0303] ./design/lib/beh_lib.sv:242 Compile module "work@rvtwoscomp".
 
 [INFO :CP0303] ./design/swerv.sv:23 Compile module "work@swerv".
 
@@ -1306,10 +1306,10 @@
 
 [NOTE :CP0309] ./design/lib/beh_lib.sv:79 Implicit port type (wire) for "Q".
 
-[NOTE :CP0309] ./design/dec/dec.sv:191 Implicit port type (wire) for "dec_tlu_ic_diag_pkt",
+[NOTE :CP0309] ./design/dec/dec.sv:193 Implicit port type (wire) for "dec_tlu_ic_diag_pkt",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] ./design/dec/dec_decode_ctl.sv:2482 Implicit port type (wire) for "out".
+[NOTE :CP0309] ./design/dec/dec_decode_ctl.sv:2484 Implicit port type (wire) for "out".
 
 [NOTE :CP0309] ./design/dec/dec_decode_ctl.sv:156 Implicit port type (wire) for "i0_ap",
 there are 9 more instances of this message.
@@ -1317,7 +1317,7 @@
 [NOTE :CP0309] ./design/dec/dec_ib_ctl.sv:83 Implicit port type (wire) for "dec_i0_brp",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] ./design/dec/dec_tlu_ctl.sv:156 Implicit port type (wire) for "trigger_pkt_any",
+[NOTE :CP0309] ./design/dec/dec_tlu_ctl.sv:158 Implicit port type (wire) for "trigger_pkt_any",
 there are 3 more instances of this message.
 
 [NOTE :CP0309] ./design/dmi/dmi_jtag_to_core_sync.v:31 Implicit port type (wire) for "reg_en",
@@ -1331,13 +1331,13 @@
 
 [NOTE :CP0309] ./design/exu/exu_alu_ctl.sv:51 Implicit port type (wire) for "predict_p_ff".
 
-[NOTE :CP0309] ./design/ifu/ifu.sv:186 Implicit port type (wire) for "i0_brp",
+[NOTE :CP0309] ./design/ifu/ifu.sv:189 Implicit port type (wire) for "i0_brp",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] ./design/ifu/ifu_aln_ctl.sv:91 Implicit port type (wire) for "i0_brp",
+[NOTE :CP0309] ./design/ifu/ifu_aln_ctl.sv:93 Implicit port type (wire) for "i0_brp",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] ./design/ifu/ifu_mem_ctl.sv:160 Implicit port type (wire) for "ic_error_f2".
+[NOTE :CP0309] ./design/ifu/ifu_mem_ctl.sv:163 Implicit port type (wire) for "ic_error_f2".
 
 [NOTE :CP0309] ./design/lsu/lsu.sv:66 Implicit port type (wire) for "lsu_error_pkt_dc3".
 
@@ -1347,7 +1347,7 @@
 [NOTE :CP0309] ./design/lsu/lsu_lsc_ctl.sv:104 Implicit port type (wire) for "lsu_error_pkt_dc3",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] ./design/lib/beh_lib.sv:208 Implicit port type (wire) for "dout".
+[NOTE :CP0309] ./design/lib/beh_lib.sv:215 Implicit port type (wire) for "dout".
 
 [NOTE :CP0309] ./design/lib/beh_lib.sv:442 Implicit port type (wire) for "dout",
 there are 3 more instances of this message.
diff --git a/third_party/tests/Ibex/Ibex.log b/third_party/tests/Ibex/Ibex.log
index 04b737c..cc060f4 100644
--- a/third_party/tests/Ibex/Ibex.log
+++ b/third_party/tests/Ibex/Ibex.log
@@ -60,7 +60,7 @@
 
 [INFO :CP0303] ./ibex/rtl/ibex_controller.sv:9 Compile module "work@ibex_controller".
 
-[INFO :CP0303] ./ibex/rtl/ibex_core.sv:10 Compile module "work@ibex_core".
+[INFO :CP0303] ./ibex/rtl/ibex_core.sv:11 Compile module "work@ibex_core".
 
 [INFO :CP0303] ./ibex/rtl/ibex_core_tracing.sv:9 Compile module "work@ibex_core_tracing".
 
@@ -72,7 +72,7 @@
 
 [INFO :CP0303] ./ibex/rtl/ibex_fetch_fifo.sv:12 Compile module "work@ibex_fetch_fifo".
 
-[INFO :CP0303] ./ibex/rtl/ibex_id_stage.sv:13 Compile module "work@ibex_id_stage".
+[INFO :CP0303] ./ibex/rtl/ibex_id_stage.sv:14 Compile module "work@ibex_id_stage".
 
 [INFO :CP0303] ./ibex/rtl/ibex_if_stage.sv:12 Compile module "work@ibex_if_stage".
 
@@ -834,7 +834,7 @@
 [NOTE :CP0309] ./ibex/rtl/ibex_decoder.sv:31 Implicit port type (wire) for "imm_a_mux_sel_o",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] ./ibex/rtl/ibex_id_stage.sv:42 Implicit port type (wire) for "pc_mux_o",
+[NOTE :CP0309] ./ibex/rtl/ibex_id_stage.sv:43 Implicit port type (wire) for "pc_mux_o",
 there are 6 more instances of this message.
 
 [INFO :EL0526] Design Elaboration...
diff --git a/third_party/tests/IbexGoogle/IbexGoogle.log b/third_party/tests/IbexGoogle/IbexGoogle.log
index 2f2ad1c..0c57b4e 100644
--- a/third_party/tests/IbexGoogle/IbexGoogle.log
+++ b/third_party/tests/IbexGoogle/IbexGoogle.log
@@ -132,9 +132,9 @@
 
 [INFO :PA0201] Parsing source file "./src/riscv_instr_pkg.sv".
 
-[SYNTX:PA0207] target/rv32i/riscv_core_setting.sv:56 Syntax error: missing ';' at '[',
+[SYNTX:PA0207] target/rv32i/riscv_core_setting.sv:57 Syntax error: missing ';' at '[',
 parameter privileged_reg_t implemented_csr[] = {
-                                          ^-- ../../../build/tests/IbexGoogle/slpp_all/work/./src/riscv_instr_pkg.sv:4234 col:42.
+                                          ^-- ../../../build/tests/IbexGoogle/slpp_all/work/./src/riscv_instr_pkg.sv:4315 col:42.
 
 [INFO :PA0201] Parsing source file "./test/riscv_instr_test_pkg.sv".
 
@@ -214,7 +214,7 @@
 
 [INFO :CP0302] ./src/riscv_page_table_list.sv:28 Compile class "riscv_instr_pkg::riscv_page_table_list".
 
-[INFO :CP0302] ./src/riscv_directed_instr_lib.sv:342 Compile class "riscv_instr_pkg::riscv_pop_stack_instr".
+[INFO :CP0302] ./src/riscv_directed_instr_lib.sv:343 Compile class "riscv_instr_pkg::riscv_pop_stack_instr".
 
 [INFO :CP0302] ./src/riscv_privil_reg.sv:18 Compile class "riscv_instr_pkg::riscv_privil_reg".
 
diff --git a/third_party/tests/Icarus/Icarus.log b/third_party/tests/Icarus/Icarus.log
index 636c081..701bfd1 100644
--- a/third_party/tests/Icarus/Icarus.log
+++ b/third_party/tests/Icarus/Icarus.log
@@ -62,7 +62,7 @@
 
 [WARNI:PA0205] contrib/fifo.v:25 No timescale set for "fifo".
 
-[WARNI:PA0205] contrib/fifo.v:159 No timescale set for "test_fifo".
+[WARNI:PA0205] contrib/fifo.v:160 No timescale set for "test_fifo".
 
 [WARNI:PA0205] contrib/gencrc.v:41 No timescale set for "test_gencrc".
 
@@ -82,7 +82,7 @@
 
 [WARNI:PA0205] contrib/pic.v:1284 No timescale set for "picregs".
 
-[WARNI:PA0205] contrib/pic.v:1785 No timescale set for "pictest".
+[WARNI:PA0205] contrib/pic.v:1789 No timescale set for "pictest".
 
 [WARNI:PA0205] ivltests/addwide.v:7 No timescale set for "source".
 
@@ -150,11 +150,11 @@
 
 [WARNI:PA0205] ivltests/deposit.v:24 No timescale set for "deposit_test".
 
-[WARNI:PA0205] ivltests/deposit.v:89 No timescale set for "dffe".
+[WARNI:PA0205] ivltests/deposit.v:93 No timescale set for "dffe".
 
-[WARNI:PA0205] ivltests/deposit.v:97 No timescale set for "UDP_dffe".
+[WARNI:PA0205] ivltests/deposit.v:101 No timescale set for "UDP_dffe".
 
-[WARNI:PA0205] ivltests/deposit.v:114 No timescale set for "had".
+[WARNI:PA0205] ivltests/deposit.v:118 No timescale set for "had".
 
 [WARNI:PA0205] ivltests/disp_parm.v:2 No timescale set for "top".
 
@@ -274,9 +274,9 @@
 
 [WARNI:PA0205] ivltests/param_times.v:42 No timescale set for "bar".
 
-[WARNI:PA0205] ivltests/port-test2.v:9 No timescale set for "port_3".
+[WARNI:PA0205] ivltests/port-test2.v:10 No timescale set for "port_3".
 
-[WARNI:PA0205] ivltests/port-test2.v:26 No timescale set for "port_test".
+[WARNI:PA0205] ivltests/port-test2.v:27 No timescale set for "port_test".
 
 [WARNI:PA0205] ivltests/port-test3.v:9 No timescale set for "CPU".
 
@@ -428,7 +428,7 @@
 
 [WARNI:PA0205] ivltests/udp_jkff.v:22 No timescale set for "test_jkff".
 
-[WARNI:PA0205] ivltests/udp_jkff.v:103 No timescale set for "jkff".
+[WARNI:PA0205] ivltests/udp_jkff.v:106 No timescale set for "jkff".
 
 [WARNI:PA0205] ivltests/udp_lfsr.v:22 No timescale set for "test_lfsr".
 
@@ -486,7 +486,7 @@
 
 [INFO :CP0305] ivltests/udp_bx.v:1 Compile udp "work@UDP".
 
-[INFO :CP0305] ivltests/deposit.v:97 Compile udp "work@UDP_dffe".
+[INFO :CP0305] ivltests/deposit.v:101 Compile udp "work@UDP_dffe".
 
 [INFO :CP0305] ivltests/ldelay5.v:40 Compile udp "work@U_drec".
 
@@ -552,7 +552,7 @@
 
 [INFO :CP0303] ivltests/pr273.v:54 Compile module "work@dff2".
 
-[INFO :CP0303] ivltests/deposit.v:89 Compile module "work@dffe".
+[INFO :CP0303] ivltests/deposit.v:93 Compile module "work@dffe".
 
 [INFO :CP0303] ivltests/signed10.v:20 Compile module "work@displaysigned".
 
@@ -612,7 +612,7 @@
 
 [INFO :CP0303] ivltests/bufif.v:25 Compile module "work@grayGap".
 
-[INFO :CP0303] ivltests/deposit.v:114 Compile module "work@had".
+[INFO :CP0303] ivltests/deposit.v:118 Compile module "work@had".
 
 [INFO :CP0303] ivltests/port-test5.v:55 Compile module "work@has_ports".
 
@@ -630,7 +630,7 @@
 
 [INFO :CP0303] ivltests/integer4ge.v:23 Compile module "work@integer4ge".
 
-[INFO :CP0305] ivltests/udp_jkff.v:103 Compile udp "work@jkff".
+[INFO :CP0305] ivltests/udp_jkff.v:106 Compile udp "work@jkff".
 
 [INFO :CP0303] ivltests/task_scope.v:54 Compile module "work@jobs".
 
@@ -750,15 +750,15 @@
 
 [INFO :CP0303] contrib/pic.v:1284 Compile module "work@picregs".
 
-[INFO :CP0303] contrib/pic.v:1785 Compile module "work@pictest".
+[INFO :CP0303] contrib/pic.v:1789 Compile module "work@pictest".
 
 [INFO :CP0303] vpi/pr521.v:1 Compile module "work@pli_test".
 
 [INFO :CP0303] ivltests/pr841.v:25 Compile module "work@pll".
 
-[INFO :CP0303] ivltests/port-test2.v:9 Compile module "work@port_3".
+[INFO :CP0303] ivltests/port-test2.v:10 Compile module "work@port_3".
 
-[INFO :CP0303] ivltests/port-test2.v:26 Compile module "work@port_test".
+[INFO :CP0303] ivltests/port-test2.v:27 Compile module "work@port_test".
 
 [INFO :CP0303] ivltests/port-test4a.v:8 Compile module "work@port_test4".
 
@@ -848,7 +848,7 @@
 
 [INFO :CP0303] contrib/div16.v:147 Compile module "work@test_div16".
 
-[INFO :CP0303] contrib/fifo.v:159 Compile module "work@test_fifo".
+[INFO :CP0303] contrib/fifo.v:160 Compile module "work@test_fifo".
 
 [INFO :CP0303] contrib/gencrc.v:41 Compile module "work@test_gencrc".
 
@@ -950,7 +950,7 @@
 
 [NOTE :CP0309] ivltests/specify_01.v:1 Implicit port type (wire) for "q".
 
-[NOTE :CP0309] ivltests/deposit.v:89 Implicit port type (wire) for "Q".
+[NOTE :CP0309] ivltests/deposit.v:93 Implicit port type (wire) for "Q".
 
 [NOTE :CP0309] contrib/div16.v:57 Implicit port type (wire) for "r".
 
@@ -962,7 +962,7 @@
 
 [NOTE :CP0309] ivltests/bufif.v:25 Implicit port type (wire) for "ad".
 
-[NOTE :CP0309] ivltests/deposit.v:114 Implicit port type (wire) for "C",
+[NOTE :CP0309] ivltests/deposit.v:118 Implicit port type (wire) for "C",
 there are 1 more instances of this message.
 
 [NOTE :CP0309] ivltests/inout.v:21 Implicit port type (wire) for "a".
@@ -1007,7 +1007,7 @@
 [NOTE :CP0309] contrib/pic.v:1066 Implicit port type (wire) for "aluasel",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] ivltests/port-test2.v:11 Implicit port type (wire) for "dummy_1",
+[NOTE :CP0309] ivltests/port-test2.v:12 Implicit port type (wire) for "dummy_1",
 there are 2 more instances of this message.
 
 [NOTE :CP0309] ivltests/port-test4a.v:10 Implicit port type (wire) for "b".
@@ -1054,7 +1054,7 @@
 
 [NOTE :EL0503] contrib/div16.v:147 Top level module "work@test_div16".
 
-[NOTE :EL0503] contrib/fifo.v:159 Top level module "work@test_fifo".
+[NOTE :EL0503] contrib/fifo.v:160 Top level module "work@test_fifo".
 
 [NOTE :EL0503] contrib/gencrc.v:41 Top level module "work@test_gencrc".
 
@@ -1062,7 +1062,7 @@
 
 [NOTE :EL0503] contrib/onehot.v:171 Top level module "work@test_onehot".
 
-[NOTE :EL0503] contrib/pic.v:1785 Top level module "work@pictest".
+[NOTE :EL0503] contrib/pic.v:1789 Top level module "work@pictest".
 
 [NOTE :EL0503] ivltests/addwide.v:38 Top level module "work@bench".
 
@@ -1744,7 +1744,7 @@
                ivltests/ga_mod.v:23 previous definition.
 
 [WARNI:EL0505] ivltests/pr721.v:1 Multiply defined module "work@port_test",
-               ivltests/port-test2.v:26 previous definition.
+               ivltests/port-test2.v:27 previous definition.
 
 [WARNI:EL0505] ivltests/port-test4b.v:8 Multiply defined module "work@port_test4",
                ivltests/port-test4a.v:8 previous definition.
diff --git a/third_party/tests/MiniAmiq/MiniAmiq.log b/third_party/tests/MiniAmiq/MiniAmiq.log
index ca745fb..a52c7d1 100644
--- a/third_party/tests/MiniAmiq/MiniAmiq.log
+++ b/third_party/tests/MiniAmiq/MiniAmiq.log
@@ -102,11 +102,11 @@
 
 [INFO :CP0301] uvm-1.2/src/uvm_pkg.sv:27 Compile package "uvm_pkg".
 
-[INFO :CP0301] ../../UVM/svaunit/sv/svaunit_pkg.sv:22 Compile package "svaunit_pkg".
+[INFO :CP0301] ../../UVM/svaunit/sv/svaunit_pkg.sv:23 Compile package "svaunit_pkg".
 
-[INFO :CP0304] ../../UVM/svaunit/sv/svaunit_vpi_interface.sv:23 Compile interface "work@svaunit_vpi_interface".
+[INFO :CP0304] ../../UVM/svaunit/sv/svaunit_vpi_interface.sv:24 Compile interface "work@svaunit_vpi_interface".
 
-[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_base.svh:23 Compile class "svaunit_pkg::svaunit_base".
+[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_base.svh:24 Compile class "svaunit_pkg::svaunit_base".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "svaunit_pkg::svaunit_base_sequence".
 
@@ -128,7 +128,7 @@
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 Compile class "svaunit_pkg::svaunit_test_suite".
 
-[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_vpi_wrapper.svh:23 Compile class "svaunit_pkg::svaunit_vpi_wrapper".
+[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_vpi_wrapper.svh:24 Compile class "svaunit_pkg::svaunit_vpi_wrapper".
 
 [INFO :CP0302] uvm-1.2/src/base/uvm_resource.svh:590 Compile class "uvm_pkg::get_t".
 
diff --git a/third_party/tests/Monitor/Monitor.log b/third_party/tests/Monitor/Monitor.log
index 9565e8a..206d909 100644
--- a/third_party/tests/Monitor/Monitor.log
+++ b/third_party/tests/Monitor/Monitor.log
@@ -114,15 +114,15 @@
 
 [INFO :CP0301] uvm-1.2/src/uvm_pkg.sv:27 Compile package "uvm_pkg".
 
-[INFO :CP0301] ../../UVM/svaunit/sv/svaunit_pkg.sv:22 Compile package "svaunit_pkg".
+[INFO :CP0301] ../../UVM/svaunit/sv/svaunit_pkg.sv:23 Compile package "svaunit_pkg".
 
 [INFO :CP0304] design.sv:2 Compile interface "work@my_interface".
 
 [INFO :CP0303] testbench.sv:30 Compile module "work@my_monitor_unit_test".
 
-[INFO :CP0304] ../../UVM/svaunit/sv/svaunit_vpi_interface.sv:23 Compile interface "work@svaunit_vpi_interface".
+[INFO :CP0304] ../../UVM/svaunit/sv/svaunit_vpi_interface.sv:24 Compile interface "work@svaunit_vpi_interface".
 
-[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_base.svh:23 Compile class "svaunit_pkg::svaunit_base".
+[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_base.svh:24 Compile class "svaunit_pkg::svaunit_base".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:245 Compile class "svaunit_pkg::svaunit_base_sequence".
 
@@ -144,7 +144,7 @@
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 Compile class "svaunit_pkg::svaunit_test_suite".
 
-[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_vpi_wrapper.svh:23 Compile class "svaunit_pkg::svaunit_vpi_wrapper".
+[INFO :CP0302] ../../UVM/svaunit/sv/svaunit_vpi_wrapper.svh:24 Compile class "svaunit_pkg::svaunit_vpi_wrapper".
 
 [INFO :CP0302] uvm-1.2/src/base/uvm_resource.svh:590 Compile class "uvm_pkg::get_t".
 
diff --git a/third_party/tests/OVMSwitch/OVMSwitch.log b/third_party/tests/OVMSwitch/OVMSwitch.log
index b02c42c..3241cc7 100644
--- a/third_party/tests/OVMSwitch/OVMSwitch.log
+++ b/third_party/tests/OVMSwitch/OVMSwitch.log
@@ -112,11 +112,11 @@
 
 [INFO :CP0301] ovm-2.1.2/src/ovm_pkg.sv:22 Compile package "ovm_pkg".
 
-[INFO :CP0304] interface.sv:43 Compile interface "work@input_interface".
+[INFO :CP0304] interface.sv:44 Compile interface "work@input_interface".
 
-[INFO :CP0304] interface.sv:17 Compile interface "work@mem_interface".
+[INFO :CP0304] interface.sv:18 Compile interface "work@mem_interface".
 
-[INFO :CP0304] interface.sv:67 Compile interface "work@output_interface".
+[INFO :CP0304] interface.sv:68 Compile interface "work@output_interface".
 
 [INFO :CP0303] rtl.sv:1 Compile module "work@switch".
 
@@ -680,15 +680,15 @@
 
 [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
 
-[INFO :CP0302] Configuration.sv:12 Compile class "work@top::Configuration".
+[INFO :CP0302] Configuration.sv:13 Compile class "work@top::Configuration".
 
-[INFO :CP0302] Driver.sv:11 Compile class "work@top::Driver".
+[INFO :CP0302] Driver.sv:12 Compile class "work@top::Driver".
 
-[INFO :CP0302] Environment.sv:12 Compile class "work@top::Environment".
+[INFO :CP0302] Environment.sv:13 Compile class "work@top::Environment".
 
-[INFO :CP0302] Packet.sv:15 Compile class "work@top::Packet".
+[INFO :CP0302] Packet.sv:16 Compile class "work@top::Packet".
 
-[INFO :CP0302] Receiver.sv:11 Compile class "work@top::Receiver".
+[INFO :CP0302] Receiver.sv:12 Compile class "work@top::Receiver".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/macros/ovm_object_defines.svh:318 Compile class "work@top::Scoreboard".
 
@@ -696,7 +696,7 @@
 
 [INFO :CP0302] Sequence.sv:11 Compile class "work@top::Seq_device0_and_device1".
 
-[INFO :CP0302] Sequencer.sv:11 Compile class "work@top::Sequencer".
+[INFO :CP0302] Sequencer.sv:12 Compile class "work@top::Sequencer".
 
 [INFO :CP0302] ../../UVM/ovm-2.1.2/src/macros/tlm_defines.svh:448 Compile class "work@top::ovm_analysis_imp_rcvd_pkt".
 
diff --git a/third_party/tests/SVSwitch/SVSwitch.log b/third_party/tests/SVSwitch/SVSwitch.log
index f7158fc..5264a37 100644
--- a/third_party/tests/SVSwitch/SVSwitch.log
+++ b/third_party/tests/SVSwitch/SVSwitch.log
@@ -58,42 +58,42 @@
 
 [INFO :CP0300] Compilation...
 
-[INFO :CP0304] interface.sv:36 Compile interface "work@input_interface".
+[INFO :CP0304] interface.sv:37 Compile interface "work@input_interface".
 
-[INFO :CP0304] interface.sv:14 Compile interface "work@mem_interface".
+[INFO :CP0304] interface.sv:15 Compile interface "work@mem_interface".
 
-[INFO :CP0304] interface.sv:56 Compile interface "work@output_interface".
+[INFO :CP0304] interface.sv:57 Compile interface "work@output_interface".
 
 [INFO :CP0303] rtl.sv:1 Compile module "work@switch".
 
-[INFO :CP0303] top.sv:10 Compile module "work@top".
+[INFO :CP0303] top.sv:11 Compile module "work@top".
 
-[INFO :CP0306] testcase.sv:16 Compile program "work@testcase".
+[INFO :CP0306] testcase.sv:17 Compile program "work@testcase".
 
-[INFO :CP0302] Driver.sv:10 Compile class "work@Driver".
+[INFO :CP0302] Driver.sv:11 Compile class "work@Driver".
 
-[INFO :CP0302] Environemnt.sv:10 Compile class "work@Environment".
+[INFO :CP0302] Environemnt.sv:11 Compile class "work@Environment".
 
-[INFO :CP0302] Receiver.sv:10 Compile class "work@Receiver".
+[INFO :CP0302] Receiver.sv:11 Compile class "work@Receiver".
 
-[INFO :CP0302] Scoreboard.sv:10 Compile class "work@Scoreboard".
+[INFO :CP0302] Scoreboard.sv:11 Compile class "work@Scoreboard".
 
-[INFO :CP0302] Coverage.sv:10 Compile class "work@coverage".
+[INFO :CP0302] Coverage.sv:11 Compile class "work@coverage".
 
 [INFO :CP0302] builtin.sv:4 Compile class "work@mailbox".
 
-[INFO :CP0302] Packet.sv:14 Compile class "work@packet".
+[INFO :CP0302] Packet.sv:15 Compile class "work@packet".
 
 [INFO :CP0302] builtin.sv:33 Compile class "work@process".
 
 [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
 
-[INFO :CP0302] testcase.sv:10 Compile class "work@small_packet".
+[INFO :CP0302] testcase.sv:11 Compile class "work@small_packet".
 
 [NOTE :CP0309] rtl.sv:1 Implicit port type (wire) for "port0",
 there are 7 more instances of this message.
 
-[WARNI:CP0314] testcase.sv:16 Using programs is discouraged "work@testcase", programs are obsoleted by UVM.
+[WARNI:CP0314] testcase.sv:17 Using programs is discouraged "work@testcase", programs are obsoleted by UVM.
 
 [INFO :EL0526] Design Elaboration...
 
@@ -165,7 +165,7 @@
 [SCO] work@switch.fsm_core.UNNAMED.UNNAMED.UNNAMED work@top.DUT.fsm_core.UNNAMED.UNNAMED.UNNAMED
 [SCO] work@switch.fsm_core.UNNAMED.UNNAMED.UNNAMED work@top.DUT.fsm_core.UNNAMED.UNNAMED.UNNAMED
 
-[NOTE :EL0503] top.sv:10 Top level module "work@top".
+[NOTE :EL0503] top.sv:11 Top level module "work@top".
 
 [NOTE :EL0508] Nb Top level modules: 1.
 
@@ -175,17 +175,17 @@
 
 [NOTE :EL0511] Nb leaf instances: 0.
 
-[NOTE :EL0523] top.sv:10 Instance "work@top".
+[NOTE :EL0523] top.sv:11 Instance "work@top".
 
-[NOTE :EL0524] top.sv:24 Interface Instance "work@top.mem_intf".
+[NOTE :EL0524] top.sv:25 Interface Instance "work@top.mem_intf".
 
-[NOTE :EL0524] top.sv:30 Interface Instance "work@top.input_intf".
+[NOTE :EL0524] top.sv:31 Interface Instance "work@top.input_intf".
 
-[NOTE :EL0525] top.sv:42 Program Instance "work@top.TC".
+[NOTE :EL0525] top.sv:43 Program Instance "work@top.TC".
 
-[NOTE :EL0523] top.sv:48 Instance "work@top.DUT".
+[NOTE :EL0523] top.sv:49 Instance "work@top.DUT".
 
-[NOTE :EL0522] testcase.sv:22 Scope "work@top.TC.UNNAMED".
+[NOTE :EL0522] testcase.sv:23 Scope "work@top.TC.UNNAMED".
 
 [NOTE :EL0522] rtl.sv:8 Scope "work@top.DUT.UNNAMED".
 
diff --git a/third_party/tests/Scr1/LICENSE b/third_party/tests/Scr1/LICENSE
new file mode 100644
index 0000000..0d753ad
--- /dev/null
+++ b/third_party/tests/Scr1/LICENSE
@@ -0,0 +1,23 @@
+﻿# Solderpad Hardware Licence Version 2.0
+
+This licence (the “Licence”) operates as a wraparound licence to the Apache License Version 2.0 (the “Apache License”) and grants to You the rights, and imposes the obligations, set out in the Apache License (which can be found here: http://apache.org/licenses/LICENSE-2.0), with the following extensions. It must be read in conjunction with the Apache License. Section 1 below modifies definitions in the Apache License, and section 2 below replaces sections 2 of the Apache License. You may, at your option, choose to treat any Work released under this License as released under the Apache License (thus ignoring all sections written below entirely). Words in italics indicate changes rom the Apache License, but are indicative and not to be taken into account in interpretation.
+
+1. The definitions set out in the Apache License are modified as follows:
+
+Copyright any reference to ‘copyright’ (whether capitalised or not) includes ‘Rights’ (as defined below).
+
+Contribution also includes any design, as well as any work of authorship.
+
+Derivative Works shall not include works that remain reversibly separable from, or merely link (or bind by name) or physically connect to or interoperate with the interfaces of the Work and Derivative Works thereof.
+
+Object form shall mean any form resulting from mechanical transformation or translation of a Source form or the application of a Source form to physical material, including but not limited to compiled object code, generated documentation, the instantiation of a hardware design or physical object and conversions to other media types, including intermediate forms such as bytecodes, FPGA bitstreams, moulds, artwork and semiconductor topographies (mask works).
+
+Rights means copyright and any similar right including design right (whether registered or unregistered), semiconductor topography (mask) rights and database rights (but excluding Patents and Trademarks).
+
+Source form shall mean the preferred form for making modifications, including but not limited to source code, net lists, board layouts, CAD files, documentation source, and configuration files.
+
+Work also includes a design or work of authorship, whether in Source form or other Object form.
+
+2. Grant of Licence
+
+2.1 Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable license under the Rights to reproduce, prepare Derivative Works of, make, adapt, repair, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form and do anything in relation to the Work as if the Rights did not exist.
diff --git a/third_party/tests/Scr1/Makefile b/third_party/tests/Scr1/Makefile
new file mode 100644
index 0000000..4976bf4
--- /dev/null
+++ b/third_party/tests/Scr1/Makefile
@@ -0,0 +1,202 @@
+#------------------------------------------------------------------------------
+# Makefile for SCR1
+#------------------------------------------------------------------------------
+
+# PARAMETERS
+
+ARCH ?=IMC
+IPIC ?=0
+export BUS  ?=AHB
+
+ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z)
+BUS_lowercase  = $(shell echo $(BUS)  | tr A-Z a-z)
+IPIC_lowercase = $(shell echo $(IPIC) | tr A-Z a-z)
+
+ifeq ($(ARCH_lowercase),)
+	export ARCH_tmp = imc
+else
+	ifneq (,$(findstring e,$(ARCH_lowercase)))
+		ARCH_tmp   += e
+		EXT_CFLAGS += -D__RVE_EXT
+	else
+		ARCH_tmp   += i
+	endif
+	ifneq (,$(findstring m,$(ARCH_lowercase)))
+		ARCH_tmp   := $(ARCH_tmp)m
+	endif
+	ifneq (,$(findstring c,$(ARCH_lowercase)))
+		ARCH_tmp   := $(ARCH_tmp)c
+		EXT_CFLAGS += -D__RVC_EXT
+	endif
+
+endif
+
+override ARCH=$(ARCH_tmp)
+
+$(info ARCH_tmp=$(ARCH_tmp))
+
+export TARGETS :=
+
+export ABI   ?= ilp32
+# Testbench memory delay patterns\
+  (FFFFFFFF - no delay, 00000000 - random delay, 00000001 - max delay)
+imem_pattern ?= FFFFFFFF
+dmem_pattern ?= FFFFFFFF
+
+VCS_OPTS       ?=
+MODELSIM_OPTS  ?=
+NCSIM_OPTS     ?=
+VERILATOR_OPTS ?=
+
+current_goal := $(MAKECMDGOALS:run_%=%)
+ifeq ($(current_goal),)
+  current_goal := verilator
+endif
+
+# Paths
+export root_dir := $(shell pwd)
+export tst_dir  := $(root_dir)/sim/tests
+export inc_dir  := $(tst_dir)/common
+export bld_dir  := $(root_dir)/build/$(current_goal)_$(BUS)_$(shell echo $(ARCH) | tr a-z A-Z)$(if $(findstring 1,$(IPIC)),_IPIC,)
+
+test_results := $(bld_dir)/test_results.txt
+test_info    := $(bld_dir)/test_info
+
+# Environment
+export CROSS_PREFIX  ?= riscv64-unknown-elf-
+export RISCV_GCC     ?= $(CROSS_PREFIX)gcc
+export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
+export RISCV_OBJCOPY ?= $(CROSS_PREFIX)objcopy -O verilog
+export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s
+#--
+ifneq (,$(findstring axi,$(BUS_lowercase)))
+export rtl_top_files := axi_top.files
+export rtl_tb_files  := axi_tb.files
+export top_module    := scr1_top_tb_axi
+else
+export rtl_top_files := ahb_top.files
+export rtl_tb_files  := ahb_tb.files
+export top_module    := scr1_top_tb_ahb
+endif
+#--
+ifeq (,$(findstring e,$(ARCH_lowercase)))
+ifeq (,$(findstring 0,$(IPIC)))
+# comment this target if you don't want to run the vectored_isr_sample
+TARGETS += vectored_isr_sample
+endif
+
+# comment this target if you don't want to run the riscv_isa
+TARGETS += riscv_isa
+
+# comment this target if you don't want to run the riscv_compliance
+TARGETS += riscv_compliance
+endif
+
+# comment this target if you don't want to run the coremark
+TARGETS += coremark
+# comment this target if you don't want to run the dhrystone
+TARGETS += dhrystone21
+# comment this target if you don't want to run the hello test
+TARGETS += hello
+
+# Targets
+.PHONY: tests run_modelsim run_vcs run_ncsim run_verilator run_verilator_wf
+
+default: run_verilator
+
+tests: $(TARGETS)
+
+$(test_info): clean_hex tests
+	cd $(bld_dir); \
+	ls -tr *.hex > $@
+
+vectored_isr_sample: | $(bld_dir)
+	$(MAKE) -C $(tst_dir)/vectored_isr_sample ARCH=$(ARCH)
+
+dhrystone21: | $(bld_dir)
+	$(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
+
+coremark: | $(bld_dir)
+	-$(MAKE) -C $(tst_dir)/benchmarks/coremark EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
+
+riscv_isa: | $(bld_dir)
+	$(MAKE) -C $(tst_dir)/riscv_isa ARCH=$(ARCH)
+
+riscv_compliance: | $(bld_dir)
+	$(MAKE) -C $(tst_dir)/riscv_compliance ARCH=$(ARCH)
+
+hello: | $(bld_dir)
+	-$(MAKE) -C $(tst_dir)/hello EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
+
+clean_hex: | $(bld_dir)
+	$(RM) $(bld_dir)/*.hex
+
+$(bld_dir):
+	mkdir -p $(bld_dir)
+
+run_vcs: $(test_info)
+	$(MAKE) -C $(root_dir)/sim build_vcs;
+	printf "" > $(test_results);
+	cd $(bld_dir); \
+	$(bld_dir)/simv \
+	+test_info=$(test_info) \
+	+test_results=$(test_results) \
+	+imem_pattern=$(imem_pattern) \
+	+dmem_pattern=$(dmem_pattern) \
+	$(VCS_OPTS)
+
+run_modelsim: $(test_info)
+	$(MAKE) -C $(root_dir)/sim build_modelsim; \
+	printf "" > $(test_results); \
+	cd $(bld_dir); \
+	vsim -c -do "run -all" +nowarn3691 \
+	+test_info=$(test_info) \
+	+test_results=$(test_results) \
+	+imem_pattern=$(imem_pattern) \
+	+dmem_pattern=$(dmem_pattern) \
+	work.$(top_module) \
+	$(MODELSIM_OPTS)
+
+run_ncsim: $(test_info)
+	$(MAKE) -C $(root_dir)/sim build_ncsim;
+	printf "" > $(test_results);
+	cd $(bld_dir); \
+	irun \
+	-R \
+	-64bit \
+	+test_info=$(test_info) \
+	+test_results=$(test_results) \
+	+imem_pattern=$(imem_pattern) \
+	+dmem_pattern=$(dmem_pattern) \
+	$(NCSIM_OPTS)
+
+run_verilator: $(test_info)
+	$(MAKE) -C $(root_dir)/sim build_verilator;
+	printf "" > $(test_results);
+	cd $(bld_dir); \
+	echo $(top_module) ; \
+	$(bld_dir)/verilator/V$(top_module) \
+	+test_info=$(test_info) \
+	+test_results=$(test_results) \
+	+imem_pattern=$(imem_pattern) \
+	+dmem_pattern=$(dmem_pattern) \
+	$(VERILATOR_OPTS)
+
+run_verilator_wf: $(test_info)
+	$(MAKE) -C $(root_dir)/sim build_verilator_wf;
+	printf "" > $(test_results);
+	cd $(bld_dir); \
+	echo $(top_module) ; \
+	$(bld_dir)/verilator/V$(top_module) \
+	+test_info=$(test_info) \
+	+test_results=$(test_results) \
+	+imem_pattern=$(imem_pattern) \
+	+dmem_pattern=$(dmem_pattern) \
+	$(VERILATOR_OPTS)
+
+clean:
+	$(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 clean
+	$(MAKE) -C $(tst_dir)/riscv_isa clean
+	$(MAKE) -C $(tst_dir)/riscv_compliance clean
+	$(RM) -R $(root_dir)/build/*
+	$(RM) $(test_info)
diff --git a/third_party/tests/Scr1/README.md b/third_party/tests/Scr1/README.md
new file mode 100644
index 0000000..72e54e9
--- /dev/null
+++ b/third_party/tests/Scr1/README.md
@@ -0,0 +1,157 @@
+SCR1 is an open-source RISC-V compatible MCU core, designed and maintained by Syntacore.
+
+## Key features
+* RV32I|E[MC] ISA
+* Machine privilege mode
+* 2 to 4 stage pipeline
+* 32-bit AXI4/AHB-Lite external interface
+* Integrated IRQ controller and advanced debug
+* Optimized for area and power
+* Written in SystemVerilog
+* Features a number of configurable parameters
+
+For more information, see SCR1 External Architecture Specification and SCR1 User Manual.
+
+## Repository contents
+Folder | Description
+------ | -----------
+docs                             | SCR1 documentation
+src                              | SCR1 RTL source and testbench files
+sim                              | Tests and scripts for simulation
+sim/tests/common                 | Common source files for tests
+sim/tests/riscv_isa              | Common source files for RISC-V ISA tests
+sim/tests/riscv_compliance       | Common source files for RISC-V Compliance tests
+sim/tests/benchmarks/dhrystone21 | Dhrystone 2.1 source files
+sim/tests/benchmarks/coremark    | Coremark platform specific source files
+sim/tests/vectored_isr_sample    | Simple test example for vectored interrupt mode
+sim/tests/hello                  | Simple "hello" test
+sim/verilator_wrap               | Wrappers for Verilator simulation
+
+## Quick start guide
+
+### Prerequisites
+
+RISC-V GCC toolchain is required to compile the software. You can use pre-built binaries or build the toolchain from scratch.
+
+#### Using pre-built binary tools
+
+Pre-built RISC-V GCC toolchain and OpenOCD binaries are available to download from http://syntacore.com/page/products/sw-tools. Download the archive (*.tar.gz* for Linux, *.zip* for Windows) for your platform, extract the archive to your preferred directory <GCC_INSTALL_PATH> and update the PATH environment variable as described in **Setting environment variables** section.
+
+#### Building tools from source
+
+You can build the RISC-V toolchain from sources.
+
+Build procedure is verified at the Ubuntu 14.04 LTS and Ubuntu 16.04 LTS distributions.
+
+    sudo apt-get install autoconf automake libmpc-dev libmpfr-dev libgmp-dev gawk bison flex texinfo libtool make g++ pkg-config libexpat1-dev zlib1g-dev
+    git clone https://github.com/riscv/riscv-gnu-toolchain.git
+    cd riscv-gnu-toolchain
+    git checkout a71fc539850f8dacf232fc580743b946c376014b
+    git submodule update --init --recursive
+    ./configure --prefix=<GCC_INSTALL_PATH> --enable-multilib
+    make
+
+More detailed instructions on how to prepare and build the toolchain can be found in https://github.com/riscv/riscv-tools/blob/master/README.md.
+
+#### Setting environment variables
+
+Add the <GCC_INSTALL_PATH>/bin folder to the PATH environment variable:
+
+    export PATH=$PATH:<GCC_INSTALL_PATH>/bin
+
+### Included tests
+
+By default, the simulation package includes the following tests:
+
+* riscv_isa
+* riscv_compliance
+* coremark
+* dhrystone21
+* vectored_isr_sample
+* hello
+
+Some of the tests depend on the selected architecture (e.g. rv32i|e base, supported extensions or IPIC), and therefore can not be used for all core configurations (these are skipped automatically).
+
+To run an arbitrary subset of tests, edit the *tests* target in the ./Makefile.
+Edit the *./sim/tests/riscv_isa/rv32_tests.inc* to specify subset of RISC-V ISA tests.
+
+#### Clone and prepare the RISC-V ISA tests
+
+Clone RISC-V ISA tests to your preferred directory <RISCV_TESTS_PATH>
+
+    git clone https://github.com/riscv/riscv-tests
+    cd riscv-tests
+    git checkout a9433c4daa287fbe101025f2a079261a10149225
+
+Set the $RISCV_TESTS environment variable accordingly:
+
+    export RISCV_TESTS=<RISCV_TESTS_PATH>
+
+#### Clone RISC-V Compliance tests
+
+Clone RISC-V Compliance tests to your preferred directory <RISCV_COMPLIANCE_TESTS_PATH>
+
+    git clone https://github.com/riscv/riscv-compliance
+    cd riscv-compliance
+    git checkout 9f280717f26f50833357db9bfb77a8c79835f162
+
+Set the $RISCV_COMPLIANCE_TESTS environment variable accordingly:
+
+    export RISCV_COMPLIANCE_TESTS=<RISCV_COMPLIANCE_TESTS_PATH>
+
+#### Prepare Coremark benchmark sources
+
+Download CoreMark from EEMBC's web site and extract the archive from
+http://www.eembc.org/coremark/download.php, or clone from https://github.com/eembc/coremark
+
+Copy the following files from into the `sim/tests/benchmarks/coremark/src` directory in this repository:
+
+* `core_main.c`
+* `core_list_join.c`
+* `coremark.h`
+* `core_matrix.c`
+* `core_state.c`
+* `core_util.c`
+
+### Running simulations 
+
+To build RTL, compile and run tests from the repo root folder:
+
+    make run_<SIMULATOR> BUS=<AHB, AXI> ARCH=<I, IM, IMC, IC, EM, EMC, EC> IPIC=<0, 1>
+
+By default, the following options are used: BUS=AHB ARCH=IMC IPIC=0.
+
+Build and run parameters can be configured in the *./Makefile*.
+
+After all the tests have finished, the results can be found in *build/test_results.txt* (default location).
+
+#### Simulator selection
+
+Currently supported simulators:
+
+* run_modelsim - Mentor Graphics ModelSim
+* run_vcs - Synopsys VCS
+* run_ncsim - Cadence NCSim
+* run_verilator - Verilator (version >= 4.0)
+* run_verilator_wf - Verilator with waveforms support
+
+Please note that RTL simulator executables should be in your PATH variable.
+
+For option run_verilator_wf the waveform is generated for the last executed test and is stored in ./build/simx.vcd.
+
+#### Architectural configuration
+
+The RISC-V toolchain automatically uses the selected ARCH for code compilation.
+
+Please make sure that architectural configuration selected for the SCR1 RTL
+matches the one used for tests compilation. SCR1 core parameters can be
+configured in *./src/includes/scr1_arch_description.svh*
+
+## SDKs
+
+There is number of FPGA-based SCR1 SDKs available.
+
+Please, refer to the https://github.com/syntacore/scr1-sdk for more details.
+
+## Contacts
+<scr1@syntacore.com>
diff --git a/third_party/tests/Scr1/Scr1.log b/third_party/tests/Scr1/Scr1.log
new file mode 100644
index 0000000..d043c7c
--- /dev/null
+++ b/third_party/tests/Scr1/Scr1.log
@@ -0,0 +1,225 @@
+[INFO :CM0023] Creating log file ../../../build/tests/Scr1/slpp_all/surelog.log.
+
+Scan libraries took 0.000s
+
+[WARNI:PP0103] src/includes/scr1_arch_description.svh:57 Undefining an unknown macro "SCR1_RVE_EXT".
+
+[WARNI:PP0103] src/includes/scr1_arch_description.svh:63 Undefining an unknown macro "SCR1_CLKCTRL_EN".
+
+Preprocessing took 0.660s
+
+Preprocessing took 0.660s
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+PP SSL Parsing: 0.000 src/top/scr1_imem_router.sv
+PP SSL Parsing: 0.000 src/top/scr1_dp_memory.sv
+PP SSL Parsing: 0.004 src/top/scr1_tcm.sv
+PP SSL Parsing: 0.002 src/top/scr1_timer.sv
+PP SSL Parsing: 0.002 src/top/scr1_mem_axi.sv
+PP SSL Parsing: 0.004 src/top/scr1_top_axi.sv
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+PP SSL Parsing: 0.002 src/tb/scr1_memory_tb_axi.sv
+PP SSL Parsing: 0.004 src/tb/scr1_top_tb_axi.sv
+
+Parsing took 16.392s
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+SSL Parsing: 0.190 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_core_top.sv
+SSL Parsing: 0.600 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_dm.sv
+SSL Parsing: 0.154 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_dmi.sv
+SSL Parsing: 0.262 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_scu.sv
+SSL Parsing: 0.026 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dmem_router.sv
+SSL Parsing: 0.008 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_imem_router.sv
+SSL Parsing: 0.038 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dp_memory.sv
+SSL Parsing: 0.030 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_tcm.sv
+SSL Parsing: 0.116 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_timer.sv
+LL  Parsing: 0.938 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_mem_axi.sv
+SSL Parsing: 0.076 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_top_axi.sv
+SSL Parsing: 0.412 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_tracelog.sv
+LL  Parsing: 2.548 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_memory_tb_axi.sv
+SSL Parsing: 1.156 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_top_tb_axi.sv
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_hdu.sv:13 No timescale set for "scr1_pipe_hdu".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_tdu.sv:11 No timescale set for "scr1_pipe_tdu".
+
+[WARNI:PA0205] src/pipeline/scr1_ipic.sv:11 No timescale set for "scr1_ipic".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_csr.sv:18 No timescale set for "scr1_pipe_csr".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_exu.sv:18 No timescale set for "scr1_pipe_exu".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_ialu.sv:10 No timescale set for "scr1_pipe_ialu".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_idu.sv:10 No timescale set for "scr1_pipe_idu".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_ifu.sv:10 No timescale set for "scr1_pipe_ifu".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_lsu.sv:12 No timescale set for "scr1_pipe_lsu".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_mprf.sv:8 No timescale set for "scr1_pipe_mprf".
+
+[WARNI:PA0205] src/pipeline/scr1_pipe_top.sv:21 No timescale set for "scr1_pipe_top".
+
+[WARNI:PA0205] src/core/primitives/scr1_reset_cells.sv:6 No timescale set for "scr1_reset_buf_cell".
+
+[WARNI:PA0205] src/core/primitives/scr1_reset_cells.sv:44 No timescale set for "scr1_reset_sync_cell".
+
+[WARNI:PA0205] src/core/primitives/scr1_reset_cells.sv:71 No timescale set for "scr1_reset_buf_qlfy_cell".
+
+[WARNI:PA0205] src/core/primitives/scr1_reset_cells.sv:132 No timescale set for "scr1_reset_and2_cell".
+
+[WARNI:PA0205] src/core/primitives/scr1_reset_cells.sv:144 No timescale set for "scr1_reset_and3_cell".
+
+[WARNI:PA0205] src/core/primitives/scr1_reset_cells.sv:156 No timescale set for "scr1_reset_mux2_cell".
+
+[WARNI:PA0205] src/core/scr1_tapc_shift_reg.sv:8 No timescale set for "scr1_tapc_shift_reg".
+
+[WARNI:PA0205] src/core/scr1_tapc.sv:11 No timescale set for "scr1_tapc".
+
+[WARNI:PA0205] src/core/scr1_tapc_synchronizer.sv:11 No timescale set for "scr1_tapc_synchronizer".
+
+[WARNI:PA0205] src/core/scr1_core_top.sv:18 No timescale set for "scr1_core_top".
+
+[WARNI:PA0205] src/core/scr1_dm.sv:11 No timescale set for "scr1_dm".
+
+[WARNI:PA0205] src/core/scr1_dmi.sv:10 No timescale set for "scr1_dmi".
+
+[WARNI:PA0205] src/core/scr1_scu.sv:9 No timescale set for "scr1_scu".
+
+[WARNI:PA0205] src/top/scr1_dmem_router.sv:7 No timescale set for "scr1_dmem_router".
+
+[WARNI:PA0205] src/top/scr1_imem_router.sv:7 No timescale set for "scr1_imem_router".
+
+[WARNI:PA0205] src/top/scr1_dp_memory.sv:8 No timescale set for "scr1_dp_memory".
+
+[WARNI:PA0205] src/top/scr1_tcm.sv:9 No timescale set for "scr1_tcm".
+
+[WARNI:PA0205] src/top/scr1_timer.sv:8 No timescale set for "scr1_timer".
+
+[WARNI:PA0205] src/top/scr1_mem_axi.sv:8 No timescale set for "scr1_mem_axi".
+
+[WARNI:PA0205] src/top/scr1_top_axi.sv:12 No timescale set for "scr1_top_axi".
+
+[WARNI:PA0205] src/pipeline/scr1_tracelog.sv:9 No timescale set for "scr1_tracelog".
+
+[WARNI:PA0205] src/tb/scr1_memory_tb_axi.sv:7 No timescale set for "scr1_memory_tb_axi".
+
+[WARNI:PA0205] src/tb/scr1_top_tb_axi.sv:9 No timescale set for "scr1_top_tb_axi".
+
+==============
+PROFILE
+==============
+Scan libraries took 0.000s
+Preprocessing took 0.660s
+PP SSL Parsing: 0.002 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
+PP SSL Parsing: 0.038 src/pipeline/scr1_pipe_hdu.sv
+PP SSL Parsing: 0.002 src/pipeline/scr1_pipe_tdu.sv
+PP SSL Parsing: 0.002 src/pipeline/scr1_ipic.sv
+PP SSL Parsing: 0.006 src/pipeline/scr1_pipe_csr.sv
+PP SSL Parsing: 0.010 src/pipeline/scr1_pipe_exu.sv
+PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_ialu.sv
+PP SSL Parsing: 0.006 src/pipeline/scr1_pipe_idu.sv
+PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_ifu.sv
+PP SSL Parsing: 0.002 src/pipeline/scr1_pipe_lsu.sv
+PP SSL Parsing: 0.000 src/pipeline/scr1_pipe_mprf.sv
+PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_top.sv
+PP SSL Parsing: 0.000 src/core/primitives/scr1_reset_cells.sv
+PP SSL Parsing: 0.000 src/core/primitives/scr1_cg.sv
+PP SSL Parsing: 0.000 src/core/scr1_clk_ctrl.sv
+PP SSL Parsing: 0.000 src/core/scr1_tapc_shift_reg.sv
+PP SSL Parsing: 0.002 src/core/scr1_tapc.sv
+PP SSL Parsing: 0.000 src/core/scr1_tapc_synchronizer.sv
+PP SSL Parsing: 0.002 src/core/scr1_core_top.sv
+PP SSL Parsing: 0.008 src/core/scr1_dm.sv
+PP SSL Parsing: 0.000 src/core/scr1_dmi.sv
+PP SSL Parsing: 0.002 src/core/scr1_scu.sv
+PP SSL Parsing: 0.002 src/top/scr1_dmem_router.sv
+PP SSL Parsing: 0.000 src/top/scr1_imem_router.sv
+PP SSL Parsing: 0.000 src/top/scr1_dp_memory.sv
+PP SSL Parsing: 0.004 src/top/scr1_tcm.sv
+PP SSL Parsing: 0.002 src/top/scr1_timer.sv
+PP SSL Parsing: 0.002 src/top/scr1_mem_axi.sv
+PP SSL Parsing: 0.004 src/top/scr1_top_axi.sv
+PP SSL Parsing: 0.006 src/pipeline/scr1_tracelog.sv
+PP SSL Parsing: 0.002 src/tb/scr1_memory_tb_axi.sv
+PP SSL Parsing: 0.004 src/tb/scr1_top_tb_axi.sv
+Parsing took 16.392s
+SSL Parsing: 0.038 ../../../build/tests/Scr1/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+SSL Parsing: 3.216 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_hdu.sv
+SSL Parsing: 0.906 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_tdu.sv
+LL  Parsing: 1.038 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_ipic.sv
+SSL Parsing: 0.336 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_csr.sv
+SSL Parsing: 0.466 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_exu.sv
+LL  Parsing: 1.272 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ialu.sv
+SSL Parsing: 0.618 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_idu.sv
+SSL Parsing: 0.398 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ifu.sv
+SSL Parsing: 0.058 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_lsu.sv
+SSL Parsing: 0.050 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_mprf.sv
+SSL Parsing: 0.226 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_top.sv
+SSL Parsing: 0.024 ../../../build/tests/Scr1/slpp_all/work/src/core/primitives/scr1_reset_cells.sv
+SSL Parsing: 0.000 ../../../build/tests/Scr1/slpp_all/work/src/core/primitives/scr1_cg.sv
+SSL Parsing: 0.000 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_clk_ctrl.sv
+SSL Parsing: 0.096 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc_shift_reg.sv
+SSL Parsing: 0.226 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc.sv
+SSL Parsing: 0.162 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc_synchronizer.sv
+SSL Parsing: 0.190 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_core_top.sv
+SSL Parsing: 0.600 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_dm.sv
+SSL Parsing: 0.154 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_dmi.sv
+SSL Parsing: 0.262 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_scu.sv
+SSL Parsing: 0.026 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dmem_router.sv
+SSL Parsing: 0.008 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_imem_router.sv
+SSL Parsing: 0.038 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dp_memory.sv
+SSL Parsing: 0.030 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_tcm.sv
+SSL Parsing: 0.116 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_timer.sv
+LL  Parsing: 0.938 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_mem_axi.sv
+SSL Parsing: 0.076 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_top_axi.sv
+SSL Parsing: 0.412 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_tracelog.sv
+LL  Parsing: 2.548 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_memory_tb_axi.sv
+SSL Parsing: 1.156 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_top_tb_axi.sv
+Total time 17.052s
+==============
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 36
+[   NOTE] : 0
+
diff --git a/third_party/tests/Scr1/Scr1.sl b/third_party/tests/Scr1/Scr1.sl
new file mode 100644
index 0000000..c199952
--- /dev/null
+++ b/third_party/tests/Scr1/Scr1.sl
@@ -0,0 +1 @@
+-writepp -parse -nocomp -noelab -profile -Isrc/includes src/pipeline/scr1_pipe_hdu.sv src/pipeline/scr1_pipe_tdu.sv src/pipeline/scr1_ipic.sv src/pipeline/scr1_pipe_csr.sv src/pipeline/scr1_pipe_exu.sv src/pipeline/scr1_pipe_ialu.sv src/pipeline/scr1_pipe_idu.sv src/pipeline/scr1_pipe_ifu.sv src/pipeline/scr1_pipe_lsu.sv src/pipeline/scr1_pipe_mprf.sv src/pipeline/scr1_pipe_top.sv src/core/primitives/scr1_reset_cells.sv src/core/primitives/scr1_cg.sv src/core/scr1_clk_ctrl.sv src/core/scr1_tapc_shift_reg.sv src/core/scr1_tapc.sv src/core/scr1_tapc_synchronizer.sv src/core/scr1_core_top.sv src/core/scr1_dm.sv src/core/scr1_dmi.sv src/core/scr1_scu.sv src/top/scr1_dmem_router.sv src/top/scr1_imem_router.sv src/top/scr1_dp_memory.sv src/top/scr1_tcm.sv src/top/scr1_timer.sv src/top/scr1_mem_axi.sv src/top/scr1_top_axi.sv src/pipeline/scr1_tracelog.sv src/tb/scr1_memory_tb_axi.sv src/tb/scr1_top_tb_axi.sv
\ No newline at end of file
diff --git a/third_party/tests/Scr1/docs/scr1_eas.pdf b/third_party/tests/Scr1/docs/scr1_eas.pdf
new file mode 100644
index 0000000..4a2b4ed
--- /dev/null
+++ b/third_party/tests/Scr1/docs/scr1_eas.pdf
Binary files differ
diff --git a/third_party/tests/Scr1/docs/scr1_um.pdf b/third_party/tests/Scr1/docs/scr1_um.pdf
new file mode 100644
index 0000000..ea24a09
--- /dev/null
+++ b/third_party/tests/Scr1/docs/scr1_um.pdf
Binary files differ
diff --git a/third_party/tests/Scr1/sim/Makefile b/third_party/tests/Scr1/sim/Makefile
new file mode 100644
index 0000000..31a28a3
--- /dev/null
+++ b/third_party/tests/Scr1/sim/Makefile
@@ -0,0 +1,105 @@
+# src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+rtl_src_dir := $(root_dir)/src/
+rtl_core_files ?= core.files
+rtl_top_files ?= ahb_top.files
+rtl_tb_files ?= ahb_tb.files
+rtl_inc_dir ?= $(root_dir)/src/includes
+top_module ?= scr1_top_tb_ahb
+
+rtl_core_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_core_files)))
+rtl_top_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_top_files)))
+rtl_tb_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_tb_files)))
+sv_list := $(rtl_core_list) $(rtl_top_list) $(rtl_tb_list)
+
+ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),build_verilator build_verilator_wf))
+ifeq ($(BUS),AHB)
+export scr1_wrapper  := $(root_dir)/sim/verilator_wrap/scr1_ahb_wrapper.c
+endif
+ifeq ($(BUS),AXI)
+export scr1_wrapper  := $(root_dir)/sim/verilator_wrap/scr1_axi_wrapper.c
+endif
+export verilator_ver ?= $(shell  expr `verilator --version | cut -f2 -d' '`)
+endif
+
+.PHONY: build_modelsim build_vcs build_ncsim build_verilator build_verilator_wf
+
+default: build_modelsim
+
+build_modelsim: $(sv_list)
+	cd $(bld_dir); \
+	vlib work; \
+	vmap work work; \
+	vlog -work work -O1 -mfcu -sv +incdir+$(rtl_inc_dir) +nowarnSVCHK  \
+	+define+SCR1_SIM_ENV \
+	$(sv_list)
+
+build_vcs: $(sv_list)
+	cd $(bld_dir); \
+	vcs \
+	-full64 \
+	-lca \
+	-sverilog \
+	-notice \
+	+lint=all,noVCDE \
+	-timescale=1ns/1ps \
+	+incdir+$(rtl_inc_dir) \
+	+define+SCR1_SIM_ENV \
+	-nc \
+	-debug_all \
+	$(sv_list)
+
+build_ncsim: $(sv_list)
+	cd $(bld_dir); \
+	irun \
+	-elaborate \
+	-64bit \
+	-disable_sem2009 \
+	-verbose \
+	-timescale 1ns/1ps \
+	-incdir $(rtl_inc_dir) \
+	-debug \
+	+define+SCR1_SIM_ENV \
+	$(sv_list) \
+	-top $(top_module)
+
+build_verilator: $(sv_list)
+	cd $(bld_dir); \
+	verilator \
+	-cc \
+	-sv \
+	+1800-2017ext+sv \
+	-Wno-fatal \
+	--top-module $(top_module) \
+	-DSCR1_SIM_ENV \
+	--clk clk \
+	--exe $(scr1_wrapper) \
+	--Mdir $(bld_dir)/verilator \
+	-I$(rtl_inc_dir) \
+	$(sv_list); \
+	cd verilator; \
+	$(MAKE) -f V$(top_module).mk;
+
+build_verilator_wf: $(sv_list)
+	cd $(bld_dir); \
+	verilator \
+	-cc \
+	-sv \
+	+1800-2017ext+sv \
+	-Wno-fatal \
+	--top-module $(top_module) \
+	-DSCR1_SIM_ENV \
+	-CFLAGS -DVCD_TRACE -CFLAGS -DTRACE_LVLV=20 \
+	-CFLAGS -DVCD_FNAME=simx.vcd \
+	--clk clk \
+	--exe $(scr1_wrapper) \
+	--trace \
+	--trace-params \
+    --trace-structs \
+    --trace-underscore \
+	--Mdir $(bld_dir)/verilator \
+	-I$(rtl_inc_dir) \
+	$(sv_list); \
+	cd verilator; \
+	$(MAKE) -f V$(top_module).mk;
+
+
diff --git a/third_party/tests/Scr1/sim/tests/benchmarks/coremark/Makefile b/third_party/tests/Scr1/sim/tests/benchmarks/coremark/Makefile
new file mode 100644
index 0000000..9a07dd5
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/benchmarks/coremark/Makefile
@@ -0,0 +1,31 @@
+src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+
+ifeq ("$(ITERATIONS)","")
+ITERATIONS=1
+endif
+
+ADD_CFLAGS  += -DITERATIONS=$(ITERATIONS)
+ADD_VPATH   := $(src_dir)/src
+ADD_incs    := -I$(src_dir)/src
+
+c_src := core_portme.c sc_print.c 
+coremark_src := ./src/core_list_join.c ./src/core_matrix.c ./src/core_main.c ./src/core_util.c ./src/core_state.c
+c_src += core_list_join.c core_matrix.c core_main.c core_util.c core_state.c
+
+include $(inc_dir)/common.mk
+
+default: check_coremark_src $(bld_dir)/coremark.elf $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump 
+
+check_coremark_src:
+	@for i in $(coremark_src) ; do \
+		if [ ! -f $$i ] ; then \
+		    printf "\n\n===========================================================================================\n"; \
+		    printf "Source file: $$i not exist!\n"; \
+		    printf "Please download CoreMark sources and place it '/coremark/src' directory in this repository\n"; \
+		    printf "===========================================================================================\n\n"; \
+		    exit 1; \
+		fi \
+	done
+
+clean:
+	$(RM) $(c_objs) $(asm_objs) $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump 
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/benchmarks/coremark/core_portme.c b/third_party/tests/Scr1/sim/tests/benchmarks/coremark/core_portme.c
new file mode 100644
index 0000000..3c801f7
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/benchmarks/coremark/core_portme.c
@@ -0,0 +1,141 @@
+/*
+	File : core_portme.c
+*/
+/*
+	Author : Shay Gal-On, EEMBC
+	Legal : TODO!
+*/
+#include <stdio.h>
+#include <stdlib.h>
+#include "coremark.h"
+#include "core_portme.h"
+#include "riscv_csr_encoding.h"
+#include "sc_test.h"
+
+#if VALIDATION_RUN
+	volatile ee_s32 seed1_volatile=0x3415;
+	volatile ee_s32 seed2_volatile=0x3415;
+	volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+	volatile ee_s32 seed1_volatile=0x0;
+	volatile ee_s32 seed2_volatile=0x0;
+	volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+	volatile ee_s32 seed1_volatile=0x8;
+	volatile ee_s32 seed2_volatile=0x8;
+	volatile ee_s32 seed3_volatile=0x8;
+#endif
+	volatile ee_s32 seed4_volatile=ITERATIONS;
+	volatile ee_s32 seed5_volatile=0;
+
+/* Porting : Timing functions
+	How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+	e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+	Sample implementation for standard time.h and windows.h definitions included.
+*/
+#if 1
+CORETIMETYPE barebones_clock() {
+	unsigned long n;
+	__asm__ __volatile__ (
+		"rdtime %0"
+		: "=r" (n));
+	return n;
+}
+#define CLOCKS_PER_SEC	10000000
+
+/* Define : TIMER_RES_DIVIDER
+	Divider to trade off timer resolution and total time that can be measured.
+
+	Use lower values to increase resolution, but make sure that overflow does not occur.
+	If there are issues with the return value overflowing, increase this value.
+	*/
+/* #define NSECS_PER_SEC CLOCKS_PER_SEC */
+/* #define CORETIMETYPE clock_t */
+#define GETMYTIME(_t) (*_t=barebones_clock())
+#define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+#define TIMER_RES_DIVIDER 1
+#define SAMPLE_TIME_IMPLEMENTATION 1
+#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER)
+#else
+
+#endif
+
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function : start_time
+	This function will be called right before starting the timed portion of the benchmark.
+
+	Implementation may be capturing a system timer (as implemented in the example code)
+	or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+	GETMYTIME(&start_time_val );
+}
+/* Function : stop_time
+	This function will be called right after ending the timed portion of the benchmark.
+
+	Implementation may be capturing a system timer (as implemented in the example code)
+	or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+	GETMYTIME(&stop_time_val );
+}
+/* Function : get_time
+	Return an abstract "ticks" number that signifies time on the system.
+
+	Actual value returned may be cpu cycles, milliseconds or any other value,
+	as long as it can be converted to seconds by <time_in_secs>.
+	This methodology is taken to accomodate any hardware or simulated platform.
+	The sample implementation returns millisecs by default,
+	and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+	CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+	return elapsed;
+}
+/* Function : time_in_secs
+	Convert the value returned by get_time to seconds.
+
+	The <secs_ret> type is used to accomodate systems with no support for floating point.
+	Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+	secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+	return retval;
+}
+
+ee_u32 default_num_contexts=1;
+
+/* Function : portable_init
+	Target specific initialization code
+	Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+    ee_printf("CoreMark 1.0\n");
+	if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+		ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer! (%u != %u)\n", sizeof(ee_ptr_int), sizeof(ee_u8 *));
+	}
+	if (sizeof(ee_u32) != 4) {
+		ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type! (%u)\n", sizeof(ee_u32));
+	}
+	p->portable_id=1;
+}
+/* Function : portable_fini
+	Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+	p->portable_id=0;
+
+    report_results(0, 0, 0, 0, 0);
+
+    /* results[0].iterations * 10000000/(total_time) */
+
+    /* extern void tohost_exit(long code); */
+
+    /* tohost_exit(0); */
+}
diff --git a/third_party/tests/Scr1/sim/tests/benchmarks/coremark/core_portme.h b/third_party/tests/Scr1/sim/tests/benchmarks/coremark/core_portme.h
new file mode 100644
index 0000000..857930f
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/benchmarks/coremark/core_portme.h
@@ -0,0 +1,210 @@
+/* File : core_portme.h */
+
+/*
+	Author : Shay Gal-On, EEMBC
+	Legal : TODO!
+*/
+/* Topic : Description
+	This file contains configuration constants required to execute on different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration : HAS_FLOAT
+	Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 0
+#endif
+/* Configuration : HAS_TIME_H
+	Define to 1 if platform has the time.h header file,
+	and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 0
+#endif
+/* Configuration : USE_CLOCK
+	Define to 1 if platform has the time.h header file,
+	and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration : HAS_STDIO
+	Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration : HAS_PRINTF
+	Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 0
+#endif
+
+#include "sc_print.h"
+#define ee_printf sc_printf
+
+/* static inline int ee_printf(const char *fmt, ...) {} */
+
+/* Configuration : CORE_TICKS
+	Define type of return from the timing functions.
+ */
+/* #include <time.h> */
+/* typedef clock_t CORE_TICKS; */
+#include <stdint.h>
+#include <stddef.h>
+#define CORETIMETYPE uint32_t
+typedef uint32_t CORE_TICKS;
+
+/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+	Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ /* #define MEM_LOCATION "STACK" */
+ #define MEM_LOCATION "STATIC"
+#endif
+
+/* Data Types :
+	To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+	*Imprtant* :
+	ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef int16_t ee_s16;
+typedef uint16_t ee_u16;
+typedef int32_t ee_s32;
+typedef float ee_f32;
+typedef uint8_t ee_u8;
+typedef uint32_t ee_u32;
+typedef uintptr_t ee_ptr_int;
+typedef size_t ee_size_t;
+/* align_mem :
+	This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration : SEED_METHOD
+	Defines method to get seed values that cannot be computed at compile time.
+
+	Valid values :
+	SEED_ARG - from command line.
+	SEED_FUNC - from a system function.
+	SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+/* Configuration : MEM_METHOD
+	Defines method to get a block of memry.
+
+	Valid values :
+	MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+	MEM_STATIC - to use a static memory array.
+	MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+/* #define MEM_METHOD MEM_STACK */
+#define MEM_METHOD MEM_STATIC
+#endif
+
+/* Configuration : MULTITHREAD
+	Define for parallel execution
+
+	Valid values :
+	1 - only one context (default).
+	N>1 - will execute N copies in parallel.
+
+	Note :
+	If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+	Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+	It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+	to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#define USE_PTHREAD 0
+#define USE_FORK 0
+#define USE_SOCKET 0
+#endif
+
+/* Configuration : MAIN_HAS_NOARGC
+	Needed if platform does not support getting arguments to main.
+
+	Valid values :
+	0 - argc/argv to main is supported
+	1 - argc/argv to main is not supported
+
+	Note :
+	This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 1
+#endif
+
+/* Configuration : MAIN_HAS_NORETURN
+	Needed if platform does not support returning a value from main.
+
+	Valid values :
+	0 - main returns an int, and return value will be 0.
+	1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable : default_num_contexts
+	Not used for this simple port, must cintain the value 1.
+*/
+extern ee_u32 default_num_contexts;
+
+typedef struct CORE_PORTABLE_S {
+	ee_u8	portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN)
+#if (TOTAL_DATA_SIZE==1200)
+#define PROFILE_RUN 1
+#elif (TOTAL_DATA_SIZE==2000)
+#define PERFORMANCE_RUN 1
+#else
+#define VALIDATION_RUN 1
+#endif
+#endif
+
+typedef ee_s16 MATDAT;
+typedef ee_s32 MATRES;
+
+
+ee_u16 crcu8(ee_u8 data, ee_u16 crc ) __attribute__ ((hot));
+ee_u16 crcu16(ee_u16 newval, ee_u16 crc) __attribute__ ((hot));
+ee_u16 crcu32(ee_u32 newval, ee_u16 crc) __attribute__ ((hot));
+ee_u16 crc16(ee_s16 newval, ee_u16 crc) __attribute__ ((hot));
+ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) __attribute__ ((hot));
+void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) __attribute__ ((hot));
+void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot));
+void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot));
+void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot));
+void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) __attribute__ ((hot));
+
+#endif /* CORE_PORTME_H */
diff --git a/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/Makefile b/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/Makefile
new file mode 100644
index 0000000..4e52408
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/Makefile
@@ -0,0 +1,13 @@
+src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+
+ADD_FLAGS   := -flto
+ADD_CFLAGS  := -DSELF_TIMED=1 -DTIME=1
+
+c_src := sc_print.c dhry_1.c dhry_2.c
+
+include $(inc_dir)/common.mk
+
+default: $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump
+
+clean:
+	$(RM) $(c_objs) $(asm_objs) $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry.h b/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry.h
new file mode 100644
index 0000000..cba0059
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry.h
@@ -0,0 +1,446 @@
+/*****************************************************************************
+ *  The BYTE UNIX Benchmarks - Release 3
+ *          Module: dhry.h   SID: 3.4 5/15/91 19:30:21
+ *
+ *****************************************************************************
+ * Bug reports, patches, comments, suggestions should be sent to:
+ *
+ *	Ben Smith, Rick Grehan or Tom Yager
+ *	ben@bytepb.byte.com   rick_g@bytepb.byte.com   tyager@bytepb.byte.com
+ *
+ *****************************************************************************
+ *  Modification Log:
+ *  addapted from:
+ *
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry.h (part 1 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *                      Siemens AG, AUT E 51
+ *                      Postfach 3220
+ *                      8520 Erlangen
+ *                      Germany (West)
+ *                              Phone:  [+49]-9131-7-20330
+ *                                      (8-17 Central European Time)
+ *                              Usenet: ..!mcvax!unido!estevax!weicker
+ *
+ *              Original Version (in Ada) published in
+ *              "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ *              pp. 1013 - 1030, together with the statistics
+ *              on which the distribution of statements etc. is based.
+ *
+ *              In this C version, the following C library functions are used:
+ *              - strcpy, strcmp (inside the measurement loop)
+ *              - printf, scanf (outside the measurement loop)
+ *              In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ *              are used for execution time measurement. For measurements
+ *              on other systems, these calls have to be changed.
+ *
+ *  Collection of Results:
+ *              Reinhold Weicker (address see above) and
+ *
+ *              Rick Richardson
+ *              PC Research. Inc.
+ *              94 Apple Orchard Drive
+ *              Tinton Falls, NJ 07724
+ *                      Phone:  (201) 834-1378 (9-17 EST)
+ *                      Usenet: ...!seismo!uunet!pcrat!rick
+ *
+ *      Please send results to Rick Richardson and/or Reinhold Weicker.
+ *      Complete information should be given on hardware and software used.
+ *      Hardware information includes: Machine type, CPU, type and size
+ *      of caches; for microprocessors: clock frequency, memory speed
+ *      (number of wait states).
+ *      Software information includes: Compiler (and runtime library)
+ *      manufacturer and version, compilation switches, OS version.
+ *      The Operating System version may give an indication about the
+ *      compiler; Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ *      The complete output generated by the program should be mailed
+ *      such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ *  History:    This version C/2.1 has been made for two reasons:
+ *
+ *              1) There is an obvious need for a common C version of
+ *              Dhrystone, since C is at present the most popular system
+ *              programming language for the class of processors
+ *              (microcomputers, minicomputers) where Dhrystone is used most.
+ *              There should be, as far as possible, only one C version of
+ *              Dhrystone such that results can be compared without
+ *              restrictions. In the past, the C versions distributed
+ *              by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ *              had small (though not significant) differences.
+ *
+ *              2) As far as it is possible without changes to the Dhrystone
+ *              statistics, optimizing compilers should be prevented from
+ *              removing significant statements.
+ *
+ *              This C version has been developed in cooperation with
+ *              Rick Richardson (Tinton Falls, NJ), it incorporates many
+ *              ideas from the "Version 1.1" distributed previously by
+ *              him over the UNIX network Usenet.
+ *              I also thank Chaim Benedelac (National Semiconductor),
+ *              David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ *              Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ *              for their help with comments on earlier versions of the
+ *              benchmark.
+ *
+ *  Changes:    In the initialization part, this version follows mostly
+ *              Rick Richardson's version distributed via Usenet, not the
+ *              version distributed earlier via floppy disk by Reinhold Weicker.
+ *              As a concession to older compilers, names have been made
+ *              unique within the first 8 characters.
+ *              Inside the measurement loop, this version follows the
+ *              version previously distributed by Reinhold Weicker.
+ *
+ *              At several places in the benchmark, code has been added,
+ *              but within the measurement loop only in branches that
+ *              are not executed. The intention is that optimizing compilers
+ *              should be prevented from moving code out of the measurement
+ *              loop, or from removing code altogether. Since the statements
+ *              that are executed within the measurement loop have NOT been
+ *              changed, the numbers defining the "Dhrystone distribution"
+ *              (distribution of statements, operand types and locality)
+ *              still hold. Except for sophisticated optimizing compilers,
+ *              execution times for this version should be the same as
+ *              for previous versions.
+ *
+ *              Since it has proven difficult to subtract the time for the
+ *              measurement loop overhead in a correct way, the loop check
+ *              has been made a part of the benchmark. This does have
+ *              an impact - though a very minor one - on the distribution
+ *              statistics which have been updated for this version.
+ *
+ *              All changes within the measurement loop are described
+ *              and discussed in the companion paper "Rationale for
+ *              Dhrystone version 2".
+ *
+ *              Because of the self-imposed limitation that the order and
+ *              distribution of the executed statements should not be
+ *              changed, there are still cases where optimizing compilers
+ *              may not generate code for some statements. To a certain
+ *              degree, this is unavoidable for small synthetic benchmarks.
+ *              Users of the benchmark are advised to check code listings
+ *              whether code is generated for all statements of Dhrystone.
+ *
+ *              Version 2.1 is identical to version 2.0 distributed via
+ *              the UNIX network Usenet in March 1988 except that it corrects
+ *              some minor deficiencies that were found by users of version 2.0.
+ *              The only change within the measurement loop is that a
+ *              non-executed "else" part was added to the "if" statement in
+ *              Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ ***************************************************************************
+ *
+ * Defines:     The following "Defines" are possible:
+ *              -DREG=register          (default: Not defined)
+ *                      As an approximation to what an average C programmer
+ *                      might do, the "register" storage class is applied
+ *                      (if enabled by -DREG=register)
+ *                      - for local variables, if they are used (dynamically)
+ *                        five or more times
+ *                      - for parameters if they are used (dynamically)
+ *                        six or more times
+ *                      Note that an optimal "register" strategy is
+ *                      compiler-dependent, and that "register" declarations
+ *                      do not necessarily lead to faster execution.
+ *              -DNOSTRUCTASSIGN        (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      assignment of structures.
+ *              -DNOENUMS               (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      enumeration types.
+ *              -DTIMES                 (default)
+ *              -DTIME
+ *                      The "times" function of UNIX (returning process times)
+ *                      or the "time" function (returning wallclock time)
+ *                      is used for measurement.
+ *                      For single user machines, "time ()" is adequate. For
+ *                      multi-user machines where you cannot get single-user
+ *                      access, use the "times ()" function. If you have
+ *                      neither, use a stopwatch in the dead of night.
+ *                      "printf"s are provided marking the points "Start Timer"
+ *                      and "Stop Timer". DO NOT use the UNIX "time(1)"
+ *                      command, as this will measure the total time to
+ *                      run this program, which will (erroneously) include
+ *                      the time to allocate storage (malloc) and to perform
+ *                      the initialization.
+ *              -DHZ=nnn
+ *                      In Berkeley UNIX, the function "times" returns process
+ *                      time in 1/HZ seconds, with HZ = 60 for most systems.
+ *                      CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ *                      A VALUE.
+ *
+ ***************************************************************************
+ *
+ *  Compilation model and measurement (IMPORTANT):
+ *
+ *  This C version of Dhrystone consists of three files:
+ *  - dhry.h (this file, containing global definitions and comments)
+ *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ *  The following "ground rules" apply for measurements:
+ *  - Separate compilation
+ *  - No procedure merging
+ *  - Otherwise, compiler optimizations are allowed but should be indicated
+ *  - Default results are those without register declarations
+ *  See the companion paper "Rationale for Dhrystone Version 2" for a more
+ *  detailed discussion of these ground rules.
+ *
+ *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ *  models ("small", "medium", "large" etc.) should be given if possible,
+ *  together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ *  Dhrystone (C version) statistics:
+ *
+ *  [Comment from the first distribution, updated for version 2.
+ *   Note that because of language differences, the numbers are slightly
+ *   different from the Ada version.]
+ *
+ *  The following program contains statements of a high level programming
+ *  language (here: C) in a distribution considered representative:
+ *
+ *    assignments                  52 (51.0 %)
+ *    control statements           33 (32.4 %)
+ *    procedure, function calls    17 (16.7 %)
+ *
+ *  103 statements are dynamically executed. The program is balanced with
+ *  respect to the three aspects:
+ *
+ *    - statement type
+ *    - operand type
+ *    - operand locality
+ *         operand global, local, parameter, or constant.
+ *
+ *  The combination of these three aspects is balanced only approximately.
+ *
+ *  1. Statement Type:
+ *  -----------------             number
+ *
+ *     V1 = V2                     9
+ *       (incl. V1 = F(..)
+ *     V = Constant               12
+ *     Assignment,                 7
+ *       with array element
+ *     Assignment,                 6
+ *       with record component
+ *                                --
+ *                                34       34
+ *
+ *     X = Y +|-|"&&"|"|" Z        5
+ *     X = Y +|-|"==" Constant     6
+ *     X = X +|- 1                 3
+ *     X = Y *|/ Z                 2
+ *     X = Expression,             1
+ *           two operators
+ *     X = Expression,             1
+ *           three operators
+ *                                --
+ *                                18       18
+ *
+ *     if ....                    14
+ *       with "else"      7
+ *       without "else"   7
+ *           executed        3
+ *           not executed    4
+ *     for ...                     7  |  counted every time
+ *     while ...                   4  |  the loop condition
+ *     do ... while                1  |  is evaluated
+ *     switch ...                  1
+ *     break                       1
+ *     declaration with            1
+ *       initialization
+ *                                --
+ *                                34       34
+ *
+ *     P (...)  procedure call    11
+ *       user procedure      10
+ *       library procedure    1
+ *     X = F (...)
+ *             function  call      6
+ *       user function        5
+ *       library function     1
+ *                                --
+ *                                17       17
+ *                                        ---
+ *                                        103
+ *
+ *    The average number of parameters in procedure or function calls
+ *    is 1.82 (not counting the function values as implicit parameters).
+ *
+ *
+ *  2. Operators
+ *  ------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *    Arithmetic             32          50.8
+ *
+ *       +                     21          33.3
+ *       -                      7          11.1
+ *       *                      3           4.8
+ *       / (int div)            1           1.6
+ *
+ *    Comparison             27           42.8
+ *
+ *       ==                     9           14.3
+ *       /=                     4            6.3
+ *       >                      1            1.6
+ *       <                      3            4.8
+ *       >=                     1            1.6
+ *       <=                     9           14.3
+ *
+ *    Logic                   4            6.3
+ *
+ *       && (AND-THEN)          1            1.6
+ *       |  (OR)                1            1.6
+ *       !  (NOT)               2            3.2
+ *
+ *                           --          -----
+ *                           63          100.1
+ *
+ *
+ *  3. Operand Type (counted once per operand reference):
+ *  ---------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *     Integer               175        72.3 %
+ *     Character              45        18.6 %
+ *     Pointer                12         5.0 %
+ *     String30                6         2.5 %
+ *     Array                   2         0.8 %
+ *     Record                  2         0.8 %
+ *                           ---       -------
+ *                           242       100.0 %
+ *
+ *  When there is an access path leading to the final operand (e.g. a record
+ *  component), only the final data type on the access path is counted.
+ *
+ *
+ *  4. Operand Locality:
+ *  -------------------
+ *                                number    approximate
+ *                                          percentage
+ *
+ *     local variable              114        47.1 %
+ *     global variable              22         9.1 %
+ *     parameter                    45        18.6 %
+ *        value                        23         9.5 %
+ *        reference                    22         9.1 %
+ *     function result               6         2.5 %
+ *     constant                     55        22.7 %
+ *                                 ---       -------
+ *                                 242       100.0 %
+ *
+ *
+ *  The program does not compute anything meaningful, but it is syntactically
+ *  and semantically correct. All variables have a value assigned to them
+ *  before they are used as a source operand.
+ *
+ *  There has been no explicit effort to account for the effects of a
+ *  cache, or to balance the use of long or short displacements for code or
+ *  data.
+ *
+ ***************************************************************************
+ */
+
+
+/* Compiler and system dependent definitions: */
+
+#ifndef TIME
+#define TIMES
+#endif
+                /* Use times(2) time function unless    */
+                /* explicitly defined otherwise         */
+
+#ifdef TIMES
+#include <sys/types.h>
+#include <sys/times.h>
+                /* for "times" */
+#endif
+
+#define Mic_secs_Per_Second     1000000
+                /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef  NOSTRUCTASSIGN
+#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s)      d = s
+#endif
+
+#ifdef  NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+  typedef int   Enumeration;
+#else
+  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+                Enumeration;
+#endif
+        /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+#include <string.h>
+                /* for strcpy, strcmp */
+
+#define Null 0
+                /* Value of a Null pointer */
+#define true  1
+#define false 0
+
+typedef int     One_Thirty;
+typedef int     One_Fifty;
+typedef char    Capital_Letter;
+typedef int     Boolean;
+typedef char    Str_30 [31];
+typedef int     Arr_1_Dim [50];
+typedef int     Arr_2_Dim [50] [50];
+
+typedef struct record
+    {
+    struct record *Ptr_Comp;
+    Enumeration    Discr;
+    union {
+          struct {
+                  Enumeration Enum_Comp;
+                  int         Int_Comp;
+                  char        Str_Comp [31];
+                  } var_1;
+          struct {
+                  Enumeration E_Comp_2;
+                  char        Str_2_Comp [31];
+                  } var_2;
+          struct {
+                  char        Ch_1_Comp;
+                  char        Ch_2_Comp;
+                  } var_3;
+          } variant;
+      } Rec_Type, *Rec_Pointer;
+
+#include "sc_print.h"
+#include "csr.h"
+
+# define printf sc_printf
+
+#define HZ 1000000
+static long time(long *x)
+{
+    return rdcycle();
+}
diff --git a/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c b/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c
new file mode 100644
index 0000000..d52acbb
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c
@@ -0,0 +1,461 @@
+/*****************************************************************************
+ *  The BYTE UNIX Benchmarks - Release 3
+ *          Module: dhry_1.c   SID: 3.4 5/15/91 19:30:21
+ *
+ *****************************************************************************
+ * Bug reports, patches, comments, suggestions should be sent to:
+ *
+ *	Ben Smith, Rick Grehan or Tom Yager
+ *	ben@bytepb.byte.com   rick_g@bytepb.byte.com   tyager@bytepb.byte.com
+ *
+ *****************************************************************************
+ *
+ * *** WARNING ****  With BYTE's modifications applied, results obtained with
+ *     *******       this version of the Dhrystone program may not be applicable
+ *                   to other versions.
+ *
+ *  Modification Log:
+ *  10/22/97 - code cleanup to remove ANSI C compiler warnings
+ *             Andy Kahn <kahn@zk3.dec.com>
+ *
+ *  Adapted from:
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry_1.c (part 2 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ ***************************************************************************/
+char SCCSid[] = "@(#) @(#)dhry_1.c:3.4 -- 5/15/91 19:30:21";
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "dhry.h"
+//#include "timeit.c"
+
+unsigned long Run_Index;
+/*
+void report()
+{
+	fprintf(stderr,"COUNT|%ld|1|lps\n", Run_Index);
+	exit(0);
+}
+*/
+/* Global Variables: */
+
+Rec_Pointer     Ptr_Glob,
+                Next_Ptr_Glob;
+int             Int_Glob;
+Boolean         Bool_Glob;
+char            Ch_1_Glob,
+                Ch_2_Glob;
+int             Arr_1_Glob [50];
+int             Arr_2_Glob [50] [50];
+
+Enumeration     Func_1 ();
+  /* forward declaration necessary since Enumeration may not simply be int */
+
+#ifndef REG
+        Boolean Reg = false;
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+        Boolean Reg = true;
+#endif
+
+/* variables for time measurement: */
+
+#ifdef TIMES
+struct tms      time_info;
+/* extern  int     times (); */
+                /* see library function "times" */
+#define Too_Small_Time 120
+                /* Measurements should last at least about 2 seconds */
+#endif
+#ifdef TIME
+extern long     time();
+                /* see library function "time"  */
+#define Too_Small_Time 2
+                /* Measurements should last at least 2 seconds */
+#endif
+
+long            Begin_Time,
+                End_Time,
+                User_Time;
+#if 0
+float           Microseconds,
+                Dhrystones_Per_Second;
+#else
+long            Microseconds,
+                Dhrystones_Per_Second;
+#endif
+
+/* end of variables for time measurement */
+
+void Proc_1 (REG Rec_Pointer Ptr_Val_Par);
+void Proc_2 (One_Fifty   *Int_Par_Ref);
+void Proc_3 (Rec_Pointer *Ptr_Ref_Par);
+void Proc_4 (void);
+void Proc_5 (void);
+
+
+extern Boolean Func_2(Str_30, Str_30);
+extern void Proc_6(Enumeration, Enumeration *);
+extern void Proc_7(One_Fifty, One_Fifty, One_Fifty *);
+extern void Proc_8(Arr_1_Dim, Arr_2_Dim, int, int);
+
+int main (argc, argv)
+int	argc;
+char	*argv[];
+  /* main program, corresponds to procedures        */
+  /* Main and Proc_0 in the Ada version             */
+{
+#ifdef SELF_TIMED
+        int             Number_Of_Runs;
+#else /* SELF_TIMED */
+        int             duration;
+#endif /* SELF_TIMED */
+        One_Fifty       Int_1_Loc;
+  REG   One_Fifty       Int_2_Loc;
+        One_Fifty       Int_3_Loc;
+  REG   char            Ch_Index;
+        Enumeration     Enum_Loc;
+        Str_30          Str_1_Loc;
+        Str_30          Str_2_Loc;
+
+  /* Initializations */
+#if 0
+  Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+  Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+#else
+  static Rec_Type glob1, glob2;
+  Next_Ptr_Glob = &glob1;
+  Ptr_Glob = &glob2;
+#endif
+
+  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
+  Ptr_Glob->Discr                       = Ident_1;
+  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
+  Ptr_Glob->variant.var_1.Int_Comp      = 40;
+  strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+          "DHRYSTONE PROGRAM, SOME STRING");
+  strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+  Arr_2_Glob [8][7] = 10;
+        /* Was missing in published program. Without this statement,    */
+        /* Arr_2_Glob [8][7] would have an undefined value.             */
+        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */
+        /* overflow may occur for this array element.                   */
+
+#ifdef SELF_TIMED
+  Number_Of_Runs = 500;//500000;
+  if (argc >= 2) {
+    Number_Of_Runs = atoi(argv[1]);
+    }
+  printf ("\n");
+  printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+  printf ("\n");
+  if (Reg)
+  {
+    printf ("Program compiled with 'register' attribute\n");
+    printf ("\n");
+  }
+  else
+  {
+    printf ("Program compiled without 'register' attribute\n");
+    printf ("\n");
+  }
+#ifdef PRATTLE
+  printf ("Please give the number of runs through the benchmark: ");
+  {
+    int n;
+    scanf ("%d", &n);
+    Number_Of_Runs = n;
+  }
+  printf ("\n");
+#endif /* PRATTLE */
+
+  printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+
+  Run_Index = 0;
+#else /* SELF_TIMED */
+  if (argc != 2) {
+    fprintf(stderr, "Usage: %s duration\n", argv[0]);
+    exit(1);
+    }
+
+  duration = atoi(argv[1]);
+  Run_Index = 0;
+  wake_me(duration, report);
+#endif /* SELF_TIMED */
+
+  /***************/
+  /* Start timer */
+  /***************/
+
+#ifdef SELF_TIMED
+#ifdef TIMES
+  times (&time_info);
+  Begin_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+  Begin_Time = time ( (long *) 0);
+#endif
+#endif /* SELF_TIMED */
+
+#ifdef SELF_TIMED
+  for (Run_Index = 1; Run_Index <= Number_Of_Runs ; ++Run_Index)
+#else /* SELF_TIMED */
+  for (Run_Index = 1; ; ++Run_Index)
+#endif /* SELF_TIMED */
+  {
+
+    Proc_5();
+    Proc_4();
+      /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+    Int_1_Loc = 2;
+    Int_2_Loc = 3;
+    strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+    Enum_Loc = Ident_2;
+    Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+      /* Bool_Glob == 1 */
+    while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
+    {
+      Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+        /* Int_3_Loc == 7 */
+      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+        /* Int_3_Loc == 7 */
+      Int_1_Loc += 1;
+    } /* while */
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+      /* Int_Glob == 5 */
+    Proc_1 (Ptr_Glob);
+    for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+                             /* loop body executed twice */
+    {
+      if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+          /* then, not executed */
+        {
+        Proc_6 (Ident_1, &Enum_Loc);
+        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+        Int_2_Loc = Run_Index;
+        Int_Glob = Run_Index;
+        }
+    }
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Int_2_Loc = Int_2_Loc * Int_1_Loc;
+    Int_1_Loc = Int_2_Loc / Int_3_Loc;
+    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+      /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+    Proc_2 (&Int_1_Loc);
+      /* Int_1_Loc == 5 */
+
+  } /* loop "for Run_Index" */
+
+  /**************/
+  /* Stop timer */
+  /**************/
+#ifdef SELF_TIMED
+#ifdef TIMES
+  times (&time_info);
+  End_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+  End_Time = time ( (long *) 0);
+#endif
+#endif /* SELF_TIMED */
+
+  /* BYTE version never executes this stuff */
+#ifdef SELF_TIMED
+  printf ("Execution ends\n");
+  printf ("\n");
+  printf ("Final values of the variables used in the benchmark:\n");
+  printf ("\n");
+  printf ("Int_Glob:            %d\n", Int_Glob);
+  printf ("        should be:   %d\n", 5);
+  printf ("Bool_Glob:           %d\n", Bool_Glob);
+  printf ("        should be:   %d\n", 1);
+  printf ("Ch_1_Glob:           %c\n", Ch_1_Glob);
+  printf ("        should be:   %c\n", 'A');
+  printf ("Ch_2_Glob:           %c\n", Ch_2_Glob);
+  printf ("        should be:   %c\n", 'B');
+  printf ("Arr_1_Glob[8]:       %d\n", Arr_1_Glob[8]);
+  printf ("        should be:   %d\n", 7);
+  printf ("Arr_2_Glob[8][7]:    %d\n", Arr_2_Glob[8][7]);
+  printf ("        should be:   Number_Of_Runs + 10\n");
+  printf ("Ptr_Glob->\n");
+  printf ("  Ptr_Comp:          %d\n", (int) Ptr_Glob->Ptr_Comp);
+  printf ("        should be:   (implementation-dependent)\n");
+  printf ("  Discr:             %d\n", Ptr_Glob->Discr);
+  printf ("        should be:   %d\n", 0);
+  printf ("  Enum_Comp:         %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+  printf ("        should be:   %d\n", 2);
+  printf ("  Int_Comp:          %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+  printf ("        should be:   %d\n", 17);
+  printf ("  Str_Comp:          %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  printf ("Next_Ptr_Glob->\n");
+  printf ("  Ptr_Comp:          %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+  printf ("        should be:   (implementation-dependent), same as above\n");
+  printf ("  Discr:             %d\n", Next_Ptr_Glob->Discr);
+  printf ("        should be:   %d\n", 0);
+  printf ("  Enum_Comp:         %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+  printf ("        should be:   %d\n", 1);
+  printf ("  Int_Comp:          %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+  printf ("        should be:   %d\n", 18);
+  printf ("  Str_Comp:          %s\n",
+                                Next_Ptr_Glob->variant.var_1.Str_Comp);
+  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  printf ("Int_1_Loc:           %d\n", Int_1_Loc);
+  printf ("        should be:   %d\n", 5);
+  printf ("Int_2_Loc:           %d\n", Int_2_Loc);
+  printf ("        should be:   %d\n", 13);
+  printf ("Int_3_Loc:           %d\n", Int_3_Loc);
+  printf ("        should be:   %d\n", 7);
+  printf ("Enum_Loc:            %d\n", Enum_Loc);
+  printf ("        should be:   %d\n", 1);
+  printf ("Str_1_Loc:           %s\n", Str_1_Loc);
+  printf ("        should be:   DHRYSTONE PROGRAM, 1'ST STRING\n");
+  printf ("Str_2_Loc:           %s\n", Str_2_Loc);
+  printf ("        should be:   DHRYSTONE PROGRAM, 2'ND STRING\n");
+  printf ("\n");
+
+  User_Time = End_Time - Begin_Time;
+
+  if (User_Time < Too_Small_Time)
+  {
+    printf ("Measured time too small to obtain meaningful results\n");
+    printf ("Please increase number of runs\n");
+    printf ("\n");
+  }
+  else
+  {
+#if 0
+#ifdef TIME
+    Microseconds = (float) User_Time * Mic_secs_Per_Second
+                        / (float) Number_Of_Runs;
+    Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;
+#else
+    Microseconds = (float) User_Time * Mic_secs_Per_Second
+                        / ((float) HZ * ((float) Number_Of_Runs));
+    Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+                        / (float) User_Time;
+#endif
+#else
+  Microseconds = ((User_Time / Number_Of_Runs) * Mic_secs_Per_Second) / HZ;
+  Dhrystones_Per_Second = (HZ * Number_Of_Runs) / User_Time;
+
+  sc_printf("Number_Of_Runs= %ld, HZ= %ld\n", Number_Of_Runs, HZ);
+  sc_printf("Time: begin= %ld, end= %ld, diff= %ld\n", Begin_Time, End_Time, User_Time);
+  sc_printf("Microseconds for one run through Dhrystone: %ld\n", Microseconds);
+  sc_printf("Dhrystones per Second:                      %ld\n", Dhrystones_Per_Second);
+
+#endif
+  }
+#endif /* SELF_TIMED */
+}
+
+
+void Proc_1 (REG Rec_Pointer Ptr_Val_Par)
+    /* executed once */
+{
+  REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+                                        /* == Ptr_Glob_Next */
+  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
+  /* corresponds to "rename" in Ada, "with" in Pascal           */
+
+  structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+  Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+  Next_Record->variant.var_1.Int_Comp
+        = Ptr_Val_Par->variant.var_1.Int_Comp;
+  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+  Proc_3 (&Next_Record->Ptr_Comp);
+    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
+                        == Ptr_Glob->Ptr_Comp */
+  if (Next_Record->Discr == Ident_1)
+    /* then, executed */
+  {
+    Next_Record->variant.var_1.Int_Comp = 6;
+    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
+           &Next_Record->variant.var_1.Enum_Comp);
+    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+           &Next_Record->variant.var_1.Int_Comp);
+  }
+  else /* not executed */
+    structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+void Proc_2 (One_Fifty   *Int_Par_Ref)
+    /* executed once */
+    /* *Int_Par_Ref == 1, becomes 4 */
+{
+  One_Fifty  Int_Loc;
+  Enumeration   Enum_Loc;
+
+  Enum_Loc = 0;
+
+  Int_Loc = *Int_Par_Ref + 10;
+  do /* executed once */
+    if (Ch_1_Glob == 'A')
+      /* then, executed */
+    {
+      Int_Loc -= 1;
+      *Int_Par_Ref = Int_Loc - Int_Glob;
+      Enum_Loc = Ident_1;
+    } /* if */
+  while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+void Proc_3 (Rec_Pointer *Ptr_Ref_Par)
+    /* executed once */
+    /* Ptr_Ref_Par becomes Ptr_Glob */
+{
+  if (Ptr_Glob != Null)
+    /* then, executed */
+    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+void Proc_4 (void) /* without parameters */
+    /* executed once */
+{
+  Boolean Bool_Loc;
+
+  Bool_Loc = Ch_1_Glob == 'A';
+  Bool_Glob = Bool_Loc | Bool_Glob;
+  Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+void Proc_5 (void) /* without parameters */
+/*******/
+    /* executed once */
+{
+  Ch_1_Glob = 'A';
+  Bool_Glob = false;
+} /* Proc_5 */
+
+
+        /* Procedure for the assignment of structures,          */
+        /* if the C compiler doesn't support this feature       */
+#ifdef  NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char   *d;
+register char   *s;
+register int    l;
+{
+        while (l--) *d++ = *s++;
+}
+#endif
diff --git a/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c b/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c
new file mode 100644
index 0000000..140161f
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c
@@ -0,0 +1,209 @@
+/*****************************************************************************
+ *  The BYTE UNIX Benchmarks - Release 3
+ *          Module: dhry_2.c   SID: 3.4 5/15/91 19:30:22
+ *          
+ *****************************************************************************
+ * Bug reports, patches, comments, suggestions should be sent to:
+ *
+ *	Ben Smith, Rick Grehan or Tom Yager
+ *	ben@bytepb.byte.com   rick_g@bytepb.byte.com   tyager@bytepb.byte.com
+ *
+ *****************************************************************************
+ *  Modification Log:
+ *  10/22/97 - code cleanup to remove ANSI C compiler warnings
+ *             Andy Kahn <kahn@zk3.dec.com>
+ *
+ *  Adapted from:
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ * **** WARNING **** See warning in n.dhry_1.c
+ *                                                                            
+ *  Version:    C, Version 2.1
+ *                                                                            
+ *  File:       dhry_2.c (part 3 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ ****************************************************************************/
+/* SCCSid is defined in dhry_1.c */
+
+#include <string.h>
+#include "dhry.h"
+
+#ifndef REG
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#endif
+
+extern  int     Int_Glob;
+extern  char    Ch_1_Glob;
+
+void Proc_6(Enumeration, Enumeration *);
+void Proc_7(One_Fifty, One_Fifty, One_Fifty *);
+void Proc_8(Arr_1_Dim, Arr_2_Dim, int, int);
+Enumeration Func_1(Capital_Letter, Capital_Letter);
+Boolean Func_2(Str_30, Str_30);
+Boolean Func_3(Enumeration);
+
+void Proc_6 (Enumeration Enum_Val_Par, Enumeration *Enum_Ref_Par)
+    /* executed once */
+    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+{
+  *Enum_Ref_Par = Enum_Val_Par;
+  if (! Func_3 (Enum_Val_Par))
+    /* then, not executed */
+    *Enum_Ref_Par = Ident_4;
+  switch (Enum_Val_Par)
+  {
+    case Ident_1: 
+      *Enum_Ref_Par = Ident_1;
+      break;
+    case Ident_2: 
+      if (Int_Glob > 100)
+        /* then */
+      *Enum_Ref_Par = Ident_1;
+      else *Enum_Ref_Par = Ident_4;
+      break;
+    case Ident_3: /* executed */
+      *Enum_Ref_Par = Ident_2;
+      break;
+    case Ident_4: break;
+    case Ident_5: 
+      *Enum_Ref_Par = Ident_3;
+      break;
+  } /* switch */
+} /* Proc_6 */
+
+void Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+One_Fifty       Int_1_Par_Val;
+One_Fifty       Int_2_Par_Val;
+One_Fifty      *Int_Par_Ref;
+/**********************************************/
+    /* executed three times                                      */ 
+    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
+    /*                  Int_Par_Ref becomes 7                    */
+    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+    /*                  Int_Par_Ref becomes 17                   */
+    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+    /*                  Int_Par_Ref becomes 18                   */
+{
+  One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 2;
+  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+void Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+    /* executed once      */
+    /* Int_Par_Val_1 == 3 */
+    /* Int_Par_Val_2 == 7 */
+Arr_1_Dim       Arr_1_Par_Ref;
+Arr_2_Dim       Arr_2_Par_Ref;
+int             Int_1_Par_Val;
+int             Int_2_Par_Val;
+{
+  REG One_Fifty Int_Index;
+  REG One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 5;
+  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+  Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Capital_Letter Ch_1_Par_Val, Capital_Letter Ch_2_Par_Val)
+/*************************************************/
+    /* executed three times                                         */
+    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
+    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
+    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
+{
+  Capital_Letter        Ch_1_Loc;
+  Capital_Letter        Ch_2_Loc;
+
+  Ch_1_Loc = Ch_1_Par_Val;
+  Ch_2_Loc = Ch_1_Loc;
+  if (Ch_2_Loc != Ch_2_Par_Val)
+    /* then, executed */
+    return (Ident_1);
+  else  /* not executed */
+  {
+    Ch_1_Glob = Ch_1_Loc;
+    return (Ident_2);
+   }
+} /* Func_1 */
+
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+    /* executed once */
+    /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+    /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30  Str_1_Par_Ref;
+Str_30  Str_2_Par_Ref;
+{
+  REG One_Thirty        Int_Loc;
+      Capital_Letter    Ch_Loc;
+
+  Ch_Loc = 'A';
+  Int_Loc = 2;
+  while (Int_Loc <= 2) /* loop body executed once */
+    if (Func_1 (Str_1_Par_Ref[Int_Loc],
+                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+      /* then, executed */
+    {
+      Ch_Loc = 'A';
+      Int_Loc += 1;
+    } /* if, while */
+  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+    /* then, not executed */
+    Int_Loc = 7;
+  if (Ch_Loc == 'R')
+    /* then, not executed */
+    return (true);
+  else /* executed */
+  {
+    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+      /* then, not executed */
+    {
+      Int_Loc += 7;
+      Int_Glob = Int_Loc;
+      return (true);
+    }
+    else /* executed */
+      return (false);
+  } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+    /* executed once        */
+    /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+  Enumeration Enum_Loc;
+
+  Enum_Loc = Enum_Par_Val;
+  if (Enum_Loc == Ident_3)
+    /* then, executed */
+    return (true);
+  else /* not executed */
+    return (false);
+} /* Func_3 */
+
diff --git a/third_party/tests/Scr1/sim/tests/common/LICENSE b/third_party/tests/Scr1/sim/tests/common/LICENSE
new file mode 100644
index 0000000..48fe522
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/LICENSE
@@ -0,0 +1,24 @@
+Copyright (c) 2012-2015, The Regents of the University of California (Regents).
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+   names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
diff --git a/third_party/tests/Scr1/sim/tests/common/common.mk b/third_party/tests/Scr1/sim/tests/common/common.mk
new file mode 100644
index 0000000..c535a83
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/common.mk
@@ -0,0 +1,44 @@
+ADD_ASM_MACRO ?= -D__ASSEMBLY__=1
+
+FLAGS = -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las $(ADD_FLAGS)
+FLAGS_STR = "$(FLAGS)"
+
+CFLAGS_COMMON = -static -std=gnu99 -fno-common -fno-builtin-printf
+CFLAGS_ARCH = -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI)
+
+CFLAGS := $(FLAGS) $(EXT_CFLAGS) \
+$(CFLAGS_COMMON) \
+$(CFLAGS_ARCH) \
+-DFLAGS_STR=\"$(FLAGS_STR)\" \
+$(ADD_CFLAGS)
+
+LDFLAGS   ?= -nostartfiles -nostdlib -lc -lgcc -march=rv32$(ARCH) -mabi=$(ABI)
+
+ifdef TCM
+ld_script := $(inc_dir)/link_tcm.ld
+asm_src   ?= crt_tcm.S
+else
+ld_script := $(inc_dir)/link.ld
+asm_src   ?= crt.S
+endif
+
+VPATH += $(src_dir) $(inc_dir) $(ADD_VPATH)
+incs  += -I$(src_dir) -I$(inc_dir) $(ADD_incs)
+
+c_objs   := $(addprefix $(bld_dir)/,$(patsubst %.c, %.o, $(c_src)))
+asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src)))
+
+$(bld_dir)/%.o: %.S
+	$(RISCV_GCC) $(CFLAGS) $(ADD_ASM_MACRO) -c $(incs) $< -o $@
+
+$(bld_dir)/%.o: %.c
+	$(RISCV_GCC) $(CFLAGS) -c $(incs) $< -o $@
+
+$(bld_dir)/%.elf: $(ld_script) $(c_objs) $(asm_objs)
+	$(RISCV_GCC) -o $@ -T $^ $(LDFLAGS)
+
+$(bld_dir)/%.hex: $(bld_dir)/%.elf
+	$(RISCV_OBJCOPY) $^ $@
+
+$(bld_dir)/%.dump: $(bld_dir)/%.elf
+	$(RISCV_OBJDUMP) $^ > $@
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/common/crt.S b/third_party/tests/Scr1/sim/tests/common/crt.S
new file mode 100644
index 0000000..f979e6c
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/crt.S
@@ -0,0 +1,141 @@
+/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+/// @file       <crt.S>
+///
+
+#include "riscv_csr_encoding.h"
+
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+
+    .globl _start
+    .globl main
+    .globl trap_entry
+    .globl handle_trap
+    .globl sc_exit
+    .weak trap_entry, handle_trap, sc_exit
+
+    .text
+    .org (64*3)
+    .align 6
+machine_trap_entry:
+    j trap_entry
+
+    .align 6
+
+_start:
+    # Global pointer init
+    .option push
+    .option norelax
+    la    gp, __global_pointer$
+    .option pop
+    # clear bss
+    la      a1, __BSS_START__
+    la      a2, __BSS_END__
+    j       4f
+3:  sw      zero, 0(a1)
+    add     a1, a1, 4
+4:  bne     a1, a2, 3b
+    la      sp, __C_STACK_TOP__
+
+    // Timer init
+    li      t0, mtime_ctrl
+    li      t1, (1 << SCR1_MTIME_CTRL_EN)   // enable, use internal clock
+    sw      t1, (t0)
+    li      t0, mtime_div
+    li      t1, (100-1)                     // divide by 100
+    sw      t1, (t0)
+    li      t0, mtimecmp
+    li      t1, -1
+    sw      t1, (t0)                        // max value for mtimecmp
+    sw      t1, 4(t0)
+
+    li      a0, 0
+    li      a1, 0
+    jal     main
+    j       sc_exit
+
+trap_entry:
+    addi sp, sp, -272
+
+    SREG x1, 1*REGBYTES(sp)
+    SREG x2, 2*REGBYTES(sp)
+    SREG x3, 3*REGBYTES(sp)
+    SREG x4, 4*REGBYTES(sp)
+    SREG x5, 5*REGBYTES(sp)
+    SREG x6, 6*REGBYTES(sp)
+    SREG x7, 7*REGBYTES(sp)
+    SREG x8, 8*REGBYTES(sp)
+    SREG x9, 9*REGBYTES(sp)
+    SREG x10, 10*REGBYTES(sp)
+    SREG x11, 11*REGBYTES(sp)
+    SREG x12, 12*REGBYTES(sp)
+    SREG x13, 13*REGBYTES(sp)
+    SREG x14, 14*REGBYTES(sp)
+    SREG x15, 15*REGBYTES(sp)
+#ifndef __RVE_EXT
+    SREG x16, 16*REGBYTES(sp)
+    SREG x17, 17*REGBYTES(sp)
+    SREG x18, 18*REGBYTES(sp)
+    SREG x19, 19*REGBYTES(sp)
+    SREG x20, 20*REGBYTES(sp)
+    SREG x21, 21*REGBYTES(sp)
+    SREG x22, 22*REGBYTES(sp)
+    SREG x23, 23*REGBYTES(sp)
+    SREG x24, 24*REGBYTES(sp)
+    SREG x25, 25*REGBYTES(sp)
+    SREG x26, 26*REGBYTES(sp)
+    SREG x27, 27*REGBYTES(sp)
+    SREG x28, 28*REGBYTES(sp)
+    SREG x29, 29*REGBYTES(sp)
+    SREG x30, 30*REGBYTES(sp)
+    SREG x31, 31*REGBYTES(sp)
+#endif // __RVE_EXT
+
+    csrr a0, mcause
+    csrr a1, mepc
+    mv a2, sp
+    jal handle_trap
+
+    LREG x1, 1*REGBYTES(sp)
+    LREG x2, 2*REGBYTES(sp)
+    LREG x3, 3*REGBYTES(sp)
+    LREG x4, 4*REGBYTES(sp)
+    LREG x5, 5*REGBYTES(sp)
+    LREG x6, 6*REGBYTES(sp)
+    LREG x7, 7*REGBYTES(sp)
+    LREG x8, 8*REGBYTES(sp)
+    LREG x9, 9*REGBYTES(sp)
+    LREG x10, 10*REGBYTES(sp)
+    LREG x11, 11*REGBYTES(sp)
+    LREG x12, 12*REGBYTES(sp)
+    LREG x13, 13*REGBYTES(sp)
+    LREG x14, 14*REGBYTES(sp)
+    LREG x15, 15*REGBYTES(sp)
+#ifndef __RVE_EXT
+    LREG x16, 16*REGBYTES(sp)
+    LREG x17, 17*REGBYTES(sp)
+    LREG x18, 18*REGBYTES(sp)
+    LREG x19, 19*REGBYTES(sp)
+    LREG x20, 20*REGBYTES(sp)
+    LREG x21, 21*REGBYTES(sp)
+    LREG x22, 22*REGBYTES(sp)
+    LREG x23, 23*REGBYTES(sp)
+    LREG x24, 24*REGBYTES(sp)
+    LREG x25, 25*REGBYTES(sp)
+    LREG x26, 26*REGBYTES(sp)
+    LREG x27, 27*REGBYTES(sp)
+    LREG x28, 28*REGBYTES(sp)
+    LREG x29, 29*REGBYTES(sp)
+    LREG x30, 30*REGBYTES(sp)
+    LREG x31, 31*REGBYTES(sp)
+#endif // __RVE_EXT
+
+    addi sp, sp, 272
+    mret
+
+handle_trap:
+sc_exit:
+    j SIM_EXIT
+
+// end of crt.S
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/common/crt_tcm.S b/third_party/tests/Scr1/sim/tests/common/crt_tcm.S
new file mode 100644
index 0000000..23519bd
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/crt_tcm.S
@@ -0,0 +1,172 @@
+/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+/// @file       <crt_tcm.S>
+///
+
+#include "riscv_csr_encoding.h"
+
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+
+    .globl _start
+    .globl main
+    .globl trap_entry
+    .globl handle_trap
+    .globl sc_exit
+    .weak trap_entry, handle_trap, sc_exit
+
+    .section .text.init
+    .org (64*3)
+    .align 6;
+machine_trap_entry:
+    j trap_entry
+
+    .align 6
+_start:
+    # Global pointer init
+    .option push
+    .option norelax
+    la    gp, __global_pointer$
+    .option pop
+    la    a0, __reloc_start
+    la    a1, __TEXT_START__
+    la    a2, __DATA_START__
+    beq   a0, a1, 21f
+    j     2f
+1:  lw    a3, 0(a0)
+    sw    a3, 0(a1)
+    add   a0, a0, 4
+    add   a1, a1, 4
+2:  bne   a1, a2, 1b
+    # clear bss
+    la    a2, __BSS_START__
+21: la    a1, __BSS_END__
+    j     4f
+3:  sw    zero, 0(a2)
+    add   a2, a2, 4
+4:  bne   a1, a2, 3b
+    // init stack
+    la    sp, __C_STACK_TOP__
+    // init hart0 TLS
+    la    a0, _tdata_begin
+    la    a2, _tbss_end
+    sub   a1, a2, a0
+    la    a4, __STACK_START__
+    sub   tp, a4, a1
+    // init tdata
+    mv    a1, tp
+    la    a2, _tdata_end
+    j     6f
+5:  lw    a3, 0(a0)
+    sw    a3, 0(a1)
+    add   a0, a0, 4
+    add   a1, a1, 4
+6:  bne   a0, a2, 5b
+    // clear tbss
+    j     8f
+7:  sw    zero, 0(a1)
+    add   a1, a1, 4
+8:  bne   a1, a4, 7b
+
+    // Timer init
+    li    t0, mtime_ctrl
+    li    t1, (1 << SCR1_MTIME_CTRL_EN)   // enable, use internal clock
+    sw    t1, (t0)
+    li    t0, mtime_div
+    li    t1, (100-1)                     // divide by 100
+    sw    t1, (t0)
+    li    t0, mtimecmp
+    li    t1, -1
+    sw    t1, (t0)                        // max value for mtimecmp
+    sw    t1, 4(t0)
+
+    li    a0, 0
+    li    a1, 0
+9:  auipc t0, %pcrel_hi(main)
+    jalr  t0, %pcrel_lo(9b)
+    j     sc_exit
+
+trap_entry:
+    addi sp, sp, -272
+
+    SREG x1, 1*REGBYTES(sp)
+    SREG x2, 2*REGBYTES(sp)
+    SREG x3, 3*REGBYTES(sp)
+    SREG x4, 4*REGBYTES(sp)
+    SREG x5, 5*REGBYTES(sp)
+    SREG x6, 6*REGBYTES(sp)
+    SREG x7, 7*REGBYTES(sp)
+    SREG x8, 8*REGBYTES(sp)
+    SREG x9, 9*REGBYTES(sp)
+    SREG x10, 10*REGBYTES(sp)
+    SREG x11, 11*REGBYTES(sp)
+    SREG x12, 12*REGBYTES(sp)
+    SREG x13, 13*REGBYTES(sp)
+    SREG x14, 14*REGBYTES(sp)
+    SREG x15, 15*REGBYTES(sp)
+#ifndef __RVE_EXT
+    SREG x16, 16*REGBYTES(sp)
+    SREG x17, 17*REGBYTES(sp)
+    SREG x18, 18*REGBYTES(sp)
+    SREG x19, 19*REGBYTES(sp)
+    SREG x20, 20*REGBYTES(sp)
+    SREG x21, 21*REGBYTES(sp)
+    SREG x22, 22*REGBYTES(sp)
+    SREG x23, 23*REGBYTES(sp)
+    SREG x24, 24*REGBYTES(sp)
+    SREG x25, 25*REGBYTES(sp)
+    SREG x26, 26*REGBYTES(sp)
+    SREG x27, 27*REGBYTES(sp)
+    SREG x28, 28*REGBYTES(sp)
+    SREG x29, 29*REGBYTES(sp)
+    SREG x30, 30*REGBYTES(sp)
+    SREG x31, 31*REGBYTES(sp)
+#endif // __RVE_EXT
+
+    csrr a0, mcause
+    csrr a1, mepc
+    mv a2, sp
+    jal handle_trap
+
+    LREG x1, 1*REGBYTES(sp)
+    LREG x2, 2*REGBYTES(sp)
+    LREG x3, 3*REGBYTES(sp)
+    LREG x4, 4*REGBYTES(sp)
+    LREG x5, 5*REGBYTES(sp)
+    LREG x6, 6*REGBYTES(sp)
+    LREG x7, 7*REGBYTES(sp)
+    LREG x8, 8*REGBYTES(sp)
+    LREG x9, 9*REGBYTES(sp)
+    LREG x10, 10*REGBYTES(sp)
+    LREG x11, 11*REGBYTES(sp)
+    LREG x12, 12*REGBYTES(sp)
+    LREG x13, 13*REGBYTES(sp)
+    LREG x14, 14*REGBYTES(sp)
+    LREG x15, 15*REGBYTES(sp)
+#ifndef __RVE_EXT
+    LREG x16, 16*REGBYTES(sp)
+    LREG x17, 17*REGBYTES(sp)
+    LREG x18, 18*REGBYTES(sp)
+    LREG x19, 19*REGBYTES(sp)
+    LREG x20, 20*REGBYTES(sp)
+    LREG x21, 21*REGBYTES(sp)
+    LREG x22, 22*REGBYTES(sp)
+    LREG x23, 23*REGBYTES(sp)
+    LREG x24, 24*REGBYTES(sp)
+    LREG x25, 25*REGBYTES(sp)
+    LREG x26, 26*REGBYTES(sp)
+    LREG x27, 27*REGBYTES(sp)
+    LREG x28, 28*REGBYTES(sp)
+    LREG x29, 29*REGBYTES(sp)
+    LREG x30, 30*REGBYTES(sp)
+    LREG x31, 31*REGBYTES(sp)
+#endif // __RVE_EXT
+
+    addi sp, sp, 272
+    mret
+
+handle_trap:
+sc_exit:
+    j SIM_EXIT
+
+// end of crt.S
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/common/csr.h b/third_party/tests/Scr1/sim/tests/common/csr.h
new file mode 100644
index 0000000..72c60fc
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/csr.h
@@ -0,0 +1,113 @@
+/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+/// @file       <csr.h>
+/// Architecture specific CSR's defs and inlines
+
+#ifndef SCR_CSR_H
+#define SCR_CSR_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define __xstringify(s) __stringify(s)
+#define __stringify(s) #s
+
+#ifdef read_csr
+#undef read_csr
+#endif
+
+#ifdef write_csr
+#undef write_csr
+#endif
+
+#ifdef swap_csr
+#undef swap_csr
+#endif
+
+#ifdef set_csr
+#undef set_csr
+#endif
+
+#ifdef clear_csr
+#undef clear_csr
+#endif
+
+#ifdef rdtime
+#undef rdtime
+#endif
+
+#ifdef rdcycle
+#undef rdcycle
+#endif
+
+#ifdef rdinstret
+#undef rdinstret
+#endif
+
+#define read_csr(reg)                                               \
+    ({                                                              \
+        unsigned long __tmp;                                        \
+        asm volatile ("csrr %0, " __xstringify(reg) : "=r"(__tmp)); \
+        __tmp;                                                      \
+    })
+
+#define write_csr(reg, val)                                             \
+    do {                                                                \
+        if (__builtin_constant_p(val) && (val) == 0)                    \
+            asm volatile ("csrw " __xstringify(reg) ", zero" ::);       \
+        else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+            asm volatile ("csrw " __xstringify(reg) ", %0" :: "i"(val)); \
+        else                                                            \
+            asm volatile ("csrw " __xstringify(reg) ", %0" :: "r"(val)); \
+    } while (0)
+
+#define swap_csr(reg, val)                                              \
+    ({                                                                  \
+        unsigned long __tmp;                                            \
+        if (__builtin_constant_p(val) && (val) == 0)                    \
+            asm volatile ("csrrw %0, " __xstringify(reg) ", zero" :  "=r"(__tmp) :); \
+        else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+            asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(val)); \
+        else                                                            \
+            asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(val)); \
+        __tmp;                                                          \
+    })
+
+#define set_csr(reg, bit)                                               \
+    ({                                                                  \
+        unsigned long __tmp;                                            \
+        if (__builtin_constant_p(bit) && (bit) < 32)                    \
+            asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \
+        else                                                            \
+            asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \
+        __tmp;                                                          \
+    })
+
+#define clear_csr(reg, bit)                                             \
+    ({                                                                  \
+        unsigned long __tmp;                                            \
+        if (__builtin_constant_p(bit) && (bit) < 32)                    \
+            asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \
+        else                                                            \
+            asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \
+        __tmp;                                                          \
+    })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+static inline unsigned long __attribute__((const)) cpuid()
+{
+  unsigned long res;
+  asm ("csrr %0, mcpuid" : "=r"(res));
+  return res;
+}
+
+static inline unsigned long __attribute__((const)) impid()
+{
+  unsigned long res;
+  asm ("csrr %0, mimpid" : "=r"(res));
+  return res;
+}
+
+#endif // SCR_CSR_H
diff --git a/third_party/tests/Scr1/sim/tests/common/link.ld b/third_party/tests/Scr1/sim/tests/common/link.ld
new file mode 100644
index 0000000..050c58d
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/link.ld
@@ -0,0 +1,99 @@
+/*
+* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+* @file       <link.ld>
+* @brief      bare metal tests' linker script
+*/
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+MEMORY {
+  RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K
+}
+
+STACK_SIZE = 1024;
+
+CL_SIZE = 32;
+
+SECTIONS {
+
+  /* code segment */
+  .text.init 0 : { 
+    FILL(0);
+    . = 0x100 - 12;
+    SIM_EXIT = .;
+    LONG(0x13);
+    SIM_STOP = .;
+    LONG(0x6F);
+    LONG(-1);
+    . = 0x100;
+    PROVIDE(__TEXT_START__ = .);
+    *(.text.init) 
+  } >RAM
+
+  .text  : {
+    *crt.o(.text .text.*)
+    *(.text .text.*)
+    *(sc_test_section)
+    . = ALIGN(CL_SIZE);
+     PROVIDE(__TEXT_END__ = .);
+  } >RAM 
+
+  /* data segment */
+  .data : {
+    *(.data .data.*)
+    . = ALIGN(CL_SIZE);
+  } >RAM
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+    . = ALIGN(CL_SIZE);
+  } >RAM
+
+  /* thread-local data segment */
+  .tdata : {
+    PROVIDE(_tls_data = .);
+    PROVIDE(_tdata_begin = .);
+    *(.tdata .tdata.*)
+    PROVIDE(_tdata_end = .);
+    . = ALIGN(CL_SIZE);
+  } >RAM
+
+  .tbss : {
+    PROVIDE(__BSS_START__ = .);
+    *(.tbss .tbss.*)
+    . = ALIGN(CL_SIZE);
+    PROVIDE(_tbss_end = .);
+  } >RAM
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  } >RAM
+
+  .bss : {
+    *(.bss .bss.*)
+    . = ALIGN(CL_SIZE);
+    PROVIDE(__BSS_END__ = .);
+  } >RAM
+
+  _end = .;
+  PROVIDE(__end = .);
+
+  /* End of uninitalized data segement */
+
+  .stack ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE : {
+    FILL(0);
+    PROVIDE(__STACK_START__ = .);
+    . += STACK_SIZE;
+    PROVIDE(__C_STACK_TOP__ = .);
+    PROVIDE(__STACK_END__ = .);
+  } >RAM
+
+  /DISCARD/ : {
+    *(.eh_frame .eh_frame.*)
+  }
+}
diff --git a/third_party/tests/Scr1/sim/tests/common/link_tcm.ld b/third_party/tests/Scr1/sim/tests/common/link_tcm.ld
new file mode 100644
index 0000000..dff8c33
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/link_tcm.ld
@@ -0,0 +1,107 @@
+/*
+* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+* @file       <link.ld>
+* @brief      bare metal tests' linker script
+*/
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+MEMORY {
+  RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K
+  TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 64K
+}
+
+STACK_SIZE = 1024;
+
+CL_SIZE = 32;
+
+SECTIONS {
+
+  /* code segment */
+  .text.init ORIGIN(RAM) : { 
+    FILL(0);
+    . = 0x100 - 12;
+    SIM_EXIT = .;
+    LONG(0x13);
+    SIM_STOP = .;
+    LONG(0x6F);
+    LONG(-1);
+    . = 0x100;
+    *crt_tcm.o(.text .text.*)
+  } >RAM
+
+  __reloc_start = .;
+
+  .text : {
+    PROVIDE(__TEXT_START__ = .);
+    *(.text .text.*)
+    *(sc_test_section)
+    . = ALIGN(CL_SIZE);
+     PROVIDE(__TEXT_END__ = .);
+  } >TCM AT>RAM
+
+  .rodata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
+    . = ALIGN(16);
+  } >TCM AT>RAM
+
+  /* data segment */
+  .data : {
+    PROVIDE(__DATA_START__ = .);
+    *(.data .data.*)
+    . = ALIGN(CL_SIZE);
+  } >TCM AT>RAM
+
+  .sdata : {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+    . = ALIGN(CL_SIZE);
+    PROVIDE(__DATA_END__ = .);
+  } >TCM AT>RAM
+
+  /* thread-local data segment */
+  .tdata : {
+    PROVIDE(_tls_data = .);
+    PROVIDE(_tdata_begin = .);
+    *(.tdata .tdata.*)
+    PROVIDE(_tdata_end = .);
+    . = ALIGN(CL_SIZE);
+  } >TCM AT>RAM
+
+  .tbss : {
+    PROVIDE(_tbss_begin = .);
+    *(.tbss .tbss.*)
+    . = ALIGN(CL_SIZE);
+    PROVIDE(_tbss_end = .);
+  } >TCM AT>RAM
+
+  /* bss segment */
+  .sbss : {
+    PROVIDE(__BSS_START__ = .);
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  } >TCM AT>RAM
+
+  .bss : {
+    *(.bss .bss.*)
+    . = ALIGN(CL_SIZE);
+    PROVIDE(__BSS_END__ = .);
+  } >TCM AT>RAM
+
+  _end = .;
+  PROVIDE(__end = .);
+
+  /* End of uninitalized data segement */
+
+  .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : {
+    PROVIDE(__STACK_START__ = .);
+    . += STACK_SIZE;
+    PROVIDE(__C_STACK_TOP__ = .);
+    PROVIDE(__STACK_END__ = .);
+  } >TCM
+
+  /DISCARD/ : {
+    *(.eh_frame .eh_frame.*)
+  }
+}
diff --git a/third_party/tests/Scr1/sim/tests/common/riscv_csr_encoding.h b/third_party/tests/Scr1/sim/tests/common/riscv_csr_encoding.h
new file mode 100644
index 0000000..a1c9f64
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/riscv_csr_encoding.h
@@ -0,0 +1,1473 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_HPP         0x00000600
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_SUM         0x00040000
+#define MSTATUS_MXR         0x00080000
+#define MSTATUS_TVM         0x00100000
+#define MSTATUS_TW          0x00200000
+#define MSTATUS_TSR         0x00400000
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS_UXL         0x0000000300000000
+#define MSTATUS_SXL         0x0000000C00000000
+#define MSTATUS64_SD        0x8000000000000000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_SUM         0x00040000
+#define SSTATUS_MXR         0x00080000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS_UXL         0x0000000300000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define DCSR_XDEBUGVER      (3U<<30)
+#define DCSR_NDRESET        (1<<29)
+#define DCSR_FULLRESET      (1<<28)
+#define DCSR_EBREAKM        (1<<15)
+#define DCSR_EBREAKH        (1<<14)
+#define DCSR_EBREAKS        (1<<13)
+#define DCSR_EBREAKU        (1<<12)
+#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STOPTIME       (1<<9)
+#define DCSR_CAUSE          (7<<6)
+#define DCSR_DEBUGINT       (1<<5)
+#define DCSR_HALT           (1<<3)
+#define DCSR_STEP           (1<<2)
+#define DCSR_PRV            (3<<0)
+
+#define DCSR_CAUSE_NONE     0
+#define DCSR_CAUSE_SWBP     1
+#define DCSR_CAUSE_HWBP     2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP     4
+#define DCSR_CAUSE_HALT     5
+
+#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT     (1<<19)
+#define MCONTROL_TIMING     (1<<18)
+#define MCONTROL_ACTION     (0x3f<<12)
+#define MCONTROL_CHAIN      (1<<11)
+#define MCONTROL_MATCH      (0xf<<7)
+#define MCONTROL_M          (1<<6)
+#define MCONTROL_H          (1<<5)
+#define MCONTROL_S          (1<<4)
+#define MCONTROL_U          (1<<3)
+#define MCONTROL_EXECUTE    (1<<2)
+#define MCONTROL_STORE      (1<<1)
+#define MCONTROL_LOAD       (1<<0)
+
+#define MCONTROL_TYPE_NONE      0
+#define MCONTROL_TYPE_MATCH     2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
+#define MCONTROL_ACTION_DEBUG_MODE        1
+#define MCONTROL_ACTION_TRACE_START       2
+#define MCONTROL_ACTION_TRACE_STOP        3
+#define MCONTROL_ACTION_TRACE_EMIT        4
+
+#define MCONTROL_MATCH_EQUAL     0
+#define MCONTROL_MATCH_NAPOT     1
+#define MCONTROL_MATCH_GE        2
+#define MCONTROL_MATCH_LT        3
+#define MCONTROL_MATCH_MASK_LOW  4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP            (1 << IRQ_S_SOFT)
+#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_STIP            (1 << IRQ_S_TIMER)
+#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_SEIP            (1 << IRQ_S_EXT)
+#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_MEIP            (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define SPTBR32_MODE 0x80000000
+#define SPTBR32_ASID 0x7FC00000
+#define SPTBR32_PPN  0x003FFFFF
+#define SPTBR64_MODE 0xF000000000000000
+#define SPTBR64_ASID 0x0FFFF00000000000
+#define SPTBR64_PPN  0x00000FFFFFFFFFFF
+
+#define SPTBR_MODE_OFF  0
+#define SPTBR_MODE_SV32 1
+#define SPTBR_MODE_SV39 8
+#define SPTBR_MODE_SV48 9
+#define SPTBR_MODE_SV57 10
+#define SPTBR_MODE_SV64 11
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define IRQ_S_SOFT   1
+#define IRQ_H_SOFT   2
+#define IRQ_M_SOFT   3
+#define IRQ_S_TIMER  5
+#define IRQ_H_TIMER  6
+#define IRQ_M_TIMER  7
+#define IRQ_S_EXT    9
+#define IRQ_H_EXT    10
+#define IRQ_M_EXT    11
+#define IRQ_COP      12
+#define IRQ_HOST     13
+
+#define DEFAULT_RSTVEC     0x00001000
+#define CLINT_BASE         0x02000000
+#define CLINT_SIZE         0x000c0000
+#define EXT_IO_BASE        0x40000000
+#define DRAM_BASE          0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V     0x001 // Valid
+#define PTE_R     0x002 // Read
+#define PTE_W     0x004 // Write
+#define PTE_X     0x008 // Execute
+#define PTE_U     0x010 // User
+#define PTE_G     0x020 // Global
+#define PTE_A     0x040 // Accessed
+#define PTE_D     0x080 // Dirty
+#define PTE_SOFT  0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#if __riscv_xlen == 64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+# define SPTBR_MODE SPTBR64_MODE
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define SPTBR_MODE SPTBR32_MODE
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define write_csr(reg, val) ({ \
+  asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+  asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
+  __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+  asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+  asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes.  */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ  0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE  0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT  0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE  0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU  0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU  0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR  0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL  0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI  0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC  0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI  0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI  0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI  0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU  0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI  0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI  0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI  0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI  0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI  0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD  0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB  0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL  0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT  0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU  0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR  0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL  0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA  0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR  0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND  0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW  0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW  0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW  0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW  0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW  0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW  0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW  0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW  0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW  0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB  0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH  0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW  0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD  0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU  0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU  0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU  0x707f
+#define MATCH_SB 0x23
+#define MASK_SB  0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH  0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW  0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD  0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE  0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I  0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL  0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH  0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU  0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU  0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV  0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU  0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM  0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU  0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW  0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW  0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW  0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW  0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW  0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W  0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W  0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W  0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W  0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W  0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W  0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W  0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W  0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W  0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W  0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W  0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D  0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D  0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D  0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D  0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D  0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D  0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D  0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D  0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D  0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D  0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D  0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL  0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK  0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET  0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET  0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET  0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET  0xffffffff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA  0xfe007fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI  0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW  0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS  0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC  0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI  0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI  0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI  0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S  0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S  0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S  0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S  0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S  0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S  0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S  0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S  0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S  0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S  0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D  0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D  0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D  0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D  0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D  0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D  0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D  0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D  0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D  0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D  0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S  0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D  0xfff0007f
+#define MATCH_FADD_Q 0x6000053
+#define MASK_FADD_Q  0xfe00007f
+#define MATCH_FSUB_Q 0xe000053
+#define MASK_FSUB_Q  0xfe00007f
+#define MATCH_FMUL_Q 0x16000053
+#define MASK_FMUL_Q  0xfe00007f
+#define MATCH_FDIV_Q 0x1e000053
+#define MASK_FDIV_Q  0xfe00007f
+#define MATCH_FSGNJ_Q 0x26000053
+#define MASK_FSGNJ_Q  0xfe00707f
+#define MATCH_FSGNJN_Q 0x26001053
+#define MASK_FSGNJN_Q  0xfe00707f
+#define MATCH_FSGNJX_Q 0x26002053
+#define MASK_FSGNJX_Q  0xfe00707f
+#define MATCH_FMIN_Q 0x2e000053
+#define MASK_FMIN_Q  0xfe00707f
+#define MATCH_FMAX_Q 0x2e001053
+#define MASK_FMAX_Q  0xfe00707f
+#define MATCH_FCVT_S_Q 0x40300053
+#define MASK_FCVT_S_Q  0xfff0007f
+#define MATCH_FCVT_Q_S 0x46000053
+#define MASK_FCVT_Q_S  0xfff0007f
+#define MATCH_FCVT_D_Q 0x42300053
+#define MASK_FCVT_D_Q  0xfff0007f
+#define MATCH_FCVT_Q_D 0x46100053
+#define MASK_FCVT_Q_D  0xfff0007f
+#define MATCH_FSQRT_Q 0x5e000053
+#define MASK_FSQRT_Q  0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S  0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S  0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S  0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D  0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D  0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D  0xfe00707f
+#define MATCH_FLE_Q 0xa6000053
+#define MASK_FLE_Q  0xfe00707f
+#define MATCH_FLT_Q 0xa6001053
+#define MASK_FLT_Q  0xfe00707f
+#define MATCH_FEQ_Q 0xa6002053
+#define MASK_FEQ_Q  0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S  0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S  0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S  0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S  0xfff0007f
+#define MATCH_FMV_X_W 0xe0000053
+#define MASK_FMV_X_W  0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S  0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D  0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D  0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D  0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D  0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D  0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D  0xfff0707f
+#define MATCH_FCVT_W_Q 0xc6000053
+#define MASK_FCVT_W_Q  0xfff0007f
+#define MATCH_FCVT_WU_Q 0xc6100053
+#define MASK_FCVT_WU_Q  0xfff0007f
+#define MATCH_FCVT_L_Q 0xc6200053
+#define MASK_FCVT_L_Q  0xfff0007f
+#define MATCH_FCVT_LU_Q 0xc6300053
+#define MASK_FCVT_LU_Q  0xfff0007f
+#define MATCH_FMV_X_Q 0xe6000053
+#define MASK_FMV_X_Q  0xfff0707f
+#define MATCH_FCLASS_Q 0xe6001053
+#define MASK_FCLASS_Q  0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W  0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU  0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L  0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU  0xfff0007f
+#define MATCH_FMV_W_X 0xf0000053
+#define MASK_FMV_W_X  0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W  0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU  0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L  0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU  0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X  0xfff0707f
+#define MATCH_FCVT_Q_W 0xd6000053
+#define MASK_FCVT_Q_W  0xfff0007f
+#define MATCH_FCVT_Q_WU 0xd6100053
+#define MASK_FCVT_Q_WU  0xfff0007f
+#define MATCH_FCVT_Q_L 0xd6200053
+#define MASK_FCVT_Q_L  0xfff0007f
+#define MATCH_FCVT_Q_LU 0xd6300053
+#define MASK_FCVT_Q_LU  0xfff0007f
+#define MATCH_FMV_Q_X 0xf6000053
+#define MASK_FMV_Q_X  0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW  0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD  0x707f
+#define MATCH_FLQ 0x4007
+#define MASK_FLQ  0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW  0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD  0x707f
+#define MATCH_FSQ 0x4027
+#define MASK_FSQ  0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S  0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S  0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S  0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S  0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D  0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D  0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D  0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D  0x600007f
+#define MATCH_FMADD_Q 0x6000043
+#define MASK_FMADD_Q  0x600007f
+#define MATCH_FMSUB_Q 0x6000047
+#define MASK_FMSUB_Q  0x600007f
+#define MATCH_FNMSUB_Q 0x600004b
+#define MASK_FNMSUB_Q  0x600007f
+#define MATCH_FNMADD_Q 0x600004f
+#define MASK_FNMADD_Q  0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP  0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP  0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR  0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR  0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK  0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD  0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD  0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW  0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP  0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP  0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN  0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD  0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW  0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW  0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD  0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW  0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW  0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI  0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL  0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI  0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI  0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI  0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI  0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI  0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB  0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR  0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR  0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND  0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW  0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW  0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J  0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ  0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ  0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI  0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP  0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP  0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP  0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV  0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD  0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP  0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP  0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP  0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0  0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1  0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2  0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD  0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1  0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1  0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1  0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2  0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD  0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1  0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2  0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1  0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2  0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD  0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1  0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3  0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1  0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2  0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD  0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1  0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_PMPCFG0 0x3a0
+#define CSR_PMPCFG1 0x3a1
+#define CSR_PMPCFG2 0x3a2
+#define CSR_PMPCFG3 0x3a3
+#define CSR_PMPADDR0 0x3b0
+#define CSR_PMPADDR1 0x3b1
+#define CSR_PMPADDR2 0x3b2
+#define CSR_PMPADDR3 0x3b3
+#define CSR_PMPADDR4 0x3b4
+#define CSR_PMPADDR5 0x3b5
+#define CSR_PMPADDR6 0x3b6
+#define CSR_PMPADDR7 0x3b7
+#define CSR_PMPADDR8 0x3b8
+#define CSR_PMPADDR9 0x3b9
+#define CSR_PMPADDR10 0x3ba
+#define CSR_PMPADDR11 0x3bb
+#define CSR_PMPADDR12 0x3bc
+#define CSR_PMPADDR13 0x3bd
+#define CSR_PMPADDR14 0x3be
+#define CSR_PMPADDR15 0x3bf
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FETCH_ACCESS 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_STORE_ACCESS 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_STORE_PAGE_FAULT 0xf
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
+DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
+DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
+DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
+DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
+DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
+DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
+DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
+DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
+DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
+DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
+DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
+DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
+DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
+DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
+DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
+DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
+DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
+DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
+DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
+DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
+DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
+DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
+DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
+#endif
+
+#include "scr1_specific.h"
diff --git a/third_party/tests/Scr1/sim/tests/common/riscv_macros.h b/third_party/tests/Scr1/sim/tests/common/riscv_macros.h
new file mode 100644
index 0000000..9bf0724
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/riscv_macros.h
@@ -0,0 +1,819 @@
+// See LICENSE for license details.
+
+#ifndef __RISCV_MACROS_H
+#define __RISCV_MACROS_H
+
+#include "riscv_csr_encoding.h"
+#include "sc_test.h"
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U                                                    \
+  .macro init;                                                          \
+  .endm
+
+#define RVTEST_RV64UF                                                   \
+  .macro init;                                                          \
+  RVTEST_FP_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV32U                                                    \
+  .macro init;                                                          \
+  .endm
+
+#define RVTEST_RV32UF                                                   \
+  .macro init;                                                          \
+  RVTEST_FP_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV64M                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_MACHINE;                                                \
+  .endm
+
+#define RVTEST_RV64S                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_SUPERVISOR;                                             \
+  .endm
+
+#define RVTEST_RV32M                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_MACHINE;                                                \
+  .endm
+
+#define RVTEST_RV32S                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_SUPERVISOR;                                             \
+  .endm
+
+#if __riscv_xlen == 64
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
+#else
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
+#endif
+
+#define INIT_PMP                                                        \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  li t0, -1;        /* Set up a PMP to permit all accesses */           \
+  csrw pmpaddr0, t0;                                                    \
+  li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X;                             \
+  csrw pmpcfg0, t0;                                                     \
+  .align 2;                                                             \
+1:
+
+#define INIT_SPTBR                                                      \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  csrwi sptbr, 0;                                                       \
+  .align 2;                                                             \
+1:
+
+#define DELEGATE_NO_TRAPS
+
+#define RVTEST_ENABLE_SUPERVISOR                                        \
+  li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1);                              \
+  csrs mstatus, a0;                                                     \
+  li a0, SIP_SSIP | SIP_STIP;                                           \
+  csrs mideleg, a0;                                                     \
+
+#define RVTEST_ENABLE_MACHINE                                           \
+  li a0, MSTATUS_MPP;                                                   \
+  csrs mstatus, a0;                                                     \
+
+#define RVTEST_FP_ENABLE                                                \
+  li a0, MSTATUS_FS & (MSTATUS_FS >> 1);                                \
+  csrs mstatus, a0;                                                     \
+  csrwi fcsr, 0
+
+#define RISCV_MULTICORE_DISABLE                                         \
+  csrr a0, mhartid;                                                     \
+  1: bnez a0, 1b
+
+#define EXTRA_TVEC_USER
+#define EXTRA_TVEC_SUPERVISOR
+#define EXTRA_TVEC_HYPERVISOR
+#define EXTRA_TVEC_MACHINE
+#define EXTRA_INIT
+#define EXTRA_INIT_TIMER
+
+#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
+
+#define RVTEST_CODE_BEGIN                                               \
+        .section .text.init;                                            \
+        .org 0xC0, 0x00;                                                \
+        .align  6;                                                      \
+        .weak stvec_handler;                                            \
+        .weak mtvec_handler;                                            \
+trap_vector:                                                            \
+        /* test whether the test came from pass/fail */                 \
+        csrr a4, mcause;                                                \
+        li a5, CAUSE_USER_ECALL;                                        \
+        beq a4, a5, _report;                                            \
+        li a5, CAUSE_SUPERVISOR_ECALL;                                  \
+        beq a4, a5, _report;                                            \
+        li a5, CAUSE_MACHINE_ECALL;                                     \
+        beq a4, a5, _report;                                            \
+        /* if an mtvec_handler is defined, jump to it */                \
+        la a4, mtvec_handler;                                           \
+        beqz a4, 1f;                                                    \
+        jr a4;                                                          \
+        /* was it an interrupt or an exception? */                      \
+1:      csrr a4, mcause;                                                \
+        bgez a4, handle_exception;                                      \
+        INTERRUPT_HANDLER;                                              \
+handle_exception:                                                       \
+        /* we don't know how to handle whatever the exception was */    \
+other_exception:                                                        \
+        /* some unhandlable exception occurred */                       \
+        li   a0, 0x1;                                                   \
+_report:                                                                \
+        j sc_exit;                                                      \
+        .align  6;                                                      \
+        .globl _start;                                                  \
+_start:                                                                 \
+        RISCV_MULTICORE_DISABLE;                                        \
+        /*INIT_SPTBR;*/                                                 \
+        /*INIT_PMP;*/                                                   \
+        DELEGATE_NO_TRAPS;                                              \
+        li TESTNUM, 0;                                                  \
+        la t0, trap_vector;                                             \
+        csrw mtvec, t0;                                                 \
+        CHECK_XLEN;                                                     \
+        /* if an stvec_handler is defined, delegate exceptions to it */ \
+        la t0, stvec_handler;                                           \
+        beqz t0, 1f;                                                    \
+        csrw stvec, t0;                                                 \
+        li t0, (1 << CAUSE_LOAD_PAGE_FAULT) |                           \
+               (1 << CAUSE_STORE_PAGE_FAULT) |                          \
+               (1 << CAUSE_FETCH_PAGE_FAULT) |                          \
+               (1 << CAUSE_MISALIGNED_FETCH) |                          \
+               (1 << CAUSE_USER_ECALL) |                                \
+               (1 << CAUSE_BREAKPOINT);                                 \
+        csrw medeleg, t0;                                               \
+        csrr t1, medeleg;                                               \
+        bne t0, t1, other_exception;                                    \
+1:      csrwi mstatus, 0;                                               \
+        init;                                                           \
+        EXTRA_INIT;                                                     \
+        EXTRA_INIT_TIMER;                                               \
+        la t0, _run_test;                                               \
+        csrw mepc, t0;                                                  \
+        csrr a0, mhartid;                                               \
+        mret;                                                           \
+        .section .text;                                                 \
+_run_test:
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END ecall: ecall
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS                                                     \
+        fence;                                                          \
+        mv a1, TESTNUM;                                                 \
+        li  a0, 0x0;                                                    \
+        ecall
+
+#define TESTNUM x28
+#define RVTEST_FAIL                                                     \
+        fence;                                                          \
+        mv a1, TESTNUM;                                                 \
+        li  a0, 0x1;                                                    \
+        ecall
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define EXTRA_DATA
+
+#define RVTEST_DATA_BEGIN                                                       \
+        EXTRA_DATA                                                              \
+        .pushsection .tohost,"aw",@progbits;                                    \
+        .align 6; .global tohost; tohost: .dword 0;                             \
+        .align 6; .global fromhost; fromhost: .dword 0;                         \
+        .popsection;                                                            \
+        .align 4;                                                               \
+        .global begin_regstate;  begin_regstate: .dword 0; .dword 0; .dword 0;  \
+        .align 4;                                                               \
+        .global begin_signature; begin_signature:
+
+#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    li  x29, MASK_XLEN(correctval); \
+    li  TESTNUM, testnum; \
+    bne testreg, x29, fail;
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x3, x1, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_OP_RVC( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, imm; \
+    )
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x1, x1, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      inst x3, x1, SEXT_IMM(imm); \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      inst x3, x1, SEXT_IMM(imm); \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+    TEST_CASE( testnum, x0, 0, \
+      li  x1, MASK_XLEN(val1); \
+      inst x0, x1, SEXT_IMM(imm); \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for vector config instructions
+#-----------------------------------------------------------------------
+
+#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE( testnum, x1, result, \
+      li x1, (bank << 12); \
+      vsetcfg x1,nxpr,nfpr; \
+      li x1, vl; \
+      vsetvl x1,x1; \
+    )
+
+#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE( testnum, x1, result, \
+      li x1, (bank << 12) | (nfpr << 6) | nxpr; \
+      vsetcfg x1; \
+      li x1, vl; \
+      vsetvl x1,x1; \
+    )
+
+#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE( testnum, x1, result, \
+      li x1, (bank << 12); \
+      vsetcfg x1,nxpr,nfpr; \
+      li x1, vl; \
+      vsetvl x1, x1; \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, val1; \
+      inst x3, x1; \
+    )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1; \
+    )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      inst x3, x1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x3, x1, x2; \
+    )
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x1, x1, x2; \
+    )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x2, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x2, x1, x2; \
+    )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x1, x1, x1; \
+    )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x3, x1, x2; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x2, MASK_XLEN(val2); \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x3, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x2, MASK_XLEN(val2); \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x3, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, MASK_XLEN(val); \
+      inst x2, x0, x1; \
+    )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, MASK_XLEN(val); \
+      inst x2, x1, x0; \
+    )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+    TEST_CASE( testnum, x0, 0, \
+      li x1, MASK_XLEN(val1); \
+      li x2, MASK_XLEN(val2); \
+      inst x0, x1, x2; \
+    )
+
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+
+#define TEST_LD_OP( testnum, inst, result, offset, base ) \
+    TEST_CASE( testnum, x3, result, \
+      la  x1, base; \
+      inst x3, offset(x1); \
+    )
+
+#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
+    TEST_CASE( testnum, x3, result, \
+      la  x1, base; \
+      li  x2, result; \
+      store_inst x2, offset(x1); \
+      load_inst x3, offset(x1); \
+    )
+
+#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x1, base; \
+    inst x3, offset(x1); \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    addi  x6, x3, 0; \
+    li  x29, result; \
+    bne x6, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b; \
+
+#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x1, base; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x3, offset(x1); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x1, result; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    la  x2, base; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x3, offset(x2); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x2, base; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, result; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x3, offset(x2); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test branch instructions
+#-----------------------------------------------------------------------
+
+#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    inst x1, 2f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
+2:  inst x1, 1b; \
+    bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    inst x1, 1f; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
+2:  inst x1, 1b; \
+3:
+
+#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x1, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 2f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
+2:  inst x1, x2, 1b; \
+    bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 1f; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
+2:  inst x1, x2, 1b; \
+3:
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+
+#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x6; \
+    bne x0, TESTNUM, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x19, x6, 0; \
+    bne x0, TESTNUM, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+#define qNaNf 0f:7fc00000
+#define sNaNf 0f:7f800001
+#define qNaN 0d:7ff8000000000000
+#define sNaN 0d:7ff0000000000001
+
+#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  flw f0, 0(a0); \
+  flw f1, 4(a0); \
+  flw f2, 8(a0); \
+  lw  a3, 12(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  j 2f; \
+  .align 2; \
+  .data; \
+  test_ ## testnum ## _data: \
+  .float val1; \
+  .float val2; \
+  .float val3; \
+  .result; \
+  .text; \
+2:
+
+#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  fld f0, 0(a0); \
+  fld f1, 8(a0); \
+  fld f2, 16(a0); \
+  ld  a3, 24(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  j 2f; \
+  .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+  .text; \
+2:
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
+                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.s a0, f3)
+
+#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.d a0, f3)
+
+#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.s a0, f3)
+
+#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.d a0, f3)
+
+#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_FCLASS_S(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
+                    fclass.s a0, fa0)
+
+#define TEST_FCLASS_D(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
+                    fclass.d a0, fa0)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  lw  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.s a0, f0; \
+  bne a0, a3, fail; \
+  j 1f; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float result; \
+1:
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  ld  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.d a0, f0; \
+  bne a0, a3, fail; \
+  j 1f; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+1:
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in TESTNUM)
+#-----------------------------------------------------------------------
+
+#define TEST_PASSFAIL \
+        bne x0, TESTNUM, pass; \
+fail: \
+        RVTEST_FAIL; \
+pass: \
+        RVTEST_PASS \
+
+
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+
+#define TEST_DATA
+
+#endif
+
diff --git a/third_party/tests/Scr1/sim/tests/common/sc_print.c b/third_party/tests/Scr1/sim/tests/common/sc_print.c
new file mode 100644
index 0000000..3af9d23
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/sc_print.c
@@ -0,0 +1,282 @@
+/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+/// @file       <sc_print.c>
+///
+
+#include <string.h>
+#include <stdarg.h>
+#include "sc_print.h"
+
+#define SC_SIM_OUTPORT (0xf0000000)
+#define CHAR_BIT (8)
+
+static void
+sc_puts(long str, long strlen) {
+	volatile char *out_ptr = (volatile char*)SC_SIM_OUTPORT;
+	const char *in_ptr = (const char*)str;
+	for (long len = strlen; len > 0; --len)
+	  *out_ptr = *in_ptr++;
+}
+
+#undef putchar
+int
+putchar(int ch) {
+	static __thread char buf[64] __attribute__((aligned(64)));
+    static __thread int buflen = 0;
+
+    buf[buflen++] = ch;
+
+	if ( ch == '\n' || buflen == sizeof(buf) ) {
+        sc_puts((long)buf, buflen);
+        buflen = 0;
+    }
+
+    return 0;
+}
+
+static void
+printf_putch(int ch, void** data)
+{
+    putchar(ch);
+}
+
+static void
+print(const char *str)
+{
+  sc_puts((long)str, strlen(str));
+}
+
+
+static long long
+getint(va_list *ap, int lflag)
+{
+    if ( lflag >= 2 )
+        return va_arg(*ap, long long);
+    else if ( lflag )
+        return va_arg(*ap, long);
+    else
+        return va_arg(*ap, int);
+}
+
+
+static unsigned long long
+getuint(va_list *ap, int lflag)
+{
+    if ( lflag >= 2 )
+        return va_arg(*ap, unsigned long long);
+    else if ( lflag )
+        return va_arg(*ap, unsigned long);
+    else
+        return va_arg(*ap, unsigned int);
+}
+
+static inline void
+printnum(void(*putch)(int, void**),
+void **putdat,
+unsigned long long num,
+unsigned base,
+int width,
+int padc,
+int hex_A)
+{
+    unsigned digs[sizeof(num) * CHAR_BIT];
+    int pos = 0;
+
+    for ( ;; ) {
+        digs[pos++] = num % base;
+        if ( num < base )
+            break;
+        num /= base;
+    }
+
+    while ( width-- > pos )
+        putch(padc, putdat);
+
+    while ( pos-- > 0 )
+        putch(digs[pos] + (digs[pos] >= 10 ? hex_A - 10 : '0'), putdat);
+}
+
+static void
+vprintfmt(void(*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
+{
+    register const char* p;
+    const char* last_fmt;
+    register int ch;
+    int err;
+    unsigned long long num;
+    int base;
+    int lflag;
+    int width;
+    int precision;
+    int altflag;
+    char padc;
+    int hex_A = 'a';
+    for ( ;; ) {
+        while ( (ch = *(unsigned char *)fmt) != '%' ) {
+            if ( ch == '\0' )
+                return;
+            ++fmt;
+            putch(ch, putdat);
+        }
+        ++fmt;
+
+        // Process a %-escape sequence
+        last_fmt = fmt;
+        padc = ' ';
+        width = -1;
+        precision = -1;
+        lflag = 0;
+        altflag = 0;
+
+reswitch:
+        switch ( ch = *(unsigned char *)fmt++ ) {
+            // flag to pad on the right
+            case '-':
+                padc = '-';
+                goto reswitch;
+
+                // flag to pad with 0's instead of spaces
+            case '0':
+                padc = '0';
+                goto reswitch;
+
+                // width field
+            case '1':
+            case '2':
+            case '3':
+            case '4':
+            case '5':
+            case '6':
+            case '7':
+            case '8':
+            case '9':
+                for ( precision = 0;; ++fmt ) {
+                    precision = precision * 10 + ch - '0';
+                    ch = *fmt;
+                    if ( ch < '0' || ch > '9' )
+                        break;
+                }
+                goto process_precision;
+
+            case '*':
+                precision = va_arg(ap, int);
+                goto process_precision;
+
+            case '.':
+                if ( width < 0 )
+                    width = 0;
+                goto reswitch;
+
+            case '#':
+                altflag = 1;
+                goto reswitch;
+
+process_precision:
+                if ( width < 0 ) {
+                    width = precision;
+                    precision = -1;
+                }
+                goto reswitch;
+
+                // long flag (doubled for long long)
+            case 'l':
+                lflag++;
+                goto reswitch;
+
+                // character
+            case 'c':
+                putch(va_arg(ap, int), putdat);
+                break;
+
+                // string
+            case 's':
+                if ( (p = va_arg(ap, char *)) == NULL )
+                    p = "(null)";
+                if ( width > 0 && padc != '-' )
+                    for ( width -= strnlen(p, precision); width > 0; width-- )
+                        putch(padc, putdat);
+                for ( ; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width-- ) {
+                    putch(ch, putdat);
+                    p++;
+                }
+                for ( ; width > 0; width-- )
+                    putch(' ', putdat);
+                break;
+
+                // (signed) decimal
+            case 'd':
+                num = getint(&ap, lflag);
+                if ( (long long)num < 0 ) {
+                    putch('-', putdat);
+                    num = -(long long)num;
+                }
+                base = 10;
+                goto signed_number;
+
+            case 'f':
+                {
+                    // #ifndef nopfloat
+                    // double num = getdouble(&ap, lflag);
+                    // printdoubleF(putch, putdat, num, width, precision, padc);
+                    // #endif
+                }
+                break;
+
+                // unsigned decimal
+            case 'u':
+                base = 10;
+                goto unsigned_number;
+
+                // (unsigned) octal
+            case 'o':
+                // should do something with padding so it's always 3 octits
+                base = 8;
+                goto unsigned_number;
+
+                // pointer
+            case 'p':
+                // static_assert(sizeof(long) == sizeof(void*));
+                lflag = 1;
+                putch('0', putdat);
+                putch('x', putdat);
+                /* fall through to 'x' */
+
+                // (unsigned) hexadecimal
+            case 'x':
+                hex_A = 'a';
+                base = 16;
+                goto unsigned_number;
+
+            case 'X':
+                hex_A = 'A';
+                base = 16;
+unsigned_number:
+                num = getuint(&ap, lflag);
+signed_number:
+                printnum(putch, putdat, num, base, width, padc, hex_A);
+                break;
+
+                // escaped '%' character
+            case '%':
+                putch(ch, putdat);
+                break;
+
+                // unrecognized escape sequence - just print it literally
+            default:
+                putch('%', putdat);
+                fmt = last_fmt;
+                break;
+        }
+    }
+}
+
+int
+sc_printf(const char* fmt, ...)
+{
+    va_list ap;
+    va_start(ap, fmt);
+
+    vprintfmt(printf_putch, NULL, fmt, ap);
+
+    va_end(ap);
+    return 0; // incorrect return value, but who cares, anyway?
+}
diff --git a/third_party/tests/Scr1/sim/tests/common/sc_print.h b/third_party/tests/Scr1/sim/tests/common/sc_print.h
new file mode 100644
index 0000000..f175417
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/sc_print.h
@@ -0,0 +1,10 @@
+/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+/// @file       <sc_print.h>
+///
+
+#ifndef SC_PRINT_H
+#define SC_PRINT_H
+
+extern int sc_printf(const char* fmt, ...);
+
+#endif // SC_PRINT_H
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/common/sc_test.h b/third_party/tests/Scr1/sim/tests/common/sc_test.h
new file mode 100644
index 0000000..f4ef679
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/sc_test.h
@@ -0,0 +1,35 @@
+/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
+/// @file       <sc_test.h>
+///
+
+#ifndef SC_TEST_H
+#define SC_TEST_H
+
+#ifdef ASM
+
+#define report_results(result) \
+li  a0, result;  \
+la t0, sc_exit;  \
+jr	 t0;
+
+.pushsection sc_test_section, "ax"
+sc_exit: j SIM_EXIT;
+.align 5
+.popsection
+#define sc_pass report_results(0x0)
+#define sc_fail report_results(0x1)
+
+#else
+
+extern void sc_exit(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3)
+    __attribute__ ((noinline, noreturn));
+
+static inline void  __attribute__ ((noreturn))
+report_results(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3)
+{
+    sc_exit(result, res0, res1, res2, res3);
+}
+
+#endif
+
+#endif // SC_TEST_H
diff --git a/third_party/tests/Scr1/sim/tests/common/scr1_specific.h b/third_party/tests/Scr1/sim/tests/common/scr1_specific.h
new file mode 100644
index 0000000..f965880
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/common/scr1_specific.h
@@ -0,0 +1,20 @@
+#ifndef __SCR1__SPECIFIC
+#define __SCR1__SPECIFIC
+
+#define mcounten        0x7E0
+
+// Memory-mapped registers
+#define mtime_ctrl      0x00490000
+#define mtime_div       0x00490004
+#define mtime           0x00490008
+#define mtimeh          0x0049000C
+#define mtimecmp        0x00490010
+#define mtimecmph       0x00490014
+
+#define SCR1_MTIME_CTRL_EN          0
+#define SCR1_MTIME_CTRL_CLKSRC      1
+
+#define SCR1_MTIME_CTRL_WR_MASK     0x3
+#define SCR1_MTIME_DIV_WR_MASK      0x3FF
+
+#endif // _SCR1__SPECIFIC
diff --git a/third_party/tests/Scr1/sim/tests/hello/Makefile b/third_party/tests/Scr1/sim/tests/hello/Makefile
new file mode 100644
index 0000000..577fed2
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/hello/Makefile
@@ -0,0 +1,10 @@
+src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+
+c_src := sc_print.c hello.c
+
+include $(inc_dir)/common.mk
+
+default: $(bld_dir)/hello.elf $(bld_dir)/hello.hex $(bld_dir)/hello.dump
+
+clean:
+	$(RM) $(c_objs) $(asm_objs) $(bld_dir)/hello.elf $(bld_dir)/hello.hex $(bld_dir)/hello.dump
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/hello/hello.c b/third_party/tests/Scr1/sim/tests/hello/hello.c
new file mode 100644
index 0000000..52cf1bc
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/hello/hello.c
@@ -0,0 +1,7 @@
+#include "sc_print.h"
+
+int main()
+{
+    sc_printf("Hello from SCR1!\n");
+    return 0;
+}
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/riscv_compliance/Makefile b/third_party/tests/Scr1/sim/tests/riscv_compliance/Makefile
new file mode 100644
index 0000000..f585082
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_compliance/Makefile
@@ -0,0 +1,205 @@
+## @file
+## Syntacore SCR* tests
+##
+## @copyright 2015-2018 Syntacore. All rights reserved.
+## RISCV-Compliance
+##
+
+ARCH ?=im
+override ARCH:=rv32$(ARCH)
+
+#I IM IMC IC 
+#EM EMC EC
+
+ifeq (rv32e,$(findstring rv32e,$(ARCH)))
+    $(info >>> RV32E - no compliance tests)
+else ## ifdef SCR_BASE_RVE_EXT
+  #ifeq (rv32i,$(findstring rv32i,$(ARCH)))
+  ifeq ($(ARCH),$(filter $(ARCH),rv32i rv32im rv32imc rv32ic))
+    $(info >>> I32 TESTS)
+    included_i += $(filter %.S,\
+                        $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32i/src/*))
+    $(info >>> UI32 TESTS)
+    included_i += $(filter %.S,\
+                        $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32ui/src/*))
+    $(info >>> M32 TESTS)
+    included_i += $(filter %.S,\
+                        $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32mi/src/*))
+    compliance_set += $(included_i)
+  endif
+
+  #$(if or ifeq(rv32im,$(findstring rv32im,$(ARCH))), (rv32imc,$(findstring rv32imc,$(ARCH))))
+  ifeq ($(ARCH),$(filter $(ARCH), rv32im rv32imc))
+    $(info >>> IM32 TESTS)
+    included_im += $(filter %.S,\
+                        $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32im/src/*))
+    compliance_set += $(included_im)
+  endif ## 
+
+  #ifeq $(or (rv32imc,$(findstring rv32imc,$(ARCH))), (rv32ic,$(findstring rv32ic,$(ARCH))))
+  ifeq ($(ARCH),$(filter $(ARCH), rv32ic rv32imc))
+    $(info >>> UC32 TESTS)
+    included_ic += $(filter %.S,\
+                        $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32uc/src/*))
+    compliance_set += $(included_ic)
+  endif ## ifdef 
+
+  ifeq (rv32imc,$(findstring rv32imc,$(ARCH)))
+    $(info >>> IMC32 TESTS)
+    included_imc += $(filter %.S,\
+                        $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32imc/src/*))
+    compliance_set += $(included_imc)
+  endif ## ifeq (rv32imc,$(findstring rv32imc,$(ARCH)))
+
+endif ## 
+
+
+$(info >>>$(ARCH) set included)
+
+ifeq ($(compliance_set),)
+$(info >>> No compliance tests included)
+endif
+
+$(info >>>>> compliance set: $(compliance_set))
+
+dst_dir       := $(bld_dir)
+test_name     := riscv_compliance
+bld_dir       := $(addprefix $(dst_dir)/, $(test_name))
+src_dir       := $(CURDIR)
+obj_dir       := $(bld_dir)/riscv_compliance_objs
+cut_list      := I-EBREAK-01 I-ECALL-01 I-MISALIGN_JMP-01 I-MISALIGN_LDST-01
+cut_list      += scall csr shamt simple
+reference_src := $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/*/*/*.reference_output)
+testnames     := $(basename $(notdir $(compliance_set)))
+filtered      := $(filter-out $(cut_list),$(testnames))
+objs          := $(addprefix $(bld_dir)/,$(filtered:%=%.o))
+test_elf      := $(addprefix $(dst_dir)/compliance_,$(filtered:%=%.elf))
+test_hex      := $(addprefix $(dst_dir)/compliance_,$(filtered:%=%.hex))
+test_dump     := $(addprefix $(bld_dir)/compliance_,$(filtered:%=%.dump))
+
+compliance_macros_file := $(root_dir)/sim/tests/riscv_compliance/compliance_io.h
+compliance_output ?= true
+
+testnames_i     := $(basename $(notdir $(included_i)))
+testnames_im     := $(basename $(notdir $(included_im)))
+testnames_ic     := $(basename $(notdir $(included_ic)))
+testnames_imc     := $(basename $(notdir $(included_imc)))
+filtered_i      := $(filter-out $(cut_list),$(testnames_i))
+filtered_im      := $(filter-out $(cut_list),$(testnames_im))
+filtered_ic      := $(filter-out $(cut_list),$(testnames_ic))
+filtered_imc      := $(filter-out $(cut_list),$(testnames_imc))
+
+# ARCH_FLAGS := -Wa,-march=rv32im -march=rv32im 
+# ARCH_FLAGS_C := -Wa,-march=rv32imc -march=rv32imc
+CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -mabi=ilp32 -D__riscv_xlen=32 -w
+LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=$(ARCH) -mabi=ilp32
+VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(asm_path) $(ref_path) $(RISCV_COMPLIANCE_TESTS)
+
+ifeq ($(compliance_output), true)
+CFLAGS += -D_COMPLIANCE_OUTPUT
+endif
+
+default: clean check_version cp_asm ref_data $(test_elf) $(test_hex) $(test_dump)
+
+define compile_template
+$(obj_dir)/$(1).o: $(obj_dir) cp_asm
+	$(RISCV_GCC) -c $$(bld_dir)/compliance_asm/$(1).S $$(CFLAGS) -Wa,$(2) $(2) -o $$@
+endef
+
+define preprocessing
+for test_asm in $(1); do                                                  \
+march_tmp=$$test_asm ;                                                    \
+march_tmp=$${march_tmp%/src*} ;                                           \
+march_tmp=$$(basename $$march_tmp) ;                                      \
+file_name="$$(basename $${test_asm})" ;                                   \
+$(RISCV_GCC) $(CFLAGS) -Wa,$(2) $(2) -E $$test_asm                        \
+-o $(bld_dir)/compliance_asm/$$file_name ;                                \
+done
+endef
+
+$(foreach SRC,$(filtered_i),$(eval $(call compile_template,$(SRC),-march=rv32i)))
+$(foreach SRC,$(filtered_im),$(eval $(call compile_template,$(SRC),-march=rv32im)))
+$(foreach SRC,$(filtered_ic),$(eval $(call compile_template,$(SRC),-march=rv32iac)))
+$(foreach SRC,$(filtered_imc),$(eval $(call compile_template,$(SRC),-march=rv32imac)))
+
+$(bld_dir) :
+	mkdir -p $(bld_dir)
+
+$(obj_dir) : | ref_data
+	mkdir -p $(obj_dir)
+
+$(dst_dir)/compliance_%.elf: $(obj_dir)/%.o | $(dep_files)
+	$(RISCV_GCC) $^ $(LDFLAGS) -o $@ -g
+
+$(dst_dir)/compliance_%.hex: $(dst_dir)/compliance_%.elf
+	$(RISCV_OBJCOPY) $^ $@
+
+$(bld_dir)/compliance_%.dump: $(dst_dir)/compliance_%.elf
+	$(RISCV_OBJDUMP) -D -w -x -S $^ > $@
+
+ref_data:
+	mkdir -p $(bld_dir)/ref_data
+	for files in $(reference_src) ; do \
+	sed_input=$$files ; \
+	sed_output=$$(basename $${files%.*}) ; \
+	sed "s/\r$$//; \
+	s/\(........\)/\1,/g; \
+	s/.$$//; s/\(.*\),\(.*\),\(.*\),\(.*\)/\4,\3,\2,\1/; \
+	s/\(.........\)/\10x/g; s/^/0x/; s/$$/,/; $$ s/.$$//" $$sed_input > $(bld_dir)/ref_data/$$sed_output; \
+	done
+
+cp_asm:
+	mkdir -p $(bld_dir)/compliance_asm
+	$(call preprocessing,$(included_i),-march=rv32i)
+	$(call preprocessing,$(included_im),-march=rv32im)
+	$(call preprocessing,$(included_ic),-march=rv32iac)
+	$(call preprocessing,$(included_imc),-march=rv32imac)
+
+
+riscv_compliance_tests_dir    := $(if $(RISCV_COMPLIANCE_TESTS), $(RISCV_COMPLIANCE_TESTS), ./undefined)
+riscv_tests_commit := 9f280717f26f50833357db9bfb77a8c79835f162
+## commit hash readed from local copy of https://github.com/riscv/riscv-compliance
+tmp_commit = $(shell cd $(riscv_compliance_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ')
+is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true)
+
+# Color
+RED=\033[0;31m
+NC=\033[0m
+
+check_version : $(riscv_compliance_tests_dir)
+	@if [ ! -d $(riscv_compliance_tests_dir) ]; then \
+		echo -e "$(RED)==========================================================================" &&\
+		echo "   Error! Environment variable RISCV_COMPLIANCE_TESTS='$(riscv_compliance_tests_dir)' " &&\
+		echo "      directory not exist!" && \
+		echo "==========================================================================$(NC)" ; \
+	fi
+ifneq (,$(is_repo_changed))
+	@echo -e "$(RED)=========================================================================="
+	@echo "   Error! Repo '$(riscv_compliance_tests_dir)' "
+	@echo "     must be unchanged!"
+	@echo -e "==========================================================================$(NC)"
+	exit 1
+endif
+ifneq ($(is_commit_good),true)
+	@echo -e "$(RED)=========================================================================="
+	@echo "   Error! riscv compliance tests must point to commit $(riscv_tests_commit)"
+	@echo -e "==========================================================================$(NC)"
+	exit 1
+endif
+
+$(riscv_compliance_tests_dir) :.
+ifndef RISCV_COMPLIANCE_TESTS
+	@echo -e "$(RED)=========================================================================="
+	@echo "    Error! Environment variable RISCV_COMPLIANCE_TESTS not set!"
+	@echo "    You must set the environment variable RISCV_COMPLIANCE_TESTS"
+	@echo "    The variable should point to the local copy of the"
+	@echo "      repository https://github.com/riscv/riscv-compliance"
+	@echo "      with the commit $(riscv_tests_commit)"
+	@echo -e "==========================================================================$(NC)"
+	exit 1
+endif
+
+clean:
+	$(RM) -R $(test_elf) $(test_hex) $(bld_dir)
+
+.PHONY: check_version clean ref_data cp_asm default
diff --git a/third_party/tests/Scr1/sim/tests/riscv_compliance/aw_test_macros.h b/third_party/tests/Scr1/sim/tests/riscv_compliance/aw_test_macros.h
new file mode 100644
index 0000000..3e052a1
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_compliance/aw_test_macros.h
@@ -0,0 +1,683 @@
+/*
+  COPY OF /riscv-compliance/riscv-test-env/aw_test_macros.h
+  */
+
+// See LICENSE for license details.
+
+#ifndef __TEST_MACROS_SCALAR_H
+#define __TEST_MACROS_SCALAR_H
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: srli a0, a0, 31; la t0, begin_signature; sw a0, 0(t0)
+
+#define TESTNUM gp
+
+#define SWSIG( testnum, testreg ) \
+    la  x28, test_res; \
+    sw testreg, (testnum<<2)(x28); \
+
+#
+# Address = base+(testnum<<2)
+# sw testreg, (testnum<<2)(basereg)
+#
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    li  x29, MASK_XLEN(correctval); \
+    li  TESTNUM, testnum; \
+        SWSIG(testnum,testreg); \
+    bne testreg, x29, fail;
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x30, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x30, x1, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x1, x1, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      inst x30, x1, SEXT_IMM(imm); \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x30, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x30, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      inst x30, x1, SEXT_IMM(imm); \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+    TEST_CASE( testnum, x0, 0, \
+      li  x1, MASK_XLEN(val1); \
+      inst x0, x1, SEXT_IMM(imm); \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x30, result, \
+      li  x1, val1; \
+      inst x30, x1; \
+    )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1; \
+    )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      inst x30, x1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x30, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x30, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x30, x1, x2; \
+    )
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x1, x1, x2; \
+    )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x2, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x2, x1, x2; \
+    )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x1, x1, x1; \
+    )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x30, x1, x2; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x30, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x30, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x2, MASK_XLEN(val2); \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x30, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x30, result, \
+      li  x4, 0; \
+1:    li  x2, MASK_XLEN(val2); \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x30, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, MASK_XLEN(val); \
+      inst x2, x0, x1; \
+    )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, MASK_XLEN(val); \
+      inst x2, x1, x0; \
+    )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+    TEST_CASE( testnum, x0, 0, \
+      li x1, MASK_XLEN(val1); \
+      li x2, MASK_XLEN(val2); \
+      inst x0, x1, x2; \
+    )
+
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+
+#define TEST_LD_OP( testnum, inst, result, offset, base ) \
+    TEST_CASE( testnum, x30, result, \
+      la  x1, base; \
+      inst x30, offset(x1); \
+    )
+
+#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
+    TEST_CASE( testnum, x30, result, \
+      la  x1, base; \
+      li  x2, result; \
+      store_inst x2, offset(x1); \
+      load_inst x30, offset(x1); \
+    )
+
+#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x4, 0; \
+1:  la  x1, base; \
+    inst x30, offset(x1); \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    addi  x6, x30, 0; \
+    li  x29, result; \
+    bne x6, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b; \
+
+#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x4, 0; \
+1:  la  x1, base; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x30, offset(x1); \
+    li  x29, result; \
+    bne x30, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x4, 0; \
+1:  li  x1, result; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    la  x2, base; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x30, offset(x2); \
+    li  x29, result; \
+    bne x30, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x4, 0; \
+1:  la  x2, base; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, result; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x30, offset(x2); \
+    li  x29, result; \
+    bne x30, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 2f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
+2:  inst x1, x2, 1b; \
+    bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 1f; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
+2:  inst x1, x2, 1b; \
+3:
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x4, 0; \
+1:  li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+
+#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x6; \
+    bne x0, TESTNUM, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x19, x6, 0; \
+    bne x0, TESTNUM, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+#define qNaNf 0f:7fc00000
+#define sNaNf 0f:7f800001
+#define qNaN 0d:7ff8000000000000
+#define sNaN 0d:7ff0000000000001
+
+#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+  la  a0, test_ ## testnum ## _data ;\
+  flw f0, 0(a0); \
+  flw f1, 4(a0); \
+  flw f2, 8(a0); \
+  lw  a3, 12(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  .pushsection .data; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float val1; \
+  .float val2; \
+  .float val3; \
+  .result; \
+  .popsection
+
+#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+  la  a0, test_ ## testnum ## _data ;\
+  fld f0, 0(a0); \
+  fld f1, 8(a0); \
+  fld f2, 16(a0); \
+  ld  a3, 24(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+  .popsection
+
+// TODO: assign a separate mem location for the comparison address?
+#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+  la  a0, test_ ## testnum ## _data ;\
+  fld f0, 0(a0); \
+  fld f1, 8(a0); \
+  fld f2, 16(a0); \
+  lw  a3, 24(a0); \
+  lw  t1, 28(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne t1, t2, fail; \
+  bne a1, a2, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+  .popsection
+
+#define TEST_FCVT_S_D32( testnum, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
+                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+                    inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.s a0, f3)
+
+#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.d a0, f3)
+
+#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.s a0, f3)
+
+#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.d a0, f3)
+
+#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst a0, f0, f1; li t2, 0)
+
+#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+                    inst a0, f0, f1; li t2, 0)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_FCLASS_S(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
+                    fclass.s a0, fa0)
+
+#define TEST_FCLASS_D32(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, \
+            la a0, test_ ## testnum ## _data ;\
+            fld fa0, 0(a0); \
+            fclass.d a0, fa0) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## testnum ## _data: \
+    .dword input; \
+    .popsection
+
+#define TEST_FCLASS_D(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
+                    fclass.d a0, fa0)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+  la  a0, test_ ## testnum ## _data ;\
+  lw  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.s a0, f0; \
+  bne a0, a3, fail; \
+  .pushsection .data; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float result; \
+  .popsection
+
+#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+  la  a0, test_ ## testnum ## _data ;\
+  lw  a3, 0(a0); \
+  lw  a4, 4(a0); \
+  li  a1, val1; \
+  inst f0, a1; \
+  \
+  fsd f0, 0(a0); \
+  lw a1, 4(a0); \
+  lw a0, 0(a0); \
+  \
+  fsflags x0; \
+  bne a0, a3, fail; \
+  bne a1, a4, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+  .popsection
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  SWSIG (testnum, TESTNUM);\
+  la  a0, test_ ## testnum ## _data ;\
+  ld  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.d a0, f0; \
+  bne a0, a3, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+  .popsection
+
+// We need some special handling here to allow 64-bit comparison in 32-bit arch
+// TODO: find a better name and clean up when intended for general usage?
+#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    la  x31, test_ ## testnum ## _data ; \
+    lw  x29, 0(x31); \
+    lw  x31, 4(x31); \
+    li  TESTNUM, testnum; \
+    SWSIG (testnum, TESTNUM);\
+    bne testreg1, x29, fail;\
+    bne testreg2, x31, fail;\
+    .pushsection .data; \
+    .align 3; \
+    test_ ## testnum ## _data: \
+    .dword correctval; \
+    .popsection
+
+// ^ x30 is used in some other macros, to avoid issues we use x31 for upper word
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in TESTNUM)
+#-----------------------------------------------------------------------
+
+#define TEST_PASSFAIL \
+        bne x0, TESTNUM, pass; \
+fail: \
+        RVTEST_FAIL; \
+pass: \
+        RVTEST_PASS \
+
+
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+
+#define TEST_DATA
+
+#endif
diff --git a/third_party/tests/Scr1/sim/tests/riscv_compliance/compliance_io.h b/third_party/tests/Scr1/sim/tests/riscv_compliance/compliance_io.h
new file mode 100644
index 0000000..5b7ca54
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_compliance/compliance_io.h
@@ -0,0 +1,70 @@
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef _COMPLIANCE_IO_H
+#define _COMPLIANCE_IO_H
+
+//-----------------------------------------------------------------------
+// RV IO Macros (Non functional)
+//-----------------------------------------------------------------------
+#ifdef _COMPLIANCE_OUTPUT
+
+#define RVTEST_IO_PUSH(_SP)                                             \
+la _SP, begin_regstate;                                                 \
+sw x3, 0(_SP);                                                          \
+sw x4, 4(_SP);                                                          \
+sw x5, 8(_SP);
+
+#define RVTEST_IO_POP(_SP)                                              \
+la _SP, begin_regstate;                                                 \
+lw x3, 0(_SP);                                                          \
+lw x4, 4(_SP);                                                          \
+lw x5, 8(_SP);	
+
+#define RVTEST_IO_WRITE_STR(_SP, _STR)	                                \
+    .section .data.string;                                              \
+20001:                                                                  \
+    .string _STR;                                                       \
+    .section .text;                                                     \
+    RVTEST_IO_PUSH(_SP)                                                 \
+    li x3, 0xF0000000;                                                  \
+    la x4, 20001b;                                                      \
+2:  lb x5, 0(x4);                                                       \
+    sb x5, 0(x3);                                                       \
+    beq x5, zero, 1f;                                                   \
+    add x4, x4, 1;                                                      \
+    j 2b;                                                               \
+1:  RVTEST_IO_POP(_SP)
+
+#else // #ifdef _COMPLIANCE_OUTPUT
+
+#define RVTEST_IO_WRITE_STR(_SP, _STR)
+
+#endif // #end #ifdef _COMPLIANCE_OUTPUT
+
+#define RVTEST_IO_INIT
+#define RVTEST_IO_CHECK()
+#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
+#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+#define RVTEST_IO_ASSERT_EQ(_R, _I) 
+
+#endif // _COMPLIANCE_IO_H
diff --git a/third_party/tests/Scr1/sim/tests/riscv_compliance/compliance_test.h b/third_party/tests/Scr1/sim/tests/riscv_compliance/compliance_test.h
new file mode 100644
index 0000000..0c7e7f9
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_compliance/compliance_test.h
@@ -0,0 +1,31 @@
+// RISC-V Compliance Test Header File
+// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
+// See LICENSE for license details.
+//
+// Description: Common header file for RV32I tests
+
+#ifndef _COMPLIANCE_TEST_H
+#define _COMPLIANCE_TEST_H
+
+//-----------------------------------------------------------------------
+// RV Compliance Macros
+//-----------------------------------------------------------------------
+
+#define RV_COMPLIANCE_HALT                                                   \
+
+#define RV_COMPLIANCE_RV32M                                                  \
+        RVTEST_RV32M                                                         \
+
+#define RV_COMPLIANCE_CODE_BEGIN                                             \
+        RVTEST_CODE_BEGIN                                                    \
+
+#define RV_COMPLIANCE_CODE_END                                               \
+        RVTEST_CODE_END                                                      \
+
+#define RV_COMPLIANCE_DATA_BEGIN                                             \
+        RVTEST_DATA_BEGIN                                                    \
+
+#define RV_COMPLIANCE_DATA_END                                               \
+        RVTEST_DATA_END                                                      \
+
+#endif
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/riscv_compliance/riscv_test.h b/third_party/tests/Scr1/sim/tests/riscv_compliance/riscv_test.h
new file mode 100644
index 0000000..fdc6156
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_compliance/riscv_test.h
@@ -0,0 +1,7 @@
+
+#ifndef _RISCV_TEST_H
+#define _RISCV_TEST_H
+
+#include "test_macros.h"
+
+#endif
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/riscv_compliance/test_macros.h b/third_party/tests/Scr1/sim/tests/riscv_compliance/test_macros.h
new file mode 100644
index 0000000..5f0615b
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_compliance/test_macros.h
@@ -0,0 +1,593 @@
+
+// RISC-V Compliance Test Header File
+// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
+// See LICENSE for license details.
+//
+// Description: Common header file for RV32I tests
+
+#ifndef _TEST_MACROS_H
+#define _TEST_MACROS_H
+
+#include "riscv_macros.h"
+
+// RISC-V Compliance IO Test Header File
+
+/*
+ * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+
+//
+// In general the following registers are reserved
+// ra, a0, t0, t1
+// Additionally on an assertion violation, t1, t2 are overwritten
+// x1, x10, x5, x6, x7 respectively
+// Floating registers reserved
+// f5
+//
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+// Base function for integer operations
+#define TEST_CASE(destreg, correctval, swreg, offset, code... ) \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+
+// Base functions for single precision floating point operations
+#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg1, 0(a0); \
+    flw reg2, 4(a0); \
+    lw t1, 8(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## test_num ## _data: \
+      .float val1; \
+      .float val2; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    lw t1, 0(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg, 0(a0); \
+    lw t1, 4(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 2; \
+    test_ ## test_num ## _data: \
+      .float val; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg1, 0(a0); \
+    flw reg2, 4(a0); \
+    flw reg3, 8(a0); \
+    lw t1, 12(a0); \
+    code; \
+    fsw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
+    .pushsection .data; \
+    .align 4; \
+    test_ ## test_num ## _data: \
+      .float val1; \
+      .float val2; \
+      .float val3; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    flw reg, 0(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .float val; \
+    .popsection
+
+#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \
+    la  a0, test_ ## test_num ## _data; \
+    li reg, val; \
+    code; \
+    fsw destreg, offset(swreg); \
+    lw a1, 0(a0); \
+    RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .word correctval; \
+    .popsection
+
+// Base functions for double precision floating point operations - rv32d
+#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg1, 0(a0); \
+    fld reg2, 8(a0); \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 16(a0); \
+    lw t2, 20(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## test_num ## _data: \
+      .double val1; \
+      .double val2; \
+      .dword correctval; \
+    .popsection; \
+    .pushsection .data; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 0(a0); \
+    lw t2, 4(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 1; \
+    test_ ## test_num ## _data: \
+      .dword correctval; \
+    .popsection; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg, 0(a0); \
+    lw t1, 8(a0); \
+    code; \
+    sw destreg, offset(swreg); \
+    RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
+    .pushsection .data; \
+    .align 2; \
+    test_ ## test_num ## _data: \
+      .double val; \
+      .word correctval; \
+    .popsection
+
+#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
+    la  a0, test_ ## test_num ## _data; \
+    fld reg1, 0(a0); \
+    fld reg2, 8(a0); \
+    fld reg3, 16(a0); \
+    code; \
+    fsd destreg, offset(swreg); \
+    lw t1, 24(a0); \
+    lw t2, 28(a0); \
+    la a0, store_ ## test_num ## _data; \
+    fsd destreg, 0(a0); \
+    lw a1, 0(a0); \
+    lw a2, 4(a0); \
+    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
+    .pushsection .data; \
+    .align 4; \
+    test_ ## test_num ## _data: \
+      .double val1; \
+      .double val2; \
+      .double val3; \
+      .dword correctval; \
+    .popsection; \
+    .pushsection .data; \
+    store_ ## test_num ## _data: \
+      .fill 1, 8, -1; \
+    .popsection
+
+//Tests for a instructions with register-register operand
+#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li  reg1, MASK_XLEN(val1); \
+      li  reg2, MASK_XLEN(val2); \
+      inst destreg, reg1, reg2; \
+    )
+
+#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val1); \
+      li reg, MASK_XLEN(val2); \
+      inst destreg, destreg, reg; \
+    )
+
+#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val1); \
+      li destreg, MASK_XLEN(val2); \
+      inst destreg, reg, destreg; \
+    )
+
+#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val1); \
+      inst destreg, destreg, destreg; \
+    )
+
+#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, x0, reg; \
+    )
+
+#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, reg, x0; \
+    )
+
+#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      inst destreg, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset) \
+    TEST_CASE( x0, 0, swreg, offset, \
+      li reg1, MASK_XLEN(val1); \
+      li reg2, MASK_XLEN(val2); \
+      inst x0, reg1, reg2; \
+    )
+
+//Tests for a instructions with register-immediate operand
+#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst destreg, reg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val); \
+      inst destreg, destreg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      inst destreg, x0, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset) \
+    TEST_CASE ( x0, 0, swreg, offset, \
+      li reg, MASK_XLEN(val); \
+      inst x0, reg, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      inst destreg, SEXT_IMM(imm); \
+      )
+
+#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      1: \
+      inst destreg, SEXT_IMM(imm); \
+      la swreg, 1b; \
+      sub destreg, destreg, swreg; \
+      )
+
+//Tests for a compressed instruction
+#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
+    TEST_CASE ( destreg, correctval, swreg, offset, \
+      li reg, MASK_XLEN(val1); \
+      li destreg, MASK_XLEN(val2); \
+      inst destreg, reg; \
+      )
+
+#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset) \
+    TEST_CASE( destreg, correctval, swreg, offset, \
+      li destreg, MASK_XLEN(val); \
+      inst destreg, imm; \
+      )
+
+#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset) \
+    TEST_CASE (x0, correctval, swreg, offset, \
+      inst imm; \
+      )
+
+//Tests for floating point instructions - single precision
+#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+      TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+        inst destreg, reg1, reg2; \
+        )
+
+#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+      TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+        inst destreg, reg1, reg2, reg3; \
+        )
+
+#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+        li reg, MASK_XLEN(val); \
+        inst destreg, reg; \
+        )
+
+#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+//Tests for floating point instructions - double precision
+#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
+      TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
+        inst destreg, reg1, reg2; \
+        )
+
+#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
+      TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
+        inst destreg, reg1, reg2, reg3; \
+        )
+
+#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \
+        li reg, MASK_XLEN(val); \
+        inst destreg, reg; \
+        )
+
+#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
+        inst destreg, reg; \
+        )
+
+#define TEST_CADDI16SP(correctval, imm, swreg, offset) \
+      TEST_CASE(x2, correctval, swreg, offset, \
+      c.addi16sp x2, imm; \
+      )
+
+#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset) \
+      TEST_CASE(destreg, correctval, swreg, offset, \
+        c.addi4spn destreg, x2, SEXT_IMM(imm); \
+        )
+
+#define TEST_CJL(inst, reg, val, swreg, offset) \
+      li x10, val; \
+      la reg, 1f; \
+      inst reg; \
+      li x10, 0x123ab; \
+1: \
+      sw x10, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \
+
+#define ABS(x) ((x >> 11) ^ x) - (x >> 11)
+
+#define TEST_CJ(inst, reg, val, swreg, offset) \
+      li reg, val; \
+      inst 1f; \
+      li reg, 0x123ab; \
+1: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CL(inst, reg, imm, swreg, offset) \
+      la reg, test_data; \
+      inst reg, imm(reg); \
+      sw reg, offset(swreg); \
+
+// lw reg, imm(x2)
+// c.lwsp reg, imm(x2)
+#define TEST_CLWSP(reg, imm, swreg, offset) \
+      la x2, test_data; \
+      c.lwsp reg, imm(x2); \
+      sw reg, offset(swreg); \
+
+#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \
+      li reg1, val; \
+      la reg2, test_data; \
+      inst reg1, imm(reg2); \
+      lw reg1, imm(reg2); \
+      sw reg1, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \
+
+#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \
+      la x2, test_data; \
+      li reg, val; \
+      c.swsp reg, imm(x2); \
+      lw reg, imm(x2); \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_CBEQZ(reg, val, swreg, offset) \
+      li reg, val; \
+      c.sub reg, reg; \
+      c.beqz reg, 3f; \
+      li reg, 0x123ab; \
+3: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \
+
+#define TEST_CBNEZ(reg, val, swreg, offset) \
+      li reg, val; \
+      c.bnez reg, 4f; \
+      li reg, 0x0; \
+4: \
+      sw reg, offset(swreg); \
+      RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
+
+#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \
+        fmv.x.s destreg, reg; \
+        )
+
+#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \
+      TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \
+        fmv.s.x destreg, reg; \
+        )
+
+#define SWSIG(a,b)
+
+
+#if __riscv_xlen == 64
+#define SATP_MODE SATP64_MODE
+#else
+#define SATP_MODE SATP32_MODE
+#endif
+
+#define SATP32_MODE         0x80000000
+#define SATP32_ASID         0x7FC00000
+#define SATP32_PPN          0x003FFFFF
+#define SATP64_MODE 0xF000000000000000
+#define SATP64_ASID 0x0FFFF00000000000
+#define SATP64_PPN  0x00000FFFFFFFFFFF
+
+#define SATP_MODE_OFF                0
+#define SATP_MODE_SV32               1
+#define SATP_MODE_SV39               8
+#define SATP_MODE_SV48               9
+#define SATP_MODE_SV57              10
+#define SATP_MODE_SV64              11
+
+#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    la  x31, test_ ## testnum ## _data ; \
+    lw  x29, 0(x31); \
+    lw  x31, 4(x31); \
+    li  TESTNUM, testnum; \
+    bne testreg1, x29, fail;\
+    bne testreg2, x31, fail;\
+    .pushsection .data; \
+    .align 3; \
+    test_ ## testnum ## _data: \
+    .dword correctval; \
+    .popsection
+
+#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  fld f0, 0(a0); \
+  fld f1, 8(a0); \
+  fld f2, 16(a0); \
+  lw  a3, 24(a0); \
+  lw  t1, 28(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne t1, t2, fail; \
+  bne a1, a2, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+  .popsection
+
+#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+                    inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FCLASS_D32(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, \
+            la a0, test_ ## testnum ## _data ;\
+            fld fa0, 0(a0); \
+            fclass.d a0, fa0) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## testnum ## _data: \
+    .dword input; \
+    .popsection
+
+#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+                    inst a0, f0, f1; li t2, 0)
+
+#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  lw  a3, 0(a0); \
+  lw  a4, 4(a0); \
+  li  a1, val1; \
+  inst f0, a1; \
+  \
+  fsd f0, 0(a0); \
+  lw a1, 4(a0); \
+  lw a0, 0(a0); \
+  \
+  fsflags x0; \
+  bne a0, a3, fail; \
+  bne a1, a4, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+  .popsection
+
+#define TEST_FCVT_S_D32( testnum, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+
+#endif
diff --git a/third_party/tests/Scr1/sim/tests/riscv_isa/Makefile b/third_party/tests/Scr1/sim/tests/riscv_isa/Makefile
new file mode 100644
index 0000000..80a9b9b
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_isa/Makefile
@@ -0,0 +1,88 @@
+
+include rv32_tests.inc
+
+override ARCH := imfc
+
+src_dir := $(CURDIR)
+obj_dir   := $(bld_dir)/riscv_objs
+test_list := $(patsubst %.S, %, $(notdir $(rv32_isa_tests)))
+objs      := $(addprefix $(obj_dir)/,$(test_list:%=%.o))
+test_elf  := $(addprefix $(bld_dir)/,$(test_list:%=%.elf))
+test_hex  := $(addprefix $(bld_dir)/,$(test_list:%=%.hex))
+test_dump := $(addprefix $(bld_dir)/,$(test_list:%=%.dump))
+
+CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=ilp32f -D__riscv_xlen=32 
+LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=rv32$(ARCH) -mabi=ilp32f
+
+VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(RISCV_TESTS)
+
+default: check_riscv_tests $(test_elf) $(test_hex) $(test_dump)
+
+define compile_template
+$(obj_dir)/$$(basename $(notdir $(SRC))).o: $$(SRC) | $(obj_dir)
+	$(RISCV_GCC) -c $$< $(CFLAGS) -o $$@
+ endef
+
+$(foreach SRC,$(rv32_isa_tests), $(eval $(compile_template)))
+
+$(obj_dir) :
+	mkdir -p $(obj_dir)
+
+$(bld_dir)/%.elf: $(obj_dir)/%.o | $(obj_dir)
+	$(RISCV_GCC) $^ $(LDFLAGS) -o $@
+
+$(bld_dir)/%.hex: $(bld_dir)/%.elf
+	$(RISCV_OBJCOPY) $^ $@
+
+$(bld_dir)/%.dump: $(bld_dir)/%.elf
+	$(RISCV_OBJDUMP) $^ > $@
+
+clean:
+	$(RM) $(test_elf) $(test_hex) $(test_dump) $(objs)
+	$(RM) -R $(obj_dir)
+
+
+.PHONY: check_riscv_tests
+
+riscv_tests_dir    := $(if $(RISCV_TESTS), $(RISCV_TESTS), ./undefined)
+riscv_tests_commit := a9433c4daa287fbe101025f2a079261a10149225
+## commit hash readed from local copy of https://github.com/riscv/riscv-tests
+tmp_commit = $(shell cd $(riscv_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ')
+is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true)
+
+# Color
+RED=\033[0;31m
+NC=\033[0m
+
+check_riscv_tests : $(riscv_tests_dir)
+	@if [ ! -d $(riscv_tests_dir) ]; then \
+		echo -e "$(RED)==========================================================================" &&\
+		echo "   Error! Environment variable RISCV_TESTS='$(riscv_tests_dir)' " &&\
+		echo "      directory not exist!" && \
+		echo "==========================================================================$(NC)" ; \
+	fi
+ifneq (,$(is_repo_changed))
+	@echo -e "$(RED)=========================================================================="
+	@echo "   Error! Repo '$(riscv_tests_dir)' "
+	@echo "     must be unchanged!"
+	@echo -e "==========================================================================$(NC)"
+	exit 1
+endif
+ifneq ($(is_commit_good),true)
+	@echo -e "$(RED)=========================================================================="
+	@echo "   Error! riscv-tests must point to commit $(riscv_tests_commit)"
+	@echo -e "==========================================================================$(NC)"
+	exit 1
+endif
+
+$(riscv_tests_dir) :.
+ifndef RISCV_TESTS
+	@echo -e "$(RED)=========================================================================="
+	@echo "    Error! Environment variable RISCV_TESTS not set!"
+	@echo "    You must set the environment variable RISCV_TESTS"
+	@echo "    The variable should point to the local copy of the"
+	@echo "      repository https://github.com/riscv/riscv-tests"
+	@echo "      with the commit $(riscv_tests_commit)"
+	@echo -e "==========================================================================$(NC)"
+	exit 1
+endif
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/riscv_isa/riscv_test.h b/third_party/tests/Scr1/sim/tests/riscv_isa/riscv_test.h
new file mode 100644
index 0000000..2b9ce0d
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_isa/riscv_test.h
@@ -0,0 +1,6 @@
+#ifndef __RISCV__TEST__H
+#define __RISCV__TEST__H
+
+#include "riscv_macros.h" 
+
+#endif // #ifndef __RISCV__TEST__H
diff --git a/third_party/tests/Scr1/sim/tests/riscv_isa/rv32_tests.inc b/third_party/tests/Scr1/sim/tests/riscv_isa/rv32_tests.inc
new file mode 100644
index 0000000..0086125
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_isa/rv32_tests.inc
@@ -0,0 +1,63 @@
+
+ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z)
+
+
+rv32_isa_tests += isa/rv32ui/add.S      \
+              isa/rv32ui/addi.S         \
+              isa/rv32ui/and.S          \
+              isa/rv32ui/andi.S         \
+              isa/rv32ui/auipc.S        \
+              isa/rv32ui/beq.S          \
+              isa/rv32ui/bge.S          \
+              isa/rv32ui/bgeu.S         \
+              isa/rv32ui/blt.S          \
+              isa/rv32ui/bltu.S         \
+              isa/rv32ui/bne.S          \
+              isa/rv32mi/csr.S          \
+              isa/rv32um/div.S          \
+              isa/rv32um/divu.S         \
+              isa/rv32ui/fence_i.S      \
+              isa/rv32mi/illegal.S      \
+              isa/rv32ui/jal.S          \
+              isa/rv32ui/jalr.S         \
+              isa/rv32ui/lb.S           \
+              isa/rv32ui/lbu.S          \
+              isa/rv32ui/lh.S           \
+              isa/rv32ui/lhu.S          \
+              isa/rv32ui/lui.S          \
+              isa/rv32ui/lw.S           \
+              isa/rv32mi/ma_addr.S      \
+              isa/rv32mi/ma_fetch.S     \
+              isa/rv32mi/mcsr.S         \
+              isa/rv32ui/or.S           \
+              isa/rv32ui/ori.S          \
+              isa/rv32uc/rvc.S          \
+              isa/rv32ui/sb.S           \
+              isa/rv32mi/sbreak.S       \
+              isa/rv32mi/scall.S        \
+              isa/rv32ui/sh.S           \
+              isa/rv32mi/shamt.S        \
+              isa/rv32ui/simple.S       \
+              isa/rv32ui/sll.S          \
+              isa/rv32ui/slli.S         \
+              isa/rv32ui/slt.S          \
+              isa/rv32ui/slti.S         \
+              isa/rv32ui/sltiu.S        \
+              isa/rv32ui/sltu.S         \
+              isa/rv32ui/sra.S          \
+              isa/rv32ui/srai.S         \
+              isa/rv32ui/srl.S          \
+              isa/rv32ui/srli.S         \
+              isa/rv32ui/sub.S          \
+              isa/rv32ui/sw.S           \
+              isa/rv32ui/xor.S          \
+              isa/rv32ui/xori.S
+
+ifneq (,$(findstring m,$(ARCH_lowercase)))
+rv32_isa_tests += isa/rv32um/mul.S      \
+              isa/rv32um/mulh.S         \
+              isa/rv32um/mulhsu.S       \
+              isa/rv32um/mulhu.S        \
+              isa/rv32um/rem.S          \
+              isa/rv32um/remu.S
+endif ## ifeq (m,$(findstring m,$(ARCH_lowercase)))
diff --git a/third_party/tests/Scr1/sim/tests/riscv_isa/test_macros.h b/third_party/tests/Scr1/sim/tests/riscv_isa/test_macros.h
new file mode 100644
index 0000000..743918d
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/riscv_isa/test_macros.h
@@ -0,0 +1,5 @@
+#ifndef __TEST__MACROS__H
+#define __TEST__MACROS__H
+
+
+#endif
diff --git a/third_party/tests/Scr1/sim/tests/vectored_isr_sample/Makefile b/third_party/tests/Scr1/sim/tests/vectored_isr_sample/Makefile
new file mode 100644
index 0000000..cce741e
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/vectored_isr_sample/Makefile
@@ -0,0 +1,13 @@
+src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+
+LDFLAGS := -nostartfiles -nostdlib -march=rv32$(ARCH) -mabi=$(ABI)
+ADD_ASM_MACRO := -DASM
+
+asm_src := v_isr_sample.S
+
+include $(inc_dir)/common.mk
+
+default: $(bld_dir)/v_isr_sample.elf $(bld_dir)/v_isr_sample.hex $(bld_dir)/v_isr_sample.dump
+
+clean:
+	$(RM)$(asm_objs) $(bld_dir)/v_isr_sample.elf $(bld_dir)/v_isr_sample.hex $(bld_dir)/v_isr_sample.dump
\ No newline at end of file
diff --git a/third_party/tests/Scr1/sim/tests/vectored_isr_sample/timer.h b/third_party/tests/Scr1/sim/tests/vectored_isr_sample/timer.h
new file mode 100644
index 0000000..c435f48
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/vectored_isr_sample/timer.h
@@ -0,0 +1,98 @@
+#ifndef __TIMER__H
+#define __TIMER__H
+
+
+#define MCAUSE_TMR_IRQ (1 << 31 | 7)
+
+#define MEM_MTIME_MASK  0xF0000000
+#define MEM_MTIME_CTRL  0x00490000
+#define MEM_MTIME_DIV   0x00490004
+#define MEM_MTIME       0x00490008
+#define MEM_MTIMEH      0x0049000C
+#define MEM_MTIMECMP    0x00490010
+#define MEM_MTIMECMPH   0x00490014
+
+#define TMP   t0
+#define TMP2  t1
+#define TMP3  t2
+
+// Reset
+.macro _reset_mtime
+    li          TMP, MEM_MTIME
+    sw          zero, 0(TMP)
+    sw          zero, 4(TMP)
+.endm
+
+.macro _reset_mtimecmp
+    li          TMP, MEM_MTIMECMP
+    not         TMP2, zero
+    sw          TMP2, 0(TMP)
+    sw          TMP2, 4(TMP)
+.endm
+
+// Write
+.macro _write_mtime_ctrl reg
+    li          TMP, MEM_MTIME_CTRL
+    sw          \reg, 0(TMP)
+.endm
+
+.macro _write_mtime_div reg
+    li          TMP, MEM_MTIME_DIV
+    sw          \reg, 0(TMP)
+.endm
+
+.macro _write_mtimecmp_32 reg
+    li          TMP, MEM_MTIMECMP
+    li          TMP2, -1
+    sw          TMP2, 0(TMP)
+    sw          zero, 4(TMP)
+    sw          \reg, 0(TMP)
+.endm
+
+.macro _write_mtime reg
+    li          TMP, MEM_MTIME
+    sw          \reg, 0(TMP)
+.endm
+
+.macro _read_mtime reg
+    li          TMP, MEM_MTIME
+    lw          \reg, 0(TMP)
+.endm
+
+// Read
+.macro _read_mtimecmp reg
+    li          TMP, MEM_MTIMECMP
+    lw          \reg, 0(TMP)
+.endm
+
+.macro _read_mtime_ctrl reg
+    li          TMP, MEM_MTIME_CTRL
+    lw          \reg, 0(TMP)
+.endm
+
+.macro _read_mtime_div reg
+    li          TMP, MEM_MTIME_DIV
+    lw          \reg, 0(TMP)
+.endm
+
+// Misc
+.macro _run_timer
+    li          TMP, MEM_MTIME_CTRL
+    lw          TMP2, 0(TMP)
+    li          TMP3, (1 << SCR1_MTIME_CTRL_EN)
+    or          TMP2, TMP2, TMP3
+    sw          TMP2, 0(TMP)
+.endm
+
+.macro _stop_timer
+    li          TMP, MEM_MTIME_CTRL
+    lw          TMP2, 0(TMP)
+    li          TMP3, (1 << SCR1_MTIME_CTRL_EN)
+    not         TMP3, TMP3
+    and         TMP2, TMP2, TMP3
+    sw          TMP2, 0(TMP)
+.endm
+
+
+
+#endif // #ifndef __TIMER__H
diff --git a/third_party/tests/Scr1/sim/tests/vectored_isr_sample/v_isr_sample.S b/third_party/tests/Scr1/sim/tests/vectored_isr_sample/v_isr_sample.S
new file mode 100644
index 0000000..7bf31e9
--- /dev/null
+++ b/third_party/tests/Scr1/sim/tests/vectored_isr_sample/v_isr_sample.S
@@ -0,0 +1,181 @@
+#include "riscv_macros.h"
+#include "sc_test.h"
+
+.altmacro
+// global interrupt bit
+#define MTIE                        (1 << IRQ_M_TIMER)
+#define MEIE                        (1 << IRQ_M_EXT)
+#define MCAUSE_EXT_IRQ              (1 << 31 | IRQ_M_EXT)
+
+// IPIC
+#define IRQ_LINES_ADDR              0xF0000100      // simulation
+#define IPIC_EOI                    0xBF4
+#define IPIC_SOI                    0xBF5
+#define IPIC_IDX                    0xBF6
+#define IPIC_ICSR                   0xBF7
+#define IPIC_ICSR_IP                (1 << 0)
+#define IPIC_ICSR_IE                (1 << 1)
+#define IPIC_ICSR_IM                (1 << 2)
+#define IPIC_ICSR_INV               (1 << 3)
+#define IPIC_ICSR_IS                (1 << 4)
+
+#include "timer.h"
+
+.macro jmp_sc_exit
+    la  t0, sc_exit
+    jr  t0
+.endm
+
+//  -----------------------------------------------------------------
+// Trap handlers
+// 0x100
+    .text
+    .option norvc
+    .align 6
+user_trap_entry:
+    csrr  a5, instret
+    csrr  a1, mcause
+    csrr  a2, mepc
+    csrr  a3, mbadaddr
+    csrr  a4, mstatus
+    li    a0, 0x100
+    jmp_sc_exit
+
+//0x140
+    .align 6
+supervisor_trap_entry:
+    csrr  a5, instret
+    csrr  a1, mcause
+    csrr  a2, mepc
+    csrr  a3, mbadaddr
+    csrr  a4, mstatus
+    li    a0, 0x140
+    jmp_sc_exit
+
+//0x180
+    .align 6
+hypervisor_trap_entry:
+    csrr  a5, instret
+    csrr  a1, mcause
+    csrr  a2, mbadaddr
+    csrr  a3, mepc
+    csrr  a4, mstatus
+    li    a0, 0x180
+    jmp_sc_exit
+
+//0x1C0
+    .align 6
+vec_usr_soft:
+// machine_trap_entry:
+trap_entry:
+    j    _trap_fail
+vec_supervisor_soft:
+    j    _trap_fail
+vec_reserved1:
+    j    _trap_fail
+vec_machine_soft:
+    j    _trap_fail
+vec_usr_tmr:
+    j    _trap_fail
+vec_supervisor_tmr:
+    j    _trap_fail
+vec_reserved2:
+    j    _trap_fail
+vec_machine_tmr:
+    j    vec_machine_tmr_handler
+vec_usr_ext:
+    j    _trap_fail
+vec_supervisor_ext:
+    j    _trap_fail
+vec_reserved3:
+    j    _trap_fail
+vec_machine_ext:
+    j    vec_machine_ext_handler
+vec_reserved4:
+    j    _trap_fail
+    j    _trap_fail
+    j    _trap_fail
+    j    _trap_fail
+
+//0x200
+    .globl _start
+_start:
+    // vectored mode
+    csrsi               mtvec, 1
+    _reset_mtimecmp;
+    _run_timer;
+    // then enable global interrrupt
+    csrs                mstatus, MSTATUS_MIE
+    // enable tmr irq
+    li                  a0, MTIE
+    csrs                mie, a0
+    // timer counter = 0 (updated in isr)
+    li                  t2, 0
+    _read_mtime         s1
+    addi                s1, s1, 256
+    _write_mtimecmp_32  s1
+    wfi
+    // disable all irq
+    csrw                mie, zero
+    // setup IPIC
+    li                  t0, IRQ_LINES_ADDR
+    sh                  zero, (t0)
+    li                  t0, 9           // IPIC irq 9
+    csrw                IPIC_IDX, t0
+    li                  t0, (IPIC_ICSR_IE | IPIC_ICSR_IM)
+    csrw                IPIC_ICSR, t0   // enable, rising edge
+    li                  t0, MEIE
+    csrs                mie, t0
+    li                  t0, IRQ_LINES_ADDR
+    li                  t1, (1 << 9)
+    sh                  t1, (t0)
+    wfi
+    li                  s1, 2
+    li                  a0, 0
+    beq                 t2, s1, 1f
+    li                  a0, -1
+1:
+    jmp_sc_exit
+
+
+vec_machine_tmr_handler:
+    csrr            a1, mcause
+    li              a5, MCAUSE_TMR_IRQ     //0x80000007 -- mcause = tmr.irq
+    li              a0, -1
+    bne             a1, a5, check_fail
+    csrr            t1, mip
+    li              t0, MIP_MTIP
+    and             t0, t1, t0
+    beqz            t1, check_fail
+    _reset_mtimecmp
+    csrr            t1, mip
+    andi            t1, t1, MIP_MTIP
+    bne             t1, zero, check_fail
+    addi            t2, t2, 1              // tmr irq counter update
+    mret
+
+vec_machine_ext_handler:
+    csrr            a1, mcause
+    li              a5, MCAUSE_EXT_IRQ     //0x8000000B -- mcause = ext.irq
+    li              a0, -1
+    bne             a1, a5, check_fail
+    csrr            t1, mip
+    li              t0, MIP_MEIP
+    and             t0, t1, t0
+    beqz            t1, check_fail
+    csrw            IPIC_SOI, zero
+    csrw            IPIC_EOI, zero
+    csrr            t1, mip
+    li              t0, MIP_MEIP
+    and             t1, t1, t0
+    bne             t1, zero, check_fail
+    addi            t2, t2, 1               // ext irq counter update
+    mret
+
+check_fail:
+    la              t0, sc_exit
+    jr              t0
+
+_trap_fail:
+    li              a0, -1
+    j               check_fail
diff --git a/third_party/tests/Scr1/sim/verilator_wrap/scr1_ahb_wrapper.c b/third_party/tests/Scr1/sim/verilator_wrap/scr1_ahb_wrapper.c
new file mode 100644
index 0000000..dd10043
--- /dev/null
+++ b/third_party/tests/Scr1/sim/verilator_wrap/scr1_ahb_wrapper.c
@@ -0,0 +1,56 @@
+
+#include <stdio.h>
+#include <verilated.h>
+#include "Vscr1_top_tb_ahb.h"
+#ifdef VCD_TRACE
+#include "verilated_vcd_c.h"
+#endif // #ifdef VCD_TRACE
+
+#define STRINGIFY(s) _STRINGIFY(s)
+#define _STRINGIFY(s) #s
+
+Vscr1_top_tb_ahb *top;
+
+vluint64_t main_time = 0;
+
+int main(int argc, char** argv) {
+    Verilated::commandArgs(argc, argv);
+
+    top = new Vscr1_top_tb_ahb;
+
+#ifdef VCD_TRACE
+    Verilated::traceEverOn(true);
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+#ifdef TRACE_LVLV
+    top->trace(tfp, TRACE_LVLV);
+#else
+    top->trace(tfp, 99);  // Trace 99 levels of hierarchy by default
+#endif // #ifdef TRACE_LVLV
+
+#ifdef VCD_FNAME
+    tfp->open(STRINGIFY(VCD_FNAME));
+#else
+    tfp->open("./simx.vcd");
+#endif // #ifdef VCD_FNAME
+#endif // #ifdef VCD_TRACE
+
+    while (!Verilated::gotFinish()) {
+        if ((main_time % 10) == 1) {
+            top->clk = 1;
+        }
+        if ((main_time % 10) == 6) {
+            top->clk = 0;
+        }
+        top->eval();
+        main_time++;
+#ifdef VCD_TRACE
+        tfp->dump(main_time);
+#endif // #ifdef VCD_TRACE
+    }
+    top->final();
+#ifdef VCD_TRACE
+    tfp->close();
+#endif // #ifdef VCD_TRACE
+    delete top;
+}
+
diff --git a/third_party/tests/Scr1/sim/verilator_wrap/scr1_axi_wrapper.c b/third_party/tests/Scr1/sim/verilator_wrap/scr1_axi_wrapper.c
new file mode 100644
index 0000000..fbb1c95
--- /dev/null
+++ b/third_party/tests/Scr1/sim/verilator_wrap/scr1_axi_wrapper.c
@@ -0,0 +1,55 @@
+
+#include <stdio.h>
+#include <verilated.h>
+#include "Vscr1_top_tb_axi.h"
+#ifdef VCD_TRACE
+#include "verilated_vcd_c.h"
+#endif // #ifdef VCD_TRACE
+
+#define STRINGIFY(s) _STRINGIFY(s)
+#define _STRINGIFY(s) #s
+
+Vscr1_top_tb_axi *top;
+
+vluint64_t main_time = 0;
+
+int main(int argc, char** argv) {
+    Verilated::commandArgs(argc, argv);
+
+    top = new Vscr1_top_tb_axi;
+#ifdef VCD_TRACE
+    Verilated::traceEverOn(true);
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+#ifdef TRACE_LVLV
+    top->trace(tfp, TRACE_LVLV);
+#else
+    top->trace(tfp, 99);  // Trace 99 levels of hierarchy by default
+#endif // #ifdef TRACE_LVLV
+
+#ifdef VCD_FNAME
+    tfp->open(STRINGIFY(VCD_FNAME));
+#else
+    tfp->open("./simx.vcd");
+#endif // #ifdef VCD_FNAME
+#endif // #ifdef VCD_TRACE
+
+    while (!Verilated::gotFinish()) {
+        if ((main_time % 10) == 1) {
+            top->clk = 1;
+        }
+        if ((main_time % 10) == 6) {
+            top->clk = 0;
+        }
+        top->eval();
+        main_time++;
+#ifdef VCD_TRACE
+        tfp->dump(main_time);
+#endif // #ifdef VCD_TRACE
+    }
+    top->final();
+#ifdef VCD_TRACE
+    tfp->close();
+#endif // #ifdef VCD_TRACE
+    delete top;
+}
+
diff --git a/third_party/tests/Scr1/src/ahb_tb.files b/third_party/tests/Scr1/src/ahb_tb.files
new file mode 100644
index 0000000..d115b47
--- /dev/null
+++ b/third_party/tests/Scr1/src/ahb_tb.files
@@ -0,0 +1,3 @@
+pipeline/scr1_tracelog.sv
+tb/scr1_memory_tb_ahb.sv
+tb/scr1_top_tb_ahb.sv
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/ahb_top.files b/third_party/tests/Scr1/src/ahb_top.files
new file mode 100644
index 0000000..252a7a7
--- /dev/null
+++ b/third_party/tests/Scr1/src/ahb_top.files
@@ -0,0 +1,10 @@
+top/scr1_dmem_router.sv
+top/scr1_imem_router.sv
+top/scr1_dp_memory.sv
+top/scr1_tcm.sv
+top/scr1_timer.sv
+top/scr1_dmem_ahb.sv
+top/scr1_imem_ahb.sv
+top/scr1_top_ahb.sv
+top/scr1_mem_axi.sv
+top/scr1_top_axi.sv
diff --git a/third_party/tests/Scr1/src/axi_tb.files b/third_party/tests/Scr1/src/axi_tb.files
new file mode 100644
index 0000000..7896093
--- /dev/null
+++ b/third_party/tests/Scr1/src/axi_tb.files
@@ -0,0 +1,3 @@
+pipeline/scr1_tracelog.sv
+tb/scr1_memory_tb_axi.sv
+tb/scr1_top_tb_axi.sv
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/axi_top.files b/third_party/tests/Scr1/src/axi_top.files
new file mode 100644
index 0000000..24f4b8e
--- /dev/null
+++ b/third_party/tests/Scr1/src/axi_top.files
@@ -0,0 +1,7 @@
+top/scr1_dmem_router.sv
+top/scr1_imem_router.sv
+top/scr1_dp_memory.sv
+top/scr1_tcm.sv
+top/scr1_timer.sv
+top/scr1_mem_axi.sv
+top/scr1_top_axi.sv
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core.files b/third_party/tests/Scr1/src/core.files
new file mode 100644
index 0000000..67f9cf1
--- /dev/null
+++ b/third_party/tests/Scr1/src/core.files
@@ -0,0 +1,21 @@
+pipeline/scr1_pipe_hdu.sv
+pipeline/scr1_pipe_tdu.sv
+pipeline/scr1_ipic.sv
+pipeline/scr1_pipe_csr.sv
+pipeline/scr1_pipe_exu.sv
+pipeline/scr1_pipe_ialu.sv
+pipeline/scr1_pipe_idu.sv
+pipeline/scr1_pipe_ifu.sv
+pipeline/scr1_pipe_lsu.sv
+pipeline/scr1_pipe_mprf.sv
+pipeline/scr1_pipe_top.sv
+core/primitives/scr1_reset_cells.sv
+core/primitives/scr1_cg.sv
+core/scr1_clk_ctrl.sv
+core/scr1_tapc_shift_reg.sv
+core/scr1_tapc.sv
+core/scr1_tapc_synchronizer.sv
+core/scr1_core_top.sv
+core/scr1_dm.sv
+core/scr1_dmi.sv
+core/scr1_scu.sv
diff --git a/third_party/tests/Scr1/src/core/primitives/scr1_cg.sv b/third_party/tests/Scr1/src/core/primitives/scr1_cg.sv
new file mode 100644
index 0000000..f94db2c
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/primitives/scr1_cg.sv
@@ -0,0 +1,32 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_cg.sv>
+/// @brief      SCR1 clock gate primitive
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_CLKCTRL_EN
+module scr1_cg (
+    input   logic   clk,
+    input   logic   clk_en,
+    input   logic   test_mode,
+    output  logic   clk_out
+);
+
+// The code below is a clock gate model for simulation.
+// For synthesis, it should be replaced by implementation-specific
+// clock gate code.
+
+logic latch_en;
+
+always_latch begin
+    if (~clk) begin
+        latch_en <= test_mode | clk_en;
+    end
+end
+
+assign clk_out  = latch_en & clk;
+
+endmodule : scr1_cg
+
+`endif // SCR1_CLKCTRL_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core/primitives/scr1_reset_cells.sv b/third_party/tests/Scr1/src/core/primitives/scr1_reset_cells.sv
new file mode 100644
index 0000000..e5ec638
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/primitives/scr1_reset_cells.sv
@@ -0,0 +1,166 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_sync_rstn.sv>
+/// @brief      Cells for reset handling
+///
+
+module scr1_reset_buf_cell (
+    input   logic           rst_n,
+    input   logic           clk,
+    input   logic           test_mode,
+    input   logic           test_rst_n,
+    input   logic           reset_n_in,
+    output  logic           reset_n_out,
+    output  logic           reset_n_status
+);
+
+logic       reset_n_ff;
+logic       reset_n_status_ff;
+logic       rst_n_mux;
+
+assign rst_n_mux = (test_mode == 1'b1) ? test_rst_n : rst_n;
+
+always_ff @(negedge rst_n_mux, posedge clk) begin
+    if (~rst_n_mux) begin
+        reset_n_ff <= 1'b0;
+    end else begin
+        reset_n_ff <= reset_n_in;
+    end
+end
+
+assign reset_n_out = (test_mode == 1'b1) ? test_rst_n : reset_n_ff;
+
+always_ff @(negedge rst_n_mux, posedge clk) begin
+    if (~rst_n_mux) begin
+        reset_n_status_ff <= 1'b0;
+    end else begin
+        reset_n_status_ff <= reset_n_in;
+    end
+end
+assign reset_n_status = reset_n_status_ff;
+
+endmodule : scr1_reset_buf_cell
+
+
+module scr1_reset_sync_cell (
+    input   logic           rst_n,
+    input   logic           clk,
+    input   logic           test_rst_n,
+    input   logic           test_mode,
+    output  logic           rst_n_out
+);
+
+logic [1:0] rst_n_dff;
+logic       local_rst_n_in;
+
+assign local_rst_n_in = (test_mode == 1'b1) ? test_rst_n : rst_n;
+
+always_ff @(negedge local_rst_n_in, posedge clk) begin
+    if (~local_rst_n_in) begin
+        rst_n_dff <= '0;
+    end else begin
+        rst_n_dff[0] <= 1'b1;
+        rst_n_dff[1] <= rst_n_dff[0];
+    end
+end
+
+assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_dff[1];
+
+endmodule : scr1_reset_sync_cell
+
+
+module scr1_reset_buf_qlfy_cell (
+    input   logic           rst_n,
+    input   logic           clk,
+    input   logic           test_rst_n,
+    input   logic           test_mode,
+    input   logic           reset_n_in,
+    output  logic           reset_n_out_qlfy,
+    output  logic           reset_n_out,
+    output  logic           reset_n_status
+);
+
+logic rst_n_mux;
+logic reset_n_in_mux;
+logic reset_n_front_ff;
+logic reset_n_victim_ff;
+logic reset_n_qualifier_ff;
+logic reset_n_lucky_ff;
+logic reset_n_status_ff;
+
+// Front async stage
+assign reset_n_in_mux = (test_mode == 1'b1) ? test_rst_n : (rst_n & reset_n_in);
+
+always_ff @(negedge reset_n_in_mux, posedge clk) begin
+    if (~reset_n_in_mux) begin
+        reset_n_front_ff    <= 1'b0;
+    end else begin
+        reset_n_front_ff    <= 1'b1;
+    end
+end
+
+// Core sync stages
+assign rst_n_mux = (test_mode == 1'b1) ? test_rst_n : rst_n;
+
+always_ff @(negedge rst_n_mux, posedge clk) begin
+    if (~rst_n_mux) begin
+        reset_n_victim_ff    <= 1'b0;
+        reset_n_qualifier_ff <= 1'b0;
+        reset_n_lucky_ff     <= 1'b0;
+    end else begin
+        reset_n_victim_ff    <= reset_n_front_ff;
+        reset_n_qualifier_ff <= reset_n_victim_ff;
+        reset_n_lucky_ff     <= reset_n_qualifier_ff;
+    end
+end
+
+assign reset_n_out_qlfy = reset_n_qualifier_ff;
+assign reset_n_out      = (test_mode == 1'b1) ? test_rst_n : reset_n_lucky_ff;
+
+// Reset status stage
+always_ff @(negedge rst_n_mux, posedge clk) begin
+    if (~rst_n_mux) begin
+        reset_n_status_ff    <= 1'b0;
+    end else begin
+        reset_n_status_ff    <= reset_n_qualifier_ff;
+    end
+end
+assign reset_n_status = reset_n_status_ff;
+
+endmodule : scr1_reset_buf_qlfy_cell
+
+
+module scr1_reset_and2_cell (
+    input   logic [1:0]     rst_n_in,
+    input   logic           test_rst_n,
+    input   logic           test_mode,
+    output  logic           rst_n_out
+);
+
+assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : (&rst_n_in);
+
+endmodule : scr1_reset_and2_cell
+
+
+module scr1_reset_and3_cell (
+    input   logic [2:0]     rst_n_in,
+    input   logic           test_rst_n,
+    input   logic           test_mode,
+    output  logic           rst_n_out
+);
+
+assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : (&rst_n_in);
+
+endmodule : scr1_reset_and3_cell
+
+
+module scr1_reset_mux2_cell (
+    input   logic [1:0]     rst_n_in,
+    input   logic           select,
+    input   logic           test_rst_n,
+    input   logic           test_mode,
+    output  logic           rst_n_out
+);
+
+assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_in[select];
+
+endmodule : scr1_reset_mux2_cell
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core/scr1_clk_ctrl.sv b/third_party/tests/Scr1/src/core/scr1_clk_ctrl.sv
new file mode 100644
index 0000000..fb96630
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/scr1_clk_ctrl.sv
@@ -0,0 +1,51 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_clk_ctrl.sv>
+/// @brief      SCR1 clock control
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_CLKCTRL_EN
+module scr1_clk_ctrl (
+    input   logic   clk,
+    input   logic   rst_n,
+    input   logic   test_mode,
+
+    input   logic   sleep_pipe,
+    input   logic   wake_pipe,
+
+    output  logic   clkout,         // always on
+    output  logic   clkout_pipe,
+    output  logic   clk_pipe_en,
+    output  logic   clkout_dbgc     // always on (for now)
+);
+
+assign clkout       = clk;
+assign clkout_dbgc  = clk;
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        clk_pipe_en <= 1'b1;
+    end else begin
+        if (clk_pipe_en) begin
+            if (sleep_pipe & ~wake_pipe) begin
+                clk_pipe_en <= 1'b0;
+            end
+        end else begin // ~clk_pipe_en
+            if (wake_pipe) begin
+                clk_pipe_en <= 1'b1;
+            end
+        end // pipeline
+    end
+end
+
+scr1_cg i_scr1_cg_pipe (
+    .clk        (clk        ),
+    .clk_en     (clk_pipe_en),
+    .test_mode  (test_mode  ),
+    .clk_out    (clkout_pipe)
+);
+
+endmodule : scr1_clk_ctrl
+
+`endif // SCR1_CLKCTRL_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core/scr1_core_top.sv b/third_party/tests/Scr1/src/core/scr1_core_top.sv
new file mode 100644
index 0000000..d208e7b
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/scr1_core_top.sv
@@ -0,0 +1,540 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_core_top.sv>
+/// @brief      SCR1 core top
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_arch_types.svh"
+`include "scr1_memif.svh"
+
+`ifdef SCR1_DBGC_EN
+`include "scr1_tapc.svh"
+`include "scr1_dm.svh"
+`include "scr1_hdu.svh"
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_IPIC_EN
+`include "scr1_ipic.svh"
+`endif // SCR1_IPIC_EN
+
+module scr1_core_top #(
+    parameter bit SCR1_RESET_INPUTS_SYNC = 1 // Reset inputs are: 1 - synchronous, 0 -asynchronous
+) (
+    // Common
+    input   logic                                   pwrup_rst_n,
+    input   logic                                   rst_n,
+    input   logic                                   cpu_rst_n,
+    input   logic                                   test_mode,
+    input   logic                                   test_rst_n,
+    input   logic                                   clk,
+    output  logic                                   core_rst_n_out,
+`ifdef SCR1_DBGC_EN
+    output  logic                                   ndm_rst_n_out,
+`endif // SCR1_DBGC_EN
+    
+    // Fuses
+    input   logic [`SCR1_XLEN-1:0]                  fuse_mhartid,
+`ifdef SCR1_DBGC_EN
+    input   logic [31:0]                            fuse_idcode,
+`endif // SCR1_DBGC_EN
+
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    input   logic [SCR1_IRQ_LINES_NUM-1:0]          irq_lines,
+`else
+    input   logic                                   ext_irq,
+`endif // SCR1_IPIC_EN
+    input   logic                                   soft_irq,
+
+    // Memory-mapped external timer
+    input   logic                                   timer_irq,
+    input   logic [63:0]                            mtime_ext,
+
+`ifdef SCR1_DBGC_EN
+    // Debug Interface
+    input   logic                                   trst_n,
+    input   logic                                   tck,
+    input   logic                                   tms,
+    input   logic                                   tdi,
+    output  logic                                   tdo,
+    output  logic                                   tdo_en,
+`endif // SCR1_DBGC_EN
+
+    // Instruction Memory Interface
+    input   logic                                   imem_req_ack,
+    output  logic                                   imem_req,
+    output  type_scr1_mem_cmd_e                     imem_cmd,
+    output  logic [`SCR1_IMEM_AWIDTH-1:0]           imem_addr,
+    input   logic [`SCR1_IMEM_DWIDTH-1:0]           imem_rdata,
+    input   type_scr1_mem_resp_e                    imem_resp,
+
+    // Data Memory Interface
+    input   logic                                   dmem_req_ack,
+    output  logic                                   dmem_req,
+    output  type_scr1_mem_cmd_e                     dmem_cmd,
+    output  type_scr1_mem_width_e                   dmem_width,
+    output  logic [`SCR1_DMEM_AWIDTH-1:0]           dmem_addr,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]           dmem_wdata,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]           dmem_rdata,
+    input   type_scr1_mem_resp_e                    dmem_resp
+);
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+
+// Reset Logic
+`ifdef SCR1_DBGC_EN
+`else // SCR1_DBGC_EN
+logic                                           core_rst_n_sync;
+`endif // SCR1_DBGC_EN
+logic                                           core_rst_n;
+logic                                           core_rst_n_qlfy;
+logic                                           pwrup_rst_n_sync;
+logic                                           rst_n_sync;
+logic                                           cpu_rst_n_sync;
+
+`ifdef SCR1_DBGC_EN
+// TAPC-DM Interface
+logic                                           tapc_dmi_ch_sel;
+logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]            tapc_dmi_ch_id;
+logic                                           tapc_dmi_ch_capture;
+logic                                           tapc_dmi_ch_shift;
+logic                                           tapc_dmi_ch_update;
+logic                                           tapc_dmi_ch_tdi;
+logic                                           tapc_dmi_ch_tdo;
+//
+logic                                           tapc_dmi_ch_sel_tapout;
+logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]            tapc_dmi_ch_id_tapout;
+logic                                           tapc_dmi_ch_capture_tapout;
+logic                                           tapc_dmi_ch_shift_tapout;
+logic                                           tapc_dmi_ch_update_tapout;
+logic                                           tapc_dmi_ch_tdi_tapout;
+logic                                           tapc_dmi_ch_tdo_tapin;
+//
+logic                                           dmi_req;
+logic                                           dmi_wr;
+logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0]             dmi_addr;
+logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]             dmi_wdata;
+logic                                           dmi_resp;
+logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]             dmi_rdata;
+// TAPC-SCU Interface
+logic                                           tapc_scu_ch_sel;
+logic                                           tapc_scu_ch_sel_tapout;
+logic                                           tapc_scu_ch_tdo;
+logic                                           tapc_ch_tdo;
+// SCU nets
+logic                                           tapc_rst_n;
+logic                                           hdu_rst_n;
+logic                                           hdu_rst_n_qlfy;
+logic                                           ndm_rst_n;
+logic                                           dm_rst_n;
+logic                                           hart_rst_n;
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_DBGC_EN
+// DM-Pipeline Interface
+// HART Run Control i/f
+logic                                           dm_active;
+logic                                           dm_cmd_req;
+type_scr1_hdu_dbgstates_e                       dm_cmd;
+logic                                           dm_cmd_resp;
+logic                                           dm_cmd_resp_qlfy;
+logic                                           dm_cmd_rcode;
+logic                                           dm_cmd_rcode_qlfy;
+logic                                           dm_hart_event;
+logic                                           dm_hart_event_qlfy;
+type_scr1_hdu_hartstatus_s                      dm_hart_status;
+type_scr1_hdu_hartstatus_s                      dm_hart_status_qlfy;
+// Program Buffer - HART instruction execution i/f
+logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]            dm_pbuf_addr;
+logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]            dm_pbuf_addr_qlfy;
+logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0]           dm_pbuf_instr;
+// HART Abstract Data regs i/f
+logic                                           dm_dreg_req;
+logic                                           dm_dreg_req_qlfy;
+logic                                           dm_dreg_wr;
+logic                                           dm_dreg_wr_qlfy;
+logic [SCR1_HDU_DATA_REG_WIDTH-1:0]             dm_dreg_wdata;
+logic [SCR1_HDU_DATA_REG_WIDTH-1:0]             dm_dreg_wdata_qlfy;
+logic                                           dm_dreg_resp;
+logic                                           dm_dreg_fail;
+logic [SCR1_HDU_DATA_REG_WIDTH-1:0]             dm_dreg_rdata;
+
+logic [`SCR1_XLEN-1 : 0]                        dm_pc_sample;
+logic [`SCR1_XLEN-1 : 0]                        dm_pc_sample_qlfy;
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_CLKCTRL_EN
+// Global clock gating logic
+logic                                           sleep_pipe;
+logic                                           wake_pipe;
+logic                                           clk_pipe;
+logic                                           clk_pipe_en;
+logic                                           clk_dbgc;
+logic                                           clk_alw_on;
+`endif // SCR1_CLKCTRL_EN
+
+// Block busy signals
+
+//-------------------------------------------------------------------------------
+// Reset Logic
+//-------------------------------------------------------------------------------
+`ifdef SCR1_DBGC_EN
+scr1_scu #(
+    .SCR1_SCU_CFG_RESET_INPUTS_SYNC     (SCR1_RESET_INPUTS_SYNC)
+) i_scu(
+    // Global signals
+    .pwrup_rst_n                (pwrup_rst_n),
+    .rst_n                      (rst_n),
+    .cpu_rst_n                  (cpu_rst_n),
+    .test_mode                  (test_mode),
+    .test_rst_n                 (test_rst_n),
+    .clk                        (clk),
+    // TAPC scan-chains
+    .tapc_ch_sel                (tapc_scu_ch_sel),
+    .tapc_ch_id                 ('0),
+    .tapc_ch_capture            (tapc_dmi_ch_capture),
+    .tapc_ch_shift              (tapc_dmi_ch_shift),
+    .tapc_ch_update             (tapc_dmi_ch_update),
+    .tapc_ch_tdi                (tapc_dmi_ch_tdi),
+    .tapc_ch_tdo                (tapc_scu_ch_tdo),
+    // Input sync resets:
+    .ndm_rst_n                  (ndm_rst_n),
+    .hart_rst_n                 (hart_rst_n),
+    // Generated resets and their attributes (qualifiers etc):
+    .core_rst_n                 (core_rst_n),
+    .core_rst_n_qlfy            (core_rst_n_qlfy),
+    .dm_rst_n                   (dm_rst_n),
+    .hdu_rst_n                  (hdu_rst_n),
+    .hdu_rst_n_qlfy             (hdu_rst_n_qlfy)
+);
+
+// TAPC reset
+scr1_reset_and2_cell i_tapc_rstn_and2_cell (
+    .rst_n_in       ({trst_n, pwrup_rst_n}),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (tapc_rst_n)
+);
+assign ndm_rst_n_out  = ndm_rst_n;
+
+generate
+
+if (SCR1_RESET_INPUTS_SYNC)
+// reset inputs are synchronous
+
+begin : gen_rst_inputs_sync
+    assign pwrup_rst_n_sync = pwrup_rst_n;
+end : gen_rst_inputs_sync
+
+else // SCR1_RESET_INPUTS_SYNC == 0, - reset inputs are asynchronous
+
+begin : gen_rst_inputs_async
+// Power-Up Reset synchronizer
+scr1_reset_sync_cell i_pwrup_rstn_reset_sync (
+    .rst_n          (pwrup_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (pwrup_rst_n_sync)
+);
+end : gen_rst_inputs_async
+
+// end of  SCR1_RESET_INPUTS_SYNC
+
+endgenerate
+
+`else // SCR1_DBGC_EN
+
+generate
+
+if (SCR1_RESET_INPUTS_SYNC)
+// reset inputs are synchronous
+
+begin : gen_rst_inputs_sync
+    assign pwrup_rst_n_sync = pwrup_rst_n;
+    assign rst_n_sync       = rst_n;
+    assign cpu_rst_n_sync   = cpu_rst_n;
+end : gen_rst_inputs_sync
+
+else // SCR1_RESET_INPUTS_SYNC == 0, - reset inputs are asynchronous
+
+begin : gen_rst_inputs_async
+// Power-Up Reset synchronizer
+scr1_reset_sync_cell i_pwrup_rstn_reset_sync (
+    .rst_n          (pwrup_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (pwrup_rst_n_sync)
+);
+
+// Regular Reset synchronizer
+scr1_reset_sync_cell i_rstn_reset_sync (
+    .rst_n          (rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (rst_n_sync)
+);
+
+// CPU Reset synchronizer
+scr1_reset_sync_cell i_cpu_rstn_reset_sync (
+    .rst_n          (cpu_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (cpu_rst_n_sync)
+);
+end : gen_rst_inputs_async
+
+// end of  SCR1_RESET_INPUTS_SYNC
+
+endgenerate
+
+// Core Reset: core_rst_n
+scr1_reset_buf_qlfy_cell i_core_rstn_buf_qlfy_cell (
+    .rst_n              (pwrup_rst_n_sync),
+    .clk                (clk),
+    .test_rst_n         (test_rst_n),
+    .test_mode          (test_mode),
+    .reset_n_in         (core_rst_n_sync),
+    .reset_n_out_qlfy   (core_rst_n_qlfy),
+    .reset_n_out        (core_rst_n),
+    .reset_n_status     ()
+);
+assign core_rst_n_sync      = rst_n_sync & cpu_rst_n_sync;
+`endif // SCR1_DBGC_EN
+assign core_rst_n_out       = core_rst_n;
+
+//-------------------------------------------------------------------------------
+// SCR1 pipeline
+//-------------------------------------------------------------------------------
+scr1_pipe_top i_pipe_top (
+    // Control
+    .pipe_rst_n             (core_rst_n         ),
+`ifdef SCR1_DBGC_EN
+    .pipe_rst_n_qlfy        (core_rst_n_qlfy    ),
+    .dbg_rst_n              (hdu_rst_n          ),
+`endif // SCR1_DBGC_EN
+`ifndef SCR1_CLKCTRL_EN
+    .clk                    (clk                ),
+`else // SCR1_CLKCTRL_EN
+    .clk                    (clk_pipe           ),
+    .sleep_pipe             (sleep_pipe         ),
+    .wake_pipe              (wake_pipe          ),
+    .clk_alw_on             (clk_alw_on         ),
+    .clk_dbgc               (clk_dbgc           ),
+    .clk_pipe_en            (clk_pipe_en        ),
+`endif // SCR1_CLKCTRL_EN
+    // Instruction memory interface
+    .imem_req               (imem_req           ),
+    .imem_cmd               (imem_cmd           ),
+    .imem_addr              (imem_addr          ),
+    .imem_req_ack           (imem_req_ack       ),
+    .imem_rdata             (imem_rdata         ),
+    .imem_resp              (imem_resp          ),
+    // Data memory interface
+    .dmem_req               (dmem_req           ),
+    .dmem_cmd               (dmem_cmd           ),
+    .dmem_width             (dmem_width         ),
+    .dmem_addr              (dmem_addr          ),
+    .dmem_wdata             (dmem_wdata         ),
+    .dmem_req_ack           (dmem_req_ack       ),
+    .dmem_rdata             (dmem_rdata         ),
+    .dmem_resp              (dmem_resp          ),
+`ifdef SCR1_DBGC_EN
+    // Debug interface:
+    // DM <-> Pipeline: HART Run Control i/f
+    .dm_active              (dm_active          ),
+    .dm_cmd_req             (dm_cmd_req         ),
+    .dm_cmd                 (dm_cmd             ),
+    .dm_cmd_resp            (dm_cmd_resp        ),
+    .dm_cmd_rcode           (dm_cmd_rcode       ),
+    .dm_hart_event          (dm_hart_event      ),
+    .dm_hart_status         (dm_hart_status     ),
+    // DM <-> Pipeline: Program Buffer - HART instruction execution i/f
+    .dm_pbuf_addr           (dm_pbuf_addr       ),
+    .dm_pbuf_instr          (dm_pbuf_instr      ),
+    // DM <-> Pipeline: HART Abstract Data regs i/f
+    .dm_dreg_req            (dm_dreg_req        ),
+    .dm_dreg_wr             (dm_dreg_wr         ),
+    .dm_dreg_wdata          (dm_dreg_wdata      ),
+    .dm_dreg_resp           (dm_dreg_resp       ),
+    .dm_dreg_fail           (dm_dreg_fail       ),
+    .dm_dreg_rdata          (dm_dreg_rdata      ),
+    //
+    .dm_pc_sample           (dm_pc_sample       ),
+`endif // SCR1_DBGC_EN
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    .irq_lines              (irq_lines          ),
+`else // SCR1_IPIC_EN
+    .ext_irq                (ext_irq            ),
+`endif // SCR1_IPIC_EN
+    .soft_irq               (soft_irq           ),
+    .timer_irq              (timer_irq          ),
+    .mtime_ext              (mtime_ext          ),
+
+    // Fuse
+    .fuse_mhartid           (fuse_mhartid       )
+);
+
+
+`ifdef SCR1_DBGC_EN
+//-------------------------------------------------------------------------------
+// TAP Controller (TAPC)
+//-------------------------------------------------------------------------------
+scr1_tapc i_tapc (
+    // JTAG signals
+    .trst_n                 (tapc_rst_n),
+    .tck                    (tck),
+    .tms                    (tms),
+    .tdi                    (tdi),
+    .tdo                    (tdo),
+    .tdo_en                 (tdo_en),
+    // Fuses:
+    .fuse_idcode            (fuse_idcode),
+    // System Control/Status signals
+    .scu_ch_sel             (tapc_scu_ch_sel_tapout),
+    // DMI scan-chains
+    .dmi_ch_sel             (tapc_dmi_ch_sel_tapout),
+    .dmi_ch_id              (tapc_dmi_ch_id_tapout),
+    .dmi_ch_capture         (tapc_dmi_ch_capture_tapout),
+    .dmi_ch_shift           (tapc_dmi_ch_shift_tapout),
+    .dmi_ch_update          (tapc_dmi_ch_update_tapout),
+    .dmi_ch_tdi             (tapc_dmi_ch_tdi_tapout),
+    .dmi_ch_tdo             (tapc_dmi_ch_tdo_tapin)
+);
+
+scr1_tapc_synchronizer i_tapc_synchronizer (
+    // System common signals
+    .pwrup_rst_n            (pwrup_rst_n_sync),
+    .dm_rst_n               (dm_rst_n),
+    .clk                    (clk),
+
+    // JTAG common signals
+    .trst_n                 (tapc_rst_n),
+    .tck                    (tck),
+
+    // System Control/Status signals
+    .scu_ch_sel             (tapc_scu_ch_sel_tapout),
+    .scu_ch_sel_core        (tapc_scu_ch_sel),
+
+    // DMI scan-chains
+    .dmi_ch_sel             (tapc_dmi_ch_sel_tapout),
+    .dmi_ch_sel_core        (tapc_dmi_ch_sel),
+    .dmi_ch_id              (tapc_dmi_ch_id_tapout),
+    .dmi_ch_id_core         (tapc_dmi_ch_id),
+    .dmi_ch_capture         (tapc_dmi_ch_capture_tapout),
+    .dmi_ch_capture_core    (tapc_dmi_ch_capture),
+    .dmi_ch_shift           (tapc_dmi_ch_shift_tapout),
+    .dmi_ch_shift_core      (tapc_dmi_ch_shift),
+    .dmi_ch_update          (tapc_dmi_ch_update_tapout),
+    .dmi_ch_update_core     (tapc_dmi_ch_update),
+    .dmi_ch_tdi             (tapc_dmi_ch_tdi_tapout),
+    .dmi_ch_tdi_core        (tapc_dmi_ch_tdi),
+    .dmi_ch_tdo             (tapc_dmi_ch_tdo_tapin),
+    .dmi_ch_tdo_core        (tapc_ch_tdo)
+);
+assign tapc_ch_tdo = (tapc_scu_ch_tdo & tapc_scu_ch_sel) | (tapc_dmi_ch_tdo & tapc_dmi_ch_sel);
+
+scr1_dmi i_dmi (
+    .rst_n                  (dm_rst_n),
+    .clk                    (clk),
+
+    // TAP scan-chains
+    .dtm_ch_sel             (tapc_dmi_ch_sel),
+    .dtm_ch_id              (tapc_dmi_ch_id),
+    .dtm_ch_capture         (tapc_dmi_ch_capture),
+    .dtm_ch_shift           (tapc_dmi_ch_shift),
+    .dtm_ch_update          (tapc_dmi_ch_update),
+    .dtm_ch_tdi             (tapc_dmi_ch_tdi),
+    .dtm_ch_tdo             (tapc_dmi_ch_tdo),
+
+    // DMI
+    .dmi_resp               (dmi_resp),
+    .dmi_rdata              (dmi_rdata),
+    .dmi_req                (dmi_req),
+    .dmi_wr                 (dmi_wr),
+    .dmi_addr               (dmi_addr),
+    .dmi_wdata              (dmi_wdata)
+);
+`endif // SCR1_DBGC_EN
+
+
+`ifdef SCR1_DBGC_EN
+
+//-------------------------------------------------------------------------------
+// Debug Module (DM)
+//-------------------------------------------------------------------------------
+assign dm_cmd_resp_qlfy    = dm_cmd_resp   & {$bits(dm_cmd_resp){hdu_rst_n_qlfy}};
+assign dm_cmd_rcode_qlfy   = dm_cmd_rcode  & {$bits(dm_cmd_rcode){hdu_rst_n_qlfy}};
+assign dm_hart_event_qlfy  = dm_hart_event & {$bits(dm_hart_event){hdu_rst_n_qlfy}};
+assign dm_hart_status_qlfy = hdu_rst_n_qlfy ? dm_hart_status : '0;
+assign dm_pbuf_addr_qlfy   = dm_pbuf_addr  & {$bits(dm_pbuf_addr){hdu_rst_n_qlfy}};
+assign dm_dreg_req_qlfy    = dm_dreg_req   & {$bits(dm_dreg_req){hdu_rst_n_qlfy}};
+assign dm_dreg_wr_qlfy     = dm_dreg_wr    & {$bits(dm_dreg_wr){hdu_rst_n_qlfy}};
+assign dm_dreg_wdata_qlfy  = dm_dreg_wdata & {$bits(dm_dreg_wdata){hdu_rst_n_qlfy}};
+assign dm_pc_sample_qlfy   = dm_pc_sample  & {$bits(dm_pc_sample){core_rst_n_qlfy}};
+
+scr1_dm i_dm (
+    // Common signals
+    .rst_n                  (dm_rst_n),
+    .clk                    (clk),
+    // DM internal interface
+    .dmi_req                (dmi_req),
+    .dmi_wr                 (dmi_wr),
+    .dmi_addr               (dmi_addr),
+    .dmi_wdata              (dmi_wdata),
+    .dmi_resp               (dmi_resp),
+    .dmi_rdata              (dmi_rdata),
+    // DM <-> Pipeline: HART Run Control i/f
+    .ndm_rst_n              (ndm_rst_n),
+    .hart_rst_n             (hart_rst_n),
+    .hart_dmactive          (dm_active),
+    .hart_cmd_req           (dm_cmd_req),
+    .hart_cmd               (dm_cmd),
+    .hart_cmd_resp          (dm_cmd_resp_qlfy),
+    .hart_cmd_rcode         (dm_cmd_rcode_qlfy),
+    .hart_event             (dm_hart_event_qlfy),
+    .hart_status            (dm_hart_status_qlfy),
+    .ro_fuse_mhartid        (fuse_mhartid),
+    .ro_pc                  (dm_pc_sample_qlfy),
+
+    // DM <-> Pipeline: HART Abstract Command / Program Buffer i/f
+    .hart_pbuf_addr         (dm_pbuf_addr_qlfy),
+    .hart_pbuf_instr        (dm_pbuf_instr),
+
+    // DM <-> Pipeline: HART Abstract Data regs i/f
+    .hart_dreg_req          (dm_dreg_req_qlfy),
+    .hart_dreg_wr           (dm_dreg_wr_qlfy),
+    .hart_dreg_wdata        (dm_dreg_wdata_qlfy),
+    .hart_dreg_resp         (dm_dreg_resp),
+    .hart_dreg_fail         (dm_dreg_fail),
+    .hart_dreg_rdata        (dm_dreg_rdata)
+);
+`endif // SCR1_DBGC_EN
+
+
+`ifdef SCR1_CLKCTRL_EN
+//-------------------------------------------------------------------------------
+// Global clock gating logic
+//-------------------------------------------------------------------------------
+scr1_clk_ctrl i_clk_ctrl (
+    .clk                (clk            ),
+    .rst_n              (rst_n          ),
+    .test_mode          (test_mode      ),
+    // Sleep/wake interface
+    .sleep_pipe         (sleep_pipe     ),
+    .wake_pipe          (wake_pipe      ),
+    // Clocks
+    .clkout             (clk_alw_on     ),
+    .clkout_pipe        (clk_pipe       ),
+    .clk_pipe_en        (clk_pipe_en    ),
+    .clkout_dbgc        (clk_dbgc       )
+);
+`endif // SCR1_CLKCTRL_EN
+
+endmodule : scr1_core_top
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core/scr1_dm.sv b/third_party/tests/Scr1/src/core/scr1_dm.sv
new file mode 100644
index 0000000..badc7da
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/scr1_dm.sv
@@ -0,0 +1,1257 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_dm.sv>
+/// @brief      Debug Module (DM)
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_DBGC_EN
+`include "scr1_csr.svh"
+`include "scr1_dm.svh"
+
+module scr1_dm (
+    // System
+    input  logic                                            rst_n,          // DM reset
+    input  logic                                            clk,            // DM clock
+
+    // DM internal interface
+    input  logic                                            dmi_req,        // DMI request
+    input  logic                                            dmi_wr,         // DMI write
+    input  logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0]              dmi_addr,       // DMI address
+    input  logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]              dmi_wdata,      // DMI write data
+    output logic                                            dmi_resp,       // DMI response
+    output logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]              dmi_rdata,      // DMI read data
+
+    // HART Run Control i/f
+    output logic                                            ndm_rst_n,      // Non-DM Reset output
+    output logic                                            hart_rst_n,     // HART reset output
+    output logic                                            hart_dmactive,  // HART DM Active
+    output logic                                            hart_cmd_req,   // HART Command request
+    output type_scr1_hdu_dbgstates_e                        hart_cmd,       // HART Command
+    input  logic                                            hart_cmd_resp,  // HART Command response
+    input  logic                                            hart_cmd_rcode, // HART Command return code: 0 - Ok; 1 - Error
+    input  logic                                            hart_event,     // HART Event: 1 if HART debug state changed
+    input  type_scr1_hdu_hartstatus_s                       hart_status,    // HART Status
+
+    input  logic [`SCR1_XLEN-1:0]                           ro_fuse_mhartid,// RO MHARTID value
+    input  logic [`SCR1_XLEN-1:0]                           ro_pc,          // RO PC value for sampling
+
+    // HART Abstract Command / Program Buffer i/f
+    input  logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]             hart_pbuf_addr, // Program Buffer address - so far request only for 1 instruction
+    output logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0]            hart_pbuf_instr,// Program Buffer instruction
+
+    // HART Abstract Data regs i/f
+    input  logic                                            hart_dreg_req,  // Abstract Data Register request
+    input  logic                                            hart_dreg_wr,   // Abstract Data Register write
+    input  logic [`SCR1_XLEN-1:0]                           hart_dreg_wdata,// Abstract Data Register write data
+    output logic                                            hart_dreg_resp, // Abstract Data Register response
+    output logic                                            hart_dreg_fail, // Abstract Data Register fail - possibly not needed ?
+    output logic [`SCR1_XLEN-1:0]                           hart_dreg_rdata // Abstract Data Register read data
+);
+
+// DMCONTROL
+localparam      DMCONTROL_HARTRESET     = 1'd0;
+localparam      DMCONTROL_RESERVEDB     = 1'd0;
+localparam      DMCONTROL_HASEL         = 1'd0;
+localparam      DMCONTROL_HARTSELLO     = 1'd0;
+localparam      DMCONTROL_HARTSELHI     = 1'd0;
+localparam      DMCONTROL_RESERVEDA     = 1'd0;
+logic           dmcontrol_haltreq_ff;
+logic           dmcontrol_resumereq_ff;
+logic           dmcontrol_ackhavereset_ff;
+logic           dmcontrol_ndmreset_ff;
+logic           dmcontrol_dmactive_ff;
+
+// DMSTATUS
+localparam      DMSTATUS_RESERVEDC      = 1'd0;
+localparam      DMSTATUS_IMPEBREAK      = 1'd1;
+localparam      DMSTATUS_RESERVEDB      = 1'd0;
+localparam      DMSTATUS_ALLUNAVAIL     = 1'd0;
+localparam      DMSTATUS_ANYUNAVAIL     = 1'd0;
+localparam      DMSTATUS_ALLANYUNAVAIL  = 1'd0;
+localparam      DMSTATUS_ALLANYNONEXIST = 1'b0;
+localparam      DMSTATUS_AUTHENTICATED  = 1'd1;
+localparam      DMSTATUS_AUTHBUSY       = 1'd0;
+localparam      DMSTATUS_RESERVEDA      = 1'd0;
+localparam      DMSTATUS_DEVTREEVALID   = 1'd0;
+localparam      DMSTATUS_VERSION        = 2'd2;
+logic           dmstatus_allany_havereset_ff;
+logic           havereset_skip_pwrup_ff;
+logic           dmstatus_allany_resumeack_ff;
+logic           dmstatus_allany_running;
+logic           dmstatus_allany_halted_ff;
+
+// HARTINFO
+localparam      HARTINFO_RESERVEDB      = 1'd0;
+localparam      HARTINFO_NSCRATCH       = 4'd1;
+localparam      HARTINFO_RESERVEDA      = 1'd0;
+localparam      HARTINFO_DATAACCESS     = 1'd0;
+localparam      HARTINFO_DATASIZE       = 4'd1;
+localparam      HARTINFO_DATAADDR       = 12'h7b2;
+
+// ABSTRACTCS
+localparam      ABSTRACTCS_RESERVEDD    = 1'd0;
+localparam      ABSTRACTCS_PROGBUFSIZE  = 5'd6;
+localparam      ABSTRACTCS_RESERVEDC    = 1'd0;
+localparam      ABSTRACTCS_RESERVEDB    = 1'd0;
+localparam      ABSTRACTCS_RESERVEDA    = 1'd0;
+localparam      ABSTRACTCS_DATACOUNT    = 4'd2;
+
+logic           abstractcs_busy;
+
+logic[SCR1_DBG_ABSTRACTCS_CMDERR_HI-
+      SCR1_DBG_ABSTRACTCS_CMDERR_LO:0]
+                abstractcs_cmderr_ff;
+
+logic           abstractcs_ro_en;
+
+// ABSTRACTAUTO
+logic           abstractauto_execdata0_ff;
+
+logic [31:0]    data0_ff;
+logic [31:0]    data1_ff;
+
+logic [31:0]    command_ff;
+logic [31:0]    progbuf0_ff;
+logic [31:0]    progbuf1_ff;
+logic [31:0]    progbuf2_ff;
+logic [31:0]    progbuf3_ff;
+logic [31:0]    progbuf4_ff;
+logic [31:0]    progbuf5_ff;
+
+localparam      ABS_CMD_HARTREG         = 1'd0;
+localparam      ABS_CMD_HARTMEM         = 2'd2;
+localparam      ABS_CMD_HARTREG_CSR     = 4'b0000;
+localparam      ABS_CMD_HARTREG_INTFPU  = 4'b0001;
+localparam      ABS_CMD_HARTREG_INT     = 7'b000_0000;
+localparam      ABS_CMD_HARTREG_FPU     = 7'b000_0001;
+localparam      ABS_EXEC_EBREAK         = 32'b000000000001_00000_000_00000_1110011;
+
+localparam      ABS_ERR_BUSY            = 1'd1,
+                ABS_ERR_CMD             = 2'd2,
+                ABS_ERR_EXCEPTION       = 2'd3,
+                ABS_ERR_NOHALT          = 3'd4;
+
+logic           dmi_req_dmcontrol_cmb;
+logic           dmi_req_abstractcs_cmb;
+logic           dmi_req_abstractauto_cmb;
+logic           dmi_req_command_cmb;
+logic           dmi_rpt_command_cmb;
+logic           dmi_req_data0_cmb;
+logic           dmi_req_data1_cmb;
+
+logic           dmi_req_progbuf0_cmb;
+logic           dmi_req_progbuf1_cmb;
+logic           dmi_req_progbuf2_cmb;
+logic           dmi_req_progbuf3_cmb;
+logic           dmi_req_progbuf4_cmb;
+logic           dmi_req_progbuf5_cmb;
+
+enum logic [3:0] {
+    ABS_STATE_IDLE,
+    ABS_STATE_ERR,
+    ABS_STATE_EXEC,
+    ABS_STATE_XREG_RW,
+    ABS_STATE_MEM_SAVE_XREG,
+    ABS_STATE_MEM_SAVE_XREG_FORADDR,
+    ABS_STATE_MEM_RW,
+    ABS_STATE_MEM_RETURN_XREG,
+    ABS_STATE_MEM_RETURN_XREG_FORADDR,
+    ABS_STATE_CSR_RO,
+    ABS_STATE_CSR_SAVE_XREG,
+    ABS_STATE_CSR_RW,
+    ABS_STATE_CSR_RETURN_XREG
+    }           abs_fsm_cmb, abs_fsm_ff;
+
+logic           abs_exec_req_cmb;
+logic           abs_exec_req_ff;
+logic [31:0]    abs_exec_instr_cmb;
+logic [31:0]    abs_exec_instr_ff;
+
+logic [SCR1_DBG_COMMAND_TYPE_HI - SCR1_DBG_COMMAND_TYPE_LO:0]
+                abs_cmd_cmb;
+
+logic           abs_cmd_csr_ro_cmb;
+logic           abs_cmd_regacs_cmb;
+
+logic [SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI-12:0]
+                abs_cmd_regtype_cmb;
+
+logic [6:0]     abs_cmd_regfile_cmb;
+logic           abs_cmd_regwr_cmb;
+logic [11:0]    abs_cmd_regno_cmb;
+
+logic [ SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI -
+        SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO : 0 ]
+                abs_cmd_regsize_cmb;
+logic           abs_cmd_regsize_valid_cmb;
+logic           abs_cmd_regvalid_cmb;
+
+logic           abs_cmd_execprogbuf_cmb;
+logic           abs_cmd_memvalid_cmb;
+logic           abs_cmd_memwr_cmb;
+
+logic [2:0]     abs_cmd_memsize_cmb;
+logic           abs_cmd_memsize_valid_cmb;
+
+logic           abs_cmd_wr_ff;
+logic           abs_cmd_wr_cmb;
+logic           abs_cmd_postexec_ff;
+logic           abs_cmd_postexec_cmb;
+logic [1:0]     abs_cmd_size_ff;
+logic [1:0]     abs_cmd_size_cmb;
+logic [11:0]    abs_cmd_regno_ff;
+
+logic           abs_err_exception_cmb;
+logic           abs_err_exception_ff;
+logic           abs_err_acc_busy_cmb;
+logic           abs_err_acc_busy_ff;
+
+logic [31:0]    abs_data0_cmb;
+logic [31:0]    abs_data1_cmb;
+
+logic [31:0]    abs_command_cmb;
+logic           abs_abstractauto_execdata0_cmb;
+logic [31:0]    abs_progbuf0_cmb;
+logic [31:0]    abs_progbuf1_cmb;
+logic [31:0]    abs_progbuf2_cmb;
+logic [31:0]    abs_progbuf3_cmb;
+logic [31:0]    abs_progbuf4_cmb;
+logic [31:0]    abs_progbuf5_cmb;
+
+logic [SCR1_DBG_ABSTRACTCS_CMDERR_HI-SCR1_DBG_ABSTRACTCS_CMDERR_LO:0]
+                abs_cmderr_cmb;
+
+// Clock enable
+logic           clk_en_dm_cmb;
+logic           clk_en_dm_ff;
+
+// DHI
+enum logic [2:0] {
+    DHI_STATE_IDLE,
+    DHI_STATE_EXEC,
+    DHI_STATE_EXEC_RUN,
+    DHI_STATE_EXEC_HALT,
+    DHI_STATE_HALT_REQ,
+    DHI_STATE_RESUME_REQ,
+    DHI_STATE_RESUME_RUN
+    }           dhi_fsm_cmb, dhi_fsm_ff, dhi_req_cmb;
+
+logic                           dhi_resp_cmb;
+logic                           dhi_resp_exception_cmb;
+logic                           hart_pbuf_ebreak_ff;
+logic                           hart_pbuf_ebreak_cmb;
+logic                           hart_cmd_req_cmb;
+type_scr1_hdu_dbgstates_e   hart_cmd_cmb;
+
+// Debug Module Interface
+// ----------------------
+
+// Register access
+always_comb begin
+    dmi_req_dmcontrol_cmb  = dmi_req  &  dmi_addr == SCR1_DBG_DMCONTROL;
+    dmi_req_abstractcs_cmb = dmi_req  &  dmi_addr == SCR1_DBG_ABSTRACTCS;
+    dmi_req_abstractauto_cmb = dmi_req  &  dmi_addr == SCR1_DBG_ABSTRACTAUTO;
+    dmi_req_data0_cmb      = dmi_req  &  dmi_addr == SCR1_DBG_DATA0;
+    dmi_req_data1_cmb      = dmi_req  &  dmi_addr == SCR1_DBG_DATA1;
+
+    dmi_req_command_cmb    = (dmi_req  &  dmi_addr == SCR1_DBG_COMMAND);
+    dmi_rpt_command_cmb    = (abstractauto_execdata0_ff & dmi_req_data0_cmb);
+    dmi_req_progbuf0_cmb   = dmi_req  &  dmi_addr == SCR1_DBG_PROGBUF0;
+    dmi_req_progbuf1_cmb   = dmi_req  &  dmi_addr == SCR1_DBG_PROGBUF1;
+    dmi_req_progbuf2_cmb   = dmi_req  &  dmi_addr == SCR1_DBG_PROGBUF2;
+    dmi_req_progbuf3_cmb   = dmi_req  &  dmi_addr == SCR1_DBG_PROGBUF3;
+    dmi_req_progbuf4_cmb   = dmi_req  &  dmi_addr == SCR1_DBG_PROGBUF4;
+    dmi_req_progbuf5_cmb   = dmi_req  &  dmi_addr == SCR1_DBG_PROGBUF5;
+end
+
+// Register data multiplexor
+always_comb begin
+    dmi_rdata = 1'b0;
+
+    if( dmi_addr == SCR1_DBG_DMSTATUS ) begin
+        dmi_rdata[SCR1_DBG_DMSTATUS_RESERVEDC_HI:
+                  SCR1_DBG_DMSTATUS_RESERVEDC_LO]       = DMSTATUS_RESERVEDC;
+
+        dmi_rdata[SCR1_DBG_DMSTATUS_IMPEBREAK]          = DMSTATUS_IMPEBREAK;
+
+        dmi_rdata[SCR1_DBG_DMSTATUS_RESERVEDB_HI:
+                  SCR1_DBG_DMSTATUS_RESERVEDB_LO]       = DMSTATUS_RESERVEDB;
+
+        dmi_rdata[SCR1_DBG_DMSTATUS_ALLHAVERESET]       = dmstatus_allany_havereset_ff;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ANYHAVERESET]       = dmstatus_allany_havereset_ff;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ALLRESUMEACK]       = dmstatus_allany_resumeack_ff;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ANYRESUMEACK]       = dmstatus_allany_resumeack_ff;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ALLNONEXISTENT]     = DMSTATUS_ALLANYNONEXIST;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ANYNONEXISTENT]     = DMSTATUS_ALLANYNONEXIST;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ALLUNAVAIL]         = DMSTATUS_ALLANYUNAVAIL;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ANYUNAVAIL]         = DMSTATUS_ALLANYUNAVAIL;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ALLRUNNING]         = ~dmstatus_allany_halted_ff;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ANYRUNNING]         = ~dmstatus_allany_halted_ff;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ALLHALTED]          = dmstatus_allany_halted_ff;
+        dmi_rdata[SCR1_DBG_DMSTATUS_ANYHALTED]          = dmstatus_allany_halted_ff;
+        dmi_rdata[SCR1_DBG_DMSTATUS_AUTHENTICATED]      = DMSTATUS_AUTHENTICATED;
+        dmi_rdata[SCR1_DBG_DMSTATUS_AUTHBUSY]           = DMSTATUS_AUTHBUSY;
+        dmi_rdata[SCR1_DBG_DMSTATUS_RESERVEDA]          = DMSTATUS_RESERVEDA;
+        dmi_rdata[SCR1_DBG_DMSTATUS_DEVTREEVALID]       = DMSTATUS_DEVTREEVALID;
+
+        dmi_rdata[SCR1_DBG_DMSTATUS_VERSION_HI:
+                  SCR1_DBG_DMSTATUS_VERSION_LO]         = DMSTATUS_VERSION;;
+    end
+    if( dmi_addr == SCR1_DBG_DMCONTROL ) begin
+        dmi_rdata[SCR1_DBG_DMCONTROL_HALTREQ]           = dmcontrol_haltreq_ff;
+        dmi_rdata[SCR1_DBG_DMCONTROL_RESUMEREQ]         = dmcontrol_resumereq_ff;
+        dmi_rdata[SCR1_DBG_DMCONTROL_HARTRESET]         = DMCONTROL_HARTRESET;
+        dmi_rdata[SCR1_DBG_DMCONTROL_ACKHAVERESET]      = dmcontrol_ackhavereset_ff;
+        dmi_rdata[SCR1_DBG_DMCONTROL_RESERVEDB]         = DMCONTROL_RESERVEDB;
+        dmi_rdata[SCR1_DBG_DMCONTROL_HASEL]             = DMCONTROL_HASEL;
+
+        dmi_rdata[SCR1_DBG_DMCONTROL_HARTSELLO_HI:
+                  SCR1_DBG_DMCONTROL_HARTSELLO_LO]      = DMCONTROL_HARTSELLO;
+
+        dmi_rdata[SCR1_DBG_DMCONTROL_HARTSELHI_HI:
+                  SCR1_DBG_DMCONTROL_HARTSELHI_LO]      = DMCONTROL_HARTSELHI;
+
+        dmi_rdata[SCR1_DBG_DMCONTROL_RESERVEDA_HI:
+                  SCR1_DBG_DMCONTROL_RESERVEDA_LO]      = DMCONTROL_RESERVEDA;
+
+        dmi_rdata[SCR1_DBG_DMCONTROL_NDMRESET]          = dmcontrol_ndmreset_ff;
+        dmi_rdata[SCR1_DBG_DMCONTROL_DMACTIVE]          = dmcontrol_dmactive_ff;
+    end
+    if( dmi_addr == SCR1_DBG_ABSTRACTCS ) begin
+        dmi_rdata[SCR1_DBG_ABSTRACTCS_RESERVEDD_HI:
+                  SCR1_DBG_ABSTRACTCS_RESERVEDD_LO]     = ABSTRACTCS_RESERVEDD;
+
+        dmi_rdata[SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_HI:
+                  SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_LO]   = ABSTRACTCS_PROGBUFSIZE;
+
+        dmi_rdata[SCR1_DBG_ABSTRACTCS_RESERVEDC_HI:
+                  SCR1_DBG_ABSTRACTCS_RESERVEDC_LO]     = ABSTRACTCS_RESERVEDC;
+
+        dmi_rdata[SCR1_DBG_ABSTRACTCS_BUSY]             = abstractcs_busy;
+        dmi_rdata[SCR1_DBG_ABSTRACTCS_RESERVEDB]        = ABSTRACTCS_RESERVEDB;
+
+        dmi_rdata[SCR1_DBG_ABSTRACTCS_CMDERR_HI:
+                  SCR1_DBG_ABSTRACTCS_CMDERR_LO]        = abstractcs_cmderr_ff;
+
+        dmi_rdata[SCR1_DBG_ABSTRACTCS_RESERVEDA_HI:
+                  SCR1_DBG_ABSTRACTCS_RESERVEDA_LO]     = ABSTRACTCS_RESERVEDA;
+
+        dmi_rdata[SCR1_DBG_ABSTRACTCS_DATACOUNT_HI:
+                  SCR1_DBG_ABSTRACTCS_DATACOUNT_LO]     = ABSTRACTCS_DATACOUNT;
+        end
+    if( dmi_addr == SCR1_DBG_ABSTRACTAUTO ) begin
+        dmi_rdata[0] = abstractauto_execdata0_ff;
+    end
+    if( dmi_addr == SCR1_DBG_DATA0 ) begin
+        dmi_rdata = data0_ff;
+    end
+    if( dmi_addr == SCR1_DBG_DATA1 ) begin
+        dmi_rdata = data1_ff;
+    end
+
+    if( dmi_addr == SCR1_DBG_PROGBUF0 ) begin
+        dmi_rdata = progbuf0_ff;
+    end
+    if( dmi_addr == SCR1_DBG_PROGBUF1 ) begin
+        dmi_rdata = progbuf1_ff;
+    end
+    if( dmi_addr == SCR1_DBG_PROGBUF2 ) begin
+        dmi_rdata = progbuf2_ff;
+    end
+    if( dmi_addr == SCR1_DBG_PROGBUF3 ) begin
+        dmi_rdata = progbuf3_ff;
+    end
+    if( dmi_addr == SCR1_DBG_PROGBUF4 ) begin
+        dmi_rdata = progbuf4_ff;
+    end
+    if( dmi_addr == SCR1_DBG_PROGBUF5 ) begin
+        dmi_rdata = progbuf5_ff;
+    end
+    if( dmi_addr == SCR1_DBG_HARTINFO ) begin
+        dmi_rdata[SCR1_DBG_HARTINFO_RESERVEDB_HI:
+                  SCR1_DBG_HARTINFO_RESERVEDB_LO]       = HARTINFO_RESERVEDB;
+
+        dmi_rdata[SCR1_DBG_HARTINFO_NSCRATCH_HI:
+                  SCR1_DBG_HARTINFO_NSCRATCH_LO]        = HARTINFO_NSCRATCH;
+
+        dmi_rdata[SCR1_DBG_HARTINFO_RESERVEDA_HI:
+                  SCR1_DBG_HARTINFO_RESERVEDA_LO]       = HARTINFO_RESERVEDA;
+
+        dmi_rdata[SCR1_DBG_HARTINFO_DATAACCESS]         = HARTINFO_DATAACCESS;
+
+        dmi_rdata[SCR1_DBG_HARTINFO_DATASIZE_HI:
+                  SCR1_DBG_HARTINFO_DATASIZE_LO]        = HARTINFO_DATASIZE;
+
+        dmi_rdata[SCR1_DBG_HARTINFO_DATAADDR_HI:
+                  SCR1_DBG_HARTINFO_DATAADDR_LO]        = HARTINFO_DATAADDR;
+    end
+    if( dmi_addr == SCR1_DBG_HALTSUM0 ) begin
+        dmi_rdata[0] = dmstatus_allany_halted_ff;
+    end
+end
+
+// Response
+always_comb dmi_resp = 1'b1;
+
+// Clock enable and reset of Debug Module
+// --------------------------------------
+always_comb clk_en_dm_cmb = (dmi_req_dmcontrol_cmb & dmi_wr) |
+                             dmcontrol_dmactive_ff | clk_en_dm_ff;
+
+assign      hart_dmactive = clk_en_dm_ff;
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if( ~rst_n ) begin
+        dmcontrol_dmactive_ff <= 1'b0;
+        clk_en_dm_ff          <= 1'b0;
+    end else if( clk_en_dm_cmb ) begin
+        if( dmi_req_dmcontrol_cmb & dmi_wr ) begin
+            dmcontrol_dmactive_ff <= dmi_wdata[SCR1_DBG_DMCONTROL_DMACTIVE];
+        end
+        clk_en_dm_ff <= dmcontrol_dmactive_ff;
+    end
+end
+
+// Reset
+// -----
+
+// NotDM reset request
+always_ff @(posedge clk, negedge rst_n) begin
+    if( ~rst_n ) begin
+        dmcontrol_ndmreset_ff        <= 1'b0;
+        dmcontrol_ackhavereset_ff    <= 1'b0;
+    end else if( clk_en_dm_cmb ) begin
+        if( ~dmcontrol_dmactive_ff ) begin
+            dmcontrol_ndmreset_ff        <= 1'b0;
+            dmcontrol_ackhavereset_ff    <= 1'b0;
+        end else begin
+            if( dmi_req_dmcontrol_cmb & dmi_wr ) begin
+                dmcontrol_ndmreset_ff <= dmi_wdata[SCR1_DBG_DMCONTROL_NDMRESET];
+
+                // Clear sticky NotDM reset status
+                dmcontrol_ackhavereset_ff <= dmi_wdata[SCR1_DBG_DMCONTROL_ACKHAVERESET];
+            end
+        end
+    end
+end
+
+// NotDM reset status
+always_ff @(posedge clk, negedge rst_n) begin
+    if( ~rst_n ) begin
+        havereset_skip_pwrup_ff      <= 1'b1;
+        dmstatus_allany_havereset_ff <= 1'b0;
+    end else if( clk_en_dm_cmb ) begin
+        if( ~dmcontrol_dmactive_ff ) begin
+            havereset_skip_pwrup_ff      <= 1'b1;
+            dmstatus_allany_havereset_ff <= 1'b0;
+        end else begin
+            if( havereset_skip_pwrup_ff ) begin
+                havereset_skip_pwrup_ff <= hart_status.dbg_state == SCR1_HDU_DBGSTATE_RESET &
+                                           ndm_rst_n & hart_rst_n;
+            end
+
+            if( ~havereset_skip_pwrup_ff &
+                hart_status.dbg_state == SCR1_HDU_DBGSTATE_RESET ) begin
+
+                dmstatus_allany_havereset_ff <= 1'b1;
+            end else if( dmcontrol_ackhavereset_ff ) begin
+                dmstatus_allany_havereset_ff <= 1'b0;
+            end
+        end
+    end
+end
+
+// Reset signal for system controlled by Debug Module
+assign hart_rst_n  = ~dmcontrol_ndmreset_ff;
+assign ndm_rst_n   = ~dmcontrol_ndmreset_ff;
+
+// Hart select
+// -----------
+// Only one hart (index 0) is currently supported
+
+// Halt/Resume
+// -----------
+
+// Halt/Resume request
+always_ff @(posedge clk, negedge rst_n) begin
+    if( ~rst_n ) begin
+        dmcontrol_haltreq_ff         <= 1'd0;
+        dmcontrol_resumereq_ff       <= 1'd0;
+    end else if( clk_en_dm_cmb ) begin
+        if( ~dmcontrol_dmactive_ff ) begin
+            dmcontrol_haltreq_ff         <= 1'd0;
+            dmcontrol_resumereq_ff       <= 1'd0;
+        end else begin
+            if( dmi_req_dmcontrol_cmb & dmi_wr ) begin
+                dmcontrol_haltreq_ff   <= dmi_wdata[SCR1_DBG_DMCONTROL_HALTREQ];
+                dmcontrol_resumereq_ff <= dmi_wdata[SCR1_DBG_DMCONTROL_RESUMEREQ];
+            end
+        end
+    end
+end
+
+// Halt status
+always_ff @(posedge clk, negedge rst_n) begin
+    if( ~rst_n ) begin
+        dmstatus_allany_halted_ff <= 1'd0;
+    end else if( clk_en_dm_cmb ) begin
+        if( ~dmcontrol_dmactive_ff ) begin
+            dmstatus_allany_halted_ff <= 1'd0;
+        end else begin
+            if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_DHALTED ) begin
+                dmstatus_allany_halted_ff <= 1'b1;
+            end else if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_RUN ) begin
+                dmstatus_allany_halted_ff <= 1'b0;
+            end
+        end
+    end
+end
+
+// Resume status
+always_ff @(posedge clk, negedge rst_n) begin
+    if( ~rst_n ) begin
+        dmstatus_allany_resumeack_ff <= 1'd0;
+    end else if( clk_en_dm_cmb ) begin
+        if( ~dmcontrol_dmactive_ff ) begin
+            dmstatus_allany_resumeack_ff <= 1'd0;
+        end else begin
+            if( ~dmcontrol_resumereq_ff ) begin
+                dmstatus_allany_resumeack_ff <= 1'b0;
+            end else if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_RUN ) begin
+                dmstatus_allany_resumeack_ff <= 1'b1;
+            end
+        end
+    end
+end
+
+// Abstract Command
+// ----------------
+
+// Decode abstract command
+always_comb begin
+    if( dmi_req_command_cmb ) begin
+       abs_cmd_regno_cmb        =  dmi_wdata[SCR1_DBG_COMMAND_ACCESSREG_REGNO_LO +: 12];
+
+       abs_cmd_csr_ro_cmb       =  abs_cmd_regno_cmb == SCR1_CSR_ADDR_MISA |
+                                   abs_cmd_regno_cmb == SCR1_CSR_ADDR_MVENDORID |
+                                   abs_cmd_regno_cmb == SCR1_CSR_ADDR_MARCHID |
+                                   abs_cmd_regno_cmb == SCR1_CSR_ADDR_MIMPID |
+                                   abs_cmd_regno_cmb == SCR1_CSR_ADDR_MHARTID |
+                                   abs_cmd_regno_cmb == SCR1_HDU_DBGCSR_ADDR_DPC;
+
+        abs_cmd_cmb             = dmi_wdata[SCR1_DBG_COMMAND_TYPE_HI : SCR1_DBG_COMMAND_TYPE_LO];
+        abs_cmd_regacs_cmb      = dmi_wdata[SCR1_DBG_COMMAND_ACCESSREG_TRANSFER];
+        abs_cmd_regtype_cmb     = dmi_wdata[SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI:12];
+        abs_cmd_regfile_cmb     = dmi_wdata[11:5];
+        abs_cmd_regsize_cmb     = dmi_wdata[SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI : SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO];
+        abs_cmd_regwr_cmb       = dmi_wdata[SCR1_DBG_COMMAND_ACCESSREG_WRITE];
+        abs_cmd_execprogbuf_cmb = dmi_wdata[SCR1_DBG_COMMAND_ACCESSREG_POSTEXEC];
+
+        abs_cmd_regvalid_cmb    = dmi_wdata[SCR1_DBG_COMMAND_ACCESSREG_RESERVEDB] == 1'd0 &
+                                  dmi_wdata[SCR1_DBG_COMMAND_ACCESSREG_RESERVEDA] == 1'd0;
+
+        abs_cmd_memsize_cmb     = dmi_wdata[SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_HI : SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_LO];
+        abs_cmd_memwr_cmb       = dmi_wdata[SCR1_DBG_COMMAND_ACCESSMEM_WRITE];
+
+        abs_cmd_memvalid_cmb    = dmi_wdata[SCR1_DBG_COMMAND_ACCESSMEM_AAMVIRTUAL] == 1'd0 &
+                                  dmi_wdata[SCR1_DBG_COMMAND_ACCESSMEM_AAMPOSTINC] == 1'd0 &
+                                  dmi_wdata[SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI:SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI] == 1'd0 &
+                                  dmi_wdata[SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI:SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI] == 1'd0;
+    end else begin
+       abs_cmd_regno_cmb        =  command_ff[SCR1_DBG_COMMAND_ACCESSREG_REGNO_LO +: 12];
+
+       abs_cmd_csr_ro_cmb       =  abs_cmd_regno_cmb == SCR1_CSR_ADDR_MISA |
+                                   abs_cmd_regno_cmb == SCR1_CSR_ADDR_MVENDORID |
+                                   abs_cmd_regno_cmb == SCR1_CSR_ADDR_MARCHID |
+                                   abs_cmd_regno_cmb == SCR1_CSR_ADDR_MIMPID |
+                                   abs_cmd_regno_cmb == SCR1_CSR_ADDR_MHARTID |
+                                   abs_cmd_regno_cmb == SCR1_HDU_DBGCSR_ADDR_DPC;
+
+        abs_cmd_cmb             = command_ff[SCR1_DBG_COMMAND_TYPE_HI : SCR1_DBG_COMMAND_TYPE_LO];
+        abs_cmd_regacs_cmb      = command_ff[SCR1_DBG_COMMAND_ACCESSREG_TRANSFER];
+        abs_cmd_regtype_cmb     = command_ff[SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI:12];
+        abs_cmd_regfile_cmb     = command_ff[11:5];
+        abs_cmd_regsize_cmb     = command_ff[SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI : SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO];
+        abs_cmd_regwr_cmb       = command_ff[SCR1_DBG_COMMAND_ACCESSREG_WRITE];
+        abs_cmd_execprogbuf_cmb = command_ff[SCR1_DBG_COMMAND_ACCESSREG_POSTEXEC];
+
+        abs_cmd_regvalid_cmb    = command_ff[SCR1_DBG_COMMAND_ACCESSREG_RESERVEDB] == 1'd0 &
+                                  command_ff[SCR1_DBG_COMMAND_ACCESSREG_RESERVEDA] == 1'd0;
+
+        abs_cmd_memsize_cmb     = command_ff[SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_HI : SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_LO];
+        abs_cmd_memwr_cmb       = command_ff[SCR1_DBG_COMMAND_ACCESSMEM_WRITE];
+
+        abs_cmd_memvalid_cmb    = command_ff[SCR1_DBG_COMMAND_ACCESSMEM_AAMVIRTUAL] == 1'd0 &
+                                  command_ff[SCR1_DBG_COMMAND_ACCESSMEM_AAMPOSTINC] == 1'd0 &
+                                  command_ff[SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI:SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI] == 1'd0 &
+                                  command_ff[SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI:SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI] == 1'd0;
+    end
+end
+
+assign abs_cmd_regsize_valid_cmb =  abs_cmd_regsize_cmb == 2'd2;
+assign abs_cmd_memsize_valid_cmb = (abs_cmd_memsize_cmb <  3'd3) ? 1'b1 : 1'b0;
+
+
+// Detect error while abstract command processing
+always_comb begin
+    abs_err_exception_cmb = abs_fsm_ff != ABS_STATE_IDLE &
+                            dhi_resp_cmb & dhi_resp_exception_cmb ? 1'b1 :
+                            abs_fsm_ff == ABS_STATE_IDLE          ? 1'b0 :
+                                                                    abs_err_exception_ff;
+
+    abs_err_acc_busy_cmb = abs_fsm_ff != ABS_STATE_IDLE &
+                           ( dmi_req_command_cmb |
+                             dmi_rpt_command_cmb |
+                             dmi_req_abstractauto_cmb |
+                             dmi_req_data0_cmb   |
+                             dmi_req_data1_cmb   |
+                             dmi_req_progbuf0_cmb |
+                             dmi_req_progbuf1_cmb |
+                             dmi_req_progbuf2_cmb |
+                             dmi_req_progbuf3_cmb |
+                             dmi_req_progbuf4_cmb |
+                             dmi_req_progbuf5_cmb ) ? 1'b1 :
+                             abs_fsm_ff == ABS_STATE_IDLE ? 1'b0 :
+                                                            abs_err_acc_busy_ff;
+end
+
+// Abstract command fsm
+always_comb begin
+    abs_data0_cmb      = data0_ff;
+    abs_data1_cmb      = data1_ff;
+    abs_command_cmb    = command_ff;
+    abs_abstractauto_execdata0_cmb = abstractauto_execdata0_ff;
+    abs_progbuf0_cmb   = progbuf0_ff;
+    abs_progbuf1_cmb   = progbuf1_ff;
+    abs_progbuf2_cmb   = progbuf2_ff;
+    abs_progbuf3_cmb   = progbuf3_ff;
+    abs_progbuf4_cmb   = progbuf4_ff;
+    abs_progbuf5_cmb   = progbuf5_ff;
+    abs_cmderr_cmb     = abstractcs_cmderr_ff;
+    abs_cmd_wr_cmb     = 1'b0;
+    abs_cmd_postexec_cmb = 1'b0;
+    abs_cmd_size_cmb   = abs_cmd_size_ff;
+    abs_exec_req_cmb   = 1'b0;
+    abs_exec_instr_cmb = abs_exec_instr_ff;
+    abs_fsm_cmb        = abs_fsm_ff;
+    abstractcs_busy    = abs_fsm_ff != ABS_STATE_IDLE  &  abs_fsm_ff != ABS_STATE_ERR;
+
+    // Wait for command request
+    if( abs_fsm_ff == ABS_STATE_IDLE ) begin
+        if( dmi_req_data0_cmb & dmi_wr ) begin
+            abs_data0_cmb = dmi_wdata;
+        end
+        if( dmi_req_data1_cmb & dmi_wr ) begin
+            abs_data1_cmb = dmi_wdata;
+        end
+        if( dmi_req_command_cmb & dmi_wr ) begin
+            abs_command_cmb = dmi_wdata;
+        end
+        if( dmi_req_abstractauto_cmb & dmi_wr ) begin
+            abs_abstractauto_execdata0_cmb = dmi_wdata[0];
+        end
+        if( dmi_req_progbuf0_cmb & dmi_wr ) begin
+            abs_progbuf0_cmb = dmi_wdata;
+        end
+        if( dmi_req_progbuf1_cmb & dmi_wr ) begin
+            abs_progbuf1_cmb = dmi_wdata;
+        end
+        if( dmi_req_progbuf2_cmb & dmi_wr ) begin
+            abs_progbuf2_cmb = dmi_wdata;
+        end
+        if( dmi_req_progbuf3_cmb & dmi_wr ) begin
+            abs_progbuf3_cmb = dmi_wdata;
+        end
+        if( dmi_req_progbuf4_cmb & dmi_wr ) begin
+            abs_progbuf4_cmb = dmi_wdata;
+        end
+        if( dmi_req_progbuf5_cmb & dmi_wr ) begin
+            abs_progbuf5_cmb = dmi_wdata;
+        end
+
+        if( (dmi_req_command_cmb & dmi_wr) | dmi_rpt_command_cmb ) begin
+            // HART int/csr access or Program Buffer execute
+            if ( (abs_cmd_cmb == ABS_CMD_HARTREG) & abs_cmd_regvalid_cmb ) begin
+                // HART int/csr access
+                if( abs_cmd_regacs_cmb ) begin
+                    // HART csr access
+                    if( abs_cmd_regtype_cmb == ABS_CMD_HARTREG_CSR ) begin
+                        if( abs_cmd_regsize_valid_cmb ) begin
+                            if( abs_cmd_regwr_cmb ) begin
+                                if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_DHALTED ) begin
+                                    abs_cmd_wr_cmb       = 1'b1;
+                                    abs_cmd_postexec_cmb = abs_cmd_execprogbuf_cmb;
+                                    abs_fsm_cmb       = ABS_STATE_CSR_SAVE_XREG;
+                                end else begin
+                                    abs_cmderr_cmb = ABS_ERR_NOHALT;
+                                    abs_fsm_cmb    = ABS_STATE_ERR;
+                                end
+                            end else begin
+                                if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_RUN &
+                                    abs_cmd_csr_ro_cmb & ~abs_cmd_execprogbuf_cmb ) begin
+                                    abs_fsm_cmb  = ABS_STATE_CSR_RO;
+                                end else if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_DHALTED ) begin
+                                    abs_cmd_postexec_cmb = abs_cmd_execprogbuf_cmb;
+                                    abs_fsm_cmb = ABS_STATE_CSR_SAVE_XREG;
+                                end else begin
+                                    abs_cmderr_cmb = ABS_ERR_NOHALT;
+                                    abs_fsm_cmb    = ABS_STATE_ERR;
+                                end
+                            end
+                        end else begin
+                            abs_cmderr_cmb = ABS_ERR_CMD;
+                            abs_fsm_cmb    = ABS_STATE_ERR;
+                        end
+                    end
+                    // HART int/fpu regfile access
+                    else if( abs_cmd_regtype_cmb == ABS_CMD_HARTREG_INTFPU ) begin
+                        // HART int regfile access
+                        if( abs_cmd_regfile_cmb == ABS_CMD_HARTREG_INT ) begin
+                            if( abs_cmd_regsize_valid_cmb ) begin
+                                if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_DHALTED ) begin
+                                    abs_cmd_wr_cmb    = abs_cmd_regwr_cmb;
+                                    abs_cmd_size_cmb     = abs_cmd_regsize_cmb[1:0];
+                                    abs_cmd_postexec_cmb = abs_cmd_execprogbuf_cmb;
+                                    abs_fsm_cmb       = ABS_STATE_XREG_RW;
+                                end else begin
+                                    abs_cmderr_cmb = ABS_ERR_NOHALT;
+                                    abs_fsm_cmb    = ABS_STATE_ERR;
+                                end
+                            end else begin
+                                abs_cmderr_cmb = ABS_ERR_CMD;
+                                abs_fsm_cmb    = ABS_STATE_ERR;
+                            end
+                        end
+                        // Error command
+                        else begin
+                            abs_cmderr_cmb = ABS_ERR_CMD;
+                            abs_fsm_cmb    = ABS_STATE_ERR;
+                        end
+                    end
+                    // Error command
+                    else begin
+                        abs_cmderr_cmb = ABS_ERR_CMD;
+                        abs_fsm_cmb    = ABS_STATE_ERR;
+                    end
+                end
+                // Program buffer execute
+                else if( abs_cmd_execprogbuf_cmb ) begin
+                    abs_fsm_cmb = ABS_STATE_EXEC;
+                end
+                // Error command
+                else begin
+                    abs_cmderr_cmb = ABS_ERR_CMD;
+                    abs_fsm_cmb    = ABS_STATE_ERR;
+                end
+            end
+            // HART memory access
+            else if ( (abs_cmd_cmb == ABS_CMD_HARTMEM) & abs_cmd_memvalid_cmb ) begin
+                if( abs_cmd_memsize_valid_cmb ) begin
+                    if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_DHALTED ) begin
+                        abs_cmd_wr_cmb    = abs_cmd_memwr_cmb;
+                        abs_cmd_size_cmb  = abs_cmd_memsize_cmb[1:0];
+                        abs_fsm_cmb       = ABS_STATE_MEM_SAVE_XREG;
+                    end else begin
+                        abs_cmderr_cmb    = ABS_ERR_NOHALT;
+                        abs_fsm_cmb       = ABS_STATE_ERR;
+                    end
+                end else begin
+                    abs_cmderr_cmb = ABS_ERR_CMD;
+                    abs_fsm_cmb    = ABS_STATE_ERR;
+                end
+            end
+            // Error command
+            else begin
+                abs_cmderr_cmb = ABS_ERR_CMD;
+                abs_fsm_cmb    = ABS_STATE_ERR;
+            end
+        end
+    end
+
+    // Execute Program Buffer
+    else if( abs_fsm_ff == ABS_STATE_EXEC ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+
+        if( hart_dreg_req & hart_dreg_wr ) begin
+            abs_data0_cmb = hart_dreg_wdata;
+        end
+
+        if( dhi_resp_cmb ) begin
+            if( dhi_resp_exception_cmb ) begin
+                abs_cmderr_cmb = ABS_ERR_EXCEPTION;
+                abs_fsm_cmb    = ABS_STATE_ERR;
+            end else if( abs_err_acc_busy_ff ) begin
+                abs_cmderr_cmb = ABS_ERR_BUSY;
+                abs_fsm_cmb    = ABS_STATE_ERR;
+            end else begin
+                abs_fsm_cmb    = ABS_STATE_IDLE;
+            end
+        end
+    end
+
+    // Access to int regfile
+    else if( abs_fsm_ff == ABS_STATE_XREG_RW ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        abs_exec_instr_cmb = { SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+                               abs_cmd_wr_ff ? 5'd0 : abs_cmd_regno_ff[4:0],
+                               3'b001,
+                               abs_cmd_wr_ff ? abs_cmd_regno_ff[4:0] : 5'd0,
+                               7'b111_0011 };
+
+        if( hart_dreg_req & hart_dreg_wr & ~abs_cmd_wr_ff ) begin
+            abs_data0_cmb = hart_dreg_wdata;
+        end
+
+        if( dhi_resp_cmb ) begin
+            if( abs_err_acc_busy_ff ) begin
+                abs_cmderr_cmb = ABS_ERR_BUSY;
+                abs_fsm_cmb    = ABS_STATE_ERR;
+            end else if( abs_cmd_postexec_ff ) begin
+                abs_fsm_cmb    = ABS_STATE_EXEC;
+            end else begin
+                abs_fsm_cmb    = ABS_STATE_IDLE;
+            end
+        end
+    end
+
+    // Access to CSR
+    else if( abs_fsm_ff == ABS_STATE_CSR_RO ) begin
+        abs_data0_cmb = abs_cmd_regno_ff[11:0] == SCR1_CSR_ADDR_MISA       ? SCR1_CSR_MISA :
+                        abs_cmd_regno_ff[11:0] == SCR1_CSR_ADDR_MVENDORID  ? SCR1_CSR_MVENDORID :
+                        abs_cmd_regno_ff[11:0] == SCR1_CSR_ADDR_MARCHID    ? SCR1_CSR_MARCHID :
+                        abs_cmd_regno_ff[11:0] == SCR1_CSR_ADDR_MIMPID     ? SCR1_CSR_MIMPID :
+                        abs_cmd_regno_ff[11:0] == SCR1_CSR_ADDR_MHARTID    ? ro_fuse_mhartid :
+                                                                                 ro_pc;
+
+        if( abs_err_acc_busy_ff ) begin
+            abs_cmderr_cmb = ABS_ERR_BUSY;
+            abs_fsm_cmb    = ABS_STATE_ERR;
+        end else begin
+            abs_fsm_cmb    = ABS_STATE_IDLE;
+        end
+    end
+    else if( abs_fsm_ff == ABS_STATE_CSR_SAVE_XREG ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        abs_exec_instr_cmb = { SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+                               5'd5,
+                               3'b001,
+                               abs_cmd_wr_ff ? 5'd5 : 5'd0,
+                               7'b111_0011 };
+
+        if( hart_dreg_req & hart_dreg_wr ) begin
+            abs_data0_cmb = hart_dreg_wdata;
+        end
+
+        if( dhi_resp_cmb ) begin
+            abs_fsm_cmb    = ABS_STATE_CSR_RW;
+        end
+    end
+    else if( abs_fsm_ff == ABS_STATE_CSR_RW ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        abs_exec_instr_cmb = { abs_cmd_regno_ff[11:0],
+                               abs_cmd_wr_ff ? 5'd5 : 5'd0,
+                               abs_cmd_wr_ff ? 3'b001 : 3'b010,
+                               abs_cmd_wr_ff ? 5'd0 : 5'd5,
+                               7'b111_0011 };
+
+        if( dhi_resp_cmb ) begin
+            abs_fsm_cmb    = ABS_STATE_CSR_RETURN_XREG;
+        end
+    end
+    else if( abs_fsm_ff == ABS_STATE_CSR_RETURN_XREG ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        abs_exec_instr_cmb = { SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+    //                           abs_cmd_wr_ff ? 5'd0 : 5'd5,
+                               5'd5,
+                               3'b001,
+                               5'd5,
+                               7'b111_0011 };
+
+        if( hart_dreg_req & hart_dreg_wr ) begin
+            abs_data0_cmb = hart_dreg_wdata;
+        end
+
+        if( dhi_resp_cmb ) begin
+            if( abs_err_exception_ff ) begin
+                abs_cmderr_cmb = ABS_ERR_EXCEPTION;
+                abs_fsm_cmb    = ABS_STATE_ERR;
+            end else if( abs_err_acc_busy_ff ) begin
+                abs_cmderr_cmb = ABS_ERR_BUSY;
+                abs_fsm_cmb    = ABS_STATE_ERR;
+            end else if( abs_cmd_postexec_ff ) begin
+                abs_fsm_cmb    = ABS_STATE_EXEC;
+            end else begin
+                abs_fsm_cmb    = ABS_STATE_IDLE;
+            end
+        end
+    end
+
+    // Access to memory
+    else if( abs_fsm_ff == ABS_STATE_MEM_SAVE_XREG ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        abs_exec_instr_cmb = { SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+                               5'd5,
+                               3'b001,
+                               abs_cmd_wr_ff ? 5'd5 : 5'd0,
+                               7'b111_0011 };
+
+        if( hart_dreg_req & hart_dreg_wr ) begin
+            abs_data0_cmb = hart_dreg_wdata;
+        end
+
+        if( dhi_resp_cmb ) begin
+            abs_fsm_cmb = ABS_STATE_MEM_SAVE_XREG_FORADDR;
+        end
+    end
+    else if( abs_fsm_ff == ABS_STATE_MEM_SAVE_XREG_FORADDR ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        abs_exec_instr_cmb = { SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+                               5'd6,
+                               3'b001,
+                               5'd6,
+                               7'b111_0011 };
+
+        if( hart_dreg_req & hart_dreg_wr ) begin
+            abs_data1_cmb = hart_dreg_wdata;
+        end
+
+        if( dhi_resp_cmb ) begin
+            abs_fsm_cmb = ABS_STATE_MEM_RW;
+        end
+    end
+    else if( abs_fsm_ff == ABS_STATE_MEM_RW ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        if( abs_cmd_wr_ff ) begin
+            abs_exec_instr_cmb = { 7'd0,
+                                   5'd5,
+                                   5'd6,
+                                   {1'b0,abs_cmd_size_ff},
+                                   5'd0,
+                                   7'b010_0011 };
+        end else begin
+            abs_exec_instr_cmb = { 12'd0,
+                                   5'd6,
+                                   {abs_cmd_size_ff == 2'b10 ? 1'b0 : 1'b1,
+                                   abs_cmd_size_ff},
+                                   5'd5,
+                                   7'b000_0011 };
+        end
+
+        if( dhi_resp_cmb ) begin
+            abs_fsm_cmb = ABS_STATE_MEM_RETURN_XREG;
+        end
+    end
+    else if( abs_fsm_ff == ABS_STATE_MEM_RETURN_XREG ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        abs_exec_instr_cmb = { SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+                               5'd5,
+                               3'b001,
+                               5'd5,
+                               7'b111_0011 };
+
+        if( hart_dreg_req & hart_dreg_wr ) begin
+            abs_data0_cmb = hart_dreg_wdata;
+        end
+
+        if( dhi_resp_cmb ) begin
+            abs_fsm_cmb = ABS_STATE_MEM_RETURN_XREG_FORADDR;
+        end
+    end
+    else if( abs_fsm_ff == ABS_STATE_MEM_RETURN_XREG_FORADDR ) begin
+        abs_exec_req_cmb   = ~dhi_resp_cmb;
+        abs_exec_instr_cmb = { SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+                               5'd6,
+                               3'b001,
+                               5'd6,
+                               7'b111_0011 };
+
+        if( hart_dreg_req & hart_dreg_wr ) begin
+            abs_data1_cmb = hart_dreg_wdata;
+        end
+
+        if( dhi_resp_cmb ) begin
+            if( abs_err_exception_ff ) begin
+                abs_cmderr_cmb = ABS_ERR_EXCEPTION;
+                abs_fsm_cmb    = ABS_STATE_ERR;
+            end else if( abs_err_acc_busy_ff ) begin
+                abs_cmderr_cmb = ABS_ERR_BUSY;
+                abs_fsm_cmb    = ABS_STATE_ERR;
+            end else if( abs_cmd_postexec_ff ) begin
+                abs_fsm_cmb    = ABS_STATE_EXEC;
+            end else begin
+                abs_fsm_cmb    = ABS_STATE_IDLE;
+            end
+        end
+    end
+
+    // Wait for error state will be resolved
+    else if( abs_fsm_ff == ABS_STATE_ERR ) begin
+        if( dmi_req_abstractcs_cmb & dmi_wr ) begin
+
+            abs_cmderr_cmb  = abstractcs_cmderr_ff &
+                              (~dmi_wdata[SCR1_DBG_ABSTRACTCS_CMDERR_HI:
+                                          SCR1_DBG_ABSTRACTCS_CMDERR_LO]);
+
+            if( abs_cmderr_cmb == 1'b0 ) begin
+                abs_fsm_cmb = ABS_STATE_IDLE;
+            end
+        end
+    end
+
+    // Unexpected hart reset processing like exception
+    if( abs_fsm_ff != ABS_STATE_IDLE &
+        hart_status.dbg_state == SCR1_HDU_DBGSTATE_RESET ) begin
+
+        abs_cmderr_cmb = ABS_ERR_EXCEPTION;
+        abs_fsm_cmb    = ABS_STATE_ERR;
+    end
+end
+
+// Regs with init with dmcontrol_dmactive_ff=0
+always_ff @(posedge clk) begin
+    if( clk_en_dm_cmb ) begin
+        if( ~dmcontrol_dmactive_ff ) begin
+            abs_exec_req_ff      <= 1'd0;
+            abs_fsm_ff           <= ABS_STATE_IDLE;
+            abstractcs_cmderr_ff <= 1'd0;
+            abstractauto_execdata0_ff <= 1'b0;
+            command_ff           <= 1'b0;
+        end else begin
+            abs_exec_req_ff      <= abs_exec_req_cmb;
+            abs_fsm_ff           <= abs_fsm_cmb;
+            abstractcs_cmderr_ff <= abs_cmderr_cmb;
+            abstractauto_execdata0_ff <= abs_abstractauto_execdata0_cmb;
+            command_ff           <= abs_command_cmb;
+        end
+    end
+end
+
+// Regs without init when dmcontrol_dmactive_ff=0
+always_ff @(posedge clk) begin
+    if( clk_en_dm_cmb ) begin
+        if( dmcontrol_dmactive_ff ) begin
+            if( abs_fsm_ff == ABS_STATE_IDLE ) begin
+                abs_cmd_postexec_ff <= abs_cmd_postexec_cmb;
+                abs_cmd_wr_ff     <= abs_cmd_wr_cmb;
+                abs_cmd_regno_ff  <= abs_cmd_regno_cmb;
+                abs_cmd_size_ff   <= abs_cmd_size_cmb;
+            end
+            abs_err_exception_ff  <= abs_err_exception_cmb;
+            abs_err_acc_busy_ff   <= abs_err_acc_busy_cmb;
+
+            abs_exec_instr_ff     <= abs_exec_instr_cmb;
+            data0_ff              <= abs_data0_cmb;
+            data1_ff              <= abs_data1_cmb;
+
+            progbuf0_ff           <= abs_progbuf0_cmb;
+            progbuf1_ff           <= abs_progbuf1_cmb;
+            progbuf2_ff           <= abs_progbuf2_cmb;
+            progbuf3_ff           <= abs_progbuf3_cmb;
+            progbuf4_ff           <= abs_progbuf4_cmb;
+            progbuf5_ff           <= abs_progbuf5_cmb;
+        end
+    end
+end
+
+// Debug Hart Interface : control
+// ------------------------------
+
+// DHI fsm internal interface
+always_comb begin
+    // Request
+    dhi_req_cmb  = DHI_STATE_IDLE;
+    if( abs_exec_req_ff ) begin
+        dhi_req_cmb = DHI_STATE_EXEC;
+    end
+    if( dmcontrol_haltreq_ff &
+        hart_status.dbg_state != SCR1_HDU_DBGSTATE_DHALTED ) begin
+
+        dhi_req_cmb = DHI_STATE_HALT_REQ;
+    end
+    if( dmcontrol_resumereq_ff & ~dmstatus_allany_resumeack_ff &
+        hart_status.dbg_state == SCR1_HDU_DBGSTATE_DHALTED ) begin
+
+        dhi_req_cmb = DHI_STATE_RESUME_REQ;
+    end
+
+    // Response
+    dhi_resp_cmb           = dhi_fsm_ff == DHI_STATE_EXEC_HALT  &
+                             hart_status.dbg_state == SCR1_HDU_DBGSTATE_DHALTED;
+
+    dhi_resp_exception_cmb = hart_event & hart_status.except & ~hart_status.ebreak;
+end
+
+// DHI fsm
+always_comb begin
+    hart_cmd_req_cmb = 1'b0;
+    hart_cmd_cmb     = hart_cmd;
+    dhi_fsm_cmb      = dhi_fsm_ff;
+
+    // Wait for debug requests
+    if( dhi_fsm_ff == DHI_STATE_IDLE ) begin
+        dhi_fsm_cmb = dhi_req_cmb;
+    end
+
+    // Execute instruction in debug run
+    else if( dhi_fsm_ff == DHI_STATE_EXEC ) begin // Request for debug run
+            hart_cmd_req_cmb = ~(hart_cmd_resp & ~hart_cmd_rcode);
+            hart_cmd_cmb     = SCR1_HDU_DBGSTATE_DRUN;
+            if( hart_cmd_resp & ~hart_cmd_rcode ) begin
+                dhi_fsm_cmb = DHI_STATE_EXEC_RUN;
+            end
+        end
+    else if( dhi_fsm_ff == DHI_STATE_EXEC_RUN ) begin // Wait for debug run
+        if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_DRUN ) begin
+            dhi_fsm_cmb = DHI_STATE_EXEC_HALT;
+        end
+    end
+
+    // Halt
+    else if( dhi_fsm_ff == DHI_STATE_HALT_REQ ) begin // Request for halt hart
+            hart_cmd_req_cmb = ~(hart_cmd_resp & ~hart_cmd_rcode);
+            hart_cmd_cmb     = SCR1_HDU_DBGSTATE_DHALTED;
+
+            if( hart_cmd_resp & ~hart_cmd_rcode ) begin
+                dhi_fsm_cmb = DHI_STATE_EXEC_HALT;
+            end
+        end
+
+    // Wait for HART halt
+    else if( dhi_fsm_ff == DHI_STATE_EXEC_HALT ) begin
+        if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_DHALTED ) begin
+            dhi_fsm_cmb = DHI_STATE_IDLE;
+        end
+    end
+
+    // Resume
+    else if( dhi_fsm_ff == DHI_STATE_RESUME_REQ ) begin // Request for hart run
+            hart_cmd_req_cmb = ~(hart_cmd_resp & ~hart_cmd_rcode);
+            hart_cmd_cmb     = SCR1_HDU_DBGSTATE_RUN;
+
+            if( hart_cmd_resp & ~hart_cmd_rcode ) begin
+                dhi_fsm_cmb = DHI_STATE_RESUME_RUN;
+            end
+        end
+    else if( dhi_fsm_ff == DHI_STATE_RESUME_RUN ) begin // Wait for hart run
+        if( hart_status.dbg_state == SCR1_HDU_DBGSTATE_RUN ) begin
+            dhi_fsm_cmb = DHI_STATE_IDLE;
+        end
+    end
+
+    // Unexpected hart reset
+    if( dhi_fsm_ff != DHI_STATE_IDLE &
+        dhi_fsm_ff != DHI_STATE_HALT_REQ &
+        hart_status.dbg_state == SCR1_HDU_DBGSTATE_RESET ) begin
+
+        dhi_fsm_cmb = DHI_STATE_IDLE;
+    end
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if( ~rst_n ) begin
+        hart_cmd_req <= 1'd0;
+        hart_cmd     <= SCR1_HDU_DBGSTATE_RUN;
+
+        dhi_fsm_ff   <= DHI_STATE_IDLE;
+    end else if( clk_en_dm_cmb ) begin
+        if( ~dmcontrol_dmactive_ff ) begin
+            hart_cmd_req <= 1'd0;
+            hart_cmd     <= SCR1_HDU_DBGSTATE_RUN;
+
+            dhi_fsm_ff   <= DHI_STATE_IDLE;
+        end else begin
+            hart_cmd_req <= hart_cmd_req_cmb;
+            hart_cmd     <= hart_cmd_cmb;
+
+            dhi_fsm_ff   <= dhi_fsm_cmb;
+        end
+    end
+end
+
+// Debug Hart Interface : program buffer
+// -------------------------------------
+
+always_comb begin
+    hart_pbuf_instr = ABS_EXEC_EBREAK;
+
+    if( abs_fsm_ff == ABS_STATE_EXEC & ~hart_pbuf_ebreak_ff ) begin
+        if( hart_pbuf_addr == 1'd0 ) hart_pbuf_instr = progbuf0_ff;
+        if( hart_pbuf_addr == 1'd1 ) hart_pbuf_instr = progbuf1_ff;
+        if( hart_pbuf_addr == 2'd2 ) hart_pbuf_instr = progbuf2_ff;
+        if( hart_pbuf_addr == 2'd3 ) hart_pbuf_instr = progbuf3_ff;
+        if( hart_pbuf_addr == 3'd4 ) hart_pbuf_instr = progbuf4_ff;
+        if( hart_pbuf_addr == 3'd5 ) hart_pbuf_instr = progbuf5_ff;
+    end else if( hart_pbuf_addr == 1'b0 ) hart_pbuf_instr = abs_exec_instr_ff;
+end
+
+// Latch EBREAK condition when program buffer execution
+always_ff @(posedge clk) begin
+    if( clk_en_dm_cmb ) begin
+        hart_pbuf_ebreak_ff <= abs_fsm_ff == ABS_STATE_EXEC &
+                               hart_pbuf_instr == ABS_EXEC_EBREAK;
+    end
+end
+
+// Debug Hart Interface : abstract command data
+// --------------------------------------------
+
+always_comb hart_dreg_resp     = 1'b1;
+always_comb hart_dreg_fail     = 1'b0;
+always_comb hart_dreg_rdata    = abs_fsm_ff == ABS_STATE_MEM_SAVE_XREG_FORADDR |
+                                 abs_fsm_ff == ABS_STATE_MEM_RETURN_XREG_FORADDR ? data1_ff : data0_ff;
+
+// pragma synthesis_off
+// synopsys translate_off
+
+// Assertions
+// ----------
+`ifndef VERILATOR
+SVA_DM_X_CONTROL :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown( {rst_n,clk,dmi_req,hart_dreg_req,hart_cmd_resp,hart_event} )
+    )
+    else $error("DM error: control signals is X - %0b",{rst_n,clk,dmi_req,hart_dreg_req,hart_cmd_resp,hart_event});
+
+SVA_DM_X_DMI :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        dmi_req |-> !$isunknown( {dmi_wr,dmi_addr,dmi_wdata} )
+    )
+    else $error("DM error: data signals is X on dmi");
+
+SVA_DM_X_HART_PBUF :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown( hart_pbuf_addr )
+    )
+    else $error("DM error: data signals is X on hart_pbuf");
+
+SVA_DM_X_HART_DREG :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        hart_dreg_req |-> !$isunknown( {hart_dreg_wr,hart_dreg_wdata} )
+    )
+    else $error("DM error: data signals is X on hart_dreg");
+
+SVA_DM_X_HART_CMD :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        hart_cmd_resp |-> !$isunknown( {hart_cmd_rcode} )
+    )
+    else $error("DM error: data signals is X on hart_cmd");
+
+SVA_DM_X_HART_EVENT :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        hart_event |-> !$isunknown( hart_status )
+    )
+    else $error("DM error: data signals is X on hart_event");
+`endif // ! VERILATOR
+// synopsys translate_on
+// pragma synthesis_on
+
+endmodule : scr1_dm
+
+`endif // SCR1_DBGC_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core/scr1_dmi.sv b/third_party/tests/Scr1/src/core/scr1_dmi.sv
new file mode 100644
index 0000000..887fb95
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/scr1_dmi.sv
@@ -0,0 +1,162 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_dmi.sv>
+/// @brief      Debug Module Interface (DMI)
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_DBGC_EN
+`include "scr1_dm.svh"
+
+module scr1_dmi (
+    // System
+    input  logic                                    rst_n,          // DMI unit reset
+    input  logic                                    clk,            // DMI unit clock
+
+    // TAP interface
+    input  logic                                    dtm_ch_sel,     // Debug Transport Module Chain Select
+    input  logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]     dtm_ch_id,      // Debug Transport Module Chain ID
+    input  logic                                    dtm_ch_capture, // Debug Transport Module Chain Capture
+    input  logic                                    dtm_ch_shift,   // Debug Transport Module Chain Shift
+    input  logic                                    dtm_ch_update,  // Debug Transport Module Chain Update
+    input  logic                                    dtm_ch_tdi,     // Debug Transport Module Chain TDI
+    output logic                                    dtm_ch_tdo,     // Debug Transport Module Chain TDO
+
+    // DM interface
+    input logic                                     dmi_resp,       // DMI response
+    input logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]       dmi_rdata,      // DMI read data
+
+    output logic                                    dmi_req,        // DMI request
+    output logic                                    dmi_wr,         // DMI write
+    output logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0]      dmi_addr,       // DMI address
+    output logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]      dmi_wdata       // DMI write data
+
+);
+
+// DTMS
+localparam                                          DTMCS_RESERVEDB_HI = 5'd31;
+localparam                                          DTMCS_RESERVEDB_LO = 5'd18;
+localparam                                          DTMCS_DMIHARDRESET = 5'd17;
+localparam                                          DTMCS_DMIRESET     = 5'd16;
+localparam                                          DTMCS_RESERVEDA    = 5'd15;
+localparam                                          DTMCS_IDLE_HI      = 5'd14;
+localparam                                          DTMCS_IDLE_LO      = 5'd12;
+localparam                                          DTMCS_DMISTAT_HI   = 5'd11;
+localparam                                          DTMCS_DMISTAT_LO   = 5'd10;
+localparam                                          DTMCS_ABITS_HI     = 5'd9;
+localparam                                          DTMCS_ABITS_LO     = 5'd4;
+localparam                                          DTMCS_VERSION_HI   = 5'd3;
+localparam                                          DTMCS_VERSION_LO   = 5'd0;
+logic                                               dtmcs_dmihardreset_cmb;
+logic                                               dtmcs_dmireset_cmb;
+
+// DMI
+localparam                                          DMI_OP_LO   = 5'd0;
+localparam                                          DMI_OP_HI   = DMI_OP_LO + SCR1_DBG_DMI_OP_WIDTH - 1;
+localparam                                          DMI_DATA_LO = DMI_OP_HI + 1;
+localparam                                          DMI_DATA_HI = DMI_DATA_LO + SCR1_DBG_DMI_DATA_WIDTH - 1;
+localparam                                          DMI_ADDR_LO = DMI_DATA_HI + 1;
+localparam                                          DMI_ADDR_HI = DMI_ADDR_LO + SCR1_DBG_DMI_ADDR_WIDTH - 1;
+
+logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]                 dmi_rdata_ff;
+
+// TAP
+logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0]        tap_dr_shift_cmb;
+logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0]        tap_dr_rdata_cmb;
+logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0]        tap_dr_ff;
+
+// Clock enable
+logic                                               clk_en_dmi_rdata_cmb;
+logic                                               clk_en_tap_dr_cmb;
+
+// TAP interface
+// -------------
+
+always_comb dtm_ch_tdo = tap_dr_ff[0];
+
+always_comb begin
+    tap_dr_rdata_cmb = 1'b0;
+    tap_dr_shift_cmb = 1'b0;
+
+    if( dtm_ch_id == 1'd1 ) begin
+        tap_dr_rdata_cmb[ DTMCS_RESERVEDB_HI : DTMCS_RESERVEDB_LO ] = 1'b0;
+        tap_dr_rdata_cmb[ DTMCS_DMIHARDRESET ]                      = 1'b0;
+        tap_dr_rdata_cmb[ DTMCS_DMIRESET ]                          = 1'b0;
+        tap_dr_rdata_cmb[ DTMCS_RESERVEDA ]                         = 1'b0;
+        tap_dr_rdata_cmb[ DTMCS_IDLE_HI    : DTMCS_IDLE_LO ]        = 1'b0;
+        // Status of dmi operation is always success because of current DM implementation
+        tap_dr_rdata_cmb[ DTMCS_DMISTAT_HI : DTMCS_DMISTAT_LO ]     = 1'b0;
+        tap_dr_rdata_cmb[ DTMCS_ABITS_HI   : DTMCS_ABITS_LO ]       = SCR1_DBG_DMI_ADDR_WIDTH;
+        tap_dr_rdata_cmb[ DTMCS_VERSION_LO : DTMCS_VERSION_LO ]     = 1'b1;
+
+        tap_dr_shift_cmb =  { dtm_ch_tdi,
+                              tap_dr_ff[SCR1_DBG_DMI_DR_DTMCS_WIDTH-1:1] };
+    end else begin
+        tap_dr_rdata_cmb[ DMI_ADDR_HI : DMI_ADDR_LO ] = 1'b0;
+        tap_dr_rdata_cmb[ DMI_DATA_HI : DMI_DATA_LO ] = dmi_rdata_ff;
+        // Status of dmi operation is always success because of current DM implementation
+        tap_dr_rdata_cmb[ DMI_OP_HI   : DMI_OP_LO ]   = 1'b0;
+
+        tap_dr_shift_cmb =  { dtm_ch_tdi,
+                              tap_dr_ff[SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:1] };
+    end
+end
+
+// Clock enable logic
+always_comb begin
+    clk_en_tap_dr_cmb = dtm_ch_capture | dtm_ch_shift;
+end
+
+// TAP data register
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        tap_dr_ff <= '0;
+    end
+    else begin
+        if( clk_en_tap_dr_cmb ) begin
+            if( dtm_ch_capture ) begin
+                tap_dr_ff <= tap_dr_rdata_cmb;
+            end else if( dtm_ch_shift ) begin
+                tap_dr_ff <= tap_dr_shift_cmb;
+            end
+        end
+    end
+end
+
+// DM interface
+// ------------
+
+always_comb begin
+    dmi_req           = 1'b0;
+    dmi_wr            = 1'b0;
+    dmi_addr          = 1'b0;
+    dmi_wdata         = 1'b0;
+    
+    if( dtm_ch_update & dtm_ch_sel  &  dtm_ch_id == 2'd2 ) begin
+        dmi_req           = tap_dr_ff[ DMI_OP_HI   : DMI_OP_LO ] != 2'b00;
+        dmi_wr            = tap_dr_ff[ DMI_OP_HI   : DMI_OP_LO ] == 2'b10;
+        dmi_addr          = tap_dr_ff[DMI_ADDR_HI : DMI_ADDR_LO];
+        dmi_wdata         = tap_dr_ff[DMI_DATA_HI : DMI_DATA_LO];
+    end
+end
+
+// Clock enable logic
+always_comb begin
+    clk_en_dmi_rdata_cmb = dmi_req & dmi_resp & ~dmi_wr;
+end
+
+// DMI readed data storage
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        dmi_rdata_ff <= '0;
+    end
+    else begin
+        if( clk_en_dmi_rdata_cmb ) begin
+            dmi_rdata_ff <= dmi_rdata;
+        end
+    end
+end
+
+endmodule : scr1_dmi
+
+`endif // SCR1_DBGC_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core/scr1_scu.sv b/third_party/tests/Scr1/src/core/scr1_scu.sv
new file mode 100644
index 0000000..64d8183
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/scr1_scu.sv
@@ -0,0 +1,418 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file <scr1_scu.sv>
+/// @brief System Control Unit (SCU)
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_DBGC_EN
+
+module scr1_scu #(
+    parameter bit SCR1_SCU_CFG_RESET_INPUTS_SYNC    = 1 // Reset inputs are: 1 - synchronous, 0 -asynchronous
+) (
+    // Global signals
+    input  logic                                      pwrup_rst_n,      // Power-Up Reset
+    input  logic                                      rst_n,            // Regular Reset
+    input  logic                                      cpu_rst_n,        // CPU Reset
+    input  logic                                      test_mode,        // DFT Test Mode
+    input  logic                                      test_rst_n,       // DFT Test Reset
+    input  logic                                      clk,              // SCU clock
+    // TAPC scan-chains
+    input  logic                                      tapc_ch_sel,      // TAPC Chain Select
+    input  logic                                      tapc_ch_id,       // TAPC Chain ID
+    input  logic                                      tapc_ch_capture,  // TAPC Chain Capture
+    input  logic                                      tapc_ch_shift,    // TAPC Chain Shift
+    input  logic                                      tapc_ch_update,   // TAPC Chain Update
+    input  logic                                      tapc_ch_tdi,      // TAPC Chain TDI
+    output logic                                      tapc_ch_tdo,      // TAPC Chain TDO
+    // Input sync resets:
+    input  logic                                      ndm_rst_n,        // Non-DM Reset input from DM
+    input  logic                                      hart_rst_n,       // HART Reset from DM
+    // Generated resets and their attributes (qualifiers etc):
+    output logic                                      core_rst_n,       // Core Reset
+    output logic                                      core_rst_n_qlfy,  // Core Reset Qualifier
+    output logic                                      dm_rst_n,         // Debug Module Reset
+    output logic                                      hdu_rst_n,        // HART Debug Unit Reset
+    output logic                                      hdu_rst_n_qlfy    // HDU Reset Qualifier
+);
+
+//======================================================================================================================
+// Local Parameters
+//======================================================================================================================
+localparam int unsigned SCR1_SCU_DR_SYSCTRL_OP_WIDTH    = 2;
+localparam int unsigned SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH  = 2;
+localparam int unsigned SCR1_SCU_DR_SYSCTRL_DATA_WIDTH  = 4;
+
+//======================================================================================================================
+// Local Types
+//======================================================================================================================
+typedef enum logic [SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1:0] {
+    SCR1_SCU_SYSCTRL_OP_WRITE       = 2'h0,
+    SCR1_SCU_SYSCTRL_OP_READ        = 2'h1,
+    SCR1_SCU_SYSCTRL_OP_SETBITS     = 2'h2,
+    SCR1_SCU_SYSCTRL_OP_CLRBITS     = 2'h3,
+    SCR1_SCU_SYSCTRL_OP_XXX         = 'X
+} type_scr1_scu_sysctrl_op_e;
+
+typedef enum logic [SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH-1:0] {
+    SCR1_SCU_SYSCTRL_ADDR_CONTROL   = 2'h0,
+    SCR1_SCU_SYSCTRL_ADDR_MODE      = 2'h1,
+    SCR1_SCU_SYSCTRL_ADDR_STATUS    = 2'h2,
+    SCR1_SCU_SYSCTRL_ADDR_STICKY    = 2'h3,
+    SCR1_SCU_SYSCTRL_ADDR_XXX       = 'X
+} type_scr1_scu_sysctrl_addr_e;
+
+typedef struct packed {
+    logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0]  data;
+    logic [SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH-1:0]  addr;
+    logic [SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1:0]    op;
+} type_scr1_scu_sysctrl_dr_s;
+
+typedef struct packed {
+    logic [2:0]                                     rsrv;
+    logic                                           sys_reset;
+} type_scr1_scu_sysctrl_control_reg_s;
+
+typedef struct packed {
+    logic [1:0]                                     rsrv;
+    logic                                           hdu_rst_mux;
+    logic                                           dm_rst_mux;
+} type_scr1_scu_sysctrl_mode_reg_s;
+
+typedef struct packed {
+    logic                                           hdu_reset;
+    logic                                           dm_reset;
+    logic                                           core_reset;
+    logic                                           sys_reset;
+} type_scr1_scu_sysctrl_status_reg_s;
+
+//======================================================================================================================
+// Local Signals
+//======================================================================================================================
+
+type_scr1_scu_sysctrl_dr_s                          shift_reg;
+type_scr1_scu_sysctrl_dr_s                          shadow_reg;
+logic                                               dr_capture;
+logic                                               dr_shift;
+logic                                               dr_update;
+logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0]          cmd_data;
+logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0]          reg_data;
+//
+type_scr1_scu_sysctrl_control_reg_s                 control_reg;
+logic                                               control_reg_wr;
+type_scr1_scu_sysctrl_mode_reg_s                    mode_reg;
+type_scr1_scu_sysctrl_mode_reg_s                    mode_reg_r;
+logic                                               mode_reg_wr;
+logic                                               mode_reg_wr_r;
+type_scr1_scu_sysctrl_status_reg_s                  status_reg_data;
+type_scr1_scu_sysctrl_status_reg_s                  status_reg_data_dly;
+type_scr1_scu_sysctrl_status_reg_s                  status_reg_data_posedge;
+type_scr1_scu_sysctrl_status_reg_s                  sticky_sts_reg;
+logic                                               sticky_sts_reg_wr;
+//
+logic                                               pwrup_rst_n_sync;
+logic                                               rst_n_sync;
+logic                                               cpu_rst_n_sync;
+//
+logic                                               sys_rst_n;
+logic                                               sys_rst_n_sync;
+logic                                               sys_rst_n_qlfy;
+logic                                               sys_rst_n_status;
+//
+logic                                               dm_rst_n_sync;
+logic                                               dm_rst_n_qlfy;
+logic                                               dm_rst_n_status;
+//
+logic                                               core_rst_n_sync;
+logic                                               core_rst_n_qlfy_sync;
+logic                                               core_rst_n_status;
+//
+logic                                               hdu_rst_n_sync;
+logic                                               hdu_rst_n_status;
+
+
+//======================================================================================================================
+// Logic
+//======================================================================================================================
+
+// -----------------------------------------------------------------------------
+// Scan-chain i/f
+// -----------------------------------------------------------------------------
+assign dr_capture = tapc_ch_sel & (tapc_ch_id == '0) & tapc_ch_capture;
+assign dr_shift   = tapc_ch_sel & (tapc_ch_id == '0) & tapc_ch_shift;
+assign dr_update  = tapc_ch_sel & (tapc_ch_id == '0) & tapc_ch_update;
+
+always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
+    if (~pwrup_rst_n_sync) begin
+        shift_reg   <= '0;
+    end
+    else begin
+        if (dr_capture)
+            shift_reg <= shadow_reg;
+        else if(dr_shift)
+            shift_reg <= {tapc_ch_tdi, shift_reg[$bits(type_scr1_scu_sysctrl_dr_s)-1:1]};
+    end
+end
+
+always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
+    if (~pwrup_rst_n_sync) begin
+        shadow_reg   <= '0;
+    end
+    else begin
+        if (dr_update) begin
+            shadow_reg.op   <= shift_reg.op;
+            shadow_reg.addr <= shift_reg.addr;
+            shadow_reg.data <= cmd_data;
+        end
+    end
+end
+
+always_comb
+begin
+    cmd_data = '0;
+
+    if (dr_update) begin
+        case (shift_reg.op)
+            SCR1_SCU_SYSCTRL_OP_WRITE : begin
+                cmd_data = shift_reg.data;
+            end
+            SCR1_SCU_SYSCTRL_OP_READ : begin
+                cmd_data = reg_data;
+            end
+            SCR1_SCU_SYSCTRL_OP_SETBITS : begin
+                cmd_data = reg_data |   shift_reg.data;
+            end
+            SCR1_SCU_SYSCTRL_OP_CLRBITS : begin
+                cmd_data = reg_data & (~shift_reg.data);
+            end
+            default: begin
+            end
+        endcase
+    end
+end
+
+assign tapc_ch_tdo = shift_reg[0];
+
+// -----------------------------------------------------------------------------
+// Registers
+// -----------------------------------------------------------------------------
+always_comb
+begin
+    control_reg_wr      = 1'b0;
+    mode_reg_wr         = 1'b0;
+    sticky_sts_reg_wr   = 1'b0;
+
+    if (dr_update && (shift_reg.op != SCR1_SCU_SYSCTRL_OP_READ)) begin
+        case (shift_reg.addr)
+            SCR1_SCU_SYSCTRL_ADDR_CONTROL : begin
+                control_reg_wr      = 1'b1;
+            end
+            SCR1_SCU_SYSCTRL_ADDR_MODE : begin
+                mode_reg_wr         = 1'b1;
+            end
+            SCR1_SCU_SYSCTRL_ADDR_STICKY : begin
+                sticky_sts_reg_wr   = (shift_reg.op == SCR1_SCU_SYSCTRL_OP_CLRBITS) ? 1'b1 : 1'b0;
+            end
+            default: begin
+            end
+        endcase
+    end
+end
+
+always_comb
+begin
+    reg_data = '0;
+
+    if (dr_update) begin
+        case (shift_reg.addr)
+            SCR1_SCU_SYSCTRL_ADDR_CONTROL : begin
+                reg_data = control_reg;
+            end
+            SCR1_SCU_SYSCTRL_ADDR_MODE : begin
+                reg_data = mode_reg;
+            end
+            SCR1_SCU_SYSCTRL_ADDR_STATUS : begin
+                reg_data = status_reg_data;
+            end
+            SCR1_SCU_SYSCTRL_ADDR_STICKY : begin
+                reg_data = sticky_sts_reg;
+            end
+            default: begin
+                reg_data = 'x;
+            end
+        endcase
+    end
+end
+
+// Control Register
+always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
+    if (~pwrup_rst_n_sync) begin
+        control_reg <= '0;
+    end
+    else begin
+        if (control_reg_wr) begin
+            control_reg <= cmd_data;
+        end
+    end
+end
+
+// Mode Register
+always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
+    if (~pwrup_rst_n_sync) begin
+        mode_reg      <= '0;
+        mode_reg_r    <= '0;
+        mode_reg_wr_r <= '0;
+    end
+    else begin
+        if (mode_reg_wr) begin
+            mode_reg <= cmd_data;
+        end
+        mode_reg_wr_r <= mode_reg_wr;
+        if (mode_reg_wr_r) begin
+            mode_reg_r <= mode_reg;
+        end
+    end
+end
+
+// Status Register
+assign status_reg_data.sys_reset    = ~sys_rst_n_status ;
+assign status_reg_data.core_reset   = ~core_rst_n_status;
+assign status_reg_data.dm_reset     = ~dm_rst_n_status  ;
+assign status_reg_data.hdu_reset    = ~hdu_rst_n_status ;
+
+always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
+    if (~pwrup_rst_n_sync) begin
+        status_reg_data_dly <= '0;
+    end
+    else begin
+        status_reg_data_dly <= status_reg_data;
+    end
+end
+
+assign status_reg_data_posedge = status_reg_data & (~status_reg_data_dly);
+
+// Sticky Status Register
+always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
+    if (~pwrup_rst_n_sync) begin
+        sticky_sts_reg <= '0;
+    end
+    else begin
+        for (int unsigned i = 0; i < $bits(type_scr1_scu_sysctrl_status_reg_s); ++i) begin
+            if (status_reg_data_posedge[i]) begin
+                sticky_sts_reg[i] <= 1'b1;
+            end
+            else if (sticky_sts_reg_wr) begin
+                sticky_sts_reg[i] <= cmd_data[i];
+            end
+        end
+    end
+end
+
+// -----------------------------------------------------------------------------
+// Reset logic
+// -----------------------------------------------------------------------------
+generate
+
+if (SCR1_SCU_CFG_RESET_INPUTS_SYNC)
+// reset inputs are synchronous
+
+begin : gen_rst_inputs_sync
+    assign pwrup_rst_n_sync     = pwrup_rst_n;
+    assign rst_n_sync           = rst_n;
+    assign cpu_rst_n_sync       = cpu_rst_n;
+end : gen_rst_inputs_sync
+
+else // SCR1_SCU_CFG_RESET_INPUTS_SYNC == 0, - reset inputs are asynchronous
+
+begin : gen_rst_inputs_async
+// Power-Up Reset synchronizer
+scr1_reset_sync_cell i_pwrup_rstn_reset_sync (
+    .rst_n          (pwrup_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (pwrup_rst_n_sync)
+);
+
+// Regular Reset synchronizer
+scr1_reset_sync_cell i_rstn_reset_sync (
+    .rst_n          (rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (rst_n_sync)
+);
+
+// CPU Reset synchronizer
+scr1_reset_sync_cell i_cpu_rstn_reset_sync (
+    .rst_n          (cpu_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (cpu_rst_n_sync)
+);
+end : gen_rst_inputs_async
+
+// end of SCR1_SCU_CFG_RESET_INPUTS_SYNC
+
+endgenerate
+
+// System Reset: sys_rst_n
+scr1_reset_buf_qlfy_cell i_sys_rstn_buf_qlfy_cell (
+    .rst_n              (pwrup_rst_n_sync),
+    .clk                (clk),
+    .test_rst_n         (test_rst_n),
+    .test_mode          (test_mode),
+    .reset_n_in         (sys_rst_n_sync),
+    .reset_n_out_qlfy   (sys_rst_n_qlfy),
+    .reset_n_out        (sys_rst_n),
+    .reset_n_status     (sys_rst_n_status)
+);
+assign sys_rst_n_sync = (~control_reg.sys_reset) & rst_n_sync;
+
+// Debug Module Reset: dm_rst_n
+scr1_reset_buf_cell i_dm_rstn_buf_cell (
+    .rst_n              (dm_rst_n_sync),
+    .clk                (clk),
+    .test_mode          (test_mode),
+    .test_rst_n         (test_rst_n),
+    .reset_n_in         (1'b1),
+    .reset_n_out        (dm_rst_n),
+    .reset_n_status     (dm_rst_n_status)
+);
+assign dm_rst_n_sync = mode_reg_r.dm_rst_mux ? sys_rst_n      : pwrup_rst_n_sync;
+assign dm_rst_n_qlfy = mode_reg.dm_rst_mux   ? sys_rst_n_qlfy : 1'b1 ;
+
+// Core Reset: core_rst_n
+scr1_reset_buf_qlfy_cell i_core_rstn_buf_qlfy_cell (
+    .rst_n              (sys_rst_n),
+    .clk                (clk),
+    .test_rst_n         (test_rst_n),
+    .test_mode          (test_mode),
+    .reset_n_in         (core_rst_n_sync),
+    .reset_n_out_qlfy   (core_rst_n_qlfy_sync),
+    .reset_n_out        (core_rst_n),
+    .reset_n_status     (core_rst_n_status)
+);
+assign core_rst_n_sync      = ndm_rst_n & hart_rst_n & cpu_rst_n_sync;
+// Reset qualifier - become active before reset is asserted
+assign core_rst_n_qlfy = sys_rst_n_qlfy & core_rst_n_qlfy_sync;
+
+
+// Hart Debug Unit Reset: hdu_rst_n
+scr1_reset_buf_cell i_hdu_rstn_buf_cell (
+    .rst_n              (hdu_rst_n_sync),
+    .clk                (clk),
+    .test_mode          (test_mode),
+    .test_rst_n         (test_rst_n),
+    .reset_n_in         (1'b1),
+    .reset_n_out        (hdu_rst_n),
+    .reset_n_status     (hdu_rst_n_status)
+);
+assign hdu_rst_n_sync = mode_reg_r.hdu_rst_mux ? pwrup_rst_n_sync : core_rst_n;
+assign hdu_rst_n_qlfy = mode_reg.hdu_rst_mux   ? 1'b1             : core_rst_n_qlfy;
+
+endmodule : scr1_scu
+
+`endif // SCR1_DBGC_EN
+
diff --git a/third_party/tests/Scr1/src/core/scr1_tapc.sv b/third_party/tests/Scr1/src/core/scr1_tapc.sv
new file mode 100644
index 0000000..995de5b
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/scr1_tapc.sv
@@ -0,0 +1,425 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_tapc.sv>
+/// @brief      TAP Controller (TAPC)
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_DBGC_EN
+`include "scr1_tapc.svh"
+`include "scr1_dm.svh"
+
+module scr1_tapc (
+    // JTAG signals
+    input   logic                                   trst_n,         // Test Reset (TRSTn)
+    input   logic                                   tck,            // Test Clock (TCK)
+    input   logic                                   tms,            // Test Mode Select (TMS)
+    input   logic                                   tdi,            // Test Data Input (TDI)
+    output  logic                                   tdo,            // Test Data Output (TDO)
+    output  logic                                   tdo_en,         // TDO Enable, signal for TDO buffer control
+    // Fuses:
+    input   logic [31:0]                            fuse_idcode,    // IDCODE value from fuses
+    // System Control Unit i/f
+    output  logic                                   scu_ch_sel,     // SCU Chain Select
+    // DMI scan-chains
+    output  logic                                   dmi_ch_sel,     // DMI Chain Select
+    output  logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]    dmi_ch_id,      // DMI Chain Identifier
+    output  logic                                   dmi_ch_capture, // DMI Chain Capture
+    output  logic                                   dmi_ch_shift,   // DMI Chain Shift
+    output  logic                                   dmi_ch_update,  // DMI Chain Update
+    output  logic                                   dmi_ch_tdi,     // DMI Chain TDI
+    input   logic                                   dmi_ch_tdo      // DMI Chain TDO
+);
+
+//======================================================================================================================
+// Local Parameters
+//======================================================================================================================
+
+//======================================================================================================================
+// Local Types
+//======================================================================================================================
+
+//======================================================================================================================
+// Local Signals
+//======================================================================================================================
+logic trst_n_int;
+
+logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0]      tap_ir_reg;         // Instruction Register (IR)
+logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0]      tap_ir_next;
+logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0]      tap_ir_shift_reg;   // Instruction Register, shift part
+
+type_scr1_tap_state_e                       tap_state_reg;      // TAP's current state
+type_scr1_tap_state_e                       tap_state_next;     // TAP's next state
+
+logic                                       dr_out;
+logic                                       dr_bypass_sel;      // BYPASS register selector
+logic                                       dr_idcode_sel;      // IDCODE register selector
+
+logic                                       dr_bld_id_sel;
+logic [SCR1_TAP_DR_BLD_ID_WIDTH-1:0]        dr_bld_id_reg_nc;
+logic [SCR1_TAP_DR_IDCODE_WIDTH-1:0]        dr_idcode_reg_nc;
+logic                                       dr_bypass_reg_nc;
+
+logic                                       dr_bld_id_tdo;
+logic                                       dr_bypass_tdo;
+logic                                       dr_idcode_tdo;
+
+logic                                       tap_fsm_ir_shift;
+logic                                       tap_fsm_dr_capture;
+logic                                       tap_fsm_dr_shift;
+logic                                       tap_fsm_dr_update;
+
+logic                                       tdo_mux_out;
+logic                                       tdo_mux_out_reg;
+logic                                       tdo_mux_en;
+logic                                       tdo_mux_en_reg;
+
+//======================================================================================================================
+// Logic
+//======================================================================================================================
+
+// -----------------------------------------------------------------------------
+// Reset logic
+// -----------------------------------------------------------------------------
+always_ff @(negedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        trst_n_int <= 1'b0;
+    end
+    else begin
+        if (tap_state_reg == SCR1_TAP_STATE_RESET) begin
+            trst_n_int <= 1'b0;
+        end
+        else begin
+            trst_n_int <= 1'b1;
+        end
+    end
+end
+
+// -----------------------------------------------------------------------------
+// TAP's FSM
+// -----------------------------------------------------------------------------
+always_ff @(posedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        tap_state_reg <= SCR1_TAP_STATE_RESET;
+    end
+    else begin
+        tap_state_reg <= tap_state_next;
+    end
+end
+
+always_comb
+begin
+    begin
+        case (tap_state_reg)
+            SCR1_TAP_STATE_RESET         : tap_state_next = tms ? SCR1_TAP_STATE_RESET        : SCR1_TAP_STATE_IDLE;
+            SCR1_TAP_STATE_IDLE          : tap_state_next = tms ? SCR1_TAP_STATE_DR_SEL_SCAN  : SCR1_TAP_STATE_IDLE;
+            SCR1_TAP_STATE_DR_SEL_SCAN   : tap_state_next = tms ? SCR1_TAP_STATE_IR_SEL_SCAN  : SCR1_TAP_STATE_DR_CAPTURE;
+            SCR1_TAP_STATE_DR_CAPTURE    : tap_state_next = tms ? SCR1_TAP_STATE_DR_EXIT1     : SCR1_TAP_STATE_DR_SHIFT;
+            SCR1_TAP_STATE_DR_SHIFT      : tap_state_next = tms ? SCR1_TAP_STATE_DR_EXIT1     : SCR1_TAP_STATE_DR_SHIFT;
+            SCR1_TAP_STATE_DR_EXIT1      : tap_state_next = tms ? SCR1_TAP_STATE_DR_UPDATE    : SCR1_TAP_STATE_DR_PAUSE;
+            SCR1_TAP_STATE_DR_PAUSE      : tap_state_next = tms ? SCR1_TAP_STATE_DR_EXIT2     : SCR1_TAP_STATE_DR_PAUSE;
+            SCR1_TAP_STATE_DR_EXIT2      : tap_state_next = tms ? SCR1_TAP_STATE_DR_UPDATE    : SCR1_TAP_STATE_DR_SHIFT;
+            SCR1_TAP_STATE_DR_UPDATE     : tap_state_next = tms ? SCR1_TAP_STATE_DR_SEL_SCAN  : SCR1_TAP_STATE_IDLE;
+            SCR1_TAP_STATE_IR_SEL_SCAN   : tap_state_next = tms ? SCR1_TAP_STATE_RESET        : SCR1_TAP_STATE_IR_CAPTURE;
+            SCR1_TAP_STATE_IR_CAPTURE    : tap_state_next = tms ? SCR1_TAP_STATE_IR_EXIT1     : SCR1_TAP_STATE_IR_SHIFT;
+            SCR1_TAP_STATE_IR_SHIFT      : tap_state_next = tms ? SCR1_TAP_STATE_IR_EXIT1     : SCR1_TAP_STATE_IR_SHIFT;
+            SCR1_TAP_STATE_IR_EXIT1      : tap_state_next = tms ? SCR1_TAP_STATE_IR_UPDATE    : SCR1_TAP_STATE_IR_PAUSE;
+            SCR1_TAP_STATE_IR_PAUSE      : tap_state_next = tms ? SCR1_TAP_STATE_IR_EXIT2     : SCR1_TAP_STATE_IR_PAUSE;
+            SCR1_TAP_STATE_IR_EXIT2      : tap_state_next = tms ? SCR1_TAP_STATE_IR_UPDATE    : SCR1_TAP_STATE_IR_SHIFT;
+            SCR1_TAP_STATE_IR_UPDATE     : tap_state_next = tms ? SCR1_TAP_STATE_DR_SEL_SCAN  : SCR1_TAP_STATE_IDLE;
+            default                          : tap_state_next = SCR1_TAP_STATE_XXX;
+        endcase
+    end
+end
+
+// -----------------------------------------------------------------------------
+// Instruction Register (IR)
+// -----------------------------------------------------------------------------
+always_ff @(negedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        tap_ir_reg <= SCR1_TAP_INSTR_IDCODE;
+    end
+    else if (~trst_n_int) begin
+        tap_ir_reg <= SCR1_TAP_INSTR_IDCODE;
+    end
+    else begin
+        tap_ir_reg <= tap_ir_next;
+    end
+end
+
+always_comb
+begin
+    case (tap_state_reg)
+        SCR1_TAP_STATE_IR_UPDATE    : tap_ir_next = tap_ir_shift_reg;
+        default                     : tap_ir_next = tap_ir_reg;
+    endcase
+end
+
+always_ff @(posedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        tap_ir_shift_reg <= '0;
+    end
+    else if (~trst_n_int) begin
+        tap_ir_shift_reg <= '0;
+    end
+    else begin
+        case (tap_state_reg)
+            SCR1_TAP_STATE_IR_CAPTURE :
+                tap_ir_shift_reg <= {{($bits(tap_ir_shift_reg)-1){1'b0}}, 1'b1};
+            SCR1_TAP_STATE_IR_SHIFT :
+                tap_ir_shift_reg <= {tdi, tap_ir_shift_reg[$left(tap_ir_shift_reg):1]};
+            default :
+                begin
+                    // Just store previous value
+                end
+        endcase
+    end
+end
+
+// -----------------------------------------------------------------------------
+// Control signals
+// -----------------------------------------------------------------------------
+always_ff @(posedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        tap_fsm_ir_shift <= 1'b0;
+    end
+    else begin
+        tap_fsm_ir_shift <= ((tap_state_reg == SCR1_TAP_STATE_IR_CAPTURE) |
+                             (tap_state_reg == SCR1_TAP_STATE_IR_SHIFT)   |
+                             (tap_state_reg == SCR1_TAP_STATE_IR_EXIT2) ) &
+                             (tms == 1'b0) & trst_n_int;
+    end
+end
+
+always_ff @(posedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        tap_fsm_dr_capture <= 1'b0;
+    end else begin
+        tap_fsm_dr_capture <= (tap_state_reg == SCR1_TAP_STATE_DR_SEL_SCAN) &
+                              (tms == 1'b0) & trst_n_int;
+    end
+end
+
+always_ff @(posedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        tap_fsm_dr_shift <= 1'b0;
+    end
+    else begin
+        tap_fsm_dr_shift <= ((tap_state_reg == SCR1_TAP_STATE_DR_CAPTURE) |
+                             (tap_state_reg == SCR1_TAP_STATE_DR_SHIFT)   |
+                             (tap_state_reg == SCR1_TAP_STATE_DR_EXIT2) ) &
+                             (tms == 1'b0) & trst_n_int;
+    end
+end
+
+always_ff @(posedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        tap_fsm_dr_update <= 1'b0;
+    end
+    else begin
+        tap_fsm_dr_update <= ((tap_state_reg == SCR1_TAP_STATE_DR_EXIT1)   |
+                              (tap_state_reg == SCR1_TAP_STATE_DR_EXIT2) ) &
+                              (tms == 1'b1) & trst_n_int;
+    end
+end
+
+// -----------------------------------------------------------------------------
+// IR Decoder / DR Outputs Multiplexor
+// -----------------------------------------------------------------------------
+always_comb
+begin
+    dr_out                  = 1'b0;
+    dr_bypass_sel           = 1'b0;
+    dr_idcode_sel           = 1'b0;
+    dr_bld_id_sel           = 1'b0;
+    scu_ch_sel              = 1'b0;
+    //scu_ch_id               = '0;
+    dmi_ch_sel              = 1'b0;
+    dmi_ch_id               = '0;
+    case (tap_ir_reg)
+        SCR1_TAP_INSTR_DTMCS : begin
+            dmi_ch_sel              = 1'b1;
+            dmi_ch_id               = 'd1;
+            dr_out                  = dmi_ch_tdo;
+        end
+
+        SCR1_TAP_INSTR_DMI_ACCESS : begin
+            dmi_ch_sel              = 1'b1;
+            dmi_ch_id               = 'd2;
+            dr_out                  = dmi_ch_tdo;
+        end
+
+        SCR1_TAP_INSTR_IDCODE : begin
+            dr_idcode_sel           = 1'b1;
+            dr_out                  = dr_idcode_tdo;
+        end
+
+        SCR1_TAP_INSTR_BYPASS : begin
+            dr_bypass_sel           = 1'b1;
+            dr_out                  = dr_bypass_tdo;
+        end
+
+        SCR1_TAP_INSTR_BLD_ID : begin
+            dr_bld_id_sel           = 1'b1;
+            dr_out                  = dr_bld_id_tdo;
+        end
+
+        SCR1_TAP_INSTR_SCU_ACCESS : begin
+            scu_ch_sel              = 1'b1;
+            //scu_ch_id               = 'd0;
+            dr_out                  = dmi_ch_tdo;
+        end
+
+        default : begin
+            dr_bypass_sel           = 1'b1;
+            dr_out                  = dr_bypass_tdo;
+        end
+    endcase
+end
+
+// -----------------------------------------------------------------------------
+// TDO Multiplexor & Output Registers
+// -----------------------------------------------------------------------------
+always_comb
+begin
+    tdo_mux_en      = 1'b0;
+    tdo_mux_out     = 1'b0;
+    if (tap_fsm_dr_shift == 1'b1) begin
+        tdo_mux_en      = 1'b1;
+        tdo_mux_out     = dr_out;
+    end else if (tap_fsm_ir_shift == 1'b1) begin
+        tdo_mux_en      = 1'b1;
+        tdo_mux_out     = tap_ir_shift_reg[0];
+    end
+end
+
+always_ff @(negedge tck, negedge trst_n)
+begin
+    if (~trst_n) begin
+        tdo_mux_out_reg <= 1'b0;
+        tdo_mux_en_reg  <= 1'b0;
+    end
+    else if (~trst_n_int) begin
+        tdo_mux_out_reg <= 1'b0;
+        tdo_mux_en_reg  <= 1'b0;
+    end
+    else begin
+        tdo_mux_out_reg <= tdo_mux_out;
+        tdo_mux_en_reg  <= tdo_mux_en;
+    end
+end
+
+assign tdo      = tdo_mux_out_reg;
+assign tdo_en   = tdo_mux_en_reg;
+
+// -----------------------------------------------------------------------------
+// DR :: BYPASS register
+// -----------------------------------------------------------------------------
+scr1_tapc_shift_reg #(
+        .SCR1_WIDTH      (SCR1_TAP_DR_BYPASS_WIDTH),
+        .SCR1_RESET_VALUE(SCR1_TAP_DR_BYPASS_WIDTH'(0))
+    )
+    i_bypass_reg(
+        .clk            (tck),
+        .rst_n          (trst_n),
+        .rst_n_sync     (trst_n_int),
+        .fsm_dr_select  (dr_bypass_sel),
+        .fsm_dr_capture (tap_fsm_dr_capture),
+        .fsm_dr_shift   (tap_fsm_dr_shift),
+        .din_serial     (tdi),
+        .din_parallel   (1'b0),
+        .dout_serial    (dr_bypass_tdo),
+        .dout_parallel  (dr_bypass_reg_nc)
+);
+
+// -----------------------------------------------------------------------------
+// DR :: IDCODE register
+// -----------------------------------------------------------------------------
+scr1_tapc_shift_reg #(
+        .SCR1_WIDTH      (SCR1_TAP_DR_IDCODE_WIDTH),
+        .SCR1_RESET_VALUE(SCR1_TAP_DR_IDCODE_WIDTH'(0))
+    )
+    i_tap_idcode_reg(
+        .clk            (tck),
+        .rst_n          (trst_n),
+        .rst_n_sync     (trst_n_int),
+        .fsm_dr_select  (dr_idcode_sel),
+        .fsm_dr_capture (tap_fsm_dr_capture),
+        .fsm_dr_shift   (tap_fsm_dr_shift),
+        .din_serial     (tdi),
+        .din_parallel   (fuse_idcode),
+        .dout_serial    (dr_idcode_tdo),
+        .dout_parallel  (dr_idcode_reg_nc)
+);
+
+// -----------------------------------------------------------------------------
+// DR :: BLD_ID register
+// -----------------------------------------------------------------------------
+scr1_tapc_shift_reg #(
+        .SCR1_WIDTH      (SCR1_TAP_DR_BLD_ID_WIDTH),
+        .SCR1_RESET_VALUE(SCR1_TAP_DR_BLD_ID_WIDTH'(0))
+    )
+    i_tap_dr_bld_id_reg(
+        .clk            (tck),
+        .rst_n          (trst_n),
+        .rst_n_sync     (trst_n_int),
+        .fsm_dr_select  (dr_bld_id_sel),
+        .fsm_dr_capture (tap_fsm_dr_capture),
+        .fsm_dr_shift   (tap_fsm_dr_shift),
+        .din_serial     (tdi),
+        .din_parallel   (SCR1_TAP_BLD_ID_VALUE),
+        .dout_serial    (dr_bld_id_tdo),
+        .dout_parallel  (dr_bld_id_reg_nc)
+);
+
+// -----------------------------------------------------------------------------
+// DR :: DAP Scan Chains
+// -----------------------------------------------------------------------------
+assign dmi_ch_tdi       = tdi;
+assign dmi_ch_capture   = tap_fsm_dr_capture;
+assign dmi_ch_shift     = tap_fsm_dr_shift;
+assign dmi_ch_update    = tap_fsm_dr_update;
+
+// Misc
+
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+// X checks
+SCR1_SVA_TAPC_XCHECK : assert property (
+    @(posedge tck) disable iff (~trst_n)
+    !$isunknown({
+        tms,
+        tdi
+    })
+) else begin
+    $error("TAPC error: unknown values");
+end
+
+SCR1_SVA_TAPC_XCHECK_NEGCLK : assert property (
+    @(negedge tck) disable iff (tap_state_reg != SCR1_TAP_STATE_DR_SHIFT)
+    !$isunknown({
+        dmi_ch_tdo
+    })
+) else begin
+    $error("TAPC @negedge error: unknown values");
+end
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_tapc
+
+`endif // SCR1_DBGC_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core/scr1_tapc_shift_reg.sv b/third_party/tests/Scr1/src/core/scr1_tapc_shift_reg.sv
new file mode 100644
index 0000000..9318398
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/scr1_tapc_shift_reg.sv
@@ -0,0 +1,114 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_tapc_shift_reg.sv>
+/// @brief      TAPC shift register. Parameterized implementation of JTAG TAPC's Shift Register.
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_DBGC_EN
+module scr1_tapc_shift_reg #(
+    parameter   int unsigned            SCR1_WIDTH       = 8,   // Register width, bits
+    parameter   logic [SCR1_WIDTH-1:0]  SCR1_RESET_VALUE = '0   // Register's value after reset
+) (
+    input  logic                    clk,            // Clock
+    input  logic                    rst_n,          // Async reset
+    input  logic                    rst_n_sync,     // Sync reset
+                                                    // TAP FSM's control signals:
+    input  logic                    fsm_dr_select,  //   - for this DR selection (operation enabling);
+    input  logic                    fsm_dr_capture, //   - to capture parallel input's data into shift register;
+    input  logic                    fsm_dr_shift,   //   - to enable data shifting;
+                                                    // Inputs:
+    input  logic                    din_serial,     //   - serial (shift_reg[msb/SCR1_WIDTH]);
+    input  logic [SCR1_WIDTH-1:0]   din_parallel,   //   - parallel (shift register's input).
+                                                    // Outputs:
+    output logic                    dout_serial,    //   - serial (shift_reg[0]);
+    output logic [SCR1_WIDTH-1:0]   dout_parallel   //   - parallel (shift register's output).
+);
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+logic [SCR1_WIDTH-1:0]   shift_reg;
+
+//-------------------------------------------------------------------------------
+// Shift register
+//-------------------------------------------------------------------------------
+generate
+    if (SCR1_WIDTH > 1)
+    begin : dr_shift_reg
+
+        always_ff @(posedge clk, negedge rst_n)
+        begin
+            if (~rst_n) begin
+                shift_reg <= SCR1_RESET_VALUE;
+            end
+            else if (~rst_n_sync) begin
+                shift_reg <= SCR1_RESET_VALUE;
+            end
+            else if (fsm_dr_select & fsm_dr_capture) begin
+                shift_reg <= din_parallel;
+            end
+            else if (fsm_dr_select & fsm_dr_shift) begin
+                shift_reg <= {din_serial, shift_reg[SCR1_WIDTH-1:1]};
+            end
+        end
+
+    end
+    else begin : dr_shift_reg
+
+        always_ff @(posedge clk, negedge rst_n)
+        begin
+            if (~rst_n) begin
+                shift_reg <= SCR1_RESET_VALUE;
+            end
+            else if (~rst_n_sync) begin
+                shift_reg <= SCR1_RESET_VALUE;
+            end
+            else if (fsm_dr_select & fsm_dr_capture) begin
+                shift_reg <= din_parallel;
+            end
+            else if (fsm_dr_select & fsm_dr_shift) begin
+                shift_reg <= din_serial;
+            end
+        end
+
+    end
+endgenerate
+
+//-------------------------------------------------------------------------------
+// Parallel output
+//-------------------------------------------------------------------------------
+assign dout_parallel = shift_reg;
+
+//-------------------------------------------------------------------------------
+// Serial output
+//-------------------------------------------------------------------------------
+assign dout_serial = shift_reg[0];
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+// X checks
+SCR1_SVA_TAPC_SHIFTREG_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown({
+        rst_n_sync,
+        fsm_dr_select,
+        fsm_dr_capture,
+        fsm_dr_shift,
+        din_serial,
+        din_parallel
+    })
+) else begin
+    $error("TAPC Shift Reg error: unknown values");
+end
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_tapc_shift_reg
+
+`endif // SCR1_DBGC_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/core/scr1_tapc_synchronizer.sv b/third_party/tests/Scr1/src/core/scr1_tapc_synchronizer.sv
new file mode 100644
index 0000000..28194d6
--- /dev/null
+++ b/third_party/tests/Scr1/src/core/scr1_tapc_synchronizer.sv
@@ -0,0 +1,182 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_tapc_synchronizer.sv>
+/// @brief      TAPC clock domain crossing synchronizer
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_DBGC_EN
+`include "scr1_tapc.svh"
+`include "scr1_dm.svh"
+
+module scr1_tapc_synchronizer (
+    // System common signals
+    input   logic                                   pwrup_rst_n,        // Power-Up Reset
+    input   logic                                   dm_rst_n,           // Debug Module Reset
+    input   logic                                   clk,                // System Clock (SysCLK)
+    // JTAG common signals
+    input   logic                                   trst_n,             // JTAG Test Reset (TRSTn)
+    input   logic                                   tck,                // JTAG Test Clock (TCK)
+    // System Control/Status signals
+    input  logic                                    scu_ch_sel,         // SCU Chain Select input  (TCK domain)
+    output logic                                    scu_ch_sel_core,    // SCU Chain Select output (SysCLK domain)
+
+    // DMI scan-chains
+    input  logic                                    dmi_ch_sel,         // DMI Chain Select input  (TCK domain)
+    output logic                                    dmi_ch_sel_core,    // DMI Chain Select output (SysCLK domain)
+
+    input  logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]     dmi_ch_id,          // DMI Chain Identifier input  (TCK domain)
+    output logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]     dmi_ch_id_core,     // DMI Chain Identifier output (SysCLK domain)
+
+    input  logic                                    dmi_ch_capture,     // DMI Chain Capture input  (TCK domain)
+    output logic                                    dmi_ch_capture_core,// DMI Chain Capture output (SysCLK domain)
+
+    input  logic                                    dmi_ch_shift,       // DMI Chain Shift input  (TCK domain)
+    output logic                                    dmi_ch_shift_core,  // DMI Chain Shift output (SysCLK domain)
+
+    input  logic                                    dmi_ch_update,      // DMI Chain Update input  (TCK domain)
+    output logic                                    dmi_ch_update_core, // DMI Chain Update output (SysCLK domain)
+
+    input  logic                                    dmi_ch_tdi,         // DMI Chain TDI input  (TCK domain)
+    output logic                                    dmi_ch_tdi_core,    // DMI Chain TDI output (SysCLK domain)
+
+    output logic                                    dmi_ch_tdo,         // DMI Chain TDO output (TCK domain)
+    input  logic                                    dmi_ch_tdo_core     // DMI Chain TDO input  (SysCLK domain)
+);
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+
+logic           tck_divpos;
+logic           tck_divneg;
+logic           tck_rise_load;
+logic           tck_rise_reset;
+logic           tck_fall_load;
+logic           tck_fall_reset;
+logic [3:0]     tck_divpos_sync;
+logic [3:0]     tck_divneg_sync;
+logic [2:0]     dmi_ch_capture_sync;
+logic [2:0]     dmi_ch_shift_sync;
+logic [2:0]     dmi_ch_tdi_sync;
+
+//-------------------------------------------------------------------------------
+// Logic
+//-------------------------------------------------------------------------------
+
+always_ff @(posedge tck, negedge trst_n) begin
+    if (~trst_n) begin
+        tck_divpos      <= 1'b0;
+    end else begin
+        tck_divpos      <= ~tck_divpos;
+    end
+end
+
+always_ff @(negedge tck, negedge trst_n) begin
+    if (~trst_n) begin
+        tck_divneg      <= 1'b0;
+    end else begin
+        tck_divneg      <= ~tck_divneg;
+    end
+end
+
+always_ff @(posedge clk, negedge pwrup_rst_n) begin
+    if (~pwrup_rst_n) begin
+        tck_divpos_sync <= 4'd0;
+        tck_divneg_sync <= 4'd0;
+    end else begin
+        tck_divpos_sync <= {tck_divpos_sync[2:0], tck_divpos};
+        tck_divneg_sync <= {tck_divneg_sync[2:0], tck_divneg};
+    end
+end
+
+assign tck_rise_load  = tck_divpos_sync[2] ^ tck_divpos_sync[1];
+assign tck_rise_reset = tck_divpos_sync[3] ^ tck_divpos_sync[2];
+assign tck_fall_load  = tck_divneg_sync[2] ^ tck_divneg_sync[1];
+assign tck_fall_reset = tck_divneg_sync[3] ^ tck_divneg_sync[2];
+
+always_ff @(posedge clk, negedge pwrup_rst_n) begin
+    if (~pwrup_rst_n) begin
+            dmi_ch_update_core   <= '0;
+    end else begin
+        if  (tck_fall_load) begin
+            dmi_ch_update_core   <= dmi_ch_update;
+        end else if (tck_fall_reset) begin
+            dmi_ch_update_core   <= '0;
+        end
+    end
+end
+
+always_ff @(negedge tck, negedge trst_n) begin
+    if (~trst_n) begin
+        dmi_ch_capture_sync[0] <= '0;
+        dmi_ch_shift_sync[0]   <= '0;
+    end else begin
+        dmi_ch_capture_sync[0] <= dmi_ch_capture;
+        dmi_ch_shift_sync[0]   <= dmi_ch_shift;
+    end
+end
+
+always_ff @(posedge clk, negedge pwrup_rst_n) begin
+    if (~pwrup_rst_n) begin
+        dmi_ch_capture_sync[2:1] <= '0;
+        dmi_ch_shift_sync[2:1]   <= '0;
+    end else begin
+        dmi_ch_capture_sync[2:1] <= {dmi_ch_capture_sync[1], dmi_ch_capture_sync[0]};
+        dmi_ch_shift_sync[2:1]   <= {dmi_ch_shift_sync[1], dmi_ch_shift_sync[0]};
+    end
+end
+
+always_ff @(posedge clk, negedge pwrup_rst_n) begin
+    if (~pwrup_rst_n) begin
+        dmi_ch_tdi_sync     <= '0;
+    end else begin
+        dmi_ch_tdi_sync     <= {dmi_ch_tdi_sync[1:0], dmi_ch_tdi};
+    end
+end
+
+always_ff @(posedge clk, negedge pwrup_rst_n) begin
+    if (~pwrup_rst_n) begin
+            dmi_ch_capture_core <= '0;
+            dmi_ch_shift_core   <= '0;
+            dmi_ch_tdi_core     <= '0;
+    end else begin
+        if (tck_rise_load) begin
+            dmi_ch_capture_core <= dmi_ch_capture_sync[2];
+            dmi_ch_shift_core   <= dmi_ch_shift_sync[2];
+            dmi_ch_tdi_core     <= dmi_ch_tdi_sync[2];
+        end else if (tck_rise_reset) begin
+            dmi_ch_capture_core <= '0;
+            dmi_ch_shift_core   <= '0;
+            dmi_ch_tdi_core     <= '0;
+        end
+    end
+end
+
+always_ff @(posedge clk, negedge dm_rst_n) begin
+    if (~dm_rst_n) begin
+            dmi_ch_sel_core     <= '0;
+            dmi_ch_id_core      <= '0;
+    end else begin
+        if (tck_rise_load) begin
+            dmi_ch_sel_core     <= dmi_ch_sel;
+            dmi_ch_id_core      <= dmi_ch_id;
+        end
+    end
+end
+
+always_ff @(posedge clk, negedge pwrup_rst_n) begin
+    if (~pwrup_rst_n) begin
+            scu_ch_sel_core     <= '0;
+    end else begin
+        if (tck_rise_load) begin
+            scu_ch_sel_core     <= scu_ch_sel;
+        end
+    end
+end
+
+assign dmi_ch_tdo = dmi_ch_tdo_core;
+
+endmodule : scr1_tapc_synchronizer
+
+`endif // SCR1_DBGC_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/includes/scr1_ahb.svh b/third_party/tests/Scr1/src/includes/scr1_ahb.svh
new file mode 100644
index 0000000..d6d38c0
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_ahb.svh
@@ -0,0 +1,42 @@
+`ifndef SCR1_AHB_SVH
+`define SCR1_AHB_SVH
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_ahb.svh>
+/// @brief      AHB header file
+///
+
+`include "scr1_arch_description.svh"
+
+parameter SCR1_AHB_WIDTH  = 32;
+
+// Encoding for HTRANS signal
+parameter logic [1:0] SCR1_HTRANS_IDLE   = 2'b00;
+parameter logic [1:0] SCR1_HTRANS_NONSEQ = 2'b10;
+parameter logic [1:0] SCR1_HTRANS_ERR    = 'x;
+
+// Encoding for HBURST signal
+parameter logic [2:0] SCR1_HBURST_SINGLE = 3'b000;
+parameter logic [2:0] SCR1_HBURST_ERR    = 'x;
+
+// Encoding for HSIZE signal
+parameter logic [2:0] SCR1_HSIZE_8B    = 3'b000;
+parameter logic [2:0] SCR1_HSIZE_16B   = 3'b001;
+parameter logic [2:0] SCR1_HSIZE_32B   = 3'b010;
+parameter logic [2:0] SCR1_HSIZE_ERR   = 'x;
+
+// Encoding HPROT signal
+// HPROT[0] : 0 - instr;      1 - data
+// HPROT[1] : 0 - user;       1 - privilege
+// HPROT[2] : 0 - not buffer; 1 - buffer
+// HPROT[3] : 0 - cacheable;  1 - cacheable
+parameter SCR1_HPROT_DATA  = 0;
+parameter SCR1_HPROT_PRV   = 1;
+parameter SCR1_HPROT_BUF   = 2;
+parameter SCR1_HPROT_CACHE = 3;
+
+// Encoding HRESP signal
+parameter logic SCR1_HRESP_OKAY  = 1'b0;
+parameter logic SCR1_HRESP_ERROR = 1'b1;
+parameter logic SCR1_HRESP_ERR   = 1'bx;
+
+`endif // SCR1_AHB_SVH
diff --git a/third_party/tests/Scr1/src/includes/scr1_arch_description.svh b/third_party/tests/Scr1/src/includes/scr1_arch_description.svh
new file mode 100644
index 0000000..a83cd73
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_arch_description.svh
@@ -0,0 +1,175 @@
+`ifndef SCR1_ARCH_DESCRIPTION_SVH
+`define SCR1_ARCH_DESCRIPTION_SVH
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_arch_description.svh>
+/// @brief      Architecture description file
+///
+
+//-------------------------------------------------------------------------------
+// Core fundamental parameters (READ-ONLY, do not modify)
+//-------------------------------------------------------------------------------
+`define SCR1_MIMPID             32'h19083000
+`define SCR1_XLEN               32
+`define SCR1_FLEN               `SCR1_XLEN
+`define SCR1_IMEM_AWIDTH        `SCR1_XLEN
+`define SCR1_IMEM_DWIDTH        `SCR1_XLEN
+`define SCR1_DMEM_AWIDTH        `SCR1_XLEN
+`define SCR1_DMEM_DWIDTH        `SCR1_XLEN
+parameter int unsigned          SCR1_CSR_MTVEC_BASE_ZERO_BITS   = 6;
+parameter int unsigned          SCR1_CSR_MTVEC_BASE_VAL_BITS    = `SCR1_XLEN-SCR1_CSR_MTVEC_BASE_ZERO_BITS;
+
+// TAP_IDCODE - value of a specific Syntacore processor's TAP identifier:
+`define SCR1_TAP_IDCODE_WIDTH    32
+`define SCR1_TAP_IDCODE          `SCR1_TAP_IDCODE_WIDTH'hDEB11001
+
+//-------------------------------------------------------------------------------
+// Recommended core architecture configurations (modifiable)
+//-------------------------------------------------------------------------------
+//`define SCR1_CFG_RV32EC_MIN
+//`define SCR1_CFG_RV32IC_BASE
+`define SCR1_CFG_RV32IMC_MAX
+
+//-------------------------------------------------------------------------------
+// Setting recommended configurations (READ-ONLY, do not modify)
+//-------------------------------------------------------------------------------
+`ifdef SCR1_CFG_RV32EC_MIN
+  `define SCR1_RVE_EXT
+  `undef  SCR1_RVM_EXT
+  `define SCR1_RVC_EXT
+  `define SCR1_IFU_QUEUE_BYPASS
+  `undef  SCR1_EXU_STAGE_BYPASS
+  `undef  SCR1_CLKCTRL_EN
+  `undef  SCR1_VECT_IRQ_EN
+  `undef  SCR1_CSR_MCOUNTEN_EN
+  `define SCR1_CFG_EXCL_UNCORE
+  parameter int unsigned SCR1_CSR_MTVEC_BASE_RW_BITS = 0;
+`elsif SCR1_CFG_RV32IC_BASE
+  `undef  SCR1_RVE_EXT
+  `undef  SCR1_RVM_EXT
+  `define SCR1_RVC_EXT
+  `define SCR1_IFU_QUEUE_BYPASS
+  `define SCR1_EXU_STAGE_BYPASS
+  `undef  SCR1_CLKCTRL_EN
+  `define SCR1_VECT_IRQ_EN
+  `define SCR1_CSR_MCOUNTEN_EN
+  parameter int unsigned SCR1_CSR_MTVEC_BASE_RW_BITS = 8;
+`elsif SCR1_CFG_RV32IMC_MAX
+  `undef  SCR1_RVE_EXT
+  `define SCR1_RVM_EXT
+  `define SCR1_RVC_EXT
+  `define SCR1_IFU_QUEUE_BYPASS
+  `define SCR1_EXU_STAGE_BYPASS
+  `define SCR1_FAST_MUL
+  `undef  SCR1_CLKCTRL_EN
+  `define SCR1_VECT_IRQ_EN
+  `define SCR1_CSR_MCOUNTEN_EN
+  parameter int unsigned SCR1_CSR_MTVEC_BASE_RW_BITS = 26;
+
+`else // RECOMMENDED_CONFIGURATIONS
+
+//-------------------------------------------------------------------------------
+// Core configurable options (modifiable)
+//-------------------------------------------------------------------------------
+// PLEASE UNDEFINE ALL RECOMMENDED CONFIGURATIONS IF YOU WANT TO USE THIS SECTION
+
+  //`define SCR1_RVE_EXT                // enables RV32E base integer instruction set
+  `define SCR1_RVM_EXT                // enables standard extension for integer mul/div
+  `define SCR1_RVC_EXT                // enables standard extension for compressed instructions
+
+  `define SCR1_IFU_QUEUE_BYPASS       // enables bypass between IFU and IDU stages
+  `define SCR1_EXU_STAGE_BYPASS       // enables bypass between IDU and EXU stages
+
+  `define SCR1_FAST_MUL               // enables one-cycle multiplication
+
+  `define SCR1_CLKCTRL_EN             // enables global clock gating
+
+  `define SCR1_VECT_IRQ_EN            // enables vectored interrupts
+  `define SCR1_CSR_MCOUNTEN_EN        // enables custom MCOUNTEN CSR
+  parameter int unsigned SCR1_CSR_MTVEC_BASE_RW_BITS = 26;    // number of writable high-order bits in MTVEC BASE field
+                                                              // legal values are 0 to 26
+                                                              // read-only bits are hardwired to reset value
+
+`endif // RECOMMENDED_CONFIGURATIONS
+
+//-------------------------------------------------------------------------------
+// Uncore configurable options (modifiable)
+//-------------------------------------------------------------------------------
+
+// `define SCR1_CFG_EXCL_UNCORE        // exclude DBGC, BRKM, IPIC (also set in SCR1_CFG_RV32EC_MIN)
+
+`ifndef SCR1_CFG_EXCL_UNCORE
+
+  `define SCR1_DBGC_EN                // enables debug controller
+  `define SCR1_BRKM_EN                // enables breakpoint module
+  parameter int unsigned SCR1_BRKM_BRKPT_NUMBER = 2;        // number of hardware breakpoints
+  `define SCR1_BRKM_BRKPT_ICOUNT_EN   // Hardware Breakpoint on instruction counter Enable
+
+  `define SCR1_IPIC_EN                // enables interrupt controller
+  `define SCR1_IPIC_SYNC_EN           // enables IPIC synchronizer
+
+`endif // SCR1_CFG_EXCL_UNCORE
+
+`define SCR1_IMEM_AHB_IN_BP         // bypass instruction memory AHB bridge input register
+`define SCR1_IMEM_AHB_OUT_BP        // bypass instruction memory AHB bridge output register
+`define SCR1_DMEM_AHB_IN_BP         // bypass data memory AHB bridge input register
+`define SCR1_DMEM_AHB_OUT_BP        // bypass data memory AHB bridge output register
+
+`define SCR1_IMEM_AXI_REQ_BP        // bypass instruction memory AXI bridge request register
+`define SCR1_IMEM_AXI_RESP_BP       // bypass instruction memory AXI bridge response register
+`define SCR1_DMEM_AXI_REQ_BP        // bypass data memory AXI bridge request register
+`define SCR1_DMEM_AXI_RESP_BP       // bypass data memory AXI bridge response register
+
+`define SCR1_TCM_EN                 // enables tightly-coupled memory
+
+//-------------------------------------------------------------------------------
+// Address constants
+//-------------------------------------------------------------------------------
+`ifndef SCR1_ARCH_CUSTOM
+
+// Base address constants
+parameter bit [`SCR1_XLEN-1:0]          SCR1_ARCH_RST_VECTOR        = 'h200;            // Reset vector
+parameter bit [`SCR1_XLEN-1:0]          SCR1_ARCH_CSR_MTVEC_BASE    = 'h1C0;            // MTVEC BASE field reset value
+
+parameter bit [`SCR1_DMEM_AWIDTH-1:0]   SCR1_TCM_ADDR_MASK          = 'hFFFF0000;       // TCM mask and size
+parameter bit [`SCR1_DMEM_AWIDTH-1:0]   SCR1_TCM_ADDR_PATTERN       = 'h00480000;       // TCM address match pattern
+
+parameter bit [`SCR1_DMEM_AWIDTH-1:0]   SCR1_TIMER_ADDR_MASK        = 'hFFFFFFE0;       // Timer mask (should be 0xFFFFFFE0)
+parameter bit [`SCR1_DMEM_AWIDTH-1:0]   SCR1_TIMER_ADDR_PATTERN     = 'h00490000;       // Timer address match pattern
+
+`else // SCR1_ARCH_CUSTOM
+ `include "scr1_arch_custom.svh"         // contains custom address constants for SDK projects
+
+`endif // SCR1_ARCH_CUSTOM
+
+
+//-------------------------------------------------------------------------------
+// Core read-only parameters (do not modify)
+//-------------------------------------------------------------------------------
+`define SCR1_SHAMT_WIDTH        5
+
+`ifndef SCR1_RVE_EXT
+`define SCR1_RVI_EXT
+`endif // ~SCR1_RVE_EXT
+
+`ifdef SCR1_RVE_EXT
+`define SCR1_MPRF_ADDR_WIDTH    4
+`else // SCR1_RVE_EXT
+`define SCR1_MPRF_ADDR_WIDTH    5
+`endif // SCR1_RVE_EXT
+
+parameter int unsigned  SCR1_CSR_ADDR_WIDTH         = 12;
+parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS]  SCR1_ARCH_CSR_MTVEC_BASE_RST_VAL    =
+                                      SCR1_CSR_MTVEC_BASE_VAL_BITS'(SCR1_ARCH_CSR_MTVEC_BASE >> SCR1_CSR_MTVEC_BASE_ZERO_BITS);
+parameter int unsigned  SCR1_CSR_MTVEC_BASE_RO_BITS = (`SCR1_XLEN-(SCR1_CSR_MTVEC_BASE_ZERO_BITS+SCR1_CSR_MTVEC_BASE_RW_BITS));
+
+`define SCR1_MTVAL_ILLEGAL_INSTR_EN
+`define SCR1_MPRF_RST_EN
+
+//-------------------------------------------------------------------------------
+// Parameters for simulation
+//-------------------------------------------------------------------------------
+//`define SCR1_SIM_ENV                    // enable simulation code (SVA, trace log)
+`define SCR1_TRACE_LOG_EN               // enable trace log
+`define SCR1_TRACE_LOG_FULL             // full trace log
+
+`endif // SCR1_ARCH_DESCRIPTION_SVH
diff --git a/third_party/tests/Scr1/src/includes/scr1_arch_types.svh b/third_party/tests/Scr1/src/includes/scr1_arch_types.svh
new file mode 100644
index 0000000..97a980a
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_arch_types.svh
@@ -0,0 +1,47 @@
+`ifndef SCR1_ARCH_TYPES_SVH
+`define SCR1_ARCH_TYPES_SVH
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_arch_types.svh>
+/// @brief      Pipeline types description file
+///
+
+`include "scr1_arch_description.svh"
+
+typedef logic [`SCR1_XLEN-1:0]  type_scr1_mprf_v;
+typedef logic [`SCR1_XLEN-1:0]  type_scr1_pc_v;
+
+//-------------------------------------------------------------------------------
+// Exception and IRQ codes
+//-------------------------------------------------------------------------------
+parameter int unsigned SCR1_EXC_CODE_WIDTH_E    = 4;
+
+// Exceptions
+typedef enum logic [SCR1_EXC_CODE_WIDTH_E-1:0] {
+    SCR1_EXC_CODE_INSTR_MISALIGN        = 4'd0,     // from EXU
+    SCR1_EXC_CODE_INSTR_ACCESS_FAULT    = 4'd1,     // from IFU
+    SCR1_EXC_CODE_ILLEGAL_INSTR         = 4'd2,     // from IDU or CSR
+    SCR1_EXC_CODE_BREAKPOINT            = 4'd3,     // from IDU or BRKM
+    SCR1_EXC_CODE_LD_ADDR_MISALIGN      = 4'd4,     // from LSU
+    SCR1_EXC_CODE_LD_ACCESS_FAULT       = 4'd5,     // from LSU
+    SCR1_EXC_CODE_ST_ADDR_MISALIGN      = 4'd6,     // from LSU
+    SCR1_EXC_CODE_ST_ACCESS_FAULT       = 4'd7,     // from LSU
+    SCR1_EXC_CODE_ECALL_M               = 4'd11     // from IDU
+} type_scr1_exc_code_e;
+
+// IRQs, reset
+parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_SOFTWARE      = 4'd3;
+parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_TIMER         = 4'd7;
+parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_EXTERNAL      = 4'd11;
+parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_RESET               = 4'd0;
+
+//-------------------------------------------------------------------------------
+// Operand width for BRKM
+//-------------------------------------------------------------------------------
+typedef enum logic [1:0] {
+    SCR1_OP_WIDTH_BYTE  = 2'b00,
+    SCR1_OP_WIDTH_HALF  = 2'b01,
+    SCR1_OP_WIDTH_WORD  = 2'b10,
+    SCR1_OP_WIDTH_ERROR = 'x
+} type_scr1_op_width_e;
+
+`endif //SCR1_ARCH_TYPES_SVH
diff --git a/third_party/tests/Scr1/src/includes/scr1_csr.svh b/third_party/tests/Scr1/src/includes/scr1_csr.svh
new file mode 100644
index 0000000..b630e7c
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_csr.svh
@@ -0,0 +1,192 @@
+`ifndef SCR1_CSR_SVH
+`define SCR1_CSR_SVH
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_csr.svh>
+/// @brief      CSR mapping/description file
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_arch_types.svh"
+`include "scr1_ipic.svh"
+
+`ifdef SCR1_RVE_EXT
+`define SCR1_CSR_REDUCED_CNT
+`endif // SCR1_RVE_EXT
+
+`ifdef SCR1_CSR_REDUCED_CNT
+`undef SCR1_CSR_MCOUNTEN_EN
+`endif // SCR1_CSR_REDUCED_CNT
+
+//-------------------------------------------------------------------------------
+// CSR addresses (standard)
+//-------------------------------------------------------------------------------
+
+// Machine Information Registers (read-only)
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MVENDORID     = 'hF11;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MARCHID       = 'hF12;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIMPID        = 'hF13;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MHARTID       = 'hF14;
+
+// Machine Trap Setup (read-write)
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MSTATUS       = 'h300;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MISA          = 'h301;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIE           = 'h304;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MTVEC         = 'h305;
+
+// Machine Trap Handling (read-write)
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MSCRATCH      = 'h340;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MEPC          = 'h341;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCAUSE        = 'h342;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MTVAL         = 'h343;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIP           = 'h344;
+
+// Machine Counters/Timers (read-write)
+`ifndef SCR1_CSR_REDUCED_CNT
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCYCLE        = 'hB00;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MINSTRET      = 'hB02;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCYCLEH       = 'hB80;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MINSTRETH     = 'hB82;
+`endif // SCR1_CSR_REDUCED_CNT
+
+// Shadow Counters/Timers (read-only)
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TIME          = 'hC01;
+`ifndef SCR1_CSR_REDUCED_CNT
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_CYCLE         = 'hC00;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_INSTRET       = 'hC02;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TIMEH         = 'hC81;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_CYCLEH        = 'hC80;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_INSTRETH      = 'hC82;
+`endif // SCR1_CSR_REDUCED_CNT
+
+`ifdef SCR1_DBGC_EN
+//parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_DBGC_SCRATCH  = 'h7C8;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_HDU_MBASE    = 'h7B0;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_HDU_MSPAN    = 'h004;    // must be power of 2
+`endif // SCR1_DBGC_EN
+
+//-------------------------------------------------------------------------------
+// CSR addresses (non-standard)
+//-------------------------------------------------------------------------------
+`ifdef SCR1_CSR_MCOUNTEN_EN
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCOUNTEN      = 'h7E0;
+`endif // SCR1_CSR_MCOUNTEN_EN
+
+`ifdef SCR1_BRKM_EN
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_MBASE    = 'h7A0;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_MSPAN    = 'h008;    // must be power of 2
+`endif // SCR1_BRKM_EN
+
+`ifdef SCR1_IPIC_EN
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_BASE     = 'hBF0;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CISV     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CISV );
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CICSR    = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CICSR);
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IPR      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IPR  );
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ISVR     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ISVR );
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_EOI      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_EOI  );
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_SOI      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_SOI  );
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IDX      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IDX  );
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ICSR     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ICSR );
+`endif // SCR1_IPIC_EN
+
+
+//-------------------------------------------------------------------------------
+// CSR definitions
+//-------------------------------------------------------------------------------
+
+// General
+parameter bit [`SCR1_XLEN-1:0] SCR1_RST_VECTOR      = SCR1_ARCH_RST_VECTOR;
+
+// Reset values TBD
+parameter bit SCR1_CSR_MIE_MSIE_RST_VAL             = 1'b0;
+parameter bit SCR1_CSR_MIE_MTIE_RST_VAL             = 1'b0;
+parameter bit SCR1_CSR_MIE_MEIE_RST_VAL             = 1'b0;
+
+parameter bit SCR1_CSR_MIP_MSIP_RST_VAL             = 1'b0;
+parameter bit SCR1_CSR_MIP_MTIP_RST_VAL             = 1'b0;
+parameter bit SCR1_CSR_MIP_MEIP_RST_VAL             = 1'b0;
+
+parameter bit SCR1_CSR_MSTATUS_MIE_RST_VAL          = 1'b0;
+parameter bit SCR1_CSR_MSTATUS_MPIE_RST_VAL         = 1'b1;
+
+// MISA
+`define SCR1_RVC_ENC                                `SCR1_XLEN'h0004
+`define SCR1_RVE_ENC                                `SCR1_XLEN'h0010
+`define SCR1_RVI_ENC                                `SCR1_XLEN'h0100
+`define SCR1_RVM_ENC                                `SCR1_XLEN'h1000
+parameter bit [1:0]             SCR1_MISA_MXL_32    = 2'd1;
+parameter bit [`SCR1_XLEN-1:0]  SCR1_CSR_MISA       = (SCR1_MISA_MXL_32 << (`SCR1_XLEN-2))
+`ifdef SCR1_RVI_EXT
+                                                    | `SCR1_RVI_ENC
+`elsif SCR1_RVE_EXT
+                                                    | `SCR1_RVE_ENC
+`endif
+`ifdef SCR1_RVC_EXT
+                                                    | `SCR1_RVC_ENC
+`endif
+`ifdef SCR1_RVM_EXT
+                                                    | `SCR1_RVM_ENC
+`endif
+                                                    ;
+
+// MVENDORID
+parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MVENDORID   = '0;
+
+// MARCHID
+parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MARCHID     = `SCR1_XLEN'd8;
+
+// MIMPID
+parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MIMPID      = `SCR1_MIMPID;
+
+// MSTATUS
+parameter bit [1:0] SCR1_CSR_MSTATUS_MPP            = 2'b11;
+parameter int unsigned SCR1_CSR_MSTATUS_MIE_OFFSET  = 3;
+parameter int unsigned SCR1_CSR_MSTATUS_MPIE_OFFSET = 7;
+parameter int unsigned SCR1_CSR_MSTATUS_MPP_OFFSET  = 11;
+
+// MTVEC
+// bits [5:0] are always zero
+parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_RST_VAL  = SCR1_ARCH_CSR_MTVEC_BASE_RST_VAL;
+
+parameter bit SCR1_CSR_MTVEC_MODE_DIRECT            = 1'b0;
+`ifdef SCR1_VECT_IRQ_EN
+parameter bit SCR1_CSR_MTVEC_MODE_VECTORED          = 1'b1;
+`endif // SCR1_VECT_IRQ_EN
+
+// MIE, MIP
+parameter int unsigned SCR1_CSR_MIE_MSIE_OFFSET     = 3;
+parameter int unsigned SCR1_CSR_MIE_MTIE_OFFSET     = 7;
+parameter int unsigned SCR1_CSR_MIE_MEIE_OFFSET     = 11;
+
+`ifdef SCR1_CSR_MCOUNTEN_EN
+// MCOUNTEN
+parameter int unsigned SCR1_CSR_MCOUNTEN_CY_OFFSET  = 0;
+parameter int unsigned SCR1_CSR_MCOUNTEN_IR_OFFSET  = 2;
+`endif // SCR1_CSR_MCOUNTEN_EN
+
+// MCAUSE
+typedef logic [`SCR1_XLEN-2:0]      type_scr1_csr_mcause_ec_v;
+
+// MCYCLE, MINSTRET
+`ifdef SCR1_CSR_REDUCED_CNT
+parameter int unsigned SCR1_CSR_COUNTERS_WIDTH      = 32;
+`else // ~SCR1_CSR_REDUCED_CNT
+parameter int unsigned SCR1_CSR_COUNTERS_WIDTH      = 64;
+`endif // ~SCR1_CSR_REDUCED_CNT
+
+// HPM
+parameter bit [6:0] SCR1_CSR_ADDR_HPMCOUNTER_MASK   = 7'b1100000;
+parameter bit [6:0] SCR1_CSR_ADDR_HPMCOUNTERH_MASK  = 7'b1100100;
+parameter bit [6:0] SCR1_CSR_ADDR_MHPMCOUNTER_MASK  = 7'b1011000;
+parameter bit [6:0] SCR1_CSR_ADDR_MHPMCOUNTERH_MASK = 7'b1011100;
+parameter bit [6:0] SCR1_CSR_ADDR_MHPMEVENT_MASK    = 7'b0011001;
+
+//-------------------------------------------------------------------------------
+// Types declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {
+    SCR1_CSR_RESP_OK,
+    SCR1_CSR_RESP_ER,
+    SCR1_CSR_RESP_ERROR = 'x
+} type_scr1_csr_resp_e;
+
+`endif // SCR1_CSR_SVH
diff --git a/third_party/tests/Scr1/src/includes/scr1_dm.svh b/third_party/tests/Scr1/src/includes/scr1_dm.svh
new file mode 100644
index 0000000..c5422d6
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_dm.svh
@@ -0,0 +1,134 @@
+`ifndef SCR1_INCLUDE_DM_DEFS
+`define SCR1_INCLUDE_DM_DEFS
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_dm.svh>
+/// @brief      Debug Module header file
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_hdu.svh"
+`include "scr1_csr.svh"
+
+parameter SCR1_DBG_DMI_ADDR_WIDTH                  = 6'd7;
+parameter SCR1_DBG_DMI_DATA_WIDTH                  = 6'd32;
+parameter SCR1_DBG_DMI_OP_WIDTH                    = 2'd2;
+                                                                    
+parameter SCR1_DBG_DMI_CH_ID_WIDTH                 = 2'd2;
+parameter SCR1_DBG_DMI_DR_DTMCS_WIDTH              = 6'd32;
+parameter SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH         = SCR1_DBG_DMI_OP_WIDTH +
+                                                     SCR1_DBG_DMI_DATA_WIDTH +
+                                                     SCR1_DBG_DMI_ADDR_WIDTH;
+
+// Debug Module addresses
+parameter SCR1_DBG_DATA0                           = 7'h4;
+parameter SCR1_DBG_DATA1                           = 7'h5;
+parameter SCR1_DBG_DMCONTROL                       = 7'h10;
+parameter SCR1_DBG_DMSTATUS                        = 7'h11;
+parameter SCR1_DBG_HARTINFO                        = 7'h12;
+parameter SCR1_DBG_ABSTRACTCS                      = 7'h16;
+parameter SCR1_DBG_COMMAND                         = 7'h17;
+parameter SCR1_DBG_ABSTRACTAUTO                    = 7'h18;
+parameter SCR1_DBG_PROGBUF0                        = 7'h20;
+parameter SCR1_DBG_PROGBUF1                        = 7'h21;
+parameter SCR1_DBG_PROGBUF2                        = 7'h22;
+parameter SCR1_DBG_PROGBUF3                        = 7'h23;
+parameter SCR1_DBG_PROGBUF4                        = 7'h24;
+parameter SCR1_DBG_PROGBUF5                        = 7'h25;
+parameter SCR1_DBG_HALTSUM0                        = 7'h40;
+
+// DMCONTROL
+parameter SCR1_DBG_DMCONTROL_HALTREQ               = 5'd31;
+parameter SCR1_DBG_DMCONTROL_RESUMEREQ             = 5'd30;
+parameter SCR1_DBG_DMCONTROL_HARTRESET             = 5'd29;
+parameter SCR1_DBG_DMCONTROL_ACKHAVERESET          = 5'd28;
+parameter SCR1_DBG_DMCONTROL_RESERVEDB             = 5'd27;
+parameter SCR1_DBG_DMCONTROL_HASEL                 = 5'd26;
+parameter SCR1_DBG_DMCONTROL_HARTSELLO_HI          = 5'd25;
+parameter SCR1_DBG_DMCONTROL_HARTSELLO_LO          = 5'd16;
+parameter SCR1_DBG_DMCONTROL_HARTSELHI_HI          = 5'd15;
+parameter SCR1_DBG_DMCONTROL_HARTSELHI_LO          = 5'd6;
+parameter SCR1_DBG_DMCONTROL_RESERVEDA_HI          = 5'd5;
+parameter SCR1_DBG_DMCONTROL_RESERVEDA_LO          = 5'd2;
+parameter SCR1_DBG_DMCONTROL_NDMRESET              = 5'd1;
+parameter SCR1_DBG_DMCONTROL_DMACTIVE              = 5'd0;
+
+// DMSTATUS
+parameter SCR1_DBG_DMSTATUS_RESERVEDC_HI           = 5'd31;
+parameter SCR1_DBG_DMSTATUS_RESERVEDC_LO           = 5'd23;
+parameter SCR1_DBG_DMSTATUS_IMPEBREAK              = 5'd22;
+parameter SCR1_DBG_DMSTATUS_RESERVEDB_HI           = 5'd21;
+parameter SCR1_DBG_DMSTATUS_RESERVEDB_LO           = 5'd20;
+parameter SCR1_DBG_DMSTATUS_ALLHAVERESET           = 5'd19;
+parameter SCR1_DBG_DMSTATUS_ANYHAVERESET           = 5'd18;
+parameter SCR1_DBG_DMSTATUS_ALLRESUMEACK           = 5'd17;
+parameter SCR1_DBG_DMSTATUS_ANYRESUMEACK           = 5'd16;
+parameter SCR1_DBG_DMSTATUS_ALLNONEXISTENT         = 5'd15;
+parameter SCR1_DBG_DMSTATUS_ANYNONEXISTENT         = 5'd14;
+parameter SCR1_DBG_DMSTATUS_ALLUNAVAIL             = 5'd13;
+parameter SCR1_DBG_DMSTATUS_ANYUNAVAIL             = 5'd12;
+parameter SCR1_DBG_DMSTATUS_ALLRUNNING             = 5'd11;
+parameter SCR1_DBG_DMSTATUS_ANYRUNNING             = 5'd10;
+parameter SCR1_DBG_DMSTATUS_ALLHALTED              = 5'd9;
+parameter SCR1_DBG_DMSTATUS_ANYHALTED              = 5'd8;
+parameter SCR1_DBG_DMSTATUS_AUTHENTICATED          = 5'd7;
+parameter SCR1_DBG_DMSTATUS_AUTHBUSY               = 5'd6;
+parameter SCR1_DBG_DMSTATUS_RESERVEDA              = 5'd5;
+parameter SCR1_DBG_DMSTATUS_DEVTREEVALID           = 5'd4;
+parameter SCR1_DBG_DMSTATUS_VERSION_HI             = 5'd3;
+parameter SCR1_DBG_DMSTATUS_VERSION_LO             = 5'd0;
+
+// COMMANDS
+parameter SCR1_DBG_COMMAND_TYPE_HI                 = 5'd31;
+parameter SCR1_DBG_COMMAND_TYPE_LO                 = 5'd24;
+
+parameter SCR1_DBG_COMMAND_ACCESSREG_RESERVEDB     = 5'd23;
+parameter SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI       = 5'd22;
+parameter SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO       = 5'd20;
+parameter SCR1_DBG_COMMAND_ACCESSREG_RESERVEDA     = 5'd19;
+parameter SCR1_DBG_COMMAND_ACCESSREG_POSTEXEC      = 5'd18;
+parameter SCR1_DBG_COMMAND_ACCESSREG_TRANSFER      = 5'd17;
+parameter SCR1_DBG_COMMAND_ACCESSREG_WRITE         = 5'd16;
+parameter SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI      = 5'd15;
+parameter SCR1_DBG_COMMAND_ACCESSREG_REGNO_LO      = 5'd0;
+
+parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMVIRTUAL    = 5'd23;
+parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_HI    = 5'd22;
+parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_LO    = 5'd20;
+parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMPOSTINC    = 5'd19;
+parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI  = 5'd18;
+parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_LO  = 5'd17;
+parameter SCR1_DBG_COMMAND_ACCESSMEM_WRITE         = 5'd16;
+parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI  = 5'd13;
+parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_LO  = 5'd0;
+
+// ABSTRACTCS
+parameter SCR1_DBG_ABSTRACTCS_RESERVEDD_HI         = 5'd31;
+parameter SCR1_DBG_ABSTRACTCS_RESERVEDD_LO         = 5'd29;
+parameter SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_HI       = 5'd28;
+parameter SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_LO       = 5'd24;
+parameter SCR1_DBG_ABSTRACTCS_RESERVEDC_HI         = 5'd23;
+parameter SCR1_DBG_ABSTRACTCS_RESERVEDC_LO         = 5'd13;
+parameter SCR1_DBG_ABSTRACTCS_BUSY                 = 5'd12;
+parameter SCR1_DBG_ABSTRACTCS_RESERVEDB            = 5'd11;
+parameter SCR1_DBG_ABSTRACTCS_CMDERR_HI            = 5'd10;
+parameter SCR1_DBG_ABSTRACTCS_CMDERR_LO            = 5'd8;
+parameter SCR1_DBG_ABSTRACTCS_RESERVEDA_HI         = 5'd7;
+parameter SCR1_DBG_ABSTRACTCS_RESERVEDA_LO         = 5'd4;
+parameter SCR1_DBG_ABSTRACTCS_DATACOUNT_HI         = 5'd3;
+parameter SCR1_DBG_ABSTRACTCS_DATACOUNT_LO         = 5'd0;
+    
+// HARTINFO 
+parameter SCR1_DBG_HARTINFO_RESERVEDB_HI           = 5'd31;
+parameter SCR1_DBG_HARTINFO_RESERVEDB_LO           = 5'd24;
+parameter SCR1_DBG_HARTINFO_NSCRATCH_HI            = 5'd23;
+parameter SCR1_DBG_HARTINFO_NSCRATCH_LO            = 5'd20;
+parameter SCR1_DBG_HARTINFO_RESERVEDA_HI           = 5'd19;
+parameter SCR1_DBG_HARTINFO_RESERVEDA_LO           = 5'd17;
+parameter SCR1_DBG_HARTINFO_DATAACCESS             = 5'd16;
+parameter SCR1_DBG_HARTINFO_DATASIZE_HI            = 5'd15;
+parameter SCR1_DBG_HARTINFO_DATASIZE_LO            = 5'd12;
+parameter SCR1_DBG_HARTINFO_DATAADDR_HI            = 5'd11;
+parameter SCR1_DBG_HARTINFO_DATAADDR_LO            = 5'd0;
+
+
+`endif // SCR1_INCLUDE_DM_DEFS
diff --git a/third_party/tests/Scr1/src/includes/scr1_hdu.svh b/third_party/tests/Scr1/src/includes/scr1_hdu.svh
new file mode 100644
index 0000000..baf7d72
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_hdu.svh
@@ -0,0 +1,148 @@
+`ifndef SCR1_INCLUDE_HDU_DEFS
+`define SCR1_INCLUDE_HDU_DEFS
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_pipe_hdu.svh>
+/// @brief      HART Debug Unit definitions file
+///
+
+
+`include "scr1_arch_description.svh"
+`include "scr1_csr.svh"
+
+`ifdef SCR1_MMU_EN
+ `define SCR1_HDU_FEATURE_MPRVEN
+`endif // SCR1_MMU_EN
+
+//==============================================================================
+// Parameters
+//==============================================================================
+//localparam int unsigned SCR1_HDU_DEBUGCSR_BASE_ADDR      = 12'h7B0;
+localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_SPAN      = SCR1_CSR_ADDR_HDU_MSPAN;
+localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_WIDTH     = $clog2(SCR1_HDU_DEBUGCSR_ADDR_SPAN);
+localparam bit [3:0]    SCR1_HDU_DEBUGCSR_DCSR_XDEBUGVER = 4'h4;
+localparam int unsigned SCR1_HDU_PBUF_ADDR_SPAN          = 8;
+localparam int unsigned SCR1_HDU_PBUF_ADDR_WIDTH         = $clog2(SCR1_HDU_PBUF_ADDR_SPAN);
+localparam int unsigned SCR1_HDU_DATA_REG_WIDTH          = 32;
+localparam int unsigned SCR1_HDU_CORE_INSTR_WIDTH        = 32;
+
+
+//==============================================================================
+// Types
+//==============================================================================
+
+// HART Debug States:
+typedef enum logic [1:0] {
+    SCR1_HDU_DBGSTATE_RESET         = 2'b00,
+    SCR1_HDU_DBGSTATE_RUN           = 2'b01,
+    SCR1_HDU_DBGSTATE_DHALTED       = 2'b10,
+    SCR1_HDU_DBGSTATE_DRUN          = 2'b11,
+    SCR1_HDU_DBGSTATE_XXX           = 'X
+} type_scr1_hdu_dbgstates_e;
+
+typedef enum logic [1:0] {
+    SCR1_HDU_PBUFSTATE_IDLE          = 2'b00,
+    SCR1_HDU_PBUFSTATE_FETCH         = 2'b01,
+    SCR1_HDU_PBUFSTATE_EXCINJECT     = 2'b10,
+    SCR1_HDU_PBUFSTATE_WAIT4END      = 2'b11,
+    SCR1_HDU_PBUFSTATE_XXX           = 'X
+} type_scr1_hdu_pbufstates_e;
+
+typedef enum logic {
+    SCR1_HDU_HARTCMD_RESUME         = 1'b0,
+    SCR1_HDU_HARTCMD_HALT           = 1'b1,
+    SCR1_HDU_HARTCMD_XXX            = 1'bX
+} type_scr1_hdu_hart_command_e;
+
+typedef enum logic {
+    SCR1_HDU_FETCH_SRC_NORMAL       = 1'b0,
+    SCR1_HDU_FETCH_SRC_PBUF         = 1'b1,
+    SCR1_HDU_FETCH_SRC_XXX          = 1'bX
+} type_scr1_hdu_fetch_src_e;
+
+typedef struct packed {
+    //logic                               reset_n;
+    logic                               except;
+    logic                               ebreak;
+    type_scr1_hdu_dbgstates_e           dbg_state;
+} type_scr1_hdu_hartstatus_s;
+
+// Debug Mode Redirection control:
+typedef struct packed {
+    logic                               sstep;          // Single Step
+    logic                               ebreak;         // Redirection after EBREAK execution
+} type_scr1_hdu_redirect_s;
+
+typedef struct packed {
+    logic                               irq_dsbl;
+    type_scr1_hdu_fetch_src_e           fetch_src;
+    logic                               pc_advmt_dsbl;
+    logic                               hwbrkpt_dsbl;
+    type_scr1_hdu_redirect_s            redirect;
+} type_scr1_hdu_runctrl_s;
+
+// HART Halt Status:
+typedef enum logic [2:0] {
+    SCR1_HDU_HALTCAUSE_NONE         = 3'b000,
+    SCR1_HDU_HALTCAUSE_EBREAK       = 3'b001,
+    SCR1_HDU_HALTCAUSE_TMREQ        = 3'b010,
+    SCR1_HDU_HALTCAUSE_DMREQ        = 3'b011,
+    SCR1_HDU_HALTCAUSE_SSTEP        = 3'b100,
+    SCR1_HDU_HALTCAUSE_RSTEXIT      = 3'b101,
+    SCR1_HDU_HALTCAUSE_XXX          = 'X
+} type_scr1_hdu_haltcause_e;
+
+typedef struct packed {
+    logic                               except;
+    type_scr1_hdu_haltcause_e           cause;
+} type_scr1_hdu_haltstatus_s;
+
+
+// Debug CSR map
+localparam SCR1_HDU_DBGCSR_OFFS_DCSR       = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd0 );
+localparam SCR1_HDU_DBGCSR_OFFS_DPC        = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd1 );
+localparam SCR1_HDU_DBGCSR_OFFS_DSCRATCH0  = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd2 );
+localparam SCR1_HDU_DBGCSR_OFFS_DSCRATCH1  = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd3 );
+
+localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DCSR      = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DCSR;
+localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DPC       = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DPC;
+localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH0 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH0;
+localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH1;
+
+// Debug CSRs :: DCSR
+typedef enum int {
+    SCR1_HDU_DCSR_PRV_BIT_R         = 0,
+    SCR1_HDU_DCSR_PRV_BIT_L         = 1,
+    SCR1_HDU_DCSR_STEP_BIT          = 2,
+    SCR1_HDU_DCSR_RSRV0_BIT_R       = 3,
+    SCR1_HDU_DCSR_RSRV0_BIT_L       = 5,
+    SCR1_HDU_DCSR_CAUSE_BIT_R       = 6,
+    SCR1_HDU_DCSR_CAUSE_BIT_L       = 8,
+    SCR1_HDU_DCSR_RSRV1_BIT_R       = 9,
+    SCR1_HDU_DCSR_RSRV1_BIT_L       = 10,
+    SCR1_HDU_DCSR_STEPIE_BIT        = 11,
+    SCR1_HDU_DCSR_RSRV2_BIT_R       = 12,
+    SCR1_HDU_DCSR_RSRV2_BIT_L       = 14,
+    SCR1_HDU_DCSR_EBREAKM_BIT       = 15,
+    SCR1_HDU_DCSR_RSRV3_BIT_R       = 16,
+    SCR1_HDU_DCSR_RSRV3_BIT_L       = 27,
+    SCR1_HDU_DCSR_XDEBUGVER_BIT_R   = 28,
+    SCR1_HDU_DCSR_XDEBUGVER_BIT_L   = 31
+} type_scr1_hdu_dcsr_bits_e;
+
+//localparam int unsigned SCR1_HDU_DEBUGCSR_DCSR_PRV_WIDTH = SCR1_HDU_DCSR_PRV_BIT_L-SCR1_HDU_DCSR_PRV_BIT_R+1;
+
+typedef struct packed {
+    logic [SCR1_HDU_DCSR_XDEBUGVER_BIT_L-SCR1_HDU_DCSR_XDEBUGVER_BIT_R:0]   xdebugver;
+    logic [SCR1_HDU_DCSR_RSRV3_BIT_L-SCR1_HDU_DCSR_RSRV3_BIT_R:0]           rsrv3;
+    logic                                                                   ebreakm;
+    logic [SCR1_HDU_DCSR_RSRV2_BIT_L-SCR1_HDU_DCSR_RSRV2_BIT_R:0]           rsrv2;
+    logic                                                                   stepie;
+    logic [SCR1_HDU_DCSR_RSRV1_BIT_L-SCR1_HDU_DCSR_RSRV1_BIT_R:0]           rsrv1;
+    logic [SCR1_HDU_DCSR_CAUSE_BIT_L-SCR1_HDU_DCSR_CAUSE_BIT_R:0]           cause;
+    logic [SCR1_HDU_DCSR_RSRV0_BIT_L-SCR1_HDU_DCSR_RSRV0_BIT_R:0]           rsrv0;
+    logic                                                                   step;
+    logic [SCR1_HDU_DCSR_PRV_BIT_L-SCR1_HDU_DCSR_PRV_BIT_R:0]               prv;
+} type_scr1_hdu_dcsr_s;
+
+
+`endif // SCR1_INCLUDE_HDU_DEFS
diff --git a/third_party/tests/Scr1/src/includes/scr1_ipic.svh b/third_party/tests/Scr1/src/includes/scr1_ipic.svh
new file mode 100644
index 0000000..cc18ead
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_ipic.svh
@@ -0,0 +1,52 @@
+`ifndef SCR1_IPIC_SVH
+`define SCR1_IPIC_SVH
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_ipic.svh>
+/// @brief      IPIC header file
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_IPIC_EN
+//-------------------------------------------------------------------------------
+// Parameters declaration
+//-------------------------------------------------------------------------------
+parameter                                   SCR1_IRQ_VECT_NUM       = 16;   // must be power of 2 in the current implementation
+parameter                                   SCR1_IRQ_VECT_WIDTH     = $clog2(SCR1_IRQ_VECT_NUM+1);
+parameter                                   SCR1_IRQ_LINES_NUM      = SCR1_IRQ_VECT_NUM;
+parameter                                   SCR1_IRQ_LINES_WIDTH    = $clog2(SCR1_IRQ_LINES_NUM);
+parameter   logic [SCR1_IRQ_VECT_WIDTH-1:0] SCR1_IRQ_VOID_VECT_NUM  = SCR1_IRQ_VECT_WIDTH'(SCR1_IRQ_VECT_NUM);
+parameter                                   SCR1_IRQ_IDX_WIDTH      = $clog2(SCR1_IRQ_VECT_NUM);
+
+// Address decoding parameters
+parameter   logic [2:0]                     SCR1_IPIC_CISV          = 3'h0;    // RO
+parameter   logic [2:0]                     SCR1_IPIC_CICSR         = 3'h1;    // {IP, IE}
+parameter   logic [2:0]                     SCR1_IPIC_IPR           = 3'h2;    // RW1C
+parameter   logic [2:0]                     SCR1_IPIC_ISVR          = 3'h3;    // RO
+parameter   logic [2:0]                     SCR1_IPIC_EOI           = 3'h4;    // RZW
+parameter   logic [2:0]                     SCR1_IPIC_SOI           = 3'h5;    // RZW
+parameter   logic [2:0]                     SCR1_IPIC_IDX           = 3'h6;    // RW
+parameter   logic [2:0]                     SCR1_IPIC_ICSR          = 3'h7;    // RW
+
+parameter                                   SCR1_IPIC_ICSR_IP       = 0;
+parameter                                   SCR1_IPIC_ICSR_IE       = 1;
+parameter                                   SCR1_IPIC_ICSR_IM       = 2;
+parameter                                   SCR1_IPIC_ICSR_INV      = 3;
+parameter                                   SCR1_IPIC_ICSR_IS       = 4;
+parameter                                   SCR1_IPIC_ICSR_PRV_LSB  = 8;
+parameter                                   SCR1_IPIC_ICSR_PRV_MSB  = 9;
+parameter                                   SCR1_IPIC_ICSR_LN_LSB   = 12;
+
+parameter   logic [1:0]                     SCR1_IPIC_PRV_M         = 2'b11;
+
+//-------------------------------------------------------------------------------
+// Types declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {
+    SCR1_CSR2IPIC_RD,
+    SCR1_CSR2IPIC_WR,
+    SCR1_CSR2IPIC_ERROR = 'x
+} type_scr1_csr2ipic_wr_e;
+
+`endif // SCR1_IPIC_EN
+`endif // SCR1_IPIC_SVH
diff --git a/third_party/tests/Scr1/src/includes/scr1_memif.svh b/third_party/tests/Scr1/src/includes/scr1_memif.svh
new file mode 100644
index 0000000..0a9dbd5
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_memif.svh
@@ -0,0 +1,39 @@
+`ifndef SCR1_MEMIF_SVH
+`define SCR1_MEMIF_SVH
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_memif.svh>
+/// @brief      Memory interface definitions file
+///
+
+`include "scr1_arch_description.svh"
+
+//-------------------------------------------------------------------------------
+// Memory command enum
+//-------------------------------------------------------------------------------
+typedef enum logic {
+    SCR1_MEM_CMD_RD     = 1'b0,
+    SCR1_MEM_CMD_WR     = 1'b1,
+    SCR1_MEM_CMD_ERROR  = 'x
+} type_scr1_mem_cmd_e;
+
+//-------------------------------------------------------------------------------
+// Memory data width enum
+//-------------------------------------------------------------------------------
+typedef enum logic[1:0] {
+    SCR1_MEM_WIDTH_BYTE     = 2'b00,
+    SCR1_MEM_WIDTH_HWORD    = 2'b01,
+    SCR1_MEM_WIDTH_WORD     = 2'b10,
+    SCR1_MEM_WIDTH_ERROR    = 'x
+} type_scr1_mem_width_e;
+
+//-------------------------------------------------------------------------------
+// Memory response enum
+//-------------------------------------------------------------------------------
+typedef enum logic[1:0] {
+    SCR1_MEM_RESP_NOTRDY    = 2'b00,
+    SCR1_MEM_RESP_RDY_OK    = 2'b01,
+    SCR1_MEM_RESP_RDY_ER    = 2'b10,
+    SCR1_MEM_RESP_ERROR     = 'x
+} type_scr1_mem_resp_e;
+
+`endif // SCR1_MEMIF_SVH
diff --git a/third_party/tests/Scr1/src/includes/scr1_riscv_isa_decoding.svh b/third_party/tests/Scr1/src/includes/scr1_riscv_isa_decoding.svh
new file mode 100644
index 0000000..ca56879
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_riscv_isa_decoding.svh
@@ -0,0 +1,181 @@
+`ifndef SCR1_RISCV_ISA_DECODING_SVH
+`define SCR1_RISCV_ISA_DECODING_SVH
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_riscv_isa_decoding.svh>
+/// @brief      RISC-V ISA definitions file
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_arch_types.svh"
+
+//-------------------------------------------------------------------------------
+// Instruction types
+//-------------------------------------------------------------------------------
+typedef enum logic [1:0] {
+    SCR1_INSTR_RVC0     = 2'b00,
+    SCR1_INSTR_RVC1     = 2'b01,
+    SCR1_INSTR_RVC2     = 2'b10,
+    SCR1_INSTR_RVI      = 2'b11
+} type_scr1_instr_type_e;
+
+//-------------------------------------------------------------------------------
+// RV32I opcodes (bits 6:2)
+//-------------------------------------------------------------------------------
+typedef enum logic [6:2] {
+    SCR1_OPCODE_LOAD        = 5'b00000,
+    SCR1_OPCODE_MISC_MEM    = 5'b00011,
+    SCR1_OPCODE_OP_IMM      = 5'b00100,
+    SCR1_OPCODE_AUIPC       = 5'b00101,
+    SCR1_OPCODE_STORE       = 5'b01000,
+    SCR1_OPCODE_OP          = 5'b01100,
+    SCR1_OPCODE_LUI         = 5'b01101,
+    SCR1_OPCODE_BRANCH      = 5'b11000,
+    SCR1_OPCODE_JALR        = 5'b11001,
+    SCR1_OPCODE_JAL         = 5'b11011,
+    SCR1_OPCODE_SYSTEM      = 5'b11100
+} type_scr1_rvi_opcode_e;
+
+
+//-------------------------------------------------------------------------------
+// IALU main operands
+//-------------------------------------------------------------------------------
+localparam SCR1_IALU_OP_ALL_NUM_E = 2;
+localparam SCR1_IALU_OP_WIDTH_E   = $clog2(SCR1_IALU_OP_ALL_NUM_E);
+typedef enum logic [SCR1_IALU_OP_WIDTH_E-1:0] {
+    SCR1_IALU_OP_REG_IMM,          // op1 = rs1; op2 = imm
+    SCR1_IALU_OP_REG_REG           // op1 = rs1; op2 = rs2
+} type_scr1_ialu_op_sel_e;
+
+//-------------------------------------------------------------------------------
+// IALU main commands
+//-------------------------------------------------------------------------------
+`ifdef SCR1_RVM_EXT
+localparam SCR1_IALU_CMD_ALL_NUM_E    = 23;
+`else // ~SCR1_RVM_EXT
+localparam SCR1_IALU_CMD_ALL_NUM_E    = 15;
+`endif // ~SCR1_RVM_EXT
+localparam SCR1_IALU_CMD_WIDTH_E      = $clog2(SCR1_IALU_CMD_ALL_NUM_E);
+typedef enum logic [SCR1_IALU_CMD_WIDTH_E-1:0] {
+    SCR1_IALU_CMD_NONE  = '0,   // IALU disable
+    SCR1_IALU_CMD_AND,          // op1 & op2
+    SCR1_IALU_CMD_OR,           // op1 | op2
+    SCR1_IALU_CMD_XOR,          // op1 ^ op2
+    SCR1_IALU_CMD_ADD,          // op1 + op2
+    SCR1_IALU_CMD_SUB,          // op1 - op2
+    SCR1_IALU_CMD_SUB_LT,       // op1 < op2
+    SCR1_IALU_CMD_SUB_LTU,      // op1 u< op2
+    SCR1_IALU_CMD_SUB_EQ,       // op1 = op2
+    SCR1_IALU_CMD_SUB_NE,       // op1 != op2
+    SCR1_IALU_CMD_SUB_GE,       // op1 >= op2
+    SCR1_IALU_CMD_SUB_GEU,      // op1 u>= op2
+    SCR1_IALU_CMD_SLL,          // op1 << op2
+    SCR1_IALU_CMD_SRL,          // op1 >> op2
+    SCR1_IALU_CMD_SRA           // op1 >>> op2
+`ifdef SCR1_RVM_EXT
+    ,
+    SCR1_IALU_CMD_MUL,          // low(unsig(op1) * unsig(op2))
+    SCR1_IALU_CMD_MULHU,        // high(unsig(op1) * unsig(op2))
+    SCR1_IALU_CMD_MULHSU,       // high(op1 * unsig(op2))
+    SCR1_IALU_CMD_MULH,         // high(op1 * op2)
+    SCR1_IALU_CMD_DIV,          // op1 / op2
+    SCR1_IALU_CMD_DIVU,         // op1 u/ op2
+    SCR1_IALU_CMD_REM,          // op1 % op2
+    SCR1_IALU_CMD_REMU          // op1 u% op2
+`endif  // SCR1_RVM_EXT
+} type_scr1_ialu_cmd_sel_e;
+
+//-------------------------------------------------------------------------------
+// IALU SUM2 operands (result is JUMP/BRANCH target, LOAD/STORE address)
+//-------------------------------------------------------------------------------
+localparam SCR1_SUM2_OP_ALL_NUM_E    = 2;
+localparam SCR1_SUM2_OP_WIDTH_E      = $clog2(SCR1_SUM2_OP_ALL_NUM_E);
+typedef enum logic [SCR1_SUM2_OP_WIDTH_E-1:0] {
+    SCR1_SUM2_OP_PC_IMM,            // op1 = curr_pc; op2 = imm (AUIPC, target new_pc for JAL and branches)
+    SCR1_SUM2_OP_REG_IMM,           // op1 = rs1; op2 = imm (target new_pc for JALR, LOAD/STORE address)
+    SCR1_SUM2_OP_ERROR = 'x
+} type_scr1_ialu_sum2_op_sel_e;
+
+//-------------------------------------------------------------------------------
+// LSU commands
+//-------------------------------------------------------------------------------
+localparam SCR1_LSU_CMD_ALL_NUM_E   = 9;
+localparam SCR1_LSU_CMD_WIDTH_E     = $clog2(SCR1_LSU_CMD_ALL_NUM_E);
+typedef enum logic [SCR1_LSU_CMD_WIDTH_E-1:0] {
+    SCR1_LSU_CMD_NONE = '0,
+    SCR1_LSU_CMD_LB,
+    SCR1_LSU_CMD_LH,
+    SCR1_LSU_CMD_LW,
+    SCR1_LSU_CMD_LBU,
+    SCR1_LSU_CMD_LHU,
+    SCR1_LSU_CMD_SB,
+    SCR1_LSU_CMD_SH,
+    SCR1_LSU_CMD_SW
+} type_scr1_lsu_cmd_sel_e;
+
+//-------------------------------------------------------------------------------
+// CSR operands
+//-------------------------------------------------------------------------------
+localparam SCR1_CSR_OP_ALL_NUM_E   = 2;
+localparam SCR1_CSR_OP_WIDTH_E     = $clog2(SCR1_CSR_OP_ALL_NUM_E);
+typedef enum logic [SCR1_CSR_OP_WIDTH_E-1:0] {
+    SCR1_CSR_OP_IMM,
+    SCR1_CSR_OP_REG
+} type_scr1_csr_op_sel_e;
+
+//-------------------------------------------------------------------------------
+// CSR commands
+//-------------------------------------------------------------------------------
+localparam SCR1_CSR_CMD_ALL_NUM_E   = 4;
+localparam SCR1_CSR_CMD_WIDTH_E     = $clog2(SCR1_CSR_CMD_ALL_NUM_E);
+typedef enum logic [SCR1_CSR_CMD_WIDTH_E-1:0] {
+    SCR1_CSR_CMD_NONE = '0,
+    SCR1_CSR_CMD_WRITE,
+    SCR1_CSR_CMD_SET,
+    SCR1_CSR_CMD_CLEAR
+} type_scr1_csr_cmd_sel_e;
+
+//-------------------------------------------------------------------------------
+// MPRF rd writeback source
+//-------------------------------------------------------------------------------
+localparam SCR1_RD_WB_ALL_NUM_E = 7;
+localparam SCR1_RD_WB_WIDTH_E   = $clog2(SCR1_RD_WB_ALL_NUM_E);
+typedef enum logic [SCR1_RD_WB_WIDTH_E-1:0] {
+    SCR1_RD_WB_NONE = '0,
+    SCR1_RD_WB_IALU,            // IALU main result
+    SCR1_RD_WB_SUM2,            // IALU SUM2 result (AUIPC)
+    SCR1_RD_WB_IMM,             // LUI
+    SCR1_RD_WB_INC_PC,          // JAL(R)
+    SCR1_RD_WB_LSU,             // Load from DMEM
+    SCR1_RD_WB_CSR              // Read CSR
+} type_scr1_rd_wb_sel_e;
+
+//-------------------------------------------------------------------------------
+// IDU to EXU full command structure
+//-------------------------------------------------------------------------------
+localparam SCR1_GPR_FIELD_WIDTH = 5;
+
+typedef struct packed {
+    logic                               instr_rvc;      // used with a different meaning for IFU access fault exception
+    type_scr1_ialu_op_sel_e             ialu_op;
+    type_scr1_ialu_cmd_sel_e            ialu_cmd;
+    type_scr1_ialu_sum2_op_sel_e        sum2_op;
+    type_scr1_lsu_cmd_sel_e             lsu_cmd;
+    type_scr1_csr_op_sel_e              csr_op;
+    type_scr1_csr_cmd_sel_e             csr_cmd;
+    type_scr1_rd_wb_sel_e               rd_wb_sel;
+    logic                               jump_req;
+    logic                               branch_req;
+    logic                               mret_req;
+    logic                               fencei_req;
+    logic                               wfi_req;
+    logic [SCR1_GPR_FIELD_WIDTH-1:0]    rs1_addr;       // used as zimm for CSRRxI instructions
+    logic [SCR1_GPR_FIELD_WIDTH-1:0]    rs2_addr;
+    logic [SCR1_GPR_FIELD_WIDTH-1:0]    rd_addr;
+    logic [`SCR1_XLEN-1:0]              imm;            // used as {funct3, CSR address} for CSR instructions
+                                                        // used as instruction field for illegal instruction exception
+    logic                               exc_req;
+    type_scr1_exc_code_e                exc_code;
+} type_scr1_exu_cmd_s;
+
+`endif // SCR1_RISCV_ISA_DECODING_SVH
+
diff --git a/third_party/tests/Scr1/src/includes/scr1_search_ms1.svh b/third_party/tests/Scr1/src/includes/scr1_search_ms1.svh
new file mode 100644
index 0000000..d29cc52
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_search_ms1.svh
@@ -0,0 +1,93 @@
+`ifndef SCR1_SEARCH_MS1_SVH
+`define SCR1_SEARCH_MS1_SVH
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_search_ms1.svh>
+/// @brief      Most significant one search function
+///
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+typedef struct {
+    logic       vd;
+    logic       idx;
+} type_scr1_search_one_2_s;
+
+typedef struct {
+    logic           vd;
+    logic [4:0]     idx;
+} type_scr1_search_one_32_s;
+
+//-------------------------------------------------------------------------------
+// Leading Zeros Count Function
+//-------------------------------------------------------------------------------
+function automatic type_scr1_search_one_2_s scr1_lead_zeros_cnt_2(
+    input   logic [1:0]     din
+);
+    type_scr1_search_one_2_s tmp;
+begin
+    tmp.vd  = |din;
+    tmp.idx = ~din[1];
+    return  tmp;
+end
+endfunction : scr1_lead_zeros_cnt_2
+
+function automatic logic [4:0] scr1_lead_zeros_cnt_32(
+    input   logic [31:0]    din
+);
+begin
+    logic [15:0]    stage1_vd;
+    logic [7:0]     stage2_vd;
+    logic [3:0]     stage3_vd;
+    logic [1:0]     stage4_vd;
+
+    logic           stage1_idx [15:0];
+    logic [1:0]     stage2_idx [7:0];
+    logic [2:0]     stage3_idx [3:0];
+    logic [3:0]     stage4_idx [1:0];
+    type_scr1_search_one_32_s tmp;
+    logic [4:0]     res;
+
+    // Stage 1
+    for (int unsigned i=0; i<16; ++i) begin
+        type_scr1_search_one_2_s tmp;
+        tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]);
+        stage1_vd[i]  = tmp.vd;
+        stage1_idx[i] = tmp.idx;
+    end
+
+    // Stage 2
+    for (int unsigned i=0; i<8; ++i) begin
+        type_scr1_search_one_2_s tmp;
+        tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]);
+        stage2_vd[i]  = tmp.vd;
+        stage2_idx[i] = (tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]};
+    end
+
+    // Stage 3
+    for (int unsigned i=0; i<4; ++i) begin
+        type_scr1_search_one_2_s tmp;
+        tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]);
+        stage3_vd[i]  = tmp.vd;
+        stage3_idx[i] = (tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]};
+    end
+
+    // Stage 4
+    for (int unsigned i=0; i<2; ++i) begin
+        type_scr1_search_one_2_s tmp;
+        tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]);
+        stage4_vd[i]  = tmp.vd;
+        stage4_idx[i] = (tmp.idx) ? {tmp.idx, stage3_idx[2*i]} : {tmp.idx, stage3_idx[2*i+1]};
+    end
+
+    // Stage 5
+    tmp.vd = |stage4_vd;
+    tmp.idx = (stage4_vd[1]) ? {1'b0, stage4_idx[1]} : {1'b1, stage4_idx[0]};
+
+    res = tmp.idx;
+
+    return res;
+end
+endfunction : scr1_lead_zeros_cnt_32
+
+`endif // SCR1_SEARCH_MS1_SVH
diff --git a/third_party/tests/Scr1/src/includes/scr1_tapc.svh b/third_party/tests/Scr1/src/includes/scr1_tapc.svh
new file mode 100644
index 0000000..fb013b9
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_tapc.svh
@@ -0,0 +1,59 @@
+`ifndef SCR1_INCLUDE_TAPC_DEFS
+`define SCR1_INCLUDE_TAPC_DEFS
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_tapc.svh>
+/// @brief      TAPC header file
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_DBGC_EN
+
+//==============================================================================
+// Parameters
+//==============================================================================
+localparam int unsigned                         SCR1_TAP_STATE_WIDTH            = 4;
+localparam int unsigned                         SCR1_TAP_INSTRUCTION_WIDTH      = 5;
+localparam int unsigned                         SCR1_TAP_DR_IDCODE_WIDTH        = 32;
+localparam int unsigned                         SCR1_TAP_DR_BLD_ID_WIDTH        = 32;
+localparam int unsigned                         SCR1_TAP_DR_BYPASS_WIDTH        = 1;
+//localparam bit [SCR1_TAP_DR_IDCODE_WIDTH-1:0]   SCR1_TAP_IDCODE_RISCV_SC        = `SCR1_TAP_IDCODE;
+localparam bit [SCR1_TAP_DR_BLD_ID_WIDTH-1:0]   SCR1_TAP_BLD_ID_VALUE           = `SCR1_MIMPID;
+
+//==============================================================================
+// Types
+//==============================================================================
+typedef enum logic [SCR1_TAP_STATE_WIDTH-1:0] {
+    SCR1_TAP_STATE_RESET,
+    SCR1_TAP_STATE_IDLE,
+    SCR1_TAP_STATE_DR_SEL_SCAN,
+    SCR1_TAP_STATE_DR_CAPTURE,
+    SCR1_TAP_STATE_DR_SHIFT,
+    SCR1_TAP_STATE_DR_EXIT1,
+    SCR1_TAP_STATE_DR_PAUSE,
+    SCR1_TAP_STATE_DR_EXIT2,
+    SCR1_TAP_STATE_DR_UPDATE,
+    SCR1_TAP_STATE_IR_SEL_SCAN,
+    SCR1_TAP_STATE_IR_CAPTURE,
+    SCR1_TAP_STATE_IR_SHIFT,
+    SCR1_TAP_STATE_IR_EXIT1,
+    SCR1_TAP_STATE_IR_PAUSE,
+    SCR1_TAP_STATE_IR_EXIT2,
+    SCR1_TAP_STATE_IR_UPDATE,
+    SCR1_TAP_STATE_XXX       = 'X
+} type_scr1_tap_state_e;
+
+typedef enum logic [SCR1_TAP_INSTRUCTION_WIDTH - 1:0] {
+    SCR1_TAP_INSTR_IDCODE            = 5'h01,
+    SCR1_TAP_INSTR_BLD_ID            = 5'h04,
+    SCR1_TAP_INSTR_SCU_ACCESS        = 5'h09,
+
+    SCR1_TAP_INSTR_DTMCS             = 5'h10,
+    SCR1_TAP_INSTR_DMI_ACCESS        = 5'h11,
+
+    SCR1_TAP_INSTR_BYPASS            = 5'h1F,
+    SCR1_TAP_INSTR_XXX               = 'X
+} type_scr1_tap_instr_e;
+
+`endif // SCR1_DBGC_EN
+`endif // SCR1_INCLUDE_TAPC_DEFS
diff --git a/third_party/tests/Scr1/src/includes/scr1_tdu.svh b/third_party/tests/Scr1/src/includes/scr1_tdu.svh
new file mode 100644
index 0000000..9a67c78
--- /dev/null
+++ b/third_party/tests/Scr1/src/includes/scr1_tdu.svh
@@ -0,0 +1,123 @@
+`ifndef SCR1_INCLUDE_TDU_DEFS
+`define SCR1_INCLUDE_TDU_DEFS
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_tdu.svh>
+/// @brief      Trigger Debug Module header
+///
+
+//`include "scr1_arch_description.svh"
+
+`ifdef SCR1_BRKM_EN
+//`include "scr1_csr.svh"
+
+`include "scr1_arch_description.svh"
+//`include "scr1_arch_types.svh"
+`include "scr1_csr.svh"
+
+parameter int unsigned  SCR1_TDU_MTRIG_NUM             = SCR1_BRKM_BRKPT_NUMBER;
+`ifdef SCR1_BRKM_BRKPT_ICOUNT_EN
+parameter int unsigned  SCR1_TDU_ALLTRIG_NUM           = SCR1_TDU_MTRIG_NUM + 1'b1;
+`else
+parameter int unsigned  SCR1_TDU_ALLTRIG_NUM           = SCR1_TDU_MTRIG_NUM;
+`endif
+
+parameter int unsigned  SCR1_TDU_ADDR_W                = `SCR1_XLEN;
+parameter int unsigned  SCR1_TDU_DATA_W                = `SCR1_XLEN;
+
+// Register map
+parameter                                     SCR1_CSR_ADDR_TDU_OFFS_W        = 3;
+parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0]  SCR1_CSR_ADDR_TDU_OFFS_TSELECT  = 'h0;
+parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0]  SCR1_CSR_ADDR_TDU_OFFS_TDATA1   = 'h1;
+parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0]  SCR1_CSR_ADDR_TDU_OFFS_TDATA2   = 'h2;
+parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0]  SCR1_CSR_ADDR_TDU_OFFS_TINFO    = 'h4;
+
+
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TSELECT       = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TSELECT;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TDATA1        = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TDATA1;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TDATA2        = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TDATA2;
+parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TINFO         = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TINFO;
+
+// TDATA1
+parameter int unsigned  SCR1_TDU_TDATA1_TYPE_HI        = `SCR1_XLEN-1;
+parameter int unsigned  SCR1_TDU_TDATA1_TYPE_LO        = `SCR1_XLEN-4;
+parameter int unsigned  SCR1_TDU_TDATA1_DMODE          = `SCR1_XLEN-5;
+
+// TDATA1: constant bits values
+parameter bit           SCR1_TDU_TDATA1_DMODE_VAL      = 1'b0;
+
+// MCONTROL: bits number
+parameter int unsigned  SCR1_TDU_MCONTROL_MASKMAX_HI   = `SCR1_XLEN-6;
+parameter int unsigned  SCR1_TDU_MCONTROL_MASKMAX_LO   = `SCR1_XLEN-11;
+parameter int unsigned  SCR1_TDU_MCONTROL_RESERVEDB_HI = `SCR1_XLEN-12;
+parameter int unsigned  SCR1_TDU_MCONTROL_RESERVEDB_LO = 21;
+parameter int unsigned  SCR1_TDU_MCONTROL_HIT          = 20;
+parameter int unsigned  SCR1_TDU_MCONTROL_SELECT       = 19;
+parameter int unsigned  SCR1_TDU_MCONTROL_TIMING       = 18;
+parameter int unsigned  SCR1_TDU_MCONTROL_ACTION_HI    = 17;
+parameter int unsigned  SCR1_TDU_MCONTROL_ACTION_LO    = 12;
+parameter int unsigned  SCR1_TDU_MCONTROL_CHAIN        = 11;
+parameter int unsigned  SCR1_TDU_MCONTROL_MATCH_HI     = 10;
+parameter int unsigned  SCR1_TDU_MCONTROL_MATCH_LO     = 7;
+parameter int unsigned  SCR1_TDU_MCONTROL_M            = 6;
+parameter int unsigned  SCR1_TDU_MCONTROL_RESERVEDA    = 5;
+parameter int unsigned  SCR1_TDU_MCONTROL_S            = 4;
+parameter int unsigned  SCR1_TDU_MCONTROL_U            = 3;
+parameter int unsigned  SCR1_TDU_MCONTROL_EXECUTE      = 2;
+parameter int unsigned  SCR1_TDU_MCONTROL_STORE        = 1;
+parameter int unsigned  SCR1_TDU_MCONTROL_LOAD         = 0;
+
+// MCONTROL: constant bits values
+parameter bit [SCR1_TDU_TDATA1_TYPE_HI-SCR1_TDU_TDATA1_TYPE_LO:0]
+                        SCR1_TDU_MCONTROL_TYPE_VAL           = 2'd2;
+
+parameter bit           SCR1_TDU_MCONTROL_SELECT_VAL         = 1'b0;
+parameter bit           SCR1_TDU_MCONTROL_TIMING_VAL         = 1'b0;
+
+parameter bit [SCR1_TDU_MCONTROL_MASKMAX_HI-SCR1_TDU_MCONTROL_MASKMAX_LO:0]
+                        SCR1_TDU_MCONTROL_MASKMAX_VAL        = 1'b0;
+
+parameter bit           SCR1_TDU_MCONTROL_RESERVEDA_VAL      = 1'b0;
+
+// ICOUNT: bits number
+parameter int unsigned  SCR1_TDU_ICOUNT_DMODE          = `SCR1_XLEN-5;
+parameter int unsigned  SCR1_TDU_ICOUNT_RESERVEDB_HI   = `SCR1_XLEN-6;
+parameter int unsigned  SCR1_TDU_ICOUNT_RESERVEDB_LO   = 25;
+parameter int unsigned  SCR1_TDU_ICOUNT_HIT            = 24;
+parameter int unsigned  SCR1_TDU_ICOUNT_COUNT_HI       = 23;
+parameter int unsigned  SCR1_TDU_ICOUNT_COUNT_LO       = 10;
+parameter int unsigned  SCR1_TDU_ICOUNT_M              = 9;
+parameter int unsigned  SCR1_TDU_ICOUNT_RESERVEDA      = 8;
+parameter int unsigned  SCR1_TDU_ICOUNT_S              = 7;
+parameter int unsigned  SCR1_TDU_ICOUNT_U              = 6;
+parameter int unsigned  SCR1_TDU_ICOUNT_ACTION_HI      = 5;
+parameter int unsigned  SCR1_TDU_ICOUNT_ACTION_LO      = 0;
+
+// ICOUNT: constant bits values
+parameter bit [SCR1_TDU_TDATA1_TYPE_HI-SCR1_TDU_TDATA1_TYPE_LO:0]
+                        SCR1_TDU_ICOUNT_TYPE_VAL             = 2'd3;
+
+parameter bit [SCR1_TDU_ICOUNT_RESERVEDB_HI-SCR1_TDU_ICOUNT_RESERVEDB_LO:0]
+                        SCR1_TDU_ICOUNT_RESERVEDB_VAL        = 1'b0;
+
+parameter bit           SCR1_TDU_ICOUNT_RESERVEDA_VAL        = 1'b0;
+
+// CPU pipeline monitors
+typedef struct packed {
+    logic                                           vd;
+    logic                                           req;
+    logic [`SCR1_XLEN-1:0]                          addr;
+} type_scr1_brkm_instr_mon_s;
+
+typedef struct packed {
+    logic                                           vd;
+    logic                                           load;
+    logic                                           store;
+`ifndef SCR1_BRKM_EN
+    type_scr1_op_width_e                            width;
+`endif // SCR1_BRKM_EN
+    logic [`SCR1_XLEN-1:0]                          addr;
+} type_scr1_brkm_lsu_mon_s;
+
+`endif // SCR1_BRKM_EN
+
+`endif // SCR1_INCLUDE_TDU_DEFS
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_ipic.sv b/third_party/tests/Scr1/src/pipeline/scr1_ipic.sv
new file mode 100644
index 0000000..655df7a
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_ipic.sv
@@ -0,0 +1,454 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_ipic.sv>
+/// @brief      Integrated Programmable Interrupt Controller (IPIC)
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_IPIC_EN
+
+`include "scr1_ipic.svh"
+
+module scr1_ipic
+(
+    // Common
+    input   logic                                   rst_n,
+    input   logic                                   clk,
+
+    // External Interrupt lines
+    input   logic [SCR1_IRQ_LINES_NUM-1:0]          irq_lines,
+
+    // CSR <-> IPIC interface
+    input   logic                                   csr2ipic_r_req,     // IPIC read request
+    input   logic                                   csr2ipic_w_req,     // IPIC write request
+    input   logic [2:0]                             csr2ipic_addr,      // IPIC address
+    input   logic [`SCR1_XLEN-1:0]                  csr2ipic_wdata,     // IPIC write data
+    output  logic [`SCR1_XLEN-1:0]                  ipic2csr_rdata,     // IPIC read data
+
+    // Interface to Core
+    output  logic                                   irq_m_req           // IRQ request from IPIC
+);
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+typedef struct {
+    logic                                   vd;
+    logic                                   idx;
+} type_scr1_search_one_2_s;
+
+typedef struct {
+    logic                                   vd;
+    logic   [SCR1_IRQ_VECT_WIDTH-1:0]       idx;
+} type_scr1_search_one_16_s;
+
+typedef struct packed {
+    logic                                   ip;
+    logic                                   ie;
+    logic                                   im;
+    logic                                   inv;
+    logic                                   is;
+    logic   [SCR1_IRQ_LINES_WIDTH-1:0]      line;
+} type_scr1_icsr_m_s;
+
+typedef struct packed {
+    logic                                   ip;
+    logic                                   ie;
+} type_scr1_cicsr_s;
+
+//-------------------------------------------------------------------------------
+// Local functions declaration
+//-------------------------------------------------------------------------------
+function automatic type_scr1_search_one_2_s scr1_search_one_2(
+    input   logic   [1:0] din
+);
+    type_scr1_search_one_2_s tmp;
+begin
+    tmp.vd  = |din;
+    tmp.idx = ~din[0];
+    return  tmp;
+end
+endfunction : scr1_search_one_2
+
+function automatic type_scr1_search_one_16_s scr1_search_one_16(
+    input   logic [15:0]    din
+);
+begin
+    logic [7:0]         stage1_vd;
+    logic [3:0]         stage2_vd;
+    logic [1:0]         stage3_vd;
+
+    logic               stage1_idx [7:0];
+    logic [1:0]         stage2_idx [3:0];
+    logic [2:0]         stage3_idx [1:0];
+    type_scr1_search_one_16_s result;
+
+    // Stage 1
+    for (int unsigned i=0; i<8; ++i) begin
+        type_scr1_search_one_2_s tmp;
+        tmp = scr1_search_one_2(din[(i+1)*2-1-:2]);
+        stage1_vd[i]  = tmp.vd;
+        stage1_idx[i] = tmp.idx;
+    end
+
+    // Stage 2
+    for (int unsigned i=0; i<4; ++i) begin
+        type_scr1_search_one_2_s tmp;
+        tmp = scr1_search_one_2(stage1_vd[(i+1)*2-1-:2]);
+        stage2_vd[i]  = tmp.vd;
+        stage2_idx[i] = (~tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]};
+    end
+
+    // Stage 3
+    for (int unsigned i=0; i<2; ++i) begin
+        type_scr1_search_one_2_s tmp;
+        tmp = scr1_search_one_2(stage2_vd[(i+1)*2-1-:2]);
+        stage3_vd[i]  = tmp.vd;
+        stage3_idx[i] = (~tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]};
+    end
+
+    // Stage 4
+    result.vd = |stage3_vd;
+    result.idx = (stage3_vd[0]) ? {1'b0, stage3_idx[0]} : {1'b1, stage3_idx[1]};
+
+    return result;
+end
+endfunction : scr1_search_one_16
+
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+logic [SCR1_IRQ_VECT_NUM-1:0]           irq_lines_i;            // Internal IRQ lines
+logic [SCR1_IRQ_VECT_NUM-1:0]           irq_edge_det;           // IRQ edge
+logic [SCR1_IRQ_VECT_NUM-1:0]           irq_lvl;                // IRQ level
+logic [SCR1_IRQ_VECT_NUM-1:0]           invr;                   // Inversion register
+logic [SCR1_IRQ_VECT_NUM-1:0]           invr_new;               // Inversion register new value
+logic [SCR1_IRQ_VECT_NUM-1:0]           irq_vect;               // Inversion IRQ mapped vector
+logic [SCR1_IRQ_VECT_NUM-1:0]           imr;                    // Interrupt mode register
+logic [SCR1_IRQ_VECT_NUM-1:0]           imr_new;                // Interrupt mode register new value
+
+logic [SCR1_IRQ_VECT_NUM-1:0]           ipr;                    // Interrupt pending register;
+                                                                    //  for level IRQ just translate the irq_vect,
+                                                                    //  for edge IRQ - latch edge detection
+logic [SCR1_IRQ_VECT_NUM-1:0]           ipr_new;                // New value for IPR
+logic [SCR1_IRQ_VECT_NUM-1:0]           ipr_m;                  // Interrupt pending register for M-mode IRQ(IPIC_IPR_M)
+logic [SCR1_IRQ_VECT_NUM-1:0]           ipr_clr;                // Interrupt pending clr
+
+logic [SCR1_IRQ_VECT_NUM-1:0]           ier;                    // Interrupt enable register(IPIC_IER)
+logic [SCR1_IRQ_VECT_NUM-1:0]           irr_m;                  // Interrupt register register(IPIC_IPR & IPIC_IER & PRV==M)
+
+
+logic [SCR1_IRQ_VECT_WIDTH-1:0]         cisv_m;                 // Number of the current M-mode interrupt in service register(IPIC_CISV_M)
+logic [SCR1_IRQ_IDX_WIDTH-1:0]          idxr_m;                 // M-mode index register(IPIC_IDX_M)
+logic [SCR1_IRQ_VECT_NUM-1:0]           isvr_m;                 // M-mode in service register(IPIC_ISVR_M)
+logic                                   soi_wr_m;               // Start of M-mode interrupt
+logic                                   eoi_wr_m;               // End of M-mode current in service interrupt
+
+type_scr1_icsr_m_s                      icsr_m;
+type_scr1_cicsr_s                       cicsr_m;
+
+type_scr1_search_one_16_s               irr_priority_m;
+type_scr1_search_one_16_s               isvr_priority_eoi_m;
+logic [SCR1_IRQ_VECT_NUM-1:0]           isvr_eoi_m;
+
+
+genvar gen_i;
+
+//-------------------------------------------------------------------------------
+// Read Logic
+//-------------------------------------------------------------------------------
+always_comb begin
+    logic cisv_found;
+
+    cisv_found      = 1'b0;
+    ipic2csr_rdata  = '0;
+    if (csr2ipic_r_req) begin
+        case (csr2ipic_addr)
+
+            SCR1_IPIC_CISV : begin
+                // Vector number for currently serviced interrupt
+                for (int unsigned i=0; i<SCR1_IRQ_VECT_NUM; ++i) begin
+                    if (cisv_m == i) begin
+                        cisv_found |= 1'b1;
+                        ipic2csr_rdata[SCR1_IRQ_VECT_WIDTH-1:0] |= cisv_m;
+                    end
+                end
+                if (~cisv_found) begin
+                    ipic2csr_rdata[SCR1_IRQ_VECT_WIDTH-1:0] = SCR1_IRQ_VOID_VECT_NUM;
+                end
+            end
+
+            SCR1_IPIC_CICSR : begin
+                // CSR for the currently serviced interrupts
+                ipic2csr_rdata[SCR1_IPIC_ICSR_IP]  = cicsr_m.ip;
+                ipic2csr_rdata[SCR1_IPIC_ICSR_IE]  = cicsr_m.ie;
+            end
+
+            SCR1_IPIC_IPR : begin
+                // Aggregated pending interrupts
+                ipic2csr_rdata = ipr_m;
+            end
+
+            SCR1_IPIC_ISVR : begin
+                // Aggregated serviced interrupts
+                ipic2csr_rdata = isvr_m;
+            end
+
+            SCR1_IPIC_EOI,
+            SCR1_IPIC_SOI : begin
+                ipic2csr_rdata = '0;
+            end
+
+            SCR1_IPIC_IDX : begin
+                // Index register for access to interrupt CSRs
+                ipic2csr_rdata = idxr_m;
+            end
+
+            SCR1_IPIC_ICSR : begin
+                // Interrupt CSR pointed by IDX
+                ipic2csr_rdata[SCR1_IPIC_ICSR_IP]  = icsr_m.ip;
+                ipic2csr_rdata[SCR1_IPIC_ICSR_IE]  = icsr_m.ie;
+                ipic2csr_rdata[SCR1_IPIC_ICSR_IM]  = icsr_m.im;
+                ipic2csr_rdata[SCR1_IPIC_ICSR_INV] = icsr_m.inv;
+                ipic2csr_rdata[SCR1_IPIC_ICSR_PRV_MSB:SCR1_IPIC_ICSR_PRV_LSB]   = SCR1_IPIC_PRV_M;
+                ipic2csr_rdata[SCR1_IPIC_ICSR_IS]  = icsr_m.is;
+                ipic2csr_rdata[SCR1_IPIC_ICSR_LN_LSB+SCR1_IRQ_LINES_WIDTH-1:SCR1_IPIC_ICSR_LN_LSB]  = icsr_m.line;
+            end
+
+            default : begin
+                ipic2csr_rdata = 'x;
+            end
+        endcase
+    end
+end
+
+assign icsr_m.ip    = ipr[idxr_m];
+assign icsr_m.ie    = ier[idxr_m];
+assign icsr_m.im    = imr[idxr_m];
+assign icsr_m.inv   = invr[idxr_m];
+assign icsr_m.is    = isvr_m[idxr_m];
+assign icsr_m.line  = SCR1_IRQ_LINES_WIDTH'(idxr_m);
+
+assign cicsr_m.ip   = ipr[cisv_m[SCR1_IRQ_VECT_WIDTH-2:0]] & ~cisv_m[SCR1_IRQ_VECT_WIDTH-1];
+assign cicsr_m.ie   = ier[cisv_m[SCR1_IRQ_VECT_WIDTH-2:0]] & ~cisv_m[SCR1_IRQ_VECT_WIDTH-1];
+
+//-------------------------------------------------------------------------------
+// Write logic
+//-------------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        ier     <= '0;
+        imr     <= '0;
+        invr    <= '0;
+        idxr_m  <= '0;
+    end else if (csr2ipic_w_req) begin
+        case (csr2ipic_addr)
+            SCR1_IPIC_CICSR : begin
+                // CSR for the currently serviced interrupt
+                if (~cisv_m[SCR1_IRQ_VECT_WIDTH-1]) begin
+                    ier[cisv_m[SCR1_IRQ_VECT_WIDTH-2:0]] <= csr2ipic_wdata[SCR1_IPIC_ICSR_IE];
+                end
+            end
+
+            SCR1_IPIC_IDX : begin
+                idxr_m      <= csr2ipic_wdata[SCR1_IRQ_IDX_WIDTH-1:0];
+            end
+
+            SCR1_IPIC_ICSR : begin
+                ier[idxr_m]     <= csr2ipic_wdata[SCR1_IPIC_ICSR_IE];
+                imr[idxr_m]     <= csr2ipic_wdata[SCR1_IPIC_ICSR_IM];
+                invr[idxr_m]    <= csr2ipic_wdata[SCR1_IPIC_ICSR_INV];
+            end
+
+            default : begin
+            end
+        endcase
+    end
+end
+
+//-------------------------------------------------------------------------------
+// IPR clear generation
+//-------------------------------------------------------------------------------
+always_comb begin
+    ipr_clr = '0;
+    eoi_wr_m  = 1'b0;
+    soi_wr_m  = 1'b0;
+    if (csr2ipic_w_req) begin
+        case (csr2ipic_addr)
+            SCR1_IPIC_CICSR : begin
+                // CSR for the currently serviced interrupt
+                ipr_clr[cisv_m[SCR1_IRQ_VECT_WIDTH-2:0]] |= (csr2ipic_wdata[SCR1_IPIC_ICSR_IP] & ~cisv_m[SCR1_IRQ_VECT_WIDTH-1]);
+            end
+
+            SCR1_IPIC_IPR : begin
+                // Aggregated pending interrupts
+                ipr_clr = csr2ipic_wdata[SCR1_IRQ_VECT_NUM-1:0];
+            end
+
+            SCR1_IPIC_EOI : begin
+                // End Of Interrupt
+                eoi_wr_m |= (~cisv_m[SCR1_IRQ_VECT_WIDTH-1]);
+            end
+
+            SCR1_IPIC_SOI : begin
+                // Start Of Interrupt
+                if (irr_priority_m.vd) begin
+                    for (int unsigned i=0; i<SCR1_IRQ_VECT_NUM; ++i) begin
+                        if (irr_priority_m.idx == i) begin
+                            soi_wr_m   |= 1'b1;
+                            ipr_clr[i] |= 1'b1;
+                        end
+                    end
+                end
+            end
+
+
+            SCR1_IPIC_ICSR : begin
+                ipr_clr[idxr_m] |= csr2ipic_wdata[SCR1_IPIC_ICSR_IP];
+            end
+
+            default : begin
+            end
+
+        endcase
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Synchronizer (optional), interrupt vector edge detect
+//-------------------------------------------------------------------------------
+`ifdef SCR1_IPIC_SYNC_EN
+logic [SCR1_IRQ_VECT_NUM-1:0]   irq_lines_sync0;
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        irq_lines_sync0 <= '0;
+        irq_lines_i     <= '0;
+    end else begin
+        irq_lines_sync0 <= irq_lines;
+        irq_lines_i     <= irq_lines_sync0;
+    end
+end
+`else // SCR1_IPIC_SYNC_EN
+assign irq_lines_i  = irq_lines;
+`endif // SCR1_IPIC_SYNC_EN
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        irq_edge_det    <= '0;
+    end else begin
+        irq_edge_det    <= irq_lines_i;
+    end
+end
+
+
+//-------------------------------------------------------------------------------
+// IMR / INVR new values
+//-------------------------------------------------------------------------------
+always_comb begin
+    invr_new    = invr;
+    imr_new     = imr;
+    if (csr2ipic_w_req & (csr2ipic_addr == SCR1_IPIC_ICSR)) begin
+        invr_new[idxr_m]    = csr2ipic_wdata[SCR1_IPIC_ICSR_INV];
+        imr_new[idxr_m]     = csr2ipic_wdata[SCR1_IPIC_ICSR_IM];
+    end
+end
+
+// Level and edge IRQ
+assign irq_lvl  = irq_lines_i ^ invr_new;
+
+//-------------------------------------------------------------------------------
+// Interrupt Pending register
+//-------------------------------------------------------------------------------
+// IP bit should not be cleared if the condition for interrupt triggering is true,
+// even if a ipr_clr request is present
+always_comb begin
+    ipr_new = '0;
+    for (int unsigned i=0; i<SCR1_IRQ_VECT_NUM; ++i) begin
+        if (ipr_clr[i] & (~irq_lvl[i] | imr_new[i])) begin
+            ipr_new[i] = 1'b0;
+        end else begin
+            if (~imr[i]) begin          // Level IRQ
+                ipr_new[i] = irq_lvl[i];
+            end else begin              // Edge IRQ
+                ipr_new[i] = ipr[i] | ((irq_edge_det[i] ^ irq_lines_i[i]) & irq_lvl[i]);
+            end
+        end
+    end
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        ipr <= '0;
+    end else begin
+        if (ipr != ipr_new) begin
+            ipr <= ipr_new;
+        end
+    end
+end
+
+assign ipr_m = ipr;
+
+//-------------------------------------------------------------------------------
+// Interrupt Requested Register
+//-------------------------------------------------------------------------------
+assign irr_m    = ipr_m & ier;
+
+//-------------------------------------------------------------------------------
+// IRQ generation for M-mode IRQ
+//-------------------------------------------------------------------------------
+assign irr_priority_m      = scr1_search_one_16(irr_m);
+assign isvr_priority_eoi_m = scr1_search_one_16(isvr_eoi_m);
+
+always_comb begin
+    isvr_eoi_m = isvr_m;
+    for (int unsigned i=0; i<SCR1_IRQ_VECT_NUM; ++i) begin
+        if (i == cisv_m) begin
+            isvr_eoi_m[i] = 1'b0;
+        end
+    end
+end
+
+always_comb begin
+
+    irq_m_req = 1'b0;
+
+    if (irr_priority_m.vd) begin            // There is a new interrupt
+        if (~|isvr_m) begin                 // No serviced interrupts
+            irq_m_req = 1'b1;
+        end else begin                      // There are serviced interrupts
+            if (irr_priority_m.idx < cisv_m) begin
+                irq_m_req = 1'b1;
+            end
+        end
+    end
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        isvr_m  <= '0;
+        cisv_m  <= SCR1_IRQ_VOID_VECT_NUM;
+    end else begin
+        if ((irq_m_req) & (soi_wr_m)) begin
+            for (int unsigned i=0; i<SCR1_IRQ_VECT_NUM; ++i) begin
+                if (i == irr_priority_m.idx) begin
+                    isvr_m[i] <= 1'b1;
+                end
+            end
+            cisv_m <= irr_priority_m.idx;
+        end else if (eoi_wr_m) begin
+            isvr_m <= isvr_eoi_m;
+            if (isvr_priority_eoi_m.vd) begin
+                cisv_m <= isvr_priority_eoi_m.idx;
+            end else begin
+                cisv_m <= SCR1_IRQ_VOID_VECT_NUM;
+            end
+
+        end
+    end
+end
+
+endmodule : scr1_ipic
+
+`endif // SCR1_IPIC_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_csr.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_csr.sv
new file mode 100644
index 0000000..baaf916
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_csr.sv
@@ -0,0 +1,1010 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_pipe_csr.sv>
+/// @brief      Control Status Registers (CSR)
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_csr.svh"
+`include "scr1_arch_types.svh"
+`include "scr1_riscv_isa_decoding.svh"
+`ifdef SCR1_IPIC_EN
+`include "scr1_ipic.svh"
+`endif // SCR1_IPIC_EN
+`ifdef SCR1_DBGC_EN
+`include "scr1_hdu.svh"
+`endif // SCR1_DBGC_EN
+`ifdef SCR1_BRKM_EN
+`include "scr1_tdu.svh"
+`endif // SCR1_BRKM_EN
+
+module scr1_pipe_csr (
+    // Common
+    input   logic                                       rst_n,
+    input   logic                                       clk,
+`ifdef SCR1_CLKCTRL_EN
+    input   logic                                       clk_alw_on,
+`endif // SCR1_CLKCTRL_EN
+
+    // EXU <-> CSR read/write interface
+    input   logic                                       exu2csr_r_req,          // CSR read/write address
+    input   logic [SCR1_CSR_ADDR_WIDTH-1:0]             exu2csr_rw_addr,        // CSR read request
+    output  logic [`SCR1_XLEN-1:0]                      csr2exu_r_data,         // CSR read data
+    input   logic                                       exu2csr_w_req,          // CSR write request
+    input   type_scr1_csr_cmd_sel_e                     exu2csr_w_cmd,          // CSR write command
+    input   logic [`SCR1_XLEN-1:0]                      exu2csr_w_data,         // CSR write data
+    output  logic                                       csr2exu_rw_exc,         // CSR read/write access exception
+
+    // EXU <-> CSR event interface
+    input   logic                                       exu2csr_take_irq,       // Take IRQ trap
+    input   logic                                       exu2csr_take_exc,       // Take exception trap
+    input   logic                                       exu2csr_mret_update,    // MRET update CSR
+    input   logic                                       exu2csr_mret_instr,     // MRET instruction
+`ifdef SCR1_DBGC_EN
+    input   logic                                       exu_no_commit,          // Forbid instruction commitment
+`endif // SCR1_DBGC_EN
+    input   type_scr1_exc_code_e                        exu2csr_exc_code,       // Exception code (see scr1_arch_types.svh)
+    input   logic [`SCR1_XLEN-1:0]                      exu2csr_trap_val,       // Trap value
+    output  logic [`SCR1_XLEN-1:0]                      csr2exu_new_pc,         // Exception/IRQ/MRET new PC
+    output  logic                                       csr2exu_irq,            // IRQ request
+    output  logic                                       csr2exu_ip_ie,          // Some IRQ pending and locally enabled
+    output  logic                                       csr2exu_mstatus_mie_up, // MSTATUS or MIE update in the current cycle
+
+`ifdef SCR1_IPIC_EN
+    // CSR <-> IPIC interface
+    output  logic                                       csr2ipic_r_req,         // IPIC read request
+    output  logic                                       csr2ipic_w_req,         // IPIC write request
+    output  logic [2:0]                                 csr2ipic_addr,          // IPIC address
+    output  logic [`SCR1_XLEN-1:0]                      csr2ipic_wdata,         // IPIC write data
+    input   logic [`SCR1_XLEN-1:0]                      ipic2csr_rdata,         // IPIC read data
+`endif // SCR1_IPIC_EN
+
+    // CSR <-> PC interface
+    input   logic [`SCR1_XLEN-1:0]                      curr_pc,                // Current PC
+    input   logic [`SCR1_XLEN-1:0]                      next_pc,                // Next PC
+`ifndef SCR1_CSR_REDUCED_CNT
+    input   logic                                       instret_nexc,           // Instruction retired (without exception)
+`endif // SCR1_CSR_REDUCED_CNT
+
+    // IRQ
+    input   logic                                       ext_irq,                // External interrupt request
+    input   logic                                       soft_irq,               // Software interrupt request
+
+    // Memory-mapped external timer
+    input   logic                                       timer_irq,              // External timer interrupt request
+    input   logic [63:0]                                mtime_ext,              // External timer value
+
+`ifdef SCR1_DBGC_EN
+    // CSR <-> HDU interface
+    output  logic                                       csr2hdu_req,           // Request to HDU
+    output  type_scr1_csr_cmd_sel_e                     csr2hdu_cmd,           // HDU command
+    output  logic [SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0]    csr2hdu_addr,          // HDU address
+    output  logic [`SCR1_XLEN-1:0]                      csr2hdu_wdata,         // HDU write data
+    input   logic [`SCR1_XLEN-1:0]                      hdu2csr_rdata,         // HDU read data
+    input   type_scr1_csr_resp_e                        hdu2csr_resp,          // HDU response
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_BRKM_EN
+    // CSR <-> TDU interface
+    output  logic                                       csr2tdu_req,           // Request to TDU
+    output  type_scr1_csr_cmd_sel_e                     csr2tdu_cmd,           // TDU command
+    output  logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0]        csr2tdu_addr,          // TDU address
+    output  logic [`SCR1_XLEN-1:0]                      csr2tdu_wdata,         // TDU write data
+    input   logic [`SCR1_XLEN-1:0]                      tdu2csr_rdata,         // TDU read data
+    input   type_scr1_csr_resp_e                        tdu2csr_resp,          // TDU response
+`endif // SCR1_BRKM_EN
+
+    // MHARTID fuse
+    input   logic [`SCR1_XLEN-1:0]                      fuse_mhartid            // MHARTID fuse
+);
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+
+// Registers
+logic [`SCR1_XLEN-1:0]                              csr_mstatus;        // Aggregated MSTATUS
+logic [`SCR1_XLEN-1:0]                              csr_mie;            // Aggregated MIE
+logic [`SCR1_XLEN-1:0]                              csr_mip;            // Aggregated MIP
+logic                                               csr_mstatus_mie;    // MSTATUS: Global interrupt enable
+logic                                               csr_mstatus_mpie;   // MSTATUS: Global interrupt enable prior to the trap
+logic                                               csr_mie_mtie;       // MIE: Machine timer interrupt enable
+logic                                               csr_mie_meie;       // MIE: Machine external interrupt enable
+logic                                               csr_mie_msie;       // MIE: Machine software interrupt enable
+logic [`SCR1_XLEN-1:0]                              csr_mscratch;       // MSCRATCH
+`ifdef SCR1_RVC_EXT
+logic [`SCR1_XLEN-1:1]                              csr_mepc;           // MEPC (RVC)
+`else // ~SCR1_RVC_EXT
+logic [`SCR1_XLEN-1:2]                              csr_mepc;           // MEPC
+`endif // ~SCR1_RVC_EXT
+logic                                               csr_mcause_i;       // MCAUSE: Interrupt
+type_scr1_exc_code_e                                csr_mcause_ec;      // MCAUSE: Exception code
+type_scr1_exc_code_e                                csr_mcause_ec_new;
+logic [`SCR1_XLEN-1:0]                              csr_mtval;          // MTVAL
+logic [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS]  csr_mtvec_base;     // MTVEC: Base (upper 26 bits)
+logic                                               csr_mtvec_mode;     // MTVEC: Mode (0-direct, 1-vectored)
+logic                                               csr_mip_mtip;       // MIP: Machine timer interrupt pending
+logic                                               csr_mip_meip;       // MIP: Machine external interrupt pending
+logic                                               csr_mip_msip;       // MIP: Machine software interrupt pending
+
+`ifndef SCR1_CSR_REDUCED_CNT
+
+logic [SCR1_CSR_COUNTERS_WIDTH-1:0]                 csr_instret;        // INSTRET
+logic [SCR1_CSR_COUNTERS_WIDTH-1:8]                 csr_instret_hi;
+logic [SCR1_CSR_COUNTERS_WIDTH-1:8]                 csr_instret_hi_new;
+logic [7:0]                                         csr_instret_lo;
+logic [7:0]                                         csr_instret_lo_new;
+
+logic [SCR1_CSR_COUNTERS_WIDTH-1:0]                 csr_cycle;          // CYCLE
+logic [SCR1_CSR_COUNTERS_WIDTH-1:8]                 csr_cycle_hi;
+logic [SCR1_CSR_COUNTERS_WIDTH-1:8]                 csr_cycle_hi_new;
+logic [7:0]                                         csr_cycle_lo;
+logic [7:0]                                         csr_cycle_lo_new;
+
+`endif // ~SCR1_CSR_REDUCED_CNT
+
+`ifdef SCR1_CSR_MCOUNTEN_EN
+logic [`SCR1_XLEN-1:0]                              csr_mcounten;       // Aggregated MCOUNTEN
+logic                                               csr_mcounten_cy;    // Cycle count enable
+logic                                               csr_mcounten_ir;    // Instret count enable
+`endif // SCR1_CSR_MCOUNTEN_EN
+
+// Read signals
+logic [`SCR1_XLEN-1:0]                              csr_r_data;
+logic                                               csr_r_exc;
+
+// Write signals
+logic                                               csr_mstatus_up;
+logic                                               csr_mie_up;
+logic                                               csr_mscratch_up;
+logic                                               csr_mepc_up;
+logic                                               csr_mcause_up;
+logic                                               csr_mtval_up;
+logic                                               csr_mtvec_up;
+`ifndef SCR1_CSR_REDUCED_CNT
+logic [1:0]                                         csr_cycle_up;
+logic [1:0]                                         csr_instret_up;
+logic                                               csr_cycle_inc_lo;
+logic                                               csr_cycle_inc_hi;
+logic                                               csr_instret_inc_lo;
+logic                                               csr_instret_inc_hi;
+`endif // SCR1_CSR_REDUCED_CNT
+
+`ifdef SCR1_CSR_MCOUNTEN_EN
+logic                                               csr_mcounten_up;
+`endif // SCR1_CSR_MCOUNTEN_EN
+
+logic [`SCR1_XLEN-1:0]                              csr_w_data;
+logic                                               csr_w_exc;
+
+// Events
+logic                                               e_exc;              // Successful exception trap
+logic                                               e_irq;              // Successful IRQ trap
+logic                                               e_mret;             // MRET instruction
+
+`ifdef SCR1_DBGC_EN
+logic                                               csr_hdu_req;
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_BRKM_EN
+logic                                               csr_brkm_req;
+`endif // SCR1_BRKM_EN
+
+
+//-------------------------------------------------------------------------------
+// Read CSR
+//-------------------------------------------------------------------------------
+
+// Aggregated CSRs
+always_comb begin
+    csr_mstatus     = '0;
+    csr_mie         = '0;
+    csr_mip         = '0;
+`ifdef SCR1_CSR_MCOUNTEN_EN
+    csr_mcounten    = '0;
+`endif // SCR1_CSR_MCOUNTEN_EN
+
+    csr_mstatus[SCR1_CSR_MSTATUS_MIE_OFFSET]                                = csr_mstatus_mie;
+    csr_mstatus[SCR1_CSR_MSTATUS_MPIE_OFFSET]                               = csr_mstatus_mpie;
+    csr_mstatus[SCR1_CSR_MSTATUS_MPP_OFFSET+1:SCR1_CSR_MSTATUS_MPP_OFFSET]  = SCR1_CSR_MSTATUS_MPP;
+
+    csr_mie[SCR1_CSR_MIE_MSIE_OFFSET]   = csr_mie_msie;
+    csr_mie[SCR1_CSR_MIE_MTIE_OFFSET]   = csr_mie_mtie;
+    csr_mie[SCR1_CSR_MIE_MEIE_OFFSET]   = csr_mie_meie;
+
+    csr_mip[SCR1_CSR_MIE_MSIE_OFFSET]   = csr_mip_msip;
+    csr_mip[SCR1_CSR_MIE_MTIE_OFFSET]   = csr_mip_mtip;
+    csr_mip[SCR1_CSR_MIE_MEIE_OFFSET]   = csr_mip_meip;
+
+`ifdef SCR1_CSR_MCOUNTEN_EN
+    csr_mcounten[SCR1_CSR_MCOUNTEN_CY_OFFSET]   = csr_mcounten_cy;
+    csr_mcounten[SCR1_CSR_MCOUNTEN_IR_OFFSET]   = csr_mcounten_ir;
+`endif // SCR1_CSR_MCOUNTEN_EN
+end
+
+always_comb begin
+    csr_r_data      = '0;
+    csr_r_exc       = 1'b0;
+`ifdef SCR1_IPIC_EN
+    csr2ipic_r_req  = 1'b0;
+`endif // SCR1_IPIC_EN
+`ifdef SCR1_DBGC_EN
+    csr_hdu_req    = 1'b0;
+`endif // SCR1_DBGC_EN
+`ifdef SCR1_BRKM_EN
+    csr_brkm_req   = 1'b0;
+`endif // SCR1_BRKM_EN
+    casez (exu2csr_rw_addr)
+        // Machine Information Registers (read-only)
+        SCR1_CSR_ADDR_MVENDORID : csr_r_data    = SCR1_CSR_MVENDORID;
+        SCR1_CSR_ADDR_MARCHID   : csr_r_data    = SCR1_CSR_MARCHID;
+        SCR1_CSR_ADDR_MIMPID    : csr_r_data    = SCR1_CSR_MIMPID;
+        SCR1_CSR_ADDR_MHARTID   : csr_r_data    = fuse_mhartid;
+
+        // Machine Trap Setup (read-write)
+        SCR1_CSR_ADDR_MSTATUS   : csr_r_data    = csr_mstatus;
+        SCR1_CSR_ADDR_MISA      : csr_r_data    = SCR1_CSR_MISA;
+        SCR1_CSR_ADDR_MIE       : csr_r_data    = csr_mie;
+        SCR1_CSR_ADDR_MTVEC     : csr_r_data    = {csr_mtvec_base, 4'd0, 2'(csr_mtvec_mode)};
+
+        // Machine Trap Handling (read-write)
+        SCR1_CSR_ADDR_MSCRATCH  : csr_r_data    = csr_mscratch;
+        SCR1_CSR_ADDR_MEPC      : csr_r_data    =
+`ifdef SCR1_RVC_EXT
+                                                  {csr_mepc, 1'b0};
+`else // SCR1_RVC_EXT
+                                                  {csr_mepc, 2'b00};
+`endif // SCR1_RVC_EXT
+
+        SCR1_CSR_ADDR_MCAUSE    : csr_r_data    = {csr_mcause_i, type_scr1_csr_mcause_ec_v'(csr_mcause_ec)};
+        SCR1_CSR_ADDR_MTVAL     : csr_r_data    = csr_mtval;
+        SCR1_CSR_ADDR_MIP       : csr_r_data    = csr_mip;
+
+        // User Counters/Timers (read-only)
+        {SCR1_CSR_ADDR_HPMCOUNTER_MASK, 5'b?????}   : begin
+            case (exu2csr_rw_addr[4:0])
+                5'd1        : csr_r_data    = mtime_ext[31:0];
+`ifndef SCR1_CSR_REDUCED_CNT
+                5'd0        : csr_r_data    = csr_cycle[31:0];
+                5'd2        : csr_r_data    = csr_instret[31:0];
+`endif // SCR1_CSR_REDUCED_CNT
+                default     : begin
+                    // return 0
+                end
+            endcase
+        end
+
+        {SCR1_CSR_ADDR_HPMCOUNTERH_MASK, 5'b?????}  : begin
+            case (exu2csr_rw_addr[4:0])
+                5'd1        : csr_r_data    = mtime_ext[63:32];
+`ifndef SCR1_CSR_REDUCED_CNT
+                5'd0        : csr_r_data    = csr_cycle[63:32];
+                5'd2        : csr_r_data    = csr_instret[63:32];
+`endif // SCR1_CSR_REDUCED_CNT
+                default     : begin
+                    // return 0
+                end
+            endcase
+        end
+
+        // Machine Counters/Timers (read-write)
+        {SCR1_CSR_ADDR_MHPMCOUNTER_MASK, 5'b?????}  : begin
+            case (exu2csr_rw_addr[4:0])
+                5'd1        : csr_r_exc     = exu2csr_r_req;
+`ifndef SCR1_CSR_REDUCED_CNT
+                5'd0        : csr_r_data    = csr_cycle[31:0];
+                5'd2        : csr_r_data    = csr_instret[31:0];
+`endif // SCR1_CSR_REDUCED_CNT
+                default     : begin
+                    // return 0
+                end
+            endcase
+        end
+
+        {SCR1_CSR_ADDR_MHPMCOUNTERH_MASK, 5'b?????} : begin
+            case (exu2csr_rw_addr[4:0])
+                5'd1        : csr_r_exc     = exu2csr_r_req;
+`ifndef SCR1_CSR_REDUCED_CNT
+                5'd0        : csr_r_data    = csr_cycle[63:32];
+                5'd2        : csr_r_data    = csr_instret[63:32];
+`endif // SCR1_CSR_REDUCED_CNT
+                default     : begin
+                    // return 0
+                end
+            endcase
+        end
+
+        {SCR1_CSR_ADDR_MHPMEVENT_MASK, 5'b?????}    : begin
+            case (exu2csr_rw_addr[4:0])
+                5'd0,
+                5'd1,
+                5'd2        : csr_r_exc = exu2csr_r_req;
+                default     : begin
+                    // return 0
+                end
+            endcase
+        end
+
+`ifdef SCR1_CSR_MCOUNTEN_EN
+        SCR1_CSR_ADDR_MCOUNTEN      : csr_r_data    = csr_mcounten;
+`endif // SCR1_CSR_MCOUNTEN_EN
+
+`ifdef SCR1_IPIC_EN
+        // IPIC registers
+        SCR1_CSR_ADDR_IPIC_CISV,
+        SCR1_CSR_ADDR_IPIC_CICSR,
+        SCR1_CSR_ADDR_IPIC_IPR,
+        SCR1_CSR_ADDR_IPIC_ISVR,
+        SCR1_CSR_ADDR_IPIC_EOI,
+        SCR1_CSR_ADDR_IPIC_SOI,
+        SCR1_CSR_ADDR_IPIC_IDX,
+        SCR1_CSR_ADDR_IPIC_ICSR     : begin
+            csr_r_data      = ipic2csr_rdata;
+            csr2ipic_r_req  = exu2csr_r_req;
+        end
+`endif // SCR1_IPIC_EN
+
+`ifdef SCR1_DBGC_EN
+        SCR1_HDU_DBGCSR_ADDR_DCSR,
+        SCR1_HDU_DBGCSR_ADDR_DPC,
+        SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+        SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 : begin
+            // HDU register access
+            csr_hdu_req = 1'b1;
+            csr_r_data  = hdu2csr_rdata;
+        end
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_BRKM_EN
+        // TDU registers
+        SCR1_CSR_ADDR_TDU_TSELECT,
+        SCR1_CSR_ADDR_TDU_TDATA1,
+        SCR1_CSR_ADDR_TDU_TDATA2,
+        SCR1_CSR_ADDR_TDU_TINFO: begin
+            csr_brkm_req    = 1'b1;
+            csr_r_data      = tdu2csr_rdata;
+        end
+`endif // SCR1_BRKM_EN
+
+        default     : begin
+            csr_r_exc   = exu2csr_r_req;
+        end
+    endcase // exu2csr_rw_addr
+end
+
+assign csr2exu_r_data   = csr_r_data;
+
+//-------------------------------------------------------------------------------
+// Write CSR
+//-------------------------------------------------------------------------------
+always_comb begin
+    case (exu2csr_w_cmd)
+        SCR1_CSR_CMD_WRITE  : csr_w_data =  exu2csr_w_data;
+        SCR1_CSR_CMD_SET    : csr_w_data =  exu2csr_w_data | csr_r_data;
+        SCR1_CSR_CMD_CLEAR  : csr_w_data = ~exu2csr_w_data & csr_r_data;
+        default             : csr_w_data = '0;
+    endcase
+end
+
+always_comb begin
+    csr_mstatus_up      = 1'b0;
+    csr_mie_up          = 1'b0;
+    csr_mscratch_up     = 1'b0;
+    csr_mepc_up         = 1'b0;
+    csr_mcause_up       = 1'b0;
+    csr_mtval_up        = 1'b0;
+    csr_mtvec_up        = 1'b0;
+
+`ifndef SCR1_CSR_REDUCED_CNT
+    csr_cycle_up        = 2'b00;
+    csr_instret_up      = 2'b00;
+`endif // SCR1_CSR_REDUCED_CNT
+
+`ifdef SCR1_CSR_MCOUNTEN_EN
+    csr_mcounten_up     = 1'b0;
+`endif // SCR1_CSR_MCOUNTEN_EN
+    csr_w_exc           = 1'b0;
+`ifdef SCR1_IPIC_EN
+    csr2ipic_w_req      = 1'b0;
+`endif // SCR1_IPIC_EN
+
+    if (exu2csr_w_req) begin
+        casez (exu2csr_rw_addr)
+            // Machine Trap Setup (read-write)
+            SCR1_CSR_ADDR_MSTATUS   : csr_mstatus_up    = 1'b1;
+            SCR1_CSR_ADDR_MISA      : begin end
+            SCR1_CSR_ADDR_MIE       : csr_mie_up        = 1'b1;
+            SCR1_CSR_ADDR_MTVEC     : csr_mtvec_up      = 1'b1;
+
+            // Machine Trap Handling (read-write)
+            SCR1_CSR_ADDR_MSCRATCH  : csr_mscratch_up   = 1'b1;
+            SCR1_CSR_ADDR_MEPC      : csr_mepc_up       = 1'b1;
+            SCR1_CSR_ADDR_MCAUSE    : csr_mcause_up     = 1'b1;
+            SCR1_CSR_ADDR_MTVAL     : csr_mtval_up      = 1'b1;
+            SCR1_CSR_ADDR_MIP       : begin end
+
+            // Machine Counters/Timers (read-write)
+            {SCR1_CSR_ADDR_MHPMCOUNTER_MASK, 5'b?????}  : begin
+                case (exu2csr_rw_addr[4:0])
+                    5'd1        : csr_w_exc         = 1'b1;
+`ifndef SCR1_CSR_REDUCED_CNT
+                    5'd0        : csr_cycle_up[0]   = 1'b1;
+                    5'd2        : csr_instret_up[0] = 1'b1;
+`endif // SCR1_CSR_REDUCED_CNT
+                    default     : begin
+                        // no exception
+                    end
+                endcase
+            end
+
+            {SCR1_CSR_ADDR_MHPMCOUNTERH_MASK, 5'b?????} : begin
+                case (exu2csr_rw_addr[4:0])
+                    5'd1        : csr_w_exc         = 1'b1;
+`ifndef SCR1_CSR_REDUCED_CNT
+                    5'd0        : csr_cycle_up[1]   = 1'b1;
+                    5'd2        : csr_instret_up[1] = 1'b1;
+`endif // SCR1_CSR_REDUCED_CNT
+                    default     : begin
+                        // no exception
+                    end
+                endcase
+            end
+
+            {SCR1_CSR_ADDR_MHPMEVENT_MASK, 5'b?????}    : begin
+                case (exu2csr_rw_addr[4:0])
+                    5'd0,
+                    5'd1,
+                    5'd2        : csr_w_exc = 1'b1;
+                    default     : begin
+                        // no exception
+                    end
+                endcase
+            end
+
+`ifdef SCR1_CSR_MCOUNTEN_EN
+            SCR1_CSR_ADDR_MCOUNTEN      : csr_mcounten_up   = 1'b1;
+`endif // SCR1_CSR_MCOUNTEN_EN
+
+`ifdef SCR1_IPIC_EN
+            // IPIC registers
+            SCR1_CSR_ADDR_IPIC_CICSR,
+            SCR1_CSR_ADDR_IPIC_IPR,
+            SCR1_CSR_ADDR_IPIC_EOI,
+            SCR1_CSR_ADDR_IPIC_SOI,
+            SCR1_CSR_ADDR_IPIC_IDX,
+            SCR1_CSR_ADDR_IPIC_ICSR     : begin
+                csr2ipic_w_req  = 1'b1;
+            end
+            SCR1_CSR_ADDR_IPIC_CISV,
+            SCR1_CSR_ADDR_IPIC_ISVR     : begin
+                // no exception on write
+            end
+`endif // SCR1_IPIC_EN
+
+`ifdef SCR1_DBGC_EN
+            SCR1_HDU_DBGCSR_ADDR_DCSR,
+            SCR1_HDU_DBGCSR_ADDR_DPC,
+            SCR1_HDU_DBGCSR_ADDR_DSCRATCH0,
+            SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 : begin
+            end
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_BRKM_EN
+            // TDU registers
+            SCR1_CSR_ADDR_TDU_TSELECT,
+            SCR1_CSR_ADDR_TDU_TDATA1,
+            SCR1_CSR_ADDR_TDU_TDATA2,
+            SCR1_CSR_ADDR_TDU_TINFO: begin
+            end
+`endif // SCR1_BRKM_EN
+
+            default : begin
+                csr_w_exc   = 1'b1;
+            end
+        endcase
+    end
+end
+
+// CSR exception
+assign csr2exu_rw_exc = csr_r_exc | csr_w_exc
+`ifdef SCR1_DBGC_EN
+                     | ((csr2hdu_req) & (hdu2csr_resp != SCR1_CSR_RESP_OK))
+`endif // SCR1_DBGC_EN
+`ifdef SCR1_BRKM_EN
+                     | ((csr2tdu_req) & (tdu2csr_resp != SCR1_CSR_RESP_OK))
+`endif // SCR1_BRKM_EN
+                    ;
+
+//-------------------------------------------------------------------------------
+// Events (IRQ, EXC, MRET)
+//-------------------------------------------------------------------------------
+assign csr2exu_mstatus_mie_up   = csr_mstatus_up | csr_mie_up | e_mret;
+
+// Event priority
+assign e_exc    = exu2csr_take_exc
+`ifdef SCR1_DBGC_EN
+                & ~exu_no_commit
+`endif // SCR1_DBGC_EN
+                ;
+assign e_irq    = exu2csr_take_irq & ~exu2csr_take_exc
+`ifdef SCR1_DBGC_EN
+                & ~exu_no_commit
+`endif // SCR1_DBGC_EN
+                ;
+assign e_mret   = exu2csr_mret_update
+`ifdef SCR1_DBGC_EN
+                & ~exu_no_commit
+`endif // SCR1_DBGC_EN
+                ;
+
+// IRQ exception codes priority
+always_comb begin
+    case (1'b1)
+        (csr_mip_meip & csr_mie_meie)   : csr_mcause_ec_new = type_scr1_exc_code_e'(SCR1_EXC_CODE_IRQ_M_EXTERNAL);
+        (csr_mip_msip & csr_mie_msie)   : csr_mcause_ec_new = type_scr1_exc_code_e'(SCR1_EXC_CODE_IRQ_M_SOFTWARE);
+        (csr_mip_mtip & csr_mie_mtie)   : csr_mcause_ec_new = type_scr1_exc_code_e'(SCR1_EXC_CODE_IRQ_M_TIMER);
+        default                         : csr_mcause_ec_new = type_scr1_exc_code_e'(SCR1_EXC_CODE_IRQ_M_EXTERNAL);
+    endcase
+end
+
+// MSTATUS
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_mstatus_mie     <= SCR1_CSR_MSTATUS_MIE_RST_VAL;
+        csr_mstatus_mpie    <= SCR1_CSR_MSTATUS_MPIE_RST_VAL;
+    end else begin
+        case (1'b1)
+            e_exc,
+            e_irq           : begin
+                csr_mstatus_mie     <= 1'b0;
+                csr_mstatus_mpie    <= csr_mstatus_mie;
+            end
+            e_mret          : begin
+                csr_mstatus_mie     <= csr_mstatus_mpie;
+                csr_mstatus_mpie    <= 1'b1;
+            end
+            csr_mstatus_up  : begin
+                csr_mstatus_mie     <= csr_w_data[SCR1_CSR_MSTATUS_MIE_OFFSET];
+                csr_mstatus_mpie    <= csr_w_data[SCR1_CSR_MSTATUS_MPIE_OFFSET];
+            end
+            default : begin end
+        endcase
+    end
+end
+
+// MEPC
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_mepc    <= '0;
+    end else begin
+        case (1'b1)
+            e_exc           : begin
+`ifdef SCR1_RVC_EXT
+                csr_mepc    <= curr_pc[`SCR1_XLEN-1:1];
+`else // SCR1_RVC_EXT
+                csr_mepc    <= curr_pc[`SCR1_XLEN-1:2];
+`endif // SCR1_RVC_EXT
+            end
+            (e_irq & ~exu2csr_mret_instr)   : begin
+`ifdef SCR1_RVC_EXT
+                csr_mepc    <= next_pc[`SCR1_XLEN-1:1];
+`else // SCR1_RVC_EXT
+                csr_mepc    <= next_pc[`SCR1_XLEN-1:2];
+`endif // SCR1_RVC_EXT
+            end
+            csr_mepc_up     : begin
+`ifdef SCR1_RVC_EXT
+                csr_mepc    <= csr_w_data[`SCR1_XLEN-1:1];
+`else // SCR1_RVC_EXT
+                csr_mepc    <= csr_w_data[`SCR1_XLEN-1:2];
+`endif // SCR1_RVC_EXT
+            end
+            default : begin end
+        endcase
+    end
+end
+
+// MCAUSE
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_mcause_i    <= 1'b0;
+        csr_mcause_ec   <= type_scr1_exc_code_e'(SCR1_EXC_CODE_RESET);
+    end else begin
+        case (1'b1)
+            e_exc           : begin
+                csr_mcause_i    <= 1'b0;
+                csr_mcause_ec   <= exu2csr_exc_code;
+            end
+            e_irq           : begin
+                csr_mcause_i    <= 1'b1;
+                csr_mcause_ec   <= csr_mcause_ec_new;
+            end
+            csr_mcause_up   : begin
+                csr_mcause_i    <= csr_w_data[`SCR1_XLEN-1];
+                csr_mcause_ec   <= type_scr1_exc_code_e'(csr_w_data[SCR1_EXC_CODE_WIDTH_E-1:0]);
+            end
+            default : begin end
+        endcase
+    end
+end
+
+// MTVAL
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_mtval   <= '0;
+    end else begin
+        case (1'b1)
+            e_exc           : begin
+                csr_mtval   <= exu2csr_trap_val;
+            end
+            e_irq           : begin
+                csr_mtval   <= '0;
+            end
+            csr_mtval_up    : begin
+                csr_mtval   <= csr_w_data;
+            end
+            default : begin end
+        endcase
+    end
+end
+
+assign csr_mip_mtip     = timer_irq;
+assign csr_mip_meip     = ext_irq;
+assign csr_mip_msip     = soft_irq;
+assign csr2exu_ip_ie    =   (csr_mip_meip & csr_mie_meie) |
+                            (csr_mip_msip & csr_mie_msie) |
+                            (csr_mip_mtip & csr_mie_mtie);
+assign csr2exu_irq      = csr2exu_ip_ie & csr_mstatus_mie;
+
+always_comb begin
+`ifndef SCR1_VECT_IRQ_EN
+    csr2exu_new_pc      = {csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)};
+`else // SCR1_VECT_IRQ_EN
+    if (csr_mtvec_mode == SCR1_CSR_MTVEC_MODE_VECTORED) begin
+        case (1'b1)
+            exu2csr_take_exc                : csr2exu_new_pc    = {csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)};
+            (csr_mip_meip & csr_mie_meie)   : csr2exu_new_pc    = {csr_mtvec_base, SCR1_EXC_CODE_IRQ_M_EXTERNAL, 2'd0};
+            (csr_mip_msip & csr_mie_msie)   : csr2exu_new_pc    = {csr_mtvec_base, SCR1_EXC_CODE_IRQ_M_SOFTWARE, 2'd0};
+            (csr_mip_mtip & csr_mie_mtie)   : csr2exu_new_pc    = {csr_mtvec_base, SCR1_EXC_CODE_IRQ_M_TIMER, 2'd0};
+            default                         : csr2exu_new_pc    = {csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)};
+        endcase // 1'b1
+    end else begin // direct mode
+        csr2exu_new_pc  = {csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)};
+    end
+`endif // SCR1_VECT_IRQ_EN
+    if (exu2csr_mret_instr & ~exu2csr_take_irq) begin
+`ifdef SCR1_RVC_EXT
+        csr2exu_new_pc  = {csr_mepc, 1'b0};
+`else // SCR1_RVC_EXT
+        csr2exu_new_pc  = {csr_mepc, 2'b00};
+`endif // SCR1_RVC_EXT
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Update CSR
+//-------------------------------------------------------------------------------
+
+// MIE
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_mie_mtie <= SCR1_CSR_MIE_MTIE_RST_VAL;
+        csr_mie_meie <= SCR1_CSR_MIE_MEIE_RST_VAL;
+        csr_mie_msie <= SCR1_CSR_MIE_MSIE_RST_VAL;
+    end else begin
+        if (csr_mie_up) begin
+            // CSRRW, CSRRS, CSRRC
+            csr_mie_mtie <= csr_w_data[SCR1_CSR_MIE_MTIE_OFFSET];
+            csr_mie_meie <= csr_w_data[SCR1_CSR_MIE_MEIE_OFFSET];
+            csr_mie_msie <= csr_w_data[SCR1_CSR_MIE_MSIE_OFFSET];
+        end
+    end
+end
+
+// MCOUNTEN
+`ifdef SCR1_CSR_MCOUNTEN_EN
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_mcounten_cy <= 1'b1;
+        csr_mcounten_ir <= 1'b1;
+    end else begin
+        if (csr_mcounten_up) begin
+            csr_mcounten_cy <= csr_w_data[SCR1_CSR_MCOUNTEN_CY_OFFSET];
+            csr_mcounten_ir <= csr_w_data[SCR1_CSR_MCOUNTEN_IR_OFFSET];
+        end
+    end
+end
+`endif // SCR1_CSR_MCOUNTEN_EN
+
+// MSCRATCH
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_mscratch    <= '0;
+    end else begin
+        if (csr_mscratch_up) begin
+            // CSRRW, CSRRS, CSRRC
+            csr_mscratch    <= csr_w_data;
+        end
+    end
+end
+
+// MTVEC
+generate
+    if (SCR1_CSR_MTVEC_BASE_RW_BITS == 0) begin : mtvec_base_ro
+        assign csr_mtvec_base   = SCR1_CSR_MTVEC_BASE_RST_VAL;
+    end else if (SCR1_CSR_MTVEC_BASE_RW_BITS == SCR1_CSR_MTVEC_BASE_VAL_BITS) begin : mtvec_base_rw
+        always_ff @(negedge rst_n, posedge clk) begin
+            if (~rst_n) begin
+                csr_mtvec_base  <= SCR1_CSR_MTVEC_BASE_RST_VAL;
+            end else begin
+                if (csr_mtvec_up) begin
+                    csr_mtvec_base  <= csr_w_data[`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS];
+                end
+            end
+        end
+    end else begin : mtvec_base_ro_rw
+        logic [(`SCR1_XLEN-1):(`SCR1_XLEN-SCR1_CSR_MTVEC_BASE_RW_BITS)]   csr_mtvec_base_reg;
+        always_ff @(negedge rst_n, posedge clk) begin
+            if (~rst_n) begin
+                csr_mtvec_base_reg <= SCR1_CSR_MTVEC_BASE_RST_VAL[(`SCR1_XLEN-1)-:SCR1_CSR_MTVEC_BASE_RW_BITS] ;
+            end else begin
+                if (csr_mtvec_up) begin
+                    csr_mtvec_base_reg <= csr_w_data[(`SCR1_XLEN-1)-:SCR1_CSR_MTVEC_BASE_RW_BITS];
+                end
+            end
+        end
+        assign csr_mtvec_base = {csr_mtvec_base_reg, SCR1_CSR_MTVEC_BASE_RST_VAL[SCR1_CSR_MTVEC_BASE_ZERO_BITS+:SCR1_CSR_MTVEC_BASE_RO_BITS]};
+    end
+endgenerate
+
+`ifdef SCR1_VECT_IRQ_EN
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_mtvec_mode  <= SCR1_CSR_MTVEC_MODE_DIRECT;
+    end else begin
+        if (csr_mtvec_up) begin
+            csr_mtvec_mode  <= csr_w_data[0];
+        end
+    end
+end
+`else // SCR1_VECT_IRQ_EN
+assign csr_mtvec_mode   = SCR1_CSR_MTVEC_MODE_DIRECT;
+`endif // SCR1_VECT_IRQ_EN
+
+
+`ifndef SCR1_CSR_REDUCED_CNT
+
+// CYCLE
+assign csr_cycle        = {csr_cycle_hi, csr_cycle_lo};
+assign csr_cycle_inc_lo = 1'b1
+ `ifdef SCR1_CSR_MCOUNTEN_EN
+                        & csr_mcounten_cy
+ `endif // SCR1_CSR_MCOUNTEN_EN
+                        ;
+assign csr_cycle_inc_hi = csr_cycle_inc_lo & (&csr_cycle_lo);
+
+always_comb begin
+    csr_cycle_lo_new = csr_cycle_lo;
+    csr_cycle_hi_new = csr_cycle_hi;
+
+    if (csr_cycle_inc_lo)   csr_cycle_lo_new = csr_cycle_lo + 1'b1;
+    if (csr_cycle_inc_hi)   csr_cycle_hi_new = csr_cycle_hi + 1'b1;
+
+    case (csr_cycle_up)
+        2'b01   : begin
+            csr_cycle_lo_new        = csr_w_data[7:0];
+            csr_cycle_hi_new[31:8]  = csr_w_data[31:8];
+        end
+        2'b10   : begin
+            csr_cycle_hi_new[63:32] = csr_w_data;
+        end
+        default : begin end
+    endcase
+end
+
+`ifndef SCR1_CLKCTRL_EN
+always_ff @(negedge rst_n, posedge clk) begin
+`else // SCR1_CLKCTRL_EN
+always_ff @(negedge rst_n, posedge clk_alw_on) begin
+`endif // SCR1_CLKCTRL_EN
+    if (~rst_n) begin
+        csr_cycle_lo    <= '0;
+        csr_cycle_hi    <= '0;
+    end else begin
+        if (csr_cycle_inc_lo | csr_cycle_up[0]) csr_cycle_lo <= csr_cycle_lo_new;
+        if (csr_cycle_inc_hi | (|csr_cycle_up)) csr_cycle_hi <= csr_cycle_hi_new;
+    end
+end
+
+`endif // SCR1_CSR_REDUCED_CNT
+
+`ifndef SCR1_CSR_REDUCED_CNT
+
+// INSTRET
+assign csr_instret          = {csr_instret_hi, csr_instret_lo};
+assign csr_instret_inc_lo   = instret_nexc
+ `ifdef SCR1_CSR_MCOUNTEN_EN
+                            & csr_mcounten_ir
+ `endif // SCR1_CSR_MCOUNTEN_EN
+                            ;
+assign csr_instret_inc_hi   = csr_instret_inc_lo & (&csr_instret_lo);
+
+always_comb begin
+    csr_instret_lo_new = csr_instret_lo;
+    csr_instret_hi_new = csr_instret_hi;
+
+    if (csr_instret_inc_lo) csr_instret_lo_new = csr_instret_lo + 1'b1;
+    if (csr_instret_inc_hi) csr_instret_hi_new = csr_instret_hi + 1'b1;
+
+    case (csr_instret_up)
+        2'b01   : begin
+            csr_instret_lo_new          = csr_w_data[7:0];
+            csr_instret_hi_new[31:8]    = csr_w_data[31:8];
+        end
+        2'b10   : begin
+            csr_instret_hi_new[63:32]   = csr_w_data;
+        end
+        default : begin end
+    endcase
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        csr_instret_lo  <= '0;
+        csr_instret_hi  <= '0;
+    end else begin
+        if (csr_instret_inc_lo | csr_instret_up[0]) csr_instret_lo <= csr_instret_lo_new;
+        if (csr_instret_inc_hi | (|csr_instret_up)) csr_instret_hi <= csr_instret_hi_new;
+    end
+end
+
+`endif // SCR1_CSR_REDUCED_CNT
+
+
+`ifdef SCR1_IPIC_EN
+//-------------------------------------------------------------------------------
+// IPIC
+//-------------------------------------------------------------------------------
+assign csr2ipic_addr    = (csr2ipic_r_req | csr2ipic_w_req) ? exu2csr_rw_addr[2:0] : '0;
+assign csr2ipic_wdata   = csr2ipic_w_req                    ? exu2csr_w_data       : '0;
+`endif // SCR1_IPIC_EN
+
+
+`ifdef SCR1_DBGC_EN
+//-------------------------------------------------------------------------------
+// HDU
+//-------------------------------------------------------------------------------
+assign csr2hdu_req      = csr_hdu_req & ((exu2csr_r_req & ~csr_r_exc) | (exu2csr_w_req & ~csr_w_exc));
+assign csr2hdu_cmd      = exu2csr_w_cmd;
+assign csr2hdu_addr     = exu2csr_rw_addr[SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0];
+assign csr2hdu_wdata    = exu2csr_w_data;
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_BRKM_EN
+//-------------------------------------------------------------------------------
+// TDU
+//-------------------------------------------------------------------------------
+assign csr2tdu_req      = csr_brkm_req & ((exu2csr_r_req & ~csr_r_exc) | (exu2csr_w_req & ~csr_w_exc));
+assign csr2tdu_cmd      = exu2csr_w_cmd;
+assign csr2tdu_addr     = exu2csr_rw_addr[SCR1_CSR_ADDR_TDU_OFFS_W-1:0];
+assign csr2tdu_wdata    = exu2csr_w_data;
+`endif // SCR1_BRKM_EN
+
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertions
+//-------------------------------------------------------------------------------
+
+// X checks
+
+SCR1_SVA_CSR_XCHECK_CTRL : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown({exu2csr_r_req, exu2csr_w_req, exu2csr_take_irq, exu2csr_take_exc, exu2csr_mret_update
+`ifndef SCR1_CSR_REDUCED_CNT
+    ,instret_nexc
+`endif // SCR1_CSR_REDUCED_CNT
+    })
+    ) else $error("CSR Error: unknown control values");
+
+SCR1_SVA_CSR_XCHECK_READ : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    exu2csr_r_req |-> !$isunknown({exu2csr_rw_addr, csr2exu_r_data, csr2exu_rw_exc})
+    ) else $error("CSR Error: unknown control values");
+
+SCR1_SVA_CSR_XCHECK_WRITE : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    exu2csr_w_req |-> !$isunknown({exu2csr_rw_addr, exu2csr_w_cmd, exu2csr_w_data, csr2exu_rw_exc})
+    ) else $error("CSR Error: unknown control values");
+
+`ifdef SCR1_IPIC_EN
+SCR1_SVA_CSR_XCHECK_READ_IPIC : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    csr2ipic_r_req |-> !$isunknown({csr2ipic_addr, ipic2csr_rdata})
+    ) else $error("CSR Error: unknown control values");
+
+SCR1_SVA_CSR_XCHECK_WRITE_IPIC : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    csr2ipic_w_req |-> !$isunknown({csr2ipic_addr, csr2ipic_wdata})
+    ) else $error("CSR Error: unknown control values");
+`endif // SCR1_IPIC_EN
+
+// Behavior checks
+
+SCR1_SVA_CSR_MRET : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    exu2csr_mret_update |=> ($stable(csr_mepc) & $stable(csr_mtval))
+    ) else $error("CSR Error: MRET wrong behavior");
+
+SCR1_SVA_CSR_MRET_IRQ : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (exu2csr_mret_instr & e_irq) |=> ($stable(csr_mepc) & (curr_pc !=
+`ifdef SCR1_RVC_EXT
+                                                                    {csr_mepc, 1'b0}
+`else // SCR1_RVC_EXT
+                                                                    {csr_mepc, 2'b00}
+`endif // SCR1_RVC_EXT
+    ))
+    ) else $error("CSR Error: MRET+IRQ wrong behavior");
+
+SCR1_SVA_CSR_EXC_IRQ : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (exu2csr_take_exc & exu2csr_take_irq) |=>
+    (~csr_mstatus_mie & ~($stable(csr_mepc)) & (~csr_mcause_i) & (curr_pc=={csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)}))
+    ) else $error("CSR Error: wrong EXC+IRQ");
+
+SCR1_SVA_CSR_EVENTS : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    $onehot0({e_irq, e_exc, e_mret})
+    ) else $error("CSR Error: more than one event at a time");
+
+SCR1_SVA_CSR_RW_EXC : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    csr2exu_rw_exc |-> (exu2csr_w_req | exu2csr_r_req)
+    ) else $error("CSR Error: impossible exception");
+
+SCR1_SVA_CSR_MSTATUS_MIE_UP : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    csr2exu_mstatus_mie_up |=> ~csr2exu_mstatus_mie_up
+    ) else $error("CSR Error: csr2exu_mstatus_mie_up can only be high for one cycle");
+
+
+`ifndef SCR1_CSR_REDUCED_CNT
+
+SCR1_SVA_CSR_CYCLE_INC : assert property (
+    @(
+`ifndef SCR1_CLKCTRL_EN
+negedge clk
+`else // SCR1_CLKCTRL_EN
+negedge clk_alw_on
+`endif // SCR1_CLKCTRL_EN
+    ) disable iff (~rst_n)
+    (~|csr_cycle_up) |=>
+`ifdef SCR1_CSR_MCOUNTEN_EN
+    ($past(csr_mcounten_cy) ? (csr_cycle == $past(csr_cycle + 1'b1)) : $stable(csr_cycle))
+`else //SCR1_CSR_MCOUNTEN_EN
+    (csr_cycle == $past(csr_cycle + 1'b1))
+`endif // SCR1_CSR_MCOUNTEN_EN
+    ) else $error("CSR Error: CYCLE increment wrong behavior");
+
+SCR1_SVA_CSR_INSTRET_INC : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (instret_nexc & ~|csr_instret_up) |=>
+`ifdef SCR1_CSR_MCOUNTEN_EN
+    ($past(csr_mcounten_ir) ? (csr_instret == $past(csr_instret + 1'b1)) : $stable(csr_instret))
+`else //SCR1_CSR_MCOUNTEN_EN
+    (csr_instret == $past(csr_instret + 1'b1))
+`endif // SCR1_CSR_MCOUNTEN_EN
+    ) else $error("CSR Error: INSTRET increment wrong behavior");
+
+SCR1_SVA_CSR_CYCLE_INSTRET_UP : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ~(&csr_instret_up | &csr_cycle_up)
+    ) else $error("CSR Error: INSTRET/CYCLE up illegal value");
+
+`endif // SCR1_CSR_REDUCED_CNT
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_csr
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_exu.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_exu.sv
new file mode 100644
index 0000000..af9039c
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_exu.sv
@@ -0,0 +1,814 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_pipe_exu.sv>
+/// @brief      Execution Unit (EXU)
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_arch_types.svh"
+`include "scr1_memif.svh"
+`include "scr1_riscv_isa_decoding.svh"
+`include "scr1_csr.svh"
+
+`ifdef SCR1_DBGC_EN
+ `include "scr1_hdu.svh"
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_BRKM_EN
+ `include "scr1_tdu.svh"
+`endif // SCR1_BRKM_EN
+
+module scr1_pipe_exu (
+    // Common
+    input   logic                               rst_n,
+    input   logic                               clk,
+`ifdef SCR1_CLKCTRL_EN
+    input   logic                               clk_alw_on,
+    input   logic                               clk_pipe_en,
+`endif // SCR1_CLKCTRL_EN
+
+    // IDU <-> EXU interface
+    input   logic                               idu2exu_req,            // Request form IDU to EXU
+    output  logic                               exu2idu_rdy,            // EXU ready for new data from IDU
+    input   type_scr1_exu_cmd_s                 idu2exu_cmd,            // EXU command
+    input   logic                               idu2exu_use_rs1,        // Clock gating on rs1_addr field
+    input   logic                               idu2exu_use_rs2,        // Clock gating on rs2_addr field
+`ifndef SCR1_EXU_STAGE_BYPASS
+    input   logic                               idu2exu_use_rd,         // Clock gating on rd_addr field
+    input   logic                               idu2exu_use_imm,        // Clock gating on imm field
+`endif // SCR1_EXU_STAGE_BYPASS
+
+    // EXU <-> MPRF interface
+    output  logic [`SCR1_MPRF_ADDR_WIDTH-1:0]   exu2mprf_rs1_addr,      // MPRF rs1 read address
+    input   logic [`SCR1_XLEN-1:0]              mprf2exu_rs1_data,      // MPRF rs1 read data
+    output  logic [`SCR1_MPRF_ADDR_WIDTH-1:0]   exu2mprf_rs2_addr,      // MPRF rs2 read address
+    input   logic [`SCR1_XLEN-1:0]              mprf2exu_rs2_data,      // MPRF rs2 read data
+    output  logic                               exu2mprf_w_req,         // MPRF write request
+    output  logic [`SCR1_MPRF_ADDR_WIDTH-1:0]   exu2mprf_rd_addr,       // MPRF rd write address
+    output  logic [`SCR1_XLEN-1:0]              exu2mprf_rd_data,       // MPRF rd write data
+
+    // EXU <-> CSR read/write interface
+    output  logic [SCR1_CSR_ADDR_WIDTH-1:0]     exu2csr_rw_addr,        // CSR read/write address
+    output  logic                               exu2csr_r_req,          // CSR read request
+    input   logic [`SCR1_XLEN-1:0]              csr2exu_r_data,         // CSR read data
+    output  logic                               exu2csr_w_req,          // CSR write request
+    output  type_scr1_csr_cmd_sel_e             exu2csr_w_cmd,          // CSR write command
+    output  logic [`SCR1_XLEN-1:0]              exu2csr_w_data,         // CSR write data
+    input   logic                               csr2exu_rw_exc,         // CSR read/write access exception
+
+    // EXU <-> CSR event interface
+    output  logic                               exu2csr_take_irq,       // Take IRQ trap
+    output  logic                               exu2csr_take_exc,       // Take exception trap
+    output  logic                               exu2csr_mret_update,    // MRET update CSR
+    output  logic                               exu2csr_mret_instr,     // MRET instruction
+    output  type_scr1_exc_code_e                exu2csr_exc_code,       // Exception code (see scr1_arch_types.svh)
+    output  logic [`SCR1_XLEN-1:0]              exu2csr_trap_val,       // Trap value
+    input   logic [`SCR1_XLEN-1:0]              csr2exu_new_pc,         // Exception/IRQ/MRET new PC
+    input   logic                               csr2exu_irq,            // IRQ request
+    input   logic                               csr2exu_ip_ie,          // Some IRQ pending and locally enabled
+    input   logic                               csr2exu_mstatus_mie_up, // MSTATUS or MIE update in the current cycle
+
+    // EXU <-> DMEM interface
+    output  logic                               exu2dmem_req,           // Data memory request
+    output  type_scr1_mem_cmd_e                 exu2dmem_cmd,           // Data memory command
+    output  type_scr1_mem_width_e               exu2dmem_width,         // Data memory width
+    output  logic [`SCR1_DMEM_AWIDTH-1:0]       exu2dmem_addr,          // Data memory address
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]       exu2dmem_wdata,         // Data memory write data
+    input   logic                               dmem2exu_req_ack,       // Data memory request acknowledge
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]       dmem2exu_rdata,         // Data memory read data
+    input   type_scr1_mem_resp_e                dmem2exu_resp,          // Data memory response
+
+    // EXU control
+    output  logic                               exu_exc_req,            // Exception on last instruction
+    output  logic                               brkpt,                  // Software Breakpoint (EBREAK)
+    output  logic                               exu_init_pc,            // Reset exit
+    output  logic                               wfi_run2halt,           // Transition to WFI halted state
+    output  logic                               instret,                // Instruction retired (with or without exception)
+    output  logic                               instret_nexc,           // Instruction retired (without exception)
+    output  logic                               exu_busy,               // EXU busy
+
+`ifdef SCR1_DBGC_EN
+    // EXU <-> HDU interface
+    input   logic                               exu_no_commit,          // Forbid instruction commitment
+    input   logic                               exu_irq_dsbl,           // Disable IRQ
+    input   logic                               exu_pc_advmt_dsbl,      // Forbid PC advancement
+    input   logic                               exu_dmode_sstep_en,     // Enable single-step
+    input   logic                               fetch_pbuf,             // Take instructions from Program Buffer
+    input   logic                               dbg_halted,             // Debug halted state
+    input   logic                               dbg_run2halt,           // Transition to debug halted state
+    input   logic                               dbg_halt2run,           // Transition to run state
+    input   logic                               dbg_run_start,          // First cycle of run state
+    input   logic [`SCR1_XLEN-1:0]              dbg_new_pc,             // New PC as starting point for HART Resume
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_BRKM_EN
+    // EXU <-> TDU interface
+    output type_scr1_brkm_instr_mon_s           exu2tdu_i_mon,          // Instruction monitor
+    input  logic [SCR1_TDU_ALLTRIG_NUM-1:0]     tdu2exu_i_match,        // Instruction breakpoint(s) match
+    input  logic                                tdu2exu_i_x_req,        // Instruction breakpoint exception
+    output type_scr1_brkm_lsu_mon_s             lsu2tdu_d_mon,          // Data monitor
+    input  logic                                tdu2lsu_i_x_req,        // Instruction breakpoint exception
+    input  logic [SCR1_TDU_MTRIG_NUM-1:0]       tdu2lsu_d_match,        // Data breakpoint(s) match
+    input  logic                                tdu2lsu_d_x_req,        // Data breakpoint exception
+    output logic [SCR1_TDU_ALLTRIG_NUM-1:0]     exu2tdu_bp_retire,      // Instruction with breakpoint flag retire
+    output logic                                brkpt_hw,               // Hardware breakpoint on current instruction
+`endif // SCR1_BRKM_EN
+
+    // PC interface
+`ifdef SCR1_CLKCTRL_EN
+    output  logic                               wfi_halted,             // WFI halted state
+`endif // SCR1_CLKCTRL_EN
+    output  logic [`SCR1_XLEN-1:0]              curr_pc,                // Current PC
+    output  logic [`SCR1_XLEN-1:0]              next_pc,                // Next PC
+    output  logic                               new_pc_req,             // New PC request
+    output  logic [`SCR1_XLEN-1:0]              new_pc                  // New PC data
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters declaration
+//-------------------------------------------------------------------------------
+
+localparam SCR1_JUMP_MASK = `SCR1_XLEN'hFFFF_FFFE;
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+
+// Instruction queue
+logic                           exu_queue_vd;
+type_scr1_exu_cmd_s             exu_queue;
+logic                           queue_barrier;
+
+`ifndef SCR1_EXU_STAGE_BYPASS
+logic                           idu2exu_use_rs1_r;
+logic                           idu2exu_use_rs2_r;
+`endif // SCR1_EXU_STAGE_BYPASS
+
+logic                           exu_rdy;
+
+// IALU interface
+`ifdef SCR1_RVM_EXT
+logic                           ialu_rdy;
+logic                           ialu_vd;
+`endif // SCR1_RVM_EXT
+logic [`SCR1_XLEN-1:0]          ialu_op1;
+logic [`SCR1_XLEN-1:0]          ialu_op2;
+logic [`SCR1_XLEN-1:0]          ialu_sum2_op1;
+logic [`SCR1_XLEN-1:0]          ialu_sum2_op2;
+logic [`SCR1_XLEN-1:0]          ialu_res;
+logic [`SCR1_XLEN-1:0]          ialu_sum2_res;
+logic                           ialu_cmp;
+
+// LSU signals
+logic                           lsu_req;
+logic                           lsu_rdy;
+logic [`SCR1_XLEN-1:0]          lsu_l_data;
+logic                           lsu_exc;
+type_scr1_exc_code_e            lsu_exc_code;
+
+// CSR signals
+enum logic {SCR1_CSR_INIT,
+            SCR1_CSR_RDY}       csr_access;
+
+// Exception/Interrupt signals
+logic                           exc_req;
+type_scr1_exc_code_e            exc_code;
+logic                           ifu_fault_rvi_hi;
+`ifndef SCR1_CLKCTRL_EN
+logic                           wfi_halted;      // 1 - halted after WFI retirement
+`endif // SCR1_CLKCTRL_EN
+logic                           wfi_halt_cond;
+logic                           wfi_run_cond;
+logic                           wfi_run_start;
+
+// PC signals
+logic [3:0]                     init_pc_v;
+logic                           init_pc;
+logic [`SCR1_XLEN-1:0]          inc_pc;
+
+`ifdef SCR1_DBGC_EN
+logic                           exu_exc_req_r;
+`endif // SCR1_DBGC_EN
+
+
+//-------------------------------------------------------------------------------
+// Instruction queue
+//-------------------------------------------------------------------------------
+`ifndef SCR1_EXU_STAGE_BYPASS
+
+assign queue_barrier    =   wfi_halted | wfi_run2halt | wfi_run_start
+`ifdef SCR1_DBGC_EN
+                            | dbg_halted | dbg_run2halt | (dbg_run_start & ~fetch_pbuf)
+`endif // SCR1_DBGC_EN
+;
+assign exu2idu_rdy      = exu_rdy & ~queue_barrier;
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        exu_queue_vd <= 1'b0;
+    end else begin
+        if (queue_barrier) begin
+            exu_queue_vd <= 1'b0;
+        end else if (exu_rdy) begin
+            exu_queue_vd <= idu2exu_req & ~new_pc_req;
+        end
+    end
+end
+
+always_ff @(posedge clk) begin
+    if (exu2idu_rdy & idu2exu_req) begin
+        exu_queue.instr_rvc      <= idu2exu_cmd.instr_rvc;
+        exu_queue.ialu_op        <= idu2exu_cmd.ialu_op;
+        exu_queue.ialu_cmd       <= idu2exu_cmd.ialu_cmd;
+        exu_queue.sum2_op        <= idu2exu_cmd.sum2_op;
+        exu_queue.lsu_cmd        <= idu2exu_cmd.lsu_cmd;
+        exu_queue.csr_op         <= idu2exu_cmd.csr_op;
+        exu_queue.csr_cmd        <= idu2exu_cmd.csr_cmd;
+        exu_queue.rd_wb_sel      <= idu2exu_cmd.rd_wb_sel;
+        exu_queue.jump_req       <= idu2exu_cmd.jump_req;
+        exu_queue.branch_req     <= idu2exu_cmd.branch_req;
+        exu_queue.mret_req       <= idu2exu_cmd.mret_req;
+        exu_queue.fencei_req     <= idu2exu_cmd.fencei_req;
+        exu_queue.wfi_req        <= idu2exu_cmd.wfi_req;
+        exu_queue.exc_req        <= idu2exu_cmd.exc_req;
+        exu_queue.exc_code       <= idu2exu_cmd.exc_code;
+        idu2exu_use_rs1_r        <= idu2exu_use_rs1;
+        idu2exu_use_rs2_r        <= idu2exu_use_rs2;
+        if (idu2exu_use_rs1) begin
+            exu_queue.rs1_addr   <= idu2exu_cmd.rs1_addr;
+        end
+        if (idu2exu_use_rs2) begin
+            exu_queue.rs2_addr   <= idu2exu_cmd.rs2_addr;
+        end
+        if (idu2exu_use_rd)  begin
+            exu_queue.rd_addr    <= idu2exu_cmd.rd_addr;
+        end
+        if (idu2exu_use_imm) begin
+            exu_queue.imm        <= idu2exu_cmd.imm;
+        end
+    end
+end
+
+`else // ~SCR1_EXU_STAGE_BYPASS
+
+assign queue_barrier    =   wfi_halted | wfi_run_start
+`ifdef SCR1_DBGC_EN
+                            | dbg_halted | (dbg_run_start & ~fetch_pbuf)
+`endif // SCR1_DBGC_EN
+;
+assign exu2idu_rdy      = exu_rdy & ~queue_barrier;
+assign exu_queue_vd     = idu2exu_req & ~queue_barrier;
+assign exu_queue        = idu2exu_cmd;
+
+`endif // ~SCR1_EXU_STAGE_BYPASS
+
+
+`ifdef SCR1_BRKM_EN
+//-------------------------------------------------------------------------------
+// Interface to Trigger debug Unit (TDU)
+//-------------------------------------------------------------------------------
+
+// Instruction monitor
+assign exu2tdu_i_mon.vd     = exu_queue_vd;
+assign exu2tdu_i_mon.req    = instret;
+assign exu2tdu_i_mon.addr   = curr_pc;
+
+always_comb begin
+    exu2tdu_bp_retire = '0;
+    if (exu_queue_vd) begin
+        exu2tdu_bp_retire = tdu2exu_i_match;
+        if (lsu_req) begin
+            exu2tdu_bp_retire[SCR1_TDU_MTRIG_NUM-1:0] |= tdu2lsu_d_match;
+        end
+    end
+end
+`endif // SCR1_BRKM_EN
+
+
+//-------------------------------------------------------------------------------
+// Operand Fetch
+//-------------------------------------------------------------------------------
+always_comb begin
+    // IALU
+    if (exu_queue.ialu_op == SCR1_IALU_OP_REG_REG) begin
+        ialu_op1 = mprf2exu_rs1_data;
+        ialu_op2 = mprf2exu_rs2_data;
+    end else begin
+        ialu_op1 = mprf2exu_rs1_data;
+        ialu_op2 = exu_queue.imm;
+    end
+`ifdef SCR1_RVM_EXT
+    ialu_op1 = ialu_vd ? ialu_op1 : '0;
+    ialu_op2 = ialu_vd ? ialu_op2 : '0;
+`endif // SCR1_RVM_EXT
+    // SUM2
+    if (exu_queue.sum2_op == SCR1_SUM2_OP_REG_IMM) begin
+        ialu_sum2_op1 = mprf2exu_rs1_data;
+        ialu_sum2_op2 = exu_queue.imm;
+    end else begin
+        ialu_sum2_op1 = curr_pc;
+        ialu_sum2_op2 = exu_queue.imm;
+    end
+end
+
+`ifdef SCR1_EXU_STAGE_BYPASS
+assign exu2mprf_rs1_addr    = (exu_queue_vd & idu2exu_use_rs1) ? `SCR1_MPRF_ADDR_WIDTH'(exu_queue.rs1_addr) : '0;
+assign exu2mprf_rs2_addr    = (exu_queue_vd & idu2exu_use_rs2) ? `SCR1_MPRF_ADDR_WIDTH'(exu_queue.rs2_addr) : '0;
+`else // SCR1_EXU_STAGE_BYPASS
+assign exu2mprf_rs1_addr    = (exu_queue_vd & idu2exu_use_rs1_r) ? `SCR1_MPRF_ADDR_WIDTH'(exu_queue.rs1_addr) : '0;
+assign exu2mprf_rs2_addr    = (exu_queue_vd & idu2exu_use_rs2_r) ? `SCR1_MPRF_ADDR_WIDTH'(exu_queue.rs2_addr) : '0;
+`endif // SCR1_EXU_STAGE_BYPASS
+
+
+//-------------------------------------------------------------------------------
+// Integer Arithmetic Logic Unit (IALU)
+//-------------------------------------------------------------------------------
+`ifdef SCR1_RVM_EXT
+assign ialu_vd  = exu_queue_vd & (exu_queue.ialu_cmd != SCR1_IALU_CMD_NONE)
+`ifdef SCR1_BRKM_EN
+                & ~tdu2exu_i_x_req
+`endif // SCR1_BRKM_EN
+                ;
+`endif // SCR1_RVM_EXT
+
+scr1_pipe_ialu i_ialu(
+`ifdef SCR1_RVM_EXT
+    // Common
+    .clk                (clk),
+    .rst_n              (rst_n),
+    .ialu_vd            (ialu_vd),
+    .ialu_rdy           (ialu_rdy),
+`endif // SCR1_RVM_EXT
+
+    // IALU
+    .ialu_op1           (ialu_op1),
+    .ialu_op2           (ialu_op2),
+    .ialu_cmd           (exu_queue.ialu_cmd),
+    .ialu_res           (ialu_res),
+    .ialu_cmp           (ialu_cmp),
+
+    // SUM2
+    .ialu_sum2_op1      (ialu_sum2_op1),
+    .ialu_sum2_op2      (ialu_sum2_op2),
+    .ialu_sum2_res      (ialu_sum2_res)
+);
+
+
+//-------------------------------------------------------------------------------
+// Load/Store
+//-------------------------------------------------------------------------------
+assign lsu_req  = ((exu_queue.lsu_cmd != SCR1_LSU_CMD_NONE) & exu_queue_vd);
+
+scr1_pipe_lsu i_lsu(
+    .rst_n              (rst_n),
+    .clk                (clk),
+
+    .exu2lsu_req        (lsu_req),              // Request to LSU
+    .exu2lsu_cmd        (exu_queue.lsu_cmd),    // LSU command
+    .exu2lsu_addr       (ialu_sum2_res),        // DMEM address
+    .exu2lsu_s_data     (mprf2exu_rs2_data),    // Data for store to DMEM
+    .lsu2exu_rdy        (lsu_rdy),              // LSU ready
+    .lsu2exu_l_data     (lsu_l_data),           // Loaded data form DMEM
+    .lsu2exu_exc        (lsu_exc),              // LSU exception
+    .lsu2exu_exc_code   (lsu_exc_code),         // LSU exception code
+
+`ifdef SCR1_BRKM_EN
+    .lsu2tdu_d_mon      (lsu2tdu_d_mon),
+    .tdu2lsu_i_x_req    (tdu2lsu_i_x_req),
+    .tdu2lsu_d_x_req    (tdu2lsu_d_x_req),
+`endif // SCR1_BRKM_EN
+
+    .lsu2dmem_req       (exu2dmem_req),         // DMEM request
+    .lsu2dmem_cmd       (exu2dmem_cmd),         // DMEM command
+    .lsu2dmem_width     (exu2dmem_width),       // DMEM width
+    .lsu2dmem_addr      (exu2dmem_addr),        // DMEM address
+    .lsu2dmem_wdata     (exu2dmem_wdata),       // DMEM write data
+    .dmem2lsu_req_ack   (dmem2exu_req_ack),     // DMEM request acknowledge
+    .dmem2lsu_rdata     (dmem2exu_rdata),       // DMEM read data
+    .dmem2lsu_resp      (dmem2exu_resp)         // DMEM response
+);
+
+
+//-------------------------------------------------------------------------------
+// CSR logic
+//-------------------------------------------------------------------------------
+always_comb begin
+    if (exu_queue.csr_op == SCR1_CSR_OP_REG) begin
+        exu2csr_w_data = mprf2exu_rs1_data;
+    end else begin
+        exu2csr_w_data = {'0, exu_queue.rs1_addr};    // zimm
+    end
+end
+
+always_comb begin
+    exu2csr_r_req    = 1'b0;
+    exu2csr_w_req    = 1'b0;
+    if (exu_queue_vd) begin
+        case (exu_queue.csr_cmd)
+            SCR1_CSR_CMD_WRITE  : begin
+                exu2csr_r_req   = |exu_queue.rd_addr;
+                exu2csr_w_req   = (csr_access == SCR1_CSR_INIT);
+            end
+            SCR1_CSR_CMD_SET,
+            SCR1_CSR_CMD_CLEAR  : begin
+                exu2csr_r_req   = 1'b1;
+                exu2csr_w_req   = (|exu_queue.rs1_addr) & (csr_access == SCR1_CSR_INIT);
+            end
+            default : begin end
+        endcase
+    end // exu_queue_vd
+`ifdef SCR1_BRKM_EN
+    if (tdu2exu_i_x_req) begin
+        exu2csr_r_req   = 1'b0;
+        exu2csr_w_req   = 1'b0;
+    end
+`endif // SCR1_BRKM_EN
+end
+
+assign exu2csr_rw_addr  = exu_queue.imm[SCR1_CSR_ADDR_WIDTH-1:0];
+assign exu2csr_w_cmd    = exu_queue.csr_cmd;
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        csr_access  <= SCR1_CSR_INIT;
+    end else begin
+        if (csr_access == SCR1_CSR_INIT) begin
+            if (csr2exu_mstatus_mie_up) begin
+                csr_access  <= SCR1_CSR_RDY;
+            end
+        end else begin // SCR1_CSR_RDY
+            csr_access  <= SCR1_CSR_INIT;
+        end
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Exception/MRET
+//-------------------------------------------------------------------------------
+
+`ifndef SCR1_RVC_EXT
+// Instruction fetch misalign (jump/branch)
+logic                   jb_misalign;
+logic [`SCR1_XLEN-1:0]  tmp_new_pc;
+
+assign tmp_new_pc   = ialu_sum2_res & SCR1_JUMP_MASK;
+assign jb_misalign  = exu_queue_vd & (exu_queue.jump_req | (exu_queue.branch_req & ialu_cmp)) & |tmp_new_pc[1:0];
+`endif // ~SCR1_RVC_EXT
+
+// Exception request
+assign exc_req  = exu_queue_vd & (
+                    exu_queue.exc_req
+                    | lsu_exc
+                    | csr2exu_rw_exc
+`ifndef SCR1_RVC_EXT
+                    | jb_misalign
+`endif // ~SCR1_RVC_EXT
+`ifdef SCR1_BRKM_EN
+                    | brkpt_hw
+`endif // SCR1_BRKM_EN
+                );
+
+// Exception code
+always_comb begin
+    case (1'b1)
+`ifdef SCR1_BRKM_EN
+        // Hardware breakpoint has the highest priority
+        brkpt_hw            : exc_code = SCR1_EXC_CODE_BREAKPOINT;
+`endif // SCR1_BRKM_EN
+        exu_queue.exc_req   : exc_code = exu_queue.exc_code;
+        lsu_exc             : exc_code = lsu_exc_code;
+        csr2exu_rw_exc      : exc_code = SCR1_EXC_CODE_ILLEGAL_INSTR;
+`ifndef SCR1_RVC_EXT
+        jb_misalign         : exc_code = SCR1_EXC_CODE_INSTR_MISALIGN;
+`endif // ~SCR1_RVC_EXT
+        default             : exc_code = SCR1_EXC_CODE_ECALL_M;
+    endcase // 1'b1
+end
+
+assign ifu_fault_rvi_hi     = exu_queue.instr_rvc;
+
+// Trap value
+always_comb begin
+    case (exc_code)
+`ifndef SCR1_RVC_EXT
+        SCR1_EXC_CODE_INSTR_MISALIGN        : exu2csr_trap_val  = tmp_new_pc;
+`endif // SCR1_RVC_EXT
+        SCR1_EXC_CODE_INSTR_ACCESS_FAULT    : exu2csr_trap_val  = ifu_fault_rvi_hi ? inc_pc : curr_pc;
+                                                                // inc_pc is pc+2 if ifu_fault_rvi_hi==1
+                                                                // so it points to the upper half of the
+                                                                // faulty RVI instruction
+`ifdef SCR1_MTVAL_ILLEGAL_INSTR_EN
+        SCR1_EXC_CODE_ILLEGAL_INSTR         : exu2csr_trap_val  = exu_queue.exc_req ?
+                                                                exu_queue.imm :
+                                                                {   exu2csr_rw_addr,            // CSR address
+                                                                    5'(exu_queue.rs1_addr),     // rs1 / zimm
+                                                                    exu_queue.imm[14:12],       // funct3
+                                                                    5'(exu_queue.rd_addr),      // rd
+                                                                    SCR1_OPCODE_SYSTEM,
+                                                                    SCR1_INSTR_RVI
+                                                                };
+`else // SCR1_MTVAL_ILLEGAL_INSTR_EN
+        SCR1_EXC_CODE_ILLEGAL_INSTR         : exu2csr_trap_val  = '0;
+`endif // SCR1_MTVAL_ILLEGAL_INSTR_EN
+`ifdef SCR1_BRKM_EN
+        SCR1_EXC_CODE_BREAKPOINT            : begin
+            if (tdu2exu_i_x_req)           exu2csr_trap_val    = curr_pc;
+            else if (tdu2lsu_d_x_req)      exu2csr_trap_val    = ialu_sum2_res;
+            else                            exu2csr_trap_val    = '0;
+        end
+`endif // SCR1_BRKM_EN
+        SCR1_EXC_CODE_LD_ADDR_MISALIGN,
+        SCR1_EXC_CODE_LD_ACCESS_FAULT,
+        SCR1_EXC_CODE_ST_ADDR_MISALIGN,
+        SCR1_EXC_CODE_ST_ACCESS_FAULT       : exu2csr_trap_val  = ialu_sum2_res;
+        default                             : exu2csr_trap_val  = '0;
+    endcase // exc_code
+end
+
+// MRET
+assign exu2csr_mret_instr = exu_queue_vd & exu_queue.mret_req
+`ifdef SCR1_BRKM_EN
+    & ~tdu2exu_i_x_req
+`endif // SCR1_BRKM_EN
+`ifdef SCR1_DBGC_EN
+    & ~dbg_halted
+`endif // SCR1_DBGC_EN
+    ;
+
+assign exu2csr_exc_code     = exc_code;
+
+//-------------------------------------------------------------------------------
+// Update PC
+//-------------------------------------------------------------------------------
+`ifdef SCR1_RVC_EXT
+assign inc_pc       = curr_pc + (exu_queue.instr_rvc ? `SCR1_XLEN'd2 : `SCR1_XLEN'd4);
+`else // ~SCR1_RVC_EXT
+assign inc_pc       = curr_pc + `SCR1_XLEN'd4;
+`endif // ~SCR1_RVC_EXT
+
+assign new_pc_req   = init_pc                                      // reset
+                    | exu2csr_take_irq
+                    | exu2csr_take_exc
+                    | (exu2csr_mret_instr & ~csr2exu_mstatus_mie_up)
+                    | (exu_queue_vd & exu_queue.fencei_req)         // FENCE.I
+                    | ((wfi_run_start)                              // WFI halt exit
+`ifdef SCR1_CLKCTRL_EN
+                        & clk_pipe_en
+`endif // SCR1_CLKCTRL_EN
+                        )
+`ifdef SCR1_DBGC_EN
+                    | (dbg_run_start & ~fetch_pbuf)                 // debug halt exit to RUN state
+`endif // SCR1_DBGC_EN
+                    | (exu_queue_vd & (exu_queue.jump_req | (exu_queue.branch_req & ialu_cmp)));    // jump / branch
+
+assign exu2csr_take_exc     = exc_req
+`ifdef SCR1_DBGC_EN
+                            & ~dbg_halted
+`endif // SCR1_DBGC_EN
+                            ;
+assign exu2csr_mret_update  = exu2csr_mret_instr & (csr_access == SCR1_CSR_INIT);
+assign exu2csr_take_irq     = csr2exu_irq & ~exu_busy
+`ifdef SCR1_DBGC_EN
+                            & ~exu_irq_dsbl
+                            & ~dbg_halted
+`endif // SCR1_DBGC_EN
+`ifdef SCR1_CLKCTRL_EN
+                            & clk_pipe_en
+`endif // SCR1_CLKCTRL_EN
+                            ;
+
+
+always_comb begin
+    case (1'b1)
+        init_pc                 : new_pc = SCR1_RST_VECTOR;
+        exu2csr_take_exc,
+        exu2csr_take_irq,
+        exu2csr_mret_instr      : new_pc = csr2exu_new_pc;
+`ifdef SCR1_DBGC_EN
+        (dbg_run_start & ~fetch_pbuf): new_pc = dbg_new_pc;
+`endif // SCR1_DBGC_EN
+        wfi_run_start           : new_pc = curr_pc;
+        exu_queue.fencei_req    : new_pc = inc_pc;
+        default                 : new_pc = ialu_sum2_res & SCR1_JUMP_MASK;
+    endcase
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        init_pc_v <= '0;
+    end else begin
+        if (~&init_pc_v) begin
+            init_pc_v <= {init_pc_v[2:0], 1'b1};
+        end
+    end
+end
+
+assign init_pc = ~init_pc_v[3] & init_pc_v[2];
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        curr_pc    <= SCR1_RST_VECTOR;
+    end else begin
+        if ((instret | exu2csr_take_irq
+`ifdef SCR1_DBGC_EN
+        | (dbg_run_start & ~fetch_pbuf))
+        & (~exu_pc_advmt_dsbl & ~exu_no_commit
+`endif // SCR1_DBGC_EN
+        )) begin
+            if (new_pc_req) begin
+                curr_pc <= new_pc;
+            end else begin
+                curr_pc[5:0] <= inc_pc[5:0];
+                if (inc_pc[6] ^ curr_pc[6]) begin
+                    curr_pc[`SCR1_XLEN-1:6] <= inc_pc[`SCR1_XLEN-1:6];
+                end
+            end
+        end // update PC
+    end
+end
+
+// PC to be loaded on MRET from interrupt trap
+assign next_pc  = (exu_queue_vd)
+                ? ((exu_queue.jump_req | (exu_queue.branch_req & ialu_cmp))
+                    ? (ialu_sum2_res & SCR1_JUMP_MASK)
+                    : (inc_pc))
+                : (curr_pc);
+
+
+
+`ifdef SCR1_DBGC_EN
+//-------------------------------------------------------------------------------
+// Debug, misc control logic
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        exu_exc_req_r   <= 1'b0;
+    end else begin
+        if (dbg_halt2run) begin
+            exu_exc_req_r   <= 1'b0;
+        end else if (instret) begin
+            exu_exc_req_r   <= exc_req;
+        end
+    end
+end
+
+`endif // SCR1_DBGC_EN
+
+assign exu_busy             = exu_queue_vd & ~exu_rdy;
+`ifdef SCR1_DBGC_EN
+assign exu_exc_req          = exu_queue_vd ? exc_req : exu_exc_req_r;
+`else // SCR1_DBGC_EN
+assign exu_exc_req          = exc_req;
+`endif // SCR1_DBGC_EN
+assign brkpt                = exu_queue_vd & (exu_queue.exc_code == SCR1_EXC_CODE_BREAKPOINT);
+`ifdef SCR1_BRKM_EN
+assign brkpt_hw             = tdu2exu_i_x_req | tdu2lsu_d_x_req;
+`endif // SCR1_BRKM_EN
+assign exu_init_pc          = init_pc;
+assign instret              = exu_queue_vd & exu_rdy;
+assign instret_nexc         = instret & ~exc_req;
+
+
+//-------------------------------------------------------------------------------
+// Write back to MPRF
+//-------------------------------------------------------------------------------
+always_comb begin
+    exu2mprf_w_req  = (exu_queue.rd_wb_sel != SCR1_RD_WB_NONE) & exu_queue_vd & ~exc_req
+`ifdef SCR1_DBGC_EN
+                    & ~exu_no_commit
+`endif // SCR1_DBGC_EN
+                    & ((exu_queue.rd_wb_sel == SCR1_RD_WB_CSR) ? (csr_access == SCR1_CSR_INIT) : exu_rdy);
+    exu2mprf_rd_addr = `SCR1_MPRF_ADDR_WIDTH'(exu_queue.rd_addr);
+    case (exu_queue.rd_wb_sel)
+        SCR1_RD_WB_SUM2     : exu2mprf_rd_data = ialu_sum2_res;
+        SCR1_RD_WB_IMM      : exu2mprf_rd_data = exu_queue.imm;
+        SCR1_RD_WB_INC_PC   : exu2mprf_rd_data = inc_pc;
+        SCR1_RD_WB_LSU      : exu2mprf_rd_data = lsu_l_data;
+        SCR1_RD_WB_CSR      : exu2mprf_rd_data = csr2exu_r_data;
+        default             : exu2mprf_rd_data = ialu_res;      // IALU by default
+    endcase
+end
+
+
+//-------------------------------------------------------------------------------
+// Execution ready
+//-------------------------------------------------------------------------------
+always_comb begin
+    case (1'b1)
+        lsu_req                 : exu_rdy = lsu_rdy | lsu_exc;
+`ifdef SCR1_RVM_EXT
+        ialu_vd                 : exu_rdy = ialu_rdy;
+`endif // SCR1_RVM_EXT
+        csr2exu_mstatus_mie_up  : exu_rdy = 1'b0;
+        default                 : exu_rdy = 1'b1;
+    endcase
+end
+
+
+//-------------------------------------------------------------------------------
+// WFI instruction
+//-------------------------------------------------------------------------------
+assign wfi_halt_cond    = ~csr2exu_ip_ie
+                        & ((exu_queue_vd & exu_queue.wfi_req) | wfi_run_start)
+`ifdef SCR1_DBGC_EN
+                        & ~exu_no_commit & ~exu_dmode_sstep_en & ~dbg_run2halt
+`endif // SCR1_DBGC_EN
+                        ;
+assign wfi_run_cond     = csr2exu_ip_ie;
+
+assign wfi_run2halt     = ~wfi_halted & wfi_halt_cond;
+
+always_ff @(negedge rst_n,
+`ifndef SCR1_CLKCTRL_EN
+posedge clk
+`else // SCR1_CLKCTRL_EN
+posedge clk_alw_on
+`endif // SCR1_CLKCTRL_EN
+) begin
+    if (~rst_n) begin
+        wfi_run_start  <= 1'b0;
+    end else begin
+        wfi_run_start <= (wfi_halted & wfi_run_cond & ~exu2csr_take_irq);
+    end
+end
+
+always_ff @(negedge rst_n,
+`ifndef SCR1_CLKCTRL_EN
+posedge clk
+`else // SCR1_CLKCTRL_EN
+posedge clk_alw_on
+`endif // SCR1_CLKCTRL_EN
+) begin
+    if (~rst_n) begin
+        wfi_halted  <= 1'b0;
+    end else begin
+        if (~wfi_halted & wfi_halt_cond) begin
+            wfi_halted  <= 1'b1;
+        end else if (wfi_halted & (wfi_run_cond
+`ifdef SCR1_DBGC_EN
+                                    | dbg_halt2run
+`endif // SCR1_DBGC_EN
+        )) begin
+            wfi_halted  <= 1'b0;
+        end
+    end
+end
+
+
+`ifdef SCR1_SIM_ENV
+//-------------------------------------------------------------------------------
+// Tracelog signals
+//-------------------------------------------------------------------------------
+logic [`SCR1_XLEN-1:0]      update_pc;
+logic                       update_pc_en;
+
+assign update_pc_en = (init_pc | instret | exu2csr_take_irq)
+`ifdef SCR1_DBGC_EN
+                    & ~exu_pc_advmt_dsbl & ~exu_no_commit
+`endif // SCR1_DBGC_EN
+                    ;
+assign update_pc    = new_pc_req ? new_pc : inc_pc;
+
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+// X checks
+
+SCR1_SVA_EXU_XCHECK_CTRL : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown({idu2exu_req, csr2exu_irq, csr2exu_ip_ie, lsu_req, lsu_rdy, exc_req})
+    ) else $error("EXU Error: unknown control values");
+
+SCR1_SVA_EXU_XCHECK_QUEUE : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    idu2exu_req |-> !$isunknown(idu2exu_cmd)
+    ) else $error("EXU Error: unknown values in queue");
+
+SCR1_SVA_EXU_XCHECK_CSR_RDATA : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    exu2csr_r_req |-> !$isunknown({csr2exu_r_data, csr2exu_rw_exc})
+    ) else $error("EXU Error: unknown values from CSR");
+
+// Behavior checks
+
+SCR1_SVA_EXU_ONEHOT : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    $onehot0({exu_queue.jump_req, exu_queue.branch_req, lsu_req})
+    ) else $error("EXU Error: illegal combination of control signals");
+
+SCR1_SVA_EXU_ONEHOT_EXC : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    exu_queue_vd |->
+    $onehot0({exu_queue.exc_req, lsu_exc, csr2exu_rw_exc
+`ifndef SCR1_RVC_EXT
+    , jb_misalign
+`endif
+    })
+    ) else $error("EXU Error: exceptions $onehot0 failed");
+
+`endif // VERILATOR
+
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_exu
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_hdu.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_hdu.sv
new file mode 100644
index 0000000..d70befe
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_hdu.sv
@@ -0,0 +1,895 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_pipe_hdu.sv>
+/// @brief      HART Debug Unit (HDU)
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_DBGC_EN
+`include "scr1_arch_types.svh"
+`include "scr1_riscv_isa_decoding.svh"
+`include "scr1_hdu.svh"
+
+
+module scr1_pipe_hdu #( parameter HART_PBUF_INSTR_REGOUT_EN = 1'b1 ) (
+    // Common signals
+    input  logic                                            rst_n,          // HDU reset
+    input  logic                                            clk,            // HDU clock
+    input  logic                                            clk_en,         // HDU clock enable
+`ifdef SCR1_CLKCTRL_EN
+    input   logic                                           clk_pipe_en,    // Pipeline clock enable
+`endif // SCR1_CLKCTRL_EN
+    // Control/status registers i/f
+    input  logic                                            csr_req,        // CSR i/f request
+    input  type_scr1_csr_cmd_sel_e                          csr_cmd,        // CSR i/f command
+    input  logic [SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0]         csr_addr,       // CSR i/f address
+    input  logic [`SCR1_XLEN-1:0]                           csr_wdata,      // CSR i/f write data
+    output type_scr1_csr_resp_e                             csr_resp,       // CSR i/f response
+    output logic [`SCR1_XLEN-1:0]                           csr_rdata,      // CSR i/f read data
+    // HART Run Control i/f
+    input  logic                                            pipe_rst_n_qlfy,// Pipeline reset qualifier
+    input  logic                                            dm_cmd_req,     // DM-HART Command request
+    input  type_scr1_hdu_dbgstates_e                        dm_cmd,         // DM-HART Command
+    output logic                                            dm_cmd_resp,    // DM-HART Command response
+    output logic                                            dm_cmd_rcode,   // DM-HART Command return code: 0 - Ok; 1 - Error
+    output logic                                            dm_hart_event,  // DM-HART Event: 1 if HART debug state changed
+    output type_scr1_hdu_hartstatus_s                       dm_hart_status, // DM-HART Status
+    // Program Buffer - HART instruction execution i/f
+    output logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]             dm_pbuf_addr,   // Program Buffer address - so far request only for 1 instruction
+    input  logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0]            dm_pbuf_instr,  // Program Buffer instruction
+    // HART Abstract Data regs i/f
+    output logic                                            dm_dreg_req,    // Abstract Data Register request
+    output logic                                            dm_dreg_wr,     // Abstract Data Register write
+    output logic [`SCR1_XLEN-1:0]                           dm_dreg_wdata,  // Abstract Data Register write data
+    input  logic                                            dm_dreg_resp,   // Abstract Data Register response
+    input  logic                                            dm_dreg_fail,   // Abstract Data Register fail
+    input  logic [`SCR1_XLEN-1:0]                           dm_dreg_rdata,  // Abstract Data Register read data
+    //
+`ifdef SCR1_BRKM_EN
+    // HDU <-> TDU
+    output  logic                                           hart_hwbrk_dsbl,        // Disables BRKM
+    input   logic                                           hart_tm_dmode_req,      // Trigger Module requests transition to debug mode
+    input   logic                                           hart_brkpt_hw,          // Hardware breakpoint on current instruction
+`endif // SCR1_BRKM_EN
+
+    // HART Run Status
+    input   logic                                           hart_exu_busy,          // EXU busy
+    input   logic                                           hart_instret,           // Instruction retired (with or without exception)
+    input   logic                                           hart_init_pc,           // Reset exit
+    // HART Halt Status
+    input   logic                                           hart_exu_exc_req,       // Exception request
+    input   logic                                           hart_brkpt,             // Software Breakpoint (EBREAK)
+    // HART Run Control
+    output  logic                                           hart_fetch_pbuf,        // Fetch instruction from Program Buffer
+    output  logic                                           hart_exu_no_commit,     // Forbid instruction commitment
+    output  logic                                           hart_exu_irq_dsbl,      // Disable IRQ
+    output  logic                                           hart_exu_pc_advmt_dsbl, // Forbid PC advancement
+    output  logic                                           hart_exu_dmode_sstep_en,// Enable single-step
+
+    // HART state
+    output  logic                                           hart_dbg_halted,        // Debug halted state
+    output  logic                                           hart_dbg_run2halt,      // Transition to debug halted state
+    output  logic                                           hart_dbg_halt2run,      // Transition to run state
+    output  logic                                           hart_dbg_run_start,     // First cycle of run state
+`ifndef SCR1_BRKM_EN
+    output logic                                            hart_cmd_rctl,
+`endif // SCR1_BRKM_EN
+    input  logic [`SCR1_XLEN-1:0]                           hart_pc,                // Current PC
+    output logic [`SCR1_XLEN-1:0]                           hart_new_pc,            // New PC for resume
+    //
+    input   logic                                           hart_pbuf_instr_rdy,    // Program Buffer Instruction i/f ready
+    output  logic                                           hart_pbuf_instr_vd,     // Program Buffer Instruction valid
+    output  logic                                           hart_pbuf_instr_err,    // Program Buffer Instruction i/f error
+    output  logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0]           hart_pbuf_instr         // Program Buffer Instruction itself
+);
+
+//======================================================================================================================
+// Local Parameters
+//======================================================================================================================
+localparam int unsigned SCR1_HDU_TIMEOUT           = 64;       // must be power of 2
+localparam int unsigned SCR1_HDU_TIMEOUT_WIDTH     = $clog2(SCR1_HDU_TIMEOUT);
+
+//======================================================================================================================
+// Local Types
+//======================================================================================================================
+
+
+//======================================================================================================================
+// Local Signals
+//======================================================================================================================
+// -- Debug FSM ----------------------------------------------------------------
+type_scr1_hdu_dbgstates_e                           dbg_state;
+type_scr1_hdu_dbgstates_e                           dbg_state_next;
+logic                                               dfsm_trans;
+logic                                               dfsm_trans_next;
+logic                                               dfsm_update;
+logic                                               dfsm_update_next;
+logic                                               dfsm_event;
+logic                                               dfsm_event_next;
+logic                                               dfsm_csr_update;
+logic                                               dfsm_cmd_req;
+logic                                               dfsm_pbuf_start_fetch;
+
+logic                                               dfsm_rctl_wr;
+logic                                               dfsm_rctl_clr;
+
+// -- HART Status --------------------------------------------------------------
+type_scr1_hdu_haltstatus_s                          hart_haltstatus;
+type_scr1_hdu_haltcause_e                           hart_haltcause;
+
+// -- HART Run Control ---------------------------------------------------------
+logic                                               hart_halt_req;
+logic                                               hart_halt_ack;
+logic                                               hart_resume_req;
+logic                                               hart_cmd_rcode;
+`ifdef SCR1_BRKM_EN
+logic                                               hart_cmd_rctl;
+`endif // SCR1_BRKM_EN
+type_scr1_hdu_runctrl_s                             hart_runctrl;
+logic                                               dmode_cause_sstep;
+logic                                               dmode_cause_except;
+logic                                               dmode_cause_ebreak;
+`ifdef SCR1_BRKM_EN
+logic                                               dmode_cause_tmreq;
+`endif // SCR1_BRKM_EN
+
+logic [SCR1_HDU_TIMEOUT_WIDTH-1:0]                  dbgc_timeout_cnt;
+logic                                               dbgc_timeout_flag;
+
+// -- PBUF ---------------------------------------------------------------------
+type_scr1_hdu_pbufstates_e                          pbuf_state;
+type_scr1_hdu_pbufstates_e                          pbuf_state_next;
+logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]                pbuf_addr;
+logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]                pbuf_addr_next;
+logic                                               pbuf_instr_wait_latching;
+
+// -- Run Control --------------------------------------------------------------
+
+
+// -- Debug CSRs ---------------------------------------------------------------
+// CSRs :: common
+logic                                               csr_wr;
+logic [`SCR1_XLEN-1:0]                              csr_wr_data;
+logic [`SCR1_XLEN-1:0]                              csr_rd_data;
+// CSRs :: DCSR
+logic                                               csr_dcsr_sel;
+logic                                               csr_dcsr_wr;
+type_scr1_hdu_dcsr_s                                csr_dcsr_in;
+type_scr1_hdu_dcsr_s                                csr_dcsr_out;
+logic                                               csr_dcsr_ebreakm;
+logic                                               csr_dcsr_stepie;
+logic                                               csr_dcsr_step;
+
+logic [SCR1_HDU_DCSR_CAUSE_BIT_L-
+       SCR1_HDU_DCSR_CAUSE_BIT_R:0]                 csr_dcsr_cause;
+
+// CSRs :: DPC
+logic                                               csr_dpc_sel;
+logic                                               csr_dpc_wr;
+logic [`SCR1_XLEN-1:0]                              csr_dpc_reg;
+logic [`SCR1_XLEN-1:0]                              csr_dpc_in;
+logic [`SCR1_XLEN-1:0]                              csr_dpc_out;
+// CSRs :: DSCRATCH0
+logic                                               csr_dscratch0_sel;
+logic                                               csr_dscratch0_wr;
+logic [`SCR1_XLEN-1:0]                              csr_dscratch0_out;
+type_scr1_csr_resp_e                                csr_dscratch0_resp;
+// CSRs :: DSCRATCH1
+//logic                                             csr_dscratch1_sel;
+//logic                                             csr_dscratch1_wr;
+//logic [`SCR1_XLEN-1:0]                            csr_dscratch1_reg;
+//logic [`SCR1_XLEN-1:0]                            csr_dscratch1_in;
+//logic [`SCR1_XLEN-1:0]                            csr_dscratch1_out;
+
+//======================================================================================================================
+// Logic
+//======================================================================================================================
+
+// -----------------------------------------------------------------------------
+// Debug FSM (Run Control)
+// -----------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk)
+begin
+    if (~rst_n) begin
+        dbg_state           <= SCR1_HDU_DBGSTATE_RESET;
+        dfsm_trans          <= 1'b0;
+        dfsm_update         <= 1'b0;
+        dfsm_event          <= 1'b0;
+    end
+    else begin
+        dbg_state           <= dbg_state_next;
+        dfsm_trans          <= dfsm_trans_next;
+        dfsm_update         <= dfsm_update_next;
+        dfsm_event          <= dfsm_event_next;
+    end
+end
+
+always_comb
+begin
+    dbg_state_next          = dbg_state;
+    dfsm_trans_next         = dfsm_trans;
+    dfsm_update_next        = dfsm_update;
+    dfsm_event_next         = 1'b0;
+    dfsm_csr_update         = 1'b0;
+    dfsm_cmd_req            = 1'b0;
+
+    dfsm_rctl_wr            = 1'b0;    
+    dfsm_rctl_clr           = 1'b0;
+    dfsm_pbuf_start_fetch   = 1'b0;
+    dm_cmd_resp             = 1'b0;
+    dm_cmd_rcode            = 1'b1;
+    hart_dbg_halted         = 1'b0;
+    hart_dbg_run_start      = 1'b0;
+
+    case (dbg_state)
+        SCR1_HDU_DBGSTATE_RESET: begin
+            dfsm_trans_next     = 1'b0;
+            dfsm_update_next    = 1'b0;
+
+            if (~pipe_rst_n_qlfy) begin
+                hart_dbg_halted     = 1'b1; // Prevent instruction issuing
+            end
+            else begin
+                dfsm_cmd_req        = dm_cmd_req;
+                if (hart_init_pc) begin
+                    if (dm_cmd_req) begin
+                        dm_cmd_resp     = 1'b1;
+                        dm_cmd_rcode    = 1'b0;
+                        case (dm_cmd)
+                            SCR1_HDU_DBGSTATE_DHALTED : begin
+                                dbg_state_next  = SCR1_HDU_DBGSTATE_DHALTED;
+                                dfsm_csr_update = 1'b1;
+                            end
+                            default : begin
+                                dbg_state_next  = SCR1_HDU_DBGSTATE_RUN;
+                            end
+                        endcase
+                    end
+                    else begin
+                        dbg_state_next  = SCR1_HDU_DBGSTATE_RUN;
+                        dfsm_event_next = 1'b1;
+                    end
+                end
+            end
+        end
+
+        SCR1_HDU_DBGSTATE_RUN: begin
+            if (~pipe_rst_n_qlfy) begin
+                //! hart_dbg_halted     = 1'b1; // Prevent instruction issuing
+                dfsm_trans_next     = 1'b0;
+                dfsm_update_next    = 1'b0;
+                dbg_state_next      = SCR1_HDU_DBGSTATE_RESET;
+                dfsm_event_next     = 1'b1;
+            end
+            else begin
+                if (dfsm_update) begin
+                    hart_dbg_halted     = 1'b1;
+                    dbg_state_next      = SCR1_HDU_DBGSTATE_DHALTED;
+                    dfsm_event_next     = 1'b1;
+                    dfsm_update_next    = 1'b0;
+                    dfsm_csr_update     = 1'b1;
+                    dfsm_rctl_clr       = 1'b1;
+                    dm_cmd_resp         = dm_cmd_req;
+                    dm_cmd_rcode        = 1'b0;//!  Take into account Halt Time-Out!!
+                end
+                else begin
+                    if (dfsm_trans) begin
+                        dfsm_cmd_req    = 1'b1;
+                        if (hart_halt_ack) begin
+                            dfsm_trans_next = 1'b0;
+                            dfsm_update_next = 1'b1;
+                        end
+                    end
+                    else begin
+                        if (hart_halt_ack) begin
+                            dfsm_update_next    = 1'b1;
+                        end
+                        else begin
+                            if (dm_cmd_req & (dm_cmd == SCR1_HDU_DBGSTATE_DHALTED)) begin
+                                dfsm_trans_next = 1'b1;
+                            end
+                        end
+                    end
+                end
+            end
+        end
+
+        SCR1_HDU_DBGSTATE_DHALTED: begin
+            if (~pipe_rst_n_qlfy) begin
+                hart_dbg_halted     = 1'b1; // Prevent instruction issuing
+                dfsm_trans_next     = 1'b0;
+                dfsm_update_next    = 1'b0;
+                dm_cmd_resp         = dm_cmd_req;   // Unexpected reset terminates CMD with error
+                dm_cmd_rcode        = 1'b1;
+                dbg_state_next      = SCR1_HDU_DBGSTATE_RESET;
+                dfsm_event_next     = 1'b1;
+            end
+            else begin
+                if (dfsm_update) begin
+                    dfsm_cmd_req            = 1'b1;
+                    hart_dbg_halted         = 1'b0;
+                    hart_dbg_run_start      = 1'b1;
+                    dfsm_update_next        = 1'b0;
+                    dm_cmd_resp             = 1'b1;
+                    dm_cmd_rcode            = 1'b0;
+                    dfsm_pbuf_start_fetch   = hart_cmd_rctl;
+                    dbg_state_next          = hart_cmd_rctl ? SCR1_HDU_DBGSTATE_DRUN : SCR1_HDU_DBGSTATE_RUN;
+                    dfsm_event_next         = 1'b1;
+                end
+                else begin
+                    hart_dbg_halted         = 1'b1;
+                    if (dfsm_trans) begin
+                        dfsm_cmd_req        = 1'b1;
+                        dfsm_trans_next     = 1'b0;
+                        dfsm_update_next    = 1'b1;
+                    end
+                    else begin
+                        hart_dbg_halted     = 1'b1;
+                        if (  dm_cmd_req &
+                            ((dm_cmd == SCR1_HDU_DBGSTATE_RUN) |
+                             (dm_cmd == SCR1_HDU_DBGSTATE_DRUN))
+                        ) begin
+                            dfsm_trans_next = 1'b1;
+                            dfsm_rctl_wr    = 1'b1;
+                        end
+                    end
+                end
+            end
+        end
+
+        SCR1_HDU_DBGSTATE_DRUN: begin
+            if (~pipe_rst_n_qlfy) begin
+                hart_dbg_halted     = 1'b1; // Prevent instruction issuing
+                dfsm_trans_next     = 1'b0;
+                dfsm_update_next    = 1'b0;
+                dm_cmd_resp         = dm_cmd_req;   // Unexpected reset terminates CMD with error
+                dm_cmd_rcode        = 1'b1;
+                dbg_state_next      = SCR1_HDU_DBGSTATE_RESET;
+                dfsm_event_next     = 1'b1;
+            end
+            else begin
+                if (dfsm_update) begin
+                    hart_dbg_halted     = 1'b1;
+                    dbg_state_next      = SCR1_HDU_DBGSTATE_DHALTED;
+                    dfsm_event_next     = 1'b1;
+                    dfsm_update_next    = 1'b0;
+                    dfsm_rctl_clr       = 1'b1;
+                    dm_cmd_resp         = dm_cmd_req;
+                    dm_cmd_rcode        = 1'b0;//!  Take into account Halt Time-Out!!
+                end
+                else begin
+                    if (dfsm_trans) begin
+                        dfsm_cmd_req    = 1'b1;
+                        if (hart_halt_ack) begin
+                            dfsm_trans_next = 1'b0;
+                            dfsm_update_next = 1'b1;
+                        end
+                    end
+                    else begin
+                        if (hart_halt_ack) begin
+                            dfsm_update_next    = 1'b1;
+                        end
+                        else begin
+                            if (dm_cmd_req & (dm_cmd == SCR1_HDU_DBGSTATE_DHALTED)) begin
+                                dfsm_trans_next = 1'b1;
+                            end
+                        end
+                    end
+                end
+            end
+        end
+
+        default: begin
+            dbg_state_next = SCR1_HDU_DBGSTATE_XXX;
+        end
+    endcase
+end
+
+always_comb
+begin
+    dm_hart_status              = '0;
+    dm_hart_status.dbg_state    = dbg_state;
+    dm_hart_status.except       = (dbg_state == SCR1_HDU_DBGSTATE_DHALTED) ? hart_haltstatus.except : 1'b0;
+    dm_hart_status.ebreak       = (dbg_state == SCR1_HDU_DBGSTATE_DHALTED) ?
+                                    ((hart_haltstatus.cause == SCR1_HDU_HALTCAUSE_EBREAK) ? 1'b1 : 1'b0)
+                                    : 1'b0;
+end
+assign dm_hart_event = dfsm_event;
+
+// -----------------------------------------------------------------------------
+// HART Run Status
+// -----------------------------------------------------------------------------
+
+// Debug mode entry cause
+assign dmode_cause_sstep    = hart_runctrl.redirect.sstep & hart_instret;
+assign dmode_cause_except   = (dbg_state == SCR1_HDU_DBGSTATE_DRUN) & hart_exu_exc_req
+`ifdef SCR1_BRKM_EN
+                                & (~hart_brkpt_hw)
+`endif // SCR1_BRKM_EN
+                                & (~hart_brkpt);
+assign dmode_cause_ebreak   = hart_runctrl.redirect.ebreak & hart_brkpt;
+`ifdef SCR1_BRKM_EN
+assign dmode_cause_tmreq    = hart_tm_dmode_req & hart_brkpt_hw;
+`endif // SCR1_BRKM_EN
+
+// State transition control
+assign hart_dbg_run2halt    = ~hart_dbg_halted & (
+    dbgc_timeout_flag | (
+        ~hart_exu_busy & (
+            dmode_cause_sstep |
+            dmode_cause_ebreak |
+            dmode_cause_except |
+            hart_halt_req
+`ifdef SCR1_BRKM_EN
+            | dmode_cause_tmreq
+`endif // SCR1_BRKM_EN
+            )
+        )
+    )
+`ifdef SCR1_CLKCTRL_EN
+    & clk_pipe_en
+`endif // SCR1_CLKCTRL_EN
+    ;
+
+assign hart_dbg_halt2run    = hart_dbg_halted & hart_resume_req
+`ifdef SCR1_CLKCTRL_EN
+                                & clk_pipe_en
+`endif // SCR1_CLKCTRL_EN
+    ;
+assign hart_halt_ack = hart_dbg_run2halt;
+
+// -----------------------------------------------------------------------------
+// HART Run Control
+// -----------------------------------------------------------------------------
+
+always_comb
+begin
+    hart_halt_req   = 1'b0;
+    hart_resume_req = 1'b0;
+    hart_cmd_rctl   = 1'b0;
+
+    case (dm_cmd)
+        SCR1_HDU_DBGSTATE_RUN : begin
+            hart_resume_req = dfsm_cmd_req;
+        end
+        SCR1_HDU_DBGSTATE_DRUN : begin
+            hart_resume_req = dfsm_cmd_req;
+            hart_cmd_rctl   = 1'b1;
+        end
+        SCR1_HDU_DBGSTATE_DHALTED : begin
+            hart_halt_req   = dfsm_cmd_req;
+        end
+        default : begin
+        end
+    endcase
+end
+
+always_ff @(negedge rst_n, posedge clk)
+begin
+    if (~rst_n) begin
+        hart_runctrl.irq_dsbl                   <= 1'b0;
+        hart_runctrl.fetch_src                  <= SCR1_HDU_FETCH_SRC_NORMAL;
+        hart_runctrl.pc_advmt_dsbl              <= 1'b0;
+        hart_runctrl.hwbrkpt_dsbl               <= 1'b0;
+        hart_runctrl.redirect                   <= '0;
+    end
+    else if(clk_en) begin
+        if (dfsm_rctl_clr) begin
+            hart_runctrl                                    <= '0;
+        end
+        else begin
+            if (dfsm_rctl_wr) begin
+                if (~hart_cmd_rctl) begin
+                    // Case : resume to RUN state
+                    hart_runctrl.irq_dsbl                   <= csr_dcsr_step ? ~csr_dcsr_stepie : 1'b0;
+                    hart_runctrl.fetch_src                  <= SCR1_HDU_FETCH_SRC_NORMAL;
+                    hart_runctrl.pc_advmt_dsbl              <= 1'b0;
+                    hart_runctrl.hwbrkpt_dsbl               <= 1'b0;
+                    hart_runctrl.redirect.sstep             <= csr_dcsr_step;
+                    hart_runctrl.redirect.ebreak            <= csr_dcsr_ebreakm;
+                end
+                else begin
+                    // Case : resume to DRUN state
+                    hart_runctrl.irq_dsbl                   <= 1'b1;
+                    hart_runctrl.fetch_src                  <= SCR1_HDU_FETCH_SRC_PBUF;
+                    hart_runctrl.pc_advmt_dsbl              <= 1'b1;
+                    hart_runctrl.hwbrkpt_dsbl               <= 1'b1;
+                    hart_runctrl.redirect.sstep             <= 1'b0;
+                    hart_runctrl.redirect.ebreak            <= 1'b1;
+                end
+            end
+        end
+    end
+end
+
+assign hart_fetch_pbuf          = hart_runctrl.fetch_src;
+assign hart_exu_irq_dsbl        = hart_runctrl.irq_dsbl;
+assign hart_exu_pc_advmt_dsbl   = hart_runctrl.pc_advmt_dsbl;
+`ifdef SCR1_BRKM_EN
+assign hart_hwbrk_dsbl          = hart_runctrl.hwbrkpt_dsbl;
+`endif // SCR1_BRKM_EN
+// No change in arch. state if dmode caused by breakpoint
+assign hart_exu_no_commit       = dmode_cause_ebreak
+`ifdef SCR1_BRKM_EN
+                                | dmode_cause_tmreq
+`endif // SCR1_BRKM_EN
+    ;
+assign hart_exu_dmode_sstep_en  = hart_runctrl.redirect.sstep;
+
+// -----------------------------------------------------------------------------
+// HART Halt Status
+// -----------------------------------------------------------------------------
+always_comb
+begin
+    case (1'b1)
+`ifdef SCR1_BRKM_EN
+        // Trigger Module request has the highest priority
+        dmode_cause_tmreq   : hart_haltcause = SCR1_HDU_HALTCAUSE_TMREQ;
+`endif // SCR1_BRKM_EN
+        dmode_cause_ebreak  : hart_haltcause = SCR1_HDU_HALTCAUSE_EBREAK;
+        hart_halt_req       : hart_haltcause = SCR1_HDU_HALTCAUSE_DMREQ;
+        dmode_cause_sstep   : hart_haltcause = SCR1_HDU_HALTCAUSE_SSTEP;
+        default             : hart_haltcause = SCR1_HDU_HALTCAUSE_NONE;
+    endcase
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        hart_haltstatus                  <= '0;
+    end else begin
+        if (hart_halt_ack) begin
+            hart_haltstatus.except       <= dmode_cause_except;
+            // Debug mode entry cause
+            hart_haltstatus.cause        <= hart_haltcause;
+        end
+    end
+end
+
+// -----------------------------------------------------------------------------
+// Halt Request Time-Out
+// -----------------------------------------------------------------------------
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        dbgc_timeout_cnt <= '1;
+    end else begin
+        if (hart_dbg_halt2run) begin
+            dbgc_timeout_cnt <= '1;
+        end
+        else if (hart_halt_req & ~hart_dbg_run2halt) begin
+            dbgc_timeout_cnt <= dbgc_timeout_cnt - 1'b1;
+        end
+    end
+end
+assign dbgc_timeout_flag = ~|dbgc_timeout_cnt;
+
+// -----------------------------------------------------------------------------
+// Program Buffer (PBUF)
+// -----------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk)
+begin
+    if (~rst_n) begin
+        pbuf_state <= SCR1_HDU_PBUFSTATE_IDLE;
+        pbuf_addr  <= '0;
+    end
+    else if(clk_en) begin
+        pbuf_state <= pbuf_state_next;
+        pbuf_addr  <= pbuf_addr_next;
+    end
+end
+assign dm_pbuf_addr = pbuf_addr;
+
+always_comb
+begin
+    pbuf_state_next         = pbuf_state;
+    pbuf_addr_next          = pbuf_addr;
+    hart_pbuf_instr_vd      = 1'b0;
+    hart_pbuf_instr_err     = 1'b0;
+
+    case (pbuf_state)
+
+        SCR1_HDU_PBUFSTATE_IDLE: begin
+            pbuf_addr_next = '0;
+            if (dfsm_pbuf_start_fetch) begin
+                pbuf_state_next = SCR1_HDU_PBUFSTATE_FETCH;
+            end
+        end
+
+        SCR1_HDU_PBUFSTATE_FETCH: begin
+            hart_pbuf_instr_vd      = ~pbuf_instr_wait_latching;
+            if (hart_exu_exc_req) begin
+                pbuf_state_next     = SCR1_HDU_PBUFSTATE_WAIT4END;
+            end
+            else begin
+                if (hart_pbuf_instr_vd & hart_pbuf_instr_rdy) begin
+                    if (pbuf_addr == (SCR1_HDU_PBUF_ADDR_SPAN-1)) begin
+                        pbuf_state_next = SCR1_HDU_PBUFSTATE_EXCINJECT;
+                    end
+                    else begin
+                        pbuf_addr_next = pbuf_addr + 1'b1;
+                    end
+                end
+            end
+        end
+
+        SCR1_HDU_PBUFSTATE_EXCINJECT: begin
+            hart_pbuf_instr_vd      = ~pbuf_instr_wait_latching;
+            hart_pbuf_instr_err     = 1'b1;
+            if (hart_exu_exc_req) begin
+                pbuf_state_next     = SCR1_HDU_PBUFSTATE_WAIT4END;
+            end
+            else begin
+                if (hart_pbuf_instr_vd & hart_pbuf_instr_rdy) begin
+                    pbuf_state_next = SCR1_HDU_PBUFSTATE_WAIT4END;
+                end
+            end
+        end
+
+        SCR1_HDU_PBUFSTATE_WAIT4END: begin
+            if (hart_dbg_halted) begin
+                pbuf_state_next = SCR1_HDU_PBUFSTATE_IDLE;
+            end
+        end
+
+        default: begin
+        end
+    endcase
+end
+
+// Pass instruction from debug program buffer to cpu pipeline with two options:
+// - through register, better for frequency
+// - through wires, better for area
+generate if( HART_PBUF_INSTR_REGOUT_EN == 1'b1  ) begin // Pass trhough register
+    always @(posedge clk, negedge rst_n) begin
+        if( ~rst_n ) pbuf_instr_wait_latching <= 1'b0;
+        else         pbuf_instr_wait_latching <= hart_pbuf_instr_vd & hart_pbuf_instr_rdy;
+    end
+
+    always @(posedge clk) begin
+        hart_pbuf_instr <= dm_pbuf_instr;
+    end
+end else begin // Pass trhough wires
+    assign pbuf_instr_wait_latching = 1'b0;
+    assign hart_pbuf_instr          = dm_pbuf_instr;
+end endgenerate
+
+// -----------------------------------------------------------------------------
+// CSRs :: Interface
+// -----------------------------------------------------------------------------
+
+// CSRs :: Interface :: Reg Select
+always_comb
+begin : csr_if_regsel
+    csr_dcsr_sel        = 1'b0;
+    csr_dpc_sel         = 1'b0;
+    csr_dscratch0_sel   = 1'b0;
+    //csr_dscratch1_sel   = 1'b0;
+
+    if (csr_req == 1'b1) begin
+        case (csr_addr)
+            SCR1_HDU_DBGCSR_OFFS_DCSR : begin
+                csr_dcsr_sel        = 1'b1;
+            end
+
+            SCR1_HDU_DBGCSR_OFFS_DPC : begin
+                csr_dpc_sel         = 1'b1;
+            end
+
+            SCR1_HDU_DBGCSR_OFFS_DSCRATCH0 : begin
+                csr_dscratch0_sel   = 1'b1;
+            end
+
+            //SCR1_HDU_DBGCSR_OFFS_DSCRATCH1 : begin
+            //    csr_dscratch1_sel   = 1'b1;
+            //end
+
+            default : begin
+                csr_dcsr_sel        = 1'bX;
+                csr_dpc_sel         = 1'bX;
+                csr_dscratch0_sel   = 1'bX;
+                //csr_dscratch1_sel   = 1'bX;
+            end
+        endcase
+    end
+end : csr_if_regsel
+
+// CSRs :: Interface :: Read Data
+always_comb
+begin : csr_if_rddata
+
+    csr_rd_data =   csr_dcsr_out      |
+                    csr_dpc_out       |
+//                    csr_dscratch1_out |
+                    csr_dscratch0_out;
+end : csr_if_rddata
+
+// CSRs :: Interface :: Writing
+always_comb
+begin : csr_if_write
+    csr_wr          = 1'b0;
+    csr_wr_data     = '0;
+
+    if (csr_req == 1'b1) begin
+        case (csr_cmd)
+            SCR1_CSR_CMD_WRITE : begin
+                csr_wr          = 1'b1;
+                csr_wr_data     = csr_wdata;
+            end
+
+            SCR1_CSR_CMD_SET : begin
+                csr_wr          = 1'b1;
+                csr_wr_data     = csr_rd_data | ( csr_wdata);
+            end
+
+            SCR1_CSR_CMD_CLEAR : begin
+                csr_wr          = 1'b1;
+                csr_wr_data     = csr_rd_data & (~csr_wdata);
+            end
+
+            default : begin
+                csr_wr_data     = 'X;
+            end
+        endcase
+    end
+end : csr_if_write
+
+// CSRs :: Interface :: Response
+always_comb
+begin
+    if (dbg_state == SCR1_HDU_DBGSTATE_DRUN) begin
+        case (csr_addr)
+                SCR1_HDU_DBGCSR_OFFS_DSCRATCH0 : begin
+                    csr_resp = csr_dscratch0_resp;
+                end
+
+                default : begin
+                    csr_resp = (csr_req == 1'b1) ?
+                                SCR1_CSR_RESP_OK :
+                                SCR1_CSR_RESP_ER;
+                end
+        endcase
+    end
+    else begin
+        csr_resp = SCR1_CSR_RESP_ER;
+    end
+end
+assign csr_rdata   = csr_rd_data;
+
+// -----------------------------------------------------------------------------
+// CSRs :: DCSR
+// -----------------------------------------------------------------------------
+always_comb
+begin
+    csr_dcsr_in                 = csr_wr_data;
+    csr_dcsr_wr                 = csr_wr & csr_dcsr_sel;
+
+    csr_dcsr_out                = '0;
+    if (csr_dcsr_sel) begin
+        csr_dcsr_out.xdebugver  = SCR1_HDU_DEBUGCSR_DCSR_XDEBUGVER;
+        csr_dcsr_out.ebreakm    = csr_dcsr_ebreakm;
+        csr_dcsr_out.stepie     = csr_dcsr_stepie;
+        csr_dcsr_out.step       = csr_dcsr_step;
+        csr_dcsr_out.prv        = 2'b11;
+        csr_dcsr_out.cause      = csr_dcsr_cause;
+    end
+end
+
+always_ff @(negedge rst_n, posedge clk)
+begin
+    if (rst_n == 1'b0) begin
+        csr_dcsr_ebreakm        <= 1'b0;
+        csr_dcsr_stepie         <= 1'b0;
+        csr_dcsr_step           <= 1'b0;
+    end
+    else if(clk_en) begin
+        if (csr_dcsr_wr) begin
+            csr_dcsr_ebreakm    <= csr_dcsr_in.ebreakm;
+            csr_dcsr_stepie     <= csr_dcsr_in.stepie;
+            csr_dcsr_step       <= csr_dcsr_in.step;
+        end
+    end
+end
+
+always_ff @(negedge rst_n, posedge clk)
+begin
+    if (rst_n == 1'b0) begin
+        csr_dcsr_cause <= 1'b0;
+    end
+    else if(clk_en) begin
+        if(dfsm_csr_update) begin
+            csr_dcsr_cause <= hart_haltstatus.cause;
+        end
+    end
+end
+
+
+// -----------------------------------------------------------------------------
+// CSRs :: DPC
+// -----------------------------------------------------------------------------
+always_comb
+begin
+    csr_dpc_in                 = csr_wr_data;
+    csr_dpc_wr                 = csr_wr & csr_dpc_sel;
+
+    csr_dpc_out                = csr_dpc_sel ? csr_dpc_reg : '0;
+end
+
+always_ff @(negedge rst_n, posedge clk)
+begin
+    if (rst_n == 1'b0) begin
+        csr_dpc_reg        <= '0;
+    end
+    else if(clk_en) begin
+        if (dfsm_csr_update) begin
+            csr_dpc_reg    <= hart_pc;
+        end
+        else if (csr_dpc_wr) begin
+            csr_dpc_reg    <= csr_dpc_in;
+        end
+    end
+end
+assign hart_new_pc = csr_dpc_reg;
+
+// -----------------------------------------------------------------------------
+// CSRs :: DSCRATCH0
+// -----------------------------------------------------------------------------
+always_comb
+begin
+    dm_dreg_req         = csr_dscratch0_sel;
+    dm_dreg_wr          = csr_wr & csr_dscratch0_sel;
+    dm_dreg_wdata       = csr_wr_data;
+    csr_dscratch0_out   = csr_dscratch0_sel ? dm_dreg_rdata : '0;
+
+    csr_dscratch0_resp  = dm_dreg_resp ?
+                            (dm_dreg_fail ? SCR1_CSR_RESP_ER : SCR1_CSR_RESP_OK) :
+                            SCR1_CSR_RESP_ER;
+end
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+SVA_HDU_XCHECK_COMMON :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown( {rst_n,clk,clk_en,csr_req,pipe_rst_n_qlfy} )
+    )
+    else $error("HDU Error: common signals are in X state");
+
+SVA_HDU_XCHECK_CSR_INTF :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        csr_req |-> !$isunknown( {csr_cmd,csr_addr,csr_wdata} )
+    )
+    else $error("HDU Error: CSR i/f is in X state");
+
+SVA_HDU_XCHECK_DM_INTF :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown( {dm_cmd_req,dm_cmd,dm_dreg_resp,
+        dm_dreg_fail} )
+    )
+    else $error("HDU Error: DM i/f is in X state");
+
+SVA_HDU_XCHECK_TDU_INTF :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown( {hart_tm_dmode_req,hart_brkpt_hw} )
+    )
+    else $error("HDU Error: TDU i/f is in X state");
+
+SVA_HDU_XCHECK_HART_INTF :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown( {hart_exu_busy,hart_instret,hart_init_pc,hart_exu_exc_req,hart_brkpt,
+        hart_pc,hart_pbuf_instr_rdy} )
+    )
+    else $error("HDU Error: HART i/f is in X state");
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_hdu
+
+`endif // SCR1_DBGC_EN
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_ialu.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_ialu.sv
new file mode 100644
index 0000000..70bef39
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_ialu.sv
@@ -0,0 +1,602 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_pipe_ialu.sv>
+/// @brief      Integer Arithmetic Logic Unit (IALU)
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_riscv_isa_decoding.svh"
+`include "scr1_search_ms1.svh"
+
+
+module scr1_pipe_ialu (
+`ifdef SCR1_RVM_EXT
+    // Common
+    input   logic                           clk,
+    input   logic                           rst_n,
+    input   logic                           ialu_vd,
+    output  logic                           ialu_rdy,
+`endif // SCR1_RVM_EXT
+
+    // IALU input
+    input   logic [`SCR1_XLEN-1:0]          ialu_op1,
+    input   logic [`SCR1_XLEN-1:0]          ialu_op2,
+    input   type_scr1_ialu_cmd_sel_e        ialu_cmd,
+    // IALU output
+    output  logic [`SCR1_XLEN-1:0]          ialu_res,
+    output  logic                           ialu_cmp,
+
+    // SUM2 input
+    input   logic [`SCR1_XLEN-1:0]          ialu_sum2_op1,
+    input   logic [`SCR1_XLEN-1:0]          ialu_sum2_op2,
+    // SUM2 output
+    output  logic [`SCR1_XLEN-1:0]          ialu_sum2_res
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters declaration
+//-------------------------------------------------------------------------------
+
+`ifdef SCR1_RVM_EXT
+ `ifndef SCR1_FAST_MUL
+localparam SCR1_MUL_WIDTH       = 1;
+localparam SCR1_MUL_INIT_CNT    = (`SCR1_XLEN/SCR1_MUL_WIDTH)-1;
+ `endif // ~SCR1_FAST_MUL
+localparam SCR1_DIV_WIDTH       = 1;
+localparam SCR1_DIV_INIT_CNT    = (`SCR1_XLEN/SCR1_DIV_WIDTH)-1;
+`endif // SCR1_RVM_EXT
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+typedef struct packed {
+    logic       z;      // Zero
+    logic       s;      // Sign
+    logic       o;      // Overflow
+    logic       c;      // Carry
+} type_scr1_ialu_flags_s;
+
+ `ifdef SCR1_RVM_EXT
+typedef enum logic [1:0] {
+    SCR1_IALU_FSM_IDLE,
+    SCR1_IALU_FSM_ITER,
+    SCR1_IALU_FSM_CORR
+} type_scr1_ialu_fsm_state;
+
+typedef enum logic [1:0] {
+   SCR1_IALU_MDU_NONE,
+   SCR1_IALU_MDU_MUL,
+   SCR1_IALU_MDU_DIV
+} type_scr1_ialu_mdu_cmd;
+ `endif // SCR1_RVM_EXT
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+
+`ifdef SCR1_RVM_EXT
+type_scr1_ialu_fsm_state                    curr_state;     // Current FSM state
+type_scr1_ialu_fsm_state                    next_state;     // Next FSM state
+logic                                       iter_req;       // Request iterative stage
+logic                                       iter_rdy;       // Request iterative stage
+type_scr1_ialu_mdu_cmd                      mdu_cmd;        // MDU command: 00 - NONE, 01 - MUL,  10 - DIV
+logic [1:0]                                 mul_cmd;        // MUL command: 00 - MUL,  01 - MULH, 10 - MULHSU, 11 - MULHU
+logic [1:0]                                 div_cmd;        // DIV command: 00 - DIV,  01 - DIVU, 10 - REM,    11 - REMU
+logic                                       corr_req;       // DIV correction request
+`endif // SCR1_RVM_EXT
+
+logic                                       sum1_sub;       // SUM1 operation: 0 - add, 1 - sub
+logic [31:0]                                sum1_op1;       // SUM1 operand 1
+logic [31:0]                                sum1_op2;       // SUM1 operand 2
+logic [32:0]                                sum1_res;       // SUM1 result
+type_scr1_ialu_flags_s                      sum1_flags;     // SUM1 flags
+
+`ifdef SCR1_RVM_EXT
+logic                                       sum2_sub;       // SUM2 operation: 0 - add, 1 - sub
+logic signed [32:0]                         sum2_op1;       // SUM2 operand 1
+ `ifdef SCR1_FAST_MUL
+logic signed [32:0]                         sum2_op2;       // SUM2 operand 2
+logic signed [32:0]                         sum2_res;       // SUM2 result
+ `else // ~SCR1_FAST_MUL
+logic signed [(32+SCR1_MUL_WIDTH)-1:0]      sum2_op2;       // SUM2 operand 2
+logic signed [(32+SCR1_MUL_WIDTH)-1:0]      sum2_res;       // SUM2 result
+ `endif // ~SCR1_FAST_MUL
+`endif // SCR1_RVM_EXT
+
+logic signed [31:0]                         shft_op1;       // SHIFT operand 1
+logic [4:0]                                 shft_op2;       // SHIFT operand 2
+logic [1:0]                                 shft_cmd;       // SHIFT command: 00 - logical left, 10 - logical right, 11 - arithmetical right
+logic [31:0]                                shft_res;       // SHIFT result
+
+`ifdef SCR1_RVM_EXT
+logic signed [32:0]                         mul_op1;        // MUL operand 1
+ `ifdef SCR1_FAST_MUL
+logic signed [32:0]                         mul_op2;        // MUL operand 1
+logic signed [63:0]                         mul_res;        // MUL result
+ `else // ~SCR1_FAST_MUL
+logic signed [SCR1_MUL_WIDTH:0]             mul_op2;        // MUL operand 2
+logic signed [(32+SCR1_MUL_WIDTH)-1:0]      mul_res;        // MUL result
+ `endif // ~SCR1_FAST_MUL
+`endif // SCR1_RVM_EXT
+
+`ifdef SCR1_RVM_EXT
+logic [4:0]                                 cnt_res;
+logic [4:0]                                 cnt_res_reg;
+logic                                       res32_1_c;
+logic                                       res32_1_c_reg;
+logic [31:0]                                res32_1;
+logic [31:0]                                res32_1_reg;
+logic [31:0]                                res32_2;
+logic [31:0]                                res32_2_reg;
+logic [31:0]                                res32_3;
+logic [31:0]                                res32_3_reg;
+`endif // SCR1_RVM_EXT
+
+
+`ifdef SCR1_RVM_EXT
+//-------------------------------------------------------------------------------
+// Control State Machine
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        curr_state <= SCR1_IALU_FSM_IDLE;
+    end else begin
+        if (~ialu_vd) begin
+            curr_state  <= SCR1_IALU_FSM_IDLE;
+        end else begin
+            curr_state  <= next_state;
+        end
+    end
+end
+
+
+always_comb begin
+    next_state = curr_state;
+    case (curr_state)
+        SCR1_IALU_FSM_IDLE : begin
+            // Switch to ITER if mul, div
+            if (iter_req) begin
+                next_state = SCR1_IALU_FSM_ITER;
+            end
+        end
+        SCR1_IALU_FSM_ITER : begin
+            // End of ITER if calculation completed
+            if (iter_rdy) begin
+                // Switch to CORR if need correction
+                if (corr_req) begin
+                    next_state = SCR1_IALU_FSM_CORR;
+                end else begin
+                    next_state = SCR1_IALU_FSM_IDLE;
+                end
+            end
+        end
+        SCR1_IALU_FSM_CORR : begin
+            next_state = SCR1_IALU_FSM_IDLE;
+        end
+    endcase
+end
+`endif // SCR1_RVM_EXT
+
+//-------------------------------------------------------------------------------
+// SUM1 - main adder
+//-------------------------------------------------------------------------------
+always_comb begin
+    // MUXs to SUM1
+    sum1_sub    = (ialu_cmd != SCR1_IALU_CMD_ADD);
+    sum1_op1    = ialu_op1;
+    sum1_op2    = ialu_op2;
+`ifdef SCR1_RVM_EXT
+    case (mdu_cmd)
+        SCR1_IALU_MDU_DIV : begin
+            case (curr_state)
+                SCR1_IALU_FSM_IDLE,
+                SCR1_IALU_FSM_ITER : begin
+                    sum1_sub    = 1'b1;
+                    sum1_op1    = (curr_state == SCR1_IALU_FSM_IDLE)
+                                    ? SCR1_DIV_INIT_CNT
+                                    : ($signed({'0, cnt_res_reg}));
+                    sum1_op2    = 32'sb1;
+                end
+                SCR1_IALU_FSM_CORR : begin
+                    sum1_sub    = 1'b1;
+                    sum1_op1    = '0;
+                    sum1_op2    = $signed(res32_2_reg);
+                end
+            endcase
+        end
+ `ifndef SCR1_FAST_MUL
+        SCR1_IALU_MDU_MUL : begin
+            sum1_sub    = 1'b1;
+            if (curr_state == SCR1_IALU_FSM_IDLE) begin
+                sum1_op1    = SCR1_MUL_INIT_CNT;
+            end else begin
+                sum1_op1    = $signed({'0, cnt_res_reg});
+            end
+            sum1_op2    = 32'sb1;
+        end
+ `endif // ~SCR1_FAST_MUL
+        default : begin end
+    endcase
+`endif // SCR1_RVM_EXT
+
+    // SUM1
+    sum1_res     = (sum1_sub)
+                        ? (sum1_op1 - sum1_op2)   // Subtraction and comparison
+                        : (sum1_op1 + sum1_op2);  // Addition
+
+    // FLAGS1 - flags for comparison (result of subtraction)
+    sum1_flags.c = sum1_res[`SCR1_XLEN];
+    sum1_flags.z = ~|sum1_res[`SCR1_XLEN-1:0];
+    sum1_flags.s = sum1_res[`SCR1_XLEN-1];
+    sum1_flags.o = (~sum1_op1[`SCR1_XLEN-1] &  sum1_op2[`SCR1_XLEN-1] &  sum1_res[`SCR1_XLEN-1]) |
+                   ( sum1_op1[`SCR1_XLEN-1] & ~sum1_op2[`SCR1_XLEN-1] & ~sum1_res[`SCR1_XLEN-1]);
+end
+
+`ifdef SCR1_RVM_EXT
+assign cnt_res     = sum1_res[4:0];
+`endif // SCR1_RVM_EXT
+
+
+//-------------------------------------------------------------------------------
+// SUM2 - additional adder
+//-------------------------------------------------------------------------------
+`ifdef SCR1_RVM_EXT
+always_comb begin
+    sum2_sub    = 1'b0;
+    sum2_op1    = $signed(ialu_sum2_op1);
+    sum2_op2    = $signed(ialu_sum2_op2);
+    case (mdu_cmd)
+        SCR1_IALU_MDU_DIV : begin
+            case (curr_state)
+                SCR1_IALU_FSM_IDLE,
+                SCR1_IALU_FSM_ITER : begin
+                    logic           sgn;
+                    logic           inv;
+                    sgn         = (curr_state == SCR1_IALU_FSM_IDLE)
+                                    ? (1'b0)
+                                    : (~res32_2_reg[0]);
+                    inv         = (~div_cmd[0] & (ialu_op1[31] ^ ialu_op2[31]));
+                    sum2_sub    = ~inv ^ sgn;
+                    sum2_op1    = (curr_state == SCR1_IALU_FSM_IDLE)
+                                    ? $signed({(~div_cmd[0] & ialu_op1[31]), ialu_op1[31]})
+                                    : $signed({res32_1_reg[31:0], res32_3_reg[31]});
+                    sum2_op2    = $signed({(~div_cmd[0] & ialu_op2[31]), ialu_op2});
+                end
+                SCR1_IALU_FSM_CORR : begin
+                    logic           sgn;
+                    logic           inv;
+                    sgn         = (~div_cmd[0] & ialu_op1[31]) ^ res32_1_c_reg;
+                    inv         = (~div_cmd[0] & (ialu_op1[31] ^ ialu_op2[31]));
+                    sum2_sub    = ~inv ^ sgn;
+                    sum2_op1    = $signed({1'b0, res32_1_reg});
+                    sum2_op2    = $signed({(~div_cmd[0] & ialu_op2[31]), ialu_op2});
+                end
+                default : begin end
+            endcase
+        end
+`ifndef SCR1_FAST_MUL
+        SCR1_IALU_MDU_MUL : begin
+            sum2_sub    = ~mul_cmd[1] & ialu_op2[31] & sum1_res[32];
+            sum2_op1    = (curr_state == SCR1_IALU_FSM_IDLE)
+                            ? ('0)
+                            : ($signed({(~&mul_cmd & res32_1_reg[31]), res32_1_reg}));
+            sum2_op2    = $signed(mul_res);
+        end
+`endif // SCR1_FAST_MUL
+       default : begin end
+   endcase
+    sum2_res     = (sum2_sub)
+                    ? (sum2_op1 - sum2_op2)   // Subtraction
+                    : (sum2_op1 + sum2_op2);  // Addition
+end
+assign ialu_sum2_res = sum2_res[31:0];
+`else // ~SCR1_RVM_EXT
+assign ialu_sum2_res = ialu_sum2_op1 + ialu_sum2_op2;  // Addition
+`endif // ~SCR1_RVM_EXT
+
+
+//-------------------------------------------------------------------------------
+// SHIFT
+//-------------------------------------------------------------------------------
+always_comb begin
+    shft_op1    = ialu_op1;
+    shft_op2    = ialu_op2[4:0];
+    case (shft_cmd)
+        2'b10   : shft_res = shft_op1  >> shft_op2;
+        2'b11   : shft_res = shft_op1 >>> shft_op2;
+        default : shft_res = shft_op1  << shft_op2;
+    endcase
+end
+
+
+ `ifdef SCR1_RVM_EXT
+//-------------------------------------------------------------------------------
+// MUL - multiplier
+//-------------------------------------------------------------------------------
+always_comb begin
+    mul_op1 = '0;
+    mul_op2 = '0;
+    mul_res = '0;
+    if (mdu_cmd == SCR1_IALU_MDU_MUL) begin
+        mul_op1 = $signed({(~&mul_cmd   & ialu_op1[31]), ialu_op1});
+`ifdef SCR1_FAST_MUL
+        mul_op2 = $signed({(~mul_cmd[1] & ialu_op2[31]), ialu_op2});
+`else // ~SCR1_FAST_MUL
+        mul_op2 = (curr_state == SCR1_IALU_FSM_IDLE)
+                        ? ($signed({1'b0, ialu_op2[SCR1_MUL_WIDTH-1:0]}))
+                        : ($signed({1'b0, res32_2_reg[SCR1_MUL_WIDTH-1:0]}));
+`endif // ~SCR1_FAST_MUL
+        mul_res = mul_op1 * mul_op2;
+    end
+end
+
+
+//-------------------------------------------------------------------------------
+// DIV - divider
+//-------------------------------------------------------------------------------
+always_comb begin
+    res32_1_c   = '0;
+    res32_1     = '0;
+    res32_2     = '0;
+    res32_3     = '0;
+    case (mdu_cmd)
+        SCR1_IALU_MDU_DIV : begin
+            case (curr_state)
+                SCR1_IALU_FSM_IDLE,
+                SCR1_IALU_FSM_ITER : begin
+                    logic [30:0]    prev_low;
+                    logic           quo;
+                    prev_low    = (curr_state == SCR1_IALU_FSM_IDLE)
+                                    ? (ialu_op1[30:0])
+                                    : (res32_3_reg[30:0]);
+                    quo         = ~((~div_cmd[0] & ialu_op1[31]) ^ (sum2_res[32]))
+                                  | ((~div_cmd[0] & ialu_op1[31]) & (~|{sum2_res, prev_low}));
+
+                    {res32_1_c, res32_1}    = sum2_res;                 // High part of extended dividend (reminder)
+                    res32_3     = (curr_state == SCR1_IALU_FSM_IDLE)
+                                    ? ({ialu_op1[30:0], 1'b0})
+                                    : ({res32_3_reg[30:0], 1'b0});      // Low part of extended dividend (reminder)
+                    res32_2     = (curr_state == SCR1_IALU_FSM_IDLE)
+                                    ? ({'0, quo})
+                                    : ({res32_2_reg[32-2:0], quo});     // Quotient
+
+                end
+                default : begin end
+            endcase
+        end
+`ifndef SCR1_FAST_MUL
+        SCR1_IALU_MDU_MUL : begin
+            {res32_1, res32_2}  = (curr_state == SCR1_IALU_FSM_IDLE)
+                                    ? ({sum2_res, ialu_op2[31:SCR1_MUL_WIDTH]})
+                                    : ({sum2_res, res32_2_reg[31:SCR1_MUL_WIDTH]});
+        end
+`endif // ~SCR1_FAST_MUL
+        default : begin end
+    endcase
+end
+`endif // SCR1_RVM_EXT
+
+
+`ifdef SCR1_RVM_EXT
+//-------------------------------------------------------------------------------
+// FSM control signals
+//-------------------------------------------------------------------------------
+always_comb begin
+    iter_req  = 1'b0;
+    iter_rdy  = 1'b0;
+    corr_req = (mdu_cmd == SCR1_IALU_MDU_DIV) & ((div_cmd == 2'b00) & (ialu_op1[31] ^ ialu_op2[31]) |
+              (div_cmd[1] & |res32_1 & ((~div_cmd[0] & ialu_op1[31]) ^ res32_1_c)));
+ `ifdef SCR1_FAST_MUL
+    if (mdu_cmd == SCR1_IALU_MDU_DIV) begin
+        iter_req  = |ialu_op1 & |ialu_op2 & (curr_state == SCR1_IALU_FSM_IDLE);
+        iter_rdy  = sum1_flags.c & (curr_state == SCR1_IALU_FSM_ITER);
+    end
+ `else // ~SCR1_FAST_MUL
+    if (mdu_cmd != SCR1_IALU_MDU_NONE) begin
+        iter_req  = |ialu_op1 & |ialu_op2 & (curr_state == SCR1_IALU_FSM_IDLE);
+        iter_rdy  = sum1_flags.c & (curr_state == SCR1_IALU_FSM_ITER);
+    end
+ `endif // ~SCR1_FAST_MUL
+end
+`endif // SCR1_RVM_EXT
+
+
+//-------------------------------------------------------------------------------
+// Operation result forming
+//-------------------------------------------------------------------------------
+always_comb begin
+    ialu_res    = '0;
+    ialu_cmp    = 1'b0;
+    shft_cmd    = 2'b0;
+`ifdef SCR1_RVM_EXT
+    mdu_cmd     = SCR1_IALU_MDU_NONE;
+    mul_cmd     = {((ialu_cmd == SCR1_IALU_CMD_MULHU) | (ialu_cmd == SCR1_IALU_CMD_MULHSU)),
+                   ((ialu_cmd == SCR1_IALU_CMD_MULHU) | (ialu_cmd == SCR1_IALU_CMD_MULH))};
+    div_cmd     = {((ialu_cmd == SCR1_IALU_CMD_REM)   | (ialu_cmd == SCR1_IALU_CMD_REMU)),
+                   ((ialu_cmd == SCR1_IALU_CMD_REMU)  | (ialu_cmd == SCR1_IALU_CMD_DIVU))};
+    ialu_rdy    = 1'b1;
+`endif // SCR1_RVM_EXT
+
+    case (ialu_cmd)
+        SCR1_IALU_CMD_AND : begin
+            ialu_res    = ialu_op1 & ialu_op2;
+        end
+        SCR1_IALU_CMD_OR : begin
+            ialu_res    = ialu_op1 | ialu_op2;
+        end
+        SCR1_IALU_CMD_XOR : begin
+            ialu_res    = ialu_op1 ^ ialu_op2;
+        end
+        SCR1_IALU_CMD_ADD : begin
+            ialu_res    = sum1_res[`SCR1_XLEN-1:0];
+        end
+        SCR1_IALU_CMD_SUB : begin
+            ialu_res    = sum1_res[`SCR1_XLEN-1:0];
+        end
+        SCR1_IALU_CMD_SUB_LT : begin
+            ialu_res    = `SCR1_XLEN'(sum1_flags.s ^ sum1_flags.o);
+            ialu_cmp    = sum1_flags.s ^ sum1_flags.o;
+        end
+        SCR1_IALU_CMD_SUB_LTU : begin
+            ialu_res    = `SCR1_XLEN'(sum1_flags.c);
+            ialu_cmp    = sum1_flags.c;
+        end
+        SCR1_IALU_CMD_SUB_EQ : begin
+            ialu_res    = `SCR1_XLEN'(sum1_flags.z);
+            ialu_cmp    = sum1_flags.z;
+        end
+        SCR1_IALU_CMD_SUB_NE : begin
+            ialu_res    = `SCR1_XLEN'(~sum1_flags.z);
+            ialu_cmp    = ~sum1_flags.z;
+        end
+        SCR1_IALU_CMD_SUB_GE : begin
+            ialu_res    = `SCR1_XLEN'(~(sum1_flags.s ^ sum1_flags.o));
+            ialu_cmp    = ~(sum1_flags.s ^ sum1_flags.o);
+        end
+        SCR1_IALU_CMD_SUB_GEU : begin
+            ialu_res    = `SCR1_XLEN'(~sum1_flags.c);
+            ialu_cmp    = ~sum1_flags.c;
+        end
+        SCR1_IALU_CMD_SLL,
+        SCR1_IALU_CMD_SRL,
+        SCR1_IALU_CMD_SRA: begin
+            shft_cmd    = {(ialu_cmd != SCR1_IALU_CMD_SLL), (ialu_cmd == SCR1_IALU_CMD_SRA)};
+            ialu_res    = shft_res;
+        end
+`ifdef SCR1_RVM_EXT
+        SCR1_IALU_CMD_MUL,
+        SCR1_IALU_CMD_MULHU,
+        SCR1_IALU_CMD_MULHSU,
+        SCR1_IALU_CMD_MULH : begin
+            mdu_cmd     = SCR1_IALU_MDU_MUL;
+ `ifdef SCR1_FAST_MUL
+            ialu_res     = (|mul_cmd) ? mul_res[(32*2)-1:32] : mul_res[31:0];
+ `else // ~SCR1_FAST_MUL
+            case (curr_state)
+                SCR1_IALU_FSM_IDLE : begin
+                    ialu_res     = '0;
+                    ialu_rdy     = ~iter_req;
+                end
+                SCR1_IALU_FSM_ITER : begin
+                    ialu_res     = (|mul_cmd) ? res32_1 : res32_2;
+                    ialu_rdy     = iter_rdy;
+                end
+            endcase
+ `endif // ~SCR1_FAST_MUL
+        end
+        SCR1_IALU_CMD_DIV,
+        SCR1_IALU_CMD_DIVU,
+        SCR1_IALU_CMD_REM,
+        SCR1_IALU_CMD_REMU : begin
+            mdu_cmd     = SCR1_IALU_MDU_DIV;
+            case (curr_state)
+                SCR1_IALU_FSM_IDLE : begin
+                    ialu_res     = (|ialu_op2 | div_cmd[1]) ? ialu_op1 : '1;
+                    ialu_rdy     = ~iter_req;
+                end
+                SCR1_IALU_FSM_ITER : begin
+                    ialu_res     = (div_cmd[1]) ? res32_1 : res32_2;
+                    ialu_rdy     = iter_rdy & ~corr_req;
+                end
+                SCR1_IALU_FSM_CORR : begin
+                    ialu_res     = (div_cmd[1]) ? sum2_res[31:0] : sum1_res[31:0];
+                    ialu_rdy     = 1'b1;
+                end
+            endcase
+        end
+`endif // SCR1_RVM_EXT
+        default : begin end
+    endcase
+end
+
+
+`ifdef SCR1_RVM_EXT
+//-------------------------------------------------------------------------------
+// Save iteration state
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk) begin
+    if (ialu_vd & ~ialu_rdy) begin
+        case (mdu_cmd)
+            SCR1_IALU_MDU_DIV : begin
+                cnt_res_reg     <= cnt_res;                     // Counter
+                res32_1_c_reg   <= res32_1_c;                   // Iteration reminder carry
+                res32_1_reg     <= res32_1;                     // Iteration reminder
+                res32_2_reg     <= res32_2;                     // Iteration quotient
+                res32_3_reg     <= res32_3;                     // Iteration reminder (low)
+            end
+ `ifndef SCR1_FAST_MUL
+            SCR1_IALU_MDU_MUL : begin
+                cnt_res_reg     <= cnt_res;                     // Counter
+                res32_2_reg     <= res32_2;                     // Multiplication low part of result / operand 2
+                res32_1_reg     <= res32_1;                     // Multiplication high part of result
+            end
+ `endif // SCR1_FAST_MUL
+            default : begin end
+        endcase
+    end
+end
+`endif // SCR1_RVM_EXT
+
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+`ifdef SCR1_RVM_EXT
+
+// X checks
+
+SCR1_SVA_IALU_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown({ialu_vd, curr_state})
+    ) else $error("IALU Error: unknown values");
+
+SCR1_SVA_IALU_XCHECK_QUEUE : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ialu_vd |-> !$isunknown({ialu_op1, ialu_op2, ialu_cmd})
+    ) else $error("IALU Error: unknown values in queue");
+
+// Behavior checks
+
+SCR1_SVA_IALU_ILL_STATE : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    $onehot0({~ialu_vd, (curr_state == SCR1_IALU_FSM_ITER), (curr_state == SCR1_IALU_FSM_CORR)})
+    ) else $error("IALU Error: illegal state");
+
+SCR1_SVA_IALU_JUMP_FROM_IDLE : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ((curr_state == SCR1_IALU_FSM_IDLE) & (~ialu_vd | ~iter_req))
+    |=> (curr_state == SCR1_IALU_FSM_IDLE)
+    ) else $error("EXU Error: illegal jump from IDLE state");
+
+SCR1_SVA_IALU_IDLE_TO_ITER : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ((curr_state == SCR1_IALU_FSM_IDLE) & ialu_vd & iter_req)
+    |=> (curr_state == SCR1_IALU_FSM_ITER)
+    ) else $error("EXU Error: illegal change state form IDLE to ITER");
+
+SCR1_SVA_IALU_JUMP_FROM_ITER : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ((curr_state == SCR1_IALU_FSM_ITER) & ~iter_rdy)
+    |=> (curr_state == SCR1_IALU_FSM_ITER)
+    ) else $error("EXU Error: illegal jump from ITER state");
+
+SCR1_SVA_IALU_ITER_TO_IDLE : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ((curr_state == SCR1_IALU_FSM_ITER) & iter_rdy & ~corr_req)
+    |=> (curr_state == SCR1_IALU_FSM_IDLE)
+    ) else $error("EXU Error: illegal state change ITER to IDLE");
+
+SCR1_SVA_IALU_ITER_TO_CORR : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ((curr_state == SCR1_IALU_FSM_ITER) & iter_rdy & corr_req)
+    |=> ((curr_state == SCR1_IALU_FSM_CORR) ##1 (curr_state == SCR1_IALU_FSM_IDLE))
+    ) else $error("EXU Error: illegal state change ITER to CORR");
+
+`endif // SCR1_RVM_EXT
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_ialu
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_idu.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_idu.sv
new file mode 100644
index 0000000..eb45286
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_idu.sv
@@ -0,0 +1,864 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_pipe_idu.sv>
+/// @brief      Instruction Decoder Unit (IDU)
+///
+
+`include "scr1_memif.svh"
+`include "scr1_arch_types.svh"
+`include "scr1_riscv_isa_decoding.svh"
+`include "scr1_arch_description.svh"
+
+module scr1_pipe_idu
+(
+`ifdef SCR1_SIM_ENV
+    input   logic                           rst_n,
+    input   logic                           clk,
+`endif // SCR1_SIM_ENV
+
+    // IFU <-> IDU interface
+    output  logic                           idu2ifu_rdy,            // IDU ready for new data
+    input   logic [`SCR1_IMEM_DWIDTH-1:0]   ifu2idu_instr,          // IFU instruction
+    input   logic                           ifu2idu_imem_err,       // Instruction access fault exception
+    input   logic                           ifu2idu_err_rvi_hi,     // 1 - imem fault when trying to fetch second half of an unaligned RVI instruction
+    input   logic                           ifu2idu_vd,             // IFU request
+
+    // IDU <-> EXU interface
+    output  logic                           idu2exu_req,            // IDU request
+    output  type_scr1_exu_cmd_s             idu2exu_cmd,            // IDU command
+    output  logic                           idu2exu_use_rs1,        // Instruction uses rs1
+    output  logic                           idu2exu_use_rs2,        // Instruction uses rs2
+    output  logic                           idu2exu_use_rd,         // Instruction uses rd
+    output  logic                           idu2exu_use_imm,        // Instruction uses immediate
+    input   logic                           exu2idu_rdy             // EXU ready for new data
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters declaration
+//-------------------------------------------------------------------------------
+localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_ZERO_ADDR   = 5'd0;
+localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_RA_ADDR     = 5'd1;
+localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_SP_ADDR     = 5'd2;
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+
+logic [`SCR1_IMEM_DWIDTH-1:0]       instr;
+type_scr1_instr_type_e              instr_type;
+type_scr1_rvi_opcode_e              rvi_opcode;
+logic                               rvi_illegal;
+logic [2:0]                         funct3;
+logic [6:0]                         funct7;
+logic [11:0]                        funct12;
+logic [4:0]                         shamt;
+`ifdef SCR1_RVC_EXT
+logic                               rvc_illegal;
+`endif  // SCR1_RVC_EXT
+`ifdef SCR1_RVE_EXT
+logic                               rve_illegal;
+`endif  // SCR1_RVE_EXT
+
+//-------------------------------------------------------------------------------
+// Decode
+//-------------------------------------------------------------------------------
+
+assign idu2ifu_rdy  = exu2idu_rdy;
+assign idu2exu_req  = ifu2idu_vd;
+assign instr        = ifu2idu_instr;
+
+// RVI / RVC
+assign instr_type   = type_scr1_instr_type_e'(instr[1:0]);
+
+// RVI / RVC fields
+assign rvi_opcode   = type_scr1_rvi_opcode_e'(instr[6:2]);                          // RVI
+assign funct3       = (instr_type == SCR1_INSTR_RVI) ? instr[14:12] : instr[15:13]; // RVI / RVC
+assign funct7       = instr[31:25];                                                 // RVI
+assign funct12      = instr[31:20];                                                 // RVI (SYSTEM)
+assign shamt        = instr[24:20];                                                 // RVI
+
+// RV32I(MC) decode
+always_comb begin
+    // Defaults
+    idu2exu_cmd.instr_rvc   = 1'b0;
+    idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+    idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_NONE;
+    idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_PC_IMM;
+    idu2exu_cmd.lsu_cmd     = SCR1_LSU_CMD_NONE;
+    idu2exu_cmd.csr_op      = SCR1_CSR_OP_REG;
+    idu2exu_cmd.csr_cmd     = SCR1_CSR_CMD_NONE;
+    idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_NONE;
+    idu2exu_cmd.jump_req    = 1'b0;
+    idu2exu_cmd.branch_req  = 1'b0;
+    idu2exu_cmd.mret_req    = 1'b0;
+    idu2exu_cmd.fencei_req  = 1'b0;
+    idu2exu_cmd.wfi_req     = 1'b0;
+    idu2exu_cmd.rs1_addr    = '0;
+    idu2exu_cmd.rs2_addr    = '0;
+    idu2exu_cmd.rd_addr     = '0;
+    idu2exu_cmd.imm         = '0;
+    idu2exu_cmd.exc_req     = 1'b0;
+    idu2exu_cmd.exc_code    = SCR1_EXC_CODE_INSTR_MISALIGN;
+    // Clock gating
+    idu2exu_use_rs1         = 1'b0;
+    idu2exu_use_rs2         = 1'b0;
+    idu2exu_use_rd          = 1'b0;
+    idu2exu_use_imm         = 1'b0;
+
+    rvi_illegal             = 1'b0;
+`ifdef SCR1_RVE_EXT
+    rve_illegal             = 1'b0;
+`endif  // SCR1_RVE_EXT
+`ifdef SCR1_RVC_EXT
+    rvc_illegal             = 1'b0;
+`endif  // SCR1_RVC_EXT
+
+    // Check for IMEM access fault
+    if (ifu2idu_imem_err) begin
+        idu2exu_cmd.exc_req     = 1'b1;
+        idu2exu_cmd.exc_code    = SCR1_EXC_CODE_INSTR_ACCESS_FAULT;
+        idu2exu_cmd.instr_rvc   = ifu2idu_err_rvi_hi;
+    end else begin  // no imem fault
+        case (instr_type)
+            SCR1_INSTR_RVI  : begin
+                idu2exu_cmd.rs1_addr    = instr[19:15];
+                idu2exu_cmd.rs2_addr    = instr[24:20];
+                idu2exu_cmd.rd_addr     = instr[11:7];
+                case (rvi_opcode)
+                    SCR1_OPCODE_AUIPC           : begin
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_PC_IMM;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_SUM2;
+                        idu2exu_cmd.imm         = {instr[31:12], 12'b0};
+`ifdef SCR1_RVE_EXT
+                        if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_AUIPC
+
+                    SCR1_OPCODE_LUI             : begin
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IMM;
+                        idu2exu_cmd.imm         = {instr[31:12], 12'b0};
+`ifdef SCR1_RVE_EXT
+                        if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_LUI
+
+                    SCR1_OPCODE_JAL             : begin
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_PC_IMM;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_INC_PC;
+                        idu2exu_cmd.jump_req    = 1'b1;
+                        idu2exu_cmd.imm         = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
+`ifdef SCR1_RVE_EXT
+                        if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_JAL
+
+                    SCR1_OPCODE_LOAD            : begin
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_REG_IMM;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_LSU;
+                        idu2exu_cmd.imm         = {{21{instr[31]}}, instr[30:20]};
+                        case (funct3)
+                            3'b000  : idu2exu_cmd.lsu_cmd = SCR1_LSU_CMD_LB;
+                            3'b001  : idu2exu_cmd.lsu_cmd = SCR1_LSU_CMD_LH;
+                            3'b010  : idu2exu_cmd.lsu_cmd = SCR1_LSU_CMD_LW;
+                            3'b100  : idu2exu_cmd.lsu_cmd = SCR1_LSU_CMD_LBU;
+                            3'b101  : idu2exu_cmd.lsu_cmd = SCR1_LSU_CMD_LHU;
+                            default : rvi_illegal = 1'b1;
+                        endcase // funct3
+`ifdef SCR1_RVE_EXT
+                        if (instr[11] | instr[19])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_LOAD
+
+                    SCR1_OPCODE_STORE           : begin
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rs2         = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_REG_IMM;
+                        idu2exu_cmd.imm         = {{21{instr[31]}}, instr[30:25], instr[11:7]};
+                        case (funct3)
+                            3'b000  : idu2exu_cmd.lsu_cmd = SCR1_LSU_CMD_SB;
+                            3'b001  : idu2exu_cmd.lsu_cmd = SCR1_LSU_CMD_SH;
+                            3'b010  : idu2exu_cmd.lsu_cmd = SCR1_LSU_CMD_SW;
+                            default : rvi_illegal = 1'b1;
+                        endcase // funct3
+`ifdef SCR1_RVE_EXT
+                        if (instr[19] | instr[24])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_STORE
+
+                    SCR1_OPCODE_OP              : begin
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rs2         = 1'b1;
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                        case (funct7)
+                            7'b0000000 : begin
+                                case (funct3)
+                                    3'b000  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_ADD;
+                                    3'b001  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_SLL;
+                                    3'b010  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_SUB_LT;
+                                    3'b011  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_SUB_LTU;
+                                    3'b100  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_XOR;
+                                    3'b101  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_SRL;
+                                    3'b110  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_OR;
+                                    3'b111  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_AND;
+                                endcase // funct3
+                            end // 7'b0000000
+
+                            7'b0100000 : begin
+                                case (funct3)
+                                    3'b000  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_SUB;
+                                    3'b101  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_SRA;
+                                    default : rvi_illegal = 1'b1;
+                                endcase // funct3
+                            end // 7'b0100000
+`ifdef SCR1_RVM_EXT
+                            7'b0000001 : begin
+                                case (funct3)
+                                    3'b000  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_MUL;
+                                    3'b001  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_MULH;
+                                    3'b010  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_MULHSU;
+                                    3'b011  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_MULHU;
+                                    3'b100  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_DIV;
+                                    3'b101  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_DIVU;
+                                    3'b110  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_REM;
+                                    3'b111  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_REMU;
+                                endcase // funct3
+                            end // 7'b0000001
+`endif  // SCR1_RVM_EXT
+                            default : rvi_illegal = 1'b1;
+                        endcase // funct7
+`ifdef SCR1_RVE_EXT
+                        if (instr[11] | instr[19] | instr[24])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_OP
+
+                    SCR1_OPCODE_OP_IMM          : begin
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.imm         = {{21{instr[31]}}, instr[30:20]};
+                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_IMM;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                        case (funct3)
+                            3'b000  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_ADD;        // ADDI
+                            3'b010  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_SUB_LT;     // SLTI
+                            3'b011  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_SUB_LTU;    // SLTIU
+                            3'b100  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_XOR;        // XORI
+                            3'b110  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_OR;         // ORI
+                            3'b111  : idu2exu_cmd.ialu_cmd  = SCR1_IALU_CMD_AND;        // ANDI
+                            3'b001  : begin
+                                case (funct7)
+                                    7'b0000000  : begin
+                                        // SLLI
+                                        idu2exu_cmd.imm         = `SCR1_XLEN'(shamt);   // zero-extend
+                                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SLL;
+                                    end
+                                    default     : rvi_illegal   = 1'b1;
+                                endcase // funct7
+                            end
+                            3'b101  : begin
+                                case (funct7)
+                                    7'b0000000  : begin
+                                        // SRLI
+                                        idu2exu_cmd.imm         = `SCR1_XLEN'(shamt);   // zero-extend
+                                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SRL;
+                                    end
+                                    7'b0100000  : begin
+                                        // SRAI
+                                        idu2exu_cmd.imm         = `SCR1_XLEN'(shamt);   // zero-extend
+                                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SRA;
+                                    end
+                                    default     : rvi_illegal   = 1'b1;
+                                endcase // funct7
+                            end
+                        endcase // funct3
+`ifdef SCR1_RVE_EXT
+                        if (instr[11] | instr[19])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_OP_IMM
+
+                    SCR1_OPCODE_MISC_MEM    : begin
+                        case (funct3)
+                            3'b000  : begin
+                                if (~|{instr[31:28], instr[19:15], instr[11:7]}) begin
+                                    // FENCE = NOP
+                                end
+                                else rvi_illegal = 1'b1;
+                            end
+                            3'b001  : begin
+                                if (~|{instr[31:15], instr[11:7]}) begin
+                                    // FENCE.I
+                                    idu2exu_cmd.fencei_req    = 1'b1;
+                                end
+                                else rvi_illegal = 1'b1;
+                            end
+                            default : rvi_illegal = 1'b1;
+                        endcase // funct3
+                    end // SCR1_OPCODE_MISC_MEM
+
+                    SCR1_OPCODE_BRANCH          : begin
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rs2         = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.imm         = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
+                        idu2exu_cmd.branch_req  = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_PC_IMM;
+                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                        case (funct3)
+                            3'b000  : idu2exu_cmd.ialu_cmd = SCR1_IALU_CMD_SUB_EQ;
+                            3'b001  : idu2exu_cmd.ialu_cmd = SCR1_IALU_CMD_SUB_NE;
+                            3'b100  : idu2exu_cmd.ialu_cmd = SCR1_IALU_CMD_SUB_LT;
+                            3'b101  : idu2exu_cmd.ialu_cmd = SCR1_IALU_CMD_SUB_GE;
+                            3'b110  : idu2exu_cmd.ialu_cmd = SCR1_IALU_CMD_SUB_LTU;
+                            3'b111  : idu2exu_cmd.ialu_cmd = SCR1_IALU_CMD_SUB_GEU;
+                            default : rvi_illegal = 1'b1;
+                        endcase // funct3
+`ifdef SCR1_RVE_EXT
+                        if (instr[19] | instr[24])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_BRANCH
+
+                    SCR1_OPCODE_JALR        : begin
+                        idu2exu_use_rs1     = 1'b1;
+                        idu2exu_use_rd      = 1'b1;
+                        idu2exu_use_imm     = 1'b1;
+                        case (funct3)
+                            3'b000  : begin
+                                // JALR
+                                idu2exu_cmd.sum2_op   = SCR1_SUM2_OP_REG_IMM;
+                                idu2exu_cmd.rd_wb_sel = SCR1_RD_WB_INC_PC;
+                                idu2exu_cmd.jump_req  = 1'b1;
+                                idu2exu_cmd.imm       = {{21{instr[31]}}, instr[30:20]};
+                            end
+                            default : rvi_illegal = 1'b1;
+                        endcase
+`ifdef SCR1_RVE_EXT
+                        if (instr[11] | instr[19])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end // SCR1_OPCODE_JALR
+
+                    SCR1_OPCODE_SYSTEM      : begin
+                        idu2exu_use_rd      = 1'b1;
+                        idu2exu_use_imm     = 1'b1;
+                        idu2exu_cmd.imm     = `SCR1_XLEN'({funct3, instr[31:20]});      // {funct3, CSR address}
+                        case (funct3)
+                            3'b000  : begin
+                                idu2exu_use_rd    = 1'b0;
+                                idu2exu_use_imm   = 1'b0;
+                                case ({instr[19:15], instr[11:7]})
+                                    10'd0 : begin
+                                        case (funct12)
+                                            12'h000 : begin
+                                                // ECALL
+                                                idu2exu_cmd.exc_req     = 1'b1;
+                                                idu2exu_cmd.exc_code    = SCR1_EXC_CODE_ECALL_M;
+                                            end
+                                            12'h001 : begin
+                                                // EBREAK
+                                                idu2exu_cmd.exc_req     = 1'b1;
+                                                idu2exu_cmd.exc_code    = SCR1_EXC_CODE_BREAKPOINT;
+                                            end
+                                            12'h302 : begin
+                                                // MRET
+                                                idu2exu_cmd.mret_req    = 1'b1;
+                                            end
+                                            12'h105 : begin
+                                                // WFI
+                                                idu2exu_cmd.wfi_req     = 1'b1;
+                                            end
+                                            default : rvi_illegal = 1'b1;
+                                        endcase // funct12
+                                    end
+                                    default : rvi_illegal = 1'b1;
+                                endcase // {instr[19:15], instr[11:7]}
+                            end
+                            3'b001  : begin
+                                // CSRRW
+                                idu2exu_use_rs1             = 1'b1;
+                                idu2exu_cmd.rd_wb_sel       = SCR1_RD_WB_CSR;
+                                idu2exu_cmd.csr_cmd         = SCR1_CSR_CMD_WRITE;
+                                idu2exu_cmd.csr_op          = SCR1_CSR_OP_REG;
+`ifdef SCR1_RVE_EXT
+                                if (instr[11] | instr[19])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end
+                            3'b010  : begin
+                                // CSRRS
+                                idu2exu_use_rs1             = 1'b1;
+                                idu2exu_cmd.rd_wb_sel       = SCR1_RD_WB_CSR;
+                                idu2exu_cmd.csr_cmd         = SCR1_CSR_CMD_SET;
+                                idu2exu_cmd.csr_op          = SCR1_CSR_OP_REG;
+`ifdef SCR1_RVE_EXT
+                                if (instr[11] | instr[19])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end
+                            3'b011  : begin
+                                // CSRRC
+                                idu2exu_use_rs1             = 1'b1;
+                                idu2exu_cmd.rd_wb_sel       = SCR1_RD_WB_CSR;
+                                idu2exu_cmd.csr_cmd         = SCR1_CSR_CMD_CLEAR;
+                                idu2exu_cmd.csr_op          = SCR1_CSR_OP_REG;
+`ifdef SCR1_RVE_EXT
+                                if (instr[11] | instr[19])  rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end
+                            3'b101  : begin
+                                // CSRRWI
+                                idu2exu_use_rs1             = 1'b1;             // zimm
+                                idu2exu_cmd.rd_wb_sel       = SCR1_RD_WB_CSR;
+                                idu2exu_cmd.csr_cmd         = SCR1_CSR_CMD_WRITE;
+                                idu2exu_cmd.csr_op          = SCR1_CSR_OP_IMM;
+`ifdef SCR1_RVE_EXT
+                                if (instr[11])              rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end
+                            3'b110  : begin
+                                // CSRRSI
+                                idu2exu_use_rs1             = 1'b1;             // zimm
+                                idu2exu_cmd.rd_wb_sel       = SCR1_RD_WB_CSR;
+                                idu2exu_cmd.csr_cmd         = SCR1_CSR_CMD_SET;
+                                idu2exu_cmd.csr_op          = SCR1_CSR_OP_IMM;
+`ifdef SCR1_RVE_EXT
+                                if (instr[11])              rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end
+                            3'b111  : begin
+                                // CSRRCI
+                                idu2exu_use_rs1             = 1'b1;             // zimm
+                                idu2exu_cmd.rd_wb_sel       = SCR1_RD_WB_CSR;
+                                idu2exu_cmd.csr_cmd         = SCR1_CSR_CMD_CLEAR;
+                                idu2exu_cmd.csr_op          = SCR1_CSR_OP_IMM;
+`ifdef SCR1_RVE_EXT
+                                if (instr[11])              rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end
+                            default : rvi_illegal = 1'b1;
+                        endcase // funct3
+                    end // SCR1_OPCODE_SYSTEM
+
+                    default : begin
+                        rvi_illegal = 1'b1;
+                    end
+                endcase // rvi_opcode
+            end // SCR1_INSTR_RVI
+
+`ifdef SCR1_RVC_EXT
+
+            // Quadrant 0
+            SCR1_INSTR_RVC0 : begin
+                idu2exu_cmd.instr_rvc   = 1'b1;
+                idu2exu_use_rs1         = 1'b1;
+                idu2exu_use_imm         = 1'b1;
+                case (funct3)
+                    3'b000  : begin
+                        if (~|instr[12:5])      rvc_illegal = 1'b1;
+                        // C.ADDI4SPN
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_ADD;
+                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_IMM;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                        idu2exu_cmd.rs1_addr    = SCR1_MPRF_SP_ADDR;
+                        idu2exu_cmd.rd_addr     = {2'b01, instr[4:2]};
+                        idu2exu_cmd.imm         = {22'd0, instr[10:7], instr[12:11], instr[5], instr[6], 2'b00};
+                    end
+                    3'b010  : begin
+                        // C.LW
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_REG_IMM;
+                        idu2exu_cmd.lsu_cmd     = SCR1_LSU_CMD_LW;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_LSU;
+                        idu2exu_cmd.rs1_addr    = {2'b01, instr[9:7]};
+                        idu2exu_cmd.rd_addr     = {2'b01, instr[4:2]};
+                        idu2exu_cmd.imm         = {25'd0, instr[5], instr[12:10], instr[6], 2'b00};
+                    end
+                    3'b110  : begin
+                        // C.SW
+                        idu2exu_use_rs2         = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_REG_IMM;
+                        idu2exu_cmd.lsu_cmd     = SCR1_LSU_CMD_SW;
+                        idu2exu_cmd.rs1_addr    = {2'b01, instr[9:7]};
+                        idu2exu_cmd.rs2_addr    = {2'b01, instr[4:2]};
+                        idu2exu_cmd.imm         = {25'd0, instr[5], instr[12:10], instr[6], 2'b00};
+                    end
+                    default : begin
+                        rvc_illegal = 1'b1;
+                    end
+                endcase // funct3
+            end // Quadrant 0
+
+            // Quadrant 1
+            SCR1_INSTR_RVC1 : begin
+                idu2exu_cmd.instr_rvc   = 1'b1;
+                idu2exu_use_rd          = 1'b1;
+                idu2exu_use_imm         = 1'b1;
+                case (funct3)
+                    3'b000  : begin
+                        // C.ADDI / C.NOP
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_ADD;
+                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_IMM;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                        idu2exu_cmd.rs1_addr    = instr[11:7];
+                        idu2exu_cmd.rd_addr     = instr[11:7];
+                        idu2exu_cmd.imm         = {{27{instr[12]}}, instr[6:2]};
+`ifdef SCR1_RVE_EXT
+                        if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end
+                    3'b001  : begin
+                        // C.JAL
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_PC_IMM;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_INC_PC;
+                        idu2exu_cmd.jump_req    = 1'b1;
+                        idu2exu_cmd.rd_addr     = SCR1_MPRF_RA_ADDR;
+                        idu2exu_cmd.imm         = {{21{instr[12]}}, instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
+                    end
+                    3'b010  : begin
+                        // C.LI
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IMM;
+                        idu2exu_cmd.rd_addr     = instr[11:7];
+                        idu2exu_cmd.imm         = {{27{instr[12]}}, instr[6:2]};
+`ifdef SCR1_RVE_EXT
+                        if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end
+                    3'b011  : begin
+                        if (~|{instr[12], instr[6:2]}) rvc_illegal = 1'b1;
+                        if (instr[11:7] == SCR1_MPRF_SP_ADDR) begin
+                            // C.ADDI16SP
+                            idu2exu_use_rs1         = 1'b1;
+                            idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_ADD;
+                            idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_IMM;
+                            idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                            idu2exu_cmd.rs1_addr    = SCR1_MPRF_SP_ADDR;
+                            idu2exu_cmd.rd_addr     = SCR1_MPRF_SP_ADDR;
+                            idu2exu_cmd.imm         = {{23{instr[12]}}, instr[4:3], instr[5], instr[2], instr[6], 4'd0};
+                        end else begin
+                            // C.LUI
+                            idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IMM;
+                            idu2exu_cmd.rd_addr     = instr[11:7];
+                            idu2exu_cmd.imm         = {{15{instr[12]}}, instr[6:2], 12'd0};
+`ifdef SCR1_RVE_EXT
+                            if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                        end
+                    end
+                    3'b100  : begin
+                        idu2exu_cmd.rs1_addr    = {2'b01, instr[9:7]};
+                        idu2exu_cmd.rd_addr     = {2'b01, instr[9:7]};
+                        idu2exu_cmd.rs2_addr    = {2'b01, instr[4:2]};
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rd          = 1'b1;
+                        case (instr[11:10])
+                            2'b00   : begin
+                                if (instr[12])          rvc_illegal = 1'b1;
+                                // C.SRLI
+                                idu2exu_use_imm         = 1'b1;
+                                idu2exu_cmd.imm         = {27'd0, instr[6:2]};
+                                idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SRL;
+                                idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_IMM;
+                                idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                            end
+                            2'b01   : begin
+                                if (instr[12])          rvc_illegal = 1'b1;
+                                // C.SRAI
+                                idu2exu_use_imm         = 1'b1;
+                                idu2exu_cmd.imm         = {27'd0, instr[6:2]};
+                                idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SRA;
+                                idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_IMM;
+                                idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                            end
+                            2'b10   : begin
+                                // C.ANDI
+                                idu2exu_use_imm         = 1'b1;
+                                idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_AND;
+                                idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_IMM;
+                                idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                                idu2exu_cmd.imm         = {{27{instr[12]}}, instr[6:2]};
+                            end
+                            2'b11   : begin
+                                idu2exu_use_rs2         = 1'b1;
+                                case ({instr[12], instr[6:5]})
+                                    3'b000  : begin
+                                        // C.SUB
+                                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SUB;
+                                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                                    end
+                                    3'b001  : begin
+                                        // C.XOR
+                                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_XOR;
+                                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                                    end
+                                    3'b010  : begin
+                                        // C.OR
+                                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_OR;
+                                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                                    end
+                                    3'b011  : begin
+                                        // C.AND
+                                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_AND;
+                                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                                    end
+                                    default : begin
+                                        rvc_illegal = 1'b1;
+                                    end
+                                endcase // {instr[12], instr[6:5]}
+                            end
+                        endcase // instr[11:10]
+                    end // funct3 == 3'b100
+                    3'b101  : begin
+                        // C.J
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_PC_IMM;
+                        idu2exu_cmd.jump_req    = 1'b1;
+                        idu2exu_cmd.imm         = {{21{instr[12]}}, instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
+                    end
+                    3'b110  : begin
+                        // C.BEQZ
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rs2         = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SUB_EQ;
+                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_PC_IMM;
+                        idu2exu_cmd.branch_req  = 1'b1;
+                        idu2exu_cmd.rs1_addr    = {2'b01, instr[9:7]};
+                        idu2exu_cmd.rs2_addr    = SCR1_MPRF_ZERO_ADDR;
+                        idu2exu_cmd.imm         = {{24{instr[12]}}, instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
+                    end
+                    3'b111  : begin
+                        // C.BNEZ
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rs2         = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SUB_NE;
+                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_PC_IMM;
+                        idu2exu_cmd.branch_req  = 1'b1;
+                        idu2exu_cmd.rs1_addr    = {2'b01, instr[9:7]};
+                        idu2exu_cmd.rs2_addr    = SCR1_MPRF_ZERO_ADDR;
+                        idu2exu_cmd.imm         = {{24{instr[12]}}, instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
+                    end
+                endcase // funct3
+            end // Quadrant 1
+
+            // Quadrant 2
+            SCR1_INSTR_RVC2 : begin
+                idu2exu_cmd.instr_rvc   = 1'b1;
+                idu2exu_use_rs1         = 1'b1;
+                case (funct3)
+                    3'b000  : begin
+                        if (instr[12])          rvc_illegal = 1'b1;
+                        // C.SLLI
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.rs1_addr    = instr[11:7];
+                        idu2exu_cmd.rd_addr     = instr[11:7];
+                        idu2exu_cmd.imm         = {27'd0, instr[6:2]};
+                        idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_SLL;
+                        idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_IMM;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+`ifdef SCR1_RVE_EXT
+                        if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end
+                    3'b010  : begin
+                        if (~|instr[11:7])      rvc_illegal = 1'b1;
+                        // C.LWSP
+                        idu2exu_use_rd          = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_REG_IMM;
+                        idu2exu_cmd.lsu_cmd     = SCR1_LSU_CMD_LW;
+                        idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_LSU;
+                        idu2exu_cmd.rs1_addr    = SCR1_MPRF_SP_ADDR;
+                        idu2exu_cmd.rd_addr     = instr[11:7];
+                        idu2exu_cmd.imm         = {24'd0, instr[3:2], instr[12], instr[6:4], 2'b00};
+`ifdef SCR1_RVE_EXT
+                        if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end
+                    3'b100  : begin
+                        if (~instr[12]) begin
+                            if (|instr[6:2]) begin
+                                // C.MV
+                                idu2exu_use_rs2         = 1'b1;
+                                idu2exu_use_rd          = 1'b1;
+                                idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_ADD;
+                                idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                                idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                                idu2exu_cmd.rs1_addr    = SCR1_MPRF_ZERO_ADDR;
+                                idu2exu_cmd.rs2_addr    = instr[6:2];
+                                idu2exu_cmd.rd_addr     = instr[11:7];
+`ifdef SCR1_RVE_EXT
+                                if (instr[11]|instr[6]) rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end else begin
+                                if (~|instr[11:7])      rvc_illegal = 1'b1;
+                                // C.JR
+                                idu2exu_use_imm         = 1'b1;
+                                idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_REG_IMM;
+                                idu2exu_cmd.jump_req    = 1'b1;
+                                idu2exu_cmd.rs1_addr    = instr[11:7];
+                                idu2exu_cmd.imm         = 0;
+`ifdef SCR1_RVE_EXT
+                                if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end
+                        end else begin  // instr[12] == 1
+                            if (~|instr[11:2]) begin
+                                // C.EBREAK
+                                idu2exu_cmd.exc_req     = 1'b1;
+                                idu2exu_cmd.exc_code    = SCR1_EXC_CODE_BREAKPOINT;
+                            end else if (~|instr[6:2]) begin
+                                // C.JALR
+                                idu2exu_use_rs1         = 1'b1;
+                                idu2exu_use_rd          = 1'b1;
+                                idu2exu_use_imm         = 1'b1;
+                                idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_REG_IMM;
+                                idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_INC_PC;
+                                idu2exu_cmd.jump_req    = 1'b1;
+                                idu2exu_cmd.rs1_addr    = instr[11:7];
+                                idu2exu_cmd.rd_addr     = SCR1_MPRF_RA_ADDR;
+                                idu2exu_cmd.imm         = 0;
+`ifdef SCR1_RVE_EXT
+                                if (instr[11])          rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end else begin
+                                // C.ADD
+                                idu2exu_use_rs1         = 1'b1;
+                                idu2exu_use_rs2         = 1'b1;
+                                idu2exu_use_rd          = 1'b1;
+                                idu2exu_cmd.ialu_cmd    = SCR1_IALU_CMD_ADD;
+                                idu2exu_cmd.ialu_op     = SCR1_IALU_OP_REG_REG;
+                                idu2exu_cmd.rd_wb_sel   = SCR1_RD_WB_IALU;
+                                idu2exu_cmd.rs1_addr    = instr[11:7];
+                                idu2exu_cmd.rs2_addr    = instr[6:2];
+                                idu2exu_cmd.rd_addr     = instr[11:7];
+`ifdef SCR1_RVE_EXT
+                                if (instr[11]|instr[6]) rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                            end
+                        end // instr[12] == 1
+                    end
+                    3'b110  : begin
+                        // C.SWSP
+                        idu2exu_use_rs1         = 1'b1;
+                        idu2exu_use_rs2         = 1'b1;
+                        idu2exu_use_imm         = 1'b1;
+                        idu2exu_cmd.sum2_op     = SCR1_SUM2_OP_REG_IMM;
+                        idu2exu_cmd.lsu_cmd     = SCR1_LSU_CMD_SW;
+                        idu2exu_cmd.rs1_addr    = SCR1_MPRF_SP_ADDR;
+                        idu2exu_cmd.rs2_addr    = instr[6:2];
+                        idu2exu_cmd.imm         = {24'd0, instr[8:7], instr[12:9], 2'b00};
+`ifdef SCR1_RVE_EXT
+                        if (instr[6])           rve_illegal = 1'b1;
+`endif  // SCR1_RVE_EXT
+                    end
+                    default : begin
+                        rvc_illegal = 1'b1;
+                    end
+                endcase // funct3
+            end // Quadrant 2
+
+            default         : begin
+            end
+`else   // SCR1_RVC_EXT
+            default         : begin
+                idu2exu_cmd.instr_rvc   = 1'b1;
+                rvi_illegal             = 1'b1;
+            end
+`endif  // SCR1_RVC_EXT
+        endcase // instr_type
+    end // no imem fault
+
+    // At this point the instruction is fully decoded
+    // given that no imem fault has happened
+
+    // Check illegal instruction
+    if (
+    rvi_illegal
+`ifdef SCR1_RVC_EXT
+    | rvc_illegal
+`endif
+`ifdef SCR1_RVE_EXT
+    | rve_illegal
+`endif
+    ) begin
+        idu2exu_cmd.ialu_cmd        = SCR1_IALU_CMD_NONE;
+        idu2exu_cmd.lsu_cmd         = SCR1_LSU_CMD_NONE;
+        idu2exu_cmd.csr_cmd         = SCR1_CSR_CMD_NONE;
+        idu2exu_cmd.rd_wb_sel       = SCR1_RD_WB_NONE;
+        idu2exu_cmd.jump_req        = 1'b0;
+        idu2exu_cmd.branch_req      = 1'b0;
+        idu2exu_cmd.mret_req        = 1'b0;
+        idu2exu_cmd.fencei_req      = 1'b0;
+        idu2exu_cmd.wfi_req         = 1'b0;
+
+        idu2exu_use_rs1             = 1'b0;
+        idu2exu_use_rs2             = 1'b0;
+        idu2exu_use_rd              = 1'b0;
+
+`ifndef SCR1_MTVAL_ILLEGAL_INSTR_EN
+        idu2exu_use_imm             = 1'b0;
+`else // SCR1_MTVAL_ILLEGAL_INSTR_EN
+        idu2exu_use_imm             = 1'b1;
+        idu2exu_cmd.imm             = instr;
+`endif // SCR1_MTVAL_ILLEGAL_INSTR_EN
+
+        idu2exu_cmd.exc_req         = 1'b1;
+        idu2exu_cmd.exc_code        = SCR1_EXC_CODE_ILLEGAL_INSTR;
+    end
+
+end // RV32I(MC) decode
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+// X checks
+
+SCR1_SVA_IDU_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown({ifu2idu_vd, exu2idu_rdy})
+    ) else $error("IDU Error: unknown values");
+
+SCR1_SVA_IDU_XCHECK2 : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ifu2idu_vd |-> !$isunknown({ifu2idu_imem_err, (ifu2idu_imem_err ? 0 : ifu2idu_instr)})
+    ) else $error("IDU Error: unknown values");
+
+// Behavior checks
+
+SCR1_SVA_IDU_IALU_CMD_RANGE : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (ifu2idu_vd & ~ifu2idu_imem_err) |->
+    ((idu2exu_cmd.ialu_cmd >= SCR1_IALU_CMD_NONE) &
+    (idu2exu_cmd.ialu_cmd <=
+`ifdef SCR1_RVM_EXT
+                            SCR1_IALU_CMD_REMU
+`else
+                            SCR1_IALU_CMD_SRA
+`endif // SCR1_RVM_EXT
+        ))
+    ) else $error("IDU Error: IALU_CMD out of range");
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_idu
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_ifu.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_ifu.sv
new file mode 100644
index 0000000..ade2456
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_ifu.sv
@@ -0,0 +1,625 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_pipe_ifu.sv>
+/// @brief      Instruction Fetch Unit (IFU)
+///
+
+`include "scr1_memif.svh"
+`include "scr1_arch_description.svh"
+`ifdef SCR1_DBGC_EN
+`include "scr1_hdu.svh"
+`endif // SCR1_DBGC_EN
+
+module scr1_pipe_ifu
+(
+    // Control signals
+    input   logic                               rst_n,
+    input   logic                               clk,
+    // Instruction memory interface
+    input   logic                               imem_req_ack,
+    output  logic                               imem_req,
+    output  type_scr1_mem_cmd_e                 imem_cmd,
+    output  logic [`SCR1_IMEM_AWIDTH-1:0]       imem_addr,
+    input   logic [`SCR1_IMEM_DWIDTH-1:0]       imem_rdata,
+    input   type_scr1_mem_resp_e                imem_resp,
+    // NEW_PC interface
+    input   logic                               new_pc_req,         // New PC request (jumps, branches, traps etc)
+    input   logic [`SCR1_XLEN-1:0]              new_pc,             // New PC
+    input   logic                               stop_fetch,         // Stop IFU
+`ifdef SCR1_DBGC_EN
+    input   logic                               fetch_pbuf,         // Fetch instructions provided by Program Buffer
+    output  logic                               ifu2hdu_pbuf_rdy,
+    input   logic                               hdu2ifu_pbuf_vd,
+    input   logic                               hdu2ifu_pbuf_err,
+    input   logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] hdu2ifu_pbuf_instr,
+`endif // SCR1_DBGC_EN
+`ifdef SCR1_CLKCTRL_EN
+    output  logic                               imem_txns_pending,  // There are pending imem transactions
+`endif // SCR1_CLKCTRL_EN
+    // Instruction decode unit interface
+    input   logic                               idu2ifu_rdy,        // IDU ready for new data
+    output  logic [`SCR1_IMEM_DWIDTH-1:0]       ifu2idu_instr,      // IFU instruction
+    output  logic                               ifu2idu_imem_err,   // Instruction access fault exception
+    output  logic                               ifu2idu_err_rvi_hi, // 1 - imem fault when trying to fetch second half of an unaligned RVI instruction
+    output  logic                               ifu2idu_vd          // IFU request
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters declaration
+//-------------------------------------------------------------------------------
+
+localparam SCR1_IFU_Q_SIZE_WORD     = 2;
+localparam SCR1_IFU_Q_SIZE_HALF     = SCR1_IFU_Q_SIZE_WORD * 2;
+localparam SCR1_TXN_CNT_W           = 3;
+
+localparam SCR1_IFU_QUEUE_ADR_W     = $clog2(SCR1_IFU_Q_SIZE_HALF);
+localparam SCR1_IFU_QUEUE_PTR_W     = SCR1_IFU_QUEUE_ADR_W + 1;
+
+localparam SCR1_IFU_Q_FREE_H_W      = $clog2(SCR1_IFU_Q_SIZE_HALF + 1);
+localparam SCR1_IFU_Q_FREE_W_W      = $clog2(SCR1_IFU_Q_SIZE_WORD + 1);
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+
+typedef enum logic {
+    SCR1_FSM_IDLE,
+    SCR1_FSM_FETCH
+} type_scr1_ifu_fsm_e;
+
+typedef enum logic[1:0] {
+    SCR1_WE_NONE,                   // No write to queue
+    SCR1_WE_RDATA_FULL,             // Write 32 rdata bits to queue
+    SCR1_WE_RDATA_HI                // Write 16 upper rdata bits to queue
+} type_scr1_we_e;
+
+typedef enum logic[1:0] {
+    SCR1_RE_NONE,                   // No queue read
+    SCR1_RE_HALFWORD,               // Read halfword
+    SCR1_RE_WORD                    // Read word
+} type_scr1_re_e;
+
+typedef enum logic {
+    SCR1_RVI_PART2,                 // Rdata has RVI upper 16 bits in its lower 16 bits
+    SCR1_OTHER
+} type_scr1_rdata_type_e;
+
+`ifdef SCR1_IFU_QUEUE_BYPASS
+typedef enum logic[1:0] {
+    SCR1_BYPASS_NONE,               // No bypass
+    SCR1_BYPASS_RVC,                // Bypass RVC
+    SCR1_BYPASS_RVI_RDATA_QUEUE,    // Bypass RVI, rdata+queue
+    SCR1_BYPASS_RVI_RDATA           // Bypass RVI, rdata only
+} type_scr1_bypass_e;
+`endif // SCR1_IFU_QUEUE_BYPASS
+
+typedef enum logic [2:0] {
+    // SCR1_RDATA_<UPPER_16_BITS>_<LOWER_16_BITS>
+    SCR1_RDATA_NONE,                // No valid rdata
+    SCR1_RDATA_RVI_HI_RVI_LO,       // Full RV32I instruction
+    SCR1_RDATA_RVC_RVC,
+    SCR1_RDATA_RVI_LO_RVC,
+    SCR1_RDATA_RVC_RVI_HI,
+    SCR1_RDATA_RVI_LO_RVI_HI,
+    SCR1_RDATA_RVC_NV,              // Rdata after unaligned new_pc
+    SCR1_RDATA_RVI_LO_NV            // Rdata after unaligned new_pc
+} type_scr1_rdata_ident_e;
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+
+type_scr1_ifu_fsm_e                 fsm;
+logic [`SCR1_XLEN-1:2]              imem_addr_r;
+logic [`SCR1_XLEN-1:2]              imem_addr_r_new;
+logic [SCR1_TXN_CNT_W-1:0]          num_txns_pending;           // Transactions sent but not yet returned
+logic [SCR1_TXN_CNT_W-1:0]          num_txns_pending_new;
+logic [SCR1_TXN_CNT_W-1:0]          discard_resp_cnt;           // Number of imem responses to discard
+logic [SCR1_TXN_CNT_W-1:0]          discard_resp_cnt_new;
+logic                               discard_resp;
+logic [SCR1_TXN_CNT_W-1:0]          num_vd_txns_pending;
+logic                               num_txns_pending_full;
+logic                               imem_resp_ok;
+logic                               imem_resp_er;
+logic                               imem_resp_vd;
+logic                               new_pc_unaligned;
+
+logic                               q_empty;
+logic                               q_flush;
+logic [SCR1_IFU_QUEUE_PTR_W-1:0]    q_rptr;
+logic [SCR1_IFU_QUEUE_PTR_W-1:0]    q_rptr_next;
+logic [SCR1_IFU_QUEUE_PTR_W-1:0]    q_wptr;
+logic [SCR1_IFU_QUEUE_PTR_W-1:0]    q_wptr_next;
+logic [SCR1_IFU_Q_FREE_H_W-1:0]     q_ocpd_h;                   // Queue occupied halfwords
+logic [SCR1_IFU_Q_FREE_H_W-1:0]     q_free_h_next;
+logic [SCR1_IFU_Q_FREE_W_W-1:0]     q_free_w_next;              // Used for imem_req logic
+
+logic [`SCR1_IMEM_DWIDTH/2-1:0]     q_data  [SCR1_IFU_Q_SIZE_HALF];
+logic                               q_err   [SCR1_IFU_Q_SIZE_HALF];
+type_scr1_re_e                      q_re;                       // Queue read
+type_scr1_we_e                      q_we;                       // Queue write
+logic                               q_head_rvc;                 // RVC instruction at read pointer
+logic                               q_head_rvi;                 // RVI instruction at read pointer
+logic [`SCR1_IMEM_DWIDTH/2-1:0]     q_data_head;
+logic [`SCR1_IMEM_DWIDTH/2-1:0]     q_data_next;
+logic                               q_err_head;
+logic                               q_err_next;
+
+type_scr1_rdata_type_e              rdata_curr;
+type_scr1_rdata_type_e              rdata_next;
+type_scr1_rdata_ident_e             rdata_ident;                // Identifies contents of rdata
+`ifdef SCR1_IFU_QUEUE_BYPASS
+type_scr1_bypass_e                  instr_bypass;               // Do not write to queue, pass directly to IDU
+logic                               instr_bypass_vd;
+`endif // SCR1_IFU_QUEUE_BYPASS
+
+
+//-------------------------------------------------------------------------------
+// Instruction queue logic
+//-------------------------------------------------------------------------------
+assign q_empty          = (q_rptr == q_wptr);
+assign q_flush          = new_pc_req | stop_fetch;
+
+assign q_ocpd_h         = SCR1_IFU_Q_FREE_H_W'(q_wptr - q_rptr);
+assign q_free_h_next    = SCR1_IFU_Q_FREE_H_W'(SCR1_IFU_Q_SIZE_HALF - (q_wptr - q_rptr_next));
+assign q_free_w_next    = SCR1_IFU_Q_FREE_W_W'(q_free_h_next >> 1'b1);
+
+assign q_head_rvi       = &(q_data_head[1:0]);
+assign q_head_rvc       = ~q_head_rvi;
+
+assign q_data_head      = q_data [SCR1_IFU_QUEUE_ADR_W'(q_rptr)];
+assign q_data_next      = q_data [SCR1_IFU_QUEUE_ADR_W'(q_rptr + 1'b1)];
+assign q_err_head       = q_err  [SCR1_IFU_QUEUE_ADR_W'(q_rptr)];
+assign q_err_next       = q_err  [SCR1_IFU_QUEUE_ADR_W'(q_rptr + 1'b1)];
+
+
+always_comb begin
+    q_re = SCR1_RE_NONE;
+
+    if (~q_empty & ifu2idu_vd & idu2ifu_rdy) begin
+        if (q_head_rvc | q_err_head
+`ifdef SCR1_IFU_QUEUE_BYPASS
+                | (q_head_rvi & instr_bypass_vd)
+`endif // SCR1_IFU_QUEUE_BYPASS
+            ) begin
+            q_re = SCR1_RE_HALFWORD;
+        end else begin
+            q_re = SCR1_RE_WORD;
+        end
+    end
+end
+
+always_comb begin
+    q_we = SCR1_WE_NONE;
+
+    if (~discard_resp) begin
+        if (imem_resp_ok) begin
+`ifdef SCR1_IFU_QUEUE_BYPASS
+            case (rdata_ident)
+                SCR1_RDATA_NONE             : q_we = SCR1_WE_NONE;
+                SCR1_RDATA_RVI_LO_NV        : q_we = SCR1_WE_RDATA_HI;
+                SCR1_RDATA_RVC_NV           : q_we = (instr_bypass_vd & idu2ifu_rdy) ? SCR1_WE_NONE : SCR1_WE_RDATA_HI;
+                SCR1_RDATA_RVI_HI_RVI_LO    : q_we = (instr_bypass_vd & idu2ifu_rdy) ? SCR1_WE_NONE : SCR1_WE_RDATA_FULL;
+                SCR1_RDATA_RVC_RVC,
+                SCR1_RDATA_RVI_LO_RVC,
+                SCR1_RDATA_RVC_RVI_HI,
+                SCR1_RDATA_RVI_LO_RVI_HI    : q_we = (instr_bypass_vd & idu2ifu_rdy) ? SCR1_WE_RDATA_HI : SCR1_WE_RDATA_FULL;
+            endcase // rdata_ident
+`else // SCR1_IFU_QUEUE_BYPASS
+            case (rdata_ident)
+                SCR1_RDATA_NONE             : q_we = SCR1_WE_NONE;
+                SCR1_RDATA_RVC_NV,
+                SCR1_RDATA_RVI_LO_NV        : q_we = SCR1_WE_RDATA_HI;
+                default                     : q_we = SCR1_WE_RDATA_FULL;
+            endcase // rdata_ident
+`endif // SCR1_IFU_QUEUE_BYPASS
+        end else if (imem_resp_er) begin
+            q_we = SCR1_WE_RDATA_FULL;
+        end // imem_resp_er
+    end // ~discard_resp
+end
+
+always_comb begin
+    q_rptr_next = q_rptr;
+    q_wptr_next = q_wptr;
+
+    if ((q_we == SCR1_WE_RDATA_HI) | (q_we == SCR1_WE_RDATA_FULL)) begin
+        q_wptr_next = q_wptr + ((q_we == SCR1_WE_RDATA_FULL) ? 2'd2 : 1'b1);
+    end
+    if ((q_re == SCR1_RE_WORD) | (q_re == SCR1_RE_HALFWORD)) begin
+        q_rptr_next = q_rptr + ((q_re == SCR1_RE_WORD) ? 2'd2 : 1'b1);
+    end
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        q_rptr  <= '0;
+        q_wptr  <= '0;
+    end else begin
+        if (q_flush) begin
+            q_rptr  <= '0;
+            q_wptr  <= '0;
+        end else begin
+            if ((q_we == SCR1_WE_RDATA_HI) | (q_we == SCR1_WE_RDATA_FULL)) begin
+                q_wptr  <= q_wptr_next;
+            end
+            if ((q_re == SCR1_RE_WORD) | (q_re == SCR1_RE_HALFWORD)) begin
+                q_rptr  <= q_rptr_next;
+            end
+        end
+    end
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        q_data  <= '{SCR1_IFU_Q_SIZE_HALF{'0}};
+        q_err   <= '{SCR1_IFU_Q_SIZE_HALF{1'b0}};
+    end else begin
+        if (imem_resp_vd & ~q_flush) begin
+            case (q_we)
+                SCR1_WE_RDATA_HI    : begin
+                    q_data  [SCR1_IFU_QUEUE_ADR_W'(q_wptr)] <= imem_rdata[31:16];
+                    q_err   [SCR1_IFU_QUEUE_ADR_W'(q_wptr)] <= imem_resp_er;
+                end
+                SCR1_WE_RDATA_FULL  : begin
+                    q_data  [SCR1_IFU_QUEUE_ADR_W'(q_wptr)] <= imem_rdata[15:0];
+                    q_err   [SCR1_IFU_QUEUE_ADR_W'(q_wptr)] <= imem_resp_er;
+                    q_data  [SCR1_IFU_QUEUE_ADR_W'(q_wptr + 1'b1)]  <= imem_rdata[31:16];
+                    q_err   [SCR1_IFU_QUEUE_ADR_W'(q_wptr + 1'b1)]  <= imem_resp_er;
+                end
+            endcase // q_we
+        end // write
+    end
+end
+
+//-------------------------------------------------------------------------------
+// RDATA logic
+//-------------------------------------------------------------------------------
+always_comb begin
+    rdata_ident = SCR1_RDATA_NONE;
+
+    if (imem_resp_ok & ~discard_resp) begin
+        if (new_pc_unaligned) begin
+            if (&imem_rdata[17:16]) begin
+                rdata_ident = SCR1_RDATA_RVI_LO_NV;
+            end else begin
+                rdata_ident = SCR1_RDATA_RVC_NV;
+            end
+        end else begin // ~new_pc_unaligned
+            if (rdata_curr == SCR1_RVI_PART2) begin
+                if (&imem_rdata[17:16]) begin
+                    rdata_ident = SCR1_RDATA_RVI_LO_RVI_HI;
+                end else begin
+                    rdata_ident = SCR1_RDATA_RVC_RVI_HI;
+                end
+            end else begin // SCR1_OTHER
+                casez ({&imem_rdata[17:16], &imem_rdata[1:0]})
+                    2'b?1   : rdata_ident   = SCR1_RDATA_RVI_HI_RVI_LO;
+                    2'b00   : rdata_ident   = SCR1_RDATA_RVC_RVC;
+                    2'b10   : rdata_ident   = SCR1_RDATA_RVI_LO_RVC;
+                endcase
+            end // SCR1_OTHER
+        end // ~new_pc_unaligned
+    end // (imem_resp_ok & ~discard_resp)
+end
+
+assign rdata_next   =   ( (rdata_ident == SCR1_RDATA_RVI_LO_NV)
+                        | (rdata_ident == SCR1_RDATA_RVI_LO_RVI_HI)
+                        | (rdata_ident == SCR1_RDATA_RVI_LO_RVC) ) ? SCR1_RVI_PART2 : SCR1_OTHER;
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        rdata_curr  <= SCR1_OTHER;
+    end else begin
+        if (new_pc_req) begin
+            rdata_curr  <= SCR1_OTHER;
+        end else if (imem_resp_vd) begin
+            rdata_curr  <= rdata_next;
+        end
+    end
+end
+
+
+//-------------------------------------------------------------------------------
+// Bypass logic
+//-------------------------------------------------------------------------------
+`ifdef SCR1_IFU_QUEUE_BYPASS
+assign instr_bypass_vd  = (instr_bypass != SCR1_BYPASS_NONE);
+
+always_comb begin
+    instr_bypass    = SCR1_BYPASS_NONE;
+
+    if (imem_resp_vd) begin
+        if (q_empty) begin
+            case (rdata_ident)
+                SCR1_RDATA_RVC_NV,
+                SCR1_RDATA_RVC_RVC,
+                SCR1_RDATA_RVI_LO_RVC       : begin
+                    instr_bypass    = SCR1_BYPASS_RVC;
+                end
+                SCR1_RDATA_RVI_HI_RVI_LO    : begin
+                    instr_bypass    = SCR1_BYPASS_RVI_RDATA;
+                end
+                default : begin end
+            endcase // rdata_ident
+        end else if ((q_ocpd_h == SCR1_IFU_Q_FREE_H_W'(1)) & q_head_rvi) begin
+            if (rdata_curr == SCR1_RVI_PART2) begin
+                instr_bypass    = SCR1_BYPASS_RVI_RDATA_QUEUE;
+            end
+        end
+    end // imem_resp_vd
+end
+`endif // SCR1_IFU_QUEUE_BYPASS
+
+
+//-------------------------------------------------------------------------------
+// Instruction memory interface logic
+//-------------------------------------------------------------------------------
+
+assign imem_req = (new_pc_req & ~num_txns_pending_full & ~stop_fetch) |
+(
+    (fsm == SCR1_FSM_FETCH) &
+    ~num_txns_pending_full &
+    (SCR1_TXN_CNT_W'(q_free_w_next) > num_vd_txns_pending)
+);
+
+assign imem_cmd                 = SCR1_MEM_CMD_RD;
+assign imem_addr                = {(new_pc_req ? new_pc[`SCR1_XLEN-1:2] : imem_addr_r), 2'b00};
+
+assign imem_resp_er             = (imem_resp == SCR1_MEM_RESP_RDY_ER);
+assign imem_resp_ok             = (imem_resp == SCR1_MEM_RESP_RDY_OK);
+assign imem_resp_vd             = (imem_resp_ok | imem_resp_er) & ~discard_resp;
+assign num_txns_pending_full    = &num_txns_pending;
+`ifdef SCR1_CLKCTRL_EN
+assign imem_txns_pending        = |num_txns_pending;
+`endif // SCR1_CLKCTRL_EN
+
+assign imem_addr_r_new = (new_pc_req ? new_pc[`SCR1_XLEN-1:2] : imem_addr_r) + 1'b1;
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        imem_addr_r <= '0;
+    end else begin
+        if (imem_req & imem_req_ack) begin
+            // if req & ack, store either incremented new_pc or incremented address
+            if (new_pc_req) begin
+                imem_addr_r <= imem_addr_r_new;
+            end else begin
+                imem_addr_r[5:2] <= imem_addr_r_new[5:2];
+                if (&imem_addr_r[5:2]) begin
+                    imem_addr_r[`SCR1_XLEN-1:6] <= imem_addr_r_new[`SCR1_XLEN-1:6];
+                end
+            end
+        end else if (new_pc_req) begin
+            imem_addr_r <= new_pc[`SCR1_XLEN-1:2];
+        end
+    end
+end
+
+assign num_txns_pending_new = num_txns_pending + (imem_req & imem_req_ack) - (imem_resp_ok | imem_resp_er);
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        num_txns_pending <= '0;
+    end else if ((imem_req & imem_req_ack) ^ (imem_resp_ok | imem_resp_er)) begin
+        num_txns_pending <= num_txns_pending_new;
+    end
+end
+
+
+always_comb begin
+    if (new_pc_req) begin
+        discard_resp_cnt_new = num_txns_pending_new - (imem_req & imem_req_ack);
+    end else if (imem_resp_er & ~discard_resp) begin
+        discard_resp_cnt_new = num_txns_pending_new;
+    end else begin
+        discard_resp_cnt_new = discard_resp_cnt - 1'b1;
+    end
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        discard_resp_cnt <= '0;
+    end else if (new_pc_req | imem_resp_er | (imem_resp_ok & discard_resp)) begin
+        discard_resp_cnt <= discard_resp_cnt_new;
+    end
+end
+
+assign num_vd_txns_pending  = num_txns_pending - discard_resp_cnt;
+assign discard_resp         = |discard_resp_cnt;
+
+
+//-------------------------------------------------------------------------------
+// Control logic
+//-------------------------------------------------------------------------------
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        fsm <= SCR1_FSM_IDLE;
+    end else begin
+        case (fsm)
+            SCR1_FSM_IDLE   : begin
+                if (new_pc_req & ~stop_fetch) begin
+                    fsm <= SCR1_FSM_FETCH;
+                end
+            end
+            SCR1_FSM_FETCH  : begin
+                if (stop_fetch | (imem_resp_er & ~discard_resp & ~new_pc_req)) begin
+                    fsm <= SCR1_FSM_IDLE;
+                end
+            end
+        endcase // fsm
+    end
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        new_pc_unaligned    <= 1'b0;
+    end else begin
+        if (new_pc_req) begin
+            new_pc_unaligned    <= new_pc[1];
+        end else if (imem_resp_vd) begin
+            new_pc_unaligned    <= 1'b0;
+        end
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Instruction decode unit interface
+//-------------------------------------------------------------------------------
+`ifdef SCR1_IFU_QUEUE_BYPASS
+
+always_comb begin
+    ifu2idu_vd          = 1'b0;
+    ifu2idu_imem_err    = 1'b0;
+    ifu2idu_err_rvi_hi  = 1'b0;
+    if ((fsm == SCR1_FSM_FETCH) | ~q_empty) begin
+        if (instr_bypass_vd) begin
+            ifu2idu_vd          = 1'b1;
+            ifu2idu_imem_err    = (instr_bypass == SCR1_BYPASS_RVI_RDATA_QUEUE) ? (imem_resp_er | q_err_head) : imem_resp_er;
+            ifu2idu_err_rvi_hi  = (instr_bypass == SCR1_BYPASS_RVI_RDATA_QUEUE) & imem_resp_er;
+        end else if (~q_empty) begin
+            if (q_ocpd_h == SCR1_IFU_Q_FREE_H_W'(1)) begin
+                ifu2idu_vd          = q_head_rvc | q_err_head;
+                ifu2idu_imem_err    = q_err_head;
+            end else begin          // 2 or more halfwords occupied
+                ifu2idu_vd          = 1'b1;
+                ifu2idu_imem_err    = q_err_head ? 1'b1 : (q_head_rvi & q_err_next);
+                ifu2idu_err_rvi_hi  = ~q_err_head & q_head_rvi & q_err_next;
+            end
+        end // ~q_empty
+    end
+`ifdef SCR1_DBGC_EN
+    if (fetch_pbuf) begin
+        ifu2idu_vd          = hdu2ifu_pbuf_vd;
+        ifu2idu_imem_err    = hdu2ifu_pbuf_err;
+    end
+`endif // SCR1_DBGC_EN
+end
+
+always_comb begin
+    case (instr_bypass)
+        SCR1_BYPASS_RVC             : begin
+            ifu2idu_instr   = `SCR1_IMEM_DWIDTH'(new_pc_unaligned ? imem_rdata[31:16] : imem_rdata[15:0]);
+        end
+        SCR1_BYPASS_RVI_RDATA       : begin
+            ifu2idu_instr   = imem_rdata;
+        end
+        SCR1_BYPASS_RVI_RDATA_QUEUE : begin
+            ifu2idu_instr   = {imem_rdata[15:0], q_data_head};
+        end
+        default                     : begin
+            ifu2idu_instr   = `SCR1_IMEM_DWIDTH'(q_head_rvc ? q_data_head : {q_data_next, q_data_head});
+        end
+    endcase // instr_bypass
+`ifdef SCR1_DBGC_EN
+    if (fetch_pbuf) begin
+        ifu2idu_instr = `SCR1_IMEM_DWIDTH'({'0, hdu2ifu_pbuf_instr});
+    end
+`endif // SCR1_DBGC_EN
+end
+
+`else   // SCR1_IFU_QUEUE_BYPASS
+
+always_comb begin
+    ifu2idu_vd          = 1'b0;
+    ifu2idu_imem_err    = 1'b0;
+    ifu2idu_err_rvi_hi  = 1'b0;
+    if (~q_empty) begin
+        if (q_ocpd_h == SCR1_IFU_Q_FREE_H_W'(1)) begin
+            ifu2idu_vd          = q_head_rvc | q_err_head;
+            ifu2idu_imem_err    = q_err_head;
+        end else begin          // 2 or more halfwords occupied
+            ifu2idu_vd          = 1'b1;
+            ifu2idu_imem_err    = q_err_head ? 1'b1 : (q_head_rvi & q_err_next);
+            ifu2idu_err_rvi_hi  = ~q_err_head & q_head_rvi & q_err_next;
+        end
+    end // ~q_empty
+`ifdef SCR1_DBGC_EN
+    if (fetch_pbuf) begin
+        ifu2idu_vd          = hdu2ifu_pbuf_vd;
+        ifu2idu_imem_err    = hdu2ifu_pbuf_err;
+    end
+`endif // SCR1_DBGC_EN
+end
+
+always_comb begin
+    ifu2idu_instr = q_head_rvc ? `SCR1_IMEM_DWIDTH'(q_data_head) : {q_data_next, q_data_head};
+`ifdef SCR1_DBGC_EN
+    if (fetch_pbuf) begin
+        ifu2idu_instr = `SCR1_IMEM_DWIDTH'({'0, hdu2ifu_pbuf_instr});
+    end
+`endif // SCR1_DBGC_EN
+end
+
+`endif  // SCR1_IFU_QUEUE_BYPASS
+
+`ifdef SCR1_DBGC_EN
+assign ifu2hdu_pbuf_rdy = idu2ifu_rdy;
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+// X checks
+
+SCR1_SVA_IFU_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown({imem_req_ack, idu2ifu_rdy, new_pc_req})
+    ) else $error("IFU Error: unknown values");
+
+SCR1_SVA_IFU_XCHECK_REQ : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    imem_req |-> !$isunknown({imem_addr, imem_cmd})
+    ) else $error("IFU Error: unknown {imem_addr, imem_cmd}");
+
+// Behavior checks
+
+SCR1_SVA_IFU_DRC_UNDERFLOW : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ~discard_resp |=> ~(discard_resp_cnt == SCR1_TXN_CNT_W'('1))
+    ) else $error("IFU Error: discard_resp_cnt underflow");
+
+SCR1_SVA_IFU_DRC_RANGE : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (discard_resp_cnt >= 0) & (discard_resp_cnt <= num_txns_pending)
+    ) else $error("IFU Error: discard_resp_cnt out of range");
+
+SCR1_SVA_IFU_QUEUE_OVF : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (q_ocpd_h >= (SCR1_IFU_Q_SIZE_HALF-1)) |->
+    ((q_ocpd_h == (SCR1_IFU_Q_SIZE_HALF-1)) ? (q_we != SCR1_WE_RDATA_FULL) : (q_we == SCR1_WE_NONE))
+    ) else $error("IFU Error: queue overflow");
+
+SCR1_SVA_IFU_IMEM_ERR_BEH : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (imem_resp_er & ~discard_resp & ~new_pc_req) |=>
+    (fsm == SCR1_FSM_IDLE) & (discard_resp_cnt == num_txns_pending)
+    ) else $error("IFU Error: incorrect behavior after memory error");
+
+SCR1_SVA_IFU_NEW_PC_REQ_BEH : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    new_pc_req |=> q_empty
+    ) else $error("IFU Error: incorrect behavior after new_pc_req");
+
+SCR1_SVA_IFU_IMEM_ADDR_ALIGNED : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    imem_req |-> ~|imem_addr[1:0]
+    ) else $error("IFU Error: unaligned IMEM access");
+
+SCR1_SVA_IFU_STOP_FETCH : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    stop_fetch |=> (fsm == SCR1_FSM_IDLE)
+    ) else $error("IFU Error: fetch not stopped");
+
+SCR1_SVA_IFU_IMEM_FAULT_RVI_HI : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    ifu2idu_err_rvi_hi |-> ifu2idu_imem_err
+    ) else $error("IFU Error: ifu2idu_imem_err == 0");
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_ifu
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_lsu.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_lsu.sv
new file mode 100644
index 0000000..118b4b2
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_lsu.sv
@@ -0,0 +1,303 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_pipe_lsu.sv>
+/// @brief      Load/Store Unit (LSU)
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_arch_types.svh"
+`include "scr1_memif.svh"
+`include "scr1_riscv_isa_decoding.svh"
+`ifdef SCR1_BRKM_EN
+`include "scr1_tdu.svh"
+`endif // SCR1_BRKM_EN
+
+module scr1_pipe_lsu (
+    // Common
+    input   logic                               rst_n,
+    input   logic                               clk,
+
+    // EXU <-> LSU interface
+    input   logic                               exu2lsu_req,            // Request to LSU
+    input   type_scr1_lsu_cmd_sel_e             exu2lsu_cmd,            // LSU command
+    input   logic [`SCR1_XLEN-1:0]              exu2lsu_addr,           // Address of DMEM
+    input   logic [`SCR1_XLEN-1:0]              exu2lsu_s_data,         // Data for store
+    output  logic                               lsu2exu_rdy,            // LSU received DMEM response
+    output  logic [`SCR1_XLEN-1:0]              lsu2exu_l_data,         // Load data
+    output  logic                               lsu2exu_exc,            // Exception from LSU
+    output  type_scr1_exc_code_e                lsu2exu_exc_code,       // Exception code
+
+    // TDU <-> LSU interface
+`ifdef SCR1_BRKM_EN
+    output  type_scr1_brkm_lsu_mon_s            lsu2tdu_d_mon,
+    input   logic                               tdu2lsu_i_x_req,
+    input   logic                               tdu2lsu_d_x_req,
+`endif // SCR1_BRKM_EN
+
+    // Data memory interface
+    output  logic                               lsu2dmem_req,
+    output  type_scr1_mem_cmd_e                 lsu2dmem_cmd,
+    output  type_scr1_mem_width_e               lsu2dmem_width,
+    output  logic [`SCR1_DMEM_AWIDTH-1:0]       lsu2dmem_addr,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]       lsu2dmem_wdata,
+    input   logic                               dmem2lsu_req_ack,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]       dmem2lsu_rdata,
+    input   type_scr1_mem_resp_e                dmem2lsu_resp
+);
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {SCR1_FSM_IDLE, SCR1_FSM_BUSY} type_scr1_lsu_fsm_e;
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+type_scr1_lsu_fsm_e         fsm;
+type_scr1_lsu_cmd_sel_e     lsu_cmd_r;
+logic                       dmem_resp_ok;
+logic                       dmem_resp_er;
+logic                       l_misalign;
+logic                       s_misalign;
+`ifdef SCR1_BRKM_EN
+logic                       lsu_hwbrk;
+`endif // SCR1_BRKM_EN
+
+
+//-------------------------------------------------------------------------------
+// Main logic
+//-------------------------------------------------------------------------------
+assign dmem_resp_ok = (dmem2lsu_resp == SCR1_MEM_RESP_RDY_OK);
+assign dmem_resp_er = (dmem2lsu_resp == SCR1_MEM_RESP_RDY_ER);
+
+//-------------------------------------------------------------------------------
+// FSM
+//-------------------------------------------------------------------------------
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        fsm         <= SCR1_FSM_IDLE;
+        lsu_cmd_r   <= SCR1_LSU_CMD_NONE;
+    end else begin
+        case (fsm)
+            SCR1_FSM_IDLE   : begin
+                if (exu2lsu_req & dmem2lsu_req_ack & ~lsu2exu_exc) begin
+                    fsm         <= SCR1_FSM_BUSY;
+                    lsu_cmd_r   <= exu2lsu_cmd;
+                end
+            end
+            SCR1_FSM_BUSY   : begin
+                if (dmem_resp_ok | dmem_resp_er) begin
+                    fsm     <= SCR1_FSM_IDLE;
+                end
+            end
+        endcase // fsm
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Load / store address misaligned exception
+//-------------------------------------------------------------------------------
+always_comb begin
+    l_misalign = 1'b0;
+    s_misalign = 1'b0;
+    if (exu2lsu_req) begin
+        case (exu2lsu_cmd)
+            SCR1_LSU_CMD_LH,
+            SCR1_LSU_CMD_LHU    : l_misalign = exu2lsu_addr[0];
+            SCR1_LSU_CMD_LW     : l_misalign = |exu2lsu_addr[1:0];
+            SCR1_LSU_CMD_SH     : s_misalign = exu2lsu_addr[0];
+            SCR1_LSU_CMD_SW     : s_misalign = |exu2lsu_addr[1:0];
+            default : begin end
+        endcase // exu2lsu_cmd
+    end
+end
+
+//-------------------------------------------------------------------------------
+// LSU <-> EXU interface
+//-------------------------------------------------------------------------------
+assign lsu2exu_rdy  =   (dmem_resp_ok | dmem_resp_er);
+assign lsu2exu_exc  =   dmem_resp_er | l_misalign | s_misalign
+`ifdef SCR1_BRKM_EN
+                        | lsu_hwbrk
+`endif // SCR1_BRKM_EN
+;
+
+//-------------------------------------------------------------------------------
+// Exception code
+//-------------------------------------------------------------------------------
+always_comb begin
+    case (1'b1)
+        dmem_resp_er    : begin
+            case (lsu_cmd_r)
+                SCR1_LSU_CMD_LB,
+                SCR1_LSU_CMD_LH,
+                SCR1_LSU_CMD_LW,
+                SCR1_LSU_CMD_LBU,
+                SCR1_LSU_CMD_LHU    : lsu2exu_exc_code = SCR1_EXC_CODE_LD_ACCESS_FAULT;
+                SCR1_LSU_CMD_SB,
+                SCR1_LSU_CMD_SH,
+                SCR1_LSU_CMD_SW     : lsu2exu_exc_code = SCR1_EXC_CODE_ST_ACCESS_FAULT;
+                // Impossible
+                default             : lsu2exu_exc_code = SCR1_EXC_CODE_INSTR_MISALIGN;
+            endcase
+        end // dmem_resp_er
+`ifdef SCR1_BRKM_EN
+        lsu_hwbrk                   : lsu2exu_exc_code = SCR1_EXC_CODE_BREAKPOINT;
+`endif // SCR1_BRKM_EN
+        l_misalign                  : lsu2exu_exc_code = SCR1_EXC_CODE_LD_ADDR_MISALIGN;
+        s_misalign                  : lsu2exu_exc_code = SCR1_EXC_CODE_ST_ADDR_MISALIGN;
+        default                     : lsu2exu_exc_code = SCR1_EXC_CODE_INSTR_MISALIGN;
+    endcase // 1'b1
+end
+
+//-------------------------------------------------------------------------------
+// Sign-extend or zero-extend received data
+//-------------------------------------------------------------------------------
+always_comb begin
+    case (lsu_cmd_r)
+        SCR1_LSU_CMD_LW     : lsu2exu_l_data = dmem2lsu_rdata;
+        SCR1_LSU_CMD_LH     : lsu2exu_l_data = $signed  (dmem2lsu_rdata[15:0]);
+        SCR1_LSU_CMD_LHU    : lsu2exu_l_data = dmem2lsu_rdata[15:0];
+        SCR1_LSU_CMD_LB     : lsu2exu_l_data = $signed  (dmem2lsu_rdata[7:0]);
+        SCR1_LSU_CMD_LBU    : lsu2exu_l_data = dmem2lsu_rdata[7:0];
+        default             : lsu2exu_l_data = '0;
+    endcase // lsu_cmd_r
+end
+
+//-------------------------------------------------------------------------------
+// Data memory interface
+//-------------------------------------------------------------------------------
+assign lsu2dmem_req     = exu2lsu_req & ~lsu2exu_exc & (fsm == SCR1_FSM_IDLE);
+assign lsu2dmem_addr    = exu2lsu_addr;
+assign lsu2dmem_wdata   = exu2lsu_s_data;
+
+always_comb begin
+    case (exu2lsu_cmd)
+        SCR1_LSU_CMD_LB,
+        SCR1_LSU_CMD_LBU    : begin
+            lsu2dmem_cmd    = SCR1_MEM_CMD_RD;
+            lsu2dmem_width  = SCR1_MEM_WIDTH_BYTE;
+        end
+        SCR1_LSU_CMD_LH,
+        SCR1_LSU_CMD_LHU    : begin
+            lsu2dmem_cmd    = SCR1_MEM_CMD_RD;
+            lsu2dmem_width  = SCR1_MEM_WIDTH_HWORD;
+        end
+        SCR1_LSU_CMD_LW     : begin
+            lsu2dmem_cmd    = SCR1_MEM_CMD_RD;
+            lsu2dmem_width  = SCR1_MEM_WIDTH_WORD;
+        end
+        SCR1_LSU_CMD_SB     : begin
+            lsu2dmem_cmd    = SCR1_MEM_CMD_WR;
+            lsu2dmem_width  = SCR1_MEM_WIDTH_BYTE;
+        end
+        SCR1_LSU_CMD_SH     : begin
+            lsu2dmem_cmd    = SCR1_MEM_CMD_WR;
+            lsu2dmem_width  = SCR1_MEM_WIDTH_HWORD;
+        end
+        SCR1_LSU_CMD_SW     : begin
+            lsu2dmem_cmd    = SCR1_MEM_CMD_WR;
+            lsu2dmem_width  = SCR1_MEM_WIDTH_WORD;
+        end
+        default             : begin
+            lsu2dmem_cmd    = SCR1_MEM_CMD_RD;
+            lsu2dmem_width  = SCR1_MEM_WIDTH_WORD;
+        end
+    endcase // exu2lsu_cmd
+end
+
+`ifdef SCR1_BRKM_EN
+//-------------------------------------------------------------------------------
+// TDU
+//-------------------------------------------------------------------------------
+assign lsu2tdu_d_mon.vd        = exu2lsu_req & (fsm == SCR1_FSM_IDLE) & ~tdu2lsu_i_x_req;
+assign lsu2tdu_d_mon.addr      = exu2lsu_addr;
+assign lsu2tdu_d_mon.load      = (lsu2dmem_cmd == SCR1_MEM_CMD_RD);
+assign lsu2tdu_d_mon.store     = (lsu2dmem_cmd == SCR1_MEM_CMD_WR);
+
+`ifndef SCR1_BRKM_EN
+always_comb begin
+    case (lsu2dmem_width)
+        SCR1_MEM_WIDTH_BYTE: begin
+            lsu2tdu_d_mon.width = SCR1_OP_WIDTH_BYTE;
+        end
+
+        SCR1_MEM_WIDTH_HWORD: begin
+            lsu2tdu_d_mon.width = SCR1_OP_WIDTH_HALF;
+        end
+
+        SCR1_MEM_WIDTH_WORD: begin
+            lsu2tdu_d_mon.width = SCR1_OP_WIDTH_WORD;
+        end
+
+        default: begin
+            lsu2tdu_d_mon.width = SCR1_OP_WIDTH_ERROR;
+        end
+    endcase
+end
+`endif // SCR1_BRKM_EN
+
+assign lsu_hwbrk    = (exu2lsu_req & tdu2lsu_i_x_req) | tdu2lsu_d_x_req;
+
+`endif // SCR1_BRKM_EN
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+// X checks
+
+SCR1_SVA_LSU_XCHECK_CTRL : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown({exu2lsu_req, fsm
+`ifdef SCR1_BRKM_EN
+        , tdu2lsu_i_x_req, tdu2lsu_d_x_req
+`endif // SCR1_BRKM_EN
+    })
+    ) else $error("LSU Error: unknown control value");
+
+SCR1_SVA_LSU_XCHECK_CMD : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    exu2lsu_req |-> !$isunknown({exu2lsu_cmd, exu2lsu_addr})
+    ) else $error("LSU Error: exception code undefined");
+
+SCR1_SVA_LSU_XCHECK_SDATA : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (exu2lsu_req & (lsu2dmem_cmd == SCR1_MEM_CMD_WR)) |-> !$isunknown({exu2lsu_s_data})
+    ) else $error("LSU Error: exception code undefined");
+
+SCR1_SVA_LSU_XCHECK_EXC : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    lsu2exu_exc |-> !$isunknown(lsu2exu_exc_code)
+    ) else $error("LSU Error: exception code undefined");
+
+// Behavior checks
+
+SCR1_SVA_LSU_EXC_ONEHOT : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    $onehot0({dmem_resp_er, l_misalign, s_misalign})
+    ) else $error("LSU Error: more than one exception at a time");
+
+SCR1_SVA_LSU_UNEXPECTED_DMEM_RESP : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    (fsm == SCR1_FSM_IDLE) |-> ~(dmem_resp_ok | dmem_resp_er)
+    ) else $error("LSU Error: not expecting memory response");
+
+SCR1_SVA_LSU_REQ_EXC : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    lsu2exu_exc |-> exu2lsu_req
+    ) else $error("LSU Error: impossible exception");
+
+`ifdef SCR1_BRKM_EN
+SCR1_COV_LSU_MISALIGN_BRKPT : cover property (
+    @(negedge clk) disable iff (~rst_n)
+    (l_misalign | s_misalign) & lsu_hwbrk
+);
+`endif // SCR1_BRKM_EN
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_lsu
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_mprf.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_mprf.sv
new file mode 100644
index 0000000..7bd0a15
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_mprf.sv
@@ -0,0 +1,83 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_pipe_mprf.sv>
+/// @brief      Multi Port Register File (MPRF)
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_arch_types.svh"
+
+module scr1_pipe_mprf (
+    // Common
+`ifdef SCR1_MPRF_RST_EN
+    input   logic                               rst_n,
+`endif // SCR1_MPRF_RST_EN
+    input   logic                               clk,
+
+    // EXU <-> MPRF interface
+    input   logic [`SCR1_MPRF_ADDR_WIDTH-1:0]   exu2mprf_rs1_addr,       // MPRF rs1 read address
+    output  logic [`SCR1_XLEN-1:0]              mprf2exu_rs1_data,       // MPRF rs1 read data
+    input   logic [`SCR1_MPRF_ADDR_WIDTH-1:0]   exu2mprf_rs2_addr,       // MPRF rs2 read address
+    output  logic [`SCR1_XLEN-1:0]              mprf2exu_rs2_data,       // MPRF rs2 read data
+    input   logic                               exu2mprf_w_req,          // MPRF write request
+    input   logic [`SCR1_MPRF_ADDR_WIDTH-1:0]   exu2mprf_rd_addr,        // MPRF rd write address
+    input   logic [`SCR1_XLEN-1:0]              exu2mprf_rd_data         // MPRF rd write data
+);
+
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+`ifdef SCR1_RVE_EXT
+type_scr1_mprf_v [1:15]     mprf_int;
+`else // ~SCR1_RVE_EXT
+type_scr1_mprf_v [1:31]     mprf_int;
+`endif // ~SCR1_RVE_EXT
+
+//-------------------------------------------------------------------------------
+// Read MPRF
+//-------------------------------------------------------------------------------
+assign mprf2exu_rs1_data = (|exu2mprf_rs1_addr) ? mprf_int[exu2mprf_rs1_addr] : '0;
+assign mprf2exu_rs2_data = (|exu2mprf_rs2_addr) ? mprf_int[exu2mprf_rs2_addr] : '0;
+
+//-------------------------------------------------------------------------------
+// Write MPRF
+//-------------------------------------------------------------------------------
+`ifdef SCR1_MPRF_RST_EN
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        mprf_int <= '0;
+    end else begin
+        if (exu2mprf_w_req & |exu2mprf_rd_addr) begin
+            mprf_int[exu2mprf_rd_addr] <= exu2mprf_rd_data;
+        end
+    end
+end
+
+`else // SCR1_MPRF_RST_EN
+
+always_ff @(posedge clk) begin
+    if (exu2mprf_w_req & |exu2mprf_rd_addr) begin
+        mprf_int[exu2mprf_rd_addr] <= exu2mprf_rd_data;
+    end
+end
+
+`endif // SCR1_MPRF_RST_EN
+
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+`ifdef SCR1_MPRF_RST_EN
+SCR1_SVA_MPRF_WRITEX : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    exu2mprf_w_req |-> !$isunknown({exu2mprf_rd_addr, (|exu2mprf_rd_addr ? exu2mprf_rd_data : `SCR1_XLEN'd0)})
+    ) else $error("MPRF error: unknown values");
+`endif // SCR1_MPRF_RST_EN
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_mprf
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_tdu.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_tdu.sv
new file mode 100644
index 0000000..634c897
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_tdu.sv
@@ -0,0 +1,479 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_pipe_tdu.sv>
+/// @brief      Trigger Debug Unit (TDU)
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_BRKM_EN
+`include "scr1_riscv_isa_decoding.svh"
+`include "scr1_tdu.svh"
+
+module scr1_pipe_tdu (
+    // Common signals
+    input  logic                                            rst_n,              // TDU reset
+    input  logic                                            clk,                // TDU clock
+    input  logic                                            clk_en,             // TDU clock enable
+    input  logic                                            dsbl,               // TDU Disable
+    // CSR I/F
+    input  logic                                            csr2tdu_req,        // CSR-TDU i/f request
+    input  type_scr1_csr_cmd_sel_e                          csr2tdu_cmd,        // CSR-TDU i/f command
+    input  logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0]             csr2tdu_addr,       // CSR-TDU i/f address
+    input  logic [SCR1_TDU_DATA_W-1:0]                      csr2tdu_wdata,      // CSR-TDU i/f write data
+    output logic [SCR1_TDU_DATA_W-1:0]                      csr2tdu_rdata,      // CSR-TDU i/f read data
+    output type_scr1_csr_resp_e                             csr2tdu_resp,       // CSR-TDU i/f response
+    // ID I/F
+    input  type_scr1_brkm_instr_mon_s                       exu2tdu_i_mon,      // Instruction stream monitoring
+    // CFU I/F
+    output logic [SCR1_TDU_ALLTRIG_NUM-1 : 0]               tdu2exu_i_match,    // Instruction BP match
+    output logic                                            tdu2exu_i_x_req,    // Instruction BP exception request
+    // LSU I/F
+`ifndef SCR1_BRKM_EN
+    output logic                                            tdu2lsu_brk_en,     // TDU-LSU Breakpoint enable
+`endif // SCR1_BRKM_EN
+    output logic                                            tdu2lsu_i_x_req,    // TDU-LSU Instruction BP exception request
+    input  type_scr1_brkm_lsu_mon_s                         tdu2lsu_d_mon,      // TDU-LSU Data address stream monitoring
+    output logic [SCR1_TDU_MTRIG_NUM-1 : 0]                 tdu2lsu_d_match,    // TDU-LSU Data BP match
+    output logic                                            tdu2lsu_d_x_req,    // TDU-LSU Data BP exception request
+    // WB I/F
+    input  logic [SCR1_TDU_ALLTRIG_NUM-1 : 0]               exu2tdu_bp_retire,  // Map of BPs being retired
+    // EPU I/F
+    output logic                                            tdu2hdu_dmode_req   // Debug Mode redirection request
+);
+
+localparam int unsigned MTRIG_NUM   = SCR1_TDU_MTRIG_NUM;
+localparam int unsigned ALLTRIG_NUM = SCR1_TDU_ALLTRIG_NUM;
+localparam int unsigned ALLTRIG_W   = $clog2(ALLTRIG_NUM);
+
+logic [ALLTRIG_W-1:0]                           tselect_ff;
+logic [MTRIG_NUM-1:0] [SCR1_TDU_DATA_W-1:0]     tdata2;
+
+logic                                           csr_addr_tselect_cmb;
+logic [MTRIG_NUM-1:0]                           csr_addr_mcontrol_cmb;
+logic [MTRIG_NUM-1:0]                           csr_addr_tdata2_cmb;
+logic                                           csr_wr_cmb;
+logic [SCR1_TDU_DATA_W-1:0]                     csr_wr_data_cmb;
+
+logic [MTRIG_NUM-1:0]                           clk_en_mcontrol_cmb;
+logic [MTRIG_NUM-1:0]                           mcontrol_dmode_ff;
+logic [MTRIG_NUM-1:0]                           mcontrol_execution_hit_cmb;
+logic [MTRIG_NUM-1:0]                           mcontrol_ldst_hit_cmb;
+logic [MTRIG_NUM-1:0]                           mcontrol_action_ff;
+logic [MTRIG_NUM-1:0] [1:0]                     mcontrol_match_ff;
+logic [MTRIG_NUM-1:0]                           mcontrol_hit_ff;
+logic [MTRIG_NUM-1:0]                           mcontrol_m_ff;
+logic [MTRIG_NUM-1:0]                           mcontrol_execution_ff;
+logic [MTRIG_NUM-1:0]                           mcontrol_load_ff;
+logic [MTRIG_NUM-1:0]                           mcontrol_store_ff;
+logic [MTRIG_NUM-1:0]                           mcontrol_write_en;
+
+genvar                                          gvar_trig;
+
+`ifdef SCR1_BRKM_BRKPT_ICOUNT_EN
+logic                                           csr_addr_icount_cmb;
+
+logic                                           clk_en_icount_cmb;
+logic                                           icount_decrement_cmb;
+logic                                           icount_hit_cmb;
+logic                                           icount_skip_ff;
+logic                                           icount_dmode_ff;
+logic                                           icount_action_ff;
+logic                                           icount_hit_ff;
+logic                                           icount_m_ff;
+logic [SCR1_TDU_ICOUNT_COUNT_HI-SCR1_TDU_ICOUNT_COUNT_LO:0]
+                                                icount_count_ff;
+
+logic                                           icount_write_en;
+`endif // SCR1_BRKM_BRKPT_ICOUNT_EN
+
+// CSR interface
+// -------------
+
+always_comb begin
+    csr_addr_tselect_cmb      = 1'b0;
+    csr_addr_tdata2_cmb       = 1'b0;
+    csr_addr_mcontrol_cmb     = 1'b0;
+
+`ifdef SCR1_BRKM_BRKPT_ICOUNT_EN
+    csr_addr_icount_cmb       = 1'b0;
+`endif // SCR1_BRKM_BRKPT_ICOUNT_EN
+
+    csr_wr_cmb            = 1'b0;
+    csr_wr_data_cmb       = 1'b0;
+
+    csr2tdu_rdata         = 1'b0;
+    csr2tdu_resp          = SCR1_CSR_RESP_ER;
+
+    if( csr2tdu_req ) begin
+        csr2tdu_resp = SCR1_CSR_RESP_OK;
+
+        // Access enable
+        if( csr2tdu_addr == SCR1_CSR_ADDR_TDU_OFFS_TSELECT ) begin
+            csr_addr_tselect_cmb = 1'b1;
+            // Read data
+            csr2tdu_rdata        = tselect_ff;
+        end
+        if( csr2tdu_addr == SCR1_CSR_ADDR_TDU_OFFS_TDATA2 ) begin
+            for( int unsigned i = 0; i < MTRIG_NUM; ++i ) begin
+                if( tselect_ff == i ) begin
+                    csr_addr_tdata2_cmb[i] = 1'b1;
+                    // Read data
+                    csr2tdu_rdata          = tdata2[ i ];
+                end
+            end
+        end
+        if( csr2tdu_addr == SCR1_CSR_ADDR_TDU_OFFS_TDATA1 ) begin
+            for( int unsigned i = 0; i < MTRIG_NUM; ++i ) begin
+                if( tselect_ff == i ) begin
+                    csr_addr_mcontrol_cmb[ i ] = 1'b1;
+                    // Read data
+                    csr2tdu_rdata[ SCR1_TDU_TDATA1_TYPE_HI:
+                                   SCR1_TDU_TDATA1_TYPE_LO ]      = SCR1_TDU_MCONTROL_TYPE_VAL;
+                    csr2tdu_rdata[ SCR1_TDU_TDATA1_DMODE ]        = mcontrol_dmode_ff[ i ];
+
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_MASKMAX_HI:
+                                   SCR1_TDU_MCONTROL_MASKMAX_LO ] = SCR1_TDU_MCONTROL_MASKMAX_VAL;
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_HIT ]        = mcontrol_hit_ff[ i ];
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_SELECT ]     = SCR1_TDU_MCONTROL_SELECT_VAL;
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_TIMING ]     = SCR1_TDU_MCONTROL_TIMING_VAL;
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_ACTION_HI:
+                                   SCR1_TDU_MCONTROL_ACTION_LO ]  = mcontrol_action_ff[ i ];
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_CHAIN ]      = 1'b0;
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_MATCH_HI:
+                                   SCR1_TDU_MCONTROL_MATCH_LO ]   = 1'b0;
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_M ]          = mcontrol_m_ff[ i ];
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_RESERVEDA ]  = SCR1_TDU_MCONTROL_RESERVEDA_VAL;
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_S ]          = 1'b0;
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_U ]          = 1'b0;
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_EXECUTE ]    = mcontrol_execution_ff[ i ];
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_STORE ]      = mcontrol_store_ff[ i ];
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_LOAD ]       = mcontrol_load_ff[ i ];
+                end
+            end
+`ifdef SCR1_BRKM_BRKPT_ICOUNT_EN
+            if( tselect_ff == (SCR1_TDU_ALLTRIG_NUM - 1'b1) ) begin
+                csr_addr_icount_cmb = 1'b1;
+                // Read data
+                csr2tdu_rdata[ SCR1_TDU_TDATA1_TYPE_HI:
+                               SCR1_TDU_TDATA1_TYPE_LO ]      = SCR1_TDU_ICOUNT_TYPE_VAL;
+                csr2tdu_rdata[ SCR1_TDU_TDATA1_DMODE ]        = icount_dmode_ff;
+
+                csr2tdu_rdata[ SCR1_TDU_ICOUNT_HIT ]          = icount_hit_ff;
+                csr2tdu_rdata[ SCR1_TDU_ICOUNT_COUNT_HI:
+                               SCR1_TDU_ICOUNT_COUNT_LO ]     = icount_count_ff;
+                csr2tdu_rdata[ SCR1_TDU_ICOUNT_U ]            = 1'b0;
+                csr2tdu_rdata[ SCR1_TDU_ICOUNT_S ]            = 1'b0;
+                csr2tdu_rdata[ SCR1_TDU_ICOUNT_M ]            = icount_m_ff;
+                csr2tdu_rdata[ SCR1_TDU_ICOUNT_ACTION_HI:
+                               SCR1_TDU_ICOUNT_ACTION_LO ]    = icount_action_ff;
+            end
+`endif // SCR1_BRKM_BRKPT_ICOUNT_EN
+        end
+        if( csr2tdu_addr == SCR1_CSR_ADDR_TDU_OFFS_TINFO ) begin
+            for( int unsigned i = 0; i < MTRIG_NUM; ++i ) begin
+                if( tselect_ff == i ) begin
+                    // Read data
+                    csr2tdu_rdata[ SCR1_TDU_MCONTROL_TYPE_VAL ] = 1'b1;
+                end
+            end
+`ifdef SCR1_BRKM_BRKPT_ICOUNT_EN
+            if( tselect_ff == (SCR1_TDU_ALLTRIG_NUM - 1'b1) ) begin
+                // Read data
+                csr2tdu_rdata[ SCR1_TDU_ICOUNT_TYPE_VAL ] = 1'b1;
+            end
+`endif // SCR1_BRKM_BRKPT_ICOUNT_EN
+        end
+
+        // Write data
+        if( csr2tdu_cmd == SCR1_CSR_CMD_WRITE ) begin
+            csr_wr_cmb      = 1'b1;
+            csr_wr_data_cmb = csr2tdu_wdata;
+        end
+        if( csr2tdu_cmd == SCR1_CSR_CMD_SET ) begin
+            csr_wr_cmb      = |csr2tdu_wdata;
+            csr_wr_data_cmb = csr2tdu_rdata | csr2tdu_wdata;
+        end
+        if( csr2tdu_cmd == SCR1_CSR_CMD_CLEAR ) begin
+            csr_wr_cmb      = |csr2tdu_wdata;
+            csr_wr_data_cmb = csr2tdu_rdata & ~csr2tdu_wdata;
+        end
+    end
+end
+
+// Trigger select
+// --------------
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if( ~rst_n ) begin
+        tselect_ff <= 1'b0;
+    end else if( clk_en ) begin
+        if( csr_addr_tselect_cmb & csr_wr_cmb ) begin
+            if( csr_wr_data_cmb[ALLTRIG_W-1:0] < ALLTRIG_NUM ) begin
+                tselect_ff <= csr_wr_data_cmb[ALLTRIG_W-1:0];
+            end
+        end
+    end
+end
+
+`ifdef SCR1_BRKM_BRKPT_ICOUNT_EN
+// Breakpoint on instruction counter
+// ---------------------------------
+
+// Hit logic
+always_comb begin
+    icount_hit_cmb = 1'b0;
+    icount_decrement_cmb = 1'b0;
+
+    if( ~dsbl ) begin
+        if( icount_m_ff ) begin
+            icount_hit_cmb       = exu2tdu_i_mon.vd & (icount_count_ff == 1'b1) & ~icount_skip_ff;
+            icount_decrement_cmb = exu2tdu_i_mon.vd & (icount_count_ff != 1'b0);
+        end
+    end
+end
+
+// Clock enable logic
+always_comb begin
+    clk_en_icount_cmb = (csr_addr_icount_cmb & csr_wr_cmb) | icount_m_ff;
+end
+
+// Write enable logic for tdata
+always_comb begin
+    icount_write_en = icount_dmode_ff ? dsbl : 1'b1;
+end
+
+// Trigger enable/hit
+always_ff @(negedge rst_n, posedge clk) begin
+    if( ~rst_n ) begin
+        icount_dmode_ff  <= 1'b0;
+        icount_m_ff      <= 1'b0;
+        icount_action_ff <= 1'b0;
+        icount_hit_ff    <= 1'b0;
+        icount_count_ff  <= 1'b0;
+        icount_skip_ff   <= 1'b0;
+    end else if( clk_en ) begin
+        if( clk_en_icount_cmb ) begin
+            if( csr_addr_icount_cmb & csr_wr_cmb & icount_write_en ) begin
+                icount_dmode_ff <= csr_wr_data_cmb[SCR1_TDU_TDATA1_DMODE];
+                icount_m_ff <= csr_wr_data_cmb[ SCR1_TDU_ICOUNT_M ];
+                icount_action_ff <= csr_wr_data_cmb[SCR1_TDU_ICOUNT_ACTION_HI:SCR1_TDU_ICOUNT_ACTION_LO] == 1'b1;
+            end
+
+            if( csr_addr_icount_cmb & csr_wr_cmb & icount_write_en ) begin
+                icount_hit_ff <= csr_wr_data_cmb[SCR1_TDU_ICOUNT_HIT];
+            end else if( exu2tdu_bp_retire[ALLTRIG_NUM - 1'b1] ) begin
+                icount_hit_ff <= 1'b1;
+            end
+
+            if( csr_addr_icount_cmb & csr_wr_cmb & icount_write_en ) begin
+                icount_count_ff <= csr_wr_data_cmb[SCR1_TDU_ICOUNT_COUNT_HI:SCR1_TDU_ICOUNT_COUNT_LO];
+            end else if( icount_decrement_cmb & exu2tdu_i_mon.req & ~icount_skip_ff ) begin
+                icount_count_ff <= icount_count_ff - 1'b1;
+            end
+
+             // skip scr write instruction to icount trigger
+            if( csr_addr_icount_cmb & csr_wr_cmb ) begin
+                icount_skip_ff <= csr_wr_data_cmb[ SCR1_TDU_ICOUNT_M ];
+            end else if( icount_skip_ff & icount_decrement_cmb & exu2tdu_i_mon.req ) begin
+                icount_skip_ff <= 1'b0;
+            end
+        end
+    end
+end
+`endif // SCR1_BRKM_BRKPT_ICOUNT_EN
+
+// Breakpoint/watchpoint on matching address
+// -----------------------------------------
+
+generate for( gvar_trig = 0; $unsigned(gvar_trig) < MTRIG_NUM; ++gvar_trig ) begin : gblock_mtrig
+
+// Breakpoint hit logic
+always_comb begin
+    mcontrol_execution_hit_cmb[gvar_trig] = 1'b0;
+
+    if( ~dsbl ) begin
+        if( mcontrol_m_ff[gvar_trig] ) begin
+            if(  mcontrol_execution_ff[gvar_trig] ) begin
+
+                mcontrol_execution_hit_cmb[gvar_trig] = exu2tdu_i_mon.vd & exu2tdu_i_mon.addr == tdata2[gvar_trig];
+            end
+        end
+    end
+end
+
+// Watchpoint hit logic
+always_comb begin
+    mcontrol_ldst_hit_cmb[gvar_trig] = 1'b0;
+
+    if( ~dsbl ) begin
+        if( mcontrol_m_ff[gvar_trig] ) begin
+            mcontrol_ldst_hit_cmb[gvar_trig] =  tdu2lsu_d_mon.vd &
+                                                ((mcontrol_load_ff[gvar_trig] & tdu2lsu_d_mon.load) |
+                                                    (mcontrol_store_ff[gvar_trig] & tdu2lsu_d_mon.store)) &
+                                                tdu2lsu_d_mon.addr == tdata2[gvar_trig];
+        end
+    end
+end
+
+// Clock enable logic
+always_comb begin
+    clk_en_mcontrol_cmb[gvar_trig] = (csr_addr_mcontrol_cmb[gvar_trig] & csr_wr_cmb) |
+                                      mcontrol_m_ff[gvar_trig];
+end
+
+// Write enable logic for tdata
+always_comb begin
+    mcontrol_write_en[ gvar_trig ] = mcontrol_dmode_ff[ gvar_trig ] ? dsbl : 1'b1;
+end
+
+// Trigger enable/hit
+always_ff @(negedge rst_n, posedge clk) begin
+    if( ~rst_n ) begin
+        mcontrol_dmode_ff[gvar_trig]     <= 1'b0;
+        mcontrol_m_ff[gvar_trig]         <= 1'b0;
+        mcontrol_execution_ff[gvar_trig] <= 1'b0;
+        mcontrol_load_ff[gvar_trig]      <= 1'b0;
+        mcontrol_store_ff[gvar_trig]     <= 1'b0;
+        mcontrol_action_ff[gvar_trig]    <= 1'b0;
+        mcontrol_hit_ff[gvar_trig]       <= 1'b0;
+    end else if( clk_en ) begin
+        if( clk_en_mcontrol_cmb[gvar_trig] ) begin
+            if( csr_addr_mcontrol_cmb[gvar_trig] & csr_wr_cmb & mcontrol_write_en[ gvar_trig ] ) begin
+                mcontrol_dmode_ff[gvar_trig] <= csr_wr_data_cmb[SCR1_TDU_TDATA1_DMODE];
+
+                // Select privilege mode
+                mcontrol_m_ff[gvar_trig] <= csr_wr_data_cmb[SCR1_TDU_MCONTROL_M];
+
+                // Select type
+                mcontrol_execution_ff[gvar_trig] <= csr_wr_data_cmb[SCR1_TDU_MCONTROL_EXECUTE];
+                mcontrol_load_ff[gvar_trig]      <= csr_wr_data_cmb[SCR1_TDU_MCONTROL_LOAD];
+                mcontrol_store_ff[gvar_trig]     <= csr_wr_data_cmb[SCR1_TDU_MCONTROL_STORE];
+
+                // Select action: dmode/exception
+                mcontrol_action_ff[gvar_trig]    <= csr_wr_data_cmb[SCR1_TDU_MCONTROL_ACTION_HI:SCR1_TDU_MCONTROL_ACTION_LO] == 1'b1;
+
+                // Exact equality is supported only for match type of triggers (zero value)
+                // Chain is not supported
+            end
+
+            // Hit status
+            if( csr_addr_mcontrol_cmb[gvar_trig] & csr_wr_cmb & mcontrol_write_en[ gvar_trig ] ) begin
+                mcontrol_hit_ff[gvar_trig] <= csr_wr_data_cmb[SCR1_TDU_MCONTROL_HIT];
+            end else if( exu2tdu_bp_retire[gvar_trig] ) begin
+                mcontrol_hit_ff[gvar_trig] <= 1'b1;
+            end
+        end
+    end
+end
+
+// Etalon address/border
+always_ff @(posedge clk) begin
+    if( clk_en ) begin
+        if( csr_addr_tdata2_cmb[gvar_trig] & csr_wr_cmb ) begin
+            if( mcontrol_write_en[ gvar_trig ] ) begin
+                tdata2[gvar_trig] <= csr_wr_data_cmb;
+            end
+        end
+    end
+end
+
+end endgenerate // gblock_mtrig
+
+// Pipeline control
+// ----------------
+
+// Breakpoint
+always_comb begin
+    // Invalidate matching instruction in writeback
+    tdu2exu_i_match = mcontrol_execution_hit_cmb;
+
+    // Load/store goes to lsu in parallel with exception
+    // request goes to epu because of that this signal
+    // invalidate load/store in lsu
+    tdu2lsu_i_x_req = |mcontrol_execution_hit_cmb;
+
+    // Generate exception
+    tdu2exu_i_x_req = |mcontrol_execution_hit_cmb;
+
+`ifdef SCR1_BRKM_BRKPT_ICOUNT_EN
+    tdu2exu_i_match[SCR1_TDU_ALLTRIG_NUM-1] = icount_hit_cmb;
+    tdu2lsu_i_x_req = tdu2lsu_i_x_req | icount_hit_cmb;
+    tdu2exu_i_x_req = tdu2exu_i_x_req | icount_hit_cmb;
+`endif // SCR1_BRKM_BRKPT_ICOUNT_EN
+end
+
+// Watchpoint
+always_comb begin
+    // Invalidate matching instruction in writeback
+    tdu2lsu_d_match = mcontrol_ldst_hit_cmb;
+    // Invalidate instruction in lsu
+    tdu2lsu_d_x_req = |mcontrol_ldst_hit_cmb;
+end
+
+// Debug mode request
+always_comb begin
+    tdu2hdu_dmode_req = 1'b0;
+
+    for( int unsigned i = 0; i < MTRIG_NUM; ++i) begin
+        tdu2hdu_dmode_req = tdu2hdu_dmode_req |
+                            (mcontrol_action_ff[i] == 1'b1 & exu2tdu_bp_retire[i]);
+    end
+
+`ifdef SCR1_BRKM_BRKPT_ICOUNT_EN
+    tdu2hdu_dmode_req = tdu2hdu_dmode_req |
+                        (icount_action_ff == 1'b1 & exu2tdu_bp_retire[ALLTRIG_NUM-1]);
+`endif // SCR1_BRKM_BRKPT_ICOUNT_EN
+end
+
+`ifndef SCR1_BRKM_EN
+// LSU debug mode enable (2 clocks on each operation)
+always_comb tdu2lsu_brk_en = (|mcontrol_m_ff) | icount_m_ff;
+`endif // SCR1_BRKM_EN
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+SVA_TDU_X_CONTROL :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown( {rst_n,clk,clk_en,dsbl,csr2tdu_req,exu2tdu_i_mon.vd,tdu2lsu_d_mon.vd,exu2tdu_bp_retire} )
+    )
+    else $error("TDU Error: control signals is X - %0b",{rst_n,clk,clk_en,dsbl,csr2tdu_req,exu2tdu_i_mon.vd,tdu2lsu_d_mon.vd,exu2tdu_bp_retire});
+
+SVA_TDU_X_CSR :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        csr2tdu_req |-> !$isunknown( {csr2tdu_cmd,csr2tdu_addr} )
+    )
+    else $error("TDU Error: csr is X");
+
+SVA_TDU_XW_CSR :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        (csr2tdu_req & csr_wr_cmb) |-> !$isunknown( csr2tdu_wdata )
+    )
+    else $error("TDU Error: csr wdata is X ");
+
+SVA_TDU_X_IMON :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        exu2tdu_i_mon.vd |-> !$isunknown( {exu2tdu_i_mon.req,exu2tdu_i_mon.addr} )
+    )
+    else $error("TDU Error: imonitor is X");
+
+SVA_TDU_X_DMON :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        tdu2lsu_d_mon.vd |-> !$isunknown( {tdu2lsu_d_mon} )
+    )
+    else $error("TDU Error: dmonitor is X");
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_tdu
+
+`endif // SCR1_BRKM_EN
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_pipe_top.sv b/third_party/tests/Scr1/src/pipeline/scr1_pipe_top.sv
new file mode 100644
index 0000000..622e05f
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_pipe_top.sv
@@ -0,0 +1,746 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_pipe_top.sv>
+/// @brief      SCR1 pipeline top
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_memif.svh"
+`include "scr1_riscv_isa_decoding.svh"
+`include "scr1_csr.svh"
+
+`ifdef SCR1_IPIC_EN
+`include "scr1_ipic.svh"
+`endif // SCR1_IPIC_EN
+
+`ifdef SCR1_DBGC_EN
+`include "scr1_hdu.svh"
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_BRKM_EN
+`include "scr1_tdu.svh"
+`endif // SCR1_BRKM_EN
+
+module scr1_pipe_top (
+    // Common
+    input   logic                                       pipe_rst_n,
+`ifdef SCR1_DBGC_EN
+    input  logic                                        pipe_rst_n_qlfy,
+    input  logic                                        dbg_rst_n,
+`endif // SCR1_DBGC_EN
+    input   logic                                       clk,
+
+    // Instruction Memory Interface
+    output  logic                                       imem_req,
+    output  type_scr1_mem_cmd_e                         imem_cmd,
+    output  logic [`SCR1_IMEM_AWIDTH-1:0]               imem_addr,
+    input   logic                                       imem_req_ack,
+    input   logic [`SCR1_IMEM_DWIDTH-1:0]               imem_rdata,
+    input   type_scr1_mem_resp_e                        imem_resp,
+
+    // Data Memory Interface
+    output  logic                                       dmem_req,
+    output  type_scr1_mem_cmd_e                         dmem_cmd,
+    output  type_scr1_mem_width_e                       dmem_width,
+    output  logic [`SCR1_DMEM_AWIDTH-1:0]               dmem_addr,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]               dmem_wdata,
+    input   logic                                       dmem_req_ack,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]               dmem_rdata,
+    input   type_scr1_mem_resp_e                        dmem_resp,
+
+`ifdef SCR1_DBGC_EN
+    // Debug interface:
+    // DM <-> Pipeline: HART Run Control i/f
+    input  logic                                        dm_active,
+    input  logic                                        dm_cmd_req,
+    input  type_scr1_hdu_dbgstates_e                    dm_cmd,
+    output logic                                        dm_cmd_resp,
+    output logic                                        dm_cmd_rcode, // 0 - Ok; 1 - Error
+    output logic                                        dm_hart_event,
+    output type_scr1_hdu_hartstatus_s                   dm_hart_status,
+    // DM <-> Pipeline: Program Buffer - HART instruction execution i/f
+    output logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]         dm_pbuf_addr, // so far request only for 1 instruction
+    input  logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0]        dm_pbuf_instr,
+    // DM <-> Pipeline: HART Abstract Data regs i/f
+    output logic                                        dm_dreg_req,
+    output logic                                        dm_dreg_wr,
+    output logic [`SCR1_XLEN-1:0]                       dm_dreg_wdata,
+    input  logic                                        dm_dreg_resp,
+    input  logic                                        dm_dreg_fail, // ? - possibly not needed
+    input  logic [`SCR1_XLEN-1:0]                       dm_dreg_rdata,
+    //
+    output logic [`SCR1_XLEN-1:0]                       dm_pc_sample,
+`endif // SCR1_DBGC_EN
+
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    input   logic [SCR1_IRQ_LINES_NUM-1:0]              irq_lines,
+`else // SCR1_IPIC_EN
+    input   logic                                       ext_irq,
+`endif // SCR1_IPIC_EN
+    input   logic                                       soft_irq,
+
+    // Memory-mapped external timer
+    input   logic                                       timer_irq,
+    input   logic [63:0]                                mtime_ext,
+
+`ifdef SCR1_CLKCTRL_EN
+    // CLK_CTRL interface
+    output  logic                                       sleep_pipe,
+    output  logic                                       wake_pipe,
+    input   logic                                       clk_alw_on,
+    input   logic                                       clk_dbgc,
+    input   logic                                       clk_pipe_en,
+`endif // SCR1_CLKCTRL_EN
+
+    // Fuse
+    input   logic [`SCR1_XLEN-1:0]                      fuse_mhartid
+);
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+
+// Pipeline control
+logic [`SCR1_XLEN-1:0]                      curr_pc;                // Current PC
+logic [`SCR1_XLEN-1:0]                      next_pc;                // Is written to MEPC on interrupt trap
+logic                                       new_pc_req;             // New PC request (jumps, branches, traps etc)
+logic [`SCR1_XLEN-1:0]                      new_pc;                 // New PC
+
+logic                                       stop_fetch;             // Stop IFU
+logic                                       exu_exc_req;            // Exception request
+logic                                       brkpt;                  // Breakpoint (sw) on current instruction
+logic                                       exu_init_pc;            // Reset exit
+logic                                       wfi_run2halt;           // Transition to WFI halted state
+logic                                       instret;                // Instruction retirement (with or without exception)
+logic                                       instret_nexc;           // Instruction retirement (without exception)
+`ifdef SCR1_IPIC_EN
+logic                                       ext_irq;                // IRQ request from IPIC
+`endif // SCR1_IPIC_EN
+`ifdef SCR1_BRKM_EN
+logic                                       brkpt_hw;               // Hardware breakpoint on current instruction
+`endif // SCR1_BRKM_EN
+`ifdef SCR1_CLKCTRL_EN
+logic                                       imem_txns_pending;      // There are pending imem transactions
+logic                                       wfi_halted;             // WFI halted state
+`endif // SCR1_CLKCTRL_EN
+
+// IFU <-> IDU
+logic                                       ifu2idu_vd;             // IFU request
+logic [`SCR1_IMEM_DWIDTH-1:0]               ifu2idu_instr;          // IFU instruction
+logic                                       ifu2idu_imem_err;       // IFU instruction access fault
+logic                                       ifu2idu_err_rvi_hi;     // 1 - imem fault when trying to fetch second half of an unaligned RVI instruction
+logic                                       idu2ifu_rdy;            // IDU ready for new data
+
+// IDU <-> EXU
+logic                                       idu2exu_req;            // IDU request
+type_scr1_exu_cmd_s                         idu2exu_cmd;            // IDU command (see scr1_riscv_isa_decoding.svh)
+logic                                       idu2exu_use_rs1;        // Instruction uses rs1
+logic                                       idu2exu_use_rs2;        // Instruction uses rs2
+logic                                       idu2exu_use_rd;         // Instruction uses rd
+logic                                       idu2exu_use_imm;        // Instruction uses immediate
+logic                                       exu2idu_rdy;            // EXU ready for new data
+
+// EXU <-> MPRF
+logic [`SCR1_MPRF_ADDR_WIDTH-1:0]           exu2mprf_rs1_addr;      // MPRF rs1 read address
+logic [`SCR1_XLEN-1:0]                      mprf2exu_rs1_data;      // MPRF rs1 read data
+logic [`SCR1_MPRF_ADDR_WIDTH-1:0]           exu2mprf_rs2_addr;      // MPRF rs2 read address
+logic [`SCR1_XLEN-1:0]                      mprf2exu_rs2_data;      // MPRF rs2 read data
+logic                                       exu2mprf_w_req;         // MPRF write request
+logic [`SCR1_MPRF_ADDR_WIDTH-1:0]           exu2mprf_rd_addr;       // MPRF rd write address
+logic [`SCR1_XLEN-1:0]                      exu2mprf_rd_data;       // MPRF rd write data
+
+// EXU <-> CSR
+logic [SCR1_CSR_ADDR_WIDTH-1:0]             exu2csr_rw_addr;        // CSR read/write address
+logic                                       exu2csr_r_req;          // CSR read request
+logic [`SCR1_XLEN-1:0]                      csr2exu_r_data;         // CSR read data
+logic                                       exu2csr_w_req;          // CSR write request
+type_scr1_csr_cmd_sel_e                     exu2csr_w_cmd;          // CSR write command
+logic [`SCR1_XLEN-1:0]                      exu2csr_w_data;         // CSR write data
+logic                                       csr2exu_rw_exc;         // CSR read/write access exception
+
+// EXU <-> CSR event interface
+logic                                       exu2csr_take_irq;       // Take IRQ trap
+logic                                       exu2csr_take_exc;       // Take exception trap
+logic                                       exu2csr_mret_update;    // MRET update CSR
+logic                                       exu2csr_mret_instr;     // MRET instruction
+type_scr1_exc_code_e                        exu2csr_exc_code;       // Exception code (see scr1_arch_types.svh)
+logic [`SCR1_XLEN-1:0]                      exu2csr_trap_val;       // Trap value
+logic [`SCR1_XLEN-1:0]                      csr2exu_new_pc;         // Exception/IRQ/MRET new PC
+logic                                       csr2exu_irq;            // IRQ request
+logic                                       csr2exu_ip_ie;          // Some IRQ pending and locally enabled
+logic                                       csr2exu_mstatus_mie_up; // MSTATUS or MIE update in the current cycle
+
+`ifdef SCR1_IPIC_EN
+// CSR <-> IPIC
+logic                                       csr2ipic_r_req;         // IPIC read request
+logic                                       csr2ipic_w_req;         // IPIC write request
+logic [2:0]                                 csr2ipic_addr;          // IPIC address
+logic [`SCR1_XLEN-1:0]                      csr2ipic_wdata;         // IPIC write data
+logic [`SCR1_XLEN-1:0]                      ipic2csr_rdata;         // IPIC read data
+`endif // SCR1_IPIC_EN
+
+`ifdef SCR1_BRKM_EN
+// CSR <-> TDU
+logic                                       csr2tdu_req;           // Request to TDU
+type_scr1_csr_cmd_sel_e                     csr2tdu_cmd;           // TDU command
+logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0]        csr2tdu_addr;          // TDU address
+logic [`SCR1_XLEN-1:0]                      csr2tdu_wdata;         // TDU write data
+logic [`SCR1_XLEN-1:0]                      tdu2csr_rdata;         // TDU read data
+type_scr1_csr_resp_e                        tdu2csr_resp;          // TDU response
+ `ifdef SCR1_DBGC_EN
+                                                                    // Qualified TDU input signals from pipe_rst_n
+                                                                    // reset domain:
+logic                                       csr2tdu_req_qlfy;      //     Request to TDU
+type_scr1_csr_cmd_sel_e                     csr2tdu_cmd_qlfy;      //     TDU command
+logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0]        csr2tdu_addr_qlfy;     //     TDU address
+logic [`SCR1_XLEN-1:0]                      csr2tdu_wdata_qlfy;    //     TDU write data
+ `endif // SCR1_DBGC_EN
+
+// EXU/LSU <-> TDU
+type_scr1_brkm_instr_mon_s                  exu2tdu_i_mon;         // Instruction monitor
+type_scr1_brkm_lsu_mon_s                    lsu2tdu_d_mon;         // Data monitor
+logic [SCR1_TDU_ALLTRIG_NUM-1:0]            tdu2exu_i_match;       // Instruction breakpoint(s) match
+logic [SCR1_TDU_MTRIG_NUM-1:0]              tdu2lsu_d_match;       // Data breakpoint(s) match
+logic                                       tdu2exu_i_x_req;       // Instruction breakpoint exception
+logic                                       tdu2lsu_i_x_req;       // Instruction breakpoint exception
+logic                                       tdu2lsu_d_x_req;       // Data breakpoint exception
+logic [SCR1_TDU_ALLTRIG_NUM-1:0]            exu2tdu_bp_retire;     // Instruction with breakpoint flag retire
+ `ifdef SCR1_DBGC_EN
+                                                                    // Qualified TDU input signals from pipe_rst_n
+                                                                    // reset domain:
+type_scr1_brkm_instr_mon_s                  exu2tdu_i_mon_qlfy;         // Instruction monitor
+type_scr1_brkm_lsu_mon_s                    lsu2tdu_d_mon_qlfy;         // Data monitor
+logic [SCR1_TDU_ALLTRIG_NUM-1:0]            exu2tdu_bp_retire_qlfy;     // Instruction with breakpoint flag retire
+ `endif // SCR1_DBGC_EN
+`endif // SCR1_BRKM_EN
+
+`ifdef SCR1_DBGC_EN
+// Debug signals:
+logic                                       fetch_pbuf;             // Fetch instructions provided by Program Buffer (via HDU)
+logic                                       csr2hdu_req;            // Request to HDU
+type_scr1_csr_cmd_sel_e                     csr2hdu_cmd;            // HDU command
+logic [SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0]    csr2hdu_addr;           // HDU address
+logic [`SCR1_XLEN-1:0]                      csr2hdu_wdata;          // HDU write data
+logic [`SCR1_XLEN-1:0]                      hdu2csr_rdata;          // HDU read data
+type_scr1_csr_resp_e                        hdu2csr_resp;           // HDU response
+                                                                    // Qualified HDU input signals from pipe_rst_n
+                                                                    // reset domain:
+logic                                       csr2hdu_req_qlfy;       //     Request to HDU
+type_scr1_csr_cmd_sel_e                     csr2hdu_cmd_qlfy;       //     HDU command
+logic [SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0]    csr2hdu_addr_qlfy;      //     HDU address
+logic [`SCR1_XLEN-1:0]                      csr2hdu_wdata_qlfy;     //     HDU write data
+
+logic                                       hwbrk_dsbl;             // Disables TDU
+logic                                       tdu2hdu_dmode_req;      // TDU requests transition to debug mode
+
+logic                                       exu_no_commit;          // Forbid instruction commitment
+logic                                       exu_irq_dsbl;           // Disable IRQ
+logic                                       exu_pc_advmt_dsbl;      // Forbid PC advancement
+logic                                       exu_dmode_sstep_en;     // Enable single-step
+
+logic                                       dbg_halted;             // Debug halted state
+logic                                       dbg_run2halt;           // Transition to debug halted state
+logic                                       dbg_halt2run;           // Transition to run state
+logic                                       dbg_run_start;          // First cycle of run state
+logic [`SCR1_XLEN-1:0]                      dbg_new_pc;             // New PC as starting point for HART Resume
+
+logic                                       ifu2hdu_pbuf_rdy;
+logic                                       hdu2ifu_pbuf_vd;
+logic                                       hdu2ifu_pbuf_err;
+logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0]       hdu2ifu_pbuf_instr;
+
+// Qualified HDU input signals from pipe_rst_n reset domain:
+logic                                       ifu2hdu_pbuf_rdy_qlfy;
+logic                                       exu_busy;
+logic                                       exu_busy_qlfy;
+logic                                       instret_qlfy;
+logic                                       exu_init_pc_qlfy;
+logic                                       exu_exc_req_qlfy;
+logic                                       brkpt_qlfy;
+logic [`SCR1_XLEN-1:0]                      curr_pc_qlfy;
+
+`endif // SCR1_DBGC_EN
+
+
+//-------------------------------------------------------------------------------
+// Pipeline logic
+//-------------------------------------------------------------------------------
+assign stop_fetch   = wfi_run2halt
+`ifdef SCR1_DBGC_EN
+                    | fetch_pbuf
+`endif // SCR1_DBGC_EN
+                    ;
+
+`ifdef SCR1_CLKCTRL_EN
+assign sleep_pipe   = wfi_halted & ~imem_txns_pending;
+assign wake_pipe    = csr2exu_ip_ie
+`ifdef SCR1_DBGC_EN
+                    | dm_active
+`endif // SCR1_DBGC_EN
+                    ;
+`endif // SCR1_CLKCTRL_EN
+
+`ifdef SCR1_DBGC_EN
+assign dm_pc_sample = curr_pc;
+`endif // SCR1_DBGC_EN
+
+//-------------------------------------------------------------------------------
+// Instruction fetch unit
+//-------------------------------------------------------------------------------
+scr1_pipe_ifu i_pipe_ifu (
+    .rst_n              (pipe_rst_n         ),
+    .clk                (clk                ),
+
+    .imem_req_ack       (imem_req_ack       ),
+    .imem_req           (imem_req           ),
+    .imem_cmd           (imem_cmd           ),
+    .imem_addr          (imem_addr          ),
+    .imem_rdata         (imem_rdata         ),
+    .imem_resp          (imem_resp          ),
+
+    .new_pc             (new_pc             ),
+    .new_pc_req         (new_pc_req         ),
+    .stop_fetch         (stop_fetch         ),
+`ifdef SCR1_DBGC_EN
+    .fetch_pbuf         (fetch_pbuf         ),
+    .ifu2hdu_pbuf_rdy   (ifu2hdu_pbuf_rdy   ),
+    .hdu2ifu_pbuf_vd    (hdu2ifu_pbuf_vd    ),
+    .hdu2ifu_pbuf_err   (hdu2ifu_pbuf_err   ),
+    .hdu2ifu_pbuf_instr (hdu2ifu_pbuf_instr ),
+`endif // SCR1_DBGC_EN
+`ifdef SCR1_CLKCTRL_EN
+    .imem_txns_pending  (imem_txns_pending  ),
+`endif // SCR1_CLKCTRL_EN
+    .idu2ifu_rdy        (idu2ifu_rdy        ),
+    .ifu2idu_instr      (ifu2idu_instr      ),
+    .ifu2idu_imem_err   (ifu2idu_imem_err   ),
+    .ifu2idu_err_rvi_hi (ifu2idu_err_rvi_hi ),
+    .ifu2idu_vd         (ifu2idu_vd         )
+);
+
+//-------------------------------------------------------------------------------
+// Instruction decode unit
+//-------------------------------------------------------------------------------
+scr1_pipe_idu i_pipe_idu (
+`ifdef SCR1_SIM_ENV
+    .rst_n              (pipe_rst_n         ),
+    .clk                (clk                ),
+`endif // SCR1_SIM_ENV
+    .idu2ifu_rdy        (idu2ifu_rdy        ),
+    .ifu2idu_instr      (ifu2idu_instr      ),
+    .ifu2idu_imem_err   (ifu2idu_imem_err   ),
+    .ifu2idu_err_rvi_hi (ifu2idu_err_rvi_hi ),
+    .ifu2idu_vd         (ifu2idu_vd         ),
+
+    .idu2exu_req        (idu2exu_req        ),
+    .idu2exu_cmd        (idu2exu_cmd        ),
+    .idu2exu_use_rs1    (idu2exu_use_rs1    ),
+    .idu2exu_use_rs2    (idu2exu_use_rs2    ),
+    .idu2exu_use_rd     (idu2exu_use_rd     ),
+    .idu2exu_use_imm    (idu2exu_use_imm    ),
+    .exu2idu_rdy        (exu2idu_rdy        )
+);
+
+//-------------------------------------------------------------------------------
+// Execution unit
+//-------------------------------------------------------------------------------
+scr1_pipe_exu i_pipe_exu (
+    .rst_n                  (pipe_rst_n           ),
+    .clk                    (clk                  ),
+`ifdef SCR1_CLKCTRL_EN
+    .clk_alw_on             (clk_alw_on           ),
+    .clk_pipe_en            (clk_pipe_en          ),
+`endif // SCR1_CLKCTRL_EN
+    .idu2exu_req            (idu2exu_req          ),
+    .exu2idu_rdy            (exu2idu_rdy          ),
+    .idu2exu_cmd            (idu2exu_cmd          ),
+    .idu2exu_use_rs1        (idu2exu_use_rs1      ),
+    .idu2exu_use_rs2        (idu2exu_use_rs2      ),
+`ifndef SCR1_EXU_STAGE_BYPASS
+    .idu2exu_use_rd         (idu2exu_use_rd       ),
+    .idu2exu_use_imm        (idu2exu_use_imm      ),
+`endif // SCR1_EXU_STAGE_BYPASS
+
+    .exu2mprf_rs1_addr      (exu2mprf_rs1_addr    ),
+    .mprf2exu_rs1_data      (mprf2exu_rs1_data    ),
+    .exu2mprf_rs2_addr      (exu2mprf_rs2_addr    ),
+    .mprf2exu_rs2_data      (mprf2exu_rs2_data    ),
+    .exu2mprf_w_req         (exu2mprf_w_req       ),
+    .exu2mprf_rd_addr       (exu2mprf_rd_addr     ),
+    .exu2mprf_rd_data       (exu2mprf_rd_data     ),
+
+    .exu2csr_rw_addr        (exu2csr_rw_addr      ),
+    .exu2csr_r_req          (exu2csr_r_req        ),
+    .csr2exu_r_data         (csr2exu_r_data       ),
+    .exu2csr_w_req          (exu2csr_w_req        ),
+    .exu2csr_w_cmd          (exu2csr_w_cmd        ),
+    .exu2csr_w_data         (exu2csr_w_data       ),
+    .csr2exu_rw_exc         (csr2exu_rw_exc       ),
+    .exu2csr_take_irq       (exu2csr_take_irq     ),
+    .exu2csr_take_exc       (exu2csr_take_exc     ),
+    .exu2csr_mret_update    (exu2csr_mret_update  ),
+    .exu2csr_mret_instr     (exu2csr_mret_instr   ),
+    .exu2csr_exc_code       (exu2csr_exc_code     ),
+    .exu2csr_trap_val       (exu2csr_trap_val     ),
+    .csr2exu_new_pc         (csr2exu_new_pc       ),
+    .csr2exu_irq            (csr2exu_irq          ),
+    .csr2exu_ip_ie          (csr2exu_ip_ie        ),
+    .csr2exu_mstatus_mie_up (csr2exu_mstatus_mie_up),
+
+    .exu2dmem_req           (dmem_req             ),
+    .exu2dmem_cmd           (dmem_cmd             ),
+    .exu2dmem_width         (dmem_width           ),
+    .exu2dmem_addr          (dmem_addr            ),
+    .exu2dmem_wdata         (dmem_wdata           ),
+    .dmem2exu_req_ack       (dmem_req_ack         ),
+    .dmem2exu_rdata         (dmem_rdata           ),
+    .dmem2exu_resp          (dmem_resp            ),
+`ifdef SCR1_DBGC_EN
+    .exu_no_commit          (exu_no_commit        ),
+    .exu_irq_dsbl           (exu_irq_dsbl         ),
+    .exu_pc_advmt_dsbl      (exu_pc_advmt_dsbl    ),
+    .exu_dmode_sstep_en     (exu_dmode_sstep_en   ),
+    .fetch_pbuf             (fetch_pbuf           ),
+    .dbg_halted             (dbg_halted           ),
+    .dbg_run2halt           (dbg_run2halt         ),
+    .dbg_halt2run           (dbg_halt2run         ),
+    .dbg_run_start          (dbg_run_start        ),
+    .dbg_new_pc             (dbg_new_pc           ),
+`endif // SCR1_DBGC_EN
+`ifdef SCR1_BRKM_EN
+    .exu2tdu_i_mon          (exu2tdu_i_mon        ),
+    .tdu2exu_i_match        (tdu2exu_i_match      ),
+    .tdu2exu_i_x_req        (tdu2exu_i_x_req      ),
+    .lsu2tdu_d_mon          (lsu2tdu_d_mon        ),
+    .tdu2lsu_i_x_req        (tdu2lsu_i_x_req      ),
+    .tdu2lsu_d_match        (tdu2lsu_d_match      ),
+    .tdu2lsu_d_x_req        (tdu2lsu_d_x_req      ),
+    .exu2tdu_bp_retire      (exu2tdu_bp_retire    ),
+    .brkpt_hw               (brkpt_hw             ),
+`endif // SCR1_BRKM_EN
+    .brkpt                  (brkpt                ),
+    .exu_exc_req            (exu_exc_req          ),
+    .exu_init_pc            (exu_init_pc          ),
+    .wfi_run2halt           (wfi_run2halt         ),
+    .instret                (instret              ),
+    .instret_nexc           (instret_nexc         ),
+`ifdef SCR1_CLKCTRL_EN
+    .wfi_halted             (wfi_halted           ),
+`endif // SCR1_CLKCTRL_EN
+    .curr_pc                (curr_pc              ),
+    .next_pc                (next_pc              ),
+    .new_pc_req             (new_pc_req           ),
+    .new_pc                 (new_pc               ),
+
+    .exu_busy               (exu_busy             )
+);
+
+//-------------------------------------------------------------------------------
+// Multi-port register file
+//-------------------------------------------------------------------------------
+scr1_pipe_mprf i_pipe_mprf (
+`ifdef SCR1_MPRF_RST_EN
+    .rst_n                  (pipe_rst_n       ),
+`endif // SCR1_MPRF_RST_EN
+    .clk                    (clk              ),
+    .exu2mprf_rs1_addr      (exu2mprf_rs1_addr),
+    .mprf2exu_rs1_data      (mprf2exu_rs1_data),
+    .exu2mprf_rs2_addr      (exu2mprf_rs2_addr),
+    .mprf2exu_rs2_data      (mprf2exu_rs2_data),
+    .exu2mprf_w_req         (exu2mprf_w_req   ),
+    .exu2mprf_rd_addr       (exu2mprf_rd_addr ),
+    .exu2mprf_rd_data       (exu2mprf_rd_data )
+);
+
+//-------------------------------------------------------------------------------
+// Control and status registers
+//-------------------------------------------------------------------------------
+scr1_pipe_csr i_pipe_csr (
+    .rst_n                  (pipe_rst_n         ),
+    .clk                    (clk                ),
+`ifdef SCR1_CLKCTRL_EN
+    .clk_alw_on             (clk_alw_on         ),
+`endif // SCR1_CLKCTRL_EN
+
+    .exu2csr_r_req          (exu2csr_r_req      ),
+    .exu2csr_rw_addr        (exu2csr_rw_addr    ),
+    .csr2exu_r_data         (csr2exu_r_data     ),
+    .exu2csr_w_req          (exu2csr_w_req      ),
+    .exu2csr_w_cmd          (exu2csr_w_cmd      ),
+    .exu2csr_w_data         (exu2csr_w_data     ),
+    .csr2exu_rw_exc         (csr2exu_rw_exc     ),
+
+    .exu2csr_take_irq       (exu2csr_take_irq   ),
+    .exu2csr_take_exc       (exu2csr_take_exc   ),
+    .exu2csr_mret_update    (exu2csr_mret_update),
+    .exu2csr_mret_instr     (exu2csr_mret_instr ),
+`ifdef SCR1_DBGC_EN
+    .exu_no_commit          (exu_no_commit      ),
+`endif // SCR1_DBGC_EN
+    .exu2csr_exc_code       (exu2csr_exc_code   ),
+    .exu2csr_trap_val       (exu2csr_trap_val   ),
+    .csr2exu_new_pc         (csr2exu_new_pc     ),
+    .csr2exu_irq            (csr2exu_irq        ),
+    .csr2exu_ip_ie          (csr2exu_ip_ie      ),
+    .csr2exu_mstatus_mie_up (csr2exu_mstatus_mie_up),
+`ifdef SCR1_IPIC_EN
+    .csr2ipic_r_req         (csr2ipic_r_req     ),
+    .csr2ipic_w_req         (csr2ipic_w_req     ),
+    .csr2ipic_addr          (csr2ipic_addr      ),
+    .csr2ipic_wdata         (csr2ipic_wdata     ),
+    .ipic2csr_rdata         (ipic2csr_rdata     ),
+`endif // SCR1_IPIC_EN
+    .curr_pc                (curr_pc            ),
+    .next_pc                (next_pc            ),
+`ifndef SCR1_CSR_REDUCED_CNT
+    .instret_nexc           (instret_nexc       ),
+`endif // SCR1_CSR_REDUCED_CNT
+    .ext_irq                (ext_irq            ),
+    .soft_irq               (soft_irq           ),
+    .timer_irq              (timer_irq          ),
+    .mtime_ext              (mtime_ext          ),
+`ifdef SCR1_DBGC_EN
+    // CSR <-> HDU interface
+    .csr2hdu_req            (csr2hdu_req        ),
+    .csr2hdu_cmd            (csr2hdu_cmd        ),
+    .csr2hdu_addr           (csr2hdu_addr       ),
+    .csr2hdu_wdata          (csr2hdu_wdata      ),
+    .hdu2csr_rdata          (hdu2csr_rdata      ),
+    .hdu2csr_resp           (hdu2csr_resp       ),
+`endif // SCR1_DBGC_EN
+`ifdef SCR1_BRKM_EN
+    .csr2tdu_req            (csr2tdu_req       ),
+    .csr2tdu_cmd            (csr2tdu_cmd       ),
+    .csr2tdu_addr           (csr2tdu_addr      ),
+    .csr2tdu_wdata          (csr2tdu_wdata     ),
+    .tdu2csr_rdata          (tdu2csr_rdata     ),
+    .tdu2csr_resp           (tdu2csr_resp      ),
+`endif // SCR1_BRKM_EN
+    .fuse_mhartid           (fuse_mhartid       )
+);
+
+//-------------------------------------------------------------------------------
+// Integrated programmable interrupt controller
+//-------------------------------------------------------------------------------
+`ifdef SCR1_IPIC_EN
+scr1_ipic i_pipe_ipic (
+    .rst_n              (pipe_rst_n     ),
+`ifdef SCR1_CLKCTRL_EN
+    .clk                (clk_alw_on     ),
+`else // SCR1_CLKCTRL_EN
+    .clk                (clk            ),
+`endif // SCR1_CLKCTRL_EN
+    .irq_lines          (irq_lines      ),
+    .csr2ipic_r_req     (csr2ipic_r_req ),
+    .csr2ipic_w_req     (csr2ipic_w_req ),
+    .csr2ipic_addr      (csr2ipic_addr  ),
+    .csr2ipic_wdata     (csr2ipic_wdata ),
+    .ipic2csr_rdata     (ipic2csr_rdata ),
+    .irq_m_req          (ext_irq        )
+);
+`endif // SCR1_IPIC_EN
+
+//-------------------------------------------------------------------------------
+// Breakpoint module
+//-------------------------------------------------------------------------------
+`ifdef SCR1_BRKM_EN
+scr1_pipe_tdu i_pipe_tdu (
+    // Common signals
+ `ifdef SCR1_DBGC_EN
+    .rst_n                  (dbg_rst_n              ),
+ `else
+    .rst_n                  (rst_n                  ),
+ `endif // SCR1_DBGC_EN
+    .clk                    (clk                    ),
+    .clk_en                 (1'b1                   ),
+ `ifdef SCR1_DBGC_EN
+    .dsbl                   (hwbrk_dsbl             ),
+ `else // SCR1_DBGC_EN
+    .dsbl                   (1'b0                   ),
+ `endif // SCR1_DBGC_EN
+
+    // CSR I/F
+ `ifdef SCR1_DBGC_EN
+    .csr2tdu_req            (csr2tdu_req_qlfy      ),
+    .csr2tdu_cmd            (csr2tdu_cmd_qlfy      ),
+    .csr2tdu_addr           (csr2tdu_addr_qlfy     ),
+    .csr2tdu_wdata          (csr2tdu_wdata_qlfy    ),
+ `else // SCR1_DBGC_EN
+    .csr2tdu_req            (csr2tdu_req           ),
+    .csr2tdu_cmd            (csr2tdu_cmd           ),
+    .csr2tdu_addr           (csr2tdu_addr          ),
+    .csr2tdu_wdata          (csr2tdu_wdata         ),
+ `endif // SCR1_DBGC_EN
+    .csr2tdu_rdata          (tdu2csr_rdata         ),
+    .csr2tdu_resp           (tdu2csr_resp          ),
+    // ID I/F
+ `ifdef SCR1_DBGC_EN
+    .exu2tdu_i_mon          (exu2tdu_i_mon_qlfy    ),
+ `else // SCR1_DBGC_EN
+    .exu2tdu_i_mon          (exu2tdu_i_mon         ),
+ `endif // SCR1_DBGC_EN
+    // CFU I/F
+    .tdu2exu_i_match        (tdu2exu_i_match       ),
+    .tdu2exu_i_x_req        (tdu2exu_i_x_req       ),
+    // LSU I/F
+    .tdu2lsu_i_x_req        (tdu2lsu_i_x_req       ),
+ `ifdef SCR1_DBGC_EN
+    .tdu2lsu_d_mon          (lsu2tdu_d_mon_qlfy    ),
+ `else // SCR1_DBGC_EN
+    .tdu2lsu_d_mon          (lsu2tdu_d_mon         ),
+ `endif // SCR1_DBGC_EN
+    .tdu2lsu_d_match        (tdu2lsu_d_match       ),
+    .tdu2lsu_d_x_req        (tdu2lsu_d_x_req       ),
+    // EPU I/F
+ `ifdef SCR1_DBGC_EN
+    .tdu2hdu_dmode_req      (tdu2hdu_dmode_req      ),
+    // WB I/F
+    .exu2tdu_bp_retire      (exu2tdu_bp_retire_qlfy)
+ `else // SCR1_DBGC_EN
+    .tdu2hdu_dmode_req      (                       ),
+    // WB I/F
+    .exu2tdu_bp_retire      (exu2tdu_bp_retire     )
+ `endif // SCR1_DBGC_EN
+);
+
+ `ifdef SCR1_DBGC_EN
+assign csr2tdu_req_qlfy         = csr2tdu_req       & {$bits(csr2tdu_req){pipe_rst_n_qlfy}};
+assign csr2tdu_cmd_qlfy         = pipe_rst_n_qlfy   ? csr2tdu_cmd : SCR1_CSR_CMD_NONE;
+assign csr2tdu_addr_qlfy        = csr2tdu_addr      & {$bits(csr2tdu_addr){pipe_rst_n_qlfy}};
+assign csr2tdu_wdata_qlfy       = csr2tdu_wdata     & {$bits(csr2tdu_wdata){pipe_rst_n_qlfy}};
+//
+assign exu2tdu_i_mon_qlfy       = pipe_rst_n_qlfy ? exu2tdu_i_mon : '0;
+assign lsu2tdu_d_mon_qlfy       = pipe_rst_n_qlfy ? lsu2tdu_d_mon : '0;
+assign exu2tdu_bp_retire_qlfy   = exu2tdu_bp_retire & {$bits(exu2tdu_bp_retire){pipe_rst_n_qlfy}};
+ `endif // SCR1_DBGC_EN
+
+`endif // SCR1_BRKM_EN
+
+//-------------------------------------------------------------------------------
+// HART Debug Unit (HDU)
+//-------------------------------------------------------------------------------
+`ifdef SCR1_DBGC_EN
+scr1_pipe_hdu i_pipe_hdu (
+    // Common signals
+    .rst_n                  (dbg_rst_n              ),
+    .clk_en                 (dm_active              ),
+`ifdef SCR1_CLKCTRL_EN
+    .clk_pipe_en            (clk_pipe_en            ),
+    .clk                    (clk_dbgc               ),
+`else
+    .clk                    (clk                    ),
+`endif // SCR1_CLKCTRL_EN
+    // Control/status registers i/f
+    .csr_req                (csr2hdu_req_qlfy       ),
+    .csr_cmd                (csr2hdu_cmd_qlfy       ),
+    .csr_addr               (csr2hdu_addr_qlfy      ),
+    .csr_wdata              (csr2hdu_wdata_qlfy     ),
+    .csr_resp               (hdu2csr_resp           ),
+    .csr_rdata              (hdu2csr_rdata          ),
+    // HART Run Control i/f
+    .pipe_rst_n_qlfy        (pipe_rst_n_qlfy        ),
+    .dm_cmd_req             (dm_cmd_req             ),
+    .dm_cmd                 (dm_cmd                 ),
+    .dm_cmd_resp            (dm_cmd_resp            ),
+    .dm_cmd_rcode           (dm_cmd_rcode           ),
+    .dm_hart_event          (dm_hart_event          ),
+    .dm_hart_status         (dm_hart_status         ),
+    // Program Buffer - HART instruction execution i/f
+    .dm_pbuf_addr           (dm_pbuf_addr           ),
+    .dm_pbuf_instr          (dm_pbuf_instr          ),
+    // HART Abstract Data regs i/f
+    .dm_dreg_req            (dm_dreg_req            ),
+    .dm_dreg_wr             (dm_dreg_wr             ),
+    .dm_dreg_wdata          (dm_dreg_wdata          ),
+    .dm_dreg_resp           (dm_dreg_resp           ),
+    .dm_dreg_fail           (dm_dreg_fail           ),
+    .dm_dreg_rdata          (dm_dreg_rdata          ),
+    //
+`ifdef SCR1_BRKM_EN
+    // HDU <-> TDU
+    .hart_hwbrk_dsbl        (hwbrk_dsbl             ),
+    .hart_tm_dmode_req      (tdu2hdu_dmode_req      ),
+    .hart_brkpt_hw          (brkpt_hw               ),
+`endif // SCR1_BRKM_EN
+
+    // HART Run Status
+    .hart_exu_busy          (exu_busy_qlfy          ),
+    .hart_instret           (instret_qlfy           ),
+    .hart_init_pc           (exu_init_pc_qlfy       ),
+    // HART Halt Status
+    .hart_exu_exc_req       (exu_exc_req_qlfy       ),
+    .hart_brkpt             (brkpt_qlfy             ),
+    // HART Run Control
+    .hart_fetch_pbuf        (fetch_pbuf             ),
+    .hart_exu_no_commit     (exu_no_commit          ),
+    .hart_exu_irq_dsbl      (exu_irq_dsbl           ),
+    .hart_exu_pc_advmt_dsbl (exu_pc_advmt_dsbl      ),
+    .hart_exu_dmode_sstep_en(exu_dmode_sstep_en     ),
+
+    // HART state
+    .hart_dbg_halted        (dbg_halted             ),
+    .hart_dbg_run2halt      (dbg_run2halt           ),
+    .hart_dbg_halt2run      (dbg_halt2run           ),
+    .hart_dbg_run_start     (dbg_run_start          ),
+    .hart_pc                (curr_pc_qlfy           ),
+    .hart_new_pc            (dbg_new_pc             ),
+    //
+    .hart_pbuf_instr_rdy    (ifu2hdu_pbuf_rdy_qlfy  ),
+    .hart_pbuf_instr_vd     (hdu2ifu_pbuf_vd        ),
+    .hart_pbuf_instr_err    (hdu2ifu_pbuf_err       ),
+    .hart_pbuf_instr        (hdu2ifu_pbuf_instr     )
+);
+
+assign csr2hdu_req_qlfy         = csr2hdu_req       & {$bits(csr2hdu_req){pipe_rst_n_qlfy}};
+assign csr2hdu_cmd_qlfy         = pipe_rst_n_qlfy   ? csr2hdu_cmd : SCR1_CSR_CMD_NONE;
+assign csr2hdu_addr_qlfy        = csr2hdu_addr      & {$bits(csr2hdu_addr){pipe_rst_n_qlfy}};
+assign csr2hdu_wdata_qlfy       = csr2hdu_wdata     & {$bits(csr2hdu_wdata){pipe_rst_n_qlfy}};
+//
+assign exu_busy_qlfy            = exu_busy          & {$bits(exu_busy){pipe_rst_n_qlfy}};
+assign instret_qlfy             = instret           & {$bits(instret){pipe_rst_n_qlfy}};
+assign exu_init_pc_qlfy         = exu_init_pc       & {$bits(exu_init_pc){pipe_rst_n_qlfy}};
+assign exu_exc_req_qlfy         = exu_exc_req       & {$bits(exu_exc_req){pipe_rst_n_qlfy}};
+assign brkpt_qlfy               = brkpt             & {$bits(brkpt){pipe_rst_n_qlfy}};
+assign ifu2hdu_pbuf_rdy_qlfy    = ifu2hdu_pbuf_rdy  & {$bits(ifu2hdu_pbuf_rdy){pipe_rst_n_qlfy}};
+assign curr_pc_qlfy             = curr_pc           & {$bits(curr_pc){pipe_rst_n_qlfy}};
+
+`endif // SCR1_DBGC_EN
+
+`ifdef SCR1_SIM_ENV
+//-------------------------------------------------------------------------------
+// Tracelog
+//-------------------------------------------------------------------------------
+
+scr1_tracelog i_tracelog (
+    .rst_n          (pipe_rst_n                         ),
+    .clk            (clk                                ),
+    .fuse_mhartid   (fuse_mhartid                       ),
+    // MPRF
+    .mprf_int       (i_pipe_mprf.mprf_int               ),
+    .mprf_wr_en     (i_pipe_mprf.exu2mprf_w_req         ),
+    .mprf_wr_addr   (i_pipe_mprf.exu2mprf_rd_addr       ),
+    .mprf_wr_data   (i_pipe_mprf.exu2mprf_rd_data       ),
+    // EXU
+    .update_pc_en   (i_pipe_exu.update_pc_en            ),
+    .update_pc      (i_pipe_exu.update_pc               ),
+    // CSR
+    .mstatus_mie    (i_pipe_csr.csr_mstatus_mie         ),
+    .mstatus_mpie   (i_pipe_csr.csr_mstatus_mpie        ),
+    .mtvec_base     (i_pipe_csr.csr_mtvec_base          ),
+    .mtvec_mode     (i_pipe_csr.csr_mtvec_mode          ),
+    .mie_meie       (i_pipe_csr.csr_mie_meie            ),
+    .mie_mtie       (i_pipe_csr.csr_mie_mtie            ),
+    .mie_msie       (i_pipe_csr.csr_mie_msie            ),
+    .mip_meip       (i_pipe_csr.csr_mip_meip            ),
+    .mip_mtip       (i_pipe_csr.csr_mip_mtip            ),
+    .mip_msip       (i_pipe_csr.csr_mip_msip            ),
+    .mepc           (i_pipe_csr.csr_mepc                ),
+    .mcause_i       (i_pipe_csr.csr_mcause_i            ),
+    .mcause_ec      (i_pipe_csr.csr_mcause_ec           ),
+    .mtval          (i_pipe_csr.csr_mtval               ),
+    .mstatus_mie_up (i_pipe_csr.csr2exu_mstatus_mie_up  )
+);
+
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_pipe_top
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/pipeline/scr1_tracelog.sv b/third_party/tests/Scr1/src/pipeline/scr1_tracelog.sv
new file mode 100644
index 0000000..66b55c1
--- /dev/null
+++ b/third_party/tests/Scr1/src/pipeline/scr1_tracelog.sv
@@ -0,0 +1,422 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_tracelog.sv>
+/// @brief      Core tracelog module
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_arch_types.svh"
+`include "scr1_csr.svh"
+
+module scr1_tracelog (
+    input   logic                                   rst_n,
+    input   logic                                   clk,
+    input   logic [`SCR1_XLEN-1:0]                  fuse_mhartid,
+    // MPRF
+`ifndef SCR1_RVE_EXT
+    input   type_scr1_mprf_v [1:31]                 mprf_int,
+`else // SCR1_RVE_EXT
+    input   type_scr1_mprf_v [1:15]                 mprf_int,
+`endif // SCR1_RVE_EXT
+    input   logic                                   mprf_wr_en,
+    input   logic [`SCR1_MPRF_ADDR_WIDTH-1:0]       mprf_wr_addr,
+    input   logic [`SCR1_XLEN-1:0]                  mprf_wr_data,
+    // EXU
+    input   logic                                   update_pc_en,
+    input   logic [`SCR1_XLEN-1:0]                  update_pc,
+    // CSR
+    input   logic                                   mstatus_mie,
+    input   logic                                   mstatus_mpie,
+    input   logic [`SCR1_XLEN-1:6]                  mtvec_base,
+    input   logic                                   mtvec_mode,
+    input   logic                                   mie_meie,
+    input   logic                                   mie_mtie,
+    input   logic                                   mie_msie,
+    input   logic                                   mip_meip,
+    input   logic                                   mip_mtip,
+    input   logic                                   mip_msip,
+ `ifdef SCR1_RVC_EXT
+    input   logic [`SCR1_XLEN-1:1]                  mepc,
+ `else // SCR1_RVC_EXT
+    input   logic [`SCR1_XLEN-1:2]                  mepc,
+ `endif // SCR1_RVC_EXT
+    input   logic                                   mcause_i,
+    input   type_scr1_exc_code_e                    mcause_ec,
+    input   logic [`SCR1_XLEN-1:0]                  mtval,
+    input   logic                                   mstatus_mie_up
+);
+
+//-------------------------------------------------------------------------------
+// MPRF register aliases
+//-------------------------------------------------------------------------------
+typedef struct {
+    logic [`SCR1_XLEN-1:0]      INT_00_ZERO ;
+    logic [`SCR1_XLEN-1:0]      INT_01_RA   ;
+    logic [`SCR1_XLEN-1:0]      INT_02_SP   ;
+    logic [`SCR1_XLEN-1:0]      INT_03_GP   ;
+    logic [`SCR1_XLEN-1:0]      INT_04_TP   ;
+    logic [`SCR1_XLEN-1:0]      INT_05_T0   ;
+    logic [`SCR1_XLEN-1:0]      INT_06_T1   ;
+    logic [`SCR1_XLEN-1:0]      INT_07_T2   ;
+    logic [`SCR1_XLEN-1:0]      INT_08_S0   ;
+    logic [`SCR1_XLEN-1:0]      INT_09_S1   ;
+    logic [`SCR1_XLEN-1:0]      INT_10_A0   ;
+    logic [`SCR1_XLEN-1:0]      INT_11_A1   ;
+    logic [`SCR1_XLEN-1:0]      INT_12_A2   ;
+    logic [`SCR1_XLEN-1:0]      INT_13_A3   ;
+    logic [`SCR1_XLEN-1:0]      INT_14_A4   ;
+    logic [`SCR1_XLEN-1:0]      INT_15_A5   ;
+`ifndef SCR1_RVE_EXT
+    logic [`SCR1_XLEN-1:0]      INT_16_A6   ;
+    logic [`SCR1_XLEN-1:0]      INT_17_A7   ;
+    logic [`SCR1_XLEN-1:0]      INT_18_S2   ;
+    logic [`SCR1_XLEN-1:0]      INT_19_S3   ;
+    logic [`SCR1_XLEN-1:0]      INT_20_S4   ;
+    logic [`SCR1_XLEN-1:0]      INT_21_S5   ;
+    logic [`SCR1_XLEN-1:0]      INT_22_S6   ;
+    logic [`SCR1_XLEN-1:0]      INT_23_S7   ;
+    logic [`SCR1_XLEN-1:0]      INT_24_S8   ;
+    logic [`SCR1_XLEN-1:0]      INT_25_S9   ;
+    logic [`SCR1_XLEN-1:0]      INT_26_S10  ;
+    logic [`SCR1_XLEN-1:0]      INT_27_S11  ;
+    logic [`SCR1_XLEN-1:0]      INT_28_T3   ;
+    logic [`SCR1_XLEN-1:0]      INT_29_T4   ;
+    logic [`SCR1_XLEN-1:0]      INT_30_T5   ;
+    logic [`SCR1_XLEN-1:0]      INT_31_T6   ;
+`endif // SCR1_RVE_EXT
+} type_scr1_ireg_name_s;
+
+type_scr1_ireg_name_s   mprf_int_alias;
+
+assign mprf_int_alias.INT_00_ZERO   = '0;
+assign mprf_int_alias.INT_01_RA     = mprf_int[1];
+assign mprf_int_alias.INT_02_SP     = mprf_int[2];
+assign mprf_int_alias.INT_03_GP     = mprf_int[3];
+assign mprf_int_alias.INT_04_TP     = mprf_int[4];
+assign mprf_int_alias.INT_05_T0     = mprf_int[5];
+assign mprf_int_alias.INT_06_T1     = mprf_int[6];
+assign mprf_int_alias.INT_07_T2     = mprf_int[7];
+assign mprf_int_alias.INT_08_S0     = mprf_int[8];
+assign mprf_int_alias.INT_09_S1     = mprf_int[9];
+assign mprf_int_alias.INT_10_A0     = mprf_int[10];
+assign mprf_int_alias.INT_11_A1     = mprf_int[11];
+assign mprf_int_alias.INT_12_A2     = mprf_int[12];
+assign mprf_int_alias.INT_13_A3     = mprf_int[13];
+assign mprf_int_alias.INT_14_A4     = mprf_int[14];
+assign mprf_int_alias.INT_15_A5     = mprf_int[15];
+`ifndef SCR1_RVE_EXT
+assign mprf_int_alias.INT_16_A6     = mprf_int[16];
+assign mprf_int_alias.INT_17_A7     = mprf_int[17];
+assign mprf_int_alias.INT_18_S2     = mprf_int[18];
+assign mprf_int_alias.INT_19_S3     = mprf_int[19];
+assign mprf_int_alias.INT_20_S4     = mprf_int[20];
+assign mprf_int_alias.INT_21_S5     = mprf_int[21];
+assign mprf_int_alias.INT_22_S6     = mprf_int[22];
+assign mprf_int_alias.INT_23_S7     = mprf_int[23];
+assign mprf_int_alias.INT_24_S8     = mprf_int[24];
+assign mprf_int_alias.INT_25_S9     = mprf_int[25];
+assign mprf_int_alias.INT_26_S10    = mprf_int[26];
+assign mprf_int_alias.INT_27_S11    = mprf_int[27];
+assign mprf_int_alias.INT_28_T3     = mprf_int[28];
+assign mprf_int_alias.INT_29_T4     = mprf_int[29];
+assign mprf_int_alias.INT_30_T5     = mprf_int[30];
+assign mprf_int_alias.INT_31_T6     = mprf_int[31];
+`endif // SCR1_RVE_EXT
+
+//-------------------------------------------------------------------------------
+// Time counter
+//-------------------------------------------------------------------------------
+int     time_cnt;
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        time_cnt    <= 0;
+    end else begin
+        time_cnt    <= time_cnt + 1;
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Trace log MPRF
+//-------------------------------------------------------------------------------
+`ifdef SCR1_TRACE_LOG_EN
+
+logic                               trace_update;
+logic                               trace_update_r;
+logic [`SCR1_XLEN-1:0]              curr_pc_log;
+`ifndef SCR1_RVE_EXT
+type_scr1_mprf_v [1:31]             mprf_int_log;
+`else // SCR1_RVE_EXT
+type_scr1_mprf_v [1:15]             mprf_int_log;
+`endif // SCR1_RVE_EXT
+logic                               mprf_up;
+logic [`SCR1_MPRF_ADDR_WIDTH-1:0]   mprf_addr;
+logic                               tracelog_full;
+int unsigned                        trace_fhandler;
+int unsigned                        trace_fhandler_diff;
+int                                 time_cnt2;
+string                              hart;
+string                              test_name;
+
+task trace_write_mprf;
+    $fwrite(trace_fhandler,  "%12d ", time_cnt);
+    $fwrite(trace_fhandler,  "%6d ", time_cnt-time_cnt2);
+    $fwrite(trace_fhandler,  "%8x ", curr_pc_log);
+`ifndef SCR1_RVE_EXT
+    for (int i=1; i<32; ++i) begin
+`else // SCR1_RVE_EXT
+    for (int i=1; i<16; ++i) begin
+`endif // SCR1_RVE_EXT
+        $fwrite(trace_fhandler,  "%8x ", mprf_int_log[i]);
+    end
+    $fwrite(trace_fhandler,  "\n");
+endtask // trace_write_mprf
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        mprf_int_log    <= '0;
+        mprf_up         <= '0;
+        mprf_addr       <= '0;
+    end else begin
+        mprf_up         <= '0;
+        mprf_addr       <= '0;
+
+        if (mprf_wr_en) begin
+            mprf_up     <= 1'b1;
+            mprf_addr   <= mprf_wr_addr;
+            if (mprf_wr_addr != 0) begin
+                mprf_int_log[$unsigned(mprf_wr_addr)] <= mprf_wr_data;
+            end
+        end
+    end
+end
+
+always_ff @(posedge clk) begin
+    curr_pc_log <= update_pc;
+end
+
+assign trace_update = update_pc_en | (mprf_wr_en & ~mstatus_mie_up);
+
+int unsigned temp_fhandler;
+
+initial begin
+`ifndef VERILATOR
+    #1 hart.hextoa(fuse_mhartid);
+`endif // VERILATOR
+
+`ifdef SCR1_TRACE_LOG_FULL
+    tracelog_full   = 1'b1;
+`else // SCR1_TRACE_LOG_FULL
+    tracelog_full   = 1'b0;
+`endif // SCR1_TRACE_LOG_FULL
+
+    // erase old logs
+    if (tracelog_full) begin
+        temp_fhandler= $fopen({"trace_mprf_", hart, ".log"}, "w");
+        $fclose(temp_fhandler);
+    end else begin
+        temp_fhandler = $fopen({"trace_mprf_diff_", hart, ".log"}, "w");
+        $fclose(temp_fhandler);
+    end
+    temp_fhandler = $fopen({"trace_csr_", hart, ".log"}, "w");
+    $fclose(temp_fhandler);
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        if (trace_fhandler) begin
+            $fflush(trace_fhandler);
+            $fclose(trace_fhandler);
+            trace_fhandler  = 0;
+        end
+        trace_update_r      <= 1'b0;
+        time_cnt2           <= 0;
+    end else begin
+        // open file
+        if ((trace_fhandler == 0) & tracelog_full) begin
+            trace_fhandler = $fopen({"trace_mprf_", hart, ".log"}, "a+");
+            // Write Header
+            $fwrite(trace_fhandler,  "# Test: %s\n", test_name);
+            $fwrite(trace_fhandler,  "          Clk# ");
+            $fwrite(trace_fhandler,  "Delay ");
+            $fwrite(trace_fhandler,  " PC     ");
+            $fwrite(trace_fhandler,  " X1_RA   ");
+            $fwrite(trace_fhandler,  " X2_SP   ");
+            $fwrite(trace_fhandler,  " X3_GP   ");
+            $fwrite(trace_fhandler,  " X4_TP   ");
+            $fwrite(trace_fhandler,  " X5_T0   ");
+            $fwrite(trace_fhandler,  " X6_T1   ");
+            $fwrite(trace_fhandler,  " X7_T2   ");
+            $fwrite(trace_fhandler,  " X8_S0   ");
+            $fwrite(trace_fhandler,  " X9_S1   ");
+            $fwrite(trace_fhandler,  " X10_A0  ");
+            $fwrite(trace_fhandler,  " X11_A1  ");
+            $fwrite(trace_fhandler,  " X12_A2  ");
+            $fwrite(trace_fhandler,  " X13_A3  ");
+            $fwrite(trace_fhandler,  " X14_A4  ");
+            $fwrite(trace_fhandler,  " X15_A5  ");
+`ifndef SCR1_RVE_EXT
+            $fwrite(trace_fhandler,  " X16_A6  ");
+            $fwrite(trace_fhandler,  " X17_A7  ");
+            $fwrite(trace_fhandler,  " X18_S2  ");
+            $fwrite(trace_fhandler,  " X19_S3  ");
+            $fwrite(trace_fhandler,  " X20_S4  ");
+            $fwrite(trace_fhandler,  " X21_S5  ");
+            $fwrite(trace_fhandler,  " X22_S6  ");
+            $fwrite(trace_fhandler,  " X23_S7  ");
+            $fwrite(trace_fhandler,  " X24_S8  ");
+            $fwrite(trace_fhandler,  " X25_S9  ");
+            $fwrite(trace_fhandler,  " X26_S10 ");
+            $fwrite(trace_fhandler,  " X27_S11 ");
+            $fwrite(trace_fhandler,  " X28_T3  ");
+            $fwrite(trace_fhandler,  " X29_T4  ");
+            $fwrite(trace_fhandler,  " X30_T5  ");
+            $fwrite(trace_fhandler,  " X31_T6  ");
+`endif // SCR1_RVE_EXT
+            $fwrite(trace_fhandler,  "\n");
+        end
+
+        trace_update_r      <= trace_update;
+
+        if (trace_update_r & tracelog_full) begin
+            time_cnt2       <= time_cnt;
+            trace_write_mprf();
+        end
+    end
+end
+
+`ifndef SCR1_TRACE_LOG_FULL
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        if (trace_fhandler_diff) begin
+            $fflush(trace_fhandler_diff);
+            $fclose(trace_fhandler_diff);
+            trace_fhandler_diff = 0;
+        end
+    end else begin
+        // open file
+        if ((trace_fhandler_diff == 0) & ~tracelog_full) begin
+            trace_fhandler_diff = $fopen({"trace_mprf_diff_", hart, ".log"}, "a+");
+            // Write Header
+            $fwrite(trace_fhandler_diff,  "# Test: %s\n", test_name);
+            $fwrite(trace_fhandler_diff,  "      Clk# ");
+            $fwrite(trace_fhandler_diff,  "  PC ");
+            $fwrite(trace_fhandler_diff,  "\n");
+        end
+
+        if (trace_update_r & ~tracelog_full) begin
+            // write updated registers
+            $fwrite(trace_fhandler_diff,  "%10d: ", time_cnt);
+            $fwrite(trace_fhandler_diff,  "%8x ", curr_pc_log);
+
+            if (mprf_up) begin
+`ifndef SCR1_RVE_EXT
+                for (int i=1; i<32; ++i) begin
+`else // SCR1_RVE_EXT
+                for (int i=1; i<16; ++i) begin
+`endif // SCR1_RVE_EXT
+                    if (mprf_addr == i) begin
+                        $fwrite(trace_fhandler_diff,  "X%2d: %8x", i, mprf_int_log[i]);
+                    end
+                end
+            end
+            $fwrite(trace_fhandler_diff,  "\n");
+        end
+    end
+end
+
+`endif // SCR1_TRACE_LOG_FULL
+
+//-------------------------------------------------------------------------------
+// Trace log CSR
+//-------------------------------------------------------------------------------
+int unsigned                trace_csr_fhandler;
+
+typedef struct packed {
+    logic [`SCR1_XLEN-1:0]  mstatus;
+    logic [`SCR1_XLEN-1:0]  mtvec;
+    logic [`SCR1_XLEN-1:0]  mie;
+    logic [`SCR1_XLEN-1:0]  mip;
+    logic [`SCR1_XLEN-1:0]  mepc;
+    logic [`SCR1_XLEN-1:0]  mcause;
+    logic [`SCR1_XLEN-1:0]  mtval;
+} type_scr1_csr_trace_s;
+
+type_scr1_csr_trace_s       csr_trace1;
+type_scr1_csr_trace_s       csr_trace2;
+
+task trace_write_csr;
+    $fwrite(trace_csr_fhandler,  "%12d   ", time_cnt);
+    $fwrite(trace_csr_fhandler,  "%8x ", csr_trace1.mstatus );
+    $fwrite(trace_csr_fhandler,  "%8x ", csr_trace1.mtvec   );
+    $fwrite(trace_csr_fhandler,  "%8x ", csr_trace1.mie     );
+    $fwrite(trace_csr_fhandler,  "%8x ", csr_trace1.mip     );
+    $fwrite(trace_csr_fhandler,  "%8x ", csr_trace1.mepc    );
+    $fwrite(trace_csr_fhandler,  "%8x ", csr_trace1.mcause  );
+    $fwrite(trace_csr_fhandler,  "%8x ", csr_trace1.mtval   );
+    $fwrite(trace_csr_fhandler,  "\n");
+endtask // trace_write_csr
+
+always_comb begin
+    csr_trace1.mtvec        = {mtvec_base, 4'd0, 2'(mtvec_mode)};
+    csr_trace1.mepc         =
+`ifdef SCR1_RVC_EXT
+                              {mepc, 1'b0};
+`else // SCR1_RVC_EXT
+                              {mepc, 2'b00};
+`endif // SCR1_RVC_EXT
+    csr_trace1.mcause       = {mcause_i, type_scr1_csr_mcause_ec_v'(mcause_ec)};
+    csr_trace1.mtval        = mtval;
+
+    csr_trace1.mstatus      = '0;
+    csr_trace1.mie          = '0;
+    csr_trace1.mip          = '0;
+
+    csr_trace1.mstatus[SCR1_CSR_MSTATUS_MIE_OFFSET]     = mstatus_mie;
+    csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPIE_OFFSET]    = mstatus_mpie;
+    csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPP_OFFSET+1:SCR1_CSR_MSTATUS_MPP_OFFSET]   = SCR1_CSR_MSTATUS_MPP;
+    csr_trace1.mie[SCR1_CSR_MIE_MSIE_OFFSET]            = mie_msie;
+    csr_trace1.mie[SCR1_CSR_MIE_MTIE_OFFSET]            = mie_mtie;
+    csr_trace1.mie[SCR1_CSR_MIE_MEIE_OFFSET]            = mie_meie;
+    csr_trace1.mip[SCR1_CSR_MIE_MSIE_OFFSET]            = mip_msip;
+    csr_trace1.mip[SCR1_CSR_MIE_MTIE_OFFSET]            = mip_mtip;
+    csr_trace1.mip[SCR1_CSR_MIE_MEIE_OFFSET]            = mip_meip;
+end
+
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        if (trace_csr_fhandler) begin
+            $fflush(trace_csr_fhandler);
+            $fclose(trace_csr_fhandler);
+            trace_csr_fhandler = 0;
+        end
+        csr_trace2  <= csr_trace1;
+    end else begin
+        // open file
+        if (trace_csr_fhandler == 0) begin
+            trace_csr_fhandler = $fopen({"trace_csr_", hart, ".log"}, "a+");
+
+            // Write Header
+            $fwrite(trace_csr_fhandler, "# Test: %s\n", test_name);
+            $fwrite(trace_csr_fhandler, "        Clk#  ");
+            $fwrite(trace_csr_fhandler, "  MSTATUS");
+            $fwrite(trace_csr_fhandler, "    MTVEC");
+            $fwrite(trace_csr_fhandler, "      MIE");
+            $fwrite(trace_csr_fhandler, "      MIP");
+            $fwrite(trace_csr_fhandler, "     MEPC");
+            $fwrite(trace_csr_fhandler, "   MCAUSE");
+            $fwrite(trace_csr_fhandler, " MTVAL"   );
+            $fwrite(trace_csr_fhandler,  "\n");
+
+            trace_write_csr();
+        end
+        csr_trace2   <= csr_trace1;
+        if (csr_trace2 != csr_trace1) begin
+            trace_write_csr();
+        end
+    end
+end
+
+`endif // SCR1_TRACE_LOG_EN
+
+endmodule : scr1_tracelog
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/tb/scr1_memory_tb_ahb.sv b/third_party/tests/Scr1/src/tb/scr1_memory_tb_ahb.sv
new file mode 100644
index 0000000..ba84ecb
--- /dev/null
+++ b/third_party/tests/Scr1/src/tb/scr1_memory_tb_ahb.sv
@@ -0,0 +1,608 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_memory_tb_ahb.sv>
+/// @brief      AHB memory testbench
+///
+
+`include "scr1_ahb.svh"
+`include "scr1_ipic.svh"
+
+module scr1_memory_tb_ahb #(
+    parameter SCR1_MEM_POWER_SIZE  = 16
+)
+(
+    // Control
+    input   logic                                   rst_n,
+    input   logic                                   clk,
+`ifdef SCR1_IPIC_EN
+    output  logic  [SCR1_IRQ_LINES_NUM-1:0]         irq_lines,
+`endif // SCR1_IPIC_EN
+    input   integer                                 imem_req_ack_stall_in,
+    input   integer                                 dmem_req_ack_stall_in,
+
+    // Instruction Memory Interface
+    // input   logic   [3:0]                           imem_hprot,
+    // input   logic   [2:0]                           imem_hburst,
+    input   logic   [2:0]                           imem_hsize,
+    input   logic   [1:0]                           imem_htrans,
+    input   logic   [SCR1_AHB_WIDTH-1:0]            imem_haddr,
+    output  logic                                   imem_hready,
+    output  logic   [SCR1_AHB_WIDTH-1:0]            imem_hrdata,
+    output  logic                                   imem_hresp,
+
+    // Memory Interface
+    // input   logic   [3:0]                           dmem_hprot,
+    // input   logic   [2:0]                           dmem_hburst,
+    input   logic   [2:0]                           dmem_hsize,
+    input   logic   [1:0]                           dmem_htrans,
+    input   logic   [SCR1_AHB_WIDTH-1:0]            dmem_haddr,
+    input   logic                                   dmem_hwrite,
+    input   logic   [SCR1_AHB_WIDTH-1:0]            dmem_hwdata,
+    output  logic                                   dmem_hready,
+    output  logic   [SCR1_AHB_WIDTH-1:0]            dmem_hrdata,
+    output  logic                                   dmem_hresp
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters
+//-------------------------------------------------------------------------------
+localparam SCR1_PRINT_ADDR      = 32'hF0000000;
+localparam SCR1_IRQ_ADDR        = 32'hF0000100;
+localparam SCR1_MEM_ERR_ADDR    = 32'hFFFFF100;
+localparam SCR1_MEM_ERR_PTR     = 32'hF0000200;
+
+//-------------------------------------------------------------------------------
+// Local Types
+//-------------------------------------------------------------------------------
+typedef enum logic {
+    SCR1_AHB_STATE_IDLE = 1'b0,
+    SCR1_AHB_STATE_DATA = 1'b1,
+    SCR1_AHB_STATE_ERR  = 1'bx
+} type_scr1_ahb_state_e;
+
+//-------------------------------------------------------------------------------
+// Memory definition
+//-------------------------------------------------------------------------------
+logic [7:0]                             memory [0:2**SCR1_MEM_POWER_SIZE-1];
+logic [31:0]                            mem_err_ptr;
+`ifdef SCR1_IPIC_EN
+logic [SCR1_IRQ_LINES_NUM-1:0]          irq_reg;
+`endif // SCR1_IPIC_EN
+logic [7:0]                             mirage [0:2**SCR1_MEM_POWER_SIZE-1];
+bit                                     mirage_en;
+bit                                     mirage_rangeen;
+bit [SCR1_AHB_WIDTH-1:0]                mirage_adrlo = '1;
+bit [SCR1_AHB_WIDTH-1:0]                mirage_adrhi = '1;
+
+`ifdef VERILATOR
+logic [255:0]                           test_file;
+`else // VERILATOR
+string                                  test_file;
+`endif // VERILATOR
+bit                                     test_file_init;
+
+//-------------------------------------------------------------------------------
+// Local functions
+//-------------------------------------------------------------------------------
+function logic [SCR1_AHB_WIDTH-1:0] scr1_read_mem(
+    logic   [SCR1_AHB_WIDTH-1:0]    addr,
+    logic   [3:0]                   r_be,
+    logic   [3:0]                   w_hazard,
+    logic   [SCR1_AHB_WIDTH-1:0]    w_data,
+    bit                             mirage_en
+);
+    logic [SCR1_AHB_WIDTH-1:0]      tmp;
+    logic [SCR1_MEM_POWER_SIZE-1:0] addr_mirage;
+begin
+    scr1_read_mem = 'x;
+
+    if(~mirage_en) begin
+        for (int unsigned i=0; i<4; ++i) begin
+            tmp[(8*(i+1)-1)-:8] = (r_be[i])
+                                        ? (w_hazard[i])
+                                            ? w_data[(8*(i+1)-1)-:8]
+                                            : memory[addr+i]
+                                        : 'x;
+        end
+    end
+    else begin
+        addr_mirage = addr;
+        for (int i = 0; i < 4; ++i) begin
+            tmp[ (i*8)+:8 ] = (r_be[i])
+                                        ? (w_hazard[i])
+                                            ? w_data[(i*8)+:8]
+                                            : mirage[addr_mirage+i]
+                                        : 'x;
+        end
+    end
+    return tmp;
+end
+endfunction : scr1_read_mem
+
+function void scr1_write_mem(
+    logic   [SCR1_AHB_WIDTH-1:0]    addr,
+    logic   [3:0]                   w_be,
+    logic   [SCR1_AHB_WIDTH-1:0]    data,
+    bit                             mirage_en
+);
+    logic [SCR1_MEM_POWER_SIZE-1:0] addr_mirage;
+begin
+    for (int unsigned i=0; i<4; ++i) begin
+        if (w_be[i]) begin
+            if(~mirage_en)
+                memory[addr+i] <= data[(8*(i+1)-1)-:8];
+            else begin
+                addr_mirage = addr;
+                mirage[addr_mirage+i] <= data[(8*(i+1)-1)-:8];
+            end
+        end
+    end
+end
+endfunction : scr1_write_mem
+
+function logic scr1_check_err_addr(
+    int addr
+);
+logic   tmp;
+begin
+    tmp = (addr == SCR1_MEM_ERR_ADDR) | (addr ==  mem_err_ptr);
+    return ~tmp;
+end
+endfunction : scr1_check_err_addr
+
+function logic [3:0] scr1_be_form(
+    input   logic [1:0]     offset,
+    input   logic [1:0]     hsize
+);
+    logic [3:0]     tmp;
+begin
+    case (hsize)
+        SCR1_HSIZE_8B : begin
+            tmp = 4'b0001 << offset;
+        end
+        SCR1_HSIZE_16B : begin
+            tmp = 4'b0011 << offset;
+        end
+        SCR1_HSIZE_32B : begin
+            tmp = 4'b1111;
+        end
+    endcase
+    return tmp;
+end
+endfunction : scr1_be_form
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+// IMEM access
+type_scr1_ahb_state_e           imem_ahb_state;
+logic   [SCR1_AHB_WIDTH-1:0]    imem_ahb_addr;
+logic   [SCR1_AHB_WIDTH-1:0]    imem_req_ack_stall;
+bit                             imem_req_ack_rnd;
+logic                           imem_req_ack;
+logic                           imem_req_ack_nc;
+logic   [3:0]                   imem_be;
+logic   [SCR1_AHB_WIDTH-1:0]    imem_hrdata_l;
+logic   [3:0]                   imem_wr_hazard;
+
+// DMEM access
+logic   [SCR1_AHB_WIDTH-1:0]    dmem_req_ack_stall;
+bit                             dmem_req_ack_rnd;
+logic                           dmem_req_ack;
+logic                           dmem_req_ack_nc;
+logic   [3:0]                   dmem_be;
+type_scr1_ahb_state_e           dmem_ahb_state;
+logic   [SCR1_AHB_WIDTH-1:0]    dmem_ahb_addr;
+logic                           dmem_ahb_wr;
+logic   [2:0]                   dmem_ahb_size;
+logic   [3:0]                   dmem_ahb_be;
+logic   [SCR1_AHB_WIDTH-1:0]    dmem_hrdata_l;
+logic   [3:0]                   dmem_wr_hazard;
+
+//-------------------------------------------------------------------------------
+// Instruction memory ready
+//-------------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        imem_req_ack_stall <= imem_req_ack_stall_in;
+        imem_req_ack_rnd   <= 1'b0;
+    end else begin
+        if (imem_req_ack_stall == '0) begin
+            imem_req_ack_rnd <= $random;
+        end else begin
+            imem_req_ack_stall <= {imem_req_ack_stall[0], imem_req_ack_stall[31:1]};
+        end
+    end
+end
+
+assign imem_req_ack = (imem_req_ack_stall == 32'd0) ?  imem_req_ack_rnd : imem_req_ack_stall[0];
+
+//-------------------------------------------------------------------------------
+// Instruction memory AHB FSM
+//-------------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        imem_ahb_state <= SCR1_AHB_STATE_IDLE;
+    end else begin
+        case (imem_ahb_state)
+            SCR1_AHB_STATE_IDLE : begin
+                if (imem_req_ack) begin
+                    case (imem_htrans)
+                        SCR1_HTRANS_IDLE : begin
+                            imem_ahb_state <= SCR1_AHB_STATE_IDLE;
+                        end
+                        SCR1_HTRANS_NONSEQ : begin
+                            imem_ahb_state <= SCR1_AHB_STATE_DATA;
+                        end
+                        default : begin
+                            imem_ahb_state <= SCR1_AHB_STATE_ERR;
+                        end
+                    endcase
+                end
+            end
+            SCR1_AHB_STATE_DATA : begin
+                if (imem_req_ack) begin
+                    case (imem_htrans)
+                        SCR1_HTRANS_IDLE : begin
+                            imem_ahb_state <= SCR1_AHB_STATE_IDLE;
+                        end
+                        SCR1_HTRANS_NONSEQ : begin
+                            imem_ahb_state <= SCR1_AHB_STATE_DATA;
+                        end
+                        default : begin
+                            imem_ahb_state <= SCR1_AHB_STATE_ERR;
+                        end
+                    endcase
+                end
+            end
+            default : begin
+                imem_ahb_state <= SCR1_AHB_STATE_ERR;
+            end
+        endcase
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Address data generation
+//-------------------------------------------------------------------------------
+assign imem_be = scr1_be_form(2'b00, imem_hsize);
+assign imem_wr_hazard = (dmem_ahb_wr & (imem_haddr[SCR1_AHB_WIDTH-1:2] == dmem_ahb_addr[SCR1_AHB_WIDTH-1:2])) ? imem_be & dmem_ahb_be : '0;
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        imem_ahb_addr  <= 'x;
+        imem_hrdata_l  <= 'x;
+    end else begin
+        case (imem_ahb_state)
+            SCR1_AHB_STATE_IDLE : begin
+                if (imem_req_ack) begin
+                    case (imem_htrans)
+                        SCR1_HTRANS_IDLE : begin
+                        end
+                        SCR1_HTRANS_NONSEQ : begin
+                            imem_ahb_addr  <= imem_haddr;
+                            if (scr1_check_err_addr(imem_haddr)) begin
+                                if(mirage_rangeen & imem_haddr>=mirage_adrlo & imem_haddr<mirage_adrhi)
+                                    imem_hrdata_l <= scr1_read_mem({imem_haddr[SCR1_AHB_WIDTH-1:2], 2'b00}, imem_be, imem_wr_hazard, dmem_hwdata, 1'b1);
+                                else
+                                    imem_hrdata_l <= scr1_read_mem({imem_haddr[SCR1_AHB_WIDTH-1:2], 2'b00}, imem_be, imem_wr_hazard, dmem_hwdata, 1'b0);
+                            end
+                        end
+                        default : begin
+                            imem_ahb_addr  <= 'x;
+                            imem_hrdata_l  <= 'x;
+                        end
+                    endcase
+                end
+            end
+            SCR1_AHB_STATE_DATA : begin
+                if (imem_req_ack) begin
+                    case (imem_htrans)
+                        SCR1_HTRANS_IDLE : begin
+                            imem_ahb_addr  <= 'x;
+                            imem_hrdata_l  <= 'x;
+                        end
+                        SCR1_HTRANS_NONSEQ : begin
+                            imem_ahb_addr  <= imem_haddr;
+                            if (scr1_check_err_addr(imem_haddr)) begin
+                                if(mirage_rangeen & imem_haddr>=mirage_adrlo & imem_haddr<mirage_adrhi)
+                                    imem_hrdata_l <= scr1_read_mem({imem_haddr[SCR1_AHB_WIDTH-1:2], 2'b00}, imem_be, imem_wr_hazard, dmem_hwdata, 1'b1);
+                                else
+                                    imem_hrdata_l <= scr1_read_mem({imem_haddr[SCR1_AHB_WIDTH-1:2], 2'b00}, imem_be, imem_wr_hazard, dmem_hwdata, 1'b0);
+                            end
+                        end
+                        default : begin
+                            imem_ahb_addr  <= 'x;
+                            imem_hrdata_l  <= 'x;
+                        end
+                    endcase
+                end
+            end
+            default : begin
+                imem_ahb_addr  <= 'x;
+                imem_hrdata_l  <= 'x;
+            end
+        endcase
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Instruction Memory responce
+//-------------------------------------------------------------------------------
+always_comb begin
+    imem_hready = 1'b0;
+    imem_hresp  = SCR1_HRESP_OKAY;
+    imem_hrdata = 'x;
+    case (imem_ahb_state)
+        SCR1_AHB_STATE_IDLE : begin
+            if (imem_req_ack) begin
+                imem_hready = 1'b1;
+            end
+        end
+        SCR1_AHB_STATE_DATA : begin
+            if (imem_req_ack) begin
+                imem_hready = 1'b1;
+                if (~scr1_check_err_addr(imem_ahb_addr)) begin
+                    imem_hresp  = SCR1_HRESP_ERROR;
+                end else begin
+                    imem_hrdata = imem_hrdata_l;
+                end
+            end
+        end
+        default : begin
+        end
+    endcase
+end
+
+//-------------------------------------------------------------------------------
+// Data memory ready
+//-------------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        dmem_req_ack_stall <= dmem_req_ack_stall_in;
+        dmem_req_ack_rnd   <= 1'b0;
+    end else begin
+        if (dmem_req_ack_stall == 32'd0) begin
+            dmem_req_ack_rnd <= $random;
+        end else begin
+            dmem_req_ack_stall <= {dmem_req_ack_stall[0], dmem_req_ack_stall[31:1]};
+        end
+    end
+end
+
+assign dmem_req_ack = (dmem_req_ack_stall == 32'd0) ?  dmem_req_ack_rnd : dmem_req_ack_stall[0];
+
+//-------------------------------------------------------------------------------
+// Data memory AHB FSM
+//-------------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        dmem_ahb_state <= SCR1_AHB_STATE_IDLE;
+    end else begin
+        case (dmem_ahb_state)
+            SCR1_AHB_STATE_IDLE : begin
+                if (dmem_req_ack) begin
+                    case (dmem_htrans)
+                        SCR1_HTRANS_IDLE : begin
+                            dmem_ahb_state <= SCR1_AHB_STATE_IDLE;
+                        end
+                        SCR1_HTRANS_NONSEQ : begin
+                            dmem_ahb_state    <= SCR1_AHB_STATE_DATA;
+                        end
+                        default : begin
+                            dmem_ahb_state    <= SCR1_AHB_STATE_ERR;
+                        end
+                    endcase
+                end
+            end
+            SCR1_AHB_STATE_DATA : begin
+                if (dmem_req_ack) begin
+                    case (dmem_htrans)
+                        SCR1_HTRANS_IDLE : begin
+                            dmem_ahb_state    <= SCR1_AHB_STATE_IDLE;
+                        end
+                        SCR1_HTRANS_NONSEQ : begin
+                            if (~dmem_hwrite & scr1_check_err_addr(dmem_haddr)) begin
+                                case (dmem_haddr)
+                                    SCR1_IRQ_ADDR : begin
+                                        // Skip access, switch to SCR1_AHB_STATE_IDLE
+                                        dmem_ahb_state    <= SCR1_AHB_STATE_IDLE;
+                                    end
+                                    SCR1_MEM_ERR_PTR : begin
+                                        // Skip access, switch to SCR1_AHB_STATE_IDLE
+                                        dmem_ahb_state    <= SCR1_AHB_STATE_IDLE;
+                                    end
+                                    default : begin
+                                        dmem_ahb_state    <= SCR1_AHB_STATE_DATA;
+                                    end
+                                endcase
+                            end
+                        end
+                        default : begin
+                            dmem_ahb_state    <= SCR1_AHB_STATE_ERR;
+                        end
+                    endcase
+                end
+            end
+            default : begin
+                dmem_ahb_state    <= SCR1_AHB_STATE_ERR;
+            end
+        endcase
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Address command latch
+//-------------------------------------------------------------------------------
+assign dmem_be = scr1_be_form(dmem_haddr[1:0], dmem_hsize);
+assign dmem_wr_hazard = (dmem_ahb_wr & (dmem_haddr[SCR1_AHB_WIDTH-1:2] == dmem_ahb_addr[SCR1_AHB_WIDTH-1:2])) ? dmem_be & dmem_ahb_be : '0;
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        dmem_ahb_addr  <= 'x;
+        dmem_ahb_wr    <= 1'b0;
+        dmem_ahb_size  <= SCR1_HSIZE_ERR;
+        dmem_ahb_be    <= '0;
+    end else begin
+        case (dmem_ahb_state)
+            SCR1_AHB_STATE_IDLE : begin
+                if (dmem_req_ack) begin
+                    case (dmem_htrans)
+                        SCR1_HTRANS_IDLE : begin
+                        end
+                        SCR1_HTRANS_NONSEQ : begin
+                            dmem_ahb_addr <= dmem_haddr;
+                            dmem_ahb_wr   <= dmem_hwrite;
+                            dmem_ahb_size <= dmem_hsize;
+                            dmem_ahb_be   <= dmem_be;
+                            if (~dmem_hwrite & scr1_check_err_addr(dmem_haddr)) begin
+                                case (dmem_haddr)
+`ifdef SCR1_IPIC_EN
+                                    SCR1_IRQ_ADDR : begin
+                                        dmem_hrdata_l <= '0;
+                                        dmem_hrdata_l[SCR1_IRQ_LINES_NUM-1:0] <= irq_reg;
+                                    end
+`endif // SCR1_IPIC_EN
+                                    SCR1_MEM_ERR_PTR : begin
+                                        dmem_hrdata_l <= mem_err_ptr;
+                                    end
+                                    default : begin
+                                        if(mirage_rangeen & dmem_haddr>=mirage_adrlo & dmem_haddr<mirage_adrhi)
+                                            dmem_hrdata_l <= scr1_read_mem({dmem_haddr[SCR1_AHB_WIDTH-1:2], 2'b00}, dmem_be, dmem_wr_hazard, dmem_hwdata, 1'b1);
+                                        else
+                                            dmem_hrdata_l <= scr1_read_mem({dmem_haddr[SCR1_AHB_WIDTH-1:2], 2'b00}, dmem_be, dmem_wr_hazard, dmem_hwdata, 1'b0);
+                                    end
+                                endcase
+                            end
+                        end
+                        default : begin
+                            dmem_ahb_addr  <= 'x;
+                            dmem_ahb_wr    <= 'x;
+                            dmem_ahb_size  <= SCR1_HSIZE_ERR;
+                            dmem_hrdata_l  <= 'x;
+                        end
+                    endcase
+                end
+            end
+            SCR1_AHB_STATE_DATA : begin
+                if (dmem_req_ack) begin
+                    case (dmem_htrans)
+                        SCR1_HTRANS_IDLE : begin
+                            dmem_ahb_addr     <= 'x;
+                            dmem_ahb_wr       <= 1'b0;
+                            dmem_ahb_size     <= SCR1_HSIZE_ERR;
+                        end
+                        SCR1_HTRANS_NONSEQ : begin
+                            dmem_ahb_addr <= dmem_haddr;
+                            dmem_ahb_wr   <= dmem_hwrite;
+                            dmem_ahb_size <= dmem_hsize;
+                            dmem_ahb_be   <= dmem_be;
+                            if (~dmem_hwrite & scr1_check_err_addr(dmem_haddr)) begin
+                                case (dmem_haddr)
+`ifdef SCR1_IPIC_EN
+                                    SCR1_IRQ_ADDR : begin
+                                        // Skip access, switch to SCR1_AHB_STATE_IDLE
+                                    end
+`endif // SCR1_IPIC_EN
+                                    SCR1_MEM_ERR_PTR : begin
+                                        // Skip access, switch to SCR1_AHB_STATE_IDLE
+                                    end
+                                    default : begin
+                                        if(mirage_rangeen & dmem_haddr>=mirage_adrlo & dmem_haddr<mirage_adrhi)
+                                            dmem_hrdata_l <= scr1_read_mem({dmem_haddr[SCR1_AHB_WIDTH-1:2], 2'b00}, dmem_be, dmem_wr_hazard, dmem_hwdata, 1'b1);
+                                        else
+                                            dmem_hrdata_l <= scr1_read_mem({dmem_haddr[SCR1_AHB_WIDTH-1:2], 2'b00}, dmem_be, dmem_wr_hazard, dmem_hwdata, 1'b0);
+                                    end
+                                endcase
+                            end
+                        end
+                        default : begin
+                            dmem_ahb_addr  <= 'x;
+                            dmem_ahb_wr    <= 'x;
+                            dmem_ahb_size  <= SCR1_HSIZE_ERR;
+                            dmem_ahb_be    <= 'x;
+                            dmem_hrdata_l  <= 'x;
+                        end
+                    endcase
+                end
+            end
+            default : begin
+                dmem_ahb_addr  <= 'x;
+                dmem_ahb_wr    <= 'x;
+                dmem_ahb_size  <= SCR1_HSIZE_ERR;
+                dmem_hrdata_l  <= 'x;
+            end
+        endcase
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Data Memory responce
+//-------------------------------------------------------------------------------
+always_comb begin
+    dmem_hready = 1'b0;
+    dmem_hresp  = SCR1_HRESP_OKAY;
+    dmem_hrdata = 'x;
+    case (dmem_ahb_state)
+        SCR1_AHB_STATE_IDLE : begin
+            if (dmem_req_ack) begin
+                dmem_hready = 1'b1;
+            end
+        end
+        SCR1_AHB_STATE_DATA : begin
+            if (dmem_req_ack) begin
+                dmem_hready = 1'b1;
+                if (~scr1_check_err_addr(dmem_ahb_addr)) begin
+                    dmem_hresp  = SCR1_HRESP_ERROR;
+                end else begin
+                    if (~dmem_ahb_wr) begin
+                        dmem_hrdata = dmem_hrdata_l;
+                    end
+                end
+            end
+        end
+        default : begin
+        end
+    endcase
+end
+
+//-------------------------------------------------------------------------------
+// Data Memory write
+//-------------------------------------------------------------------------------
+always @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+`ifdef SCR1_IPIC_EN
+        irq_reg     <= '0;
+`endif // SCR1_IPIC_EN
+        mem_err_ptr <= SCR1_MEM_ERR_ADDR;
+        if (test_file_init) $readmemh(test_file, memory);
+    end else begin
+        if ((dmem_ahb_state == SCR1_AHB_STATE_DATA) & dmem_req_ack & dmem_ahb_wr) begin
+            if (scr1_check_err_addr(dmem_ahb_addr)) begin
+                case (dmem_ahb_addr)
+                    SCR1_PRINT_ADDR : begin
+                        $write("%c", dmem_hwdata[7:0]);
+                    end
+`ifdef SCR1_IPIC_EN
+                    SCR1_IRQ_ADDR : begin
+                        irq_reg <= dmem_hwdata[SCR1_IRQ_LINES_NUM-1:0];
+                    end
+`endif // SCR1_IPIC_EN
+                    SCR1_MEM_ERR_PTR : begin
+                        mem_err_ptr <= dmem_hwdata;
+                    end
+                    default : begin
+                        if(mirage_rangeen & dmem_ahb_addr>=mirage_adrlo & dmem_ahb_addr<mirage_adrhi)
+                            scr1_write_mem({dmem_ahb_addr[SCR1_AHB_WIDTH-1:2], 2'b00}, dmem_ahb_be, dmem_hwdata, 1'b1);
+                        else
+                            scr1_write_mem({dmem_ahb_addr[SCR1_AHB_WIDTH-1:2], 2'b00}, dmem_ahb_be, dmem_hwdata, 1'b0);
+                    end
+                endcase
+            end
+        end
+    end
+end
+
+`ifdef SCR1_IPIC_EN
+assign irq_lines = irq_reg;
+`endif // SCR1_IPIC_EN
+
+endmodule : scr1_memory_tb_ahb
diff --git a/third_party/tests/Scr1/src/tb/scr1_memory_tb_axi.sv b/third_party/tests/Scr1/src/tb/scr1_memory_tb_axi.sv
new file mode 100644
index 0000000..0370eb5
--- /dev/null
+++ b/third_party/tests/Scr1/src/tb/scr1_memory_tb_axi.sv
@@ -0,0 +1,348 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_memory_tb_axi.sv>
+/// @brief      AXI memory testbench
+///
+
+`include "scr1_ipic.svh"
+
+module scr1_memory_tb_axi #(
+    parameter SIZE   = 1*1024*1024,
+    parameter N_IF   = 2,
+    parameter W_ID   = 4,
+    parameter W_ADR  = 32,
+    parameter W_DATA = 32
+)
+(
+    // System
+    input   logic                          rst_n,
+    input   logic                          clk,
+`ifdef SCR1_IPIC_EN
+    output  logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines,
+`endif // SCR1_IPIC_EN
+
+    // Write address channel
+    input  logic [N_IF-1:0]                awvalid,
+    input  logic [N_IF-1:0] [W_ID-1:0]     awid,
+    input  logic [N_IF-1:0] [W_ADR-1:0]    awaddr,
+    input  logic [N_IF-1:0] [2:0]          awsize,
+    input  logic [N_IF-1:0] [7:0]          awlen,
+    output logic [N_IF-1:0]                awready,
+
+    // Write data channel
+    input  logic [N_IF-1:0]                wvalid,
+    input  logic [N_IF-1:0] [W_DATA-1:0]   wdata,
+    input  logic [N_IF-1:0] [W_DATA/8-1:0] wstrb,
+    input  logic [N_IF-1:0]                wlast,
+    output logic [N_IF-1:0]                wready,
+
+    // Write response channel
+    input  logic [N_IF-1:0]                bready,
+    output logic [N_IF-1:0]                bvalid,
+    output logic [N_IF-1:0] [W_ID-1:0]     bid,
+    output logic [N_IF-1:0] [1:0]          bresp,
+
+    // Read address channel
+    input  logic [N_IF-1:0]                arvalid,
+    input  logic [N_IF-1:0] [W_ID-1:0]     arid,
+    input  logic [N_IF-1:0] [W_ADR-1:0]    araddr,
+    input  logic [N_IF-1:0] [1:0]          arburst,
+    input  logic [N_IF-1:0] [2:0]          arsize,
+    input  logic [N_IF-1:0] [7:0]          arlen,
+    output logic [N_IF-1:0]                arready,
+
+    // Read data channel
+    input  logic [N_IF-1:0]                rready,
+    output logic [N_IF-1:0]                rvalid,
+    output logic [N_IF-1:0] [W_ID-1:0]     rid,
+    output logic [N_IF-1:0] [W_DATA-1:0]   rdata,
+    output logic [N_IF-1:0]                rlast,
+    output logic [N_IF-1:0] [1:0]          rresp
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters
+//-------------------------------------------------------------------------------
+localparam [W_ADR-1:0]                      PRINT_ADDR     = 32'hF000_0000;
+localparam [W_ADR-1:0]                      IRQ_ADDR       = 32'hF000_0100;
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+logic  [7:0]                                memory [0:SIZE-1];
+logic  [N_IF-1:0] [W_ADR-1:0]               awaddr_hold;
+logic  [N_IF-1:0] [2:0]                     awsize_hold;
+genvar                                      gi;
+genvar                                      gj;
+
+`ifdef VERILATOR
+logic [255:0]                               test_file;
+`else // VERILATOR
+string                                      test_file;
+`endif // VERILATOR
+bit                                         test_file_init;
+
+//-------------------------------------------------------------------------------
+// Local functions
+//-------------------------------------------------------------------------------
+
+function automatic logic [W_DATA-1:0] mem_read (
+    logic [W_ADR:0] adr,
+    int             bytes_num,
+    int             bytes_max
+    );
+
+    logic [W_ADR:0] byte_lane;
+
+    mem_read  = 'x;
+    byte_lane = 0;
+
+    for(int i=0; i<$clog2(bytes_max); ++i) begin
+        byte_lane[i] = adr[i];
+    end
+
+    for(int i=byte_lane; i<bytes_max & bytes_num!=0; ++i) begin
+`ifdef SCR1_IPIC_EN
+        if (adr[W_ADR-1:1]==IRQ_ADDR[W_ADR-1:1]) begin
+            if( i*8 < SCR1_IRQ_LINES_NUM ) begin
+                if( SCR1_IRQ_LINES_NUM < 8 ) begin
+                    mem_read[(i*8)+:8] = irq_lines;
+                end else begin
+                    mem_read[(i*8)+:8] = irq_lines[(i*8)+:8];
+                end
+            end
+        end else begin
+            mem_read[(i*8)+:8] = memory[adr];
+        end
+`else // SCR1_IPIC_EN
+        mem_read[(i*8)+:8] = memory[adr];
+`endif // SCR1_IPIC_EN
+        adr = adr+1'b1;
+        bytes_num = bytes_num - 1'b1;
+    end
+endfunction : mem_read
+
+function automatic void mem_write (
+    logic [W_ADR-1:0]      adr,
+    logic [W_DATA-1:0]     data,
+    logic [(W_DATA/8)-1:0] bytes_en,
+    int                    bytes_num,
+    int                    bytes_max
+    );
+
+    logic[W_ADR:0]         byte_lane;
+
+    byte_lane = 0;
+
+    for(int i=0; i<$clog2(bytes_max); ++i) begin
+        byte_lane[i] = adr[i];
+    end
+
+    for(int i=byte_lane; i<bytes_max & bytes_num!=0; ++i) begin
+        if(bytes_en[i] & adr==PRINT_ADDR) begin
+            $write("%c",data[(i*8)+:8]);
+`ifdef SCR1_IPIC_EN
+        end else if(bytes_en[i] & adr[W_ADR-1:1]==IRQ_ADDR[W_ADR-1:1]) begin
+            if( i*8 < SCR1_IRQ_LINES_NUM ) begin
+                if( SCR1_IRQ_LINES_NUM < 8 ) begin
+                    irq_lines = data[SCR1_IRQ_LINES_NUM-1:0];
+                end else begin
+                    irq_lines[(i*8)+:8] = data[(i*8)+:8];
+                end
+            end
+`endif // SCR1_IPIC_EN
+        end else if(bytes_en[i]) begin
+            memory[adr] = data[(i*8)+:8];
+        end
+        adr       = adr+1'b1;
+        bytes_num = bytes_num-1'b1;
+    end
+endfunction : mem_write
+
+generate for(gi=0; gi<N_IF; ++gi) begin : rw_if
+
+//-------------------------------------------------------------------------------
+// Read operation
+//-------------------------------------------------------------------------------
+always @(posedge clk, negedge rst_n) begin
+    if(~rst_n) begin
+        arready[gi] <= 1'b1;
+        rvalid[gi]  <= 1'b0;
+        rresp[gi]   <= 2'd3;
+        rdata[gi]   <= 'x;
+        rlast[gi]   <= 1'b0;
+        rid[gi]     <= '0;
+    end else begin
+
+        // Read data: acked
+        if( rvalid[gi] & rready[gi] ) begin
+            arready[gi] <= 1'b1;
+            rvalid[gi]  <= 1'b0;
+        end else if( rvalid[gi] & !rready[gi] ) begin
+            arready[gi] <= 1'b0;
+        end
+
+        // Read data: valid
+        if( arvalid[gi] & arready[gi] & ~(rvalid[gi] & !rready[gi]) ) begin
+
+            rvalid[gi] <= 1'b1;
+            rresp[gi]  <= '0;
+            rlast[gi]  <= 1'b1;
+            rid[gi]    <= arid[gi];
+
+            rdata[gi]  <= mem_read( araddr[gi],
+                                    2**arsize[gi],
+                                    W_DATA/8 );
+        end
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Write operation
+//-------------------------------------------------------------------------------
+always @(posedge clk, negedge rst_n) begin
+    if(~rst_n) begin
+        bvalid[gi]  <= '0;
+        bresp[gi]   <= 2'd3;
+        awready[gi] <= 1'b1;
+        wready[gi]  <= 1'b1;
+        if (test_file_init) $readmemh(test_file, memory);
+    end else begin
+
+        // Write data: response
+        if( bvalid[gi] & bready[gi] ) begin
+            bvalid[gi]  <= 1'b0;
+            awready[gi] <= 1'b1;
+            wready[gi]  <= 1'b1;
+        end else if( bvalid[gi] & !bready[gi] ) begin
+            awready[gi] <= 1'b0;
+            wready[gi]  <= 1'b0;
+        end
+
+        // Write data: get address
+        if( awvalid[gi] & awready[gi] & ~(bvalid[gi] & !bready[gi]) ) begin
+            bid <= awid[gi];
+            if( ~wvalid[gi] ) begin
+                awaddr_hold[gi] <= awaddr[gi];
+                awsize_hold[gi] <= awsize[gi];
+                awready[gi] <= 1'b0;
+            end
+        end
+
+        // Write data: get data
+        if( wvalid[gi] & wready[gi] & wlast[gi] ) begin
+            bvalid[gi] <= 1'b1;
+            bresp[gi]  <= '0;
+
+            mem_write( awready[gi] ? awaddr[gi] : awaddr_hold[gi],
+                       wdata[gi],
+                       wstrb[gi],
+                       2**(awready[gi] ? awsize[gi] : awsize_hold[gi]),
+                       W_DATA/8 );
+        end
+    end
+end
+
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertions
+//-------------------------------------------------------------------------------
+SVA_TBMEM_AWADDR_404 :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        awvalid[gi] |-> awaddr[gi]<SIZE | awaddr[gi]==PRINT_ADDR |
+        awaddr[gi]==IRQ_ADDR
+    )
+    else $error("TBMEM: awaddr[%0d] >= SIZE",gi);
+
+SVA_TBMEM_X_AWVALID :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown(awvalid[gi])
+    )
+    else $error("TBMEM: X state on awvalid[%0d]",gi);
+
+SVA_TBMEM_X_AWCHANNEL :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        awvalid[gi] |-> !$isunknown({awid[gi],awaddr[gi],awsize[gi],awlen[gi]})
+    )
+    else $error("TBMEM: X state on aw channel[%0d]",gi);
+
+SVA_TBMEM_AWLEN :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        awvalid[gi] |-> awlen[gi]==0
+    )
+    else $error("TBMEM: awlen[%0d] = %0d is not supported",gi,awlen[gi]);
+
+SVA_TBMEM_X_WVALID :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown(wvalid[gi])
+    )
+    else $error("TBMEM: X state on wvalid[%0d]",gi);
+
+SVA_TBMEM_X_WCHANNEL :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        wvalid[gi] |-> !$isunknown({wstrb[gi],wlast[gi]})
+    )
+    else $error("TBMEM: X state on w channel[%0d]",gi);
+
+for(gj=0; gj<W_DATA/8; ++gj) begin : SVA_TBMEM_X_WSTRB
+WDATA :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        (wvalid[gi] & wstrb[gi][gj]) |-> !$isunknown(wdata[gi][(gj*8)+:8])
+    )
+    else $error("TBMEM: X state on wdata with wstrb[%0d][%0d]",gi,gj);
+end
+
+SVA_TBMEM_X_BREADY :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        bvalid[gi] |-> !$isunknown(bready[gi])
+    )
+    else $error("TBMEM: X state on bready[%0d]",gi);
+
+SVA_TBMEM_ARADDR_404 :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        arvalid[gi] |-> araddr[gi]<SIZE | araddr[gi]==PRINT_ADDR |
+        awaddr[gi]==IRQ_ADDR
+    )
+    else $error("TBMEM: awaddr[%0d] >= SIZE",gi);
+
+SVA_TBMEM_X_ARVALID :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        !$isunknown(arvalid[gi])
+    )
+    else $error("TBMEM: X state on arvalid[%0d]",gi);
+
+SVA_TBMEM_X_ARCHANNEL :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        arvalid[gi] |-> !$isunknown({arid[gi],araddr[gi],arsize[gi],arlen[gi]})
+    )
+    else $error("TBMEM: X state on ar channel[%0d]",gi);
+
+SVA_TBMEM_ARLEN :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        arvalid[gi] |-> arlen[gi]==0
+    )
+    else $error("TBMEM: arlen[%0d] = %0d is not supported",gi,arlen[gi]);
+
+SVA_TBMEM_X_RREADY :
+    assert property (
+        @(negedge clk) disable iff (~rst_n)
+        rvalid[gi] |-> !$isunknown(rready[gi])
+    )
+    else $error("TBMEM: X state on rready[%0d]",gi);
+
+`endif // VERILATOR
+
+end endgenerate
+
+endmodule : scr1_memory_tb_axi
diff --git a/third_party/tests/Scr1/src/tb/scr1_top_tb_ahb.sv b/third_party/tests/Scr1/src/tb/scr1_top_tb_ahb.sv
new file mode 100644
index 0000000..7485c89
--- /dev/null
+++ b/third_party/tests/Scr1/src/tb/scr1_top_tb_ahb.sv
@@ -0,0 +1,457 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_top_tb_ahb.sv>
+/// @brief      SCR1 top testbench AHB
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_ahb.svh"
+`ifdef SCR1_IPIC_EN
+`include "scr1_ipic.svh"
+`endif // SCR1_IPIC_EN
+
+module scr1_top_tb_ahb (
+`ifdef VERILATOR
+    input logic clk
+`endif // VERILATOR
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters
+//-------------------------------------------------------------------------------
+localparam                          SCR1_MEM_SIZE       = 1024*1024;
+localparam logic [`SCR1_XLEN-1:0]   SCR1_EXIT_ADDR      = 32'h000000F8;
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+logic                                   rst_n;
+`ifndef VERILATOR
+logic                                   clk         = 1'b0;
+`endif // VERILATOR
+logic                                   rtc_clk     = 1'b0;
+`ifdef SCR1_IPIC_EN
+logic [SCR1_IRQ_LINES_NUM-1:0]          irq_lines;
+`else // SCR1_IPIC_EN
+logic                                   ext_irq     = 1'b0;
+`endif // SCR1_IPIC_EN
+logic                                   soft_irq    = 1'b0;
+logic [31:0]                            fuse_mhartid;
+integer                                 imem_req_ack_stall;
+integer                                 dmem_req_ack_stall;
+
+logic                                   test_mode   = 1'b0;
+`ifdef SCR1_DBGC_EN
+logic                                   trst_n;
+logic                                   tck;
+logic                                   tms;
+logic                                   tdi;
+logic                                   tdo;
+logic                                   tdo_en;
+`endif // SCR1_DBGC_EN
+
+// Instruction Memory Interface
+logic   [3:0]                           imem_hprot;
+logic   [2:0]                           imem_hburst;
+logic   [2:0]                           imem_hsize;
+logic   [1:0]                           imem_htrans;
+logic   [SCR1_AHB_WIDTH-1:0]            imem_haddr;
+logic                                   imem_hready;
+logic   [SCR1_AHB_WIDTH-1:0]            imem_hrdata;
+logic                                   imem_hresp;
+
+// Memory Interface
+logic   [3:0]                           dmem_hprot;
+logic   [2:0]                           dmem_hburst;
+logic   [2:0]                           dmem_hsize;
+logic   [1:0]                           dmem_htrans;
+logic   [SCR1_AHB_WIDTH-1:0]            dmem_haddr;
+logic                                   dmem_hwrite;
+logic   [SCR1_AHB_WIDTH-1:0]            dmem_hwdata;
+logic                                   dmem_hready;
+logic   [SCR1_AHB_WIDTH-1:0]            dmem_hrdata;
+logic                                   dmem_hresp;
+
+int unsigned                            f_results;
+int unsigned                            f_info;
+string                                  s_results;
+string                                  s_info;
+`ifdef VERILATOR
+logic [255:0]                           test_file;
+`else // VERILATOR
+string                                  test_file;
+`endif // VERILATOR
+
+bit                                     test_running;
+int unsigned                            tests_passed;
+int unsigned                            tests_total;
+
+bit [1:0]                               rst_cnt;
+bit                                     rst_init;
+
+
+`ifdef VERILATOR
+function bit is_compliance (logic [255:0] testname);
+    bit res;
+    logic [79:0] pattern;
+begin
+    pattern = 80'h636f6d706c69616e6365; // compliance
+    res = 0;
+    for (int i = 0; i<= 176; i++) begin
+        if(testname[i+:80] == pattern) begin
+            return ~res;
+        end
+    end
+    return res;
+end
+endfunction : is_compliance
+
+function logic [255:0] get_filename (logic [255:0] testname);
+logic [255:0] res;
+int i, j;
+begin
+    testname[15:8] = 8'h66;
+    testname[23:16] = 8'h6C;
+    testname[31:24] = 8'h65;
+
+    for (i = 0; i <= 248; i += 8) begin
+        if (testname[i+:8] == 0) begin
+            break;
+        end
+    end
+    i -= 8;
+    for (j = 255; i > 0;i -= 8) begin
+        res[j-:8] = testname[i+:8];
+        j -= 8;
+    end
+    for (; j >= 0;j -= 8) begin
+        res[j-:8] = 0;
+    end
+
+    return res;
+end
+endfunction : get_filename
+
+function logic [255:0] get_ref_filename (logic [255:0] testname);
+logic [255:0] res;
+int i, j;
+logic [79:0] pattern;
+begin
+    pattern = 80'h636f6d706c69616e6365; // compliance
+
+    for(int i = 0; i <= 176; i++) begin
+        if(testname[i+:80] == pattern) begin
+            testname[(i-8)+:88] = 0;
+            break;
+        end
+    end
+
+    for(i = 32; i <= 248; i += 8) begin
+        if(testname[i+:8] == 0) break;
+    end
+    i -= 8;
+    for(j = 255; i > 32;i -= 8) begin
+        res[j-:8] = testname[i+:8];
+        j -= 8;
+    end
+    for(; j >=0;j -= 8) begin
+        res[j-:8] = 0;
+    end
+
+    return res;
+end
+endfunction : get_ref_filename
+
+`else // VERILATOR
+function bit is_compliance (string testname);
+begin
+    return (testname.substr(0, 9) == "compliance");
+end
+endfunction : is_compliance
+
+function string get_filename (string testname);
+int length;
+begin
+    length = testname.len();
+    testname[length-1] = "f";
+    testname[length-2] = "l";
+    testname[length-3] = "e";
+    
+    return testname;
+end
+endfunction : get_filename
+
+function string get_ref_filename (string testname);
+begin
+    return testname.substr(11, testname.len() - 5);
+end
+endfunction : get_ref_filename
+
+`endif // VERILATOR
+
+`ifndef VERILATOR
+always #5   clk     = ~clk;         // 100 MHz
+always #500 rtc_clk = ~rtc_clk;     // 1 MHz
+`endif // VERILATOR
+
+// Reset logic
+assign rst_n = &rst_cnt;
+
+always_ff @(posedge clk) begin
+    if (rst_init)       rst_cnt <= '0;
+    else if (~&rst_cnt) rst_cnt <= rst_cnt + 1'b1;
+end
+
+
+`ifdef SCR1_DBGC_EN
+initial begin
+    trst_n  = 1'b0;
+    tck     = 1'b0;
+    tdi     = 1'b0;
+    #900ns trst_n   = 1'b1;
+    #500ns tms      = 1'b1;
+    #800ns tms      = 1'b0;
+    #500ns trst_n   = 1'b0;
+    #100ns tms      = 1'b1;
+end
+`endif // SCR1_DBGC_EN
+
+//-------------------------------------------------------------------------------
+// Run tests
+//-------------------------------------------------------------------------------
+
+initial begin
+    $value$plusargs("imem_pattern=%h", imem_req_ack_stall);
+    $value$plusargs("dmem_pattern=%h", dmem_req_ack_stall);
+    $value$plusargs("test_info=%s", s_info);
+    $value$plusargs("test_results=%s", s_results);
+
+    fuse_mhartid = 0;
+
+    f_info      = $fopen(s_info, "r");
+    f_results   = $fopen(s_results, "a");
+end
+
+always_ff @(posedge clk) begin
+    if (test_running) begin
+        rst_init <= 1'b0;
+        if ((i_top.i_core_top.i_pipe_top.curr_pc == SCR1_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
+        `ifdef VERILATOR
+        logic [255:0] full_filename;
+        full_filename = test_file;
+        `else // VERILATOR
+        string full_filename;
+        full_filename = test_file;
+        `endif // VERILATOR
+
+            if (is_compliance(test_file)) begin
+                bit test_pass;
+                logic [31:0] tmpv, start, stop, ref_data, test_data;
+                integer fd;
+                `ifdef VERILATOR
+                logic [2047:0] tmpstr;
+                `else // VERILATOR
+                string tmpstr;
+                `endif // VERILATOR
+                
+                test_running <= 1'b0;
+                test_pass = 1;
+
+                $sformat(tmpstr, "riscv64-unknown-elf-readelf -s %s | grep 'begin_signature\\|end_signature' | awk '{print $2}' > elfinfo", get_filename(test_file));
+                fd = $fopen("script.sh", "w");
+                if (fd == 0) begin
+                    $write("Can't open script.sh\n");
+                    test_pass = 0;
+                end
+                $fwrite(fd, "%s", tmpstr);
+                $fclose(fd);
+
+                $system("sh script.sh");
+
+                fd = $fopen("elfinfo", "r");
+                if (fd == 0) begin
+                    $write("Can't open elfinfo\n");
+                    test_pass = 0;
+                end
+                if ($fscanf(fd,"%h\n%h", start, stop) != 2) begin
+                    $write("Wrong elfinfo data\n");
+                    test_pass = 0;
+                end
+                if (start > stop) begin
+                    tmpv = start;
+                    start = stop;
+                    stop = tmpv;
+                end
+                $fclose(fd);
+
+                $sformat(tmpstr, "riscv_compliance/ref_data/%s", get_ref_filename(test_file));
+                fd = $fopen(tmpstr,"r");
+                if (fd == 0) begin
+                    $write("Can't open reference_data file: %s\n", tmpstr);
+                    test_pass = 0;
+                end
+                while (!$feof(fd) && (start != stop)) begin
+                    $fscanf(fd, "0x%h,\n", ref_data);
+                    test_data = {i_memory_tb.memory[start+3], i_memory_tb.memory[start+2], i_memory_tb.memory[start+1], i_memory_tb.memory[start]};
+                    test_pass &= (ref_data == test_data);
+                    start += 4;
+                end
+                $fclose(fd);
+
+                tests_total += 1;
+                tests_passed += test_pass;
+                $fwrite(f_results, "%s\t\t%s\n", test_file, (test_pass ? "PASS" : "__FAIL"));
+                if (test_pass) begin
+                    $write("\033[0;32mTest passed\033[0m\n");
+                end else begin
+                    $write("\033[0;31mTest failed\033[0m\n");
+                end
+            end else begin
+                bit test_pass;
+                test_running <= 1'b0;
+                test_pass = (i_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] == 0);
+                tests_total     += 1;
+                tests_passed    += test_pass;
+                $fwrite(f_results, "%s\t\t%s\n", test_file, (test_pass ? "PASS" : "__FAIL"));
+                if (test_pass) begin
+                    $write("\033[0;32mTest passed\033[0m\n");
+                end else begin
+                    $write("\033[0;31mTest failed\033[0m\n");
+                end
+            end
+        end
+    end else begin
+`ifdef VERILATOR
+        if ($fgets(test_file,f_info)) begin
+`else // VERILATOR
+        if (!$feof(f_info)) begin
+            $fscanf(f_info, "%s\n", test_file);
+`endif // VERILATOR
+            // Launch new test
+`ifdef SCR1_TRACE_LOG_EN
+            i_top.i_core_top.i_pipe_top.i_tracelog.test_name = test_file;
+`endif
+            i_memory_tb.test_file = test_file;
+            i_memory_tb.test_file_init = 1'b1;
+            $write("\033[0;34m---Test: %s\033[0m\n", test_file);
+            test_running <= 1'b1;
+            rst_init <= 1'b1;
+        end else begin
+            // Exit
+            $display("\n#--------------------------------------");
+            $display("# Summary: %0d/%0d tests passed", tests_passed, tests_total);
+            $display("#--------------------------------------\n");
+            $fclose(f_info);
+            $fclose(f_results);
+            $finish();
+        end
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Core instance
+//-------------------------------------------------------------------------------
+scr1_top_ahb i_top (
+    // Reset
+    .pwrup_rst_n            (rst_n                  ),
+    .rst_n                  (rst_n                  ),
+    .cpu_rst_n              (rst_n                  ),
+`ifdef SCR1_DBGC_EN
+    .ndm_rst_n_out          (),
+`endif // SCR1_DBGC_EN
+
+    // Clock
+    .clk                    (clk                    ),
+    .rtc_clk                (rtc_clk                ),
+
+    // Fuses
+    .fuse_mhartid           (fuse_mhartid           ),
+`ifdef SCR1_DBGC_EN
+    .fuse_idcode            (`SCR1_TAP_IDCODE       ),
+`endif // SCR1_DBGC_EN
+
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    .irq_lines              (irq_lines              ),
+`else // SCR1_IPIC_EN
+    .ext_irq                (ext_irq                ),
+`endif // SCR1_IPIC_EN
+    .soft_irq               (soft_irq               ),
+
+    // DFT
+    .test_mode              (1'b0                   ),
+    .test_rst_n             (1'b1                   ),
+
+`ifdef SCR1_DBGC_EN
+    // JTAG
+    .trst_n                 (trst_n                 ),
+    .tck                    (tck                    ),
+    .tms                    (tms                    ),
+    .tdi                    (tdi                    ),
+    .tdo                    (tdo                    ),
+    .tdo_en                 (tdo_en                 ),
+`endif // SCR1_DBGC_EN
+
+    // Instruction Memory Interface
+    .imem_hprot         (imem_hprot     ),
+    .imem_hburst        (imem_hburst    ),
+    .imem_hsize         (imem_hsize     ),
+    .imem_htrans        (imem_htrans    ),
+    .imem_hmastlock     (),
+    .imem_haddr         (imem_haddr     ),
+    .imem_hready        (imem_hready    ),
+    .imem_hrdata        (imem_hrdata    ),
+    .imem_hresp         (imem_hresp     ),
+
+    // Data Memory Interface
+    .dmem_hprot         (dmem_hprot     ),
+    .dmem_hburst        (dmem_hburst    ),
+    .dmem_hsize         (dmem_hsize     ),
+    .dmem_htrans        (dmem_htrans    ),
+    .dmem_hmastlock     (),
+    .dmem_haddr         (dmem_haddr     ),
+    .dmem_hwrite        (dmem_hwrite    ),
+    .dmem_hwdata        (dmem_hwdata    ),
+    .dmem_hready        (dmem_hready    ),
+    .dmem_hrdata        (dmem_hrdata    ),
+    .dmem_hresp         (dmem_hresp     )
+);
+
+//-------------------------------------------------------------------------------
+// Memory instance
+//-------------------------------------------------------------------------------
+scr1_memory_tb_ahb #(
+    .SCR1_MEM_POWER_SIZE    ($clog2(SCR1_MEM_SIZE))
+) i_memory_tb (
+    // Control
+    .rst_n                  (rst_n),
+    .clk                    (clk),
+`ifdef SCR1_IPIC_EN
+    .irq_lines              (irq_lines),
+`endif // SCR1_IPIC_EN
+    .imem_req_ack_stall_in  (imem_req_ack_stall),
+    .dmem_req_ack_stall_in  (dmem_req_ack_stall ),
+
+    // Instruction Memory Interface
+    // .imem_hprot             (imem_hprot ),
+    // .imem_hburst            (imem_hburst),
+    .imem_hsize             (imem_hsize ),
+    .imem_htrans            (imem_htrans),
+    .imem_haddr             (imem_haddr ),
+    .imem_hready            (imem_hready),
+    .imem_hrdata            (imem_hrdata),
+    .imem_hresp             (imem_hresp ),
+
+    // Data Memory Interface
+    // .dmem_hprot             (dmem_hprot ),
+    // .dmem_hburst            (dmem_hburst),
+    .dmem_hsize             (dmem_hsize ),
+    .dmem_htrans            (dmem_htrans),
+    .dmem_haddr             (dmem_haddr ),
+    .dmem_hwrite            (dmem_hwrite),
+    .dmem_hwdata            (dmem_hwdata),
+    .dmem_hready            (dmem_hready),
+    .dmem_hrdata            (dmem_hrdata),
+    .dmem_hresp             (dmem_hresp )
+);
+
+endmodule : scr1_top_tb_ahb
diff --git a/third_party/tests/Scr1/src/tb/scr1_top_tb_axi.sv b/third_party/tests/Scr1/src/tb/scr1_top_tb_axi.sv
new file mode 100644
index 0000000..55fb386
--- /dev/null
+++ b/third_party/tests/Scr1/src/tb/scr1_top_tb_axi.sv
@@ -0,0 +1,611 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_top_tb_axi.sv>
+/// @brief      SCR1 top testbench AXI
+///
+
+`include "scr1_arch_description.svh"
+`ifdef SCR1_IPIC_EN
+`include "scr1_ipic.svh"
+`endif // SCR1_IPIC_EN
+
+module scr1_top_tb_axi (
+`ifdef VERILATOR
+    input logic clk
+`endif // VERILATOR
+);
+
+//------------------------------------------------------------------------------
+// Local parameters
+//------------------------------------------------------------------------------
+localparam                          SCR1_MEM_SIZE       = 1024*1024;
+localparam logic [`SCR1_XLEN-1:0]   SCR1_EXIT_ADDR      = 32'h000000F8;
+
+//------------------------------------------------------------------------------
+// Local signal declaration
+//------------------------------------------------------------------------------
+logic                                   rst_n;
+`ifndef VERILATOR
+logic                                   clk         = 1'b0;
+`endif // VERILATOR
+logic                                   rtc_clk     = 1'b0;
+logic   [31:0]                          fuse_mhartid;
+integer                                 imem_req_ack_stall;
+integer                                 dmem_req_ack_stall;
+`ifdef SCR1_IPIC_EN
+logic [SCR1_IRQ_LINES_NUM-1:0]          irq_lines;
+`else // SCR1_IPIC_EN
+logic                                   ext_irq     = 1'b0;
+`endif // SCR1_IPIC_EN
+logic                                   soft_irq    = 1'b0;
+
+`ifdef SCR1_DBGC_EN
+logic                                   trst_n;
+logic                                   tck;
+logic                                   tms;
+logic                                   tdi;
+logic                                   tdo;
+logic                                   tdo_en;
+`endif // SCR1_DBGC_EN
+
+// Instruction Memory
+logic [3:0]                             io_axi_imem_awid;
+logic [31:0]                            io_axi_imem_awaddr;
+logic [7:0]                             io_axi_imem_awlen;
+logic [2:0]                             io_axi_imem_awsize;
+logic [1:0]                             io_axi_imem_awburst;
+logic                                   io_axi_imem_awlock;
+logic [3:0]                             io_axi_imem_awcache;
+logic [2:0]                             io_axi_imem_awprot;
+logic [3:0]                             io_axi_imem_awregion;
+logic [3:0]                             io_axi_imem_awuser;
+logic [3:0]                             io_axi_imem_awqos;
+logic                                   io_axi_imem_awvalid;
+logic                                   io_axi_imem_awready;
+logic [31:0]                            io_axi_imem_wdata;
+logic [3:0]                             io_axi_imem_wstrb;
+logic                                   io_axi_imem_wlast;
+logic [3:0]                             io_axi_imem_wuser;
+logic                                   io_axi_imem_wvalid;
+logic                                   io_axi_imem_wready;
+logic [3:0]                             io_axi_imem_bid;
+logic [1:0]                             io_axi_imem_bresp;
+logic                                   io_axi_imem_bvalid;
+logic [3:0]                             io_axi_imem_buser;
+logic                                   io_axi_imem_bready;
+logic [3:0]                             io_axi_imem_arid;
+logic [31:0]                            io_axi_imem_araddr;
+logic [7:0]                             io_axi_imem_arlen;
+logic [2:0]                             io_axi_imem_arsize;
+logic [1:0]                             io_axi_imem_arburst;
+logic                                   io_axi_imem_arlock;
+logic [3:0]                             io_axi_imem_arcache;
+logic [2:0]                             io_axi_imem_arprot;
+logic [3:0]                             io_axi_imem_arregion;
+logic [3:0]                             io_axi_imem_aruser;
+logic [3:0]                             io_axi_imem_arqos;
+logic                                   io_axi_imem_arvalid;
+logic                                   io_axi_imem_arready;
+logic [3:0]                             io_axi_imem_rid;
+logic [31:0]                            io_axi_imem_rdata;
+logic [1:0]                             io_axi_imem_rresp;
+logic                                   io_axi_imem_rlast;
+logic [3:0]                             io_axi_imem_ruser;
+logic                                   io_axi_imem_rvalid;
+logic                                   io_axi_imem_rready;
+
+// Data Memory
+logic [3:0]                             io_axi_dmem_awid;
+logic [31:0]                            io_axi_dmem_awaddr;
+logic [7:0]                             io_axi_dmem_awlen;
+logic [2:0]                             io_axi_dmem_awsize;
+logic [1:0]                             io_axi_dmem_awburst;
+logic                                   io_axi_dmem_awlock;
+logic [3:0]                             io_axi_dmem_awcache;
+logic [2:0]                             io_axi_dmem_awprot;
+logic [3:0]                             io_axi_dmem_awregion;
+logic [3:0]                             io_axi_dmem_awuser;
+logic [3:0]                             io_axi_dmem_awqos;
+logic                                   io_axi_dmem_awvalid;
+logic                                   io_axi_dmem_awready;
+logic [31:0]                            io_axi_dmem_wdata;
+logic [3:0]                             io_axi_dmem_wstrb;
+logic                                   io_axi_dmem_wlast;
+logic [3:0]                             io_axi_dmem_wuser;
+logic                                   io_axi_dmem_wvalid;
+logic                                   io_axi_dmem_wready;
+logic [3:0]                             io_axi_dmem_bid;
+logic [1:0]                             io_axi_dmem_bresp;
+logic                                   io_axi_dmem_bvalid;
+logic [3:0]                             io_axi_dmem_buser;
+logic                                   io_axi_dmem_bready;
+logic [3:0]                             io_axi_dmem_arid;
+logic [31:0]                            io_axi_dmem_araddr;
+logic [7:0]                             io_axi_dmem_arlen;
+logic [2:0]                             io_axi_dmem_arsize;
+logic [1:0]                             io_axi_dmem_arburst;
+logic                                   io_axi_dmem_arlock;
+logic [3:0]                             io_axi_dmem_arcache;
+logic [2:0]                             io_axi_dmem_arprot;
+logic [3:0]                             io_axi_dmem_arregion;
+logic [3:0]                             io_axi_dmem_aruser;
+logic [3:0]                             io_axi_dmem_arqos;
+logic                                   io_axi_dmem_arvalid;
+logic                                   io_axi_dmem_arready;
+logic [3:0]                             io_axi_dmem_rid;
+logic [31:0]                            io_axi_dmem_rdata;
+logic [1:0]                             io_axi_dmem_rresp;
+logic                                   io_axi_dmem_rlast;
+logic [3:0]                             io_axi_dmem_ruser;
+logic                                   io_axi_dmem_rvalid;
+logic                                   io_axi_dmem_rready;
+
+int unsigned                            f_results;
+int unsigned                            f_info;
+string                                  s_results;
+string                                  s_info;
+`ifdef VERILATOR
+logic [255:0]                           test_file;
+`else // VERILATOR
+string                                  test_file;
+`endif // VERILATOR
+
+bit                                     test_running;
+int unsigned                            tests_passed;
+int unsigned                            tests_total;
+
+bit [1:0]                               rst_cnt;
+bit                                     rst_init;
+
+
+`ifdef VERILATOR
+function bit is_compliance (logic [255:0] testname);
+    bit res;
+    logic [79:0] pattern;
+begin
+    pattern = 80'h636f6d706c69616e6365; // compliance
+    res = 0;
+    for (int i = 0; i<= 176; i++) begin
+        if(testname[i+:80] == pattern) begin
+            return ~res;
+        end
+    end
+    return res;
+end
+endfunction : is_compliance
+
+function logic [255:0] get_filename (logic [255:0] testname);
+logic [255:0] res;
+int i, j;
+begin
+    testname[15:8] = 8'h66;
+    testname[23:16] = 8'h6C;
+    testname[31:24] = 8'h65;
+
+    for (i = 0; i <= 248; i += 8) begin
+        if (testname[i+:8] == 0) begin
+            break;
+        end
+    end
+    i -= 8;
+    for (j = 255; i > 0;i -= 8) begin
+        res[j-:8] = testname[i+:8];
+        j -= 8;
+    end
+    for (; j >= 0;j -= 8) begin
+        res[j-:8] = 0;
+    end
+
+    return res;
+end
+endfunction : get_filename
+
+function logic [255:0] get_ref_filename (logic [255:0] testname);
+logic [255:0] res;
+int i, j;
+logic [79:0] pattern;
+begin
+    pattern = 80'h636f6d706c69616e6365; // compliance
+
+    for(int i = 0; i <= 176; i++) begin
+        if(testname[i+:80] == pattern) begin
+            testname[(i-8)+:88] = 0;
+            break;
+        end
+    end
+
+    for(i = 32; i <= 248; i += 8) begin
+        if(testname[i+:8] == 0) break;
+    end
+    i -= 8;
+    for(j = 255; i > 32;i -= 8) begin
+        res[j-:8] = testname[i+:8];
+        j -= 8;
+    end
+    for(; j >=0;j -= 8) begin
+        res[j-:8] = 0;
+    end
+
+    return res;
+end
+endfunction : get_ref_filename
+
+`else // VERILATOR
+function bit is_compliance (string testname);
+begin
+    return (testname.substr(0, 9) == "compliance");
+end
+endfunction : is_compliance
+
+function string get_filename (string testname);
+int length;
+begin
+    length = testname.len();
+    testname[length-1] = "f";
+    testname[length-2] = "l";
+    testname[length-3] = "e";
+    
+    return testname;
+end
+endfunction : get_filename
+
+function string get_ref_filename (string testname);
+begin
+    return testname.substr(11, testname.len() - 5);
+end
+endfunction : get_ref_filename
+
+`endif // VERILATOR
+
+`ifndef VERILATOR
+always #5   clk     = ~clk;         // 100 MHz
+always #500 rtc_clk = ~rtc_clk;     // 1 MHz
+`endif // VERILATOR
+
+// Reset logic
+assign rst_n = &rst_cnt;
+
+always_ff @(posedge clk) begin
+    if (rst_init)       rst_cnt <= '0;
+    else if (~&rst_cnt) rst_cnt <= rst_cnt + 1'b1;
+end
+
+
+`ifdef SCR1_DBGC_EN
+initial begin
+    trst_n  = 1'b0;
+    tck     = 1'b0;
+    tdi     = 1'b0;
+    #900ns trst_n   = 1'b1;
+    #500ns tms      = 1'b1;
+    #800ns tms      = 1'b0;
+    #500ns trst_n   = 1'b0;
+    #100ns tms      = 1'b1;
+end
+`endif // SCR1_DBGC_EN
+
+//-------------------------------------------------------------------------------
+// Run tests
+//-------------------------------------------------------------------------------
+
+initial begin
+    $value$plusargs("imem_pattern=%h", imem_req_ack_stall);
+    $value$plusargs("dmem_pattern=%h", dmem_req_ack_stall);
+    $value$plusargs("test_info=%s", s_info);
+    $value$plusargs("test_results=%s", s_results);
+
+    fuse_mhartid = 0;
+
+    f_info      = $fopen(s_info, "r");
+    f_results   = $fopen(s_results, "a");
+end
+
+always_ff @(posedge clk) begin
+    if (test_running) begin
+        rst_init <= 1'b0;
+        if ((i_top.i_core_top.i_pipe_top.curr_pc == SCR1_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
+        `ifdef VERILATOR
+        logic [255:0] full_filename;
+        full_filename = test_file;
+        `else // VERILATOR
+        string full_filename;
+        full_filename = test_file;
+        `endif // VERILATOR
+
+            if (is_compliance(test_file)) begin
+                bit test_pass;
+                logic [31:0] tmpv, start, stop, ref_data, test_data;
+                integer fd;
+                `ifdef VERILATOR
+                logic [2047:0] tmpstr;
+                `else // VERILATOR
+                string tmpstr;
+                `endif // VERILATOR
+                
+                test_running <= 1'b0;
+                test_pass = 1;
+
+                $sformat(tmpstr, "riscv64-unknown-elf-readelf -s %s | grep 'begin_signature\\|end_signature' | awk '{print $2}' > elfinfo", get_filename(test_file));
+                fd = $fopen("script.sh", "w");
+                if (fd == 0) begin
+                    $write("Can't open script.sh\n");
+                    test_pass = 0;
+                end
+                $fwrite(fd, "%s", tmpstr);
+                $fclose(fd);
+
+                $system("sh script.sh");
+
+                fd = $fopen("elfinfo", "r");
+                if (fd == 0) begin
+                    $write("Can't open elfinfo\n");
+                    test_pass = 0;
+                end
+                if ($fscanf(fd,"%h\n%h", start, stop) != 2) begin
+                    $write("Wrong elfinfo data\n");
+                    test_pass = 0;
+                end
+                if (start > stop) begin
+                    tmpv = start;
+                    start = stop;
+                    stop = tmpv;
+                end
+                $fclose(fd);
+
+                $sformat(tmpstr, "riscv_compliance/ref_data/%s", get_ref_filename(test_file));
+                fd = $fopen(tmpstr,"r");
+                if (fd == 0) begin
+                    $write("Can't open reference_data file: %s\n", tmpstr);
+                    test_pass = 0;
+                end
+                while (!$feof(fd) && (start != stop)) begin
+                    $fscanf(fd, "0x%h,\n", ref_data);
+                    test_data = {i_memory_tb.memory[start+3], i_memory_tb.memory[start+2], i_memory_tb.memory[start+1], i_memory_tb.memory[start]};
+                    test_pass &= (ref_data == test_data);
+                    start += 4;
+                end
+                $fclose(fd);
+
+                tests_total += 1;
+                tests_passed += test_pass;
+                $fwrite(f_results, "%s\t\t%s\n", test_file, (test_pass ? "PASS" : "__FAIL"));
+                if (test_pass) begin
+                    $write("\033[0;32mTest passed\033[0m\n");
+                end else begin
+                    $write("\033[0;31mTest failed\033[0m\n");
+                end
+            end else begin
+                bit test_pass;
+                test_running <= 1'b0;
+                test_pass = (i_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] == 0);
+                tests_total     += 1;
+                tests_passed    += test_pass;
+                $fwrite(f_results, "%s\t\t%s\n", test_file, (test_pass ? "PASS" : "__FAIL"));
+                if (test_pass) begin
+                    $write("\033[0;32mTest passed\033[0m\n");
+                end else begin
+                    $write("\033[0;31mTest failed\033[0m\n");
+                end
+            end
+        end
+    end else begin
+`ifdef VERILATOR
+        if ($fgets(test_file,f_info)) begin
+`else // VERILATOR
+        if (!$feof(f_info)) begin
+            $fscanf(f_info, "%s\n", test_file);
+`endif // VERILATOR
+            // Launch new test
+`ifdef SCR1_TRACE_LOG_EN
+            i_top.i_core_top.i_pipe_top.i_tracelog.test_name = test_file;
+`endif // SCR1_TRACE_LOG_EN
+            i_memory_tb.test_file = test_file;
+            i_memory_tb.test_file_init = 1'b1;
+            $write("\033[0;34m---Test: %s\033[0m\n", test_file);
+            test_running <= 1'b1;
+            rst_init <= 1'b1;
+        end else begin
+            // Exit
+            $display("\n#--------------------------------------");
+            $display("# Summary: %0d/%0d tests passed", tests_passed, tests_total);
+            $display("#--------------------------------------\n");
+            $fclose(f_info);
+            $fclose(f_results);
+            $finish();
+        end
+    end
+end
+
+//------------------------------------------------------------------------------
+// Core instance
+//------------------------------------------------------------------------------
+scr1_top_axi i_top (
+    // Reset
+    .pwrup_rst_n            (rst_n                  ),
+    .rst_n                  (rst_n                  ),
+    .cpu_rst_n              (rst_n                  ),
+`ifdef SCR1_DBGC_EN
+    .ndm_rst_n_out          (),
+`endif // SCR1_DBGC_EN
+
+    // Clock
+    .clk                    (clk                    ),
+    .rtc_clk                (rtc_clk                ),
+
+    // Fuses
+    .fuse_mhartid           (fuse_mhartid           ),
+`ifdef SCR1_DBGC_EN
+    .fuse_idcode            (`SCR1_TAP_IDCODE       ),
+`endif // SCR1_DBGC_EN
+
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    .irq_lines              (irq_lines              ),
+`else // SCR1_IPIC_EN
+    .ext_irq                (ext_irq                ),
+`endif // SCR1_IPIC_EN
+    .soft_irq               (soft_irq               ),
+
+    // DFT
+    .test_mode              (1'b0                   ),
+    .test_rst_n             (1'b1                   ),
+
+`ifdef SCR1_DBGC_EN
+    // JTAG
+    .trst_n                 (trst_n                 ),
+    .tck                    (tck                    ),
+    .tms                    (tms                    ),
+    .tdi                    (tdi                    ),
+    .tdo                    (tdo                    ),
+    .tdo_en                 (tdo_en                 ),
+`endif // SCR1_DBGC_EN
+
+    // Instruction memory interface
+    .io_axi_imem_awid       (io_axi_imem_awid       ),
+    .io_axi_imem_awaddr     (io_axi_imem_awaddr     ),
+    .io_axi_imem_awlen      (io_axi_imem_awlen      ),
+    .io_axi_imem_awsize     (io_axi_imem_awsize     ),
+    .io_axi_imem_awburst    (),
+    .io_axi_imem_awlock     (),
+    .io_axi_imem_awcache    (),
+    .io_axi_imem_awprot     (),
+    .io_axi_imem_awregion   (),
+    .io_axi_imem_awuser     (),
+    .io_axi_imem_awqos      (),
+    .io_axi_imem_awvalid    (io_axi_imem_awvalid    ),
+    .io_axi_imem_awready    (io_axi_imem_awready    ),
+    .io_axi_imem_wdata      (io_axi_imem_wdata      ),
+    .io_axi_imem_wstrb      (io_axi_imem_wstrb      ),
+    .io_axi_imem_wlast      (io_axi_imem_wlast      ),
+    .io_axi_imem_wuser      (),
+    .io_axi_imem_wvalid     (io_axi_imem_wvalid     ),
+    .io_axi_imem_wready     (io_axi_imem_wready     ),
+    .io_axi_imem_bid        (io_axi_imem_bid        ),
+    .io_axi_imem_bresp      (io_axi_imem_bresp      ),
+    .io_axi_imem_bvalid     (io_axi_imem_bvalid     ),
+    .io_axi_imem_buser      (4'd0                   ),
+    .io_axi_imem_bready     (io_axi_imem_bready     ),
+    .io_axi_imem_arid       (io_axi_imem_arid       ),
+    .io_axi_imem_araddr     (io_axi_imem_araddr     ),
+    .io_axi_imem_arlen      (io_axi_imem_arlen      ),
+    .io_axi_imem_arsize     (io_axi_imem_arsize     ),
+    .io_axi_imem_arburst    (io_axi_imem_arburst    ),
+    .io_axi_imem_arlock     (),
+    .io_axi_imem_arcache    (),
+    .io_axi_imem_arprot     (),
+    .io_axi_imem_arregion   (),
+    .io_axi_imem_aruser     (),
+    .io_axi_imem_arqos      (),
+    .io_axi_imem_arvalid    (io_axi_imem_arvalid    ),
+    .io_axi_imem_arready    (io_axi_imem_arready    ),
+    .io_axi_imem_rid        (io_axi_imem_rid        ),
+    .io_axi_imem_rdata      (io_axi_imem_rdata      ),
+    .io_axi_imem_rresp      (io_axi_imem_rresp      ),
+    .io_axi_imem_rlast      (io_axi_imem_rlast      ),
+    .io_axi_imem_ruser      (4'd0                   ),
+    .io_axi_imem_rvalid     (io_axi_imem_rvalid     ),
+    .io_axi_imem_rready     (io_axi_imem_rready     ),
+
+    // Data memory interface
+    .io_axi_dmem_awid       (io_axi_dmem_awid       ),
+    .io_axi_dmem_awaddr     (io_axi_dmem_awaddr     ),
+    .io_axi_dmem_awlen      (io_axi_dmem_awlen      ),
+    .io_axi_dmem_awsize     (io_axi_dmem_awsize     ),
+    .io_axi_dmem_awburst    (),
+    .io_axi_dmem_awlock     (),
+    .io_axi_dmem_awcache    (),
+    .io_axi_dmem_awprot     (),
+    .io_axi_dmem_awregion   (),
+    .io_axi_dmem_awuser     (),
+    .io_axi_dmem_awqos      (),
+    .io_axi_dmem_awvalid    (io_axi_dmem_awvalid    ),
+    .io_axi_dmem_awready    (io_axi_dmem_awready    ),
+    .io_axi_dmem_wdata      (io_axi_dmem_wdata      ),
+    .io_axi_dmem_wstrb      (io_axi_dmem_wstrb      ),
+    .io_axi_dmem_wlast      (io_axi_dmem_wlast      ),
+    .io_axi_dmem_wuser      (),
+    .io_axi_dmem_wvalid     (io_axi_dmem_wvalid     ),
+    .io_axi_dmem_wready     (io_axi_dmem_wready     ),
+    .io_axi_dmem_bid        (io_axi_dmem_bid        ),
+    .io_axi_dmem_bresp      (io_axi_dmem_bresp      ),
+    .io_axi_dmem_bvalid     (io_axi_dmem_bvalid     ),
+    .io_axi_dmem_buser      (4'd0                   ),
+    .io_axi_dmem_bready     (io_axi_dmem_bready     ),
+    .io_axi_dmem_arid       (io_axi_dmem_arid       ),
+    .io_axi_dmem_araddr     (io_axi_dmem_araddr     ),
+    .io_axi_dmem_arlen      (io_axi_dmem_arlen      ),
+    .io_axi_dmem_arsize     (io_axi_dmem_arsize     ),
+    .io_axi_dmem_arburst    (io_axi_dmem_arburst    ),
+    .io_axi_dmem_arlock     (),
+    .io_axi_dmem_arcache    (),
+    .io_axi_dmem_arprot     (),
+    .io_axi_dmem_arregion   (),
+    .io_axi_dmem_aruser     (),
+    .io_axi_dmem_arqos      (),
+    .io_axi_dmem_arvalid    (io_axi_dmem_arvalid    ),
+    .io_axi_dmem_arready    (io_axi_dmem_arready    ),
+    .io_axi_dmem_rid        (io_axi_dmem_rid        ),
+    .io_axi_dmem_rdata      (io_axi_dmem_rdata      ),
+    .io_axi_dmem_rresp      (io_axi_dmem_rresp      ),
+    .io_axi_dmem_rlast      (io_axi_dmem_rlast      ),
+    .io_axi_dmem_ruser      (4'd0                   ),
+    .io_axi_dmem_rvalid     (io_axi_dmem_rvalid     ),
+    .io_axi_dmem_rready     (io_axi_dmem_rready     )
+);
+
+
+//-------------------------------------------------------------------------------
+// Memory instance
+//-------------------------------------------------------------------------------
+scr1_memory_tb_axi #(
+    .SIZE    (SCR1_MEM_SIZE),
+    .N_IF    (2            ),
+    .W_ADR   (32           ),
+    .W_DATA  (32           )
+) i_memory_tb (
+    // Common
+    .rst_n          (rst_n),
+    .clk            (clk),
+`ifdef SCR1_IPIC_EN
+    .irq_lines      (irq_lines),
+`endif // SCR1_IPIC_EN
+
+    // Write address channel
+    .awid           ( {io_axi_imem_awid,   io_axi_dmem_awid}      ),
+    .awaddr         ( {io_axi_imem_awaddr, io_axi_dmem_awaddr}    ),
+    .awsize         ( {io_axi_imem_awsize, io_axi_dmem_awsize}    ),
+    .awlen          ( {io_axi_imem_awlen,  io_axi_dmem_awlen}     ),
+    .awvalid        ( {io_axi_imem_awvalid,io_axi_dmem_awvalid}   ),
+    .awready        ( {io_axi_imem_awready,io_axi_dmem_awready}   ),
+
+    // Write data channel
+    .wdata          ( {io_axi_imem_wdata,  io_axi_dmem_wdata}     ),
+    .wstrb          ( {io_axi_imem_wstrb,  io_axi_dmem_wstrb}     ),
+    .wvalid         ( {io_axi_imem_wvalid, io_axi_dmem_wvalid}    ),
+    .wlast          ( {io_axi_imem_wlast,  io_axi_dmem_wlast}     ),
+    .wready         ( {io_axi_imem_wready, io_axi_dmem_wready}    ),
+
+    // Write response channel
+    .bready         ( {io_axi_imem_bready, io_axi_dmem_bready}    ),
+    .bvalid         ( {io_axi_imem_bvalid, io_axi_dmem_bvalid}    ),
+    .bid            ( {io_axi_imem_bid,    io_axi_dmem_bid}       ),
+    .bresp          ( {io_axi_imem_bresp,  io_axi_dmem_bresp}     ),
+
+    // Read address channel
+    .arid           ( {io_axi_imem_arid,   io_axi_dmem_arid}      ),
+    .araddr         ( {io_axi_imem_araddr, io_axi_dmem_araddr}    ),
+    .arburst        ( {io_axi_imem_arburst,io_axi_dmem_arburst}   ),
+    .arsize         ( {io_axi_imem_arsize, io_axi_dmem_arsize}    ),
+    .arlen          ( {io_axi_imem_arlen,  io_axi_dmem_arlen}     ),
+    .arvalid        ( {io_axi_imem_arvalid,io_axi_dmem_arvalid}   ),
+    .arready        ( {io_axi_imem_arready,io_axi_dmem_arready}   ),
+
+    // Read data channel
+    .rvalid         ( {io_axi_imem_rvalid, io_axi_dmem_rvalid}    ),
+    .rready         ( {io_axi_imem_rready, io_axi_dmem_rready}    ),
+    .rid            ( {io_axi_imem_rid,    io_axi_dmem_rid}       ),
+    .rdata          ( {io_axi_imem_rdata,  io_axi_dmem_rdata}     ),
+    .rlast          ( {io_axi_imem_rlast,  io_axi_dmem_rlast}     ),
+    .rresp          ( {io_axi_imem_rresp,  io_axi_dmem_rresp}     )
+);
+
+endmodule : scr1_top_tb_axi
diff --git a/third_party/tests/Scr1/src/top/scr1_dmem_ahb.sv b/third_party/tests/Scr1/src/top/scr1_dmem_ahb.sv
new file mode 100644
index 0000000..fb27dc3
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_dmem_ahb.sv
@@ -0,0 +1,466 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_dmem_ahb.sv>
+/// @brief      Data memory AHB bridge
+///
+
+`include "scr1_ahb.svh"
+`include "scr1_memif.svh"
+
+module scr1_dmem_ahb (
+    // Control Signals
+    input   logic                           rst_n,
+    input   logic                           clk,
+
+    // Core Interface
+    output  logic                           dmem_req_ack,
+    input   logic                           dmem_req,
+    input   type_scr1_mem_cmd_e             dmem_cmd,
+    input   type_scr1_mem_width_e           dmem_width,
+    input   logic   [SCR1_AHB_WIDTH-1:0]    dmem_addr,
+    input   logic   [SCR1_AHB_WIDTH-1:0]    dmem_wdata,
+    output  logic   [SCR1_AHB_WIDTH-1:0]    dmem_rdata,
+    output  type_scr1_mem_resp_e            dmem_resp,
+
+    // AHB Interface
+    output  logic   [3:0]                   hprot,
+    output  logic   [2:0]                   hburst,
+    output  logic   [2:0]                   hsize,
+    output  logic   [1:0]                   htrans,
+    output  logic                           hmastlock,
+    output  logic   [SCR1_AHB_WIDTH-1:0]    haddr,
+    output  logic                           hwrite,
+    output  logic   [SCR1_AHB_WIDTH-1:0]    hwdata,
+    input   logic                           hready,
+    input   logic   [SCR1_AHB_WIDTH-1:0]    hrdata,
+    input   logic                           hresp
+
+);
+
+//-------------------------------------------------------------------------------
+// Local Parameters
+//-------------------------------------------------------------------------------
+`ifndef SCR1_DMEM_AHB_OUT_BP
+localparam  SCR1_FIFO_WIDTH = 2;
+localparam  SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
+`endif // SCR1_DMEM_AHB_OUT_BP
+
+//-------------------------------------------------------------------------------
+// Local type declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {
+    SCR1_FSM_ADDR = 1'b0,
+    SCR1_FSM_DATA = 1'b1,
+    SCR1_FSM_ERR  = 1'bx
+} type_scr1_fsm_e;
+
+typedef struct packed {
+    logic                           hwrite;
+    logic   [2:0]                   hwidth;
+    logic   [SCR1_AHB_WIDTH-1:0]    haddr;
+    logic   [SCR1_AHB_WIDTH-1:0]    hwdata;
+} type_scr1_req_fifo_s;
+
+typedef struct packed {
+    logic                           hwrite;
+    logic   [2:0]                   hwidth;
+    logic   [1:0]                   haddr;
+    logic   [SCR1_AHB_WIDTH-1:0]    hwdata;
+} type_scr1_data_fifo_s;
+
+typedef struct packed {
+    logic                           hresp;
+    logic   [2:0]                   hwidth;
+    logic   [1:0]                   haddr;
+    logic   [SCR1_AHB_WIDTH-1:0]    hrdata;
+} type_scr1_resp_fifo_s;
+
+//-------------------------------------------------------------------------------
+// Local functions
+//-------------------------------------------------------------------------------
+function automatic logic   [2:0] scr1_conv_mem2ahb_width (
+    input   type_scr1_mem_width_e    dmem_width
+);
+    logic   [2:0]   tmp;
+begin
+    case (dmem_width)
+        SCR1_MEM_WIDTH_BYTE : begin
+            tmp = SCR1_HSIZE_8B;
+        end
+        SCR1_MEM_WIDTH_HWORD : begin
+            tmp = SCR1_HSIZE_16B;
+        end
+        SCR1_MEM_WIDTH_WORD : begin
+            tmp = SCR1_HSIZE_32B;
+        end
+        default : begin
+            tmp = SCR1_HSIZE_ERR;
+        end
+    endcase
+    return tmp;
+end
+endfunction : scr1_conv_mem2ahb_width
+
+function automatic logic[SCR1_AHB_WIDTH-1:0] scr1_conv_mem2ahb_wdata (
+    input   logic   [1:0]                   dmem_addr,
+    input   type_scr1_mem_width_e           dmem_width,
+    input   logic   [SCR1_AHB_WIDTH-1:0]    dmem_wdata
+);
+    logic   [SCR1_AHB_WIDTH-1:0]  tmp;
+begin
+    tmp = 'x;
+    case (dmem_width)
+        SCR1_MEM_WIDTH_BYTE : begin
+            case (dmem_addr)
+                2'b00 : begin
+                    tmp[7:0]   = dmem_wdata[7:0];
+                end
+                2'b01 : begin
+                    tmp[15:8]  = dmem_wdata[7:0];
+                end
+                2'b10 : begin
+                    tmp[23:16] = dmem_wdata[7:0];
+                end
+                2'b11 : begin
+                    tmp[31:24] = dmem_wdata[7:0];
+                end
+                default : begin
+                end
+            endcase
+        end
+        SCR1_MEM_WIDTH_HWORD : begin
+            case (dmem_addr[1])
+                1'b0 : begin
+                    tmp[15:0]  = dmem_wdata[15:0];
+                end
+                1'b1 : begin
+                    tmp[31:16] = dmem_wdata[15:0];
+                end
+                default : begin
+                end
+            endcase
+        end
+        SCR1_MEM_WIDTH_WORD : begin
+            tmp = dmem_wdata;
+        end
+        default : begin
+        end
+    endcase
+    return tmp;
+end
+endfunction : scr1_conv_mem2ahb_wdata
+
+function automatic logic[SCR1_AHB_WIDTH-1:0] scr1_conv_ahb2mem_rdata (
+    input   logic [2:0]                 hwidth,
+    input   logic [1:0]                 haddr,
+    input   logic [SCR1_AHB_WIDTH-1:0]  hrdata
+);
+    logic   [SCR1_AHB_WIDTH-1:0]  tmp;
+begin
+    tmp = 'x;
+    case (hwidth)
+        SCR1_HSIZE_8B : begin
+            case (haddr)
+                2'b00 : tmp[7:0] = hrdata[7:0];
+                2'b01 : tmp[7:0] = hrdata[15:8];
+                2'b10 : tmp[7:0] = hrdata[23:16];
+                2'b11 : tmp[7:0] = hrdata[31:24];
+                default : begin
+                end
+            endcase
+        end
+        SCR1_HSIZE_16B : begin
+            case (haddr[1])
+                1'b0 : tmp[15:0] = hrdata[15:0];
+                1'b1 : tmp[15:0] = hrdata[31:16];
+                default : begin
+                end
+            endcase
+        end
+        SCR1_HSIZE_32B : begin
+            tmp = hrdata;
+        end
+        default : begin
+        end
+    endcase
+    return tmp;
+end
+endfunction : scr1_conv_ahb2mem_rdata
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+type_scr1_fsm_e                             fsm;
+logic                                       req_fifo_rd;
+logic                                       req_fifo_wr;
+logic                                       req_fifo_up;
+`ifdef SCR1_DMEM_AHB_OUT_BP
+type_scr1_req_fifo_s                        req_fifo_new;
+type_scr1_req_fifo_s                        req_fifo_r;
+type_scr1_req_fifo_s [0:0]                  req_fifo;
+`else // SCR1_DMEM_AHB_OUT_BP
+type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1]  req_fifo;
+type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1]  req_fifo_new;
+logic       [SCR1_FIFO_CNT_WIDTH-1:0]       req_fifo_cnt;
+logic       [SCR1_FIFO_CNT_WIDTH-1:0]       req_fifo_cnt_new;
+`endif // SCR1_DMEM_AHB_OUT_BP
+logic                                       req_fifo_empty;
+logic                                       req_fifo_full;
+
+type_scr1_data_fifo_s                       data_fifo;
+type_scr1_resp_fifo_s                       resp_fifo;
+logic                                       resp_fifo_hready;
+
+//-------------------------------------------------------------------------------
+// Interface to Core
+//-------------------------------------------------------------------------------
+assign dmem_req_ack = ~req_fifo_full;
+assign req_fifo_wr  = ~req_fifo_full & dmem_req;
+
+assign dmem_rdata = scr1_conv_ahb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata);
+
+assign dmem_resp = (resp_fifo_hready)
+                    ? (resp_fifo.hresp == SCR1_HRESP_OKAY)
+                        ? SCR1_MEM_RESP_RDY_OK
+                        : SCR1_MEM_RESP_RDY_ER
+                    : SCR1_MEM_RESP_NOTRDY ;
+
+//-------------------------------------------------------------------------------
+// REQ_FIFO
+//-------------------------------------------------------------------------------
+`ifdef SCR1_DMEM_AHB_OUT_BP
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        req_fifo_full <= 1'b0;
+    end else begin
+        if (~req_fifo_full) begin
+            req_fifo_full <= dmem_req & ~req_fifo_rd;
+        end else begin
+            req_fifo_full <= ~req_fifo_rd;
+        end
+    end
+end
+assign req_fifo_empty = ~(req_fifo_full | dmem_req);
+
+assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
+always_ff @(posedge clk) begin
+    if (req_fifo_up) begin
+        req_fifo_r <= req_fifo_new;
+    end
+end
+
+assign req_fifo_new.hwrite = dmem_req ? (dmem_cmd == SCR1_MEM_CMD_WR)       : 1'b0;
+assign req_fifo_new.hwidth = dmem_req ? scr1_conv_mem2ahb_width(dmem_width) : '0;
+assign req_fifo_new.haddr  = dmem_req ? dmem_addr                           : '0;
+assign req_fifo_new.hwdata = (dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR))
+                                ? scr1_conv_mem2ahb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata)
+                                : '0;
+assign req_fifo[0] = (req_fifo_full) ? req_fifo_r: req_fifo_new;
+
+`else // SCR1_DMEM_AHB_OUT_BP
+always_comb begin
+    req_fifo_up      = 1'b0;
+    req_fifo_cnt_new = req_fifo_cnt;
+    req_fifo_new     = req_fifo;
+    case ({req_fifo_rd, req_fifo_wr})
+        2'b00 : begin
+            // nothing todo
+        end
+        2'b01: begin
+            // FIFO write
+            req_fifo_up = 1'b1;
+            req_fifo_new[req_fifo_cnt].hwrite = (dmem_cmd == SCR1_MEM_CMD_WR);
+            req_fifo_new[req_fifo_cnt].hwidth = scr1_conv_mem2ahb_width(dmem_width);
+            req_fifo_new[req_fifo_cnt].haddr  = dmem_addr;
+            req_fifo_new[req_fifo_cnt].hwdata = scr1_conv_mem2ahb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata);
+            req_fifo_cnt_new = req_fifo_cnt + 1'b1;
+        end
+        2'b10 : begin
+            // FIFO read
+            req_fifo_up = 1'b1;
+            req_fifo_new[0] = req_fifo_new[1];
+            req_fifo_new[1].hwrite = 1'b0;
+            req_fifo_new[1].hwidth = SCR1_HSIZE_32B;
+            req_fifo_new[1].haddr  = 'x;
+            req_fifo_new[1].hwdata = 'x;
+            req_fifo_cnt_new = req_fifo_cnt - 1'b1;
+        end
+        2'b11 : begin
+            // Read and Write FIFO. It is possible only when fifo_cnt = 1
+            req_fifo_up = 1'b1;
+            req_fifo_new[0].hwrite = (dmem_cmd == SCR1_MEM_CMD_WR);
+            req_fifo_new[0].hwidth = scr1_conv_mem2ahb_width(dmem_width);
+            req_fifo_new[0].haddr  = dmem_addr;
+            req_fifo_new[0].hwdata = scr1_conv_mem2ahb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata);
+        end
+        default : begin
+            req_fifo_up      = 'x;
+            req_fifo_cnt_new = 'x;
+            req_fifo_new     = 'x;
+        end
+    endcase
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        req_fifo_cnt <= '0;
+    end else begin
+        if (req_fifo_up) begin
+            req_fifo_cnt <= req_fifo_cnt_new;
+        end
+    end
+end
+assign req_fifo_full  = (req_fifo_cnt == SCR1_FIFO_WIDTH);
+assign req_fifo_empty = ~(|req_fifo_cnt);
+
+always_ff @(posedge clk) begin
+    if (req_fifo_up) begin
+        req_fifo <= req_fifo_new;
+    end
+end
+`endif // SCR1_DMEM_AHB_OUT_BP
+//-------------------------------------------------------------------------------
+// FSM
+//-------------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        fsm <= SCR1_FSM_ADDR;
+    end else begin
+        case (fsm)
+            SCR1_FSM_ADDR : begin
+                if (hready) begin
+                    fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
+                end
+            end
+            SCR1_FSM_DATA : begin
+                if (hready) begin
+                    if (hresp == SCR1_HRESP_OKAY) begin
+                        fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
+                    end else begin
+                        fsm <= SCR1_FSM_ADDR;
+                    end
+                end
+            end
+            default : begin
+                fsm <= SCR1_FSM_ERR;
+            end
+        endcase
+    end
+end
+
+always_comb begin
+    req_fifo_rd = 1'b0;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            if (hready) begin
+                req_fifo_rd = ~req_fifo_empty;
+            end
+        end
+        SCR1_FSM_DATA : begin
+            if (hready) begin
+                req_fifo_rd = ~req_fifo_empty & (hresp == SCR1_HRESP_OKAY);
+            end
+        end
+        default : begin
+            req_fifo_rd = 1'bx;
+        end
+    endcase
+end
+
+//-------------------------------------------------------------------------------
+// FIFO data
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk) begin
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            if (~req_fifo_empty) begin
+                data_fifo.hwrite <= req_fifo[0].hwrite;
+                data_fifo.hwidth <= req_fifo[0].hwidth;
+                data_fifo.haddr  <= req_fifo[0].haddr[1:0];
+                data_fifo.hwdata <= req_fifo[0].hwdata;
+            end
+        end
+        SCR1_FSM_DATA : begin
+            if (hready) begin
+                if (hresp == SCR1_HRESP_OKAY) begin
+                    if (~req_fifo_empty) begin
+                        data_fifo.hwrite <= req_fifo[0].hwrite;
+                        data_fifo.hwidth <= req_fifo[0].hwidth;
+                        data_fifo.haddr  <= req_fifo[0].haddr[1:0];
+                        data_fifo.hwdata <= req_fifo[0].hwdata;
+                    end
+                end
+            end
+        end
+        default : begin
+        end
+    endcase
+end
+
+//-------------------------------------------------------------------------------
+// FIFO response
+//-------------------------------------------------------------------------------
+`ifdef SCR1_DMEM_AHB_IN_BP
+assign resp_fifo_hready = (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
+assign resp_fifo.hresp  = hresp;
+assign resp_fifo.hwidth = data_fifo.hwidth;
+assign resp_fifo.haddr  = data_fifo.haddr;
+assign resp_fifo.hrdata = hrdata;
+`else // SCR1_DMEM_AHB_IN_BP
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        resp_fifo_hready <= 1'b0;
+    end else begin
+        resp_fifo_hready <= (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
+    end
+end
+
+always_ff @(posedge clk) begin
+    if (hready & (fsm == SCR1_FSM_DATA)) begin
+        resp_fifo.hresp  <= hresp;
+        resp_fifo.hwidth <= data_fifo.hwidth;
+        resp_fifo.haddr  <= data_fifo.haddr;
+        resp_fifo.hrdata <= hrdata;
+    end
+end
+`endif // SCR1_DMEM_AHB_IN_BP
+
+//-------------------------------------------------------------------------------
+// Interface to AHB
+//-------------------------------------------------------------------------------
+assign hprot[SCR1_HPROT_DATA]  = 1'b1;
+assign hprot[SCR1_HPROT_PRV]   = 1'b0;
+assign hprot[SCR1_HPROT_BUF]   = 1'b0;
+assign hprot[SCR1_HPROT_CACHE] = 1'b0;
+
+assign hburst       = SCR1_HBURST_SINGLE;
+assign hsize        = req_fifo[0].hwidth;
+assign hmastlock    = 1'b0;
+
+always_comb begin
+    htrans = SCR1_HTRANS_IDLE;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            if (~req_fifo_empty) begin
+                htrans = SCR1_HTRANS_NONSEQ;
+            end
+        end
+        SCR1_FSM_DATA : begin
+            if (hready) begin
+                if (hresp == SCR1_HRESP_OKAY) begin
+                    if (~req_fifo_empty) begin
+                        htrans = SCR1_HTRANS_NONSEQ;
+                    end
+                end
+            end
+        end
+        default : begin
+            htrans = SCR1_HTRANS_ERR;
+        end
+    endcase
+end
+
+assign haddr  = req_fifo[0].haddr;
+assign hwrite = req_fifo[0].hwrite;
+assign hwdata = data_fifo.hwdata;
+
+endmodule : scr1_dmem_ahb
diff --git a/third_party/tests/Scr1/src/top/scr1_dmem_router.sv b/third_party/tests/Scr1/src/top/scr1_dmem_router.sv
new file mode 100644
index 0000000..a5cde2f
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_dmem_router.sv
@@ -0,0 +1,259 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_dmem_router.sv>
+/// @brief      Data memory router
+///
+`include "scr1_memif.svh"
+`include "scr1_arch_description.svh"
+
+module scr1_dmem_router
+#(
+    parameter SCR1_PORT1_ADDR_MASK      = `SCR1_DMEM_AWIDTH'hFFFF0000,
+    parameter SCR1_PORT1_ADDR_PATTERN   = `SCR1_DMEM_AWIDTH'h00010000,
+    parameter SCR1_PORT2_ADDR_MASK      = `SCR1_DMEM_AWIDTH'hFFFF0000,
+    parameter SCR1_PORT2_ADDR_PATTERN   = `SCR1_DMEM_AWIDTH'h00020000
+)
+(
+    // Control signals
+    input   logic                           rst_n,
+    input   logic                           clk,
+
+    // Core interface
+    output  logic                           dmem_req_ack,
+    input   logic                           dmem_req,
+    input   type_scr1_mem_cmd_e             dmem_cmd,
+    input   type_scr1_mem_width_e           dmem_width,
+    input   logic [`SCR1_DMEM_AWIDTH-1:0]   dmem_addr,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]   dmem_wdata,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]   dmem_rdata,
+    output  type_scr1_mem_resp_e            dmem_resp,
+
+    // PORT0 interface
+    input   logic                           port0_req_ack,
+    output  logic                           port0_req,
+    output  type_scr1_mem_cmd_e             port0_cmd,
+    output  type_scr1_mem_width_e           port0_width,
+    output  logic [`SCR1_DMEM_AWIDTH-1:0]   port0_addr,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]   port0_wdata,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]   port0_rdata,
+    input   type_scr1_mem_resp_e            port0_resp,
+
+    // PORT1 interface
+    input   logic                           port1_req_ack,
+    output  logic                           port1_req,
+    output  type_scr1_mem_cmd_e             port1_cmd,
+    output  type_scr1_mem_width_e           port1_width,
+    output  logic [`SCR1_DMEM_AWIDTH-1:0]   port1_addr,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]   port1_wdata,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]   port1_rdata,
+    input   type_scr1_mem_resp_e            port1_resp,
+
+    // PORT2 interface
+    input   logic                           port2_req_ack,
+    output  logic                           port2_req,
+    output  type_scr1_mem_cmd_e             port2_cmd,
+    output  type_scr1_mem_width_e           port2_width,
+    output  logic [`SCR1_DMEM_AWIDTH-1:0]   port2_addr,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]   port2_wdata,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]   port2_rdata,
+    input   type_scr1_mem_resp_e            port2_resp
+);
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {
+    SCR1_FSM_ADDR,
+    SCR1_FSM_DATA
+} type_scr1_fsm_e;
+
+typedef enum logic [1:0] {
+    SCR1_SEL_PORT0,
+    SCR1_SEL_PORT1,
+    SCR1_SEL_PORT2
+} type_scr1_sel_e;
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+type_scr1_fsm_e                 fsm;
+type_scr1_sel_e                 port_sel;
+type_scr1_sel_e                 port_sel_r;
+logic [`SCR1_DMEM_DWIDTH-1:0]   sel_rdata;
+type_scr1_mem_resp_e            sel_resp;
+logic                           sel_req_ack;
+
+//-------------------------------------------------------------------------------
+// FSM
+//-------------------------------------------------------------------------------
+always_comb begin
+    port_sel    = SCR1_SEL_PORT0;
+    if ((dmem_addr & SCR1_PORT1_ADDR_MASK) == SCR1_PORT1_ADDR_PATTERN) begin
+        port_sel    = SCR1_SEL_PORT1;
+    end else if ((dmem_addr & SCR1_PORT2_ADDR_MASK) == SCR1_PORT2_ADDR_PATTERN) begin
+        port_sel    = SCR1_SEL_PORT2;
+    end
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        fsm         <= SCR1_FSM_ADDR;
+        port_sel_r  <= SCR1_SEL_PORT0;
+    end else begin
+        case (fsm)
+            SCR1_FSM_ADDR : begin
+                if (dmem_req & sel_req_ack) begin
+                    fsm         <= SCR1_FSM_DATA;
+                    port_sel_r  <= port_sel;
+                end
+            end
+            SCR1_FSM_DATA : begin
+                case (sel_resp)
+                    SCR1_MEM_RESP_RDY_OK : begin
+                        if (dmem_req & sel_req_ack) begin
+                            fsm         <= SCR1_FSM_DATA;
+                            port_sel_r  <= port_sel;
+                        end else begin
+                            fsm <= SCR1_FSM_ADDR;
+                        end
+                    end
+                    SCR1_MEM_RESP_RDY_ER : begin
+                        fsm <= SCR1_FSM_ADDR;
+                    end
+                    default : begin
+                    end
+                endcase
+            end
+            default : begin
+            end
+        endcase
+    end
+end
+
+always_comb begin
+    if ((fsm == SCR1_FSM_ADDR) | ((fsm == SCR1_FSM_DATA) & (sel_resp == SCR1_MEM_RESP_RDY_OK))) begin
+        case (port_sel)
+            SCR1_SEL_PORT0  : sel_req_ack   = port0_req_ack;
+            SCR1_SEL_PORT1  : sel_req_ack   = port1_req_ack;
+            SCR1_SEL_PORT2  : sel_req_ack   = port2_req_ack;
+            default         : sel_req_ack   = 1'b0;
+        endcase
+    end else begin
+        sel_req_ack = 1'b0;
+    end
+end
+
+always_comb begin
+    case (port_sel_r)
+        SCR1_SEL_PORT0  : begin
+            sel_rdata   = port0_rdata;
+            sel_resp    = port0_resp;
+        end
+        SCR1_SEL_PORT1  : begin
+            sel_rdata   = port1_rdata;
+            sel_resp    = port1_resp;
+        end
+        SCR1_SEL_PORT2  : begin
+            sel_rdata   = port2_rdata;
+            sel_resp    = port2_resp;
+        end
+        default         : begin
+            sel_rdata   = '0;
+            sel_resp    = SCR1_MEM_RESP_RDY_ER;
+        end
+    endcase
+end
+
+//-------------------------------------------------------------------------------
+// Interface to core
+//-------------------------------------------------------------------------------
+assign dmem_req_ack = sel_req_ack;
+assign dmem_rdata   = sel_rdata;
+assign dmem_resp    = sel_resp;
+
+//-------------------------------------------------------------------------------
+// Interface to PORT0
+//-------------------------------------------------------------------------------
+always_comb begin
+    port0_req = 1'b0;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            port0_req = dmem_req & (port_sel == SCR1_SEL_PORT0);
+        end
+        SCR1_FSM_DATA : begin
+            if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
+                port0_req = dmem_req & (port_sel == SCR1_SEL_PORT0);
+            end
+        end
+        default : begin
+        end
+    endcase
+end
+
+assign port0_cmd    = (port_sel == SCR1_SEL_PORT0) ? dmem_cmd   : SCR1_MEM_CMD_ERROR;
+assign port0_width  = (port_sel == SCR1_SEL_PORT0) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
+assign port0_addr   = (port_sel == SCR1_SEL_PORT0) ? dmem_addr  : 'x;
+assign port0_wdata  = (port_sel == SCR1_SEL_PORT0) ? dmem_wdata : 'x;
+
+//-------------------------------------------------------------------------------
+// Interface to PORT1
+//-------------------------------------------------------------------------------
+always_comb begin
+    port1_req = 1'b0;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            port1_req = dmem_req & (port_sel == SCR1_SEL_PORT1);
+        end
+        SCR1_FSM_DATA : begin
+            if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
+                port1_req = dmem_req & (port_sel == SCR1_SEL_PORT1);
+            end
+        end
+        default : begin
+        end
+    endcase
+end
+
+assign port1_cmd    = (port_sel == SCR1_SEL_PORT1) ? dmem_cmd   : SCR1_MEM_CMD_ERROR;
+assign port1_width  = (port_sel == SCR1_SEL_PORT1) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
+assign port1_addr   = (port_sel == SCR1_SEL_PORT1) ? dmem_addr  : 'x;
+assign port1_wdata  = (port_sel == SCR1_SEL_PORT1) ? dmem_wdata : 'x;
+
+//-------------------------------------------------------------------------------
+// Interface to PORT2
+//-------------------------------------------------------------------------------
+always_comb begin
+    port2_req = 1'b0;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            port2_req = dmem_req & (port_sel == SCR1_SEL_PORT2);
+        end
+        SCR1_FSM_DATA : begin
+            if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
+                port2_req = dmem_req & (port_sel == SCR1_SEL_PORT2);
+            end
+        end
+        default : begin
+        end
+    endcase
+end
+
+assign port2_cmd    = (port_sel == SCR1_SEL_PORT2) ? dmem_cmd   : SCR1_MEM_CMD_ERROR;
+assign port2_width  = (port_sel == SCR1_SEL_PORT2) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
+assign port2_addr   = (port_sel == SCR1_SEL_PORT2) ? dmem_addr  : 'x;
+assign port2_wdata  = (port_sel == SCR1_SEL_PORT2) ? dmem_wdata : 'x;
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+SCR1_SVA_DMEM_RT_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    dmem_req |-> !$isunknown({port_sel, dmem_cmd, dmem_width})
+    ) else $error("DMEM router Error: unknown values");
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_dmem_router
diff --git a/third_party/tests/Scr1/src/top/scr1_dp_memory.sv b/third_party/tests/Scr1/src/top/scr1_dp_memory.sv
new file mode 100644
index 0000000..0528a8b
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_dp_memory.sv
@@ -0,0 +1,104 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_dp_memory.sv>
+/// @brief      Dual-port synchronous memory with byte enable inputs
+///
+
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_TCM_EN
+module scr1_dp_memory
+#(
+    parameter SCR1_WIDTH    = 32,
+    parameter SCR1_SIZE     = `SCR1_IMEM_AWIDTH'h00010000,
+    parameter SCR1_NBYTES   = SCR1_WIDTH / 8
+)
+(
+    input   logic                           clk,
+    // Port A
+    input   logic                           rena,
+    input   logic [$clog2(SCR1_SIZE)-1:2]   addra,
+    output  logic [SCR1_WIDTH-1:0]          qa,
+    // Port B
+    input   logic                           renb,
+    input   logic                           wenb,
+    input   logic [SCR1_NBYTES-1:0]         webb,
+    input   logic [$clog2(SCR1_SIZE)-1:2]   addrb,
+    input   logic [SCR1_WIDTH-1:0]          datab,
+    output  logic [SCR1_WIDTH-1:0]          qb
+);
+
+`ifdef SCR1_TARGET_FPGA_INTEL
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+logic [SCR1_NBYTES-1:0][7:0] memory_array [0:(SCR1_SIZE/SCR1_NBYTES)-1];
+logic [3:0] wenbb;
+//-------------------------------------------------------------------------------
+// Port B memory behavioral description
+//-------------------------------------------------------------------------------
+assign wenbb = {4{wenb}} & webb;
+always_ff @(posedge clk) begin
+    if (wenb) begin
+        if (wenbb[0]) begin
+            memory_array[addrb][0] <= datab[0+:8];
+        end
+        if (wenbb[1]) begin
+            memory_array[addrb][1] <= datab[8+:8];
+        end
+        if (wenbb[2]) begin
+            memory_array[addrb][2] <= datab[16+:8];
+        end
+        if (wenbb[3]) begin
+            memory_array[addrb][3] <= datab[24+:8];
+        end
+    end
+    qb <= memory_array[addrb];
+end
+//-------------------------------------------------------------------------------
+// Port A memory behavioral description
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk) begin
+    qa <= memory_array[addra];
+end
+
+`else // SCR1_TARGET_FPGA_INTEL
+
+// CASE: OTHERS - SCR1_TARGET_FPGA_XILINX, SIMULATION, ASIC etc
+
+localparam int unsigned RAM_SIZE_WORDS = SCR1_SIZE/SCR1_NBYTES;
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+logic [SCR1_WIDTH-1:0]                  ram_block [RAM_SIZE_WORDS-1:0];
+
+//-------------------------------------------------------------------------------
+// Port A memory behavioral description
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk) begin
+    if (rena) begin
+        qa <= ram_block[addra];
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Port B memory behavioral description
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk) begin
+    if (wenb) begin
+        for (int i=0; i<SCR1_NBYTES; i++) begin
+            if (webb[i]) begin
+                ram_block[addrb][i*8 +: 8] <= datab[i*8 +: 8];
+            end
+        end
+    end
+    if (renb) begin
+        qb <= ram_block[addrb];
+    end
+end
+
+`endif // SCR1_TARGET_FPGA_INTEL
+
+endmodule : scr1_dp_memory
+
+`endif // SCR1_TCM_EN
diff --git a/third_party/tests/Scr1/src/top/scr1_imem_ahb.sv b/third_party/tests/Scr1/src/top/scr1_imem_ahb.sv
new file mode 100644
index 0000000..777d892
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_imem_ahb.sv
@@ -0,0 +1,321 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_imem_ahb.sv>
+/// @brief      Instruction memory AHB bridge
+///
+
+`include "scr1_ahb.svh"
+`include "scr1_memif.svh"
+
+module scr1_imem_ahb (
+    // Control Signals
+    input   logic                           rst_n,
+    input   logic                           clk,
+
+    // Core Interface
+    output  logic                           imem_req_ack,
+    input   logic                           imem_req,
+    input   logic   [SCR1_AHB_WIDTH-1:0]    imem_addr,
+    output  logic   [SCR1_AHB_WIDTH-1:0]    imem_rdata,
+    output  type_scr1_mem_resp_e            imem_resp,
+
+    // AHB Interface
+    output  logic   [3:0]                   hprot,
+    output  logic   [2:0]                   hburst,
+    output  logic   [2:0]                   hsize,
+    output  logic   [1:0]                   htrans,
+    output  logic                           hmastlock,
+    output  logic   [SCR1_AHB_WIDTH-1:0]    haddr,
+    input   logic                           hready,
+    input   logic   [SCR1_AHB_WIDTH-1:0]    hrdata,
+    input   logic                           hresp
+
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters declaration
+//-------------------------------------------------------------------------------
+`ifndef SCR1_IMEM_AHB_OUT_BP
+localparam  SCR1_FIFO_WIDTH = 2;
+localparam  SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
+`endif // SCR1_IMEM_AHB_OUT_BP
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {
+    SCR1_FSM_ADDR = 1'b0,
+    SCR1_FSM_DATA = 1'b1,
+    SCR1_FSM_ERR  = 1'bx
+} type_scr1_fsm_e;
+
+typedef struct packed {
+    logic   [SCR1_AHB_WIDTH-1:0]    haddr;
+} type_scr1_req_fifo_s;
+
+typedef struct packed {
+    logic                           hresp;
+    logic   [SCR1_AHB_WIDTH-1:0]    hrdata;
+} type_scr1_resp_fifo_s;
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+type_scr1_fsm_e                             fsm;
+logic                                       req_fifo_rd;
+logic                                       req_fifo_wr;
+logic                                       req_fifo_up;
+`ifdef SCR1_IMEM_AHB_OUT_BP
+type_scr1_req_fifo_s                        req_fifo_r;
+type_scr1_req_fifo_s [0:0]                  req_fifo;
+`else // SCR1_IMEM_AHB_OUT_BP
+type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1]  req_fifo;
+type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1]  req_fifo_new;
+logic       [SCR1_FIFO_CNT_WIDTH-1:0]       req_fifo_cnt;
+logic       [SCR1_FIFO_CNT_WIDTH-1:0]       req_fifo_cnt_new;
+`endif // SCR1_IMEM_AHB_OUT_BP
+logic                                       req_fifo_empty;
+logic                                       req_fifo_full;
+
+type_scr1_resp_fifo_s                       resp_fifo;
+logic                                       resp_fifo_hready;
+
+//-------------------------------------------------------------------------------
+// Interface to Core
+//-------------------------------------------------------------------------------
+assign imem_req_ack = ~req_fifo_full;
+assign req_fifo_wr  = ~req_fifo_full & imem_req;
+
+assign imem_rdata = resp_fifo.hrdata;
+
+assign imem_resp = (resp_fifo_hready)
+                    ? (resp_fifo.hresp == SCR1_HRESP_OKAY)
+                        ? SCR1_MEM_RESP_RDY_OK
+                        : SCR1_MEM_RESP_RDY_ER
+                    : SCR1_MEM_RESP_NOTRDY;
+
+//-------------------------------------------------------------------------------
+// REQ_FIFO
+//-------------------------------------------------------------------------------
+`ifdef SCR1_IMEM_AHB_OUT_BP
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        req_fifo_full <= 1'b0;
+    end else begin
+        if (~req_fifo_full) begin
+            req_fifo_full <= imem_req & ~req_fifo_rd;
+        end else begin
+            req_fifo_full <= ~req_fifo_rd;
+        end
+    end
+end
+assign req_fifo_empty = ~(req_fifo_full | imem_req);
+
+assign req_fifo_up    = ~req_fifo_rd & req_fifo_wr;
+always_ff @(posedge clk) begin
+    if (req_fifo_up) begin
+        req_fifo_r.haddr <= imem_addr;
+    end
+end
+
+assign req_fifo[0] = (req_fifo_full) ? req_fifo_r : imem_addr;
+
+`else // SCR1_IMEM_AHB_OUT_BP
+always_comb begin
+    req_fifo_up      = 1'b0;
+    req_fifo_cnt_new = req_fifo_cnt;
+    req_fifo_new     = req_fifo;
+    case ({req_fifo_rd, req_fifo_wr})
+        2'b00 : begin
+            // nothing todo
+        end
+        2'b01: begin
+            // FIFO write
+            req_fifo_up = 1'b1;
+            req_fifo_new[req_fifo_cnt].haddr  = imem_addr;
+            req_fifo_cnt_new = req_fifo_cnt + 1'b1;
+        end
+        2'b10 : begin
+            // FIFO read
+            req_fifo_up     = 1'b1;
+            req_fifo_new[0] = req_fifo_new[1];
+            req_fifo_new[1].haddr  = 'x;
+            req_fifo_cnt_new = req_fifo_cnt - 1'b1;
+        end
+        2'b11 : begin
+            // Read and Write FIFO. It is possible only when fifo_cnt = 1
+            req_fifo_up           = 1'b1;
+            req_fifo_new[0].haddr = imem_addr;
+        end
+        default : begin
+            req_fifo_up      = 'x;
+            req_fifo_cnt_new = 'x;
+            req_fifo_new     = 'x;
+        end
+    endcase
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        req_fifo_cnt <= '0;
+    end else begin
+        if (req_fifo_up) begin
+            req_fifo_cnt <= req_fifo_cnt_new;
+        end
+    end
+end
+assign req_fifo_full  = (req_fifo_cnt == SCR1_FIFO_WIDTH);
+assign req_fifo_empty = ~(|req_fifo_cnt);
+
+always_ff @(posedge clk) begin
+    if (req_fifo_up) begin
+        req_fifo <= req_fifo_new;
+    end
+end
+`endif // SCR1_IMEM_AHB_OUT_BP
+
+//-------------------------------------------------------------------------------
+// FSM
+//-------------------------------------------------------------------------------
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        fsm <= SCR1_FSM_ADDR;
+    end else begin
+        case (fsm)
+            SCR1_FSM_ADDR : begin
+                if (hready) begin
+                    fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
+                end
+            end
+            SCR1_FSM_DATA : begin
+                if (hready) begin
+                    if (hresp == SCR1_HRESP_OKAY) begin
+                        fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
+                    end else begin
+                        fsm <= SCR1_FSM_ADDR;
+                    end
+                end
+            end
+            default : begin
+                fsm <= SCR1_FSM_ERR;
+            end
+        endcase
+    end
+end
+
+always_comb begin
+    req_fifo_rd = 1'b0;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            if (hready) begin
+                req_fifo_rd = ~req_fifo_empty;
+            end
+        end
+        SCR1_FSM_DATA : begin
+            if (hready) begin
+                req_fifo_rd = ~req_fifo_empty & (hresp == SCR1_HRESP_OKAY);
+            end
+        end
+        default : begin
+            req_fifo_rd = 1'bx;
+        end
+    endcase
+end
+
+//-------------------------------------------------------------------------------
+// FIFO response
+//-------------------------------------------------------------------------------
+`ifdef SCR1_IMEM_AHB_IN_BP
+assign resp_fifo_hready = (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
+assign resp_fifo.hresp  = hresp;
+assign resp_fifo.hrdata = hrdata;
+`else // SCR1_IMEM_AHB_IN_BP
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        resp_fifo_hready <= 1'b0;
+    end else begin
+        resp_fifo_hready <= (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
+    end
+end
+
+always_ff @(posedge clk) begin
+    if (hready & (fsm == SCR1_FSM_DATA)) begin
+        resp_fifo.hresp  <= hresp;
+        resp_fifo.hrdata <= hrdata;
+    end
+end
+`endif // SCR1_IMEM_AHB_IN_BP
+
+//-------------------------------------------------------------------------------
+// Interface to AHB
+//-------------------------------------------------------------------------------
+assign hprot[SCR1_HPROT_DATA]  = 1'b0;
+assign hprot[SCR1_HPROT_PRV]   = 1'b0;
+assign hprot[SCR1_HPROT_BUF]   = 1'b0;
+assign hprot[SCR1_HPROT_CACHE] = 1'b0;
+
+assign hburst       = SCR1_HBURST_SINGLE;
+assign hsize        = SCR1_HSIZE_32B;
+assign hmastlock    = 1'b0;
+
+always_comb begin
+    htrans = SCR1_HTRANS_IDLE;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            if (~req_fifo_empty) begin
+                htrans = SCR1_HTRANS_NONSEQ;
+            end
+        end
+        SCR1_FSM_DATA : begin
+            if (hready) begin
+                if (hresp == SCR1_HRESP_OKAY) begin
+                    if (~req_fifo_empty) begin
+                        htrans = SCR1_HTRANS_NONSEQ;
+                    end
+                end
+            end
+        end
+        default : begin
+            htrans = SCR1_HTRANS_ERR;
+        end
+    endcase
+end
+
+assign haddr  = req_fifo[0].haddr;
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+// Check Core interface
+SCR1_SVA_IMEM_AHB_BRIDGE_REQ_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown(imem_req)
+    ) else $error("IMEM AHB bridge Error: imem_req has unknown values");
+
+SCR1_IMEM_AHB_BRIDGE_ADDR_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    imem_req |-> !$isunknown(imem_addr)
+    ) else $error("IMEM AHB bridge Error: imem_addr has unknown values");
+
+SCR1_IMEM_AHB_BRIDGE_ADDR_ALLIGN : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    imem_req |-> (imem_addr[1:0] == '0)
+    ) else $error("IMEM AHB bridge Error: imem_addr has unalign values");
+
+// Check AHB interface
+SCR1_IMEM_AHB_BRIDGE_HREADY_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown(hready)
+    ) else $error("IMEM AHB bridge Error: hready has unknown values");
+
+SCR1_IMEM_AHB_BRIDGE_HRESP_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    !$isunknown(hresp)
+    ) else $error("IMEM AHB bridge Error: hresp has unknown values");
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_imem_ahb
diff --git a/third_party/tests/Scr1/src/top/scr1_imem_router.sv b/third_party/tests/Scr1/src/top/scr1_imem_router.sv
new file mode 100644
index 0000000..3f51ccd
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_imem_router.sv
@@ -0,0 +1,177 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_imem_router.sv>
+/// @brief      Instruction memory router
+///
+`include "scr1_memif.svh"
+`include "scr1_arch_description.svh"
+
+module scr1_imem_router
+#(
+    parameter SCR1_ADDR_MASK    = `SCR1_IMEM_AWIDTH'hFFFF0000,
+    parameter SCR1_ADDR_PATTERN = `SCR1_IMEM_AWIDTH'h00010000
+)
+(
+    // Control signals
+    input   logic                           rst_n,
+    input   logic                           clk,
+
+    // Core interface
+    output  logic                           imem_req_ack,
+    input   logic                           imem_req,
+    input   type_scr1_mem_cmd_e             imem_cmd,
+    input   logic [`SCR1_IMEM_AWIDTH-1:0]   imem_addr,
+    output  logic [`SCR1_IMEM_DWIDTH-1:0]   imem_rdata,
+    output  type_scr1_mem_resp_e            imem_resp,
+
+    // PORT0 interface
+    input   logic                           port0_req_ack,
+    output  logic                           port0_req,
+    output  type_scr1_mem_cmd_e             port0_cmd,
+    output  logic [`SCR1_IMEM_AWIDTH-1:0]   port0_addr,
+    input   logic [`SCR1_IMEM_DWIDTH-1:0]   port0_rdata,
+    input   type_scr1_mem_resp_e            port0_resp,
+
+    // PORT1 interface
+    input   logic                           port1_req_ack,
+    output  logic                           port1_req,
+    output  type_scr1_mem_cmd_e             port1_cmd,
+    output  logic [`SCR1_IMEM_AWIDTH-1:0]   port1_addr,
+    input   logic [`SCR1_IMEM_DWIDTH-1:0]   port1_rdata,
+    input   type_scr1_mem_resp_e            port1_resp
+);
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {
+    SCR1_FSM_ADDR,
+    SCR1_FSM_DATA
+} type_scr1_fsm_e;
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+type_scr1_fsm_e                 fsm;
+logic                           port_sel;
+logic                           port_sel_r;
+logic [`SCR1_IMEM_DWIDTH-1:0]   sel_rdata;
+type_scr1_mem_resp_e            sel_resp;
+logic                           sel_req_ack;
+
+//-------------------------------------------------------------------------------
+// FSM
+//-------------------------------------------------------------------------------
+assign port_sel = ((imem_addr & SCR1_ADDR_MASK) == SCR1_ADDR_PATTERN);
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        fsm        <= SCR1_FSM_ADDR;
+        port_sel_r <= 1'b0;
+    end else begin
+        case (fsm)
+            SCR1_FSM_ADDR : begin
+                if (imem_req & sel_req_ack) begin
+                    fsm <= SCR1_FSM_DATA;
+                    port_sel_r <= port_sel;
+                end
+            end
+            SCR1_FSM_DATA : begin
+                case (sel_resp)
+                    SCR1_MEM_RESP_RDY_OK : begin
+                        if (imem_req & sel_req_ack) begin
+                            fsm <= SCR1_FSM_DATA;
+                            port_sel_r <= port_sel;
+                        end else begin
+                            fsm <= SCR1_FSM_ADDR;
+                        end
+                    end
+                    SCR1_MEM_RESP_RDY_ER : begin
+                        fsm <= SCR1_FSM_ADDR;
+                    end
+                    default : begin
+                    end
+                endcase
+            end
+            default : begin
+            end
+        endcase
+    end
+end
+
+always_comb begin
+    if ((fsm == SCR1_FSM_ADDR) | ((fsm == SCR1_FSM_DATA) & (sel_resp == SCR1_MEM_RESP_RDY_OK))) begin
+        sel_req_ack = (port_sel) ? port1_req_ack : port0_req_ack;
+    end else begin
+        sel_req_ack = 1'b0;
+    end
+end
+
+assign sel_rdata = (port_sel_r) ? port1_rdata : port0_rdata;
+assign sel_resp  = (port_sel_r) ? port1_resp  : port0_resp;
+
+//-------------------------------------------------------------------------------
+// Interface to core
+//-------------------------------------------------------------------------------
+assign imem_req_ack = sel_req_ack;
+assign imem_rdata   = sel_rdata;
+assign imem_resp    = sel_resp;
+
+//-------------------------------------------------------------------------------
+// Interface to PORT0
+//-------------------------------------------------------------------------------
+always_comb begin
+    port0_req = 1'b0;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            port0_req = imem_req & ~port_sel;
+        end
+        SCR1_FSM_DATA : begin
+            if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
+                port0_req = imem_req & ~port_sel;
+            end
+        end
+        default : begin
+        end
+    endcase
+end
+
+assign port0_cmd   = (~port_sel) ? imem_cmd  : SCR1_MEM_CMD_ERROR;
+assign port0_addr  = (~port_sel) ? imem_addr : 'x;
+
+//-------------------------------------------------------------------------------
+// Interface to PORT1
+//-------------------------------------------------------------------------------
+always_comb begin
+    port1_req = 1'b0;
+    case (fsm)
+        SCR1_FSM_ADDR : begin
+            port1_req = imem_req & port_sel;
+        end
+        SCR1_FSM_DATA : begin
+            if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
+                port1_req = imem_req & port_sel;
+            end
+        end
+        default : begin
+        end
+    endcase
+end
+
+assign port1_cmd   = (port_sel) ? imem_cmd  : SCR1_MEM_CMD_ERROR;
+assign port1_addr  = (port_sel) ? imem_addr : 'x;
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+SCR1_SVA_IMEM_RT_XCHECK : assert property (
+    @(negedge clk) disable iff (~rst_n)
+    imem_req |-> !$isunknown({port_sel, imem_cmd})
+    ) else $error("IMEM router Error: unknown values");
+
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_imem_router
diff --git a/third_party/tests/Scr1/src/top/scr1_mem_axi.sv b/third_party/tests/Scr1/src/top/scr1_mem_axi.sv
new file mode 100644
index 0000000..9032ed7
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_mem_axi.sv
@@ -0,0 +1,362 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_mem_axi.sv>
+/// @brief      Memory AXI bridge
+///
+
+`include "scr1_memif.svh"
+`include "scr1_arch_description.svh"
+
+module scr1_mem_axi
+#(
+    parameter SCR1_REQ_BUF_SIZE     = 2,                    // Power of 2 value
+    parameter SCR1_AXI_IDWIDTH      = 4,
+    parameter SCR1_ADDR_WIDTH       = 32,
+    parameter SCR1_AXI_REQ_BP       = 1,
+    parameter SCR1_AXI_RESP_BP      = 1
+)
+(
+    // Clock and Reset
+    input   logic                           clk,
+    input   logic                           rst_n,
+    input   logic                           axi_reinit,
+    // Core Interface
+    output  logic                           core_idle,
+    output  logic                           core_req_ack,
+    input   logic                           core_req,
+    input   type_scr1_mem_cmd_e             core_cmd,
+    input   type_scr1_mem_width_e           core_width,
+    input   logic [SCR1_ADDR_WIDTH-1:0]     core_addr,
+    input   logic [31:0]                    core_wdata,
+    output  logic [31:0]                    core_rdata,
+    output  type_scr1_mem_resp_e            core_resp,
+
+    // AXI
+    output  logic [SCR1_AXI_IDWIDTH-1:0]    awid,
+    output  logic [SCR1_ADDR_WIDTH-1:0]     awaddr,
+    output  logic [ 7:0]                    awlen,
+    output  logic [ 2:0]                    awsize,
+    output  logic [ 1:0]                    awburst,
+    output  logic                           awlock,
+    output  logic [ 3:0]                    awcache,
+    output  logic [ 2:0]                    awprot,
+    output  logic [ 3:0]                    awregion,
+    output  logic [ 3:0]                    awuser,
+    output  logic [ 3:0]                    awqos,
+    output  logic                           awvalid,
+    input   logic                           awready,
+    output  logic [31:0]                    wdata,
+    output  logic [3:0]                     wstrb,
+    output  logic                           wlast,
+    output  logic [3:0]                     wuser,
+    output  logic                           wvalid,
+    input   logic                           wready,
+    input   logic [SCR1_AXI_IDWIDTH-1:0]    bid,
+    input   logic [ 1:0]                    bresp,
+    input   logic                           bvalid,
+    input   logic [ 3:0]                    buser,
+    output  logic                           bready,
+    output  logic [SCR1_AXI_IDWIDTH-1:0]    arid,
+    output  logic [SCR1_ADDR_WIDTH-1:0]     araddr,
+    output  logic [ 7:0]                    arlen,
+    output  logic [ 2:0]                    arsize,
+    output  logic [ 1:0]                    arburst,
+    output  logic                           arlock,
+    output  logic [ 3:0]                    arcache,
+    output  logic [ 2:0]                    arprot,
+    output  logic [ 3:0]                    arregion,
+    output  logic [ 3:0]                    aruser,
+    output  logic [ 3:0]                    arqos,
+    output  logic                           arvalid,
+    input   logic                           arready,
+    input   logic [SCR1_AXI_IDWIDTH-1:0]    rid,
+    input   logic [31:0]                    rdata,
+    input   logic [ 1:0]                    rresp,
+    input   logic                           rlast,
+    input   logic [ 3:0]                    ruser,
+    input   logic                           rvalid,
+    output  logic                           rready
+);
+
+
+// Local functions
+function automatic logic [2:0] width2axsize (
+    input   type_scr1_mem_width_e    width );
+    logic [2:0] axsize;
+begin
+    case (width)
+        SCR1_MEM_WIDTH_BYTE :  axsize = 3'b000;
+        SCR1_MEM_WIDTH_HWORD:  axsize = 3'b001;
+        SCR1_MEM_WIDTH_WORD :  axsize = 3'b010;
+                     default:  axsize = 'x;
+    endcase
+
+    return axsize;
+end
+endfunction: width2axsize
+
+typedef struct packed {
+    type_scr1_mem_width_e                               axi_width;
+    logic                    [SCR1_ADDR_WIDTH-1:0]      axi_addr;
+    logic                                   [31:0]      axi_wdata;
+} type_scr1_request_s;
+
+typedef struct packed {
+    logic                                               req_write;
+    logic                                               req_addr;
+    logic                                               req_data;
+    logic                                               req_resp;
+} type_scr1_req_status_s;
+
+
+type_scr1_request_s         [SCR1_REQ_BUF_SIZE-1:0]     req_fifo;
+type_scr1_req_status_s      [SCR1_REQ_BUF_SIZE-1:0]     req_status;
+type_scr1_req_status_s      [SCR1_REQ_BUF_SIZE-1:0]     req_status_new;
+logic                       [SCR1_REQ_BUF_SIZE-1:0]     req_status_en;
+logic               [$clog2(SCR1_REQ_BUF_SIZE)-1:0]     req_aval_ptr;
+logic               [$clog2(SCR1_REQ_BUF_SIZE)-1:0]     req_proc_ptr;
+logic               [$clog2(SCR1_REQ_BUF_SIZE)-1:0]     req_done_ptr;
+logic                                                   rresp_err;
+logic                                       [31:0]      rcvd_rdata;
+type_scr1_mem_resp_e                                    rcvd_resp;
+logic                                                   force_read;
+logic                                                   force_write;
+
+
+
+assign core_req_ack =   ~axi_reinit                        &
+                        ~req_status[req_aval_ptr].req_resp &
+                         core_resp!=SCR1_MEM_RESP_RDY_ER;
+
+
+assign rready      = ~req_status[req_done_ptr].req_write;
+assign bready      =  req_status[req_done_ptr].req_write;
+
+
+assign force_read  = bit'(SCR1_AXI_REQ_BP) & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_RD;
+assign force_write = bit'(SCR1_AXI_REQ_BP) & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_WR;
+
+
+always_comb begin: idle_status
+    core_idle = 1'b1;
+    for (int unsigned i=0; i<SCR1_REQ_BUF_SIZE; ++i) begin
+        core_idle &= req_status[i].req_resp==1'b0;
+    end
+end
+
+always_ff @(posedge clk) begin
+    if (core_req & core_req_ack) begin
+        req_fifo[req_aval_ptr].axi_width <= core_width;
+        req_fifo[req_aval_ptr].axi_addr  <= core_addr;
+        req_fifo[req_aval_ptr].axi_wdata <= core_wdata;
+    end
+end
+
+// Request Status Queue
+// It is used for holding control info of processing requests
+
+// Combinational logic of Request Status Queue
+always_comb begin
+    // Default
+    req_status_en  = '0; // No update
+    req_status_new = req_status; // Hold request info
+
+    // Update status on new core request
+    if( core_req & core_req_ack ) begin
+        req_status_en[req_aval_ptr]            = 1'd1;
+
+        req_status_new[req_aval_ptr].req_resp  = 1'd1;
+        req_status_new[req_aval_ptr].req_write = core_cmd == SCR1_MEM_CMD_WR;
+
+        req_status_new[req_aval_ptr].req_addr  = ~( (force_read & arready) |
+                                                    (force_write & awready) );
+
+        req_status_new[req_aval_ptr].req_data  = ~( (force_write & wready & awlen == 8'd0) |
+                                                    (~force_write & core_cmd == SCR1_MEM_CMD_RD) );
+    end
+
+    // Update status on AXI address phase
+    if ( (awvalid & awready) | (arvalid & arready) ) begin
+        req_status_en[req_proc_ptr]           = 1'd1;
+        req_status_new[req_proc_ptr].req_addr = 1'd0;
+    end
+
+    // Update status on AXI data phase
+    if ( wvalid & wready & wlast ) begin
+        req_status_en[req_proc_ptr]           = 1'd1;
+        req_status_new[req_proc_ptr].req_data = 1'd0;
+    end
+
+    // Update status when AXI finish transaction
+    if ( (bvalid & bready) | (rvalid & rready & rlast) ) begin
+        req_status_en[req_done_ptr]           = 1'd1;
+        req_status_new[req_done_ptr].req_resp = 1'd0;
+    end
+end
+
+// Request Status Queue register
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        req_status <= '0;
+    end else begin
+        for (int unsigned i = 0; i < SCR1_REQ_BUF_SIZE; ++i) begin
+            if ( req_status_en[i] ) begin
+                req_status[i] <= req_status_new[i];
+            end
+        end
+    end
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n)                         req_aval_ptr <= '0;
+    else if (core_req & core_req_ack)   req_aval_ptr <= req_aval_ptr + 1'b1;
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        req_proc_ptr <= '0;
+    end else begin
+        if ((                                                    awvalid & awready & wvalid & wready & wlast) |
+            (~force_write & ~req_status[req_proc_ptr].req_data & awvalid & awready                          ) |
+            (~force_write & ~req_status[req_proc_ptr].req_addr &                     wvalid & wready & wlast) |
+            (               ~req_status[req_proc_ptr].req_data & arvalid & arready                          )  ) begin
+
+            req_proc_ptr <= req_proc_ptr + 1'b1;
+        end
+    end
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        req_done_ptr <= '0;
+    end else begin
+        if ((bvalid & bready | rvalid & rready & rlast) & req_status[req_done_ptr].req_resp) begin
+
+            req_done_ptr <= req_done_ptr + 1'b1;
+        end
+    end
+end
+
+
+
+assign arvalid = req_status[req_proc_ptr].req_addr & ~req_status[req_proc_ptr].req_write | force_read;
+assign awvalid = req_status[req_proc_ptr].req_addr &  req_status[req_proc_ptr].req_write | force_write;
+assign  wvalid = req_status[req_proc_ptr].req_data &  req_status[req_proc_ptr].req_write | force_write;
+
+assign araddr  = (~force_read )? req_fifo[req_proc_ptr].axi_addr : core_addr;
+assign awaddr  = (~force_write)? req_fifo[req_proc_ptr].axi_addr : core_addr;
+
+always_comb begin
+    if (bvalid & bready & req_status[req_done_ptr].req_resp) begin
+        rcvd_resp = (bresp==2'b00)? SCR1_MEM_RESP_RDY_OK :
+                                    SCR1_MEM_RESP_RDY_ER;
+    end else begin
+        if (rvalid & rready & rlast & req_status[req_done_ptr].req_resp) begin
+            rcvd_resp = (rresp==2'b00)? SCR1_MEM_RESP_RDY_OK :
+                                        SCR1_MEM_RESP_RDY_ER;
+        end else begin
+            rcvd_resp = SCR1_MEM_RESP_NOTRDY;
+        end
+    end
+end
+
+
+
+
+// Write data signals adaptation
+always_comb begin
+    if (force_write)
+        case (core_width)
+            SCR1_MEM_WIDTH_BYTE :  wstrb = 4'h1 << core_addr[1:0];
+            SCR1_MEM_WIDTH_HWORD:  wstrb = 4'h3 << core_addr[1:0];
+            SCR1_MEM_WIDTH_WORD :  wstrb = 4'hf << core_addr[1:0];
+                         default:  wstrb = 'x;
+        endcase
+    else
+        case (req_fifo[req_proc_ptr].axi_width)
+            SCR1_MEM_WIDTH_BYTE :  wstrb = 4'h1 << req_fifo[req_proc_ptr].axi_addr[1:0];
+            SCR1_MEM_WIDTH_HWORD:  wstrb = 4'h3 << req_fifo[req_proc_ptr].axi_addr[1:0];
+            SCR1_MEM_WIDTH_WORD :  wstrb = 4'hf << req_fifo[req_proc_ptr].axi_addr[1:0];
+                         default:  wstrb = 'x;
+        endcase
+end
+
+
+
+assign wdata = (force_write)?                       core_wdata << (8*                       core_addr[1:0]) :
+                              req_fifo[req_proc_ptr].axi_wdata << (8* req_fifo[req_proc_ptr].axi_addr[1:0]);
+
+
+// Read data adaptation
+always_comb begin
+    case (req_fifo[req_done_ptr].axi_width)
+        SCR1_MEM_WIDTH_BYTE :  rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
+        SCR1_MEM_WIDTH_HWORD:  rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
+        SCR1_MEM_WIDTH_WORD :  rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
+                     default:  rcvd_rdata = 'x;
+    endcase
+end
+
+
+generate
+    if (SCR1_AXI_RESP_BP == 1) begin : axi_resp_bp
+        assign core_rdata = (rvalid & rready & rlast) ? rcvd_rdata : '0;
+        assign core_resp  = (axi_reinit) ? SCR1_MEM_RESP_NOTRDY : rcvd_resp;
+    end else begin : axi_resp_no_bp
+        always_ff @(negedge rst_n, posedge clk) begin
+            if (~rst_n)              core_resp  <= SCR1_MEM_RESP_NOTRDY;
+            else                     core_resp  <= (axi_reinit) ? SCR1_MEM_RESP_NOTRDY : rcvd_resp;
+        end
+        always_ff @(posedge clk) begin
+            if (rvalid & rready & rlast) core_rdata <= rcvd_rdata;
+        end
+    end
+endgenerate
+
+
+
+// AXI interface assignments
+assign awid     = SCR1_AXI_IDWIDTH'(1);
+assign awlen    = 8'd0;
+assign awsize   = (force_write) ? width2axsize(core_width) : width2axsize(req_fifo[req_proc_ptr].axi_width);
+assign awburst  = 2'd1;
+assign awcache  = 4'd2;
+assign awlock   = '0;
+assign awprot   = '0;
+assign awregion = '0;
+assign awuser   = '0;
+assign awqos    = '0;
+
+assign arid     = SCR1_AXI_IDWIDTH'(0);
+assign arlen    = 8'd0;
+assign arsize   = (force_read) ? width2axsize(core_width) : width2axsize(req_fifo[req_proc_ptr].axi_width);
+assign arburst  = 2'd1;
+assign arcache  = 4'd2;
+assign arprot   = '0;
+assign arregion = '0;
+assign arlock   = '0;
+assign arqos    = '0;
+assign aruser   = '0;
+
+assign wlast    = 1'd1;
+assign wuser    = '0;
+
+
+`ifdef SCR1_SIM_ENV
+`ifndef VERILATOR
+
+// X checks
+SCR1_SVA_AXI_X_CHECK0  : assert property (@(negedge clk) disable iff (~rst_n)   !$isunknown({core_req, awready, wready, bvalid, arready, rvalid}) )
+                                                                                                        else $error("AXI bridge: X state on input");
+SCR1_SVA_AXI_X_CHECK1  : assert property (@(negedge clk) disable iff (~rst_n)   core_req |->
+                                                                                    !$isunknown({core_cmd, core_width, core_addr}) )
+                                                                                                        else $error("AXI bridge: X state on input");
+SCR1_SVA_AXI_X_CHECK2  : assert property (@(negedge clk) disable iff (~rst_n)   bvalid |->
+                                                                                    !$isunknown({bid, bresp}) )
+                                                                                                        else $error("AXI bridge: X state on input");
+SCR1_SVA_AXI_X_CHECK3  : assert property (@(negedge clk) disable iff (~rst_n)   rvalid |->
+                                                                                    !$isunknown({rid, rresp}) )
+                                                                                                        else $error("AXI bridge: X state on input");
+`endif // VERILATOR
+`endif // SCR1_SIM_ENV
+
+endmodule : scr1_mem_axi
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/top/scr1_tcm.sv b/third_party/tests/Scr1/src/top/scr1_tcm.sv
new file mode 100644
index 0000000..bce6974
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_tcm.sv
@@ -0,0 +1,131 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_tcm.sv>
+/// @brief      Tightly-Coupled Memory (TCM)
+///
+
+`include "scr1_memif.svh"
+`include "scr1_arch_description.svh"
+
+`ifdef SCR1_TCM_EN
+module scr1_tcm
+#(
+    parameter SCR1_TCM_SIZE = `SCR1_IMEM_AWIDTH'h00010000
+)
+(
+    // Control signals
+    input   logic                           clk,
+    input   logic                           rst_n,
+
+    // Core instruction interface
+    output  logic                           imem_req_ack,
+    input   logic                           imem_req,
+    input   logic [`SCR1_IMEM_AWIDTH-1:0]   imem_addr,
+    output  logic [`SCR1_IMEM_DWIDTH-1:0]   imem_rdata,
+    output  type_scr1_mem_resp_e            imem_resp,
+
+    // Core data interface
+    output  logic                           dmem_req_ack,
+    input   logic                           dmem_req,
+    input   type_scr1_mem_cmd_e             dmem_cmd,
+    input   type_scr1_mem_width_e           dmem_width,
+    input   logic [`SCR1_DMEM_AWIDTH-1:0]   dmem_addr,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]   dmem_wdata,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]   dmem_rdata,
+    output  type_scr1_mem_resp_e            dmem_resp
+);
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+logic                               imem_req_en;
+logic                               dmem_req_en;
+logic                               imem_rd;
+logic                               dmem_rd;
+logic                               dmem_wr;
+logic [`SCR1_DMEM_DWIDTH-1:0]       dmem_writedata;
+logic [`SCR1_DMEM_DWIDTH-1:0]       dmem_rdata_local;
+logic [3:0]                         dmem_byteen;
+logic [1:0]                         dmem_rdata_shift_reg;
+//-------------------------------------------------------------------------------
+// Core interface
+//-------------------------------------------------------------------------------
+assign imem_req_en = (imem_resp == SCR1_MEM_RESP_RDY_OK) ^ imem_req;
+assign dmem_req_en = (dmem_resp == SCR1_MEM_RESP_RDY_OK) ^ dmem_req;
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        imem_resp <= SCR1_MEM_RESP_NOTRDY;
+    end else if (imem_req_en) begin
+        imem_resp <= imem_req ? SCR1_MEM_RESP_RDY_OK : SCR1_MEM_RESP_NOTRDY;
+    end
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        dmem_resp <= SCR1_MEM_RESP_NOTRDY;
+    end else if (dmem_req_en) begin
+        dmem_resp <= dmem_req ? SCR1_MEM_RESP_RDY_OK : SCR1_MEM_RESP_NOTRDY;
+    end
+end
+
+assign imem_req_ack = 1'b1;
+assign dmem_req_ack = 1'b1;
+//-------------------------------------------------------------------------------
+// Memory data composing
+//-------------------------------------------------------------------------------
+assign imem_rd  = imem_req;
+assign dmem_rd  = dmem_req & (dmem_cmd == SCR1_MEM_CMD_RD);
+assign dmem_wr  = dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR);
+
+always_comb begin
+    dmem_writedata = dmem_wdata;
+    dmem_byteen    = 4'b1111;
+    case ( dmem_width )
+        SCR1_MEM_WIDTH_BYTE : begin
+            dmem_writedata  = {(`SCR1_DMEM_DWIDTH /  8){dmem_wdata[7:0]}};
+            dmem_byteen     = 1'b1 << dmem_addr[1:0];
+        end
+        SCR1_MEM_WIDTH_HWORD : begin
+            dmem_writedata  = {(`SCR1_DMEM_DWIDTH / 16){dmem_wdata[15:0]}};
+            dmem_byteen     = 2'b11 << {dmem_addr[1], 1'b0};
+        end
+        default : begin
+        end
+    endcase
+end
+//-------------------------------------------------------------------------------
+// Memory instantiation
+//-------------------------------------------------------------------------------
+scr1_dp_memory #(
+    .SCR1_WIDTH ( 32            ),
+    .SCR1_SIZE  ( SCR1_TCM_SIZE )
+) i_dp_memory (
+    .clk    ( clk                                   ),
+    // Instruction port
+    // Port A
+    .rena   ( imem_rd                               ),
+    .addra  ( imem_addr[$clog2(SCR1_TCM_SIZE)-1:2]  ),
+    .qa     ( imem_rdata                            ),
+    // Data port
+    // Port B
+    .renb   ( dmem_rd                               ),
+    .wenb   ( dmem_wr                               ),
+    .webb   ( dmem_byteen                           ),
+    .addrb  ( dmem_addr[$clog2(SCR1_TCM_SIZE)-1:2]  ),
+    .qb     ( dmem_rdata_local                      ),
+    .datab  ( dmem_writedata                        )
+);
+//-------------------------------------------------------------------------------
+// Data memory output generation
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk) begin
+    if (dmem_rd) begin
+        dmem_rdata_shift_reg <= dmem_addr[1:0];
+    end
+end
+
+assign dmem_rdata = dmem_rdata_local >> ( 8 * dmem_rdata_shift_reg );
+
+endmodule : scr1_tcm
+
+`endif // SCR1_TCM_EN
diff --git a/third_party/tests/Scr1/src/top/scr1_timer.sv b/third_party/tests/Scr1/src/top/scr1_timer.sv
new file mode 100644
index 0000000..56c2813
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_timer.sv
@@ -0,0 +1,271 @@
+/// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details
+/// @file       <scr1_timer.sv>
+/// @brief      Memory-mapped Timer
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_memif.svh"
+
+module scr1_timer (
+    // Common
+    input   logic                                   rst_n,
+    input   logic                                   clk,
+    input   logic                                   rtc_clk,
+
+    // Memory interface
+    input   logic                                   dmem_req,
+    input   type_scr1_mem_cmd_e                     dmem_cmd,
+    input   type_scr1_mem_width_e                   dmem_width,
+    input   logic [`SCR1_DMEM_AWIDTH-1:0]           dmem_addr,
+    input   logic [`SCR1_DMEM_DWIDTH-1:0]           dmem_wdata,
+    output  logic                                   dmem_req_ack,
+    output  logic [`SCR1_DMEM_DWIDTH-1:0]           dmem_rdata,
+    output  type_scr1_mem_resp_e                    dmem_resp,
+
+    // Timer interface
+    output  logic [63:0]                            timer_val,
+    output  logic                                   timer_irq
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters declaration
+//-------------------------------------------------------------------------------
+localparam int unsigned SCR1_TIMER_ADDR_WIDTH                               = 5;
+localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_CONTROL             = 5'h0;
+localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_DIVIDER             = 5'h4;
+localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMELO             = 5'h8;
+localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMEHI             = 5'hC;
+localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMECMPLO          = 5'h10;
+localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMECMPHI          = 5'h14;
+
+localparam int unsigned SCR1_TIMER_CONTROL_EN_OFFSET                        = 0;
+localparam int unsigned SCR1_TIMER_CONTROL_CLKSRC_OFFSET                    = 1;
+localparam int unsigned SCR1_TIMER_DIVIDER_WIDTH                            = 10;
+
+//-------------------------------------------------------------------------------
+// Local signals declaration
+//-------------------------------------------------------------------------------
+logic [63:0]                                        mtime_reg;
+logic [63:0]                                        mtime_new;
+logic [63:0]                                        mtimecmp_reg;
+logic [63:0]                                        mtimecmp_new;
+logic                                               timer_en;
+logic                                               timer_clksrc_rtc;
+logic [SCR1_TIMER_DIVIDER_WIDTH-1:0]                timer_div;
+
+logic                                               control_up;
+logic                                               divider_up;
+logic                                               mtimelo_up;
+logic                                               mtimehi_up;
+logic                                               mtimecmplo_up;
+logic                                               mtimecmphi_up;
+
+logic                                               dmem_req_valid;
+
+logic [3:0]                                         rtc_sync;
+logic                                               rtc_ext_pulse;
+logic [SCR1_TIMER_DIVIDER_WIDTH-1:0]                timeclk_cnt;
+logic                                               timeclk_cnt_en;
+logic                                               time_posedge;
+logic                                               time_cmp_flag;
+
+//-------------------------------------------------------------------------------
+// Registers
+//-------------------------------------------------------------------------------
+
+// CONTROL
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        timer_en            <= 1'b1;
+        timer_clksrc_rtc    <= 1'b0;
+    end else begin
+        if (control_up) begin
+            timer_en            <= dmem_wdata[SCR1_TIMER_CONTROL_EN_OFFSET];
+            timer_clksrc_rtc    <= dmem_wdata[SCR1_TIMER_CONTROL_CLKSRC_OFFSET];
+        end
+    end
+end
+
+// DIVIDER
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        timer_div   <= '0;
+    end else begin
+        if (divider_up) begin
+            timer_div   <= dmem_wdata[SCR1_TIMER_DIVIDER_WIDTH-1:0];
+        end
+    end
+end
+
+// MTIME
+assign time_posedge = (timeclk_cnt_en & (timeclk_cnt == 0));
+
+always_comb begin
+    mtime_new   = mtime_reg;
+    if (time_posedge) begin
+        mtime_new   = mtime_reg + 1'b1;
+    end
+    if (mtimelo_up) begin
+        mtime_new[31:0]     = dmem_wdata;
+    end
+    if (mtimehi_up) begin
+        mtime_new[63:32]    = dmem_wdata;
+    end
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        mtime_reg   <= '0;
+    end else begin
+        if (time_posedge | mtimelo_up | mtimehi_up) begin
+            mtime_reg   <= mtime_new;
+        end
+    end
+end
+
+// MTIMECMP
+always_comb begin
+    mtimecmp_new    = mtimecmp_reg;
+    if (mtimecmplo_up) begin
+        mtimecmp_new[31:0]  = dmem_wdata;
+    end
+    if (mtimecmphi_up) begin
+        mtimecmp_new[63:32] = dmem_wdata;
+    end
+end
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        mtimecmp_reg    <= '0;
+    end else begin
+        if (mtimecmplo_up | mtimecmphi_up) begin
+            mtimecmp_reg    <= mtimecmp_new;
+        end
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Interrupt pending
+//-------------------------------------------------------------------------------
+assign time_cmp_flag = (mtime_reg >= ((mtimecmplo_up | mtimecmphi_up) ? mtimecmp_new : mtimecmp_reg));
+
+always_ff @(posedge clk, negedge rst_n) begin
+    if (~rst_n) begin
+        timer_irq   <= 1'b0;
+    end else begin
+        if (~timer_irq) begin
+            timer_irq   <= time_cmp_flag;
+        end else begin // 1'b1
+            if (mtimecmplo_up | mtimecmphi_up) begin
+                timer_irq   <= time_cmp_flag;
+            end
+        end
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Timer divider
+//-------------------------------------------------------------------------------
+assign timeclk_cnt_en   = (~timer_clksrc_rtc ? 1'b1 : rtc_ext_pulse) & timer_en;
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        timeclk_cnt <= '0;
+    end else begin
+        case (1'b1)
+            divider_up      : timeclk_cnt   <= dmem_wdata[SCR1_TIMER_DIVIDER_WIDTH-1:0];
+            time_posedge    : timeclk_cnt   <= timer_div;
+            timeclk_cnt_en  : timeclk_cnt   <= timeclk_cnt - 1'b1;
+            default         : begin end
+        endcase
+    end
+end
+
+//-------------------------------------------------------------------------------
+// RTC synchronization
+//-------------------------------------------------------------------------------
+assign rtc_ext_pulse    = rtc_sync[3] ^ rtc_sync[2];
+
+always_ff @(negedge rst_n, posedge rtc_clk) begin
+    if (~rst_n) begin
+        rtc_sync[0] <= 1'b0;
+    end else begin
+        if (timer_clksrc_rtc) begin
+            rtc_sync[0] <= ~rtc_sync[0];
+        end
+    end
+end
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        rtc_sync[3:1]   <= '0;
+    end else begin
+        if (timer_clksrc_rtc) begin
+            rtc_sync[3:1]   <= rtc_sync[2:0];
+        end
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Memory interface
+//-------------------------------------------------------------------------------
+assign dmem_req_valid   =   (dmem_width == SCR1_MEM_WIDTH_WORD) & (~|dmem_addr[1:0]) &
+                            (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:2] <= (SCR1_TIMER_MTIMECMPHI >> 2));
+
+assign dmem_req_ack     = 1'b1;
+
+always_ff @(negedge rst_n, posedge clk) begin
+    if (~rst_n) begin
+        dmem_resp   <= SCR1_MEM_RESP_NOTRDY;
+        dmem_rdata  <= '0;
+    end else begin
+        if (dmem_req) begin
+            if (dmem_req_valid) begin
+                dmem_resp   <= SCR1_MEM_RESP_RDY_OK;
+                if (dmem_cmd == SCR1_MEM_CMD_RD) begin
+                    case (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:0])
+                        SCR1_TIMER_CONTROL      : dmem_rdata    <= `SCR1_DMEM_DWIDTH'({timer_clksrc_rtc, timer_en});
+                        SCR1_TIMER_DIVIDER      : dmem_rdata    <= `SCR1_DMEM_DWIDTH'(timer_div);
+                        SCR1_TIMER_MTIMELO      : dmem_rdata    <= mtime_reg[31:0];
+                        SCR1_TIMER_MTIMEHI      : dmem_rdata    <= mtime_reg[63:32];
+                        SCR1_TIMER_MTIMECMPLO   : dmem_rdata    <= mtimecmp_reg[31:0];
+                        SCR1_TIMER_MTIMECMPHI   : dmem_rdata    <= mtimecmp_reg[63:32];
+                        default                 : begin end
+                    endcase
+                end
+            end else begin
+                dmem_resp   <= SCR1_MEM_RESP_RDY_ER;
+            end
+        end else begin
+            dmem_resp   <= SCR1_MEM_RESP_NOTRDY;
+            dmem_rdata  <= '0;
+        end
+    end
+end
+
+always_comb begin
+    control_up      = 1'b0;
+    divider_up      = 1'b0;
+    mtimelo_up      = 1'b0;
+    mtimehi_up      = 1'b0;
+    mtimecmplo_up   = 1'b0;
+    mtimecmphi_up   = 1'b0;
+    if (dmem_req & dmem_req_valid & (dmem_cmd == SCR1_MEM_CMD_WR)) begin
+        case (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:0])
+            SCR1_TIMER_CONTROL      : control_up    = 1'b1;
+            SCR1_TIMER_DIVIDER      : divider_up    = 1'b1;
+            SCR1_TIMER_MTIMELO      : mtimelo_up    = 1'b1;
+            SCR1_TIMER_MTIMEHI      : mtimehi_up    = 1'b1;
+            SCR1_TIMER_MTIMECMPLO   : mtimecmplo_up = 1'b1;
+            SCR1_TIMER_MTIMECMPHI   : mtimecmphi_up = 1'b1;
+            default                 : begin end
+        endcase
+    end
+end
+
+//-------------------------------------------------------------------------------
+// Timer interface
+//-------------------------------------------------------------------------------
+assign timer_val    = mtime_reg;
+
+endmodule : scr1_timer
\ No newline at end of file
diff --git a/third_party/tests/Scr1/src/top/scr1_top_ahb.sv b/third_party/tests/Scr1/src/top/scr1_top_ahb.sv
new file mode 100644
index 0000000..4c7fe74
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_top_ahb.sv
@@ -0,0 +1,479 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_top_ahb.sv>
+/// @brief      SCR1 AHB top
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_memif.svh"
+`include "scr1_ahb.svh"
+`ifdef SCR1_IPIC_EN
+`include "scr1_ipic.svh"
+`endif // SCR1_IPIC_EN
+
+`ifdef SCR1_TCM_EN
+ `define SCR1_IMEM_ROUTER_EN
+`endif // SCR1_TCM_EN
+
+module scr1_top_ahb (
+    // Control
+    input   logic                                   pwrup_rst_n,            // Power-Up Reset
+    input   logic                                   rst_n,                  // Regular Reset signal
+    input   logic                                   cpu_rst_n,              // CPU Reset (Core Reset)
+    input   logic                                   test_mode,              // Test mode
+    input   logic                                   test_rst_n,             // Test mode's reset
+    input   logic                                   clk,                    // System clock
+    input   logic                                   rtc_clk,                // Real-time clock
+`ifdef SCR1_DBGC_EN
+    output  logic                                   ndm_rst_n_out,          // Non-DM Reset from the Debug Module (DM)
+`endif // SCR1_DBGC_EN
+
+    // Fuses
+    input   logic [`SCR1_XLEN-1:0]                  fuse_mhartid,           // Hart ID
+`ifdef SCR1_DBGC_EN
+    input   logic [31:0]                            fuse_idcode,            // TAPC IDCODE
+`endif // SCR1_DBGC_EN
+
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    input   logic [SCR1_IRQ_LINES_NUM-1:0]          irq_lines,              // IRQ lines to IPIC
+`else // SCR1_IPIC_EN
+    input   logic                                   ext_irq,                // External IRQ input
+`endif // SCR1_IPIC_EN
+    input   logic                                   soft_irq,               // Software IRQ input
+
+`ifdef SCR1_DBGC_EN
+    // -- JTAG I/F
+    input   logic                                   trst_n,
+    input   logic                                   tck,
+    input   logic                                   tms,
+    input   logic                                   tdi,
+    output  logic                                   tdo,
+    output  logic                                   tdo_en,
+`endif // SCR1_DBGC_EN
+
+    // Instruction Memory Interface
+    output  logic [3:0]                             imem_hprot,
+    output  logic [2:0]                             imem_hburst,
+    output  logic [2:0]                             imem_hsize,
+    output  logic [1:0]                             imem_htrans,
+    output  logic                                   imem_hmastlock,
+    output  logic [SCR1_AHB_WIDTH-1:0]              imem_haddr,
+    input   logic                                   imem_hready,
+    input   logic [SCR1_AHB_WIDTH-1:0]              imem_hrdata,
+    input   logic                                   imem_hresp,
+
+    // Data Memory Interface
+    output  logic [3:0]                             dmem_hprot,
+    output  logic [2:0]                             dmem_hburst,
+    output  logic [2:0]                             dmem_hsize,
+    output  logic [1:0]                             dmem_htrans,
+    output  logic                                   dmem_hmastlock,
+    output  logic [SCR1_AHB_WIDTH-1:0]              dmem_haddr,
+    output  logic                                   dmem_hwrite,
+    output  logic [SCR1_AHB_WIDTH-1:0]              dmem_hwdata,
+    input   logic                                   dmem_hready,
+    input   logic [SCR1_AHB_WIDTH-1:0]              dmem_hrdata,
+    input   logic                                   dmem_hresp
+);
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+// Reset logic
+logic                                               pwrup_rst_n_sync;
+logic                                               rst_n_sync;
+logic                                               cpu_rst_n_sync;
+logic                                               reset_n_sync;
+logic                                               reset_n;
+logic                                               core_rst_n_local;
+
+// Instruction memory interface from core to router
+logic                                               core_imem_req_ack;
+logic                                               core_imem_req;
+type_scr1_mem_cmd_e                                 core_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0]                       core_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0]                       core_imem_rdata;
+type_scr1_mem_resp_e                                core_imem_resp;
+
+// Data memory interface from core to router
+logic                                               core_dmem_req_ack;
+logic                                               core_dmem_req;
+type_scr1_mem_cmd_e                                 core_dmem_cmd;
+type_scr1_mem_width_e                               core_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0]                       core_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_rdata;
+type_scr1_mem_resp_e                                core_dmem_resp;
+
+// Instruction memory interface from router to AHB bridge
+logic                                               ahb_imem_req_ack;
+logic                                               ahb_imem_req;
+type_scr1_mem_cmd_e                                 ahb_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0]                       ahb_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0]                       ahb_imem_rdata;
+type_scr1_mem_resp_e                                ahb_imem_resp;
+
+// Data memory interface from router to AHB bridge
+logic                                               ahb_dmem_req_ack;
+logic                                               ahb_dmem_req;
+type_scr1_mem_cmd_e                                 ahb_dmem_cmd;
+type_scr1_mem_width_e                               ahb_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0]                       ahb_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       ahb_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       ahb_dmem_rdata;
+type_scr1_mem_resp_e                                ahb_dmem_resp;
+
+`ifdef SCR1_TCM_EN
+// Instruction memory interface from router to TCM
+logic                                               tcm_imem_req_ack;
+logic                                               tcm_imem_req;
+type_scr1_mem_cmd_e                                 tcm_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0]                       tcm_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0]                       tcm_imem_rdata;
+type_scr1_mem_resp_e                                tcm_imem_resp;
+
+// Data memory interface from router to TCM
+logic                                               tcm_dmem_req_ack;
+logic                                               tcm_dmem_req;
+type_scr1_mem_cmd_e                                 tcm_dmem_cmd;
+type_scr1_mem_width_e                               tcm_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0]                       tcm_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_rdata;
+type_scr1_mem_resp_e                                tcm_dmem_resp;
+`endif // SCR1_TCM_EN
+
+// Data memory interface from router to memory-mapped timer
+logic                                               timer_dmem_req_ack;
+logic                                               timer_dmem_req;
+type_scr1_mem_cmd_e                                 timer_dmem_cmd;
+type_scr1_mem_width_e                               timer_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0]                       timer_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_rdata;
+type_scr1_mem_resp_e                                timer_dmem_resp;
+
+logic                                               timer_irq;
+logic [63:0]                                        timer_val;
+
+
+//-------------------------------------------------------------------------------
+// Reset logic
+//-------------------------------------------------------------------------------
+// Power-Up Reset synchronizer
+scr1_reset_sync_cell i_pwrup_rstn_reset_sync (
+    .rst_n          (pwrup_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (pwrup_rst_n_sync)
+);
+
+// Regular Reset synchronizer
+scr1_reset_sync_cell i_rstn_reset_sync (
+    .rst_n          (rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (rst_n_sync)
+);
+
+// CPU Reset synchronizer
+scr1_reset_sync_cell i_cpu_rstn_reset_sync (
+    .rst_n          (cpu_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (cpu_rst_n_sync)
+);
+
+// Combo Reset (Power-Up and Regular Resets): reset_n
+scr1_reset_buf_cell i_reset_buf_cell (
+    .rst_n              (reset_n_sync),
+    .clk                (clk),
+    .test_mode          (test_mode),
+    .test_rst_n         (test_rst_n),
+    .reset_n_in         (1'b1),
+    .reset_n_out        (reset_n),
+    .reset_n_status     ()
+);
+assign reset_n_sync = rst_n_sync & pwrup_rst_n_sync;
+
+//-------------------------------------------------------------------------------
+// SCR1 core instance
+//-------------------------------------------------------------------------------
+scr1_core_top i_core_top (
+    // Control
+    .pwrup_rst_n    (pwrup_rst_n_sync   ),
+    .rst_n          (rst_n_sync         ),
+    .cpu_rst_n      (cpu_rst_n_sync     ),
+    .test_mode      (test_mode          ),
+    .test_rst_n     (test_rst_n         ),
+    .clk            (clk                ),
+    .core_rst_n_out (core_rst_n_local   ),
+`ifdef SCR1_DBGC_EN
+    .ndm_rst_n_out  (ndm_rst_n_out      ),
+`endif // SCR1_DBGC_EN
+    .fuse_mhartid   (fuse_mhartid       ),
+`ifdef SCR1_DBGC_EN
+    .fuse_idcode    (fuse_idcode        ),
+`endif // SCR1_DBGC_EN
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    .irq_lines      (irq_lines          ),
+`else // SCR1_IPIC_EN
+    .ext_irq        (ext_irq            ),
+`endif // SCR1_IPIC_EN
+    .soft_irq       (soft_irq           ),
+    .timer_irq      (timer_irq          ),
+    .mtime_ext      (timer_val          ),
+`ifdef SCR1_DBGC_EN
+    // JTAG interface
+    .trst_n         (trst_n             ),
+    .tck            (tck                ),
+    .tms            (tms                ),
+    .tdi            (tdi                ),
+    .tdo            (tdo                ),
+    .tdo_en         (tdo_en             ),
+`endif // SCR1_DBGC_EN
+    // Instruction memory interface
+    .imem_req_ack   (core_imem_req_ack  ),
+    .imem_req       (core_imem_req      ),
+    .imem_cmd       (core_imem_cmd      ),
+    .imem_addr      (core_imem_addr     ),
+    .imem_rdata     (core_imem_rdata    ),
+    .imem_resp      (core_imem_resp     ),
+    // Data memory interface
+    .dmem_req_ack   (core_dmem_req_ack  ),
+    .dmem_req       (core_dmem_req      ),
+    .dmem_cmd       (core_dmem_cmd      ),
+    .dmem_width     (core_dmem_width    ),
+    .dmem_addr      (core_dmem_addr     ),
+    .dmem_wdata     (core_dmem_wdata    ),
+    .dmem_rdata     (core_dmem_rdata    ),
+    .dmem_resp      (core_dmem_resp     )
+);
+
+
+`ifdef SCR1_TCM_EN
+//-------------------------------------------------------------------------------
+// TCM instance
+//-------------------------------------------------------------------------------
+scr1_tcm #(
+    .SCR1_TCM_SIZE  (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
+) i_tcm (
+    .clk            (clk                ),
+    .rst_n          (core_rst_n_local   ),
+    // Instruction interface to TCM
+    .imem_req_ack   (tcm_imem_req_ack   ),
+    .imem_req       (tcm_imem_req       ),
+    .imem_addr      (tcm_imem_addr      ),
+    .imem_rdata     (tcm_imem_rdata     ),
+    .imem_resp      (tcm_imem_resp      ),
+    // Data interface to TCM
+    .dmem_req_ack   (tcm_dmem_req_ack   ),
+    .dmem_req       (tcm_dmem_req       ),
+    .dmem_cmd       (tcm_dmem_cmd       ),
+    .dmem_width     (tcm_dmem_width     ),
+    .dmem_addr      (tcm_dmem_addr      ),
+    .dmem_wdata     (tcm_dmem_wdata     ),
+    .dmem_rdata     (tcm_dmem_rdata     ),
+    .dmem_resp      (tcm_dmem_resp      )
+);
+`endif // SCR1_TCM_EN
+
+
+//-------------------------------------------------------------------------------
+// Memory-mapped timer instance
+//-------------------------------------------------------------------------------
+scr1_timer i_timer (
+    // Common
+    .rst_n          (core_rst_n_local   ),
+    .clk            (clk                ),
+    .rtc_clk        (rtc_clk            ),
+    // Memory interface
+    .dmem_req       (timer_dmem_req     ),
+    .dmem_cmd       (timer_dmem_cmd     ),
+    .dmem_width     (timer_dmem_width   ),
+    .dmem_addr      (timer_dmem_addr    ),
+    .dmem_wdata     (timer_dmem_wdata   ),
+    .dmem_req_ack   (timer_dmem_req_ack ),
+    .dmem_rdata     (timer_dmem_rdata   ),
+    .dmem_resp      (timer_dmem_resp    ),
+    // Timer interface
+    .timer_val      (timer_val          ),
+    .timer_irq      (timer_irq          )
+);
+
+
+`ifdef SCR1_IMEM_ROUTER_EN
+//-------------------------------------------------------------------------------
+// Instruction memory router
+//-------------------------------------------------------------------------------
+scr1_imem_router #(
+    .SCR1_ADDR_MASK     (SCR1_TCM_ADDR_MASK),
+    .SCR1_ADDR_PATTERN  (SCR1_TCM_ADDR_PATTERN)
+) i_imem_router (
+    .rst_n          (core_rst_n_local   ),
+    .clk            (clk                ),
+    // Interface to core
+    .imem_req_ack   (core_imem_req_ack  ),
+    .imem_req       (core_imem_req      ),
+    .imem_cmd       (core_imem_cmd      ),
+    .imem_addr      (core_imem_addr     ),
+    .imem_rdata     (core_imem_rdata    ),
+    .imem_resp      (core_imem_resp     ),
+    // Interface to AHB bridge
+    .port0_req_ack  (ahb_imem_req_ack   ),
+    .port0_req      (ahb_imem_req       ),
+    .port0_cmd      (ahb_imem_cmd       ),
+    .port0_addr     (ahb_imem_addr      ),
+    .port0_rdata    (ahb_imem_rdata     ),
+    .port0_resp     (ahb_imem_resp      ),
+    // Interface to TCM
+    .port1_req_ack  (tcm_imem_req_ack   ),
+    .port1_req      (tcm_imem_req       ),
+    .port1_cmd      (tcm_imem_cmd       ),
+    .port1_addr     (tcm_imem_addr      ),
+    .port1_rdata    (tcm_imem_rdata     ),
+    .port1_resp     (tcm_imem_resp      )
+);
+
+`else // SCR1_IMEM_ROUTER_EN
+
+assign ahb_imem_req         = core_imem_req;
+assign ahb_imem_cmd         = core_imem_cmd;
+assign ahb_imem_addr        = core_imem_addr;
+assign core_imem_req_ack    = ahb_imem_req_ack;
+assign core_imem_resp       = ahb_imem_resp;
+assign core_imem_rdata      = ahb_imem_rdata;
+
+`endif // SCR1_IMEM_ROUTER_EN
+
+
+//-------------------------------------------------------------------------------
+// Data memory router
+//-------------------------------------------------------------------------------
+scr1_dmem_router #(
+
+`ifdef SCR1_TCM_EN
+    .SCR1_PORT1_ADDR_MASK       (SCR1_TCM_ADDR_MASK),
+    .SCR1_PORT1_ADDR_PATTERN    (SCR1_TCM_ADDR_PATTERN),
+`else // SCR1_TCM_EN
+    .SCR1_PORT1_ADDR_MASK       (32'h00000000),
+    .SCR1_PORT1_ADDR_PATTERN    (32'hFFFFFFFF),
+`endif // SCR1_TCM_EN
+
+    .SCR1_PORT2_ADDR_MASK       (SCR1_TIMER_ADDR_MASK),
+    .SCR1_PORT2_ADDR_PATTERN    (SCR1_TIMER_ADDR_PATTERN)
+
+) i_dmem_router (
+    .rst_n          (core_rst_n_local   ),
+    .clk            (clk                ),
+    // Interface to core
+    .dmem_req_ack   (core_dmem_req_ack  ),
+    .dmem_req       (core_dmem_req      ),
+    .dmem_cmd       (core_dmem_cmd      ),
+    .dmem_width     (core_dmem_width    ),
+    .dmem_addr      (core_dmem_addr     ),
+    .dmem_wdata     (core_dmem_wdata    ),
+    .dmem_rdata     (core_dmem_rdata    ),
+    .dmem_resp      (core_dmem_resp     ),
+`ifdef SCR1_TCM_EN
+    // Interface to TCM
+    .port1_req_ack  (tcm_dmem_req_ack   ),
+    .port1_req      (tcm_dmem_req       ),
+    .port1_cmd      (tcm_dmem_cmd       ),
+    .port1_width    (tcm_dmem_width     ),
+    .port1_addr     (tcm_dmem_addr      ),
+    .port1_wdata    (tcm_dmem_wdata     ),
+    .port1_rdata    (tcm_dmem_rdata     ),
+    .port1_resp     (tcm_dmem_resp      ),
+`else // SCR1_TCM_EN
+    .port1_req_ack  (1'b0),
+    .port1_req      (),
+    .port1_cmd      (),
+    .port1_width    (),
+    .port1_addr     (),
+    .port1_wdata    (),
+    .port1_rdata    ('0),
+    .port1_resp     (SCR1_MEM_RESP_RDY_ER),
+`endif // SCR1_TCM_EN
+    // Interface to memory-mapped timer
+    .port2_req_ack  (timer_dmem_req_ack ),
+    .port2_req      (timer_dmem_req     ),
+    .port2_cmd      (timer_dmem_cmd     ),
+    .port2_width    (timer_dmem_width   ),
+    .port2_addr     (timer_dmem_addr    ),
+    .port2_wdata    (timer_dmem_wdata   ),
+    .port2_rdata    (timer_dmem_rdata   ),
+    .port2_resp     (timer_dmem_resp    ),
+    // Interface to AHB bridge
+    .port0_req_ack  (ahb_dmem_req_ack   ),
+    .port0_req      (ahb_dmem_req       ),
+    .port0_cmd      (ahb_dmem_cmd       ),
+    .port0_width    (ahb_dmem_width     ),
+    .port0_addr     (ahb_dmem_addr      ),
+    .port0_wdata    (ahb_dmem_wdata     ),
+    .port0_rdata    (ahb_dmem_rdata     ),
+    .port0_resp     (ahb_dmem_resp      )
+);
+
+
+//-------------------------------------------------------------------------------
+// Instruction memory AHB bridge
+//-------------------------------------------------------------------------------
+scr1_imem_ahb i_imem_ahb (
+    .rst_n          (core_rst_n_local   ),
+    .clk            (clk                ),
+    // Interface to imem router
+    .imem_req_ack   (ahb_imem_req_ack   ),
+    .imem_req       (ahb_imem_req       ),
+    .imem_addr      (ahb_imem_addr      ),
+    .imem_rdata     (ahb_imem_rdata     ),
+    .imem_resp      (ahb_imem_resp      ),
+    // AHB interface
+    .hprot          (imem_hprot         ),
+    .hburst         (imem_hburst        ),
+    .hsize          (imem_hsize         ),
+    .htrans         (imem_htrans        ),
+    .hmastlock      (imem_hmastlock     ),
+    .haddr          (imem_haddr         ),
+    .hready         (imem_hready        ),
+    .hrdata         (imem_hrdata        ),
+    .hresp          (imem_hresp         )
+);
+
+
+//-------------------------------------------------------------------------------
+// Data memory AHB bridge
+//-------------------------------------------------------------------------------
+scr1_dmem_ahb i_dmem_ahb (
+    .rst_n          (core_rst_n_local   ),
+    .clk            (clk                ),
+    // Interface to dmem router
+    .dmem_req_ack   (ahb_dmem_req_ack   ),
+    .dmem_req       (ahb_dmem_req       ),
+    .dmem_cmd       (ahb_dmem_cmd       ),
+    .dmem_width     (ahb_dmem_width     ),
+    .dmem_addr      (ahb_dmem_addr      ),
+    .dmem_wdata     (ahb_dmem_wdata     ),
+    .dmem_rdata     (ahb_dmem_rdata     ),
+    .dmem_resp      (ahb_dmem_resp      ),
+    // AHB interface
+    .hprot          (dmem_hprot         ),
+    .hburst         (dmem_hburst        ),
+    .hsize          (dmem_hsize         ),
+    .htrans         (dmem_htrans        ),
+    .hmastlock      (dmem_hmastlock     ),
+    .haddr          (dmem_haddr         ),
+    .hwrite         (dmem_hwrite        ),
+    .hwdata         (dmem_hwdata        ),
+    .hready         (dmem_hready        ),
+    .hrdata         (dmem_hrdata        ),
+    .hresp          (dmem_hresp         )
+);
+
+endmodule : scr1_top_ahb
+
+
diff --git a/third_party/tests/Scr1/src/top/scr1_top_axi.sv b/third_party/tests/Scr1/src/top/scr1_top_axi.sv
new file mode 100644
index 0000000..abc4e11
--- /dev/null
+++ b/third_party/tests/Scr1/src/top/scr1_top_axi.sv
@@ -0,0 +1,652 @@
+/// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details
+/// @file       <scr1_top_axi.sv>
+/// @brief      SCR1 AXI top
+///
+
+`include "scr1_arch_description.svh"
+`include "scr1_memif.svh"
+`ifdef SCR1_IPIC_EN
+`include "scr1_ipic.svh"
+`endif // SCR1_IPIC_EN
+
+`ifdef SCR1_TCM_EN
+ `define SCR1_IMEM_ROUTER_EN
+`endif // SCR1_TCM_EN
+
+module scr1_top_axi (
+    // Control
+    input   logic                                   pwrup_rst_n,            // Power-Up Reset
+    input   logic                                   rst_n,                  // Regular Reset signal
+    input   logic                                   cpu_rst_n,              // CPU Reset (Core Reset)
+    input   logic                                   test_mode,              // Test mode
+    input   logic                                   test_rst_n,             // Test mode's reset
+    input   logic                                   clk,                    // System clock
+    input   logic                                   rtc_clk,                // Real-time clock
+`ifdef SCR1_DBGC_EN
+    output  logic                                   ndm_rst_n_out,          // Non-DM Reset from the Debug Module (DM)
+`endif // SCR1_DBGC_EN
+
+    // Fuses
+    input   logic [`SCR1_XLEN-1:0]                  fuse_mhartid,           // Hart ID
+`ifdef SCR1_DBGC_EN
+    input   logic [31:0]                            fuse_idcode,            // TAPC IDCODE
+`endif // SCR1_DBGC_EN
+
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    input   logic [SCR1_IRQ_LINES_NUM-1:0]          irq_lines,              // IRQ lines to IPIC
+`else // SCR1_IPIC_EN
+    input   logic                                   ext_irq,                // External IRQ input
+`endif // SCR1_IPIC_EN
+    input   logic                                   soft_irq,               // Software IRQ input
+
+`ifdef SCR1_DBGC_EN
+    // -- JTAG I/F
+    input   logic                                   trst_n,
+    input   logic                                   tck,
+    input   logic                                   tms,
+    input   logic                                   tdi,
+    output  logic                                   tdo,
+    output  logic                                   tdo_en,
+`endif // SCR1_DBGC_EN
+
+    // Instruction Memory Interface
+    output  logic [3:0]                             io_axi_imem_awid,
+    output  logic [31:0]                            io_axi_imem_awaddr,
+    output  logic [7:0]                             io_axi_imem_awlen,
+    output  logic [2:0]                             io_axi_imem_awsize,
+    output  logic [1:0]                             io_axi_imem_awburst,
+    output  logic                                   io_axi_imem_awlock,
+    output  logic [3:0]                             io_axi_imem_awcache,
+    output  logic [2:0]                             io_axi_imem_awprot,
+    output  logic [3:0]                             io_axi_imem_awregion,
+    output  logic [3:0]                             io_axi_imem_awuser,
+    output  logic [3:0]                             io_axi_imem_awqos,
+    output  logic                                   io_axi_imem_awvalid,
+    input   logic                                   io_axi_imem_awready,
+    output  logic [31:0]                            io_axi_imem_wdata,
+    output  logic [3:0]                             io_axi_imem_wstrb,
+    output  logic                                   io_axi_imem_wlast,
+    output  logic [3:0]                             io_axi_imem_wuser,
+    output  logic                                   io_axi_imem_wvalid,
+    input   logic                                   io_axi_imem_wready,
+    input   logic [3:0]                             io_axi_imem_bid,
+    input   logic [1:0]                             io_axi_imem_bresp,
+    input   logic                                   io_axi_imem_bvalid,
+    input   logic [3:0]                             io_axi_imem_buser,
+    output  logic                                   io_axi_imem_bready,
+    output  logic [3:0]                             io_axi_imem_arid,
+    output  logic [31:0]                            io_axi_imem_araddr,
+    output  logic [7:0]                             io_axi_imem_arlen,
+    output  logic [2:0]                             io_axi_imem_arsize,
+    output  logic [1:0]                             io_axi_imem_arburst,
+    output  logic                                   io_axi_imem_arlock,
+    output  logic [3:0]                             io_axi_imem_arcache,
+    output  logic [2:0]                             io_axi_imem_arprot,
+    output  logic [3:0]                             io_axi_imem_arregion,
+    output  logic [3:0]                             io_axi_imem_aruser,
+    output  logic [3:0]                             io_axi_imem_arqos,
+    output  logic                                   io_axi_imem_arvalid,
+    input   logic                                   io_axi_imem_arready,
+    input   logic [3:0]                             io_axi_imem_rid,
+    input   logic [31:0]                            io_axi_imem_rdata,
+    input   logic [1:0]                             io_axi_imem_rresp,
+    input   logic                                   io_axi_imem_rlast,
+    input   logic [3:0]                             io_axi_imem_ruser,
+    input   logic                                   io_axi_imem_rvalid,
+    output  logic                                   io_axi_imem_rready,
+
+    // Data Memory Interface
+    output  logic [3:0]                             io_axi_dmem_awid,
+    output  logic [31:0]                            io_axi_dmem_awaddr,
+    output  logic [7:0]                             io_axi_dmem_awlen,
+    output  logic [2:0]                             io_axi_dmem_awsize,
+    output  logic [1:0]                             io_axi_dmem_awburst,
+    output  logic                                   io_axi_dmem_awlock,
+    output  logic [3:0]                             io_axi_dmem_awcache,
+    output  logic [2:0]                             io_axi_dmem_awprot,
+    output  logic [3:0]                             io_axi_dmem_awregion,
+    output  logic [3:0]                             io_axi_dmem_awuser,
+    output  logic [3:0]                             io_axi_dmem_awqos,
+    output  logic                                   io_axi_dmem_awvalid,
+    input   logic                                   io_axi_dmem_awready,
+    output  logic [31:0]                            io_axi_dmem_wdata,
+    output  logic [3:0]                             io_axi_dmem_wstrb,
+    output  logic                                   io_axi_dmem_wlast,
+    output  logic [3:0]                             io_axi_dmem_wuser,
+    output  logic                                   io_axi_dmem_wvalid,
+    input   logic                                   io_axi_dmem_wready,
+    input   logic [3:0]                             io_axi_dmem_bid,
+    input   logic [1:0]                             io_axi_dmem_bresp,
+    input   logic                                   io_axi_dmem_bvalid,
+    input   logic [3:0]                             io_axi_dmem_buser,
+    output  logic                                   io_axi_dmem_bready,
+    output  logic [3:0]                             io_axi_dmem_arid,
+    output  logic [31:0]                            io_axi_dmem_araddr,
+    output  logic [7:0]                             io_axi_dmem_arlen,
+    output  logic [2:0]                             io_axi_dmem_arsize,
+    output  logic [1:0]                             io_axi_dmem_arburst,
+    output  logic                                   io_axi_dmem_arlock,
+    output  logic [3:0]                             io_axi_dmem_arcache,
+    output  logic [2:0]                             io_axi_dmem_arprot,
+    output  logic [3:0]                             io_axi_dmem_arregion,
+    output  logic [3:0]                             io_axi_dmem_aruser,
+    output  logic [3:0]                             io_axi_dmem_arqos,
+    output  logic                                   io_axi_dmem_arvalid,
+    input   logic                                   io_axi_dmem_arready,
+    input   logic [3:0]                             io_axi_dmem_rid,
+    input   logic [31:0]                            io_axi_dmem_rdata,
+    input   logic [1:0]                             io_axi_dmem_rresp,
+    input   logic                                   io_axi_dmem_rlast,
+    input   logic [3:0]                             io_axi_dmem_ruser,
+    input   logic                                   io_axi_dmem_rvalid,
+    output  logic                                   io_axi_dmem_rready
+);
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+// Reset logic
+logic                                               pwrup_rst_n_sync;
+logic                                               rst_n_sync;
+logic                                               cpu_rst_n_sync;
+logic                                               reset_n_sync;
+logic                                               reset_n;
+logic                                               core_rst_n_local;
+
+// Instruction memory interface from core to router
+logic                                               core_imem_req_ack;
+logic                                               core_imem_req;
+type_scr1_mem_cmd_e                                 core_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0]                       core_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0]                       core_imem_rdata;
+type_scr1_mem_resp_e                                core_imem_resp;
+
+// Data memory interface from core to router
+logic                                               core_dmem_req_ack;
+logic                                               core_dmem_req;
+type_scr1_mem_cmd_e                                 core_dmem_cmd;
+type_scr1_mem_width_e                               core_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0]                       core_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_rdata;
+type_scr1_mem_resp_e                                core_dmem_resp;
+
+// Instruction memory interface from router to AXI bridge
+logic                                               axi_imem_req_ack;
+logic                                               axi_imem_req;
+type_scr1_mem_cmd_e                                 axi_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0]                       axi_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0]                       axi_imem_rdata;
+type_scr1_mem_resp_e                                axi_imem_resp;
+
+// Data memory interface from router to AXI bridge
+logic                                               axi_dmem_req_ack;
+logic                                               axi_dmem_req;
+type_scr1_mem_cmd_e                                 axi_dmem_cmd;
+type_scr1_mem_width_e                               axi_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0]                       axi_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       axi_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       axi_dmem_rdata;
+type_scr1_mem_resp_e                                axi_dmem_resp;
+
+`ifdef SCR1_TCM_EN
+// Instruction memory interface from router to TCM
+logic                                               tcm_imem_req_ack;
+logic                                               tcm_imem_req;
+type_scr1_mem_cmd_e                                 tcm_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0]                       tcm_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0]                       tcm_imem_rdata;
+type_scr1_mem_resp_e                                tcm_imem_resp;
+
+// Data memory interface from router to TCM
+logic                                               tcm_dmem_req_ack;
+logic                                               tcm_dmem_req;
+type_scr1_mem_cmd_e                                 tcm_dmem_cmd;
+type_scr1_mem_width_e                               tcm_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0]                       tcm_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_rdata;
+type_scr1_mem_resp_e                                tcm_dmem_resp;
+`endif // SCR1_TCM_EN
+
+// Data memory interface from router to memory-mapped timer
+logic                                               timer_dmem_req_ack;
+logic                                               timer_dmem_req;
+type_scr1_mem_cmd_e                                 timer_dmem_cmd;
+type_scr1_mem_width_e                               timer_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0]                       timer_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_rdata;
+type_scr1_mem_resp_e                                timer_dmem_resp;
+
+// Misc
+logic                                               timer_irq;
+logic [63:0]                                        timer_val;
+logic                                               axi_reinit;
+logic                                               axi_imem_idle;
+logic                                               axi_dmem_idle;
+
+//-------------------------------------------------------------------------------
+// Reset logic
+//-------------------------------------------------------------------------------
+// Power-Up Reset synchronizer
+scr1_reset_sync_cell i_pwrup_rstn_reset_sync (
+    .rst_n          (pwrup_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (pwrup_rst_n_sync)
+);
+
+// Regular Reset synchronizer
+scr1_reset_sync_cell i_rstn_reset_sync (
+    .rst_n          (rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (rst_n_sync)
+);
+
+// CPU Reset synchronizer
+scr1_reset_sync_cell i_cpu_rstn_reset_sync (
+    .rst_n          (cpu_rst_n),
+    .clk            (clk),
+    .test_rst_n     (test_rst_n),
+    .test_mode      (test_mode),
+    .rst_n_out      (cpu_rst_n_sync)
+);
+
+// Combo Reset (Power-Up and Regular Resets): reset_n
+scr1_reset_buf_cell i_reset_buf_cell (
+    .rst_n              (reset_n_sync),
+    .clk                (clk),
+    .test_mode          (test_mode),
+    .test_rst_n         (test_rst_n),
+    .reset_n_in         (1'b1),
+    .reset_n_out        (reset_n),
+    .reset_n_status     ()
+);
+assign reset_n_sync = rst_n_sync & pwrup_rst_n_sync;
+
+//-------------------------------------------------------------------------------
+// SCR1 core instance
+//-------------------------------------------------------------------------------
+scr1_core_top i_core_top (
+    // Control
+    .pwrup_rst_n    (pwrup_rst_n_sync   ),
+    .rst_n          (rst_n_sync         ),
+    .cpu_rst_n      (cpu_rst_n_sync     ),
+    .test_mode      (test_mode          ),
+    .test_rst_n     (test_rst_n         ),
+    .clk            (clk                ),
+    .core_rst_n_out (core_rst_n_local   ),
+`ifdef SCR1_DBGC_EN
+    .ndm_rst_n_out  (ndm_rst_n_out      ),
+`endif // SCR1_DBGC_EN
+    .fuse_mhartid   (fuse_mhartid       ),
+`ifdef SCR1_DBGC_EN
+    .fuse_idcode    (fuse_idcode        ),
+`endif // SCR1_DBGC_EN
+    // IRQ
+`ifdef SCR1_IPIC_EN
+    .irq_lines      (irq_lines          ),
+`else // SCR1_IPIC_EN
+    .ext_irq        (ext_irq            ),
+`endif // SCR1_IPIC_EN
+    .soft_irq       (soft_irq           ),
+    .timer_irq      (timer_irq          ),
+    .mtime_ext      (timer_val          ),
+`ifdef SCR1_DBGC_EN
+    // JTAG interface
+    .trst_n         (trst_n             ),
+    .tck            (tck                ),
+    .tms            (tms                ),
+    .tdi            (tdi                ),
+    .tdo            (tdo                ),
+    .tdo_en         (tdo_en             ),
+`endif // SCR1_DBGC_EN
+    // Instruction memory interface
+    .imem_req_ack   (core_imem_req_ack  ),
+    .imem_req       (core_imem_req      ),
+    .imem_cmd       (core_imem_cmd      ),
+    .imem_addr      (core_imem_addr     ),
+    .imem_rdata     (core_imem_rdata    ),
+    .imem_resp      (core_imem_resp     ),
+    // Data memory interface
+    .dmem_req_ack   (core_dmem_req_ack  ),
+    .dmem_req       (core_dmem_req      ),
+    .dmem_cmd       (core_dmem_cmd      ),
+    .dmem_width     (core_dmem_width    ),
+    .dmem_addr      (core_dmem_addr     ),
+    .dmem_wdata     (core_dmem_wdata    ),
+    .dmem_rdata     (core_dmem_rdata    ),
+    .dmem_resp      (core_dmem_resp     )
+);
+
+
+`ifdef SCR1_TCM_EN
+//-------------------------------------------------------------------------------
+// TCM instance
+//-------------------------------------------------------------------------------
+scr1_tcm #(
+    .SCR1_TCM_SIZE  (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
+) i_tcm (
+    .clk            (clk                ),
+    .rst_n          (core_rst_n_local   ),
+    // Instruction interface to TCM
+    .imem_req_ack   (tcm_imem_req_ack   ),
+    .imem_req       (tcm_imem_req       ),
+    .imem_addr      (tcm_imem_addr      ),
+    .imem_rdata     (tcm_imem_rdata     ),
+    .imem_resp      (tcm_imem_resp      ),
+    // Data interface to TCM
+    .dmem_req_ack   (tcm_dmem_req_ack   ),
+    .dmem_req       (tcm_dmem_req       ),
+    .dmem_cmd       (tcm_dmem_cmd       ),
+    .dmem_width     (tcm_dmem_width     ),
+    .dmem_addr      (tcm_dmem_addr      ),
+    .dmem_wdata     (tcm_dmem_wdata     ),
+    .dmem_rdata     (tcm_dmem_rdata     ),
+    .dmem_resp      (tcm_dmem_resp      )
+);
+`endif // SCR1_TCM_EN
+
+
+//-------------------------------------------------------------------------------
+// Memory-mapped timer instance
+//-------------------------------------------------------------------------------
+scr1_timer i_timer (
+    // Common
+    .rst_n          (core_rst_n_local   ),
+    .clk            (clk                ),
+    .rtc_clk        (rtc_clk            ),
+    // Memory interface
+    .dmem_req       (timer_dmem_req     ),
+    .dmem_cmd       (timer_dmem_cmd     ),
+    .dmem_width     (timer_dmem_width   ),
+    .dmem_addr      (timer_dmem_addr    ),
+    .dmem_wdata     (timer_dmem_wdata   ),
+    .dmem_req_ack   (timer_dmem_req_ack ),
+    .dmem_rdata     (timer_dmem_rdata   ),
+    .dmem_resp      (timer_dmem_resp    ),
+    // Timer interface
+    .timer_val      (timer_val          ),
+    .timer_irq      (timer_irq          )
+);
+
+
+`ifdef SCR1_IMEM_ROUTER_EN
+//-------------------------------------------------------------------------------
+// Instruction memory router
+//-------------------------------------------------------------------------------
+scr1_imem_router #(
+    .SCR1_ADDR_MASK     (SCR1_TCM_ADDR_MASK),
+    .SCR1_ADDR_PATTERN  (SCR1_TCM_ADDR_PATTERN)
+) i_imem_router (
+    .rst_n          (core_rst_n_local   ),
+    .clk            (clk                ),
+    // Interface to core
+    .imem_req_ack   (core_imem_req_ack  ),
+    .imem_req       (core_imem_req      ),
+    .imem_cmd       (core_imem_cmd      ),
+    .imem_addr      (core_imem_addr     ),
+    .imem_rdata     (core_imem_rdata    ),
+    .imem_resp      (core_imem_resp     ),
+    // Interface to AXI bridge
+    .port0_req_ack  (axi_imem_req_ack   ),
+    .port0_req      (axi_imem_req       ),
+    .port0_cmd      (axi_imem_cmd       ),
+    .port0_addr     (axi_imem_addr      ),
+    .port0_rdata    (axi_imem_rdata     ),
+    .port0_resp     (axi_imem_resp      ),
+    // Interface to TCM
+    .port1_req_ack  (tcm_imem_req_ack   ),
+    .port1_req      (tcm_imem_req       ),
+    .port1_cmd      (tcm_imem_cmd       ),
+    .port1_addr     (tcm_imem_addr      ),
+    .port1_rdata    (tcm_imem_rdata     ),
+    .port1_resp     (tcm_imem_resp      )
+);
+
+`else // SCR1_IMEM_ROUTER_EN
+
+assign axi_imem_req         = core_imem_req;
+assign axi_imem_cmd         = core_imem_cmd;
+assign axi_imem_addr        = core_imem_addr;
+assign core_imem_req_ack    = axi_imem_req_ack;
+assign core_imem_resp       = axi_imem_resp;
+assign core_imem_rdata      = axi_imem_rdata;
+
+`endif // SCR1_IMEM_ROUTER_EN
+
+
+//-------------------------------------------------------------------------------
+// Data memory router
+//-------------------------------------------------------------------------------
+scr1_dmem_router #(
+
+`ifdef SCR1_TCM_EN
+    .SCR1_PORT1_ADDR_MASK       (SCR1_TCM_ADDR_MASK),
+    .SCR1_PORT1_ADDR_PATTERN    (SCR1_TCM_ADDR_PATTERN),
+`else // SCR1_TCM_EN
+    .SCR1_PORT1_ADDR_MASK       (32'h00000000),
+    .SCR1_PORT1_ADDR_PATTERN    (32'hFFFFFFFF),
+`endif // SCR1_TCM_EN
+
+    .SCR1_PORT2_ADDR_MASK       (SCR1_TIMER_ADDR_MASK),
+    .SCR1_PORT2_ADDR_PATTERN    (SCR1_TIMER_ADDR_PATTERN)
+
+) i_dmem_router (
+    .rst_n          (core_rst_n_local   ),
+    .clk            (clk                ),
+    // Interface to core
+    .dmem_req_ack   (core_dmem_req_ack  ),
+    .dmem_req       (core_dmem_req      ),
+    .dmem_cmd       (core_dmem_cmd      ),
+    .dmem_width     (core_dmem_width    ),
+    .dmem_addr      (core_dmem_addr     ),
+    .dmem_wdata     (core_dmem_wdata    ),
+    .dmem_rdata     (core_dmem_rdata    ),
+    .dmem_resp      (core_dmem_resp     ),
+`ifdef SCR1_TCM_EN
+    // Interface to TCM
+    .port1_req_ack  (tcm_dmem_req_ack   ),
+    .port1_req      (tcm_dmem_req       ),
+    .port1_cmd      (tcm_dmem_cmd       ),
+    .port1_width    (tcm_dmem_width     ),
+    .port1_addr     (tcm_dmem_addr      ),
+    .port1_wdata    (tcm_dmem_wdata     ),
+    .port1_rdata    (tcm_dmem_rdata     ),
+    .port1_resp     (tcm_dmem_resp      ),
+`else // SCR1_TCM_EN
+    .port1_req_ack  (1'b0),
+    .port1_req      (),
+    .port1_cmd      (),
+    .port1_width    (),
+    .port1_addr     (),
+    .port1_wdata    (),
+    .port1_rdata    ('0),
+    .port1_resp     (SCR1_MEM_RESP_RDY_ER),
+`endif // SCR1_TCM_EN
+    // Interface to memory-mapped timer
+    .port2_req_ack  (timer_dmem_req_ack ),
+    .port2_req      (timer_dmem_req     ),
+    .port2_cmd      (timer_dmem_cmd     ),
+    .port2_width    (timer_dmem_width   ),
+    .port2_addr     (timer_dmem_addr    ),
+    .port2_wdata    (timer_dmem_wdata   ),
+    .port2_rdata    (timer_dmem_rdata   ),
+    .port2_resp     (timer_dmem_resp    ),
+    // Interface to AXI bridge
+    .port0_req_ack  (axi_dmem_req_ack   ),
+    .port0_req      (axi_dmem_req       ),
+    .port0_cmd      (axi_dmem_cmd       ),
+    .port0_width    (axi_dmem_width     ),
+    .port0_addr     (axi_dmem_addr      ),
+    .port0_wdata    (axi_dmem_wdata     ),
+    .port0_rdata    (axi_dmem_rdata     ),
+    .port0_resp     (axi_dmem_resp      )
+);
+
+
+//-------------------------------------------------------------------------------
+// Instruction memory AXI bridge
+//-------------------------------------------------------------------------------
+scr1_mem_axi #(
+`ifdef SCR1_IMEM_AXI_REQ_BP
+    .SCR1_AXI_REQ_BP    (1),
+`else // SCR1_IMEM_AXI_REQ_BP
+    .SCR1_AXI_REQ_BP    (0),
+`endif // SCR1_IMEM_AXI_REQ_BP
+`ifdef SCR1_IMEM_AXI_RESP_BP
+    .SCR1_AXI_RESP_BP   (1)
+`else // SCR1_IMEM_AXI_RESP_BP
+    .SCR1_AXI_RESP_BP   (0)
+`endif // SCR1_IMEM_AXI_RESP_BP
+) i_imem_axi (
+    .clk            (clk                    ),
+    .rst_n          (reset_n                ),
+    .axi_reinit     (axi_reinit             ),
+    // Interface to core
+    .core_idle      (axi_imem_idle          ),
+    .core_req_ack   (axi_imem_req_ack       ),
+    .core_req       (axi_imem_req           ),
+    .core_cmd       (axi_imem_cmd           ),
+    .core_width     (SCR1_MEM_WIDTH_WORD    ),
+    .core_addr      (axi_imem_addr          ),
+    .core_wdata     ('0                     ),
+    .core_rdata     (axi_imem_rdata         ),
+    .core_resp      (axi_imem_resp          ),
+    // AXI I/O
+    .awid           (io_axi_imem_awid       ),
+    .awaddr         (io_axi_imem_awaddr     ),
+    .awlen          (io_axi_imem_awlen      ),
+    .awsize         (io_axi_imem_awsize     ),
+    .awburst        (io_axi_imem_awburst    ),
+    .awlock         (io_axi_imem_awlock     ),
+    .awcache        (io_axi_imem_awcache    ),
+    .awprot         (io_axi_imem_awprot     ),
+    .awregion       (io_axi_imem_awregion   ),
+    .awuser         (io_axi_imem_awuser     ),
+    .awqos          (io_axi_imem_awqos      ),
+    .awvalid        (io_axi_imem_awvalid    ),
+    .awready        (io_axi_imem_awready    ),
+    .wdata          (io_axi_imem_wdata      ),
+    .wstrb          (io_axi_imem_wstrb      ),
+    .wlast          (io_axi_imem_wlast      ),
+    .wuser          (io_axi_imem_wuser      ),
+    .wvalid         (io_axi_imem_wvalid     ),
+    .wready         (io_axi_imem_wready     ),
+    .bid            (io_axi_imem_bid        ),
+    .bresp          (io_axi_imem_bresp      ),
+    .bvalid         (io_axi_imem_bvalid     ),
+    .buser          (io_axi_imem_buser      ),
+    .bready         (io_axi_imem_bready     ),
+    .arid           (io_axi_imem_arid       ),
+    .araddr         (io_axi_imem_araddr     ),
+    .arlen          (io_axi_imem_arlen      ),
+    .arsize         (io_axi_imem_arsize     ),
+    .arburst        (io_axi_imem_arburst    ),
+    .arlock         (io_axi_imem_arlock     ),
+    .arcache        (io_axi_imem_arcache    ),
+    .arprot         (io_axi_imem_arprot     ),
+    .arregion       (io_axi_imem_arregion   ),
+    .aruser         (io_axi_imem_aruser     ),
+    .arqos          (io_axi_imem_arqos      ),
+    .arvalid        (io_axi_imem_arvalid    ),
+    .arready        (io_axi_imem_arready    ),
+    .rid            (io_axi_imem_rid        ),
+    .rdata          (io_axi_imem_rdata      ),
+    .rresp          (io_axi_imem_rresp      ),
+    .rlast          (io_axi_imem_rlast      ),
+    .ruser          (io_axi_imem_ruser      ),
+    .rvalid         (io_axi_imem_rvalid     ),
+    .rready         (io_axi_imem_rready     )
+);
+
+
+//-------------------------------------------------------------------------------
+// Data memory AXI bridge
+//-------------------------------------------------------------------------------
+scr1_mem_axi #(
+`ifdef SCR1_DMEM_AXI_REQ_BP
+    .SCR1_AXI_REQ_BP    (1),
+`else // SCR1_DMEM_AXI_REQ_BP
+    .SCR1_AXI_REQ_BP    (0),
+`endif // SCR1_DMEM_AXI_REQ_BP
+`ifdef SCR1_DMEM_AXI_RESP_BP
+    .SCR1_AXI_RESP_BP   (1)
+`else // SCR1_DMEM_AXI_RESP_BP
+    .SCR1_AXI_RESP_BP   (0)
+`endif // SCR1_DMEM_AXI_RESP_BP
+) i_dmem_axi (
+    .clk            (clk                    ),
+    .rst_n          (reset_n                ),
+    .axi_reinit     (axi_reinit             ),
+    // Interface to core
+    .core_idle      (axi_dmem_idle          ),
+    .core_req_ack   (axi_dmem_req_ack       ),
+    .core_req       (axi_dmem_req           ),
+    .core_cmd       (axi_dmem_cmd           ),
+    .core_width     (axi_dmem_width         ),
+    .core_addr      (axi_dmem_addr          ),
+    .core_wdata     (axi_dmem_wdata         ),
+    .core_rdata     (axi_dmem_rdata         ),
+    .core_resp      (axi_dmem_resp          ),
+    // AXI I/O
+    .awid           (io_axi_dmem_awid       ),
+    .awaddr         (io_axi_dmem_awaddr     ),
+    .awlen          (io_axi_dmem_awlen      ),
+    .awsize         (io_axi_dmem_awsize     ),
+    .awburst        (io_axi_dmem_awburst    ),
+    .awlock         (io_axi_dmem_awlock     ),
+    .awcache        (io_axi_dmem_awcache    ),
+    .awprot         (io_axi_dmem_awprot     ),
+    .awregion       (io_axi_dmem_awregion   ),
+    .awuser         (io_axi_dmem_awuser     ),
+    .awqos          (io_axi_dmem_awqos      ),
+    .awvalid        (io_axi_dmem_awvalid    ),
+    .awready        (io_axi_dmem_awready    ),
+    .wdata          (io_axi_dmem_wdata      ),
+    .wstrb          (io_axi_dmem_wstrb      ),
+    .wlast          (io_axi_dmem_wlast      ),
+    .wuser          (io_axi_dmem_wuser      ),
+    .wvalid         (io_axi_dmem_wvalid     ),
+    .wready         (io_axi_dmem_wready     ),
+    .bid            (io_axi_dmem_bid        ),
+    .bresp          (io_axi_dmem_bresp      ),
+    .bvalid         (io_axi_dmem_bvalid     ),
+    .buser          (io_axi_dmem_buser      ),
+    .bready         (io_axi_dmem_bready     ),
+    .arid           (io_axi_dmem_arid       ),
+    .araddr         (io_axi_dmem_araddr     ),
+    .arlen          (io_axi_dmem_arlen      ),
+    .arsize         (io_axi_dmem_arsize     ),
+    .arburst        (io_axi_dmem_arburst    ),
+    .arlock         (io_axi_dmem_arlock     ),
+    .arcache        (io_axi_dmem_arcache    ),
+    .arprot         (io_axi_dmem_arprot     ),
+    .arregion       (io_axi_dmem_arregion   ),
+    .aruser         (io_axi_dmem_aruser     ),
+    .arqos          (io_axi_dmem_arqos      ),
+    .arvalid        (io_axi_dmem_arvalid    ),
+    .arready        (io_axi_dmem_arready    ),
+    .rid            (io_axi_dmem_rid        ),
+    .rdata          (io_axi_dmem_rdata      ),
+    .rresp          (io_axi_dmem_rresp      ),
+    .rlast          (io_axi_dmem_rlast      ),
+    .ruser          (io_axi_dmem_ruser      ),
+    .rvalid         (io_axi_dmem_rvalid     ),
+    .rready         (io_axi_dmem_rready     )
+);
+
+//-------------------------------------------------------------------------------
+// AXI reinit logic
+//-------------------------------------------------------------------------------
+always_ff @(negedge core_rst_n_local, posedge clk) begin
+    if (~core_rst_n_local)                      axi_reinit <= 1'b1;
+    else if (axi_imem_idle & axi_dmem_idle)     axi_reinit <= 1'b0;
+end
+
+endmodule : scr1_top_axi
\ No newline at end of file
diff --git a/third_party/tests/SimpleVMM/SimpleVMM.log b/third_party/tests/SimpleVMM/SimpleVMM.log
index c6d6504..66f7774 100644
--- a/third_party/tests/SimpleVMM/SimpleVMM.log
+++ b/third_party/tests/SimpleVMM/SimpleVMM.log
@@ -111,49 +111,49 @@
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2625 Compile class "work@vmm_broadcast".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1801 Compile class "work@vmm_channel".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1803 Compile class "work@vmm_channel".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2002 Compile class "work@vmm_consensus".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2006 Compile class "work@vmm_consensus".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1540 Compile class "work@vmm_data".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1543 Compile class "work@vmm_data".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2192 Compile class "work@vmm_env".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2195 Compile class "work@vmm_env".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1076 Compile class "work@vmm_log".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1082 Compile class "work@vmm_log".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:286 Compile class "work@vmm_log_below_iter".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:287 Compile class "work@vmm_log_below_iter".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1040 Compile class "work@vmm_log_callbacks".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1044 Compile class "work@vmm_log_callbacks".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1063 Compile class "work@vmm_log_catcher".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1068 Compile class "work@vmm_log_catcher".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:93 Compile class "work@vmm_log_catcher_descr".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:97 Compile class "work@vmm_log_catcher_descr".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1013 Compile class "work@vmm_log_format".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1014 Compile class "work@vmm_log_format".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:23 Compile class "work@vmm_log_modifier".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:24 Compile class "work@vmm_log_modifier".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:65 Compile class "work@vmm_log_msg".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:68 Compile class "work@vmm_log_msg".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:44 Compile class "work@vmm_log_watchpoint".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_log.sv:46 Compile class "work@vmm_log_watchpoint".
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1748 Compile class "work@vmm_ms_scenario".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1776 Compile class "work@vmm_ms_scenario_election".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1777 Compile class "work@vmm_ms_scenario_election".
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2553 Compile class "work@vmm_ms_scenario_gen".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2533 Compile class "work@vmm_ms_scenario_gen_callbacks".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2536 Compile class "work@vmm_ms_scenario_gen_callbacks".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1430 Compile class "work@vmm_notification".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1435 Compile class "work@vmm_notification".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_notify.sv:23 Compile class "work@vmm_notification_config".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_notify.sv:24 Compile class "work@vmm_notification_config".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1449 Compile class "work@vmm_notify".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1455 Compile class "work@vmm_notify".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1425 Compile class "work@vmm_notify_callbacks".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:1429 Compile class "work@vmm_notify_callbacks".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:966 Compile class "work@vmm_opts".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:970 Compile class "work@vmm_opts".
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_opts.sv:23 Compile class "work@vmm_opts_info".
 
@@ -161,21 +161,21 @@
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2710 Compile class "work@vmm_scheduler".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2678 Compile class "work@vmm_scheduler_election".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2679 Compile class "work@vmm_scheduler_election".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2304 Compile class "work@vmm_subenv".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2306 Compile class "work@vmm_subenv".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2876 Compile class "work@vmm_test".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2877 Compile class "work@vmm_test".
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_test.sv:24 Compile class "work@vmm_test_registry".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_version.sv:28 Compile class "work@vmm_version".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm_version.sv:29 Compile class "work@vmm_version".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2149 Compile class "work@vmm_voter".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2151 Compile class "work@vmm_voter".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2378 Compile class "work@vmm_xactor".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2381 Compile class "work@vmm_xactor".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2374 Compile class "work@vmm_xactor_callbacks".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2376 Compile class "work@vmm_xactor_callbacks".
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2511 Compile class "work@vmm_xactor_iter".
 
@@ -183,7 +183,7 @@
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:733 Compile class "work@xvc_action_channel".
 
-[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2850 Compile class "work@xvc_manager".
+[INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2851 Compile class "work@xvc_manager".
 
 [INFO :CP0302] ../../UVM/vmm-1.1.1a/sv/std_lib/vmm.sv:2800 Compile class "work@xvc_xactor".
 
diff --git a/third_party/tests/UVMSwitch/UVMSwitch.log b/third_party/tests/UVMSwitch/UVMSwitch.log
index 3f82ece..14b62c6 100644
--- a/third_party/tests/UVMSwitch/UVMSwitch.log
+++ b/third_party/tests/UVMSwitch/UVMSwitch.log
@@ -21,266 +21,266 @@
 [INFO :PP0122] Preprocessing source file "top.sv".
 
 1 top.sv 1 in
-15 ../../UVM/uvm-1.2/src/uvm_macros.svh 1 in
-53 ../../UVM/uvm-1.2/src/macros/uvm_version_defines.svh 1 in
-186 ../../UVM/uvm-1.2/src/uvm_macros.svh 69 out
-186 ../../UVM/uvm-1.2/src/macros/uvm_global_defines.svh 1 in
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+3010 ../../UVM/uvm-1.2/src/uvm_macros.svh 76 out
+3010 ../../UVM/uvm-1.2/src/macros/uvm_callback_defines.svh 1 in
+3257 ../../UVM/uvm-1.2/src/uvm_macros.svh 77 out
+3257 ../../UVM/uvm-1.2/src/macros/uvm_reg_defines.svh 1 in
+3321 ../../UVM/uvm-1.2/src/uvm_macros.svh 78 out
+3321 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 1 in
+3497 ../../UVM/uvm-1.2/src/uvm_macros.svh 79 out
+3499 top.sv 17 out
+3502 Configuration.sv 1 in
+3536 top.sv 21 out
+3536 Packet.sv 1 in
+3582 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 253 in
+3583 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 439 in
+3591 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 255 out
+3592 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 409 in
+3601 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 256 out
+3602 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+3607 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 257 out
+3608 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 153 in
+3629 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 258 out
+3630 Packet.sv 49 out
+3631 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 628 in
+3664 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2615 in
+3671 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 662 out
+3673 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2592 in
+3680 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 664 out
+3702 Packet.sv 50 out
+3703 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 628 in
+3736 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2615 in
+3743 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 662 out
+3745 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2592 in
+3752 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 664 out
+3774 Packet.sv 51 out
+3775 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 628 in
+3808 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2615 in
+3815 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 662 out
+3817 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2592 in
+3824 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 664 out
+3846 Packet.sv 52 out
+3847 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1716 in
+3848 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1587 in
+3900 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1573 in
+3902 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1640 out
+3909 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2660 in
+3943 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1647 out
+3947 ../../UVM/uvm-1.2/src/macros/uvm_printer_defines.svh 100 in
+3948 ../../UVM/uvm-1.2/src/macros/uvm_printer_defines.svh 110 in
+3965 ../../UVM/uvm-1.2/src/macros/uvm_printer_defines.svh 50 in
+3970 ../../UVM/uvm-1.2/src/macros/uvm_printer_defines.svh 128 out
+3982 ../../UVM/uvm-1.2/src/macros/uvm_printer_defines.svh 50 in
+3987 ../../UVM/uvm-1.2/src/macros/uvm_printer_defines.svh 140 out
+3995 ../../UVM/uvm-1.2/src/macros/uvm_printer_defines.svh 102 out
+3996 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1651 out
+4012 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1573 in
+4014 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1668 out
+4038 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1573 in
+4040 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1692 out
+4052 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 1718 out
+4053 Packet.sv 53 out
+4054 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 628 in
+4087 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2615 in
+4094 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 662 out
+4096 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 2592 in
+4103 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 664 out
+4125 Packet.sv 54 out
+4126 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 264 in
+4129 Packet.sv 55 out
+4192 top.sv 22 out
+4192 Sequencer.sv 1 in
+4206 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 149 in
+4207 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 155 in
+4208 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 89 in
+4236 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 157 out
+4237 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 338 in
+4238 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 330 in
+4239 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 467 in
+4247 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 332 out
+4248 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+4253 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 333 out
+4254 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 340 out
+4255 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 153 in
+4276 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 341 out
+4277 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 158 out
+4278 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 151 out
+4279 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 214 in
+4280 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 346 in
+4283 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 216 out
+4284 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 152 out
+4285 Sequencer.sv 17 out
+4289 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 138 in
+4296 Sequencer.sv 21 out
+4311 top.sv 23 out
+4311 Sequence.sv 1 in
+4328 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 73 in
+4329 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 39 in
+4330 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 33 in
+4332 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 41 out
+4333 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 447 in
+4338 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 163 in
+4342 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 45 in
+4342 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 168 out
+4342 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 51 in
+4342 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 168 out
+4344 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 453 out
+4346 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 42 out
+4347 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 253 in
+4348 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 439 in
+4356 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 255 out
+4357 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 409 in
+4366 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 256 out
+4367 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+4372 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 257 out
+4373 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 153 in
+4394 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 258 out
+4395 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 43 out
+4396 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 75 out
+4397 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 46 in
+4398 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 264 in
+4401 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 48 out
+4402 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 76 out
+4403 Sequence.sv 19 out
+4407 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 113 in
+4408 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 199 in
+4411 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 146 in
+4417 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 203 out
+4420 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 129 in
+4423 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 45 in
+4423 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 133 out
+4423 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 51 in
+4423 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 133 out
+4425 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 206 out
+4430 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 115 out
+4431 Sequence.sv 23 out
+4432 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 113 in
+4433 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 199 in
+4436 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 146 in
+4442 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 203 out
+4445 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 129 in
+4448 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 45 in
+4448 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 133 out
+4448 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 51 in
+4448 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 133 out
+4450 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 206 out
+4455 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 115 out
+4456 Sequence.sv 24 out
+4470 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 73 in
+4471 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 39 in
+4472 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 33 in
+4474 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 41 out
+4475 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 447 in
+4480 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 163 in
+4484 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 45 in
+4484 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 168 out
+4484 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 51 in
+4484 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 168 out
+4486 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 453 out
+4488 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 42 out
+4489 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 253 in
+4490 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 439 in
+4498 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 255 out
+4499 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 409 in
+4508 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 256 out
+4509 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+4514 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 257 out
+4515 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 153 in
+4536 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 258 out
+4537 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 43 out
+4538 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 75 out
+4539 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 46 in
+4540 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 264 in
+4543 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 48 out
+4544 ../../UVM/uvm-1.2/src/macros/uvm_deprecated_defines.svh 76 out
+4545 Sequence.sv 38 out
+4549 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 113 in
+4550 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 199 in
+4553 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 146 in
+4559 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 203 out
+4562 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 129 in
+4565 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 45 in
+4565 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 133 out
+4565 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 51 in
+4565 ../../UVM/uvm-1.2/src/macros/uvm_message_defines.svh 133 out
+4567 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 206 out
+4572 ../../UVM/uvm-1.2/src/macros/uvm_sequence_defines.svh 115 out
+4573 Sequence.sv 42 out
+4580 top.sv 24 out
+4580 Driver.sv 1 in
+4599 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 330 in
+4600 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 467 in
+4608 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 332 out
+4609 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+4614 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 333 out
+4615 Driver.sv 22 out
+4713 top.sv 25 out
+4713 Receiver.sv 1 in
+4733 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 330 in
+4734 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 467 in
+4742 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 332 out
+4743 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+4748 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 333 out
+4749 Receiver.sv 23 out
+4807 top.sv 26 out
+4807 Scoreboard.sv 1 in
+4817 ../../UVM/uvm-1.2/src/macros/uvm_tlm_defines.svh 491 in
+4820 ../../UVM/uvm-1.2/src/tlm1/uvm_tlm_imps.svh 205 in
+4827 ../../UVM/uvm-1.2/src/tlm1/uvm_tlm_imps.svh 176 in
+4831 ../../UVM/uvm-1.2/src/tlm1/uvm_tlm_imps.svh 213 out
+4832 ../../UVM/uvm-1.2/src/macros/uvm_tlm_defines.svh 495 out
+4832 ../../UVM/uvm-1.2/src/macros/uvm_tlm_defines.svh 572 in
+4832 ../../UVM/uvm-1.2/src/macros/uvm_tlm_defines.svh 495 out
+4838 Scoreboard.sv 13 out
+4839 ../../UVM/uvm-1.2/src/macros/uvm_tlm_defines.svh 491 in
+4842 ../../UVM/uvm-1.2/src/tlm1/uvm_tlm_imps.svh 205 in
+4849 ../../UVM/uvm-1.2/src/tlm1/uvm_tlm_imps.svh 176 in
+4853 ../../UVM/uvm-1.2/src/tlm1/uvm_tlm_imps.svh 213 out
+4854 ../../UVM/uvm-1.2/src/macros/uvm_tlm_defines.svh 495 out
+4854 ../../UVM/uvm-1.2/src/macros/uvm_tlm_defines.svh 572 in
+4854 ../../UVM/uvm-1.2/src/macros/uvm_tlm_defines.svh 495 out
+4860 Scoreboard.sv 14 out
+4863 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 330 in
+4864 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 467 in
+4872 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 332 out
+4873 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+4878 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 333 out
+4879 Scoreboard.sv 17 out
+4924 top.sv 27 out
+4924 Environment.sv 1 in
+4937 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 330 in
+4938 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 467 in
+4946 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 332 out
+4947 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+4952 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 333 out
+4953 Environment.sv 16 out
+5001 top.sv 28 out
+5001 test.sv 1 in
+5011 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 330 in
+5012 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 467 in
+5020 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 332 out
+5021 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 427 in
+5026 ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh 333 out
+5027 test.sv 12 out
+5060 top.sv 29 out
 [INFO :PP0123] Preprocessing include file "../../UVM/uvm-1.2/src/uvm_macros.svh".
 
 [INFO :PP0123] Preprocessing include file "../../UVM/uvm-1.2/src/macros/uvm_version_defines.svh".
@@ -361,11 +361,11 @@
 
 [INFO :CP0301] uvm-1.2/src/uvm_pkg.sv:27 Compile package "uvm_pkg".
 
-[INFO :CP0304] interface.sv:43 Compile interface "work@input_interface".
+[INFO :CP0304] interface.sv:44 Compile interface "work@input_interface".
 
-[INFO :CP0304] interface.sv:17 Compile interface "work@mem_interface".
+[INFO :CP0304] interface.sv:18 Compile interface "work@mem_interface".
 
-[INFO :CP0304] interface.sv:67 Compile interface "work@output_interface".
+[INFO :CP0304] interface.sv:68 Compile interface "work@output_interface".
 
 [INFO :CP0303] rtl.sv:1 Compile module "work@switch".
 
@@ -1023,15 +1023,15 @@
 
 [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
 
-[INFO :CP0302] Configuration.sv:12 Compile class "work@top::Configuration".
+[INFO :CP0302] Configuration.sv:13 Compile class "work@top::Configuration".
 
-[INFO :CP0302] Driver.sv:11 Compile class "work@top::Driver".
+[INFO :CP0302] Driver.sv:12 Compile class "work@top::Driver".
 
-[INFO :CP0302] Environment.sv:12 Compile class "work@top::Environment".
+[INFO :CP0302] Environment.sv:13 Compile class "work@top::Environment".
 
-[INFO :CP0302] Packet.sv:15 Compile class "work@top::Packet".
+[INFO :CP0302] Packet.sv:16 Compile class "work@top::Packet".
 
-[INFO :CP0302] Receiver.sv:11 Compile class "work@top::Receiver".
+[INFO :CP0302] Receiver.sv:12 Compile class "work@top::Receiver".
 
 [INFO :CP0302] ../../UVM/uvm-1.2/src/macros/uvm_object_defines.svh:330 Compile class "work@top::Scoreboard".
 
@@ -1039,7 +1039,7 @@
 
 [INFO :CP0302] Sequence.sv:11 Compile class "work@top::Seq_device0_and_device1".
 
-[INFO :CP0302] Sequencer.sv:11 Compile class "work@top::Sequencer".
+[INFO :CP0302] Sequencer.sv:12 Compile class "work@top::Sequencer".
 
 [INFO :CP0302] test.sv:10 Compile class "work@top::test1".
 
diff --git a/third_party/tests/UtdSV/UtdSV.log b/third_party/tests/UtdSV/UtdSV.log
index 71f9be6..79f20f9 100644
--- a/third_party/tests/UtdSV/UtdSV.log
+++ b/third_party/tests/UtdSV/UtdSV.log
@@ -23,9 +23,9 @@
 [NOTE :PP0105] tlu.h:361 Multiply defined macro "INT_THR_HI",
                tlu.h:358 previous definition.
 
-[SYNTX:PA0207] ifdef-2.v:6 Syntax error: token recognition error at: '"first_block, second_block not defined,\n',
+[SYNTX:PA0207] ifdef-2.v:8 Syntax error: token recognition error at: '"first_block, second_block not defined,\n',
     "first_block, second_block not defined,
-    ^-- ../../../build/tests/UtdSV/slpp_unit/work/ifdef-2.v:6 col:4.
+    ^-- ../../../build/tests/UtdSV/slpp_unit/work/ifdef-2.v:8 col:4.
 
 [SYNTX:PA0207] pad_jbusl.v:351 Syntax error: no viable alternative at input 'bw_io_dtl_padx12 I61 (\n     .ps_select_buf   ({ps_sel_end } ),\n     .bypass_en_buf   ({bypass_en_end } ),\n     .serial_out      ({serial_out[127:116] } ),\n     .serial_in       ({serial_in[127:116] } ),\n     .to_core         ({io_jbi_j_ad[127:116] } ),\n     .pad             ({j_ad[127:116] } ),\n     .por_l_buf       ({net674[0] ,net674[1] } ),\n     .oe_buf          ({net675[0] ,net675[1] } ),\n     .reset_l_buf     ({net0234[0] ,net0234[1] } ),\n     .update_dr_buf   ({update_dr_end } ),\n     .cbu1            ({net682[0] ,net682[1] ,net682[2] ,net682[3] ,\n            net682[4] ,net682[5] ,net682[6] ,net682[7] } ),\n     .cbd1            ({net684[0] ,net684[1] ,net684[2] ,net684[3] ,\n            net684[4] ,net684[5] ,net684[6] ,net684[7] } ),\n     .up_open_buf     ({net664[0] ,net664[1] } ),\n     .mode_ctl_buf    ({mode_ctl_end } ),\n     .se_buf          ({se_buf_end } ),\n     .shift_dr_buf    ({shift_dr_end } ),\n     .hiz_l_buf       ({hiz_l_end } ),\n     .rst_val_dn_buf  ({net670[0] ,net670[1] } ),\n     .down_25_buf     ({net678[0] ,net678[1] } ),\n     .data            ({jbi_io_j_ad[127:116] } ),\n     .clock_dr_buf    ({clock_dr_end } ),\n     .rst_val_up_buf  ({net669[0] ,net669[1] } ),\n     .sel_bypass_buf  ({net667[0] ,net667[1] } ),\n     .cbu0            ({net683[0] ,net683[1] ,net683[2] ,net683[3] ,\n            net683[4] ,net683[5] ,net683[6] ,net683[7] } ),\n     .cbd0            ({net685[0] ,net685[1] ,net685[2] ,net685[3] ,\n            net685[4] ,net685[5] ,net685[6] ,net685[7] } ),\n     .rst_io_l_buf    ({net671[0] ,net671[1] } ),\n     .bso             (bscan[5] ),\n     .so              (scan[5] ),\n     .bsr_si          (pad_jbusl_bsi ),\n     .si              (pad_jbusl_headel_so ),\n     .clk             (clk ),\n     .vddo            (vddo ),\n     .ref',
      .ref             (dtl_l_vref ) );
@@ -247,7 +247,7 @@
 
 [WARNI:PA0205] loops.v:3 No timescale set for "tb_loops".
 
-[WARNI:PA0205] lsu_stb_ctldp.v:23 No timescale set for "lsu_stb_ctldp".
+[WARNI:PA0205] lsu_stb_ctldp.v:24 No timescale set for "lsu_stb_ctldp".
 
 [WARNI:PA0205] lsu_tagdp.v:21 No timescale set for "lsu_tagdp".
 
@@ -761,13 +761,13 @@
 
 [INFO :CP0303] lsu_pcx_qmon.v:35 Compile module "work@lsu_pcx_qmon".
 
-[INFO :CP0303] lsu_qdp1.v:38 Compile module "work@lsu_qdp1".
+[INFO :CP0303] lsu_qdp1.v:39 Compile module "work@lsu_qdp1".
 
-[INFO :CP0303] lsu_qdp2.v:40 Compile module "work@lsu_qdp2".
+[INFO :CP0303] lsu_qdp2.v:41 Compile module "work@lsu_qdp2".
 
 [INFO :CP0303] lsu_rrobin_picker2.v:36 Compile module "work@lsu_rrobin_picker2".
 
-[INFO :CP0303] lsu_stb_ctldp.v:23 Compile module "work@lsu_stb_ctldp".
+[INFO :CP0303] lsu_stb_ctldp.v:24 Compile module "work@lsu_stb_ctldp".
 
 [INFO :CP0303] lsu_stb_rwdp.v:37 Compile module "work@lsu_stb_rwdp".
 
@@ -1472,16 +1472,16 @@
 [NOTE :CP0309] lsu_pcx_qmon.v:37 Implicit port type (wire) for "so",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] lsu_qdp1.v:40 Implicit port type (wire) for "so",
+[NOTE :CP0309] lsu_qdp1.v:41 Implicit port type (wire) for "so",
 there are 49 more instances of this message.
 
-[NOTE :CP0309] lsu_qdp2.v:42 Implicit port type (wire) for "so",
+[NOTE :CP0309] lsu_qdp2.v:43 Implicit port type (wire) for "so",
 there are 41 more instances of this message.
 
 [NOTE :CP0309] lsu_rrobin_picker2.v:38 Implicit port type (wire) for "so",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] lsu_stb_ctldp.v:25 Implicit port type (wire) for "so",
+[NOTE :CP0309] lsu_stb_ctldp.v:26 Implicit port type (wire) for "so",
 there are 17 more instances of this message.
 
 [NOTE :CP0309] lsu_stb_rwdp.v:39 Implicit port type (wire) for "so",
@@ -2056,13 +2056,13 @@
 
 [NOTE :EL0503] lsu_pcx_qmon.v:35 Top level module "work@lsu_pcx_qmon".
 
-[NOTE :EL0503] lsu_qdp1.v:38 Top level module "work@lsu_qdp1".
+[NOTE :EL0503] lsu_qdp1.v:39 Top level module "work@lsu_qdp1".
 
-[NOTE :EL0503] lsu_qdp2.v:40 Top level module "work@lsu_qdp2".
+[NOTE :EL0503] lsu_qdp2.v:41 Top level module "work@lsu_qdp2".
 
 [NOTE :EL0503] lsu_rrobin_picker2.v:36 Top level module "work@lsu_rrobin_picker2".
 
-[NOTE :EL0503] lsu_stb_ctldp.v:23 Top level module "work@lsu_stb_ctldp".
+[NOTE :EL0503] lsu_stb_ctldp.v:24 Top level module "work@lsu_stb_ctldp".
 
 [NOTE :EL0503] lsu_stb_rwdp.v:37 Top level module "work@lsu_stb_rwdp".
 
@@ -2793,20 +2793,6 @@
 
 [WARNI:EL0500] ctu_top_rptr2.v:81 Cannot find a module definition for "work@ctu_top_rptr2::dff_s".
 
-[WARNI:EL0500] dbginit_mon.v:168 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:169 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:170 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:171 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:172 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:174 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:175 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:176 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:177 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2817,7 +2803,7 @@
 
 [WARNI:EL0500] dbginit_mon.v:180 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:181 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+[WARNI:EL0500] dbginit_mon.v:182 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:183 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
@@ -2827,44 +2813,44 @@
 
 [WARNI:EL0500] dbginit_mon.v:186 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:187 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:188 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:189 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:190 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:191 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:192 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:193 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:194 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:195 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:196 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:197 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:198 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:199 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:200 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:201 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:202 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:203 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:204 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:205 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:206 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:207 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:208 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:209 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:210 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:211 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:212 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2873,8 +2859,6 @@
 
 [WARNI:EL0500] dbginit_mon.v:214 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:215 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:216 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:217 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2883,6 +2867,8 @@
 
 [WARNI:EL0500] dbginit_mon.v:219 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:220 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:221 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:222 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2891,12 +2877,12 @@
 
 [WARNI:EL0500] dbginit_mon.v:224 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:225 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:226 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:227 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:228 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:229 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:230 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2905,8 +2891,6 @@
 
 [WARNI:EL0500] dbginit_mon.v:232 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:233 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:234 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:235 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2923,6 +2907,8 @@
 
 [WARNI:EL0500] dbginit_mon.v:241 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:242 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:243 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:244 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2931,12 +2917,12 @@
 
 [WARNI:EL0500] dbginit_mon.v:246 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:247 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:248 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:249 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:250 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:251 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:252 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2945,8 +2931,6 @@
 
 [WARNI:EL0500] dbginit_mon.v:254 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:255 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:256 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:257 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2955,6 +2939,14 @@
 
 [WARNI:EL0500] dbginit_mon.v:259 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:260 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:261 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:262 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:263 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] dbginit_mon.v:264 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:265 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -2963,30 +2955,6 @@
 
 [WARNI:EL0500] dbginit_mon.v:267 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
-[WARNI:EL0500] dbginit_mon.v:268 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:269 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:270 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:271 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:272 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:273 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:274 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:275 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:276 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:277 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:278 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
-[WARNI:EL0500] dbginit_mon.v:279 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
-
 [WARNI:EL0500] dbginit_mon.v:280 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
 [WARNI:EL0500] dbginit_mon.v:281 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
@@ -3003,6 +2971,38 @@
 
 [WARNI:EL0500] dbginit_mon.v:287 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
 
+[WARNI:EL0500] dbginit_mon.v:288 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:289 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:290 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:291 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:292 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:293 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:294 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:295 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:296 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:297 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:298 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:299 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:300 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:301 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:302 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
+[WARNI:EL0500] dbginit_mon.v:303 Cannot find a module definition for "work@dbginit_mon::dbginit_inst".
+
 [WARNI:EL0500] efc_lib.v:48 Cannot find a module definition for "work@bw_efc_latch::bw_u1_scanlg_2x".
 
 [WARNI:EL0500] ff_dram_sc_bank0.v:126 Cannot find a module definition for "work@ff_dram_sc_bank0::dff_s".
@@ -4893,19 +4893,19 @@
 
 [WARNI:EL0500] lsu_qdp1.v:332 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:360 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:361 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
 [WARNI:EL0500] lsu_qdp1.v:379 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:412 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:414 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
 [WARNI:EL0500] lsu_qdp1.v:435 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:465 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:466 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
 [WARNI:EL0500] lsu_qdp1.v:485 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:516 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:517 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
 [WARNI:EL0500] lsu_qdp1.v:536 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
@@ -4915,87 +4915,87 @@
 
 [WARNI:EL0500] lsu_qdp1.v:684 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:761 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:762 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:793 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:794 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:812 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:813 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:823 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:824 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:844 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:845 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:859 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:860 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:873 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:874 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:887 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:888 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:901 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:902 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:915 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:916 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:929 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:930 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:943 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:944 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:979 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:980 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1000 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1001 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1015 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
+[WARNI:EL0500] lsu_qdp1.v:1016 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1032 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1034 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1039 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1043 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1056 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:1062 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1078 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1084 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1092 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
+[WARNI:EL0500] lsu_qdp1.v:1098 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1109 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1116 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1116 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1125 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1132 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:1142 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1154 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1164 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1168 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
+[WARNI:EL0500] lsu_qdp1.v:1178 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1185 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1196 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1192 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1205 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1208 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
+[WARNI:EL0500] lsu_qdp1.v:1222 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1230 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1244 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1244 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
+[WARNI:EL0500] lsu_qdp1.v:1258 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1261 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1276 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1268 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1285 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1277 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1297 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1290 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1310 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1315 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1336 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1326 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1348 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1333 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1357 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1377 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1403 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1554 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1555 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1563 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
+[WARNI:EL0500] lsu_qdp1.v:1565 Cannot find a module definition for "work@lsu_qdp1::mux2ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1571 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1574 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
 [WARNI:EL0500] lsu_qdp1.v:1609 Cannot find a module definition for "work@lsu_qdp1::mux3ds".
 
@@ -5009,55 +5009,55 @@
 
 [WARNI:EL0500] lsu_qdp1.v:1726 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1741 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1742 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1748 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1751 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1759 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1764 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1766 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1773 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1777 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1786 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1784 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1795 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1795 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
+[WARNI:EL0500] lsu_qdp1.v:1808 Cannot find a module definition for "work@lsu_qdp1::clken_buf".
 
-[WARNI:EL0500] lsu_qdp1.v:1802 Cannot find a module definition for "work@lsu_qdp1::dff_s".
+[WARNI:EL0500] lsu_qdp1.v:1817 Cannot find a module definition for "work@lsu_qdp1::dff_s".
 
-[WARNI:EL0500] lsu_qdp1.v:1811 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1827 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1823 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1839 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp1.v:1856 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
+[WARNI:EL0500] lsu_qdp1.v:1873 Cannot find a module definition for "work@lsu_qdp1::mux4ds".
 
-[WARNI:EL0500] lsu_qdp2.v:298 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
+[WARNI:EL0500] lsu_qdp2.v:299 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
 
 [WARNI:EL0500] lsu_qdp2.v:314 Cannot find a module definition for "work@lsu_qdp2::dff_s".
 
-[WARNI:EL0500] lsu_qdp2.v:321 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
+[WARNI:EL0500] lsu_qdp2.v:323 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
 
 [WARNI:EL0500] lsu_qdp2.v:338 Cannot find a module definition for "work@lsu_qdp2::dff_s".
 
-[WARNI:EL0500] lsu_qdp2.v:345 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
+[WARNI:EL0500] lsu_qdp2.v:347 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
 
 [WARNI:EL0500] lsu_qdp2.v:362 Cannot find a module definition for "work@lsu_qdp2::dff_s".
 
-[WARNI:EL0500] lsu_qdp2.v:369 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
+[WARNI:EL0500] lsu_qdp2.v:371 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
 
 [WARNI:EL0500] lsu_qdp2.v:386 Cannot find a module definition for "work@lsu_qdp2::dff_s".
 
 [WARNI:EL0500] lsu_qdp2.v:394 Cannot find a module definition for "work@lsu_qdp2::mux4ds".
 
-[WARNI:EL0500] lsu_qdp2.v:469 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
+[WARNI:EL0500] lsu_qdp2.v:470 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
 
-[WARNI:EL0500] lsu_qdp2.v:475 Cannot find a module definition for "work@lsu_qdp2::dff_s".
+[WARNI:EL0500] lsu_qdp2.v:478 Cannot find a module definition for "work@lsu_qdp2::dff_s".
 
 [WARNI:EL0500] lsu_qdp2.v:547 Cannot find a module definition for "work@lsu_qdp2::mux2ds".
 
 [WARNI:EL0500] lsu_qdp2.v:558 Cannot find a module definition for "work@lsu_qdp2::mux2ds".
 
-[WARNI:EL0500] lsu_qdp2.v:604 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
+[WARNI:EL0500] lsu_qdp2.v:605 Cannot find a module definition for "work@lsu_qdp2::clken_buf".
 
 [WARNI:EL0500] lsu_qdp2.v:620 Cannot find a module definition for "work@lsu_qdp2::dff_s".
 
@@ -5101,37 +5101,37 @@
 
 [WARNI:EL0500] lsu_rrobin_picker2.v:160 Cannot find a module definition for "work@lsu_rrobin_picker2::dff_s".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:75 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
+[WARNI:EL0500] lsu_stb_ctldp.v:77 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:82 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
+[WARNI:EL0500] lsu_stb_ctldp.v:86 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:89 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
+[WARNI:EL0500] lsu_stb_ctldp.v:95 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:96 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
+[WARNI:EL0500] lsu_stb_ctldp.v:104 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:103 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
+[WARNI:EL0500] lsu_stb_ctldp.v:113 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:110 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
+[WARNI:EL0500] lsu_stb_ctldp.v:122 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:117 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
+[WARNI:EL0500] lsu_stb_ctldp.v:131 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:124 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
-
-[WARNI:EL0500] lsu_stb_ctldp.v:133 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
-
-[WARNI:EL0500] lsu_stb_ctldp.v:142 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
+[WARNI:EL0500] lsu_stb_ctldp.v:140 Cannot find a module definition for "work@lsu_stb_ctldp::clken_buf".
 
 [WARNI:EL0500] lsu_stb_ctldp.v:151 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:159 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
+[WARNI:EL0500] lsu_stb_ctldp.v:162 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:167 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
-
-[WARNI:EL0500] lsu_stb_ctldp.v:175 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
+[WARNI:EL0500] lsu_stb_ctldp.v:173 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
 
 [WARNI:EL0500] lsu_stb_ctldp.v:183 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
 
-[WARNI:EL0500] lsu_stb_ctldp.v:192 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
+[WARNI:EL0500] lsu_stb_ctldp.v:193 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
+
+[WARNI:EL0500] lsu_stb_ctldp.v:203 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
+
+[WARNI:EL0500] lsu_stb_ctldp.v:213 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
+
+[WARNI:EL0500] lsu_stb_ctldp.v:224 Cannot find a module definition for "work@lsu_stb_ctldp::dff_s".
 
 [WARNI:EL0500] lsu_stb_rwdp.v:118 Cannot find a module definition for "work@lsu_stb_rwdp::mux4ds".
 
@@ -6909,7 +6909,7 @@
 
 [WARNI:EL0500] sctag_wbctl.v:1136 Cannot find a module definition for "work@sctag_wbctl::dffrl_s".
 
-[WARNI:EL0500] sctag_wbctl.v:1168 Cannot find a module definition for "work@sctag_wbctl::dffrl_s".
+[WARNI:EL0500] sctag_wbctl.v:1172 Cannot find a module definition for "work@sctag_wbctl::dffrl_s".
 
 [WARNI:EL0500] sparc_exu_aluaddsub.v:68 Cannot find a module definition for "work@sparc_exu_aluaddsub::dff_s".
 
@@ -7195,13 +7195,13 @@
 
 [WARNI:EL0500] sparc_ffu_vis.v:169 Cannot find a module definition for "work@sparc_ffu_vis::mux3ds".
 
-[WARNI:EL0500] sparc_ifu_sscan.v:46 Cannot find a module definition for "work@sparc_ifu_sscan::dff_s".
+[WARNI:EL0500] sparc_ifu_sscan.v:47 Cannot find a module definition for "work@sparc_ifu_sscan::dff_s".
 
-[WARNI:EL0500] sparc_ifu_sscan.v:50 Cannot find a module definition for "work@sparc_ifu_sscan::dffe_s".
+[WARNI:EL0500] sparc_ifu_sscan.v:51 Cannot find a module definition for "work@sparc_ifu_sscan::dffe_s".
 
-[WARNI:EL0500] sparc_ifu_sscan.v:52 Cannot find a module definition for "work@sparc_ifu_sscan::dff_s".
+[WARNI:EL0500] sparc_ifu_sscan.v:54 Cannot find a module definition for "work@sparc_ifu_sscan::dff_s".
 
-[WARNI:EL0500] sparc_ifu_sscan.v:57 Cannot find a module definition for "work@sparc_ifu_sscan::sink".
+[WARNI:EL0500] sparc_ifu_sscan.v:60 Cannot find a module definition for "work@sparc_ifu_sscan::sink".
 
 [WARNI:EL0500] sparc_ifu_thrcmpl.v:129 Cannot find a module definition for "work@sparc_ifu_thrcmpl::dffr_s".
 
diff --git a/third_party/tests/Verilator/Verilator.log b/third_party/tests/Verilator/Verilator.log
index dcdc149..314546b 100644
--- a/third_party/tests/Verilator/Verilator.log
+++ b/third_party/tests/Verilator/Verilator.log
@@ -3852,9 +3852,9 @@
 
 [INFO :PA0201] Parsing source file "t_clk_concat2.v".
 
-[SYNTX:PA0207] t_clk_concat2.v:80 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
+[SYNTX:PA0207] t_clk_concat2.v:82 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
    input       clk;
-   ^-- ../../../build/tests/Verilator/slpp_unit/work/t_clk_concat2.v:80 col:3.
+   ^-- ../../../build/tests/Verilator/slpp_unit/work/t_clk_concat2.v:82 col:3.
 
 [INFO :PA0201] Parsing source file "t_clk_concat3.v".
 
@@ -3972,11 +3972,11 @@
 
 [INFO :PA0201] Parsing source file "t_dpi_display.v".
 
-[SYNTX:PA0207] t_dpi_display.v:10 Syntax error: no viable alternative at input 'module t ();\n\n   SURELOG_MACRO_NOT_DEFINED:error!!!  "Only Verilator supports PLI-ish DPI calls and sformat conversion."',
+[SYNTX:PA0207] t_dpi_display.v:11 Syntax error: no viable alternative at input 'module t ();\n\n\n   SURELOG_MACRO_NOT_DEFINED:error!!!  "Only Verilator supports PLI-ish DPI calls and sformat conversion."',
    SURELOG_MACRO_NOT_DEFINED:error!!!  "Only Verilator supports PLI-ish DPI calls and sformat conversion."
-                                       ^-- ../../../build/tests/Verilator/slpp_unit/work/t_dpi_display.v:10 col:39.
+                                       ^-- ../../../build/tests/Verilator/slpp_unit/work/t_dpi_display.v:11 col:39.
 
-[ERROR:PA0203] t_dpi_display.v:10 Unknown macro "error".
+[ERROR:PA0203] t_dpi_display.v:11 Unknown macro "error".
 
 [INFO :PA0201] Parsing source file "t_dpi_dup_bad.v".
 
@@ -4010,19 +4010,19 @@
 
 [INFO :PA0201] Parsing source file "t_dpi_sys.v".
 
-[SYNTX:PA0207] t_dpi_sys.v:14 Syntax error: no viable alternative at input 'module t ();\n\n   SURELOG_MACRO_NOT_DEFINED:error!!!  "Only Verilator supports PLI-ish DPI calls."',
+[SYNTX:PA0207] t_dpi_sys.v:15 Syntax error: no viable alternative at input 'module t ();\n\n\n   SURELOG_MACRO_NOT_DEFINED:error!!!  "Only Verilator supports PLI-ish DPI calls."',
    SURELOG_MACRO_NOT_DEFINED:error!!!  "Only Verilator supports PLI-ish DPI calls."
-                                       ^-- ../../../build/tests/Verilator/slpp_unit/work/t_dpi_sys.v:14 col:39.
+                                       ^-- ../../../build/tests/Verilator/slpp_unit/work/t_dpi_sys.v:15 col:39.
 
-[ERROR:PA0203] t_dpi_sys.v:14 Unknown macro "error".
+[ERROR:PA0203] t_dpi_sys.v:15 Unknown macro "error".
 
 [INFO :PA0201] Parsing source file "t_dpi_threads.v".
 
-[SYNTX:PA0207] t_dpi_threads.v:18 Syntax error: extraneous input '"Only Verilator supports PLI-ish DPI calls."' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
+[SYNTX:PA0207] t_dpi_threads.v:19 Syntax error: extraneous input '"Only Verilator supports PLI-ish DPI calls."' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
    SURELOG_MACRO_NOT_DEFINED:error!!!  "Only Verilator supports PLI-ish DPI calls."
-                                       ^-- ../../../build/tests/Verilator/slpp_unit/work/t_dpi_threads.v:18 col:39.
+                                       ^-- ../../../build/tests/Verilator/slpp_unit/work/t_dpi_threads.v:19 col:39.
 
-[ERROR:PA0203] t_dpi_threads.v:18 Unknown macro "error".
+[ERROR:PA0203] t_dpi_threads.v:19 Unknown macro "error".
 
 [INFO :PA0201] Parsing source file "t_dpi_vams.v".
 
@@ -4030,11 +4030,11 @@
 
 [INFO :PA0201] Parsing source file "t_dpi_var.v".
 
-[SYNTX:PA0207] t_dpi_var.v:64 Syntax error: no viable alternative at input 'module sub (/*AUTOARG*/\n   // Outputs\n   fr_a, fr_b, fr_chk,\n   // Inputs\n   in\n   );\n\nSURELOG_MACRO_NOT_DEFINED:systemc_imp_header!!! \n  void',
+[SYNTX:PA0207] t_dpi_var.v:65 Syntax error: no viable alternative at input 'module sub (/*AUTOARG*/\n   // Outputs\n   fr_a, fr_b, fr_chk,\n   // Inputs\n   in\n   );\n\nSURELOG_MACRO_NOT_DEFINED:systemc_imp_header!!! \n  void',
   void mon_class_name(const char* namep);
-  ^-- ../../../build/tests/Verilator/slpp_unit/work/t_dpi_var.v:64 col:2.
+  ^-- ../../../build/tests/Verilator/slpp_unit/work/t_dpi_var.v:65 col:2.
 
-[ERROR:PA0203] t_dpi_var.v:63 Unknown macro "systemc_imp_header".
+[ERROR:PA0203] t_dpi_var.v:64 Unknown macro "systemc_imp_header".
 
 [INFO :PA0201] Parsing source file "t_embed1.v".
 
@@ -4344,11 +4344,11 @@
 
 [INFO :PA0201] Parsing source file "t_gen_missing.v".
 
-[SYNTX:PA0207] t_gen_missing.v:8 Syntax error: extraneous input '"Bad Test"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
+[SYNTX:PA0207] t_gen_missing.v:9 Syntax error: extraneous input '"Bad Test"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
  SURELOG_MACRO_NOT_DEFINED:error!!!  "Bad Test"
-                                     ^-- ../../../build/tests/Verilator/slpp_unit/work/t_gen_missing.v:8 col:37.
+                                     ^-- ../../../build/tests/Verilator/slpp_unit/work/t_gen_missing.v:9 col:37.
 
-[ERROR:PA0203] t_gen_missing.v:8 Unknown macro "error".
+[ERROR:PA0203] t_gen_missing.v:9 Unknown macro "error".
 
 [INFO :PA0201] Parsing source file "t_gen_self_return.v".
 
@@ -5082,7 +5082,7 @@
 
 [SYNTX:PA0207] t_preproc.v:100 Syntax error: token recognition error at: '"twoline: \"first \n',
 $display("twoline: \"first 
-         ^-- ../../../build/tests/Verilator/slpp_unit/work/t_preproc.v:125 col:9.
+         ^-- ../../../build/tests/Verilator/slpp_unit/work/t_preproc.v:126 col:9.
 
 [INFO :PA0201] Parsing source file "t_preproc_def09.v".
 
@@ -5124,17 +5124,17 @@
 
 [INFO :PA0201] Parsing source file "t_preproc_persist_inc.v".
 
-[SYNTX:PA0207] t_preproc_persist_inc.v:6 Syntax error: no viable alternative at input 'Inside "t_preproc_persist_inc.v"',
+[SYNTX:PA0207] t_preproc_persist_inc.v:7 Syntax error: no viable alternative at input 'Inside "t_preproc_persist_inc.v"',
  Inside "t_preproc_persist_inc.v".
-        ^-- ../../../build/tests/Verilator/slpp_unit/work/t_preproc_persist_inc.v:6 col:8.
+        ^-- ../../../build/tests/Verilator/slpp_unit/work/t_preproc_persist_inc.v:7 col:8.
 
 [INFO :PA0201] Parsing source file "t_preproc_ttempty.v".
 
 [INFO :PA0201] Parsing source file "t_preproc_undefineall.v".
 
 [SYNTX:PA0207] t_preproc_undefineall.v:8 Syntax error: extraneous input '"Test setup error, PREDEF_COMMAND_LINE pre-missing"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
-SURELOG_MACRO_NOT_DEFINED:error!!!  "Test setup error, PREDEF_COMMAND_LINE pre-missing" 
-                                    ^-- ../../../build/tests/Verilator/slpp_unit/work/t_preproc_undefineall.v:8 col:36.
+ SURELOG_MACRO_NOT_DEFINED:error!!!  "Test setup error, PREDEF_COMMAND_LINE pre-missing" 
+                                     ^-- ../../../build/tests/Verilator/slpp_unit/work/t_preproc_undefineall.v:8 col:37.
 
 [ERROR:PA0203] t_preproc_undefineall.v:8 Unknown macro "error".
 
@@ -5328,11 +5328,11 @@
 
 [INFO :PA0201] Parsing source file "t_tri_gate.v".
 
-[SYNTX:PA0207] t_tri_gate.v:21 Syntax error: extraneous input '"Unknown test name"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
+[SYNTX:PA0207] t_tri_gate.v:22 Syntax error: extraneous input '"Unknown test name"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', 'context', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
  SURELOG_MACRO_NOT_DEFINED:error!!!  "Unknown test name"
-                                     ^-- ../../../build/tests/Verilator/slpp_unit/work/t_tri_gate.v:21 col:37.
+                                     ^-- ../../../build/tests/Verilator/slpp_unit/work/t_tri_gate.v:22 col:37.
 
-[ERROR:PA0203] t_tri_gate.v:21 Unknown macro "error".
+[ERROR:PA0203] t_tri_gate.v:22 Unknown macro "error".
 
 [INFO :PA0201] Parsing source file "t_tri_gen.v".
 
@@ -7216,9 +7216,9 @@
 
 [INFO :PA0201] Parsing source file "t_sv_cpu_code/ports.sv".
 
-[SYNTX:PA0207] t_sv_cpu_code/ports.sv:39 Syntax error: extraneous input 'SURELOG_MACRO_NOT_DEFINED:PACKED!!!' expecting {'{', 'packed'},
+[SYNTX:PA0207] t_sv_cpu_code/ports.sv:41 Syntax error: extraneous input 'SURELOG_MACRO_NOT_DEFINED:PACKED!!!' expecting {'{', 'packed'},
   struct SURELOG_MACRO_NOT_DEFINED:PACKED!!! 
-         ^-- ../../../build/tests/Verilator/slpp_unit/work/t_sv_cpu_code/ports.sv:39 col:9.
+         ^-- ../../../build/tests/Verilator/slpp_unit/work/t_sv_cpu_code/ports.sv:41 col:9.
 
 [INFO :PA0201] Parsing source file "t_sv_cpu_code/ac_dig.sv".
 
@@ -7254,7 +7254,7 @@
 
 [WARNI:PA0205] t_array_query.v:29 No timescale set for "array_test".
 
-[WARNI:PA0205] t_array_rev.v:42 No timescale set for "arr_rev".
+[WARNI:PA0205] t_array_rev.v:44 No timescale set for "arr_rev".
 
 [WARNI:PA0205] t_bench_mux4k.v:89 No timescale set for "mux4096".
 
@@ -7290,7 +7290,7 @@
 
 [WARNI:PA0205] t_case_itemwidth.v:91 No timescale set for "test".
 
-[WARNI:PA0205] t_case_reducer.v:120 No timescale set for "clz".
+[WARNI:PA0205] t_case_reducer.v:121 No timescale set for "clz".
 
 [WARNI:PA0205] verilated.v:2 No timescale set for "t_case_write1_tasks".
 
@@ -7314,7 +7314,7 @@
 
 [WARNI:PA0205] t_clk_concat.v:30 No timescale set for "t1".
 
-[WARNI:PA0205] t_clk_concat.v:43 No timescale set for "t2".
+[WARNI:PA0205] t_clk_concat.v:45 No timescale set for "t2".
 
 [WARNI:PA0205] t_clk_concat6.v:49 No timescale set for "ident".
 
@@ -7332,29 +7332,29 @@
 
 [WARNI:PA0205] t_clk_first.v:30 No timescale set for "t_clk".
 
-[WARNI:PA0205] t_clk_first.v:133 No timescale set for "t_clk_flop".
+[WARNI:PA0205] t_clk_first.v:138 No timescale set for "t_clk_flop".
 
-[WARNI:PA0205] t_clk_first.v:151 No timescale set for "t_clk_two".
+[WARNI:PA0205] t_clk_first.v:156 No timescale set for "t_clk_two".
 
-[WARNI:PA0205] t_clk_first.v:175 No timescale set for "t_clk_twob".
+[WARNI:PA0205] t_clk_first.v:180 No timescale set for "t_clk_twob".
 
 [WARNI:PA0205] t_clk_inp_init.v:13 No timescale set for "dut".
 
-[WARNI:PA0205] t_clk_latchgate.v:97 No timescale set for "llq".
+[WARNI:PA0205] t_clk_latchgate.v:98 No timescale set for "llq".
 
-[WARNI:PA0205] t_clk_latchgate.v:116 No timescale set for "ffq".
+[WARNI:PA0205] t_clk_latchgate.v:117 No timescale set for "ffq".
 
 [WARNI:PA0205] t_clk_scope_bad.v:26 No timescale set for "flop".
 
 [WARNI:PA0205] t_const_dec_mixed_bad.v:6 No timescale set for "MODULE NAME UNKNOWN".
 
-[WARNI:PA0205] t_cover_line.v:67 No timescale set for "alpha".
+[WARNI:PA0205] t_cover_line.v:69 No timescale set for "alpha".
 
-[WARNI:PA0205] t_cover_line.v:87 No timescale set for "beta".
+[WARNI:PA0205] t_cover_line.v:89 No timescale set for "beta".
 
-[WARNI:PA0205] t_cover_line.v:114 No timescale set for "tsk".
+[WARNI:PA0205] t_cover_line.v:116 No timescale set for "tsk".
 
-[WARNI:PA0205] t_cover_line.v:142 No timescale set for "off".
+[WARNI:PA0205] t_cover_line.v:144 No timescale set for "off".
 
 [WARNI:PA0205] t_crazy_sel.v:7 No timescale set for "foo_intf".
 
@@ -7394,7 +7394,7 @@
 
 [WARNI:PA0205] t_dedupe_seq_logic.v:116 No timescale set for "add2".
 
-[WARNI:PA0205] t_display.v:156 No timescale set for "sub2".
+[WARNI:PA0205] t_display.v:158 No timescale set for "sub2".
 
 [WARNI:PA0205] t_dpi_accessors.v:50 No timescale set for "test_sub".
 
@@ -7472,25 +7472,25 @@
 
 [WARNI:PA0205] t_func_paramed.v:53 No timescale set for "extractor".
 
-[WARNI:PA0205] t_func_public.v:33 No timescale set for "tpub".
+[WARNI:PA0205] t_func_public.v:34 No timescale set for "tpub".
 
 [WARNI:PA0205] t_func_regfirst.v:49 No timescale set for "f6".
 
-[WARNI:PA0205] t_func_v.v:13 No timescale set for "level1".
+[WARNI:PA0205] t_func_v.v:14 No timescale set for "level1".
 
-[WARNI:PA0205] t_func_v.v:23 No timescale set for "level2".
+[WARNI:PA0205] t_func_v.v:25 No timescale set for "level2".
 
 [WARNI:PA0205] t_func_wide.v:30 No timescale set for "muxtop".
 
-[WARNI:PA0205] t_gate_elim.v:66 No timescale set for "ta".
+[WARNI:PA0205] t_gate_elim.v:67 No timescale set for "ta".
 
-[WARNI:PA0205] t_gate_elim.v:76 No timescale set for "tb".
+[WARNI:PA0205] t_gate_elim.v:77 No timescale set for "tb".
 
-[WARNI:PA0205] t_gate_elim.v:86 No timescale set for "tc".
+[WARNI:PA0205] t_gate_elim.v:87 No timescale set for "tc".
 
-[WARNI:PA0205] t_gate_elim.v:96 No timescale set for "td".
+[WARNI:PA0205] t_gate_elim.v:97 No timescale set for "td".
 
-[WARNI:PA0205] t_gate_elim.v:106 No timescale set for "te".
+[WARNI:PA0205] t_gate_elim.v:107 No timescale set for "te".
 
 [WARNI:PA0205] t_gate_fdup.v:6 No timescale set for "fnor2".
 
@@ -7506,11 +7506,11 @@
 
 [WARNI:PA0205] t_gen_for.v:74 No timescale set for "paramed".
 
-[WARNI:PA0205] t_gen_for.v:129 No timescale set for "mbuf".
+[WARNI:PA0205] t_gen_for.v:133 No timescale set for "mbuf".
 
-[WARNI:PA0205] t_gen_for.v:136 No timescale set for "enflop".
+[WARNI:PA0205] t_gen_for.v:140 No timescale set for "enflop".
 
-[WARNI:PA0205] t_gen_for.v:162 No timescale set for "enflop_one".
+[WARNI:PA0205] t_gen_for.v:166 No timescale set for "enflop_one".
 
 [WARNI:PA0205] t_gen_for0.v:34 No timescale set for "Testit".
 
@@ -7518,21 +7518,21 @@
 
 [WARNI:PA0205] t_gen_for_overlap.v:35 No timescale set for "sub1".
 
-[WARNI:PA0205] t_gen_forif.v:67 No timescale set for "Test_wrap1".
+[WARNI:PA0205] t_gen_forif.v:68 No timescale set for "Test_wrap1".
 
-[WARNI:PA0205] t_gen_forif.v:75 No timescale set for "Test_wrap2".
+[WARNI:PA0205] t_gen_forif.v:76 No timescale set for "Test_wrap2".
 
-[WARNI:PA0205] t_gen_intdot.v:45 No timescale set for "Generate".
+[WARNI:PA0205] t_gen_intdot.v:46 No timescale set for "Generate".
 
-[WARNI:PA0205] t_gen_intdot.v:58 No timescale set for "Checker".
+[WARNI:PA0205] t_gen_intdot.v:59 No timescale set for "Checker".
 
-[WARNI:PA0205] t_gen_intdot.v:77 No timescale set for "Genit".
+[WARNI:PA0205] t_gen_intdot.v:78 No timescale set for "Genit".
 
-[WARNI:PA0205] t_gen_intdot2.v:38 No timescale set for "One".
+[WARNI:PA0205] t_gen_intdot2.v:39 No timescale set for "One".
 
-[WARNI:PA0205] t_gen_missing.v:12 No timescale set for "foobar".
+[WARNI:PA0205] t_gen_missing.v:14 No timescale set for "foobar".
 
-[WARNI:PA0205] t_gen_missing.v:45 No timescale set for "foo0".
+[WARNI:PA0205] t_gen_missing.v:47 No timescale set for "foo0".
 
 [WARNI:PA0205] t_gen_upscope.v:78 No timescale set for "tag".
 
@@ -7552,11 +7552,11 @@
 
 [WARNI:PA0205] t_inst_dff.v:109 No timescale set for "dff".
 
-[WARNI:PA0205] t_inst_dtree.v:19 No timescale set for "bmod".
+[WARNI:PA0205] t_inst_dtree.v:21 No timescale set for "bmod".
 
-[WARNI:PA0205] t_inst_dtree.v:28 No timescale set for "cmod".
+[WARNI:PA0205] t_inst_dtree.v:32 No timescale set for "cmod".
 
-[WARNI:PA0205] t_inst_dtree.v:38 No timescale set for "dmod".
+[WARNI:PA0205] t_inst_dtree.v:44 No timescale set for "dmod".
 
 [WARNI:PA0205] t_inst_first_a.v:6 No timescale set for "t_inst_first_a".
 
@@ -7578,7 +7578,7 @@
 
 [WARNI:PA0205] t_inst_recurse_bad.v:21 No timescale set for "looped2".
 
-[WARNI:PA0205] t_inst_sv.v:61 No timescale set for "t_inst".
+[WARNI:PA0205] t_inst_sv.v:62 No timescale set for "t_inst".
 
 [WARNI:PA0205] t_inst_tree.v:63 No timescale set for "ps".
 
@@ -7590,7 +7590,7 @@
 
 [WARNI:PA0205] t_inst_tree.v:100 No timescale set for "l5".
 
-[WARNI:PA0205] t_inst_v2k.v:62 No timescale set for "hello".
+[WARNI:PA0205] t_inst_v2k.v:63 No timescale set for "hello".
 
 [WARNI:PA0205] t_inst_wideconst.v:59 No timescale set for "wide".
 
@@ -7602,15 +7602,15 @@
 
 [WARNI:PA0205] t_interface1.v:8 No timescale set for "ifc".
 
-[WARNI:PA0205] t_interface2.v:64 No timescale set for "counter_io".
+[WARNI:PA0205] t_interface2.v:65 No timescale set for "counter_io".
 
-[WARNI:PA0205] t_interface2.v:72 No timescale set for "ifunused".
+[WARNI:PA0205] t_interface2.v:73 No timescale set for "ifunused".
 
-[WARNI:PA0205] t_interface2.v:76 No timescale set for "counter_ansi".
+[WARNI:PA0205] t_interface2.v:77 No timescale set for "counter_ansi".
 
-[WARNI:PA0205] t_interface2.v:93 No timescale set for "counter_nansi".
+[WARNI:PA0205] t_interface2.v:95 No timescale set for "counter_nansi".
 
-[WARNI:PA0205] t_interface2.v:104 No timescale set for "modunused".
+[WARNI:PA0205] t_interface2.v:106 No timescale set for "modunused".
 
 [WARNI:PA0205] t_interface_array_bad.v:45 No timescale set for "baz".
 
@@ -7628,9 +7628,9 @@
 
 [WARNI:PA0205] t_interface_bind_public.v:100 No timescale set for "SimpleTestHarness".
 
-[WARNI:PA0205] t_interface_down.v:44 No timescale set for "wrapper".
+[WARNI:PA0205] t_interface_down.v:46 No timescale set for "wrapper".
 
-[WARNI:PA0205] t_interface_down.v:55 No timescale set for "lower".
+[WARNI:PA0205] t_interface_down.v:59 No timescale set for "lower".
 
 [WARNI:PA0205] t_interface_dups.v:88 No timescale set for "dti".
 
@@ -7640,9 +7640,9 @@
 
 [WARNI:PA0205] t_interface_modport.v:6 No timescale set for "counter_if".
 
-[WARNI:PA0205] t_interface_modport.v:103 No timescale set for "counter_ansi_m".
+[WARNI:PA0205] t_interface_modport.v:106 No timescale set for "counter_ansi_m".
 
-[WARNI:PA0205] t_interface_modport.v:116 No timescale set for "counter_nansi_m".
+[WARNI:PA0205] t_interface_modport.v:120 No timescale set for "counter_nansi_m".
 
 [WARNI:PA0205] t_interface_modport_export.v:8 No timescale set for "test_if".
 
@@ -7706,19 +7706,19 @@
 
 [WARNI:PA0205] t_math_cmp.v:71 No timescale set for "prover".
 
-[WARNI:PA0205] t_math_imm.v:73 No timescale set for "example".
+[WARNI:PA0205] t_math_imm.v:74 No timescale set for "example".
 
 [WARNI:PA0205] t_math_imm2.v:13 No timescale set for "t_math_imm2".
 
-[WARNI:PA0205] t_math_pow4.v:43 No timescale set for "test004".
+[WARNI:PA0205] t_math_pow4.v:44 No timescale set for "test004".
 
-[WARNI:PA0205] t_math_real.v:141 No timescale set for "sub_cast_bug374".
+[WARNI:PA0205] t_math_real.v:142 No timescale set for "sub_cast_bug374".
 
-[WARNI:PA0205] t_math_signed.v:164 No timescale set for "by_width".
+[WARNI:PA0205] t_math_signed.v:165 No timescale set for "by_width".
 
-[WARNI:PA0205] t_math_signed_wire.v:29 No timescale set for "Test1".
+[WARNI:PA0205] t_math_signed_wire.v:30 No timescale set for "Test1".
 
-[WARNI:PA0205] t_math_signed_wire.v:41 No timescale set for "Test2".
+[WARNI:PA0205] t_math_signed_wire.v:42 No timescale set for "Test2".
 
 [WARNI:PA0205] t_math_vliw.v:58 No timescale set for "vliw".
 
@@ -7768,13 +7768,13 @@
 
 [WARNI:PA0205] t_order_first.v:20 No timescale set for "t_netlist".
 
-[WARNI:PA0205] t_order_multidriven.v:61 No timescale set for "FooWr".
+[WARNI:PA0205] t_order_multidriven.v:63 No timescale set for "FooWr".
 
-[WARNI:PA0205] t_order_multidriven.v:86 No timescale set for "FooRd".
+[WARNI:PA0205] t_order_multidriven.v:88 No timescale set for "FooRd".
 
-[WARNI:PA0205] t_order_multidriven.v:125 No timescale set for "FooMem".
+[WARNI:PA0205] t_order_multidriven.v:128 No timescale set for "FooMem".
 
-[WARNI:PA0205] t_order_multidriven.v:151 No timescale set for "FooMemImpl".
+[WARNI:PA0205] t_order_multidriven.v:154 No timescale set for "FooMemImpl".
 
 [WARNI:PA0205] t_package.v:20 No timescale set for "p2".
 
@@ -7786,15 +7786,15 @@
 
 [WARNI:PA0205] t_package_export.v:14 No timescale set for "pkg10".
 
-[WARNI:PA0205] t_package_export.v:19 No timescale set for "pkg11".
+[WARNI:PA0205] t_package_export.v:20 No timescale set for "pkg11".
 
-[WARNI:PA0205] t_package_export.v:23 No timescale set for "pkg20".
+[WARNI:PA0205] t_package_export.v:24 No timescale set for "pkg20".
 
-[WARNI:PA0205] t_package_export.v:27 No timescale set for "pkg21".
+[WARNI:PA0205] t_package_export.v:29 No timescale set for "pkg21".
 
-[WARNI:PA0205] t_package_export.v:31 No timescale set for "pkg30".
+[WARNI:PA0205] t_package_export.v:33 No timescale set for "pkg30".
 
-[WARNI:PA0205] t_package_export.v:35 No timescale set for "pkg31".
+[WARNI:PA0205] t_package_export.v:38 No timescale set for "pkg31".
 
 [WARNI:PA0205] t_package_twodeep.v:8 No timescale set for "pkg2".
 
@@ -7880,25 +7880,25 @@
 
 [WARNI:PA0205] t_sv_conditional.v:62 No timescale set for "st3_testbench".
 
-[WARNI:PA0205] t_sv_conditional.v:145 No timescale set for "simple_test_3".
+[WARNI:PA0205] t_sv_conditional.v:146 No timescale set for "simple_test_3".
 
-[WARNI:PA0205] t_sv_conditional.v:230 No timescale set for "counterA".
+[WARNI:PA0205] t_sv_conditional.v:231 No timescale set for "counterA".
 
-[WARNI:PA0205] t_sv_conditional.v:277 No timescale set for "counterB".
+[WARNI:PA0205] t_sv_conditional.v:278 No timescale set for "counterB".
 
-[WARNI:PA0205] t_sv_conditional.v:311 No timescale set for "simple_test_3a".
+[WARNI:PA0205] t_sv_conditional.v:312 No timescale set for "simple_test_3a".
 
-[WARNI:PA0205] t_sv_conditional.v:331 No timescale set for "simple_test_3b".
+[WARNI:PA0205] t_sv_conditional.v:332 No timescale set for "simple_test_3b".
 
-[WARNI:PA0205] t_sv_conditional.v:363 No timescale set for "simple_test_3c".
+[WARNI:PA0205] t_sv_conditional.v:364 No timescale set for "simple_test_3c".
 
-[WARNI:PA0205] t_sv_conditional.v:395 No timescale set for "simple_test_3d".
+[WARNI:PA0205] t_sv_conditional.v:396 No timescale set for "simple_test_3d".
 
-[WARNI:PA0205] t_sv_conditional.v:425 No timescale set for "simple_test_3e".
+[WARNI:PA0205] t_sv_conditional.v:426 No timescale set for "simple_test_3e".
 
-[WARNI:PA0205] t_sv_conditional.v:449 No timescale set for "simple_test_3f".
+[WARNI:PA0205] t_sv_conditional.v:450 No timescale set for "simple_test_3f".
 
-[WARNI:PA0205] t_sv_cpu.v:79 No timescale set for "testbench".
+[WARNI:PA0205] t_sv_cpu.v:81 No timescale set for "testbench".
 
 [WARNI:PA0205] t_trace_param.v:6 No timescale set for "my_funcs".
 
@@ -7908,9 +7908,9 @@
 
 [WARNI:PA0205] t_trace_public.v:32 No timescale set for "glbl".
 
-[WARNI:PA0205] t_trace_public.v:36 No timescale set for "neg".
+[WARNI:PA0205] t_trace_public.v:38 No timescale set for "neg".
 
-[WARNI:PA0205] t_trace_public.v:51 No timescale set for "little".
+[WARNI:PA0205] t_trace_public.v:53 No timescale set for "little".
 
 [WARNI:PA0205] t_tri_array.v:65 No timescale set for "Pad".
 
@@ -7920,7 +7920,7 @@
 
 [WARNI:PA0205] t_tri_gate.v:20 No timescale set for "tbuf".
 
-[WARNI:PA0205] t_tri_gate.v:24 No timescale set for "mux".
+[WARNI:PA0205] t_tri_gate.v:26 No timescale set for "mux".
 
 [WARNI:PA0205] t_tri_gen.v:27 No timescale set for "updown".
 
@@ -7948,17 +7948,17 @@
 
 [WARNI:PA0205] t_tri_unconn.v:90 No timescale set for "t_tri1".
 
-[WARNI:PA0205] t_tri_various.v:146 No timescale set for "Test3".
+[WARNI:PA0205] t_tri_various.v:155 No timescale set for "Test3".
 
-[WARNI:PA0205] t_tri_various.v:154 No timescale set for "Test4".
+[WARNI:PA0205] t_tri_various.v:165 No timescale set for "Test4".
 
-[WARNI:PA0205] t_tri_various.v:159 No timescale set for "Test5".
+[WARNI:PA0205] t_tri_various.v:170 No timescale set for "Test5".
 
-[WARNI:PA0205] t_tri_various.v:167 No timescale set for "Test6".
+[WARNI:PA0205] t_tri_various.v:178 No timescale set for "Test6".
 
-[WARNI:PA0205] t_tri_various.v:173 No timescale set for "Test6a".
+[WARNI:PA0205] t_tri_various.v:184 No timescale set for "Test6a".
 
-[WARNI:PA0205] t_tri_various.v:177 No timescale set for "Test7".
+[WARNI:PA0205] t_tri_various.v:188 No timescale set for "Test7".
 
 [WARNI:PA0205] t_type_param.v:15 No timescale set for "foo_wrapper".
 
@@ -7972,25 +7972,25 @@
 
 [WARNI:PA0205] t_udp_noname.v:35 No timescale set for "udp".
 
-[WARNI:PA0205] t_unoptflat_simple_3.v:41 No timescale set for "test1".
+[WARNI:PA0205] t_unoptflat_simple_3.v:42 No timescale set for "test1".
 
-[WARNI:PA0205] t_unoptflat_simple_3.v:60 No timescale set for "test2".
+[WARNI:PA0205] t_unoptflat_simple_3.v:61 No timescale set for "test2".
 
-[WARNI:PA0205] t_vams_wreal.v:87 No timescale set for "through".
+[WARNI:PA0205] t_vams_wreal.v:89 No timescale set for "through".
 
-[WARNI:PA0205] t_vams_wreal.v:93 No timescale set for "within_range".
+[WARNI:PA0205] t_vams_wreal.v:95 No timescale set for "within_range".
 
-[WARNI:PA0205] t_vams_wreal.v:106 No timescale set for "wreal_bus".
+[WARNI:PA0205] t_vams_wreal.v:108 No timescale set for "wreal_bus".
 
-[WARNI:PA0205] t_vams_wreal.v:114 No timescale set for "first_level".
+[WARNI:PA0205] t_vams_wreal.v:116 No timescale set for "first_level".
 
-[WARNI:PA0205] t_vams_wreal.v:121 No timescale set for "second_level".
+[WARNI:PA0205] t_vams_wreal.v:125 No timescale set for "second_level".
 
 [WARNI:PA0205] t_var_dup_bad.v:46 No timescale set for "sub0".
 
 [WARNI:PA0205] t_var_dup_bad.v:68 No timescale set for "sub3".
 
-[WARNI:PA0205] t_var_in_assign.v:59 No timescale set for "z".
+[WARNI:PA0205] t_var_in_assign.v:60 No timescale set for "z".
 
 [WARNI:PA0205] t_var_notfound_bad.v:32 No timescale set for "subsub".
 
@@ -7998,7 +7998,7 @@
 
 [WARNI:PA0205] t_var_port_bad.v:11 No timescale set for "subok".
 
-[WARNI:PA0205] t_vpi_var.v:87 No timescale set for "arr".
+[WARNI:PA0205] t_vpi_var.v:95 No timescale set for "arr".
 
 [WARNI:PA0205] t_xml_first.v:44 No timescale set for "mod2".
 
@@ -8016,7 +8016,7 @@
 
 [WARNI:PA0205] t_sv_cpu_code/pad_vdd.sv:12 No timescale set for "pad_vdd".
 
-[WARNI:PA0205] t_sv_cpu_code/ports.sv:9 No timescale set for "ports".
+[WARNI:PA0205] t_sv_cpu_code/ports.sv:11 No timescale set for "ports".
 
 [WARNI:PA0205] t_sv_cpu_code/ac_dig.sv:8 No timescale set for "ac_dig".
 
@@ -8074,27 +8074,27 @@
 
 [ERROR:PA0206] t_altera_lpm.v:4383 Missing timeunit/timeprecision for "lpm_ram_dq".
 
-[ERROR:PA0206] t_altera_lpm.v:4639 Missing timeunit/timeprecision for "lpm_ram_dp".
+[ERROR:PA0206] t_altera_lpm.v:4641 Missing timeunit/timeprecision for "lpm_ram_dp".
 
-[ERROR:PA0206] t_altera_lpm.v:4930 Missing timeunit/timeprecision for "lpm_ram_io".
+[ERROR:PA0206] t_altera_lpm.v:4934 Missing timeunit/timeprecision for "lpm_ram_io".
 
-[ERROR:PA0206] t_altera_lpm.v:5192 Missing timeunit/timeprecision for "lpm_rom".
+[ERROR:PA0206] t_altera_lpm.v:5198 Missing timeunit/timeprecision for "lpm_rom".
 
-[ERROR:PA0206] t_altera_lpm.v:5407 Missing timeunit/timeprecision for "lpm_fifo".
+[ERROR:PA0206] t_altera_lpm.v:5415 Missing timeunit/timeprecision for "lpm_fifo".
 
-[ERROR:PA0206] t_altera_lpm.v:5738 Missing timeunit/timeprecision for "lpm_fifo_dc_dffpipe".
+[ERROR:PA0206] t_altera_lpm.v:5746 Missing timeunit/timeprecision for "lpm_fifo_dc_dffpipe".
 
-[ERROR:PA0206] t_altera_lpm.v:5825 Missing timeunit/timeprecision for "lpm_fifo_dc_fefifo".
+[ERROR:PA0206] t_altera_lpm.v:5837 Missing timeunit/timeprecision for "lpm_fifo_dc_fefifo".
 
-[ERROR:PA0206] t_altera_lpm.v:6033 Missing timeunit/timeprecision for "lpm_fifo_dc_async".
+[ERROR:PA0206] t_altera_lpm.v:6045 Missing timeunit/timeprecision for "lpm_fifo_dc_async".
 
-[ERROR:PA0206] t_altera_lpm.v:6470 Missing timeunit/timeprecision for "lpm_fifo_dc".
+[ERROR:PA0206] t_altera_lpm.v:6482 Missing timeunit/timeprecision for "lpm_fifo_dc".
 
-[ERROR:PA0206] t_altera_lpm.v:6593 Missing timeunit/timeprecision for "lpm_inpad".
+[ERROR:PA0206] t_altera_lpm.v:6605 Missing timeunit/timeprecision for "lpm_inpad".
 
-[ERROR:PA0206] t_altera_lpm.v:6649 Missing timeunit/timeprecision for "lpm_outpad".
+[ERROR:PA0206] t_altera_lpm.v:6661 Missing timeunit/timeprecision for "lpm_outpad".
 
-[ERROR:PA0206] t_altera_lpm.v:6705 Missing timeunit/timeprecision for "lpm_bipad".
+[ERROR:PA0206] t_altera_lpm.v:6717 Missing timeunit/timeprecision for "lpm_bipad".
 
 [ERROR:PA0206] t_array_interface.v:6 Missing timeunit/timeprecision for "intf".
 
@@ -8104,7 +8104,7 @@
 
 [ERROR:PA0206] t_array_query.v:29 Missing timeunit/timeprecision for "array_test".
 
-[ERROR:PA0206] t_array_rev.v:42 Missing timeunit/timeprecision for "arr_rev".
+[ERROR:PA0206] t_array_rev.v:44 Missing timeunit/timeprecision for "arr_rev".
 
 [ERROR:PA0206] t_bench_mux4k.v:89 Missing timeunit/timeprecision for "mux4096".
 
@@ -8140,7 +8140,7 @@
 
 [ERROR:PA0206] t_case_itemwidth.v:91 Missing timeunit/timeprecision for "test".
 
-[ERROR:PA0206] t_case_reducer.v:120 Missing timeunit/timeprecision for "clz".
+[ERROR:PA0206] t_case_reducer.v:121 Missing timeunit/timeprecision for "clz".
 
 [ERROR:PA0206] verilated.v:2 Missing timeunit/timeprecision for "t_case_write1_tasks".
 
@@ -8164,7 +8164,7 @@
 
 [ERROR:PA0206] t_clk_concat.v:30 Missing timeunit/timeprecision for "t1".
 
-[ERROR:PA0206] t_clk_concat.v:43 Missing timeunit/timeprecision for "t2".
+[ERROR:PA0206] t_clk_concat.v:45 Missing timeunit/timeprecision for "t2".
 
 [ERROR:PA0206] t_clk_concat6.v:49 Missing timeunit/timeprecision for "ident".
 
@@ -8182,29 +8182,29 @@
 
 [ERROR:PA0206] t_clk_first.v:30 Missing timeunit/timeprecision for "t_clk".
 
-[ERROR:PA0206] t_clk_first.v:133 Missing timeunit/timeprecision for "t_clk_flop".
+[ERROR:PA0206] t_clk_first.v:138 Missing timeunit/timeprecision for "t_clk_flop".
 
-[ERROR:PA0206] t_clk_first.v:151 Missing timeunit/timeprecision for "t_clk_two".
+[ERROR:PA0206] t_clk_first.v:156 Missing timeunit/timeprecision for "t_clk_two".
 
-[ERROR:PA0206] t_clk_first.v:175 Missing timeunit/timeprecision for "t_clk_twob".
+[ERROR:PA0206] t_clk_first.v:180 Missing timeunit/timeprecision for "t_clk_twob".
 
 [ERROR:PA0206] t_clk_inp_init.v:13 Missing timeunit/timeprecision for "dut".
 
-[ERROR:PA0206] t_clk_latchgate.v:97 Missing timeunit/timeprecision for "llq".
+[ERROR:PA0206] t_clk_latchgate.v:98 Missing timeunit/timeprecision for "llq".
 
-[ERROR:PA0206] t_clk_latchgate.v:116 Missing timeunit/timeprecision for "ffq".
+[ERROR:PA0206] t_clk_latchgate.v:117 Missing timeunit/timeprecision for "ffq".
 
 [ERROR:PA0206] t_clk_scope_bad.v:26 Missing timeunit/timeprecision for "flop".
 
 [ERROR:PA0206] t_const_dec_mixed_bad.v:6 Missing timeunit/timeprecision for "MODULE NAME UNKNOWN".
 
-[ERROR:PA0206] t_cover_line.v:67 Missing timeunit/timeprecision for "alpha".
+[ERROR:PA0206] t_cover_line.v:69 Missing timeunit/timeprecision for "alpha".
 
-[ERROR:PA0206] t_cover_line.v:87 Missing timeunit/timeprecision for "beta".
+[ERROR:PA0206] t_cover_line.v:89 Missing timeunit/timeprecision for "beta".
 
-[ERROR:PA0206] t_cover_line.v:114 Missing timeunit/timeprecision for "tsk".
+[ERROR:PA0206] t_cover_line.v:116 Missing timeunit/timeprecision for "tsk".
 
-[ERROR:PA0206] t_cover_line.v:142 Missing timeunit/timeprecision for "off".
+[ERROR:PA0206] t_cover_line.v:144 Missing timeunit/timeprecision for "off".
 
 [ERROR:PA0206] t_crazy_sel.v:7 Missing timeunit/timeprecision for "foo_intf".
 
@@ -8244,7 +8244,7 @@
 
 [ERROR:PA0206] t_dedupe_seq_logic.v:116 Missing timeunit/timeprecision for "add2".
 
-[ERROR:PA0206] t_display.v:156 Missing timeunit/timeprecision for "sub2".
+[ERROR:PA0206] t_display.v:158 Missing timeunit/timeprecision for "sub2".
 
 [ERROR:PA0206] t_dpi_accessors.v:50 Missing timeunit/timeprecision for "test_sub".
 
@@ -8322,31 +8322,31 @@
 
 [ERROR:PA0206] t_func_paramed.v:53 Missing timeunit/timeprecision for "extractor".
 
-[ERROR:PA0206] t_func_public.v:33 Missing timeunit/timeprecision for "tpub".
+[ERROR:PA0206] t_func_public.v:34 Missing timeunit/timeprecision for "tpub".
 
 [ERROR:PA0206] t_func_regfirst.v:49 Missing timeunit/timeprecision for "f6".
 
-[ERROR:PA0206] t_func_v.v:13 Missing timeunit/timeprecision for "level1".
+[ERROR:PA0206] t_func_v.v:14 Missing timeunit/timeprecision for "level1".
 
-[ERROR:PA0206] t_func_v.v:23 Missing timeunit/timeprecision for "level2".
+[ERROR:PA0206] t_func_v.v:25 Missing timeunit/timeprecision for "level2".
 
 [ERROR:PA0206] t_func_wide.v:30 Missing timeunit/timeprecision for "muxtop".
 
-[ERROR:PA0206] t_gate_elim.v:66 Missing timeunit/timeprecision for "ta".
+[ERROR:PA0206] t_gate_elim.v:67 Missing timeunit/timeprecision for "ta".
 
-[ERROR:PA0206] t_gate_elim.v:76 Missing timeunit/timeprecision for "tb".
+[ERROR:PA0206] t_gate_elim.v:77 Missing timeunit/timeprecision for "tb".
 
-[ERROR:PA0206] t_gate_elim.v:86 Missing timeunit/timeprecision for "tc".
+[ERROR:PA0206] t_gate_elim.v:87 Missing timeunit/timeprecision for "tc".
 
-[ERROR:PA0206] t_gate_elim.v:96 Missing timeunit/timeprecision for "td".
+[ERROR:PA0206] t_gate_elim.v:97 Missing timeunit/timeprecision for "td".
 
-[ERROR:PA0206] t_gate_elim.v:106 Missing timeunit/timeprecision for "te".
+[ERROR:PA0206] t_gate_elim.v:107 Missing timeunit/timeprecision for "te".
 
 [ERROR:PA0206] t_gate_fdup.v:6 Missing timeunit/timeprecision for "fnor2".
 
 [ERROR:PA0206] t_gate_implicit.v:78 Missing timeunit/timeprecision for "Mxor".
 
-[ERROR:PA0206] t_gen_assign.v:46 Missing timeunit/timeprecision for "assigns".
+[ERROR:PA0206] t_gen_assign.v:47 Missing timeunit/timeprecision for "assigns".
 
 [ERROR:PA0206] t_gen_cond_bitrange.v:46 Missing timeunit/timeprecision for "test_gen".
 
@@ -8358,11 +8358,11 @@
 
 [ERROR:PA0206] t_gen_for.v:74 Missing timeunit/timeprecision for "paramed".
 
-[ERROR:PA0206] t_gen_for.v:129 Missing timeunit/timeprecision for "mbuf".
+[ERROR:PA0206] t_gen_for.v:133 Missing timeunit/timeprecision for "mbuf".
 
-[ERROR:PA0206] t_gen_for.v:136 Missing timeunit/timeprecision for "enflop".
+[ERROR:PA0206] t_gen_for.v:140 Missing timeunit/timeprecision for "enflop".
 
-[ERROR:PA0206] t_gen_for.v:162 Missing timeunit/timeprecision for "enflop_one".
+[ERROR:PA0206] t_gen_for.v:166 Missing timeunit/timeprecision for "enflop_one".
 
 [ERROR:PA0206] t_gen_for0.v:34 Missing timeunit/timeprecision for "Testit".
 
@@ -8370,21 +8370,21 @@
 
 [ERROR:PA0206] t_gen_for_overlap.v:35 Missing timeunit/timeprecision for "sub1".
 
-[ERROR:PA0206] t_gen_forif.v:67 Missing timeunit/timeprecision for "Test_wrap1".
+[ERROR:PA0206] t_gen_forif.v:68 Missing timeunit/timeprecision for "Test_wrap1".
 
-[ERROR:PA0206] t_gen_forif.v:75 Missing timeunit/timeprecision for "Test_wrap2".
+[ERROR:PA0206] t_gen_forif.v:76 Missing timeunit/timeprecision for "Test_wrap2".
 
-[ERROR:PA0206] t_gen_intdot.v:45 Missing timeunit/timeprecision for "Generate".
+[ERROR:PA0206] t_gen_intdot.v:46 Missing timeunit/timeprecision for "Generate".
 
-[ERROR:PA0206] t_gen_intdot.v:58 Missing timeunit/timeprecision for "Checker".
+[ERROR:PA0206] t_gen_intdot.v:59 Missing timeunit/timeprecision for "Checker".
 
-[ERROR:PA0206] t_gen_intdot.v:77 Missing timeunit/timeprecision for "Genit".
+[ERROR:PA0206] t_gen_intdot.v:78 Missing timeunit/timeprecision for "Genit".
 
-[ERROR:PA0206] t_gen_intdot2.v:38 Missing timeunit/timeprecision for "One".
+[ERROR:PA0206] t_gen_intdot2.v:39 Missing timeunit/timeprecision for "One".
 
-[ERROR:PA0206] t_gen_missing.v:12 Missing timeunit/timeprecision for "foobar".
+[ERROR:PA0206] t_gen_missing.v:14 Missing timeunit/timeprecision for "foobar".
 
-[ERROR:PA0206] t_gen_missing.v:45 Missing timeunit/timeprecision for "foo0".
+[ERROR:PA0206] t_gen_missing.v:47 Missing timeunit/timeprecision for "foo0".
 
 [ERROR:PA0206] t_gen_upscope.v:78 Missing timeunit/timeprecision for "tag".
 
@@ -8394,9 +8394,9 @@
 
 [ERROR:PA0206] t_init_concat.v:59 Missing timeunit/timeprecision for "regfile".
 
-[ERROR:PA0206] t_initial_edge.v:69 Missing timeunit/timeprecision for "initial_edge_n".
+[ERROR:PA0206] t_initial_edge.v:70 Missing timeunit/timeprecision for "initial_edge_n".
 
-[ERROR:PA0206] t_initial_edge.v:85 Missing timeunit/timeprecision for "initial_edge".
+[ERROR:PA0206] t_initial_edge.v:86 Missing timeunit/timeprecision for "initial_edge".
 
 [ERROR:PA0206] t_inst_aport.v:65 Missing timeunit/timeprecision for "callee".
 
@@ -8408,11 +8408,11 @@
 
 [ERROR:PA0206] t_inst_dff.v:109 Missing timeunit/timeprecision for "dff".
 
-[ERROR:PA0206] t_inst_dtree.v:19 Missing timeunit/timeprecision for "bmod".
+[ERROR:PA0206] t_inst_dtree.v:21 Missing timeunit/timeprecision for "bmod".
 
-[ERROR:PA0206] t_inst_dtree.v:28 Missing timeunit/timeprecision for "cmod".
+[ERROR:PA0206] t_inst_dtree.v:32 Missing timeunit/timeprecision for "cmod".
 
-[ERROR:PA0206] t_inst_dtree.v:38 Missing timeunit/timeprecision for "dmod".
+[ERROR:PA0206] t_inst_dtree.v:44 Missing timeunit/timeprecision for "dmod".
 
 [ERROR:PA0206] t_inst_first_a.v:6 Missing timeunit/timeprecision for "t_inst_first_a".
 
@@ -8434,7 +8434,7 @@
 
 [ERROR:PA0206] t_inst_recurse_bad.v:21 Missing timeunit/timeprecision for "looped2".
 
-[ERROR:PA0206] t_inst_sv.v:61 Missing timeunit/timeprecision for "t_inst".
+[ERROR:PA0206] t_inst_sv.v:62 Missing timeunit/timeprecision for "t_inst".
 
 [ERROR:PA0206] t_inst_tree.v:63 Missing timeunit/timeprecision for "ps".
 
@@ -8446,7 +8446,7 @@
 
 [ERROR:PA0206] t_inst_tree.v:100 Missing timeunit/timeprecision for "l5".
 
-[ERROR:PA0206] t_inst_v2k.v:62 Missing timeunit/timeprecision for "hello".
+[ERROR:PA0206] t_inst_v2k.v:63 Missing timeunit/timeprecision for "hello".
 
 [ERROR:PA0206] t_inst_wideconst.v:59 Missing timeunit/timeprecision for "wide".
 
@@ -8458,15 +8458,15 @@
 
 [ERROR:PA0206] t_interface1.v:8 Missing timeunit/timeprecision for "ifc".
 
-[ERROR:PA0206] t_interface2.v:64 Missing timeunit/timeprecision for "counter_io".
+[ERROR:PA0206] t_interface2.v:65 Missing timeunit/timeprecision for "counter_io".
 
-[ERROR:PA0206] t_interface2.v:72 Missing timeunit/timeprecision for "ifunused".
+[ERROR:PA0206] t_interface2.v:73 Missing timeunit/timeprecision for "ifunused".
 
-[ERROR:PA0206] t_interface2.v:76 Missing timeunit/timeprecision for "counter_ansi".
+[ERROR:PA0206] t_interface2.v:77 Missing timeunit/timeprecision for "counter_ansi".
 
-[ERROR:PA0206] t_interface2.v:93 Missing timeunit/timeprecision for "counter_nansi".
+[ERROR:PA0206] t_interface2.v:95 Missing timeunit/timeprecision for "counter_nansi".
 
-[ERROR:PA0206] t_interface2.v:104 Missing timeunit/timeprecision for "modunused".
+[ERROR:PA0206] t_interface2.v:106 Missing timeunit/timeprecision for "modunused".
 
 [ERROR:PA0206] t_interface_array_bad.v:45 Missing timeunit/timeprecision for "baz".
 
@@ -8484,9 +8484,9 @@
 
 [ERROR:PA0206] t_interface_bind_public.v:100 Missing timeunit/timeprecision for "SimpleTestHarness".
 
-[ERROR:PA0206] t_interface_down.v:44 Missing timeunit/timeprecision for "wrapper".
+[ERROR:PA0206] t_interface_down.v:46 Missing timeunit/timeprecision for "wrapper".
 
-[ERROR:PA0206] t_interface_down.v:55 Missing timeunit/timeprecision for "lower".
+[ERROR:PA0206] t_interface_down.v:59 Missing timeunit/timeprecision for "lower".
 
 [ERROR:PA0206] t_interface_dups.v:88 Missing timeunit/timeprecision for "dti".
 
@@ -8496,9 +8496,9 @@
 
 [ERROR:PA0206] t_interface_modport.v:6 Missing timeunit/timeprecision for "counter_if".
 
-[ERROR:PA0206] t_interface_modport.v:103 Missing timeunit/timeprecision for "counter_ansi_m".
+[ERROR:PA0206] t_interface_modport.v:106 Missing timeunit/timeprecision for "counter_ansi_m".
 
-[ERROR:PA0206] t_interface_modport.v:116 Missing timeunit/timeprecision for "counter_nansi_m".
+[ERROR:PA0206] t_interface_modport.v:120 Missing timeunit/timeprecision for "counter_nansi_m".
 
 [ERROR:PA0206] t_interface_modport_export.v:8 Missing timeunit/timeprecision for "test_if".
 
@@ -8562,19 +8562,19 @@
 
 [ERROR:PA0206] t_math_cmp.v:71 Missing timeunit/timeprecision for "prover".
 
-[ERROR:PA0206] t_math_imm.v:73 Missing timeunit/timeprecision for "example".
+[ERROR:PA0206] t_math_imm.v:74 Missing timeunit/timeprecision for "example".
 
 [ERROR:PA0206] t_math_imm2.v:13 Missing timeunit/timeprecision for "t_math_imm2".
 
-[ERROR:PA0206] t_math_pow4.v:43 Missing timeunit/timeprecision for "test004".
+[ERROR:PA0206] t_math_pow4.v:44 Missing timeunit/timeprecision for "test004".
 
-[ERROR:PA0206] t_math_real.v:141 Missing timeunit/timeprecision for "sub_cast_bug374".
+[ERROR:PA0206] t_math_real.v:142 Missing timeunit/timeprecision for "sub_cast_bug374".
 
-[ERROR:PA0206] t_math_signed.v:164 Missing timeunit/timeprecision for "by_width".
+[ERROR:PA0206] t_math_signed.v:165 Missing timeunit/timeprecision for "by_width".
 
-[ERROR:PA0206] t_math_signed_wire.v:29 Missing timeunit/timeprecision for "Test1".
+[ERROR:PA0206] t_math_signed_wire.v:30 Missing timeunit/timeprecision for "Test1".
 
-[ERROR:PA0206] t_math_signed_wire.v:41 Missing timeunit/timeprecision for "Test2".
+[ERROR:PA0206] t_math_signed_wire.v:42 Missing timeunit/timeprecision for "Test2".
 
 [ERROR:PA0206] t_math_vliw.v:58 Missing timeunit/timeprecision for "vliw".
 
@@ -8624,13 +8624,13 @@
 
 [ERROR:PA0206] t_order_first.v:20 Missing timeunit/timeprecision for "t_netlist".
 
-[ERROR:PA0206] t_order_multidriven.v:61 Missing timeunit/timeprecision for "FooWr".
+[ERROR:PA0206] t_order_multidriven.v:63 Missing timeunit/timeprecision for "FooWr".
 
-[ERROR:PA0206] t_order_multidriven.v:86 Missing timeunit/timeprecision for "FooRd".
+[ERROR:PA0206] t_order_multidriven.v:88 Missing timeunit/timeprecision for "FooRd".
 
-[ERROR:PA0206] t_order_multidriven.v:125 Missing timeunit/timeprecision for "FooMem".
+[ERROR:PA0206] t_order_multidriven.v:128 Missing timeunit/timeprecision for "FooMem".
 
-[ERROR:PA0206] t_order_multidriven.v:151 Missing timeunit/timeprecision for "FooMemImpl".
+[ERROR:PA0206] t_order_multidriven.v:154 Missing timeunit/timeprecision for "FooMemImpl".
 
 [ERROR:PA0206] t_package.v:20 Missing timeunit/timeprecision for "p2".
 
@@ -8642,15 +8642,15 @@
 
 [ERROR:PA0206] t_package_export.v:14 Missing timeunit/timeprecision for "pkg10".
 
-[ERROR:PA0206] t_package_export.v:19 Missing timeunit/timeprecision for "pkg11".
+[ERROR:PA0206] t_package_export.v:20 Missing timeunit/timeprecision for "pkg11".
 
-[ERROR:PA0206] t_package_export.v:23 Missing timeunit/timeprecision for "pkg20".
+[ERROR:PA0206] t_package_export.v:24 Missing timeunit/timeprecision for "pkg20".
 
-[ERROR:PA0206] t_package_export.v:27 Missing timeunit/timeprecision for "pkg21".
+[ERROR:PA0206] t_package_export.v:29 Missing timeunit/timeprecision for "pkg21".
 
-[ERROR:PA0206] t_package_export.v:31 Missing timeunit/timeprecision for "pkg30".
+[ERROR:PA0206] t_package_export.v:33 Missing timeunit/timeprecision for "pkg30".
 
-[ERROR:PA0206] t_package_export.v:35 Missing timeunit/timeprecision for "pkg31".
+[ERROR:PA0206] t_package_export.v:38 Missing timeunit/timeprecision for "pkg31".
 
 [ERROR:PA0206] t_package_twodeep.v:8 Missing timeunit/timeprecision for "pkg2".
 
@@ -8736,25 +8736,25 @@
 
 [ERROR:PA0206] t_sv_conditional.v:62 Missing timeunit/timeprecision for "st3_testbench".
 
-[ERROR:PA0206] t_sv_conditional.v:145 Missing timeunit/timeprecision for "simple_test_3".
+[ERROR:PA0206] t_sv_conditional.v:146 Missing timeunit/timeprecision for "simple_test_3".
 
-[ERROR:PA0206] t_sv_conditional.v:230 Missing timeunit/timeprecision for "counterA".
+[ERROR:PA0206] t_sv_conditional.v:231 Missing timeunit/timeprecision for "counterA".
 
-[ERROR:PA0206] t_sv_conditional.v:277 Missing timeunit/timeprecision for "counterB".
+[ERROR:PA0206] t_sv_conditional.v:278 Missing timeunit/timeprecision for "counterB".
 
-[ERROR:PA0206] t_sv_conditional.v:311 Missing timeunit/timeprecision for "simple_test_3a".
+[ERROR:PA0206] t_sv_conditional.v:312 Missing timeunit/timeprecision for "simple_test_3a".
 
-[ERROR:PA0206] t_sv_conditional.v:331 Missing timeunit/timeprecision for "simple_test_3b".
+[ERROR:PA0206] t_sv_conditional.v:332 Missing timeunit/timeprecision for "simple_test_3b".
 
-[ERROR:PA0206] t_sv_conditional.v:363 Missing timeunit/timeprecision for "simple_test_3c".
+[ERROR:PA0206] t_sv_conditional.v:364 Missing timeunit/timeprecision for "simple_test_3c".
 
-[ERROR:PA0206] t_sv_conditional.v:395 Missing timeunit/timeprecision for "simple_test_3d".
+[ERROR:PA0206] t_sv_conditional.v:396 Missing timeunit/timeprecision for "simple_test_3d".
 
-[ERROR:PA0206] t_sv_conditional.v:425 Missing timeunit/timeprecision for "simple_test_3e".
+[ERROR:PA0206] t_sv_conditional.v:426 Missing timeunit/timeprecision for "simple_test_3e".
 
-[ERROR:PA0206] t_sv_conditional.v:449 Missing timeunit/timeprecision for "simple_test_3f".
+[ERROR:PA0206] t_sv_conditional.v:450 Missing timeunit/timeprecision for "simple_test_3f".
 
-[ERROR:PA0206] t_sv_cpu.v:79 Missing timeunit/timeprecision for "testbench".
+[ERROR:PA0206] t_sv_cpu.v:81 Missing timeunit/timeprecision for "testbench".
 
 [ERROR:PA0206] t_trace_param.v:6 Missing timeunit/timeprecision for "my_funcs".
 
@@ -8764,9 +8764,9 @@
 
 [ERROR:PA0206] t_trace_public.v:32 Missing timeunit/timeprecision for "glbl".
 
-[ERROR:PA0206] t_trace_public.v:36 Missing timeunit/timeprecision for "neg".
+[ERROR:PA0206] t_trace_public.v:38 Missing timeunit/timeprecision for "neg".
 
-[ERROR:PA0206] t_trace_public.v:51 Missing timeunit/timeprecision for "little".
+[ERROR:PA0206] t_trace_public.v:53 Missing timeunit/timeprecision for "little".
 
 [ERROR:PA0206] t_tri_array.v:65 Missing timeunit/timeprecision for "Pad".
 
@@ -8776,7 +8776,7 @@
 
 [ERROR:PA0206] t_tri_gate.v:20 Missing timeunit/timeprecision for "tbuf".
 
-[ERROR:PA0206] t_tri_gate.v:24 Missing timeunit/timeprecision for "mux".
+[ERROR:PA0206] t_tri_gate.v:26 Missing timeunit/timeprecision for "mux".
 
 [ERROR:PA0206] t_tri_gen.v:27 Missing timeunit/timeprecision for "updown".
 
@@ -8804,17 +8804,17 @@
 
 [ERROR:PA0206] t_tri_unconn.v:90 Missing timeunit/timeprecision for "t_tri1".
 
-[ERROR:PA0206] t_tri_various.v:146 Missing timeunit/timeprecision for "Test3".
+[ERROR:PA0206] t_tri_various.v:155 Missing timeunit/timeprecision for "Test3".
 
-[ERROR:PA0206] t_tri_various.v:154 Missing timeunit/timeprecision for "Test4".
+[ERROR:PA0206] t_tri_various.v:165 Missing timeunit/timeprecision for "Test4".
 
-[ERROR:PA0206] t_tri_various.v:159 Missing timeunit/timeprecision for "Test5".
+[ERROR:PA0206] t_tri_various.v:170 Missing timeunit/timeprecision for "Test5".
 
-[ERROR:PA0206] t_tri_various.v:167 Missing timeunit/timeprecision for "Test6".
+[ERROR:PA0206] t_tri_various.v:178 Missing timeunit/timeprecision for "Test6".
 
-[ERROR:PA0206] t_tri_various.v:173 Missing timeunit/timeprecision for "Test6a".
+[ERROR:PA0206] t_tri_various.v:184 Missing timeunit/timeprecision for "Test6a".
 
-[ERROR:PA0206] t_tri_various.v:177 Missing timeunit/timeprecision for "Test7".
+[ERROR:PA0206] t_tri_various.v:188 Missing timeunit/timeprecision for "Test7".
 
 [ERROR:PA0206] t_type_param.v:15 Missing timeunit/timeprecision for "foo_wrapper".
 
@@ -8828,25 +8828,25 @@
 
 [ERROR:PA0206] t_udp_noname.v:35 Missing timeunit/timeprecision for "udp".
 
-[ERROR:PA0206] t_unoptflat_simple_3.v:41 Missing timeunit/timeprecision for "test1".
+[ERROR:PA0206] t_unoptflat_simple_3.v:42 Missing timeunit/timeprecision for "test1".
 
-[ERROR:PA0206] t_unoptflat_simple_3.v:60 Missing timeunit/timeprecision for "test2".
+[ERROR:PA0206] t_unoptflat_simple_3.v:61 Missing timeunit/timeprecision for "test2".
 
-[ERROR:PA0206] t_vams_wreal.v:87 Missing timeunit/timeprecision for "through".
+[ERROR:PA0206] t_vams_wreal.v:89 Missing timeunit/timeprecision for "through".
 
-[ERROR:PA0206] t_vams_wreal.v:93 Missing timeunit/timeprecision for "within_range".
+[ERROR:PA0206] t_vams_wreal.v:95 Missing timeunit/timeprecision for "within_range".
 
-[ERROR:PA0206] t_vams_wreal.v:106 Missing timeunit/timeprecision for "wreal_bus".
+[ERROR:PA0206] t_vams_wreal.v:108 Missing timeunit/timeprecision for "wreal_bus".
 
-[ERROR:PA0206] t_vams_wreal.v:114 Missing timeunit/timeprecision for "first_level".
+[ERROR:PA0206] t_vams_wreal.v:116 Missing timeunit/timeprecision for "first_level".
 
-[ERROR:PA0206] t_vams_wreal.v:121 Missing timeunit/timeprecision for "second_level".
+[ERROR:PA0206] t_vams_wreal.v:125 Missing timeunit/timeprecision for "second_level".
 
 [ERROR:PA0206] t_var_dup_bad.v:46 Missing timeunit/timeprecision for "sub0".
 
 [ERROR:PA0206] t_var_dup_bad.v:68 Missing timeunit/timeprecision for "sub3".
 
-[ERROR:PA0206] t_var_in_assign.v:59 Missing timeunit/timeprecision for "z".
+[ERROR:PA0206] t_var_in_assign.v:60 Missing timeunit/timeprecision for "z".
 
 [ERROR:PA0206] t_var_notfound_bad.v:32 Missing timeunit/timeprecision for "subsub".
 
@@ -8854,7 +8854,7 @@
 
 [ERROR:PA0206] t_var_port_bad.v:11 Missing timeunit/timeprecision for "subok".
 
-[ERROR:PA0206] t_vpi_var.v:87 Missing timeunit/timeprecision for "arr".
+[ERROR:PA0206] t_vpi_var.v:95 Missing timeunit/timeprecision for "arr".
 
 [ERROR:PA0206] t_xml_first.v:44 Missing timeunit/timeprecision for "mod2".
 
@@ -8872,7 +8872,7 @@
 
 [ERROR:PA0206] t_sv_cpu_code/pad_vdd.sv:12 Missing timeunit/timeprecision for "pad_vdd".
 
-[ERROR:PA0206] t_sv_cpu_code/ports.sv:9 Missing timeunit/timeprecision for "ports".
+[ERROR:PA0206] t_sv_cpu_code/ports.sv:11 Missing timeunit/timeprecision for "ports".
 
 [ERROR:PA0206] t_sv_cpu_code/ac_dig.sv:8 Missing timeunit/timeprecision for "ac_dig".
 
diff --git a/third_party/tests/Yosys/Yosys.log b/third_party/tests/Yosys/Yosys.log
index c41a9cd..f6e6ddd 100644
--- a/third_party/tests/Yosys/Yosys.log
+++ b/third_party/tests/Yosys/Yosys.log
@@ -112,11 +112,11 @@
 
 [WARNI:PA0205] simple/multiplier.v:8 No timescale set for "Multiplier_flat".
 
-[WARNI:PA0205] simple/multiplier.v:66 No timescale set for "Multiplier_2D".
+[WARNI:PA0205] simple/multiplier.v:69 No timescale set for "Multiplier_2D".
 
-[WARNI:PA0205] simple/multiplier.v:98 No timescale set for "RippleCarryAdder".
+[WARNI:PA0205] simple/multiplier.v:101 No timescale set for "RippleCarryAdder".
 
-[WARNI:PA0205] simple/multiplier.v:119 No timescale set for "FullAdder".
+[WARNI:PA0205] simple/multiplier.v:122 No timescale set for "FullAdder".
 
 [WARNI:PA0205] simple/dff_different_styles.v:2 No timescale set for "dff".
 
@@ -488,7 +488,7 @@
 
 [WARNI:PA0205] various/pmux2shiftx.v:36 No timescale set for "issue01135".
 
-[WARNI:PA0205] various/specify.v:16 No timescale set for "test2".
+[WARNI:PA0205] various/specify.v:18 No timescale set for "test2".
 
 [WARNI:PA0205] various/specify.v:35 No timescale set for "issue01144".
 
@@ -948,7 +948,7 @@
 
 [WARNI:PA0205] sva/extnets.sv:9 No timescale set for "A".
 
-[WARNI:PA0205] sva/extnets.sv:15 No timescale set for "B".
+[WARNI:PA0205] sva/extnets.sv:17 No timescale set for "B".
 
 [WARNI:PA0205] svinterfaces/svinterface_at_top.sv:33 No timescale set for "MyInterface".
 
diff --git a/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log b/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log
index 0959c71..ece4d89 100644
--- a/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log
+++ b/third_party/tests/YosysBigSim/amber23/YosysBigSimAmber23.log
@@ -4,7 +4,7 @@
 
 [SYNTX:PA0207] rtl/a23_decode.v:174 Syntax error: mismatched input 'type' expecting {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'context', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier},
 reg     [3:0]          type;
-                       ^-- ../../../build/tests/YosysBigSimAmber23/slpp_unit/work/rtl/a23_decode.v:518 col:23.
+                       ^-- ../../../build/tests/YosysBigSimAmber23/slpp_unit/work/rtl/a23_decode.v:526 col:23.
 
 [WARNI:PA0205] sim/bench.v:2 No timescale set for "testbench".
 
diff --git a/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log b/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log
index 3cadbf9..ac55da6 100644
--- a/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log
+++ b/third_party/tests/YosysBigSim/lm32/YosysBigSimLm32.log
@@ -48,17 +48,17 @@
 
 [WARNI:PA0205] rtl/lm32_multiplier.v:55 No timescale set for "lm32_multiplier".
 
-[WARNI:PA0205] rtl/lm32_icache.v:67 No timescale set for "lm32_icache".
+[WARNI:PA0205] rtl/lm32_icache.v:68 No timescale set for "lm32_icache".
 
 [WARNI:PA0205] rtl/lm32_interrupt.v:55 No timescale set for "lm32_interrupt".
 
-[WARNI:PA0205] rtl/lm32_dtlb.v:41 No timescale set for "lm32_dtlb".
+[WARNI:PA0205] rtl/lm32_dtlb.v:42 No timescale set for "lm32_dtlb".
 
 [WARNI:PA0205] rtl/lm32_logic_op.v:55 No timescale set for "lm32_logic_op".
 
-[WARNI:PA0205] rtl/lm32_debug.v:61 No timescale set for "lm32_debug".
+[WARNI:PA0205] rtl/lm32_debug.v:62 No timescale set for "lm32_debug".
 
-[WARNI:PA0205] rtl/lm32_dcache.v:62 No timescale set for "lm32_dcache".
+[WARNI:PA0205] rtl/lm32_dcache.v:63 No timescale set for "lm32_dcache".
 
 [WARNI:PA0205] rtl/lm32_adder.v:55 No timescale set for "lm32_adder".
 
@@ -66,7 +66,7 @@
 
 [WARNI:PA0205] rtl/lm32_top.v:55 No timescale set for "lm32_top".
 
-[WARNI:PA0205] rtl/lm32_itlb.v:40 No timescale set for "lm32_itlb".
+[WARNI:PA0205] rtl/lm32_itlb.v:41 No timescale set for "lm32_itlb".
 
 [WARNI:PA0205] rtl/lm32_ram.v:60 No timescale set for "lm32_ram".
 
@@ -86,23 +86,23 @@
 
 [INFO :CP0303] rtl/lm32_cpu.v:98 Compile module "work@lm32_cpu".
 
-[INFO :CP0303] rtl/lm32_dcache.v:62 Compile module "work@lm32_dcache".
+[INFO :CP0303] rtl/lm32_dcache.v:63 Compile module "work@lm32_dcache".
 
-[INFO :CP0303] rtl/lm32_debug.v:61 Compile module "work@lm32_debug".
+[INFO :CP0303] rtl/lm32_debug.v:62 Compile module "work@lm32_debug".
 
 [INFO :CP0303] rtl/lm32_decoder.v:65 Compile module "work@lm32_decoder".
 
 [INFO :CP0303] rtl/lm32_dp_ram.v:36 Compile module "work@lm32_dp_ram".
 
-[INFO :CP0303] rtl/lm32_dtlb.v:41 Compile module "work@lm32_dtlb".
+[INFO :CP0303] rtl/lm32_dtlb.v:42 Compile module "work@lm32_dtlb".
 
-[INFO :CP0303] rtl/lm32_icache.v:67 Compile module "work@lm32_icache".
+[INFO :CP0303] rtl/lm32_icache.v:68 Compile module "work@lm32_icache".
 
 [INFO :CP0303] rtl/lm32_instruction_unit.v:76 Compile module "work@lm32_instruction_unit".
 
 [INFO :CP0303] rtl/lm32_interrupt.v:55 Compile module "work@lm32_interrupt".
 
-[INFO :CP0303] rtl/lm32_itlb.v:40 Compile module "work@lm32_itlb".
+[INFO :CP0303] rtl/lm32_itlb.v:41 Compile module "work@lm32_itlb".
 
 [INFO :CP0303] rtl/lm32_load_store_unit.v:68 Compile module "work@lm32_load_store_unit".
 
@@ -126,45 +126,45 @@
 [NOTE :CP0309] rtl/lm32_addsub.v:61 Implicit port type (wire) for "Result",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_cpu.v:118 Implicit port type (wire) for "I_DAT_O",
+[NOTE :CP0309] rtl/lm32_cpu.v:134 Implicit port type (wire) for "I_DAT_O",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_dcache.v:80 Implicit port type (wire) for "stall_request",
+[NOTE :CP0309] rtl/lm32_dcache.v:83 Implicit port type (wire) for "stall_request",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_debug.v:81 Implicit port type (wire) for "bp_match",
+[NOTE :CP0309] rtl/lm32_debug.v:89 Implicit port type (wire) for "bp_match",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_decoder.v:80 Implicit port type (wire) for "x_bypass_enable",
+[NOTE :CP0309] rtl/lm32_decoder.v:90 Implicit port type (wire) for "x_bypass_enable",
 there are 28 more instances of this message.
 
 [NOTE :CP0309] rtl/lm32_dp_ram.v:49 Implicit port type (wire) for "do_a",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_dtlb.v:62 Implicit port type (wire) for "physical_load_store_address_m",
+[NOTE :CP0309] rtl/lm32_dtlb.v:63 Implicit port type (wire) for "physical_load_store_address_m",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_icache.v:83 Implicit port type (wire) for "stall_request",
+[NOTE :CP0309] rtl/lm32_icache.v:87 Implicit port type (wire) for "stall_request",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_instruction_unit.v:116 Implicit port type (wire) for "icache_stall_request",
+[NOTE :CP0309] rtl/lm32_instruction_unit.v:131 Implicit port type (wire) for "icache_stall_request",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_interrupt.v:71 Implicit port type (wire) for "interrupt_exception".
+[NOTE :CP0309] rtl/lm32_interrupt.v:75 Implicit port type (wire) for "interrupt_exception".
 
-[NOTE :CP0309] rtl/lm32_itlb.v:60 Implicit port type (wire) for "stall_request",
+[NOTE :CP0309] rtl/lm32_itlb.v:61 Implicit port type (wire) for "stall_request",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_load_store_unit.v:106 Implicit port type (wire) for "dcache_refill_request",
+[NOTE :CP0309] rtl/lm32_load_store_unit.v:114 Implicit port type (wire) for "dcache_refill_request",
 there are 8 more instances of this message.
 
-[NOTE :CP0309] rtl/lm32_mc_arithmetic.v:69 Implicit port type (wire) for "stall_request_x".
+[NOTE :CP0309] rtl/lm32_mc_arithmetic.v:75 Implicit port type (wire) for "stall_request_x".
 
 [NOTE :CP0309] rtl/lm32_ram.v:72 Implicit port type (wire) for "read_data".
 
 [NOTE :CP0309] rtl/lm32_shifter.v:65 Implicit port type (wire) for "shifter_result_m".
 
-[NOTE :CP0309] rtl/lm32_top.v:75 Implicit port type (wire) for "I_DAT_O",
+[NOTE :CP0309] rtl/lm32_top.v:87 Implicit port type (wire) for "I_DAT_O",
 there are 17 more instances of this message.
 
 [INFO :EL0526] Design Elaboration...
diff --git a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log
index da63ee6..d1ffb2d 100644
--- a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log
+++ b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log
@@ -44,142 +44,142 @@
 
 [WARNI:PA0205] rtl/omsp_clock_mux.v:44 No timescale set for "omsp_clock_mux".
 
-[WARNI:PA0205] rtl/omsp_dbg_uart.v:46 No timescale set for "omsp_dbg_uart".
+[WARNI:PA0205] rtl/omsp_dbg_uart.v:47 No timescale set for "omsp_dbg_uart".
 
-[WARNI:PA0205] rtl/omsp_wakeup_cell.v:46 No timescale set for "omsp_wakeup_cell".
+[WARNI:PA0205] rtl/omsp_wakeup_cell.v:47 No timescale set for "omsp_wakeup_cell".
 
-[WARNI:PA0205] rtl/omsp_frontend.v:46 No timescale set for "omsp_frontend".
+[WARNI:PA0205] rtl/omsp_frontend.v:47 No timescale set for "omsp_frontend".
 
 [WARNI:PA0205] rtl/omsp_sync_cell.v:44 No timescale set for "omsp_sync_cell".
 
-[WARNI:PA0205] rtl/omsp_dbg.v:46 No timescale set for "omsp_dbg".
+[WARNI:PA0205] rtl/omsp_dbg.v:47 No timescale set for "omsp_dbg".
 
-[WARNI:PA0205] rtl/omsp_watchdog.v:46 No timescale set for "omsp_watchdog".
+[WARNI:PA0205] rtl/omsp_watchdog.v:47 No timescale set for "omsp_watchdog".
 
 [WARNI:PA0205] rtl/omsp_and_gate.v:44 No timescale set for "omsp_and_gate".
 
 [WARNI:PA0205] rtl/omsp_clock_gate.v:44 No timescale set for "omsp_clock_gate".
 
-[WARNI:PA0205] rtl/omsp_execution_unit.v:46 No timescale set for "omsp_execution_unit".
+[WARNI:PA0205] rtl/omsp_execution_unit.v:47 No timescale set for "omsp_execution_unit".
 
 [WARNI:PA0205] rtl/omsp_sync_reset.v:44 No timescale set for "omsp_sync_reset".
 
 [WARNI:PA0205] rtl/omsp_scan_mux.v:44 No timescale set for "omsp_scan_mux".
 
-[WARNI:PA0205] rtl/omsp_mem_backbone.v:46 No timescale set for "omsp_mem_backbone".
+[WARNI:PA0205] rtl/omsp_mem_backbone.v:47 No timescale set for "omsp_mem_backbone".
 
-[WARNI:PA0205] rtl/omsp_multiplier.v:46 No timescale set for "omsp_multiplier".
+[WARNI:PA0205] rtl/omsp_multiplier.v:47 No timescale set for "omsp_multiplier".
 
-[WARNI:PA0205] rtl/omsp_sfr.v:47 No timescale set for "omsp_sfr".
+[WARNI:PA0205] rtl/omsp_sfr.v:48 No timescale set for "omsp_sfr".
 
-[WARNI:PA0205] rtl/omsp_alu.v:46 No timescale set for "omsp_alu".
+[WARNI:PA0205] rtl/omsp_alu.v:47 No timescale set for "omsp_alu".
 
-[WARNI:PA0205] rtl/openMSP430.v:46 No timescale set for "openMSP430".
+[WARNI:PA0205] rtl/openMSP430.v:47 No timescale set for "openMSP430".
 
-[WARNI:PA0205] rtl/omsp_dbg_i2c.v:46 No timescale set for "omsp_dbg_i2c".
+[WARNI:PA0205] rtl/omsp_dbg_i2c.v:47 No timescale set for "omsp_dbg_i2c".
 
-[WARNI:PA0205] rtl/omsp_clock_module.v:46 No timescale set for "omsp_clock_module".
+[WARNI:PA0205] rtl/omsp_clock_module.v:47 No timescale set for "omsp_clock_module".
 
-[WARNI:PA0205] rtl/omsp_register_file.v:46 No timescale set for "omsp_register_file".
+[WARNI:PA0205] rtl/omsp_register_file.v:47 No timescale set for "omsp_register_file".
 
-[WARNI:PA0205] rtl/omsp_dbg_hwbrk.v:46 No timescale set for "omsp_dbg_hwbrk".
+[WARNI:PA0205] rtl/omsp_dbg_hwbrk.v:47 No timescale set for "omsp_dbg_hwbrk".
 
 [INFO :CP0300] Compilation...
 
-[INFO :CP0303] rtl/omsp_alu.v:46 Compile module "work@omsp_alu".
+[INFO :CP0303] rtl/omsp_alu.v:47 Compile module "work@omsp_alu".
 
 [INFO :CP0303] rtl/omsp_and_gate.v:44 Compile module "work@omsp_and_gate".
 
 [INFO :CP0303] rtl/omsp_clock_gate.v:44 Compile module "work@omsp_clock_gate".
 
-[INFO :CP0303] rtl/omsp_clock_module.v:46 Compile module "work@omsp_clock_module".
+[INFO :CP0303] rtl/omsp_clock_module.v:47 Compile module "work@omsp_clock_module".
 
 [INFO :CP0303] rtl/omsp_clock_mux.v:44 Compile module "work@omsp_clock_mux".
 
-[INFO :CP0303] rtl/omsp_dbg.v:46 Compile module "work@omsp_dbg".
+[INFO :CP0303] rtl/omsp_dbg.v:47 Compile module "work@omsp_dbg".
 
-[INFO :CP0303] rtl/omsp_dbg_hwbrk.v:46 Compile module "work@omsp_dbg_hwbrk".
+[INFO :CP0303] rtl/omsp_dbg_hwbrk.v:47 Compile module "work@omsp_dbg_hwbrk".
 
-[INFO :CP0303] rtl/omsp_dbg_i2c.v:46 Compile module "work@omsp_dbg_i2c".
+[INFO :CP0303] rtl/omsp_dbg_i2c.v:47 Compile module "work@omsp_dbg_i2c".
 
-[INFO :CP0303] rtl/omsp_dbg_uart.v:46 Compile module "work@omsp_dbg_uart".
+[INFO :CP0303] rtl/omsp_dbg_uart.v:47 Compile module "work@omsp_dbg_uart".
 
-[INFO :CP0303] rtl/omsp_execution_unit.v:46 Compile module "work@omsp_execution_unit".
+[INFO :CP0303] rtl/omsp_execution_unit.v:47 Compile module "work@omsp_execution_unit".
 
-[INFO :CP0303] rtl/omsp_frontend.v:46 Compile module "work@omsp_frontend".
+[INFO :CP0303] rtl/omsp_frontend.v:47 Compile module "work@omsp_frontend".
 
-[INFO :CP0303] rtl/omsp_mem_backbone.v:46 Compile module "work@omsp_mem_backbone".
+[INFO :CP0303] rtl/omsp_mem_backbone.v:47 Compile module "work@omsp_mem_backbone".
 
-[INFO :CP0303] rtl/omsp_multiplier.v:46 Compile module "work@omsp_multiplier".
+[INFO :CP0303] rtl/omsp_multiplier.v:47 Compile module "work@omsp_multiplier".
 
-[INFO :CP0303] rtl/omsp_register_file.v:46 Compile module "work@omsp_register_file".
+[INFO :CP0303] rtl/omsp_register_file.v:47 Compile module "work@omsp_register_file".
 
 [INFO :CP0303] rtl/omsp_scan_mux.v:44 Compile module "work@omsp_scan_mux".
 
-[INFO :CP0303] rtl/omsp_sfr.v:47 Compile module "work@omsp_sfr".
+[INFO :CP0303] rtl/omsp_sfr.v:48 Compile module "work@omsp_sfr".
 
 [INFO :CP0303] rtl/omsp_sync_cell.v:44 Compile module "work@omsp_sync_cell".
 
 [INFO :CP0303] rtl/omsp_sync_reset.v:44 Compile module "work@omsp_sync_reset".
 
-[INFO :CP0303] rtl/omsp_wakeup_cell.v:46 Compile module "work@omsp_wakeup_cell".
+[INFO :CP0303] rtl/omsp_wakeup_cell.v:47 Compile module "work@omsp_wakeup_cell".
 
-[INFO :CP0303] rtl/omsp_watchdog.v:46 Compile module "work@omsp_watchdog".
+[INFO :CP0303] rtl/omsp_watchdog.v:47 Compile module "work@omsp_watchdog".
 
-[INFO :CP0303] rtl/openMSP430.v:46 Compile module "work@openMSP430".
+[INFO :CP0303] rtl/openMSP430.v:47 Compile module "work@openMSP430".
 
 [INFO :CP0303] sim/bench.v:6 Compile module "work@testbench".
 
-[NOTE :CP0309] rtl/omsp_alu.v:49 Implicit port type (wire) for "alu_out",
+[NOTE :CP0309] rtl/omsp_alu.v:50 Implicit port type (wire) for "alu_out",
 there are 3 more instances of this message.
 
 [NOTE :CP0309] rtl/omsp_and_gate.v:47 Implicit port type (wire) for "y".
 
 [NOTE :CP0309] rtl/omsp_clock_gate.v:47 Implicit port type (wire) for "gclk".
 
-[NOTE :CP0309] rtl/omsp_clock_module.v:49 Implicit port type (wire) for "aclk",
+[NOTE :CP0309] rtl/omsp_clock_module.v:50 Implicit port type (wire) for "aclk",
 there are 14 more instances of this message.
 
 [NOTE :CP0309] rtl/omsp_clock_mux.v:47 Implicit port type (wire) for "clk_out".
 
-[NOTE :CP0309] rtl/omsp_dbg.v:49 Implicit port type (wire) for "dbg_cpu_reset",
+[NOTE :CP0309] rtl/omsp_dbg.v:50 Implicit port type (wire) for "dbg_cpu_reset",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] rtl/omsp_dbg_hwbrk.v:49 Implicit port type (wire) for "brk_halt",
+[NOTE :CP0309] rtl/omsp_dbg_hwbrk.v:50 Implicit port type (wire) for "brk_halt",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] rtl/omsp_dbg_i2c.v:50 Implicit port type (wire) for "dbg_din".
+[NOTE :CP0309] rtl/omsp_dbg_i2c.v:51 Implicit port type (wire) for "dbg_din".
 
-[NOTE :CP0309] rtl/omsp_dbg_uart.v:50 Implicit port type (wire) for "dbg_din",
+[NOTE :CP0309] rtl/omsp_dbg_uart.v:51 Implicit port type (wire) for "dbg_din",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] rtl/omsp_execution_unit.v:49 Implicit port type (wire) for "cpuoff",
+[NOTE :CP0309] rtl/omsp_execution_unit.v:50 Implicit port type (wire) for "cpuoff",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] rtl/omsp_frontend.v:50 Implicit port type (wire) for "decode_noirq",
+[NOTE :CP0309] rtl/omsp_frontend.v:51 Implicit port type (wire) for "decode_noirq",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] rtl/omsp_mem_backbone.v:49 Implicit port type (wire) for "dbg_mem_din",
+[NOTE :CP0309] rtl/omsp_mem_backbone.v:50 Implicit port type (wire) for "dbg_mem_din",
 there are 15 more instances of this message.
 
-[NOTE :CP0309] rtl/omsp_multiplier.v:49 Implicit port type (wire) for "per_dout".
+[NOTE :CP0309] rtl/omsp_multiplier.v:50 Implicit port type (wire) for "per_dout".
 
-[NOTE :CP0309] rtl/omsp_register_file.v:49 Implicit port type (wire) for "cpuoff",
+[NOTE :CP0309] rtl/omsp_register_file.v:50 Implicit port type (wire) for "cpuoff",
 there are 9 more instances of this message.
 
 [NOTE :CP0309] rtl/omsp_scan_mux.v:47 Implicit port type (wire) for "data_out".
 
-[NOTE :CP0309] rtl/omsp_sfr.v:50 Implicit port type (wire) for "cpu_id",
+[NOTE :CP0309] rtl/omsp_sfr.v:51 Implicit port type (wire) for "cpu_id",
 there are 5 more instances of this message.
 
 [NOTE :CP0309] rtl/omsp_sync_cell.v:47 Implicit port type (wire) for "data_out".
 
 [NOTE :CP0309] rtl/omsp_sync_reset.v:47 Implicit port type (wire) for "rst_s".
 
-[NOTE :CP0309] rtl/omsp_watchdog.v:49 Implicit port type (wire) for "per_dout",
+[NOTE :CP0309] rtl/omsp_watchdog.v:50 Implicit port type (wire) for "per_dout",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] rtl/openMSP430.v:49 Implicit port type (wire) for "aclk",
+[NOTE :CP0309] rtl/openMSP430.v:50 Implicit port type (wire) for "aclk",
 there are 25 more instances of this message.
 
 [INFO :EL0526] Design Elaboration...
@@ -188,7 +188,7 @@
 
 [NOTE :EL0503] rtl/omsp_clock_mux.v:44 Top level module "work@omsp_clock_mux".
 
-[NOTE :EL0503] rtl/omsp_wakeup_cell.v:46 Top level module "work@omsp_wakeup_cell".
+[NOTE :EL0503] rtl/omsp_wakeup_cell.v:47 Top level module "work@omsp_wakeup_cell".
 
 [NOTE :EL0503] rtl/omsp_and_gate.v:44 Top level module "work@omsp_and_gate".
 
@@ -196,9 +196,9 @@
 
 [NOTE :EL0503] rtl/omsp_scan_mux.v:44 Top level module "work@omsp_scan_mux".
 
-[NOTE :EL0503] rtl/omsp_dbg_i2c.v:46 Top level module "work@omsp_dbg_i2c".
+[NOTE :EL0503] rtl/omsp_dbg_i2c.v:47 Top level module "work@omsp_dbg_i2c".
 
-[NOTE :EL0503] rtl/omsp_dbg_hwbrk.v:46 Top level module "work@omsp_dbg_hwbrk".
+[NOTE :EL0503] rtl/omsp_dbg_hwbrk.v:47 Top level module "work@omsp_dbg_hwbrk".
 
 [NOTE :EL0504] Multiple top level modules in design.
 
diff --git a/third_party/tests/YosysBoom/YosysSmallBoom.log b/third_party/tests/YosysBoom/YosysSmallBoom.log
index ab9fa11..bac1642 100644
--- a/third_party/tests/YosysBoom/YosysSmallBoom.log
+++ b/third_party/tests/YosysBoom/YosysSmallBoom.log
@@ -2,1171 +2,1171 @@
 
 [INFO :CM0020] Separate compilation-unit mode is on.
 
-[WARNI:PA0205] SmallBoom.v:28 No timescale set for "AsyncResetReg".
+[WARNI:PA0205] SmallBoom.v:32 No timescale set for "AsyncResetReg".
 
-[WARNI:PA0205] SmallBoom.v:61 No timescale set for "IntXbar".
+[WARNI:PA0205] SmallBoom.v:67 No timescale set for "IntXbar".
 
-[WARNI:PA0205] SmallBoom.v:70 No timescale set for "TLXbar".
+[WARNI:PA0205] SmallBoom.v:76 No timescale set for "TLXbar".
 
-[WARNI:PA0205] SmallBoom.v:1484 No timescale set for "TLBuffer".
+[WARNI:PA0205] SmallBoom.v:1587 No timescale set for "TLBuffer".
 
-[WARNI:PA0205] SmallBoom.v:1583 No timescale set for "TLFIFOFixer".
+[WARNI:PA0205] SmallBoom.v:1686 No timescale set for "TLFIFOFixer".
 
-[WARNI:PA0205] SmallBoom.v:1682 No timescale set for "SimpleLazyModule".
+[WARNI:PA0205] SmallBoom.v:1785 No timescale set for "SimpleLazyModule".
 
-[WARNI:PA0205] SmallBoom.v:2105 No timescale set for "Queue".
+[WARNI:PA0205] SmallBoom.v:2208 No timescale set for "Queue".
 
-[WARNI:PA0205] SmallBoom.v:2345 No timescale set for "Queue_1".
+[WARNI:PA0205] SmallBoom.v:2454 No timescale set for "Queue_1".
 
-[WARNI:PA0205] SmallBoom.v:2465 No timescale set for "Queue_2".
+[WARNI:PA0205] SmallBoom.v:2580 No timescale set for "Queue_2".
 
-[WARNI:PA0205] SmallBoom.v:2565 No timescale set for "Queue_4".
+[WARNI:PA0205] SmallBoom.v:2686 No timescale set for "Queue_4".
 
-[WARNI:PA0205] SmallBoom.v:2705 No timescale set for "AXI4Buffer".
+[WARNI:PA0205] SmallBoom.v:2832 No timescale set for "AXI4Buffer".
 
-[WARNI:PA0205] SmallBoom.v:3046 No timescale set for "Queue_5".
+[WARNI:PA0205] SmallBoom.v:3173 No timescale set for "Queue_5".
 
-[WARNI:PA0205] SmallBoom.v:3098 No timescale set for "Queue_7".
+[WARNI:PA0205] SmallBoom.v:3231 No timescale set for "Queue_7".
 
-[WARNI:PA0205] SmallBoom.v:3178 No timescale set for "AXI4UserYanker".
+[WARNI:PA0205] SmallBoom.v:3317 No timescale set for "AXI4UserYanker".
 
-[WARNI:PA0205] SmallBoom.v:3930 No timescale set for "Queue_17".
+[WARNI:PA0205] SmallBoom.v:4081 No timescale set for "Queue_17".
 
-[WARNI:PA0205] SmallBoom.v:4090 No timescale set for "AXI4Deinterleaver".
+[WARNI:PA0205] SmallBoom.v:4247 No timescale set for "AXI4Deinterleaver".
 
-[WARNI:PA0205] SmallBoom.v:5190 No timescale set for "AXI4IdIndexer".
+[WARNI:PA0205] SmallBoom.v:5425 No timescale set for "AXI4IdIndexer".
 
-[WARNI:PA0205] SmallBoom.v:5316 No timescale set for "Queue_23".
+[WARNI:PA0205] SmallBoom.v:5551 No timescale set for "Queue_23".
 
-[WARNI:PA0205] SmallBoom.v:5424 No timescale set for "Queue_24".
+[WARNI:PA0205] SmallBoom.v:5665 No timescale set for "Queue_24".
 
-[WARNI:PA0205] SmallBoom.v:5687 No timescale set for "TLToAXI4".
+[WARNI:PA0205] SmallBoom.v:5934 No timescale set for "TLToAXI4".
 
-[WARNI:PA0205] SmallBoom.v:6453 No timescale set for "TLWidthWidget".
+[WARNI:PA0205] SmallBoom.v:6778 No timescale set for "TLWidthWidget".
 
-[WARNI:PA0205] SmallBoom.v:6510 No timescale set for "SimpleLazyModule_1".
+[WARNI:PA0205] SmallBoom.v:6835 No timescale set for "SimpleLazyModule_1".
 
-[WARNI:PA0205] SmallBoom.v:7749 No timescale set for "TLWidthWidget_1".
+[WARNI:PA0205] SmallBoom.v:8074 No timescale set for "TLWidthWidget_1".
 
-[WARNI:PA0205] SmallBoom.v:7812 No timescale set for "SimpleLazyModule_2".
+[WARNI:PA0205] SmallBoom.v:8137 No timescale set for "SimpleLazyModule_2".
 
-[WARNI:PA0205] SmallBoom.v:7977 No timescale set for "TLWidthWidget_2".
+[WARNI:PA0205] SmallBoom.v:8302 No timescale set for "TLWidthWidget_2".
 
-[WARNI:PA0205] SmallBoom.v:8034 No timescale set for "SimpleLazyModule_3".
+[WARNI:PA0205] SmallBoom.v:8359 No timescale set for "SimpleLazyModule_3".
 
-[WARNI:PA0205] SmallBoom.v:8183 No timescale set for "SystemBus".
+[WARNI:PA0205] SmallBoom.v:8508 No timescale set for "SystemBus".
 
-[WARNI:PA0205] SmallBoom.v:9206 No timescale set for "TLXbar_3".
+[WARNI:PA0205] SmallBoom.v:9531 No timescale set for "TLXbar_3".
 
-[WARNI:PA0205] SmallBoom.v:9263 No timescale set for "Queue_25".
+[WARNI:PA0205] SmallBoom.v:9588 No timescale set for "Queue_25".
 
-[WARNI:PA0205] SmallBoom.v:9483 No timescale set for "Queue_26".
+[WARNI:PA0205] SmallBoom.v:9814 No timescale set for "Queue_26".
 
-[WARNI:PA0205] SmallBoom.v:9663 No timescale set for "TLBuffer_4".
+[WARNI:PA0205] SmallBoom.v:10000 No timescale set for "TLBuffer_4".
 
-[WARNI:PA0205] SmallBoom.v:9828 No timescale set for "TLFIFOFixer_2".
+[WARNI:PA0205] SmallBoom.v:10165 No timescale set for "TLFIFOFixer_2".
 
-[WARNI:PA0205] SmallBoom.v:10433 No timescale set for "Queue_27".
+[WARNI:PA0205] SmallBoom.v:10776 No timescale set for "Queue_27".
 
-[WARNI:PA0205] SmallBoom.v:10561 No timescale set for "Queue_28".
+[WARNI:PA0205] SmallBoom.v:10910 No timescale set for "Queue_28".
 
-[WARNI:PA0205] SmallBoom.v:10649 No timescale set for "AXI4ToTL".
+[WARNI:PA0205] SmallBoom.v:11004 No timescale set for "AXI4ToTL".
 
-[WARNI:PA0205] SmallBoom.v:11595 No timescale set for "Queue_29".
+[WARNI:PA0205] SmallBoom.v:11992 No timescale set for "Queue_29".
 
-[WARNI:PA0205] SmallBoom.v:11675 No timescale set for "AXI4UserYanker_1".
+[WARNI:PA0205] SmallBoom.v:12078 No timescale set for "AXI4UserYanker_1".
 
-[WARNI:PA0205] SmallBoom.v:11957 No timescale set for "Queue_33".
+[WARNI:PA0205] SmallBoom.v:12372 No timescale set for "Queue_33".
 
-[WARNI:PA0205] SmallBoom.v:12125 No timescale set for "AXI4Fragmenter".
+[WARNI:PA0205] SmallBoom.v:12546 No timescale set for "AXI4Fragmenter".
 
-[WARNI:PA0205] SmallBoom.v:13036 No timescale set for "AXI4IdIndexer_1".
+[WARNI:PA0205] SmallBoom.v:13475 No timescale set for "AXI4IdIndexer_1".
 
-[WARNI:PA0205] SmallBoom.v:13132 No timescale set for "SimpleLazyModule_5".
+[WARNI:PA0205] SmallBoom.v:13571 No timescale set for "SimpleLazyModule_5".
 
-[WARNI:PA0205] SmallBoom.v:14094 No timescale set for "FrontBus".
+[WARNI:PA0205] SmallBoom.v:14533 No timescale set for "FrontBus".
 
-[WARNI:PA0205] SmallBoom.v:14485 No timescale set for "TLXbar_4".
+[WARNI:PA0205] SmallBoom.v:14924 No timescale set for "TLXbar_4".
 
-[WARNI:PA0205] SmallBoom.v:14539 No timescale set for "Queue_38".
+[WARNI:PA0205] SmallBoom.v:14978 No timescale set for "Queue_38".
 
-[WARNI:PA0205] SmallBoom.v:14619 No timescale set for "AXI4UserYanker_2".
+[WARNI:PA0205] SmallBoom.v:15064 No timescale set for "AXI4UserYanker_2".
 
-[WARNI:PA0205] SmallBoom.v:16051 No timescale set for "AXI4IdIndexer_2".
+[WARNI:PA0205] SmallBoom.v:16508 No timescale set for "AXI4IdIndexer_2".
 
-[WARNI:PA0205] SmallBoom.v:16185 No timescale set for "Queue_71".
+[WARNI:PA0205] SmallBoom.v:16642 No timescale set for "Queue_71".
 
-[WARNI:PA0205] SmallBoom.v:16448 No timescale set for "TLToAXI4_1".
+[WARNI:PA0205] SmallBoom.v:16911 No timescale set for "TLToAXI4_1".
 
-[WARNI:PA0205] SmallBoom.v:23842 No timescale set for "TLBuffer_6".
+[WARNI:PA0205] SmallBoom.v:25847 No timescale set for "TLBuffer_6".
 
-[WARNI:PA0205] SmallBoom.v:23896 No timescale set for "ProbePicker".
+[WARNI:PA0205] SmallBoom.v:25901 No timescale set for "ProbePicker".
 
-[WARNI:PA0205] SmallBoom.v:23950 No timescale set for "SimpleLazyModule_6".
+[WARNI:PA0205] SmallBoom.v:25955 No timescale set for "SimpleLazyModule_6".
 
-[WARNI:PA0205] SmallBoom.v:24771 No timescale set for "SimpleLazyModule_7".
+[WARNI:PA0205] SmallBoom.v:26776 No timescale set for "SimpleLazyModule_7".
 
-[WARNI:PA0205] SmallBoom.v:24912 No timescale set for "MemoryBus".
+[WARNI:PA0205] SmallBoom.v:26917 No timescale set for "MemoryBus".
 
-[WARNI:PA0205] SmallBoom.v:25315 No timescale set for "TLFIFOFixer_3".
+[WARNI:PA0205] SmallBoom.v:27320 No timescale set for "TLFIFOFixer_3".
 
-[WARNI:PA0205] SmallBoom.v:25966 No timescale set for "TLXbar_5".
+[WARNI:PA0205] SmallBoom.v:27977 No timescale set for "TLXbar_5".
 
-[WARNI:PA0205] SmallBoom.v:26029 No timescale set for "TLXbar_6".
+[WARNI:PA0205] SmallBoom.v:28040 No timescale set for "TLXbar_6".
 
-[WARNI:PA0205] SmallBoom.v:26634 No timescale set for "Queue_72".
+[WARNI:PA0205] SmallBoom.v:28669 No timescale set for "Queue_72".
 
-[WARNI:PA0205] SmallBoom.v:26814 No timescale set for "Queue_73".
+[WARNI:PA0205] SmallBoom.v:28855 No timescale set for "Queue_73".
 
-[WARNI:PA0205] SmallBoom.v:27034 No timescale set for "TLBuffer_7".
+[WARNI:PA0205] SmallBoom.v:29081 No timescale set for "TLBuffer_7".
 
-[WARNI:PA0205] SmallBoom.v:27199 No timescale set for "TLAtomicAutomata_1".
+[WARNI:PA0205] SmallBoom.v:29246 No timescale set for "TLAtomicAutomata_1".
 
-[WARNI:PA0205] SmallBoom.v:28665 No timescale set for "Queue_74".
+[WARNI:PA0205] SmallBoom.v:30730 No timescale set for "Queue_74".
 
-[WARNI:PA0205] SmallBoom.v:28757 No timescale set for "TLError".
+[WARNI:PA0205] SmallBoom.v:30828 No timescale set for "TLError".
 
-[WARNI:PA0205] SmallBoom.v:28920 No timescale set for "Queue_75".
+[WARNI:PA0205] SmallBoom.v:30997 No timescale set for "Queue_75".
 
-[WARNI:PA0205] SmallBoom.v:29040 No timescale set for "TLBuffer_8".
+[WARNI:PA0205] SmallBoom.v:31123 No timescale set for "TLBuffer_8".
 
-[WARNI:PA0205] SmallBoom.v:29177 No timescale set for "SimpleLazyModule_8".
+[WARNI:PA0205] SmallBoom.v:31260 No timescale set for "SimpleLazyModule_8".
 
-[WARNI:PA0205] SmallBoom.v:29313 No timescale set for "Repeater".
+[WARNI:PA0205] SmallBoom.v:31396 No timescale set for "Repeater".
 
-[WARNI:PA0205] SmallBoom.v:29396 No timescale set for "TLFragmenter".
+[WARNI:PA0205] SmallBoom.v:31485 No timescale set for "TLFragmenter".
 
-[WARNI:PA0205] SmallBoom.v:29706 No timescale set for "SimpleLazyModule_9".
+[WARNI:PA0205] SmallBoom.v:31813 No timescale set for "SimpleLazyModule_9".
 
-[WARNI:PA0205] SmallBoom.v:29831 No timescale set for "Repeater_1".
+[WARNI:PA0205] SmallBoom.v:31938 No timescale set for "Repeater_1".
 
-[WARNI:PA0205] SmallBoom.v:29914 No timescale set for "TLFragmenter_1".
+[WARNI:PA0205] SmallBoom.v:32027 No timescale set for "TLFragmenter_1".
 
-[WARNI:PA0205] SmallBoom.v:30224 No timescale set for "SimpleLazyModule_10".
+[WARNI:PA0205] SmallBoom.v:32355 No timescale set for "SimpleLazyModule_10".
 
-[WARNI:PA0205] SmallBoom.v:30349 No timescale set for "Repeater_2".
+[WARNI:PA0205] SmallBoom.v:32480 No timescale set for "Repeater_2".
 
-[WARNI:PA0205] SmallBoom.v:30432 No timescale set for "TLFragmenter_2".
+[WARNI:PA0205] SmallBoom.v:32569 No timescale set for "TLFragmenter_2".
 
-[WARNI:PA0205] SmallBoom.v:30742 No timescale set for "SimpleLazyModule_11".
+[WARNI:PA0205] SmallBoom.v:32897 No timescale set for "SimpleLazyModule_11".
 
-[WARNI:PA0205] SmallBoom.v:30867 No timescale set for "Repeater_3".
+[WARNI:PA0205] SmallBoom.v:33022 No timescale set for "Repeater_3".
 
-[WARNI:PA0205] SmallBoom.v:30942 No timescale set for "TLFragmenter_3".
+[WARNI:PA0205] SmallBoom.v:33103 No timescale set for "TLFragmenter_3".
 
-[WARNI:PA0205] SmallBoom.v:31194 No timescale set for "SimpleLazyModule_13".
+[WARNI:PA0205] SmallBoom.v:33367 No timescale set for "SimpleLazyModule_13".
 
-[WARNI:PA0205] SmallBoom.v:31291 No timescale set for "PeripheryBus_1".
+[WARNI:PA0205] SmallBoom.v:33464 No timescale set for "PeripheryBus_1".
 
-[WARNI:PA0205] SmallBoom.v:32470 No timescale set for "LevelGateway".
+[WARNI:PA0205] SmallBoom.v:34643 No timescale set for "LevelGateway".
 
-[WARNI:PA0205] SmallBoom.v:32501 No timescale set for "PLICFanIn".
+[WARNI:PA0205] SmallBoom.v:34680 No timescale set for "PLICFanIn".
 
-[WARNI:PA0205] SmallBoom.v:32529 No timescale set for "Queue_77".
+[WARNI:PA0205] SmallBoom.v:34708 No timescale set for "Queue_77".
 
-[WARNI:PA0205] SmallBoom.v:32661 No timescale set for "TLPLIC".
+[WARNI:PA0205] SmallBoom.v:34846 No timescale set for "TLPLIC".
 
-[WARNI:PA0205] SmallBoom.v:33197 No timescale set for "CLINT".
+[WARNI:PA0205] SmallBoom.v:35412 No timescale set for "CLINT".
 
-[WARNI:PA0205] SmallBoom.v:33564 No timescale set for "DMIToTL".
+[WARNI:PA0205] SmallBoom.v:35785 No timescale set for "DMIToTL".
 
-[WARNI:PA0205] SmallBoom.v:33611 No timescale set for "TLXbar_7".
+[WARNI:PA0205] SmallBoom.v:35832 No timescale set for "TLXbar_7".
 
-[WARNI:PA0205] SmallBoom.v:33936 No timescale set for "AsyncResetRegVec_w32_i0".
+[WARNI:PA0205] SmallBoom.v:36181 No timescale set for "AsyncResetRegVec_w32_i0".
 
-[WARNI:PA0205] SmallBoom.v:34464 No timescale set for "AsyncResetRegVec_w1_i0".
+[WARNI:PA0205] SmallBoom.v:36709 No timescale set for "AsyncResetRegVec_w1_i0".
 
-[WARNI:PA0205] SmallBoom.v:34489 No timescale set for "TLDebugModuleOuter".
+[WARNI:PA0205] SmallBoom.v:36734 No timescale set for "TLDebugModuleOuter".
 
-[WARNI:PA0205] SmallBoom.v:34691 No timescale set for "IntSyncCrossingSource".
+[WARNI:PA0205] SmallBoom.v:36936 No timescale set for "IntSyncCrossingSource".
 
-[WARNI:PA0205] SmallBoom.v:34697 No timescale set for "AsyncResetSynchronizerShiftReg_w1_d3_i0".
+[WARNI:PA0205] SmallBoom.v:36942 No timescale set for "AsyncResetSynchronizerShiftReg_w1_d3_i0".
 
-[WARNI:PA0205] SmallBoom.v:34753 No timescale set for "AsyncResetSynchronizerShiftReg_w1_d4_i0".
+[WARNI:PA0205] SmallBoom.v:36998 No timescale set for "AsyncResetSynchronizerShiftReg_w1_d4_i0".
 
-[WARNI:PA0205] SmallBoom.v:34825 No timescale set for "AsyncValidSync".
+[WARNI:PA0205] SmallBoom.v:37070 No timescale set for "AsyncValidSync".
 
-[WARNI:PA0205] SmallBoom.v:34845 No timescale set for "AsyncResetSynchronizerShiftReg_w1_d1_i0".
+[WARNI:PA0205] SmallBoom.v:37090 No timescale set for "AsyncResetSynchronizerShiftReg_w1_d1_i0".
 
-[WARNI:PA0205] SmallBoom.v:34869 No timescale set for "AsyncValidSync_1".
+[WARNI:PA0205] SmallBoom.v:37114 No timescale set for "AsyncValidSync_1".
 
-[WARNI:PA0205] SmallBoom.v:34890 No timescale set for "AsyncValidSync_2".
+[WARNI:PA0205] SmallBoom.v:37135 No timescale set for "AsyncValidSync_2".
 
-[WARNI:PA0205] SmallBoom.v:34911 No timescale set for "AsyncQueueSource".
+[WARNI:PA0205] SmallBoom.v:37156 No timescale set for "AsyncQueueSource".
 
-[WARNI:PA0205] SmallBoom.v:35081 No timescale set for "SynchronizerShiftReg_w43_d1".
+[WARNI:PA0205] SmallBoom.v:37332 No timescale set for "SynchronizerShiftReg_w43_d1".
 
-[WARNI:PA0205] SmallBoom.v:35095 No timescale set for "AsyncQueueSink".
+[WARNI:PA0205] SmallBoom.v:37352 No timescale set for "AsyncQueueSink".
 
-[WARNI:PA0205] SmallBoom.v:35297 No timescale set for "TLAsyncCrossingSource".
+[WARNI:PA0205] SmallBoom.v:37554 No timescale set for "TLAsyncCrossingSource".
 
-[WARNI:PA0205] SmallBoom.v:35462 No timescale set for "AsyncQueueSource_1".
+[WARNI:PA0205] SmallBoom.v:37719 No timescale set for "AsyncQueueSource_1".
 
-[WARNI:PA0205] SmallBoom.v:35624 No timescale set for "TLDebugModuleOuterAsync".
+[WARNI:PA0205] SmallBoom.v:37887 No timescale set for "TLDebugModuleOuterAsync".
 
-[WARNI:PA0205] SmallBoom.v:36041 No timescale set for "TLDebugModuleInner".
+[WARNI:PA0205] SmallBoom.v:38304 No timescale set for "TLDebugModuleInner".
 
-[WARNI:PA0205] SmallBoom.v:42940 No timescale set for "SynchronizerShiftReg_w55_d1".
+[WARNI:PA0205] SmallBoom.v:45233 No timescale set for "SynchronizerShiftReg_w55_d1".
 
-[WARNI:PA0205] SmallBoom.v:42954 No timescale set for "AsyncQueueSink_1".
+[WARNI:PA0205] SmallBoom.v:45253 No timescale set for "AsyncQueueSink_1".
 
-[WARNI:PA0205] SmallBoom.v:43156 No timescale set for "AsyncQueueSource_2".
+[WARNI:PA0205] SmallBoom.v:45455 No timescale set for "AsyncQueueSource_2".
 
-[WARNI:PA0205] SmallBoom.v:43326 No timescale set for "TLAsyncCrossingSink".
+[WARNI:PA0205] SmallBoom.v:45631 No timescale set for "TLAsyncCrossingSink".
 
-[WARNI:PA0205] SmallBoom.v:43487 No timescale set for "ResetCatchAndSync_d3".
+[WARNI:PA0205] SmallBoom.v:45792 No timescale set for "ResetCatchAndSync_d3".
 
-[WARNI:PA0205] SmallBoom.v:43509 No timescale set for "SynchronizerShiftReg_w14_d1".
+[WARNI:PA0205] SmallBoom.v:45814 No timescale set for "SynchronizerShiftReg_w14_d1".
 
-[WARNI:PA0205] SmallBoom.v:43523 No timescale set for "AsyncQueueSink_2".
+[WARNI:PA0205] SmallBoom.v:45834 No timescale set for "AsyncQueueSink_2".
 
-[WARNI:PA0205] SmallBoom.v:43709 No timescale set for "TLDebugModuleInnerAsync".
+[WARNI:PA0205] SmallBoom.v:46020 No timescale set for "TLDebugModuleInnerAsync".
 
-[WARNI:PA0205] SmallBoom.v:44039 No timescale set for "TLDebugModule".
+[WARNI:PA0205] SmallBoom.v:46356 No timescale set for "TLDebugModule".
 
-[WARNI:PA0205] SmallBoom.v:44314 No timescale set for "TLXbar_8".
+[WARNI:PA0205] SmallBoom.v:46631 No timescale set for "TLXbar_8".
 
-[WARNI:PA0205] SmallBoom.v:44644 No timescale set for "IntXbar_4".
+[WARNI:PA0205] SmallBoom.v:46985 No timescale set for "IntXbar_4".
 
-[WARNI:PA0205] SmallBoom.v:44662 No timescale set for "WritebackUnit".
+[WARNI:PA0205] SmallBoom.v:47003 No timescale set for "WritebackUnit".
 
-[WARNI:PA0205] SmallBoom.v:44844 No timescale set for "ProbeUnit".
+[WARNI:PA0205] SmallBoom.v:47191 No timescale set for "ProbeUnit".
 
-[WARNI:PA0205] SmallBoom.v:45112 No timescale set for "Arbiter".
+[WARNI:PA0205] SmallBoom.v:47471 No timescale set for "Arbiter".
 
-[WARNI:PA0205] SmallBoom.v:45132 No timescale set for "Arbiter_1".
+[WARNI:PA0205] SmallBoom.v:47491 No timescale set for "Arbiter_1".
 
-[WARNI:PA0205] SmallBoom.v:45164 No timescale set for "Arbiter_2".
+[WARNI:PA0205] SmallBoom.v:47523 No timescale set for "Arbiter_2".
 
-[WARNI:PA0205] SmallBoom.v:45204 No timescale set for "Arbiter_3".
+[WARNI:PA0205] SmallBoom.v:47563 No timescale set for "Arbiter_3".
 
-[WARNI:PA0205] SmallBoom.v:45240 No timescale set for "Arbiter_4".
+[WARNI:PA0205] SmallBoom.v:47599 No timescale set for "Arbiter_4".
 
-[WARNI:PA0205] SmallBoom.v:45251 No timescale set for "Queue_78".
+[WARNI:PA0205] SmallBoom.v:47610 No timescale set for "Queue_78".
 
-[WARNI:PA0205] SmallBoom.v:45411 No timescale set for "Queue_79".
+[WARNI:PA0205] SmallBoom.v:47776 No timescale set for "Queue_79".
 
-[WARNI:PA0205] SmallBoom.v:45463 No timescale set for "MSHR".
+[WARNI:PA0205] SmallBoom.v:47834 No timescale set for "MSHR".
 
-[WARNI:PA0205] SmallBoom.v:46459 No timescale set for "MSHR_1".
+[WARNI:PA0205] SmallBoom.v:48836 No timescale set for "MSHR_1".
 
-[WARNI:PA0205] SmallBoom.v:47455 No timescale set for "Arbiter_5".
+[WARNI:PA0205] SmallBoom.v:49838 No timescale set for "Arbiter_5".
 
-[WARNI:PA0205] SmallBoom.v:47461 No timescale set for "Arbiter_6".
+[WARNI:PA0205] SmallBoom.v:49844 No timescale set for "Arbiter_6".
 
-[WARNI:PA0205] SmallBoom.v:47491 No timescale set for "IOMSHR".
+[WARNI:PA0205] SmallBoom.v:49874 No timescale set for "IOMSHR".
 
-[WARNI:PA0205] SmallBoom.v:48001 No timescale set for "MSHRFile".
+[WARNI:PA0205] SmallBoom.v:50396 No timescale set for "MSHRFile".
 
-[WARNI:PA0205] SmallBoom.v:49371 No timescale set for "packageanon2".
+[WARNI:PA0205] SmallBoom.v:51797 No timescale set for "packageanon2".
 
-[WARNI:PA0205] SmallBoom.v:49413 No timescale set for "PMPChecker".
+[WARNI:PA0205] SmallBoom.v:51839 No timescale set for "PMPChecker".
 
-[WARNI:PA0205] SmallBoom.v:50371 No timescale set for "TLB".
+[WARNI:PA0205] SmallBoom.v:52797 No timescale set for "TLB".
 
-[WARNI:PA0205] SmallBoom.v:54673 No timescale set for "L1MetadataArray".
+[WARNI:PA0205] SmallBoom.v:57111 No timescale set for "L1MetadataArray".
 
-[WARNI:PA0205] SmallBoom.v:54834 No timescale set for "Arbiter_7".
+[WARNI:PA0205] SmallBoom.v:57278 No timescale set for "Arbiter_7".
 
-[WARNI:PA0205] SmallBoom.v:54874 No timescale set for "DataArray".
+[WARNI:PA0205] SmallBoom.v:57318 No timescale set for "DataArray".
 
-[WARNI:PA0205] SmallBoom.v:55019 No timescale set for "Arbiter_9".
+[WARNI:PA0205] SmallBoom.v:57469 No timescale set for "Arbiter_9".
 
-[WARNI:PA0205] SmallBoom.v:55054 No timescale set for "Arbiter_10".
+[WARNI:PA0205] SmallBoom.v:57504 No timescale set for "Arbiter_10".
 
-[WARNI:PA0205] SmallBoom.v:55079 No timescale set for "AMOALU".
+[WARNI:PA0205] SmallBoom.v:57529 No timescale set for "AMOALU".
 
-[WARNI:PA0205] SmallBoom.v:55230 No timescale set for "BoomNonBlockingDCache".
+[WARNI:PA0205] SmallBoom.v:57680 No timescale set for "BoomNonBlockingDCache".
 
-[WARNI:PA0205] SmallBoom.v:57676 No timescale set for "ICache".
+[WARNI:PA0205] SmallBoom.v:60150 No timescale set for "ICache".
 
-[WARNI:PA0205] SmallBoom.v:58326 No timescale set for "TLB_1".
+[WARNI:PA0205] SmallBoom.v:60812 No timescale set for "TLB_1".
 
-[WARNI:PA0205] SmallBoom.v:67381 No timescale set for "BranchChecker".
+[WARNI:PA0205] SmallBoom.v:69879 No timescale set for "BranchChecker".
 
-[WARNI:PA0205] SmallBoom.v:67606 No timescale set for "FetchTargetQueue".
+[WARNI:PA0205] SmallBoom.v:70110 No timescale set for "FetchTargetQueue".
 
-[WARNI:PA0205] SmallBoom.v:68704 No timescale set for "FetchBuffer".
+[WARNI:PA0205] SmallBoom.v:71226 No timescale set for "FetchBuffer".
 
-[WARNI:PA0205] SmallBoom.v:73100 No timescale set for "RVCExpander".
+[WARNI:PA0205] SmallBoom.v:75688 No timescale set for "RVCExpander".
 
-[WARNI:PA0205] SmallBoom.v:73542 No timescale set for "BranchDecode".
+[WARNI:PA0205] SmallBoom.v:76130 No timescale set for "BranchDecode".
 
-[WARNI:PA0205] SmallBoom.v:73639 No timescale set for "FetchMonitor".
+[WARNI:PA0205] SmallBoom.v:76227 No timescale set for "FetchMonitor".
 
-[WARNI:PA0205] SmallBoom.v:73940 No timescale set for "ElasticReg".
+[WARNI:PA0205] SmallBoom.v:76567 No timescale set for "ElasticReg".
 
-[WARNI:PA0205] SmallBoom.v:74103 No timescale set for "ElasticReg_1".
+[WARNI:PA0205] SmallBoom.v:76736 No timescale set for "ElasticReg_1".
 
-[WARNI:PA0205] SmallBoom.v:74334 No timescale set for "FetchControlUnit".
+[WARNI:PA0205] SmallBoom.v:76973 No timescale set for "FetchControlUnit".
 
-[WARNI:PA0205] SmallBoom.v:76770 No timescale set for "Queue_82".
+[WARNI:PA0205] SmallBoom.v:79517 No timescale set for "Queue_82".
 
-[WARNI:PA0205] SmallBoom.v:76930 No timescale set for "Queue_83".
+[WARNI:PA0205] SmallBoom.v:79683 No timescale set for "Queue_83".
 
-[WARNI:PA0205] SmallBoom.v:77050 No timescale set for "BimodalTable".
+[WARNI:PA0205] SmallBoom.v:79809 No timescale set for "BimodalTable".
 
-[WARNI:PA0205] SmallBoom.v:78129 No timescale set for "BTBsa".
+[WARNI:PA0205] SmallBoom.v:80906 No timescale set for "BTBsa".
 
-[WARNI:PA0205] SmallBoom.v:79039 No timescale set for "ElasticReg_2".
+[WARNI:PA0205] SmallBoom.v:81822 No timescale set for "ElasticReg_2".
 
-[WARNI:PA0205] SmallBoom.v:79115 No timescale set for "ElasticReg_3".
+[WARNI:PA0205] SmallBoom.v:81904 No timescale set for "ElasticReg_3".
 
-[WARNI:PA0205] SmallBoom.v:79208 No timescale set for "GShareBrPredictor".
+[WARNI:PA0205] SmallBoom.v:82003 No timescale set for "GShareBrPredictor".
 
-[WARNI:PA0205] SmallBoom.v:79630 No timescale set for "BranchPredictionStage".
+[WARNI:PA0205] SmallBoom.v:82455 No timescale set for "BranchPredictionStage".
 
-[WARNI:PA0205] SmallBoom.v:79895 No timescale set for "BoomFrontend".
+[WARNI:PA0205] SmallBoom.v:82732 No timescale set for "BoomFrontend".
 
-[WARNI:PA0205] SmallBoom.v:81032 No timescale set for "Queue_86".
+[WARNI:PA0205] SmallBoom.v:83875 No timescale set for "Queue_86".
 
-[WARNI:PA0205] SmallBoom.v:81252 No timescale set for "Queue_87".
+[WARNI:PA0205] SmallBoom.v:84101 No timescale set for "Queue_87".
 
-[WARNI:PA0205] SmallBoom.v:81452 No timescale set for "Queue_88".
+[WARNI:PA0205] SmallBoom.v:84307 No timescale set for "Queue_88".
 
-[WARNI:PA0205] SmallBoom.v:81590 No timescale set for "Queue_89".
+[WARNI:PA0205] SmallBoom.v:84451 No timescale set for "Queue_89".
 
-[WARNI:PA0205] SmallBoom.v:81750 No timescale set for "Queue_90".
+[WARNI:PA0205] SmallBoom.v:84617 No timescale set for "Queue_90".
 
-[WARNI:PA0205] SmallBoom.v:81827 No timescale set for "TLBuffer_11".
+[WARNI:PA0205] SmallBoom.v:84700 No timescale set for "TLBuffer_11".
 
-[WARNI:PA0205] SmallBoom.v:82140 No timescale set for "SynchronizerShiftReg_w1_d3".
+[WARNI:PA0205] SmallBoom.v:85013 No timescale set for "SynchronizerShiftReg_w1_d3".
 
-[WARNI:PA0205] SmallBoom.v:82160 No timescale set for "IntSyncCrossingSink".
+[WARNI:PA0205] SmallBoom.v:85039 No timescale set for "IntSyncCrossingSink".
 
-[WARNI:PA0205] SmallBoom.v:82177 No timescale set for "IntSyncCrossingSink_1".
+[WARNI:PA0205] SmallBoom.v:85056 No timescale set for "IntSyncCrossingSink_1".
 
-[WARNI:PA0205] SmallBoom.v:82186 No timescale set for "IntSyncCrossingSink_2".
+[WARNI:PA0205] SmallBoom.v:85065 No timescale set for "IntSyncCrossingSink_2".
 
-[WARNI:PA0205] SmallBoom.v:82192 No timescale set for "HellaCacheArbiter".
+[WARNI:PA0205] SmallBoom.v:85071 No timescale set for "HellaCacheArbiter".
 
-[WARNI:PA0205] SmallBoom.v:82289 No timescale set for "RRArbiter".
+[WARNI:PA0205] SmallBoom.v:85174 No timescale set for "RRArbiter".
 
-[WARNI:PA0205] SmallBoom.v:82361 No timescale set for "packageanon2_60".
+[WARNI:PA0205] SmallBoom.v:85252 No timescale set for "packageanon2_60".
 
-[WARNI:PA0205] SmallBoom.v:82367 No timescale set for "packageanon2_61".
+[WARNI:PA0205] SmallBoom.v:85258 No timescale set for "packageanon2_61".
 
-[WARNI:PA0205] SmallBoom.v:82397 No timescale set for "PTW".
+[WARNI:PA0205] SmallBoom.v:85288 No timescale set for "PTW".
 
-[WARNI:PA0205] SmallBoom.v:85035 No timescale set for "MemAddrCalcUnit".
+[WARNI:PA0205] SmallBoom.v:87950 No timescale set for "MemAddrCalcUnit".
 
-[WARNI:PA0205] SmallBoom.v:85282 No timescale set for "ALUExeUnit".
+[WARNI:PA0205] SmallBoom.v:88221 No timescale set for "ALUExeUnit".
 
-[WARNI:PA0205] SmallBoom.v:85771 No timescale set for "ALU".
+[WARNI:PA0205] SmallBoom.v:88716 No timescale set for "ALU".
 
-[WARNI:PA0205] SmallBoom.v:86068 No timescale set for "ALUUnit".
+[WARNI:PA0205] SmallBoom.v:89013 No timescale set for "ALUUnit".
 
-[WARNI:PA0205] SmallBoom.v:88062 No timescale set for "PipelinedMultiplier".
+[WARNI:PA0205] SmallBoom.v:91031 No timescale set for "PipelinedMultiplier".
 
-[WARNI:PA0205] SmallBoom.v:88178 No timescale set for "PipelinedMulUnit".
+[WARNI:PA0205] SmallBoom.v:91153 No timescale set for "PipelinedMulUnit".
 
-[WARNI:PA0205] SmallBoom.v:89394 No timescale set for "UOPCodeFPUDecoder".
+[WARNI:PA0205] SmallBoom.v:92375 No timescale set for "UOPCodeFPUDecoder".
 
-[WARNI:PA0205] SmallBoom.v:89558 No timescale set for "RoundAnyRawFNToRecFN".
+[WARNI:PA0205] SmallBoom.v:92539 No timescale set for "RoundAnyRawFNToRecFN".
 
-[WARNI:PA0205] SmallBoom.v:89682 No timescale set for "INToRecFN".
+[WARNI:PA0205] SmallBoom.v:92663 No timescale set for "INToRecFN".
 
-[WARNI:PA0205] SmallBoom.v:90071 No timescale set for "RoundAnyRawFNToRecFN_1".
+[WARNI:PA0205] SmallBoom.v:93052 No timescale set for "RoundAnyRawFNToRecFN_1".
 
-[WARNI:PA0205] SmallBoom.v:90195 No timescale set for "INToRecFN_1".
+[WARNI:PA0205] SmallBoom.v:93176 No timescale set for "INToRecFN_1".
 
-[WARNI:PA0205] SmallBoom.v:90584 No timescale set for "IntToFP".
+[WARNI:PA0205] SmallBoom.v:93565 No timescale set for "IntToFP".
 
-[WARNI:PA0205] SmallBoom.v:91422 No timescale set for "IntToFPUnit".
+[WARNI:PA0205] SmallBoom.v:94409 No timescale set for "IntToFPUnit".
 
-[WARNI:PA0205] SmallBoom.v:91746 No timescale set for "BranchKillableQueue".
+[WARNI:PA0205] SmallBoom.v:94751 No timescale set for "BranchKillableQueue".
 
-[WARNI:PA0205] SmallBoom.v:92332 No timescale set for "MulDiv".
+[WARNI:PA0205] SmallBoom.v:95353 No timescale set for "MulDiv".
 
-[WARNI:PA0205] SmallBoom.v:93424 No timescale set for "DivUnit".
+[WARNI:PA0205] SmallBoom.v:96451 No timescale set for "DivUnit".
 
-[WARNI:PA0205] SmallBoom.v:94240 No timescale set for "ALUExeUnit_1".
+[WARNI:PA0205] SmallBoom.v:97273 No timescale set for "ALUExeUnit_1".
 
-[WARNI:PA0205] SmallBoom.v:96401 No timescale set for "MulAddRecFNToRaw_preMul".
+[WARNI:PA0205] SmallBoom.v:99446 No timescale set for "MulAddRecFNToRaw_preMul".
 
-[WARNI:PA0205] SmallBoom.v:96766 No timescale set for "MulAddRecFNToRaw_postMul".
+[WARNI:PA0205] SmallBoom.v:99811 No timescale set for "MulAddRecFNToRaw_postMul".
 
-[WARNI:PA0205] SmallBoom.v:97855 No timescale set for "RoundAnyRawFNToRecFN_2".
+[WARNI:PA0205] SmallBoom.v:100900 No timescale set for "RoundAnyRawFNToRecFN_2".
 
-[WARNI:PA0205] SmallBoom.v:98360 No timescale set for "RoundRawFNToRecFN".
+[WARNI:PA0205] SmallBoom.v:101405 No timescale set for "RoundRawFNToRecFN".
 
-[WARNI:PA0205] SmallBoom.v:98405 No timescale set for "MulAddRecFNPipe".
+[WARNI:PA0205] SmallBoom.v:101450 No timescale set for "MulAddRecFNPipe".
 
-[WARNI:PA0205] SmallBoom.v:98731 No timescale set for "FPUFMAPipe".
+[WARNI:PA0205] SmallBoom.v:101782 No timescale set for "FPUFMAPipe".
 
-[WARNI:PA0205] SmallBoom.v:98861 No timescale set for "FMADecoder".
+[WARNI:PA0205] SmallBoom.v:101918 No timescale set for "FMADecoder".
 
-[WARNI:PA0205] SmallBoom.v:98903 No timescale set for "MulAddRecFNToRaw_preMul_1".
+[WARNI:PA0205] SmallBoom.v:101960 No timescale set for "MulAddRecFNToRaw_preMul_1".
 
-[WARNI:PA0205] SmallBoom.v:99200 No timescale set for "MulAddRecFNToRaw_postMul_1".
+[WARNI:PA0205] SmallBoom.v:102257 No timescale set for "MulAddRecFNToRaw_postMul_1".
 
-[WARNI:PA0205] SmallBoom.v:99861 No timescale set for "RoundAnyRawFNToRecFN_3".
+[WARNI:PA0205] SmallBoom.v:102918 No timescale set for "RoundAnyRawFNToRecFN_3".
 
-[WARNI:PA0205] SmallBoom.v:100270 No timescale set for "RoundRawFNToRecFN_1".
+[WARNI:PA0205] SmallBoom.v:103327 No timescale set for "RoundRawFNToRecFN_1".
 
-[WARNI:PA0205] SmallBoom.v:100315 No timescale set for "MulAddRecFNPipe_1".
+[WARNI:PA0205] SmallBoom.v:103372 No timescale set for "MulAddRecFNPipe_1".
 
-[WARNI:PA0205] SmallBoom.v:100641 No timescale set for "FPUFMAPipe_1".
+[WARNI:PA0205] SmallBoom.v:103704 No timescale set for "FPUFMAPipe_1".
 
-[WARNI:PA0205] SmallBoom.v:100761 No timescale set for "CompareRecFN".
+[WARNI:PA0205] SmallBoom.v:103830 No timescale set for "CompareRecFN".
 
-[WARNI:PA0205] SmallBoom.v:100907 No timescale set for "RecFNToIN".
+[WARNI:PA0205] SmallBoom.v:103976 No timescale set for "RecFNToIN".
 
-[WARNI:PA0205] SmallBoom.v:101127 No timescale set for "RecFNToIN_1".
+[WARNI:PA0205] SmallBoom.v:104196 No timescale set for "RecFNToIN_1".
 
-[WARNI:PA0205] SmallBoom.v:101317 No timescale set for "FPToInt".
+[WARNI:PA0205] SmallBoom.v:104386 No timescale set for "FPToInt".
 
-[WARNI:PA0205] SmallBoom.v:101821 No timescale set for "RoundAnyRawFNToRecFN_4".
+[WARNI:PA0205] SmallBoom.v:104896 No timescale set for "RoundAnyRawFNToRecFN_4".
 
-[WARNI:PA0205] SmallBoom.v:102218 No timescale set for "RecFNToRecFN".
+[WARNI:PA0205] SmallBoom.v:105293 No timescale set for "RecFNToRecFN".
 
-[WARNI:PA0205] SmallBoom.v:102292 No timescale set for "FPToFP".
+[WARNI:PA0205] SmallBoom.v:105367 No timescale set for "FPToFP".
 
-[WARNI:PA0205] SmallBoom.v:102610 No timescale set for "FPU".
+[WARNI:PA0205] SmallBoom.v:105691 No timescale set for "FPU".
 
-[WARNI:PA0205] SmallBoom.v:103104 No timescale set for "FPUUnit".
+[WARNI:PA0205] SmallBoom.v:106191 No timescale set for "FPUUnit".
 
-[WARNI:PA0205] SmallBoom.v:104605 No timescale set for "UOPCodeFDivDecoder".
+[WARNI:PA0205] SmallBoom.v:107698 No timescale set for "UOPCodeFDivDecoder".
 
-[WARNI:PA0205] SmallBoom.v:104633 No timescale set for "RoundAnyRawFNToRecFN_5".
+[WARNI:PA0205] SmallBoom.v:107726 No timescale set for "RoundAnyRawFNToRecFN_5".
 
-[WARNI:PA0205] SmallBoom.v:104698 No timescale set for "RecFNToRecFN_1".
+[WARNI:PA0205] SmallBoom.v:107791 No timescale set for "RecFNToRecFN_1".
 
-[WARNI:PA0205] SmallBoom.v:104760 No timescale set for "DivSqrtRecF64ToRaw_mulAddZ31".
+[WARNI:PA0205] SmallBoom.v:107853 No timescale set for "DivSqrtRecF64ToRaw_mulAddZ31".
 
-[WARNI:PA0205] SmallBoom.v:106507 No timescale set for "RoundAnyRawFNToRecFN_7".
+[WARNI:PA0205] SmallBoom.v:109606 No timescale set for "RoundAnyRawFNToRecFN_7".
 
-[WARNI:PA0205] SmallBoom.v:106959 No timescale set for "RoundRawFNToRecFN_2".
+[WARNI:PA0205] SmallBoom.v:110058 No timescale set for "RoundRawFNToRecFN_2".
 
-[WARNI:PA0205] SmallBoom.v:107008 No timescale set for "DivSqrtRecF64_mulAddZ31".
+[WARNI:PA0205] SmallBoom.v:110107 No timescale set for "DivSqrtRecF64_mulAddZ31".
 
-[WARNI:PA0205] SmallBoom.v:107140 No timescale set for "Mul54".
+[WARNI:PA0205] SmallBoom.v:110239 No timescale set for "Mul54".
 
-[WARNI:PA0205] SmallBoom.v:107197 No timescale set for "DivSqrtRecF64".
+[WARNI:PA0205] SmallBoom.v:110302 No timescale set for "DivSqrtRecF64".
 
-[WARNI:PA0205] SmallBoom.v:107294 No timescale set for "FDivSqrtUnit".
+[WARNI:PA0205] SmallBoom.v:110399 No timescale set for "FDivSqrtUnit".
 
-[WARNI:PA0205] SmallBoom.v:109293 No timescale set for "BranchKillableQueue_1".
+[WARNI:PA0205] SmallBoom.v:112422 No timescale set for "BranchKillableQueue_1".
 
-[WARNI:PA0205] SmallBoom.v:109956 No timescale set for "FPUExeUnit".
+[WARNI:PA0205] SmallBoom.v:113100 No timescale set for "FPUExeUnit".
 
-[WARNI:PA0205] SmallBoom.v:111431 No timescale set for "IssueSlot".
+[WARNI:PA0205] SmallBoom.v:114581 No timescale set for "IssueSlot".
 
-[WARNI:PA0205] SmallBoom.v:112835 No timescale set for "IssueUnitCollapsing".
+[WARNI:PA0205] SmallBoom.v:115997 No timescale set for "IssueUnitCollapsing".
 
-[WARNI:PA0205] SmallBoom.v:116786 No timescale set for "RegisterFileSynthesizable".
+[WARNI:PA0205] SmallBoom.v:119960 No timescale set for "RegisterFileSynthesizable".
 
-[WARNI:PA0205] SmallBoom.v:116892 No timescale set for "RegisterReadDecode".
+[WARNI:PA0205] SmallBoom.v:120081 No timescale set for "RegisterReadDecode".
 
-[WARNI:PA0205] SmallBoom.v:117387 No timescale set for "RegisterRead".
+[WARNI:PA0205] SmallBoom.v:120576 No timescale set for "RegisterRead".
 
-[WARNI:PA0205] SmallBoom.v:119024 No timescale set for "Arbiter_12".
+[WARNI:PA0205] SmallBoom.v:122219 No timescale set for "Arbiter_12".
 
-[WARNI:PA0205] SmallBoom.v:119066 No timescale set for "FpPipeline".
+[WARNI:PA0205] SmallBoom.v:122261 No timescale set for "FpPipeline".
 
-[WARNI:PA0205] SmallBoom.v:121349 No timescale set for "DecodeUnit".
+[WARNI:PA0205] SmallBoom.v:124592 No timescale set for "DecodeUnit".
 
-[WARNI:PA0205] SmallBoom.v:123108 No timescale set for "BranchMaskGenerationLogic".
+[WARNI:PA0205] SmallBoom.v:126351 No timescale set for "BranchMaskGenerationLogic".
 
-[WARNI:PA0205] SmallBoom.v:123195 No timescale set for "RenameMapTableElement_1".
+[WARNI:PA0205] SmallBoom.v:126444 No timescale set for "RenameMapTableElement_1".
 
-[WARNI:PA0205] SmallBoom.v:123248 No timescale set for "RenameMapTable".
+[WARNI:PA0205] SmallBoom.v:126503 No timescale set for "RenameMapTable".
 
-[WARNI:PA0205] SmallBoom.v:125963 No timescale set for "RenameFreeListHelper".
+[WARNI:PA0205] SmallBoom.v:129626 No timescale set for "RenameFreeListHelper".
 
-[WARNI:PA0205] SmallBoom.v:126706 No timescale set for "RenameFreeList".
+[WARNI:PA0205] SmallBoom.v:130375 No timescale set for "RenameFreeList".
 
-[WARNI:PA0205] SmallBoom.v:127027 No timescale set for "BusyTableHelper".
+[WARNI:PA0205] SmallBoom.v:130702 No timescale set for "BusyTableHelper".
 
-[WARNI:PA0205] SmallBoom.v:131262 No timescale set for "BusyTable".
+[WARNI:PA0205] SmallBoom.v:134943 No timescale set for "BusyTable".
 
-[WARNI:PA0205] SmallBoom.v:131339 No timescale set for "RenameMapTable_1".
+[WARNI:PA0205] SmallBoom.v:135020 No timescale set for "RenameMapTable_1".
 
-[WARNI:PA0205] SmallBoom.v:134080 No timescale set for "RenameFreeList_1".
+[WARNI:PA0205] SmallBoom.v:138145 No timescale set for "RenameFreeList_1".
 
-[WARNI:PA0205] SmallBoom.v:134390 No timescale set for "BusyTableHelper_1".
+[WARNI:PA0205] SmallBoom.v:138461 No timescale set for "BusyTableHelper_1".
 
-[WARNI:PA0205] SmallBoom.v:136992 No timescale set for "BusyTable_1".
+[WARNI:PA0205] SmallBoom.v:141069 No timescale set for "BusyTable_1".
 
-[WARNI:PA0205] SmallBoom.v:137072 No timescale set for "RenameStage".
+[WARNI:PA0205] SmallBoom.v:141149 No timescale set for "RenameStage".
 
-[WARNI:PA0205] SmallBoom.v:138546 No timescale set for "IssueSlot_4".
+[WARNI:PA0205] SmallBoom.v:142665 No timescale set for "IssueSlot_4".
 
-[WARNI:PA0205] SmallBoom.v:140180 No timescale set for "IssueUnitCollapsing_1".
+[WARNI:PA0205] SmallBoom.v:144341 No timescale set for "IssueUnitCollapsing_1".
 
-[WARNI:PA0205] SmallBoom.v:143435 No timescale set for "IssueUnitCollapsing_2".
+[WARNI:PA0205] SmallBoom.v:147614 No timescale set for "IssueUnitCollapsing_2".
 
-[WARNI:PA0205] SmallBoom.v:147635 No timescale set for "RegisterFileSynthesizable_1".
+[WARNI:PA0205] SmallBoom.v:151832 No timescale set for "RegisterFileSynthesizable_1".
 
-[WARNI:PA0205] SmallBoom.v:147830 No timescale set for "Arbiter_13".
+[WARNI:PA0205] SmallBoom.v:152043 No timescale set for "Arbiter_13".
 
-[WARNI:PA0205] SmallBoom.v:147876 No timescale set for "RegisterReadDecode_1".
+[WARNI:PA0205] SmallBoom.v:152089 No timescale set for "RegisterReadDecode_1".
 
-[WARNI:PA0205] SmallBoom.v:147958 No timescale set for "RegisterReadDecode_2".
+[WARNI:PA0205] SmallBoom.v:152171 No timescale set for "RegisterReadDecode_2".
 
-[WARNI:PA0205] SmallBoom.v:148685 No timescale set for "RegisterRead_1".
+[WARNI:PA0205] SmallBoom.v:152898 No timescale set for "RegisterRead_1".
 
-[WARNI:PA0205] SmallBoom.v:151001 No timescale set for "LoadReqSlot".
+[WARNI:PA0205] SmallBoom.v:155220 No timescale set for "LoadReqSlot".
 
-[WARNI:PA0205] SmallBoom.v:151228 No timescale set for "DCacheShim".
+[WARNI:PA0205] SmallBoom.v:155453 No timescale set for "DCacheShim".
 
-[WARNI:PA0205] SmallBoom.v:152379 No timescale set for "ForwardingAgeLogic".
+[WARNI:PA0205] SmallBoom.v:156622 No timescale set for "ForwardingAgeLogic".
 
-[WARNI:PA0205] SmallBoom.v:152444 No timescale set for "LoadStoreUnit".
+[WARNI:PA0205] SmallBoom.v:156687 No timescale set for "LoadStoreUnit".
 
-[WARNI:PA0205] SmallBoom.v:164762 No timescale set for "Rob".
+[WARNI:PA0205] SmallBoom.v:169131 No timescale set for "Rob".
 
-[WARNI:PA0205] SmallBoom.v:170465 No timescale set for "CSRFile".
+[WARNI:PA0205] SmallBoom.v:175008 No timescale set for "CSRFile".
 
-[WARNI:PA0205] SmallBoom.v:174594 No timescale set for "BoomCore".
+[WARNI:PA0205] SmallBoom.v:179155 No timescale set for "BoomCore".
 
-[WARNI:PA0205] SmallBoom.v:180493 No timescale set for "BoomTile".
+[WARNI:PA0205] SmallBoom.v:185144 No timescale set for "BoomTile".
 
-[WARNI:PA0205] SmallBoom.v:183252 No timescale set for "AsyncResetRegVec_w2_i0".
+[WARNI:PA0205] SmallBoom.v:187903 No timescale set for "AsyncResetRegVec_w2_i0".
 
-[WARNI:PA0205] SmallBoom.v:183292 No timescale set for "IntSyncCrossingSource_2".
+[WARNI:PA0205] SmallBoom.v:187943 No timescale set for "IntSyncCrossingSource_2".
 
-[WARNI:PA0205] SmallBoom.v:183316 No timescale set for "IntSyncCrossingSource_3".
+[WARNI:PA0205] SmallBoom.v:187967 No timescale set for "IntSyncCrossingSource_3".
 
-[WARNI:PA0205] SmallBoom.v:183340 No timescale set for "SynchronizerShiftReg_w2_d3".
+[WARNI:PA0205] SmallBoom.v:187991 No timescale set for "SynchronizerShiftReg_w2_d3".
 
-[WARNI:PA0205] SmallBoom.v:183360 No timescale set for "IntXing".
+[WARNI:PA0205] SmallBoom.v:188017 No timescale set for "IntXing".
 
-[WARNI:PA0205] SmallBoom.v:183382 No timescale set for "TLROM".
+[WARNI:PA0205] SmallBoom.v:188039 No timescale set for "TLROM".
 
-[WARNI:PA0205] SmallBoom.v:184428 No timescale set for "Queue_91".
+[WARNI:PA0205] SmallBoom.v:189085 No timescale set for "Queue_91".
 
-[WARNI:PA0205] SmallBoom.v:184528 No timescale set for "TLBroadcastTracker".
+[WARNI:PA0205] SmallBoom.v:189191 No timescale set for "TLBroadcastTracker".
 
-[WARNI:PA0205] SmallBoom.v:184764 No timescale set for "TLBroadcastTracker_1".
+[WARNI:PA0205] SmallBoom.v:189457 No timescale set for "TLBroadcastTracker_1".
 
-[WARNI:PA0205] SmallBoom.v:185000 No timescale set for "TLBroadcastTracker_2".
+[WARNI:PA0205] SmallBoom.v:189723 No timescale set for "TLBroadcastTracker_2".
 
-[WARNI:PA0205] SmallBoom.v:185236 No timescale set for "TLBroadcastTracker_3".
+[WARNI:PA0205] SmallBoom.v:189989 No timescale set for "TLBroadcastTracker_3".
 
-[WARNI:PA0205] SmallBoom.v:185472 No timescale set for "TLBroadcast".
+[WARNI:PA0205] SmallBoom.v:190255 No timescale set for "TLBroadcast".
 
-[WARNI:PA0205] SmallBoom.v:186931 No timescale set for "ExampleBoomSystem".
+[WARNI:PA0205] SmallBoom.v:191756 No timescale set for "ExampleBoomSystem".
 
-[WARNI:PA0205] SmallBoom.v:188568 No timescale set for "AXI4RAM".
+[WARNI:PA0205] SmallBoom.v:193399 No timescale set for "AXI4RAM".
 
-[WARNI:PA0205] SmallBoom.v:189065 No timescale set for "Queue_95".
+[WARNI:PA0205] SmallBoom.v:193902 No timescale set for "Queue_95".
 
-[WARNI:PA0205] SmallBoom.v:189185 No timescale set for "Queue_97".
+[WARNI:PA0205] SmallBoom.v:194028 No timescale set for "Queue_97".
 
-[WARNI:PA0205] SmallBoom.v:189305 No timescale set for "Queue_99".
+[WARNI:PA0205] SmallBoom.v:194154 No timescale set for "Queue_99".
 
-[WARNI:PA0205] SmallBoom.v:189464 No timescale set for "AXI4Buffer_1".
+[WARNI:PA0205] SmallBoom.v:194319 No timescale set for "AXI4Buffer_1".
 
-[WARNI:PA0205] SmallBoom.v:189719 No timescale set for "Queue_100".
+[WARNI:PA0205] SmallBoom.v:194574 No timescale set for "Queue_100".
 
-[WARNI:PA0205] SmallBoom.v:189867 No timescale set for "AXI4Fragmenter_1".
+[WARNI:PA0205] SmallBoom.v:194728 No timescale set for "AXI4Fragmenter_1".
 
-[WARNI:PA0205] SmallBoom.v:190696 No timescale set for "SimAXIMem".
+[WARNI:PA0205] SmallBoom.v:195575 No timescale set for "SimAXIMem".
 
-[WARNI:PA0205] SmallBoom.v:191101 No timescale set for "AXI4RAM_1".
+[WARNI:PA0205] SmallBoom.v:195980 No timescale set for "AXI4RAM_1".
 
-[WARNI:PA0205] SmallBoom.v:191524 No timescale set for "Queue_103".
+[WARNI:PA0205] SmallBoom.v:196409 No timescale set for "Queue_103".
 
-[WARNI:PA0205] SmallBoom.v:191644 No timescale set for "AXI4Buffer_2".
+[WARNI:PA0205] SmallBoom.v:196535 No timescale set for "AXI4Buffer_2".
 
-[WARNI:PA0205] SmallBoom.v:191899 No timescale set for "Queue_108".
+[WARNI:PA0205] SmallBoom.v:196790 No timescale set for "Queue_108".
 
-[WARNI:PA0205] SmallBoom.v:192047 No timescale set for "AXI4Fragmenter_2".
+[WARNI:PA0205] SmallBoom.v:196944 No timescale set for "AXI4Fragmenter_2".
 
-[WARNI:PA0205] SmallBoom.v:192876 No timescale set for "SimAXIMem_1".
+[WARNI:PA0205] SmallBoom.v:197791 No timescale set for "SimAXIMem_1".
 
-[WARNI:PA0205] SmallBoom.v:193281 No timescale set for "TestHarness".
+[WARNI:PA0205] SmallBoom.v:198196 No timescale set for "TestHarness".
 
-[WARNI:PA0205] SmallBoom.v:193820 No timescale set for "EICG_wrapper".
+[WARNI:PA0205] SmallBoom.v:198741 No timescale set for "EICG_wrapper".
 
-[WARNI:PA0205] SmallBoom.v:193844 No timescale set for "plusarg_reader".
+[WARNI:PA0205] SmallBoom.v:198765 No timescale set for "plusarg_reader".
 
-[WARNI:PA0205] SmallBoom.v:193861 No timescale set for "SimDTM".
+[WARNI:PA0205] SmallBoom.v:198784 No timescale set for "SimDTM".
 
 [INFO :CP0300] Compilation...
 
-[INFO :CP0303] SmallBoom.v:85771 Compile module "work@ALU".
+[INFO :CP0303] SmallBoom.v:88716 Compile module "work@ALU".
 
-[INFO :CP0303] SmallBoom.v:85282 Compile module "work@ALUExeUnit".
+[INFO :CP0303] SmallBoom.v:88221 Compile module "work@ALUExeUnit".
 
-[INFO :CP0303] SmallBoom.v:94240 Compile module "work@ALUExeUnit_1".
+[INFO :CP0303] SmallBoom.v:97273 Compile module "work@ALUExeUnit_1".
 
-[INFO :CP0303] SmallBoom.v:86068 Compile module "work@ALUUnit".
+[INFO :CP0303] SmallBoom.v:89013 Compile module "work@ALUUnit".
 
-[INFO :CP0303] SmallBoom.v:55079 Compile module "work@AMOALU".
+[INFO :CP0303] SmallBoom.v:57529 Compile module "work@AMOALU".
 
-[INFO :CP0303] SmallBoom.v:2705 Compile module "work@AXI4Buffer".
+[INFO :CP0303] SmallBoom.v:2832 Compile module "work@AXI4Buffer".
 
-[INFO :CP0303] SmallBoom.v:189464 Compile module "work@AXI4Buffer_1".
+[INFO :CP0303] SmallBoom.v:194319 Compile module "work@AXI4Buffer_1".
 
-[INFO :CP0303] SmallBoom.v:191644 Compile module "work@AXI4Buffer_2".
+[INFO :CP0303] SmallBoom.v:196535 Compile module "work@AXI4Buffer_2".
 
-[INFO :CP0303] SmallBoom.v:4090 Compile module "work@AXI4Deinterleaver".
+[INFO :CP0303] SmallBoom.v:4247 Compile module "work@AXI4Deinterleaver".
 
-[INFO :CP0303] SmallBoom.v:12125 Compile module "work@AXI4Fragmenter".
+[INFO :CP0303] SmallBoom.v:12546 Compile module "work@AXI4Fragmenter".
 
-[INFO :CP0303] SmallBoom.v:189867 Compile module "work@AXI4Fragmenter_1".
+[INFO :CP0303] SmallBoom.v:194728 Compile module "work@AXI4Fragmenter_1".
 
-[INFO :CP0303] SmallBoom.v:192047 Compile module "work@AXI4Fragmenter_2".
+[INFO :CP0303] SmallBoom.v:196944 Compile module "work@AXI4Fragmenter_2".
 
-[INFO :CP0303] SmallBoom.v:5190 Compile module "work@AXI4IdIndexer".
+[INFO :CP0303] SmallBoom.v:5425 Compile module "work@AXI4IdIndexer".
 
-[INFO :CP0303] SmallBoom.v:13036 Compile module "work@AXI4IdIndexer_1".
+[INFO :CP0303] SmallBoom.v:13475 Compile module "work@AXI4IdIndexer_1".
 
-[INFO :CP0303] SmallBoom.v:16051 Compile module "work@AXI4IdIndexer_2".
+[INFO :CP0303] SmallBoom.v:16508 Compile module "work@AXI4IdIndexer_2".
 
-[INFO :CP0303] SmallBoom.v:188568 Compile module "work@AXI4RAM".
+[INFO :CP0303] SmallBoom.v:193399 Compile module "work@AXI4RAM".
 
-[INFO :CP0303] SmallBoom.v:191101 Compile module "work@AXI4RAM_1".
+[INFO :CP0303] SmallBoom.v:195980 Compile module "work@AXI4RAM_1".
 
-[INFO :CP0303] SmallBoom.v:10649 Compile module "work@AXI4ToTL".
+[INFO :CP0303] SmallBoom.v:11004 Compile module "work@AXI4ToTL".
 
-[INFO :CP0303] SmallBoom.v:3178 Compile module "work@AXI4UserYanker".
+[INFO :CP0303] SmallBoom.v:3317 Compile module "work@AXI4UserYanker".
 
-[INFO :CP0303] SmallBoom.v:11675 Compile module "work@AXI4UserYanker_1".
+[INFO :CP0303] SmallBoom.v:12078 Compile module "work@AXI4UserYanker_1".
 
-[INFO :CP0303] SmallBoom.v:14619 Compile module "work@AXI4UserYanker_2".
+[INFO :CP0303] SmallBoom.v:15064 Compile module "work@AXI4UserYanker_2".
 
-[INFO :CP0303] SmallBoom.v:45112 Compile module "work@Arbiter".
+[INFO :CP0303] SmallBoom.v:47471 Compile module "work@Arbiter".
 
-[INFO :CP0303] SmallBoom.v:45132 Compile module "work@Arbiter_1".
+[INFO :CP0303] SmallBoom.v:47491 Compile module "work@Arbiter_1".
 
-[INFO :CP0303] SmallBoom.v:55054 Compile module "work@Arbiter_10".
+[INFO :CP0303] SmallBoom.v:57504 Compile module "work@Arbiter_10".
 
-[INFO :CP0303] SmallBoom.v:119024 Compile module "work@Arbiter_12".
+[INFO :CP0303] SmallBoom.v:122219 Compile module "work@Arbiter_12".
 
-[INFO :CP0303] SmallBoom.v:147830 Compile module "work@Arbiter_13".
+[INFO :CP0303] SmallBoom.v:152043 Compile module "work@Arbiter_13".
 
-[INFO :CP0303] SmallBoom.v:45164 Compile module "work@Arbiter_2".
+[INFO :CP0303] SmallBoom.v:47523 Compile module "work@Arbiter_2".
 
-[INFO :CP0303] SmallBoom.v:45204 Compile module "work@Arbiter_3".
+[INFO :CP0303] SmallBoom.v:47563 Compile module "work@Arbiter_3".
 
-[INFO :CP0303] SmallBoom.v:45240 Compile module "work@Arbiter_4".
+[INFO :CP0303] SmallBoom.v:47599 Compile module "work@Arbiter_4".
 
-[INFO :CP0303] SmallBoom.v:47455 Compile module "work@Arbiter_5".
+[INFO :CP0303] SmallBoom.v:49838 Compile module "work@Arbiter_5".
 
-[INFO :CP0303] SmallBoom.v:47461 Compile module "work@Arbiter_6".
+[INFO :CP0303] SmallBoom.v:49844 Compile module "work@Arbiter_6".
 
-[INFO :CP0303] SmallBoom.v:54834 Compile module "work@Arbiter_7".
+[INFO :CP0303] SmallBoom.v:57278 Compile module "work@Arbiter_7".
 
-[INFO :CP0303] SmallBoom.v:55019 Compile module "work@Arbiter_9".
+[INFO :CP0303] SmallBoom.v:57469 Compile module "work@Arbiter_9".
 
-[INFO :CP0303] SmallBoom.v:35095 Compile module "work@AsyncQueueSink".
+[INFO :CP0303] SmallBoom.v:37352 Compile module "work@AsyncQueueSink".
 
-[INFO :CP0303] SmallBoom.v:42954 Compile module "work@AsyncQueueSink_1".
+[INFO :CP0303] SmallBoom.v:45253 Compile module "work@AsyncQueueSink_1".
 
-[INFO :CP0303] SmallBoom.v:43523 Compile module "work@AsyncQueueSink_2".
+[INFO :CP0303] SmallBoom.v:45834 Compile module "work@AsyncQueueSink_2".
 
-[INFO :CP0303] SmallBoom.v:34911 Compile module "work@AsyncQueueSource".
+[INFO :CP0303] SmallBoom.v:37156 Compile module "work@AsyncQueueSource".
 
-[INFO :CP0303] SmallBoom.v:35462 Compile module "work@AsyncQueueSource_1".
+[INFO :CP0303] SmallBoom.v:37719 Compile module "work@AsyncQueueSource_1".
 
-[INFO :CP0303] SmallBoom.v:43156 Compile module "work@AsyncQueueSource_2".
+[INFO :CP0303] SmallBoom.v:45455 Compile module "work@AsyncQueueSource_2".
 
-[INFO :CP0303] SmallBoom.v:28 Compile module "work@AsyncResetReg".
+[INFO :CP0303] SmallBoom.v:32 Compile module "work@AsyncResetReg".
 
-[INFO :CP0303] SmallBoom.v:34464 Compile module "work@AsyncResetRegVec_w1_i0".
+[INFO :CP0303] SmallBoom.v:36709 Compile module "work@AsyncResetRegVec_w1_i0".
 
-[INFO :CP0303] SmallBoom.v:183252 Compile module "work@AsyncResetRegVec_w2_i0".
+[INFO :CP0303] SmallBoom.v:187903 Compile module "work@AsyncResetRegVec_w2_i0".
 
-[INFO :CP0303] SmallBoom.v:33936 Compile module "work@AsyncResetRegVec_w32_i0".
+[INFO :CP0303] SmallBoom.v:36181 Compile module "work@AsyncResetRegVec_w32_i0".
 
-[INFO :CP0303] SmallBoom.v:34845 Compile module "work@AsyncResetSynchronizerShiftReg_w1_d1_i0".
+[INFO :CP0303] SmallBoom.v:37090 Compile module "work@AsyncResetSynchronizerShiftReg_w1_d1_i0".
 
-[INFO :CP0303] SmallBoom.v:34697 Compile module "work@AsyncResetSynchronizerShiftReg_w1_d3_i0".
+[INFO :CP0303] SmallBoom.v:36942 Compile module "work@AsyncResetSynchronizerShiftReg_w1_d3_i0".
 
-[INFO :CP0303] SmallBoom.v:34753 Compile module "work@AsyncResetSynchronizerShiftReg_w1_d4_i0".
+[INFO :CP0303] SmallBoom.v:36998 Compile module "work@AsyncResetSynchronizerShiftReg_w1_d4_i0".
 
-[INFO :CP0303] SmallBoom.v:34825 Compile module "work@AsyncValidSync".
+[INFO :CP0303] SmallBoom.v:37070 Compile module "work@AsyncValidSync".
 
-[INFO :CP0303] SmallBoom.v:34869 Compile module "work@AsyncValidSync_1".
+[INFO :CP0303] SmallBoom.v:37114 Compile module "work@AsyncValidSync_1".
 
-[INFO :CP0303] SmallBoom.v:34890 Compile module "work@AsyncValidSync_2".
+[INFO :CP0303] SmallBoom.v:37135 Compile module "work@AsyncValidSync_2".
 
-[INFO :CP0303] SmallBoom.v:78129 Compile module "work@BTBsa".
+[INFO :CP0303] SmallBoom.v:80906 Compile module "work@BTBsa".
 
-[INFO :CP0303] SmallBoom.v:77050 Compile module "work@BimodalTable".
+[INFO :CP0303] SmallBoom.v:79809 Compile module "work@BimodalTable".
 
-[INFO :CP0303] SmallBoom.v:174594 Compile module "work@BoomCore".
+[INFO :CP0303] SmallBoom.v:179155 Compile module "work@BoomCore".
 
-[INFO :CP0303] SmallBoom.v:79895 Compile module "work@BoomFrontend".
+[INFO :CP0303] SmallBoom.v:82732 Compile module "work@BoomFrontend".
 
-[INFO :CP0303] SmallBoom.v:55230 Compile module "work@BoomNonBlockingDCache".
+[INFO :CP0303] SmallBoom.v:57680 Compile module "work@BoomNonBlockingDCache".
 
-[INFO :CP0303] SmallBoom.v:180493 Compile module "work@BoomTile".
+[INFO :CP0303] SmallBoom.v:185144 Compile module "work@BoomTile".
 
-[INFO :CP0303] SmallBoom.v:67381 Compile module "work@BranchChecker".
+[INFO :CP0303] SmallBoom.v:69879 Compile module "work@BranchChecker".
 
-[INFO :CP0303] SmallBoom.v:73542 Compile module "work@BranchDecode".
+[INFO :CP0303] SmallBoom.v:76130 Compile module "work@BranchDecode".
 
-[INFO :CP0303] SmallBoom.v:91746 Compile module "work@BranchKillableQueue".
+[INFO :CP0303] SmallBoom.v:94751 Compile module "work@BranchKillableQueue".
 
-[INFO :CP0303] SmallBoom.v:109293 Compile module "work@BranchKillableQueue_1".
+[INFO :CP0303] SmallBoom.v:112422 Compile module "work@BranchKillableQueue_1".
 
-[INFO :CP0303] SmallBoom.v:123108 Compile module "work@BranchMaskGenerationLogic".
+[INFO :CP0303] SmallBoom.v:126351 Compile module "work@BranchMaskGenerationLogic".
 
-[INFO :CP0303] SmallBoom.v:79630 Compile module "work@BranchPredictionStage".
+[INFO :CP0303] SmallBoom.v:82455 Compile module "work@BranchPredictionStage".
 
-[INFO :CP0303] SmallBoom.v:131262 Compile module "work@BusyTable".
+[INFO :CP0303] SmallBoom.v:134943 Compile module "work@BusyTable".
 
-[INFO :CP0303] SmallBoom.v:127027 Compile module "work@BusyTableHelper".
+[INFO :CP0303] SmallBoom.v:130702 Compile module "work@BusyTableHelper".
 
-[INFO :CP0303] SmallBoom.v:134390 Compile module "work@BusyTableHelper_1".
+[INFO :CP0303] SmallBoom.v:138461 Compile module "work@BusyTableHelper_1".
 
-[INFO :CP0303] SmallBoom.v:136992 Compile module "work@BusyTable_1".
+[INFO :CP0303] SmallBoom.v:141069 Compile module "work@BusyTable_1".
 
-[INFO :CP0303] SmallBoom.v:33197 Compile module "work@CLINT".
+[INFO :CP0303] SmallBoom.v:35412 Compile module "work@CLINT".
 
-[INFO :CP0303] SmallBoom.v:170465 Compile module "work@CSRFile".
+[INFO :CP0303] SmallBoom.v:175008 Compile module "work@CSRFile".
 
-[INFO :CP0303] SmallBoom.v:100761 Compile module "work@CompareRecFN".
+[INFO :CP0303] SmallBoom.v:103830 Compile module "work@CompareRecFN".
 
-[INFO :CP0303] SmallBoom.v:151228 Compile module "work@DCacheShim".
+[INFO :CP0303] SmallBoom.v:155453 Compile module "work@DCacheShim".
 
-[INFO :CP0303] SmallBoom.v:33564 Compile module "work@DMIToTL".
+[INFO :CP0303] SmallBoom.v:35785 Compile module "work@DMIToTL".
 
-[INFO :CP0303] SmallBoom.v:54874 Compile module "work@DataArray".
+[INFO :CP0303] SmallBoom.v:57318 Compile module "work@DataArray".
 
-[INFO :CP0303] SmallBoom.v:121349 Compile module "work@DecodeUnit".
+[INFO :CP0303] SmallBoom.v:124592 Compile module "work@DecodeUnit".
 
-[INFO :CP0303] SmallBoom.v:107197 Compile module "work@DivSqrtRecF64".
+[INFO :CP0303] SmallBoom.v:110302 Compile module "work@DivSqrtRecF64".
 
-[INFO :CP0303] SmallBoom.v:104760 Compile module "work@DivSqrtRecF64ToRaw_mulAddZ31".
+[INFO :CP0303] SmallBoom.v:107853 Compile module "work@DivSqrtRecF64ToRaw_mulAddZ31".
 
-[INFO :CP0303] SmallBoom.v:107008 Compile module "work@DivSqrtRecF64_mulAddZ31".
+[INFO :CP0303] SmallBoom.v:110107 Compile module "work@DivSqrtRecF64_mulAddZ31".
 
-[INFO :CP0303] SmallBoom.v:93424 Compile module "work@DivUnit".
+[INFO :CP0303] SmallBoom.v:96451 Compile module "work@DivUnit".
 
-[INFO :CP0303] SmallBoom.v:193820 Compile module "work@EICG_wrapper".
+[INFO :CP0303] SmallBoom.v:198741 Compile module "work@EICG_wrapper".
 
-[INFO :CP0303] SmallBoom.v:73940 Compile module "work@ElasticReg".
+[INFO :CP0303] SmallBoom.v:76567 Compile module "work@ElasticReg".
 
-[INFO :CP0303] SmallBoom.v:74103 Compile module "work@ElasticReg_1".
+[INFO :CP0303] SmallBoom.v:76736 Compile module "work@ElasticReg_1".
 
-[INFO :CP0303] SmallBoom.v:79039 Compile module "work@ElasticReg_2".
+[INFO :CP0303] SmallBoom.v:81822 Compile module "work@ElasticReg_2".
 
-[INFO :CP0303] SmallBoom.v:79115 Compile module "work@ElasticReg_3".
+[INFO :CP0303] SmallBoom.v:81904 Compile module "work@ElasticReg_3".
 
-[INFO :CP0303] SmallBoom.v:186931 Compile module "work@ExampleBoomSystem".
+[INFO :CP0303] SmallBoom.v:191756 Compile module "work@ExampleBoomSystem".
 
-[INFO :CP0303] SmallBoom.v:107294 Compile module "work@FDivSqrtUnit".
+[INFO :CP0303] SmallBoom.v:110399 Compile module "work@FDivSqrtUnit".
 
-[INFO :CP0303] SmallBoom.v:98861 Compile module "work@FMADecoder".
+[INFO :CP0303] SmallBoom.v:101918 Compile module "work@FMADecoder".
 
-[INFO :CP0303] SmallBoom.v:102292 Compile module "work@FPToFP".
+[INFO :CP0303] SmallBoom.v:105367 Compile module "work@FPToFP".
 
-[INFO :CP0303] SmallBoom.v:101317 Compile module "work@FPToInt".
+[INFO :CP0303] SmallBoom.v:104386 Compile module "work@FPToInt".
 
-[INFO :CP0303] SmallBoom.v:102610 Compile module "work@FPU".
+[INFO :CP0303] SmallBoom.v:105691 Compile module "work@FPU".
 
-[INFO :CP0303] SmallBoom.v:109956 Compile module "work@FPUExeUnit".
+[INFO :CP0303] SmallBoom.v:113100 Compile module "work@FPUExeUnit".
 
-[INFO :CP0303] SmallBoom.v:98731 Compile module "work@FPUFMAPipe".
+[INFO :CP0303] SmallBoom.v:101782 Compile module "work@FPUFMAPipe".
 
-[INFO :CP0303] SmallBoom.v:100641 Compile module "work@FPUFMAPipe_1".
+[INFO :CP0303] SmallBoom.v:103704 Compile module "work@FPUFMAPipe_1".
 
-[INFO :CP0303] SmallBoom.v:103104 Compile module "work@FPUUnit".
+[INFO :CP0303] SmallBoom.v:106191 Compile module "work@FPUUnit".
 
-[INFO :CP0303] SmallBoom.v:68704 Compile module "work@FetchBuffer".
+[INFO :CP0303] SmallBoom.v:71226 Compile module "work@FetchBuffer".
 
-[INFO :CP0303] SmallBoom.v:74334 Compile module "work@FetchControlUnit".
+[INFO :CP0303] SmallBoom.v:76973 Compile module "work@FetchControlUnit".
 
-[INFO :CP0303] SmallBoom.v:73639 Compile module "work@FetchMonitor".
+[INFO :CP0303] SmallBoom.v:76227 Compile module "work@FetchMonitor".
 
-[INFO :CP0303] SmallBoom.v:67606 Compile module "work@FetchTargetQueue".
+[INFO :CP0303] SmallBoom.v:70110 Compile module "work@FetchTargetQueue".
 
-[INFO :CP0303] SmallBoom.v:152379 Compile module "work@ForwardingAgeLogic".
+[INFO :CP0303] SmallBoom.v:156622 Compile module "work@ForwardingAgeLogic".
 
-[INFO :CP0303] SmallBoom.v:119066 Compile module "work@FpPipeline".
+[INFO :CP0303] SmallBoom.v:122261 Compile module "work@FpPipeline".
 
-[INFO :CP0303] SmallBoom.v:14094 Compile module "work@FrontBus".
+[INFO :CP0303] SmallBoom.v:14533 Compile module "work@FrontBus".
 
-[INFO :CP0303] SmallBoom.v:79208 Compile module "work@GShareBrPredictor".
+[INFO :CP0303] SmallBoom.v:82003 Compile module "work@GShareBrPredictor".
 
-[INFO :CP0303] SmallBoom.v:82192 Compile module "work@HellaCacheArbiter".
+[INFO :CP0303] SmallBoom.v:85071 Compile module "work@HellaCacheArbiter".
 
-[INFO :CP0303] SmallBoom.v:57676 Compile module "work@ICache".
+[INFO :CP0303] SmallBoom.v:60150 Compile module "work@ICache".
 
-[INFO :CP0303] SmallBoom.v:89682 Compile module "work@INToRecFN".
+[INFO :CP0303] SmallBoom.v:92663 Compile module "work@INToRecFN".
 
-[INFO :CP0303] SmallBoom.v:90195 Compile module "work@INToRecFN_1".
+[INFO :CP0303] SmallBoom.v:93176 Compile module "work@INToRecFN_1".
 
-[INFO :CP0303] SmallBoom.v:47491 Compile module "work@IOMSHR".
+[INFO :CP0303] SmallBoom.v:49874 Compile module "work@IOMSHR".
 
-[INFO :CP0303] SmallBoom.v:82160 Compile module "work@IntSyncCrossingSink".
+[INFO :CP0303] SmallBoom.v:85039 Compile module "work@IntSyncCrossingSink".
 
-[INFO :CP0303] SmallBoom.v:82177 Compile module "work@IntSyncCrossingSink_1".
+[INFO :CP0303] SmallBoom.v:85056 Compile module "work@IntSyncCrossingSink_1".
 
-[INFO :CP0303] SmallBoom.v:82186 Compile module "work@IntSyncCrossingSink_2".
+[INFO :CP0303] SmallBoom.v:85065 Compile module "work@IntSyncCrossingSink_2".
 
-[INFO :CP0303] SmallBoom.v:34691 Compile module "work@IntSyncCrossingSource".
+[INFO :CP0303] SmallBoom.v:36936 Compile module "work@IntSyncCrossingSource".
 
-[INFO :CP0303] SmallBoom.v:183292 Compile module "work@IntSyncCrossingSource_2".
+[INFO :CP0303] SmallBoom.v:187943 Compile module "work@IntSyncCrossingSource_2".
 
-[INFO :CP0303] SmallBoom.v:183316 Compile module "work@IntSyncCrossingSource_3".
+[INFO :CP0303] SmallBoom.v:187967 Compile module "work@IntSyncCrossingSource_3".
 
-[INFO :CP0303] SmallBoom.v:90584 Compile module "work@IntToFP".
+[INFO :CP0303] SmallBoom.v:93565 Compile module "work@IntToFP".
 
-[INFO :CP0303] SmallBoom.v:91422 Compile module "work@IntToFPUnit".
+[INFO :CP0303] SmallBoom.v:94409 Compile module "work@IntToFPUnit".
 
-[INFO :CP0303] SmallBoom.v:61 Compile module "work@IntXbar".
+[INFO :CP0303] SmallBoom.v:67 Compile module "work@IntXbar".
 
-[INFO :CP0303] SmallBoom.v:44644 Compile module "work@IntXbar_4".
+[INFO :CP0303] SmallBoom.v:46985 Compile module "work@IntXbar_4".
 
-[INFO :CP0303] SmallBoom.v:183360 Compile module "work@IntXing".
+[INFO :CP0303] SmallBoom.v:188017 Compile module "work@IntXing".
 
-[INFO :CP0303] SmallBoom.v:111431 Compile module "work@IssueSlot".
+[INFO :CP0303] SmallBoom.v:114581 Compile module "work@IssueSlot".
 
-[INFO :CP0303] SmallBoom.v:138546 Compile module "work@IssueSlot_4".
+[INFO :CP0303] SmallBoom.v:142665 Compile module "work@IssueSlot_4".
 
-[INFO :CP0303] SmallBoom.v:112835 Compile module "work@IssueUnitCollapsing".
+[INFO :CP0303] SmallBoom.v:115997 Compile module "work@IssueUnitCollapsing".
 
-[INFO :CP0303] SmallBoom.v:140180 Compile module "work@IssueUnitCollapsing_1".
+[INFO :CP0303] SmallBoom.v:144341 Compile module "work@IssueUnitCollapsing_1".
 
-[INFO :CP0303] SmallBoom.v:143435 Compile module "work@IssueUnitCollapsing_2".
+[INFO :CP0303] SmallBoom.v:147614 Compile module "work@IssueUnitCollapsing_2".
 
-[INFO :CP0303] SmallBoom.v:54673 Compile module "work@L1MetadataArray".
+[INFO :CP0303] SmallBoom.v:57111 Compile module "work@L1MetadataArray".
 
-[INFO :CP0303] SmallBoom.v:32470 Compile module "work@LevelGateway".
+[INFO :CP0303] SmallBoom.v:34643 Compile module "work@LevelGateway".
 
-[INFO :CP0303] SmallBoom.v:151001 Compile module "work@LoadReqSlot".
+[INFO :CP0303] SmallBoom.v:155220 Compile module "work@LoadReqSlot".
 
-[INFO :CP0303] SmallBoom.v:152444 Compile module "work@LoadStoreUnit".
+[INFO :CP0303] SmallBoom.v:156687 Compile module "work@LoadStoreUnit".
 
-[INFO :CP0303] SmallBoom.v:45463 Compile module "work@MSHR".
+[INFO :CP0303] SmallBoom.v:47834 Compile module "work@MSHR".
 
-[INFO :CP0303] SmallBoom.v:48001 Compile module "work@MSHRFile".
+[INFO :CP0303] SmallBoom.v:50396 Compile module "work@MSHRFile".
 
-[INFO :CP0303] SmallBoom.v:46459 Compile module "work@MSHR_1".
+[INFO :CP0303] SmallBoom.v:48836 Compile module "work@MSHR_1".
 
-[INFO :CP0303] SmallBoom.v:85035 Compile module "work@MemAddrCalcUnit".
+[INFO :CP0303] SmallBoom.v:87950 Compile module "work@MemAddrCalcUnit".
 
-[INFO :CP0303] SmallBoom.v:24912 Compile module "work@MemoryBus".
+[INFO :CP0303] SmallBoom.v:26917 Compile module "work@MemoryBus".
 
-[INFO :CP0303] SmallBoom.v:107140 Compile module "work@Mul54".
+[INFO :CP0303] SmallBoom.v:110239 Compile module "work@Mul54".
 
-[INFO :CP0303] SmallBoom.v:98405 Compile module "work@MulAddRecFNPipe".
+[INFO :CP0303] SmallBoom.v:101450 Compile module "work@MulAddRecFNPipe".
 
-[INFO :CP0303] SmallBoom.v:100315 Compile module "work@MulAddRecFNPipe_1".
+[INFO :CP0303] SmallBoom.v:103372 Compile module "work@MulAddRecFNPipe_1".
 
-[INFO :CP0303] SmallBoom.v:96766 Compile module "work@MulAddRecFNToRaw_postMul".
+[INFO :CP0303] SmallBoom.v:99811 Compile module "work@MulAddRecFNToRaw_postMul".
 
-[INFO :CP0303] SmallBoom.v:99200 Compile module "work@MulAddRecFNToRaw_postMul_1".
+[INFO :CP0303] SmallBoom.v:102257 Compile module "work@MulAddRecFNToRaw_postMul_1".
 
-[INFO :CP0303] SmallBoom.v:96401 Compile module "work@MulAddRecFNToRaw_preMul".
+[INFO :CP0303] SmallBoom.v:99446 Compile module "work@MulAddRecFNToRaw_preMul".
 
-[INFO :CP0303] SmallBoom.v:98903 Compile module "work@MulAddRecFNToRaw_preMul_1".
+[INFO :CP0303] SmallBoom.v:101960 Compile module "work@MulAddRecFNToRaw_preMul_1".
 
-[INFO :CP0303] SmallBoom.v:92332 Compile module "work@MulDiv".
+[INFO :CP0303] SmallBoom.v:95353 Compile module "work@MulDiv".
 
-[INFO :CP0303] SmallBoom.v:32501 Compile module "work@PLICFanIn".
+[INFO :CP0303] SmallBoom.v:34680 Compile module "work@PLICFanIn".
 
-[INFO :CP0303] SmallBoom.v:49413 Compile module "work@PMPChecker".
+[INFO :CP0303] SmallBoom.v:51839 Compile module "work@PMPChecker".
 
-[INFO :CP0303] SmallBoom.v:82397 Compile module "work@PTW".
+[INFO :CP0303] SmallBoom.v:85288 Compile module "work@PTW".
 
-[INFO :CP0303] SmallBoom.v:31291 Compile module "work@PeripheryBus_1".
+[INFO :CP0303] SmallBoom.v:33464 Compile module "work@PeripheryBus_1".
 
-[INFO :CP0303] SmallBoom.v:88178 Compile module "work@PipelinedMulUnit".
+[INFO :CP0303] SmallBoom.v:91153 Compile module "work@PipelinedMulUnit".
 
-[INFO :CP0303] SmallBoom.v:88062 Compile module "work@PipelinedMultiplier".
+[INFO :CP0303] SmallBoom.v:91031 Compile module "work@PipelinedMultiplier".
 
-[INFO :CP0303] SmallBoom.v:23896 Compile module "work@ProbePicker".
+[INFO :CP0303] SmallBoom.v:25901 Compile module "work@ProbePicker".
 
-[INFO :CP0303] SmallBoom.v:44844 Compile module "work@ProbeUnit".
+[INFO :CP0303] SmallBoom.v:47191 Compile module "work@ProbeUnit".
 
-[INFO :CP0303] SmallBoom.v:2105 Compile module "work@Queue".
+[INFO :CP0303] SmallBoom.v:2208 Compile module "work@Queue".
 
-[INFO :CP0303] SmallBoom.v:2345 Compile module "work@Queue_1".
+[INFO :CP0303] SmallBoom.v:2454 Compile module "work@Queue_1".
 
-[INFO :CP0303] SmallBoom.v:189719 Compile module "work@Queue_100".
+[INFO :CP0303] SmallBoom.v:194574 Compile module "work@Queue_100".
 
-[INFO :CP0303] SmallBoom.v:191524 Compile module "work@Queue_103".
+[INFO :CP0303] SmallBoom.v:196409 Compile module "work@Queue_103".
 
-[INFO :CP0303] SmallBoom.v:191899 Compile module "work@Queue_108".
+[INFO :CP0303] SmallBoom.v:196790 Compile module "work@Queue_108".
 
-[INFO :CP0303] SmallBoom.v:3930 Compile module "work@Queue_17".
+[INFO :CP0303] SmallBoom.v:4081 Compile module "work@Queue_17".
 
-[INFO :CP0303] SmallBoom.v:2465 Compile module "work@Queue_2".
+[INFO :CP0303] SmallBoom.v:2580 Compile module "work@Queue_2".
 
-[INFO :CP0303] SmallBoom.v:5316 Compile module "work@Queue_23".
+[INFO :CP0303] SmallBoom.v:5551 Compile module "work@Queue_23".
 
-[INFO :CP0303] SmallBoom.v:5424 Compile module "work@Queue_24".
+[INFO :CP0303] SmallBoom.v:5665 Compile module "work@Queue_24".
 
-[INFO :CP0303] SmallBoom.v:9263 Compile module "work@Queue_25".
+[INFO :CP0303] SmallBoom.v:9588 Compile module "work@Queue_25".
 
-[INFO :CP0303] SmallBoom.v:9483 Compile module "work@Queue_26".
+[INFO :CP0303] SmallBoom.v:9814 Compile module "work@Queue_26".
 
-[INFO :CP0303] SmallBoom.v:10433 Compile module "work@Queue_27".
+[INFO :CP0303] SmallBoom.v:10776 Compile module "work@Queue_27".
 
-[INFO :CP0303] SmallBoom.v:10561 Compile module "work@Queue_28".
+[INFO :CP0303] SmallBoom.v:10910 Compile module "work@Queue_28".
 
-[INFO :CP0303] SmallBoom.v:11595 Compile module "work@Queue_29".
+[INFO :CP0303] SmallBoom.v:11992 Compile module "work@Queue_29".
 
-[INFO :CP0303] SmallBoom.v:11957 Compile module "work@Queue_33".
+[INFO :CP0303] SmallBoom.v:12372 Compile module "work@Queue_33".
 
-[INFO :CP0303] SmallBoom.v:14539 Compile module "work@Queue_38".
+[INFO :CP0303] SmallBoom.v:14978 Compile module "work@Queue_38".
 
-[INFO :CP0303] SmallBoom.v:2565 Compile module "work@Queue_4".
+[INFO :CP0303] SmallBoom.v:2686 Compile module "work@Queue_4".
 
-[INFO :CP0303] SmallBoom.v:3046 Compile module "work@Queue_5".
+[INFO :CP0303] SmallBoom.v:3173 Compile module "work@Queue_5".
 
-[INFO :CP0303] SmallBoom.v:3098 Compile module "work@Queue_7".
+[INFO :CP0303] SmallBoom.v:3231 Compile module "work@Queue_7".
 
-[INFO :CP0303] SmallBoom.v:16185 Compile module "work@Queue_71".
+[INFO :CP0303] SmallBoom.v:16642 Compile module "work@Queue_71".
 
-[INFO :CP0303] SmallBoom.v:26634 Compile module "work@Queue_72".
+[INFO :CP0303] SmallBoom.v:28669 Compile module "work@Queue_72".
 
-[INFO :CP0303] SmallBoom.v:26814 Compile module "work@Queue_73".
+[INFO :CP0303] SmallBoom.v:28855 Compile module "work@Queue_73".
 
-[INFO :CP0303] SmallBoom.v:28665 Compile module "work@Queue_74".
+[INFO :CP0303] SmallBoom.v:30730 Compile module "work@Queue_74".
 
-[INFO :CP0303] SmallBoom.v:28920 Compile module "work@Queue_75".
+[INFO :CP0303] SmallBoom.v:30997 Compile module "work@Queue_75".
 
-[INFO :CP0303] SmallBoom.v:32529 Compile module "work@Queue_77".
+[INFO :CP0303] SmallBoom.v:34708 Compile module "work@Queue_77".
 
-[INFO :CP0303] SmallBoom.v:45251 Compile module "work@Queue_78".
+[INFO :CP0303] SmallBoom.v:47610 Compile module "work@Queue_78".
 
-[INFO :CP0303] SmallBoom.v:45411 Compile module "work@Queue_79".
+[INFO :CP0303] SmallBoom.v:47776 Compile module "work@Queue_79".
 
-[INFO :CP0303] SmallBoom.v:76770 Compile module "work@Queue_82".
+[INFO :CP0303] SmallBoom.v:79517 Compile module "work@Queue_82".
 
-[INFO :CP0303] SmallBoom.v:76930 Compile module "work@Queue_83".
+[INFO :CP0303] SmallBoom.v:79683 Compile module "work@Queue_83".
 
-[INFO :CP0303] SmallBoom.v:81032 Compile module "work@Queue_86".
+[INFO :CP0303] SmallBoom.v:83875 Compile module "work@Queue_86".
 
-[INFO :CP0303] SmallBoom.v:81252 Compile module "work@Queue_87".
+[INFO :CP0303] SmallBoom.v:84101 Compile module "work@Queue_87".
 
-[INFO :CP0303] SmallBoom.v:81452 Compile module "work@Queue_88".
+[INFO :CP0303] SmallBoom.v:84307 Compile module "work@Queue_88".
 
-[INFO :CP0303] SmallBoom.v:81590 Compile module "work@Queue_89".
+[INFO :CP0303] SmallBoom.v:84451 Compile module "work@Queue_89".
 
-[INFO :CP0303] SmallBoom.v:81750 Compile module "work@Queue_90".
+[INFO :CP0303] SmallBoom.v:84617 Compile module "work@Queue_90".
 
-[INFO :CP0303] SmallBoom.v:184428 Compile module "work@Queue_91".
+[INFO :CP0303] SmallBoom.v:189085 Compile module "work@Queue_91".
 
-[INFO :CP0303] SmallBoom.v:189065 Compile module "work@Queue_95".
+[INFO :CP0303] SmallBoom.v:193902 Compile module "work@Queue_95".
 
-[INFO :CP0303] SmallBoom.v:189185 Compile module "work@Queue_97".
+[INFO :CP0303] SmallBoom.v:194028 Compile module "work@Queue_97".
 
-[INFO :CP0303] SmallBoom.v:189305 Compile module "work@Queue_99".
+[INFO :CP0303] SmallBoom.v:194154 Compile module "work@Queue_99".
 
-[INFO :CP0303] SmallBoom.v:82289 Compile module "work@RRArbiter".
+[INFO :CP0303] SmallBoom.v:85174 Compile module "work@RRArbiter".
 
-[INFO :CP0303] SmallBoom.v:73100 Compile module "work@RVCExpander".
+[INFO :CP0303] SmallBoom.v:75688 Compile module "work@RVCExpander".
 
-[INFO :CP0303] SmallBoom.v:100907 Compile module "work@RecFNToIN".
+[INFO :CP0303] SmallBoom.v:103976 Compile module "work@RecFNToIN".
 
-[INFO :CP0303] SmallBoom.v:101127 Compile module "work@RecFNToIN_1".
+[INFO :CP0303] SmallBoom.v:104196 Compile module "work@RecFNToIN_1".
 
-[INFO :CP0303] SmallBoom.v:102218 Compile module "work@RecFNToRecFN".
+[INFO :CP0303] SmallBoom.v:105293 Compile module "work@RecFNToRecFN".
 
-[INFO :CP0303] SmallBoom.v:104698 Compile module "work@RecFNToRecFN_1".
+[INFO :CP0303] SmallBoom.v:107791 Compile module "work@RecFNToRecFN_1".
 
-[INFO :CP0303] SmallBoom.v:116786 Compile module "work@RegisterFileSynthesizable".
+[INFO :CP0303] SmallBoom.v:119960 Compile module "work@RegisterFileSynthesizable".
 
-[INFO :CP0303] SmallBoom.v:147635 Compile module "work@RegisterFileSynthesizable_1".
+[INFO :CP0303] SmallBoom.v:151832 Compile module "work@RegisterFileSynthesizable_1".
 
-[INFO :CP0303] SmallBoom.v:117387 Compile module "work@RegisterRead".
+[INFO :CP0303] SmallBoom.v:120576 Compile module "work@RegisterRead".
 
-[INFO :CP0303] SmallBoom.v:116892 Compile module "work@RegisterReadDecode".
+[INFO :CP0303] SmallBoom.v:120081 Compile module "work@RegisterReadDecode".
 
-[INFO :CP0303] SmallBoom.v:147876 Compile module "work@RegisterReadDecode_1".
+[INFO :CP0303] SmallBoom.v:152089 Compile module "work@RegisterReadDecode_1".
 
-[INFO :CP0303] SmallBoom.v:147958 Compile module "work@RegisterReadDecode_2".
+[INFO :CP0303] SmallBoom.v:152171 Compile module "work@RegisterReadDecode_2".
 
-[INFO :CP0303] SmallBoom.v:148685 Compile module "work@RegisterRead_1".
+[INFO :CP0303] SmallBoom.v:152898 Compile module "work@RegisterRead_1".
 
-[INFO :CP0303] SmallBoom.v:126706 Compile module "work@RenameFreeList".
+[INFO :CP0303] SmallBoom.v:130375 Compile module "work@RenameFreeList".
 
-[INFO :CP0303] SmallBoom.v:125963 Compile module "work@RenameFreeListHelper".
+[INFO :CP0303] SmallBoom.v:129626 Compile module "work@RenameFreeListHelper".
 
-[INFO :CP0303] SmallBoom.v:134080 Compile module "work@RenameFreeList_1".
+[INFO :CP0303] SmallBoom.v:138145 Compile module "work@RenameFreeList_1".
 
-[INFO :CP0303] SmallBoom.v:123248 Compile module "work@RenameMapTable".
+[INFO :CP0303] SmallBoom.v:126503 Compile module "work@RenameMapTable".
 
-[INFO :CP0303] SmallBoom.v:123195 Compile module "work@RenameMapTableElement_1".
+[INFO :CP0303] SmallBoom.v:126444 Compile module "work@RenameMapTableElement_1".
 
-[INFO :CP0303] SmallBoom.v:131339 Compile module "work@RenameMapTable_1".
+[INFO :CP0303] SmallBoom.v:135020 Compile module "work@RenameMapTable_1".
 
-[INFO :CP0303] SmallBoom.v:137072 Compile module "work@RenameStage".
+[INFO :CP0303] SmallBoom.v:141149 Compile module "work@RenameStage".
 
-[INFO :CP0303] SmallBoom.v:29313 Compile module "work@Repeater".
+[INFO :CP0303] SmallBoom.v:31396 Compile module "work@Repeater".
 
-[INFO :CP0303] SmallBoom.v:29831 Compile module "work@Repeater_1".
+[INFO :CP0303] SmallBoom.v:31938 Compile module "work@Repeater_1".
 
-[INFO :CP0303] SmallBoom.v:30349 Compile module "work@Repeater_2".
+[INFO :CP0303] SmallBoom.v:32480 Compile module "work@Repeater_2".
 
-[INFO :CP0303] SmallBoom.v:30867 Compile module "work@Repeater_3".
+[INFO :CP0303] SmallBoom.v:33022 Compile module "work@Repeater_3".
 
-[INFO :CP0303] SmallBoom.v:43487 Compile module "work@ResetCatchAndSync_d3".
+[INFO :CP0303] SmallBoom.v:45792 Compile module "work@ResetCatchAndSync_d3".
 
-[INFO :CP0303] SmallBoom.v:164762 Compile module "work@Rob".
+[INFO :CP0303] SmallBoom.v:169131 Compile module "work@Rob".
 
-[INFO :CP0303] SmallBoom.v:89558 Compile module "work@RoundAnyRawFNToRecFN".
+[INFO :CP0303] SmallBoom.v:92539 Compile module "work@RoundAnyRawFNToRecFN".
 
-[INFO :CP0303] SmallBoom.v:90071 Compile module "work@RoundAnyRawFNToRecFN_1".
+[INFO :CP0303] SmallBoom.v:93052 Compile module "work@RoundAnyRawFNToRecFN_1".
 
-[INFO :CP0303] SmallBoom.v:97855 Compile module "work@RoundAnyRawFNToRecFN_2".
+[INFO :CP0303] SmallBoom.v:100900 Compile module "work@RoundAnyRawFNToRecFN_2".
 
-[INFO :CP0303] SmallBoom.v:99861 Compile module "work@RoundAnyRawFNToRecFN_3".
+[INFO :CP0303] SmallBoom.v:102918 Compile module "work@RoundAnyRawFNToRecFN_3".
 
-[INFO :CP0303] SmallBoom.v:101821 Compile module "work@RoundAnyRawFNToRecFN_4".
+[INFO :CP0303] SmallBoom.v:104896 Compile module "work@RoundAnyRawFNToRecFN_4".
 
-[INFO :CP0303] SmallBoom.v:104633 Compile module "work@RoundAnyRawFNToRecFN_5".
+[INFO :CP0303] SmallBoom.v:107726 Compile module "work@RoundAnyRawFNToRecFN_5".
 
-[INFO :CP0303] SmallBoom.v:106507 Compile module "work@RoundAnyRawFNToRecFN_7".
+[INFO :CP0303] SmallBoom.v:109606 Compile module "work@RoundAnyRawFNToRecFN_7".
 
-[INFO :CP0303] SmallBoom.v:98360 Compile module "work@RoundRawFNToRecFN".
+[INFO :CP0303] SmallBoom.v:101405 Compile module "work@RoundRawFNToRecFN".
 
-[INFO :CP0303] SmallBoom.v:100270 Compile module "work@RoundRawFNToRecFN_1".
+[INFO :CP0303] SmallBoom.v:103327 Compile module "work@RoundRawFNToRecFN_1".
 
-[INFO :CP0303] SmallBoom.v:106959 Compile module "work@RoundRawFNToRecFN_2".
+[INFO :CP0303] SmallBoom.v:110058 Compile module "work@RoundRawFNToRecFN_2".
 
-[INFO :CP0303] SmallBoom.v:190696 Compile module "work@SimAXIMem".
+[INFO :CP0303] SmallBoom.v:195575 Compile module "work@SimAXIMem".
 
-[INFO :CP0303] SmallBoom.v:192876 Compile module "work@SimAXIMem_1".
+[INFO :CP0303] SmallBoom.v:197791 Compile module "work@SimAXIMem_1".
 
-[INFO :CP0303] SmallBoom.v:193861 Compile module "work@SimDTM".
+[INFO :CP0303] SmallBoom.v:198784 Compile module "work@SimDTM".
 
-[INFO :CP0303] SmallBoom.v:1682 Compile module "work@SimpleLazyModule".
+[INFO :CP0303] SmallBoom.v:1785 Compile module "work@SimpleLazyModule".
 
-[INFO :CP0303] SmallBoom.v:6510 Compile module "work@SimpleLazyModule_1".
+[INFO :CP0303] SmallBoom.v:6835 Compile module "work@SimpleLazyModule_1".
 
-[INFO :CP0303] SmallBoom.v:30224 Compile module "work@SimpleLazyModule_10".
+[INFO :CP0303] SmallBoom.v:32355 Compile module "work@SimpleLazyModule_10".
 
-[INFO :CP0303] SmallBoom.v:30742 Compile module "work@SimpleLazyModule_11".
+[INFO :CP0303] SmallBoom.v:32897 Compile module "work@SimpleLazyModule_11".
 
-[INFO :CP0303] SmallBoom.v:31194 Compile module "work@SimpleLazyModule_13".
+[INFO :CP0303] SmallBoom.v:33367 Compile module "work@SimpleLazyModule_13".
 
-[INFO :CP0303] SmallBoom.v:7812 Compile module "work@SimpleLazyModule_2".
+[INFO :CP0303] SmallBoom.v:8137 Compile module "work@SimpleLazyModule_2".
 
-[INFO :CP0303] SmallBoom.v:8034 Compile module "work@SimpleLazyModule_3".
+[INFO :CP0303] SmallBoom.v:8359 Compile module "work@SimpleLazyModule_3".
 
-[INFO :CP0303] SmallBoom.v:13132 Compile module "work@SimpleLazyModule_5".
+[INFO :CP0303] SmallBoom.v:13571 Compile module "work@SimpleLazyModule_5".
 
-[INFO :CP0303] SmallBoom.v:23950 Compile module "work@SimpleLazyModule_6".
+[INFO :CP0303] SmallBoom.v:25955 Compile module "work@SimpleLazyModule_6".
 
-[INFO :CP0303] SmallBoom.v:24771 Compile module "work@SimpleLazyModule_7".
+[INFO :CP0303] SmallBoom.v:26776 Compile module "work@SimpleLazyModule_7".
 
-[INFO :CP0303] SmallBoom.v:29177 Compile module "work@SimpleLazyModule_8".
+[INFO :CP0303] SmallBoom.v:31260 Compile module "work@SimpleLazyModule_8".
 
-[INFO :CP0303] SmallBoom.v:29706 Compile module "work@SimpleLazyModule_9".
+[INFO :CP0303] SmallBoom.v:31813 Compile module "work@SimpleLazyModule_9".
 
-[INFO :CP0303] SmallBoom.v:43509 Compile module "work@SynchronizerShiftReg_w14_d1".
+[INFO :CP0303] SmallBoom.v:45814 Compile module "work@SynchronizerShiftReg_w14_d1".
 
-[INFO :CP0303] SmallBoom.v:82140 Compile module "work@SynchronizerShiftReg_w1_d3".
+[INFO :CP0303] SmallBoom.v:85013 Compile module "work@SynchronizerShiftReg_w1_d3".
 
-[INFO :CP0303] SmallBoom.v:183340 Compile module "work@SynchronizerShiftReg_w2_d3".
+[INFO :CP0303] SmallBoom.v:187991 Compile module "work@SynchronizerShiftReg_w2_d3".
 
-[INFO :CP0303] SmallBoom.v:35081 Compile module "work@SynchronizerShiftReg_w43_d1".
+[INFO :CP0303] SmallBoom.v:37332 Compile module "work@SynchronizerShiftReg_w43_d1".
 
-[INFO :CP0303] SmallBoom.v:42940 Compile module "work@SynchronizerShiftReg_w55_d1".
+[INFO :CP0303] SmallBoom.v:45233 Compile module "work@SynchronizerShiftReg_w55_d1".
 
-[INFO :CP0303] SmallBoom.v:8183 Compile module "work@SystemBus".
+[INFO :CP0303] SmallBoom.v:8508 Compile module "work@SystemBus".
 
-[INFO :CP0303] SmallBoom.v:43326 Compile module "work@TLAsyncCrossingSink".
+[INFO :CP0303] SmallBoom.v:45631 Compile module "work@TLAsyncCrossingSink".
 
-[INFO :CP0303] SmallBoom.v:35297 Compile module "work@TLAsyncCrossingSource".
+[INFO :CP0303] SmallBoom.v:37554 Compile module "work@TLAsyncCrossingSource".
 
-[INFO :CP0303] SmallBoom.v:27199 Compile module "work@TLAtomicAutomata_1".
+[INFO :CP0303] SmallBoom.v:29246 Compile module "work@TLAtomicAutomata_1".
 
-[INFO :CP0303] SmallBoom.v:50371 Compile module "work@TLB".
+[INFO :CP0303] SmallBoom.v:52797 Compile module "work@TLB".
 
-[INFO :CP0303] SmallBoom.v:58326 Compile module "work@TLB_1".
+[INFO :CP0303] SmallBoom.v:60812 Compile module "work@TLB_1".
 
-[INFO :CP0303] SmallBoom.v:185472 Compile module "work@TLBroadcast".
+[INFO :CP0303] SmallBoom.v:190255 Compile module "work@TLBroadcast".
 
-[INFO :CP0303] SmallBoom.v:184528 Compile module "work@TLBroadcastTracker".
+[INFO :CP0303] SmallBoom.v:189191 Compile module "work@TLBroadcastTracker".
 
-[INFO :CP0303] SmallBoom.v:184764 Compile module "work@TLBroadcastTracker_1".
+[INFO :CP0303] SmallBoom.v:189457 Compile module "work@TLBroadcastTracker_1".
 
-[INFO :CP0303] SmallBoom.v:185000 Compile module "work@TLBroadcastTracker_2".
+[INFO :CP0303] SmallBoom.v:189723 Compile module "work@TLBroadcastTracker_2".
 
-[INFO :CP0303] SmallBoom.v:185236 Compile module "work@TLBroadcastTracker_3".
+[INFO :CP0303] SmallBoom.v:189989 Compile module "work@TLBroadcastTracker_3".
 
-[INFO :CP0303] SmallBoom.v:1484 Compile module "work@TLBuffer".
+[INFO :CP0303] SmallBoom.v:1587 Compile module "work@TLBuffer".
 
-[INFO :CP0303] SmallBoom.v:81827 Compile module "work@TLBuffer_11".
+[INFO :CP0303] SmallBoom.v:84700 Compile module "work@TLBuffer_11".
 
-[INFO :CP0303] SmallBoom.v:9663 Compile module "work@TLBuffer_4".
+[INFO :CP0303] SmallBoom.v:10000 Compile module "work@TLBuffer_4".
 
-[INFO :CP0303] SmallBoom.v:23842 Compile module "work@TLBuffer_6".
+[INFO :CP0303] SmallBoom.v:25847 Compile module "work@TLBuffer_6".
 
-[INFO :CP0303] SmallBoom.v:27034 Compile module "work@TLBuffer_7".
+[INFO :CP0303] SmallBoom.v:29081 Compile module "work@TLBuffer_7".
 
-[INFO :CP0303] SmallBoom.v:29040 Compile module "work@TLBuffer_8".
+[INFO :CP0303] SmallBoom.v:31123 Compile module "work@TLBuffer_8".
 
-[INFO :CP0303] SmallBoom.v:44039 Compile module "work@TLDebugModule".
+[INFO :CP0303] SmallBoom.v:46356 Compile module "work@TLDebugModule".
 
-[INFO :CP0303] SmallBoom.v:36041 Compile module "work@TLDebugModuleInner".
+[INFO :CP0303] SmallBoom.v:38304 Compile module "work@TLDebugModuleInner".
 
-[INFO :CP0303] SmallBoom.v:43709 Compile module "work@TLDebugModuleInnerAsync".
+[INFO :CP0303] SmallBoom.v:46020 Compile module "work@TLDebugModuleInnerAsync".
 
-[INFO :CP0303] SmallBoom.v:34489 Compile module "work@TLDebugModuleOuter".
+[INFO :CP0303] SmallBoom.v:36734 Compile module "work@TLDebugModuleOuter".
 
-[INFO :CP0303] SmallBoom.v:35624 Compile module "work@TLDebugModuleOuterAsync".
+[INFO :CP0303] SmallBoom.v:37887 Compile module "work@TLDebugModuleOuterAsync".
 
-[INFO :CP0303] SmallBoom.v:28757 Compile module "work@TLError".
+[INFO :CP0303] SmallBoom.v:30828 Compile module "work@TLError".
 
-[INFO :CP0303] SmallBoom.v:1583 Compile module "work@TLFIFOFixer".
+[INFO :CP0303] SmallBoom.v:1686 Compile module "work@TLFIFOFixer".
 
-[INFO :CP0303] SmallBoom.v:9828 Compile module "work@TLFIFOFixer_2".
+[INFO :CP0303] SmallBoom.v:10165 Compile module "work@TLFIFOFixer_2".
 
-[INFO :CP0303] SmallBoom.v:25315 Compile module "work@TLFIFOFixer_3".
+[INFO :CP0303] SmallBoom.v:27320 Compile module "work@TLFIFOFixer_3".
 
-[INFO :CP0303] SmallBoom.v:29396 Compile module "work@TLFragmenter".
+[INFO :CP0303] SmallBoom.v:31485 Compile module "work@TLFragmenter".
 
-[INFO :CP0303] SmallBoom.v:29914 Compile module "work@TLFragmenter_1".
+[INFO :CP0303] SmallBoom.v:32027 Compile module "work@TLFragmenter_1".
 
-[INFO :CP0303] SmallBoom.v:30432 Compile module "work@TLFragmenter_2".
+[INFO :CP0303] SmallBoom.v:32569 Compile module "work@TLFragmenter_2".
 
-[INFO :CP0303] SmallBoom.v:30942 Compile module "work@TLFragmenter_3".
+[INFO :CP0303] SmallBoom.v:33103 Compile module "work@TLFragmenter_3".
 
-[INFO :CP0303] SmallBoom.v:32661 Compile module "work@TLPLIC".
+[INFO :CP0303] SmallBoom.v:34846 Compile module "work@TLPLIC".
 
-[INFO :CP0303] SmallBoom.v:183382 Compile module "work@TLROM".
+[INFO :CP0303] SmallBoom.v:188039 Compile module "work@TLROM".
 
-[INFO :CP0303] SmallBoom.v:5687 Compile module "work@TLToAXI4".
+[INFO :CP0303] SmallBoom.v:5934 Compile module "work@TLToAXI4".
 
-[INFO :CP0303] SmallBoom.v:16448 Compile module "work@TLToAXI4_1".
+[INFO :CP0303] SmallBoom.v:16911 Compile module "work@TLToAXI4_1".
 
-[INFO :CP0303] SmallBoom.v:6453 Compile module "work@TLWidthWidget".
+[INFO :CP0303] SmallBoom.v:6778 Compile module "work@TLWidthWidget".
 
-[INFO :CP0303] SmallBoom.v:7749 Compile module "work@TLWidthWidget_1".
+[INFO :CP0303] SmallBoom.v:8074 Compile module "work@TLWidthWidget_1".
 
-[INFO :CP0303] SmallBoom.v:7977 Compile module "work@TLWidthWidget_2".
+[INFO :CP0303] SmallBoom.v:8302 Compile module "work@TLWidthWidget_2".
 
-[INFO :CP0303] SmallBoom.v:70 Compile module "work@TLXbar".
+[INFO :CP0303] SmallBoom.v:76 Compile module "work@TLXbar".
 
-[INFO :CP0303] SmallBoom.v:9206 Compile module "work@TLXbar_3".
+[INFO :CP0303] SmallBoom.v:9531 Compile module "work@TLXbar_3".
 
-[INFO :CP0303] SmallBoom.v:14485 Compile module "work@TLXbar_4".
+[INFO :CP0303] SmallBoom.v:14924 Compile module "work@TLXbar_4".
 
-[INFO :CP0303] SmallBoom.v:25966 Compile module "work@TLXbar_5".
+[INFO :CP0303] SmallBoom.v:27977 Compile module "work@TLXbar_5".
 
-[INFO :CP0303] SmallBoom.v:26029 Compile module "work@TLXbar_6".
+[INFO :CP0303] SmallBoom.v:28040 Compile module "work@TLXbar_6".
 
-[INFO :CP0303] SmallBoom.v:33611 Compile module "work@TLXbar_7".
+[INFO :CP0303] SmallBoom.v:35832 Compile module "work@TLXbar_7".
 
-[INFO :CP0303] SmallBoom.v:44314 Compile module "work@TLXbar_8".
+[INFO :CP0303] SmallBoom.v:46631 Compile module "work@TLXbar_8".
 
-[INFO :CP0303] SmallBoom.v:193281 Compile module "work@TestHarness".
+[INFO :CP0303] SmallBoom.v:198196 Compile module "work@TestHarness".
 
-[INFO :CP0303] SmallBoom.v:104605 Compile module "work@UOPCodeFDivDecoder".
+[INFO :CP0303] SmallBoom.v:107698 Compile module "work@UOPCodeFDivDecoder".
 
-[INFO :CP0303] SmallBoom.v:89394 Compile module "work@UOPCodeFPUDecoder".
+[INFO :CP0303] SmallBoom.v:92375 Compile module "work@UOPCodeFPUDecoder".
 
-[INFO :CP0303] SmallBoom.v:44662 Compile module "work@WritebackUnit".
+[INFO :CP0303] SmallBoom.v:47003 Compile module "work@WritebackUnit".
 
-[INFO :CP0303] SmallBoom.v:49371 Compile module "work@packageanon2".
+[INFO :CP0303] SmallBoom.v:51797 Compile module "work@packageanon2".
 
-[INFO :CP0303] SmallBoom.v:82361 Compile module "work@packageanon2_60".
+[INFO :CP0303] SmallBoom.v:85252 Compile module "work@packageanon2_60".
 
-[INFO :CP0303] SmallBoom.v:82367 Compile module "work@packageanon2_61".
+[INFO :CP0303] SmallBoom.v:85258 Compile module "work@packageanon2_61".
 
-[INFO :CP0303] SmallBoom.v:193844 Compile module "work@plusarg_reader".
+[INFO :CP0303] SmallBoom.v:198765 Compile module "work@plusarg_reader".
 
 [INFO :CP0302] builtin.sv:4 Compile class "work@mailbox".
 
@@ -1174,845 +1174,845 @@
 
 [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
 
-[NOTE :CP0309] SmallBoom.v:85776 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:88721 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:85307 Implicit port type (wire) for "io_ll_iresp_valid",
+[NOTE :CP0309] SmallBoom.v:88246 Implicit port type (wire) for "io_ll_iresp_valid",
 there are 63 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:94243 Implicit port type (wire) for "io_fu_types",
+[NOTE :CP0309] SmallBoom.v:97276 Implicit port type (wire) for "io_fu_types",
 there are 62 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:86165 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:89110 Implicit port type (wire) for "io_resp_valid",
 there are 130 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:55084 Implicit port type (wire) for "io_out".
+[NOTE :CP0309] SmallBoom.v:57534 Implicit port type (wire) for "io_out".
 
-[NOTE :CP0309] SmallBoom.v:2708 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:2835 Implicit port type (wire) for "auto_in_aw_ready",
 there are 36 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:189467 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:194322 Implicit port type (wire) for "auto_in_aw_ready",
 there are 25 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:191647 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:196538 Implicit port type (wire) for "auto_in_aw_ready",
 there are 25 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:4093 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:4250 Implicit port type (wire) for "auto_in_aw_ready",
 there are 40 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:12128 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:12549 Implicit port type (wire) for "auto_in_aw_ready",
 there are 30 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:189870 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:194731 Implicit port type (wire) for "auto_in_aw_ready",
 there are 24 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:192050 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:196947 Implicit port type (wire) for "auto_in_aw_ready",
 there are 24 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:5191 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:5426 Implicit port type (wire) for "auto_in_aw_ready",
 there are 40 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:13037 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:13476 Implicit port type (wire) for "auto_in_aw_ready",
 there are 30 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:16052 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:16509 Implicit port type (wire) for "auto_in_aw_ready",
 there are 40 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:188571 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:193402 Implicit port type (wire) for "auto_in_aw_ready",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:191104 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:195983 Implicit port type (wire) for "auto_in_aw_ready",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:10652 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:11007 Implicit port type (wire) for "auto_in_aw_ready",
 there are 20 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:3181 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:3320 Implicit port type (wire) for "auto_in_aw_ready",
 there are 38 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:11678 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:12081 Implicit port type (wire) for "auto_in_aw_ready",
 there are 28 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:14622 Implicit port type (wire) for "auto_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:15067 Implicit port type (wire) for "auto_in_aw_ready",
 there are 38 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:45113 Implicit port type (wire) for "io_in_0_ready",
+[NOTE :CP0309] SmallBoom.v:47472 Implicit port type (wire) for "io_in_0_ready",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:45133 Implicit port type (wire) for "io_in_0_ready",
+[NOTE :CP0309] SmallBoom.v:47492 Implicit port type (wire) for "io_in_0_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:55059 Implicit port type (wire) for "io_in_1_ready",
+[NOTE :CP0309] SmallBoom.v:57509 Implicit port type (wire) for "io_in_1_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:119031 Implicit port type (wire) for "io_in_1_ready",
+[NOTE :CP0309] SmallBoom.v:122226 Implicit port type (wire) for "io_in_1_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:147840 Implicit port type (wire) for "io_in_1_ready",
+[NOTE :CP0309] SmallBoom.v:152053 Implicit port type (wire) for "io_in_1_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:45165 Implicit port type (wire) for "io_in_0_ready",
+[NOTE :CP0309] SmallBoom.v:47524 Implicit port type (wire) for "io_in_0_ready",
 there are 8 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:45205 Implicit port type (wire) for "io_in_0_ready",
+[NOTE :CP0309] SmallBoom.v:47564 Implicit port type (wire) for "io_in_0_ready",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:45241 Implicit port type (wire) for "io_in_0_ready",
+[NOTE :CP0309] SmallBoom.v:47600 Implicit port type (wire) for "io_in_0_ready",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:47456 Implicit port type (wire) for "io_in_0_ready".
+[NOTE :CP0309] SmallBoom.v:49839 Implicit port type (wire) for "io_in_0_ready".
 
-[NOTE :CP0309] SmallBoom.v:47462 Implicit port type (wire) for "io_in_0_ready",
+[NOTE :CP0309] SmallBoom.v:49845 Implicit port type (wire) for "io_in_0_ready",
 there are 8 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:54835 Implicit port type (wire) for "io_in_1_ready",
+[NOTE :CP0309] SmallBoom.v:57279 Implicit port type (wire) for "io_in_1_ready",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:55020 Implicit port type (wire) for "io_in_1_ready",
+[NOTE :CP0309] SmallBoom.v:57470 Implicit port type (wire) for "io_in_1_ready",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:35099 Implicit port type (wire) for "io_deq_valid",
+[NOTE :CP0309] SmallBoom.v:37356 Implicit port type (wire) for "io_deq_valid",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:42958 Implicit port type (wire) for "io_deq_valid",
+[NOTE :CP0309] SmallBoom.v:45257 Implicit port type (wire) for "io_deq_valid",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:43526 Implicit port type (wire) for "io_deq_valid",
+[NOTE :CP0309] SmallBoom.v:45837 Implicit port type (wire) for "io_deq_valid",
 there are 8 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:34914 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:37159 Implicit port type (wire) for "io_enq_ready",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:35465 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:37722 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:43159 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:45458 Implicit port type (wire) for "io_enq_ready",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:34468 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:36713 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:183256 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:187907 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:33940 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:36185 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:34849 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:37094 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:34701 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:36946 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:34757 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:37002 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:34828 Implicit port type (wire) for "io_out".
+[NOTE :CP0309] SmallBoom.v:37073 Implicit port type (wire) for "io_out".
 
-[NOTE :CP0309] SmallBoom.v:34873 Implicit port type (wire) for "io_out".
+[NOTE :CP0309] SmallBoom.v:37118 Implicit port type (wire) for "io_out".
 
-[NOTE :CP0309] SmallBoom.v:34894 Implicit port type (wire) for "io_out".
+[NOTE :CP0309] SmallBoom.v:37139 Implicit port type (wire) for "io_out".
 
-[NOTE :CP0309] SmallBoom.v:78134 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:80911 Implicit port type (wire) for "io_resp_valid",
 there are 10 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:77055 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:79814 Implicit port type (wire) for "io_resp_valid",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:174603 Implicit port type (wire) for "io_ifu_fetchpacket_ready",
+[NOTE :CP0309] SmallBoom.v:179164 Implicit port type (wire) for "io_ifu_fetchpacket_ready",
 there are 111 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:79899 Implicit port type (wire) for "auto_icache_master_out_a_valid",
+[NOTE :CP0309] SmallBoom.v:82736 Implicit port type (wire) for "auto_icache_master_out_a_valid",
 there are 43 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:55234 Implicit port type (wire) for "auto_out_a_valid",
+[NOTE :CP0309] SmallBoom.v:57684 Implicit port type (wire) for "auto_out_a_valid",
 there are 43 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:180502 Implicit port type (wire) for "auto_tl_master_xing_out_a_valid",
+[NOTE :CP0309] SmallBoom.v:185153 Implicit port type (wire) for "auto_tl_master_xing_out_a_valid",
 there are 18 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:67384 Implicit port type (wire) for "io_req_valid",
+[NOTE :CP0309] SmallBoom.v:69882 Implicit port type (wire) for "io_req_valid",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:73545 Implicit port type (wire) for "io_is_br",
+[NOTE :CP0309] SmallBoom.v:76133 Implicit port type (wire) for "io_is_br",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:91749 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:94754 Implicit port type (wire) for "io_enq_ready",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:109296 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:112425 Implicit port type (wire) for "io_enq_ready",
 there are 10 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:123113 Implicit port type (wire) for "io_br_tag_0",
+[NOTE :CP0309] SmallBoom.v:126356 Implicit port type (wire) for "io_br_tag_0",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:79637 Implicit port type (wire) for "io_f2_btb_resp_valid",
+[NOTE :CP0309] SmallBoom.v:82462 Implicit port type (wire) for "io_f2_btb_resp_valid",
 there are 13 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:131279 Implicit port type (wire) for "io_values_0_prs1_busy",
+[NOTE :CP0309] SmallBoom.v:134960 Implicit port type (wire) for "io_values_0_prs1_busy",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:127032 Implicit port type (wire) for "io_p_rs_busy_0",
+[NOTE :CP0309] SmallBoom.v:130707 Implicit port type (wire) for "io_p_rs_busy_0",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:134396 Implicit port type (wire) for "io_p_rs_busy_0",
+[NOTE :CP0309] SmallBoom.v:138467 Implicit port type (wire) for "io_p_rs_busy_0",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:137009 Implicit port type (wire) for "io_values_0_prs1_busy",
+[NOTE :CP0309] SmallBoom.v:141086 Implicit port type (wire) for "io_values_0_prs1_busy",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:33200 Implicit port type (wire) for "auto_int_out_0",
+[NOTE :CP0309] SmallBoom.v:35415 Implicit port type (wire) for "auto_int_out_0",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:170477 Implicit port type (wire) for "io_rw_rdata",
+[NOTE :CP0309] SmallBoom.v:175020 Implicit port type (wire) for "io_rw_rdata",
 there are 103 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:100765 Implicit port type (wire) for "io_lt",
+[NOTE :CP0309] SmallBoom.v:103834 Implicit port type (wire) for "io_lt",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:151249 Implicit port type (wire) for "io_core_resp_valid",
+[NOTE :CP0309] SmallBoom.v:155474 Implicit port type (wire) for "io_core_resp_valid",
 there are 28 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:33566 Implicit port type (wire) for "auto_out_a_valid",
+[NOTE :CP0309] SmallBoom.v:35787 Implicit port type (wire) for "auto_out_a_valid",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:54883 Implicit port type (wire) for "io_resp_0",
+[NOTE :CP0309] SmallBoom.v:57327 Implicit port type (wire) for "io_resp_0",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:121383 Implicit port type (wire) for "io_deq_uop_valid",
+[NOTE :CP0309] SmallBoom.v:124626 Implicit port type (wire) for "io_deq_uop_valid",
 there are 68 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:107200 Implicit port type (wire) for "io_inReady_div",
+[NOTE :CP0309] SmallBoom.v:110305 Implicit port type (wire) for "io_inReady_div",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:104763 Implicit port type (wire) for "io_inReady_div",
+[NOTE :CP0309] SmallBoom.v:107856 Implicit port type (wire) for "io_inReady_div",
 there are 18 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:107011 Implicit port type (wire) for "io_inReady_div",
+[NOTE :CP0309] SmallBoom.v:110110 Implicit port type (wire) for "io_inReady_div",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:93427 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:96454 Implicit port type (wire) for "io_req_ready",
 there are 92 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:193821 Implicit port type (wire) for "out".
+[NOTE :CP0309] SmallBoom.v:198742 Implicit port type (wire) for "out".
 
-[NOTE :CP0309] SmallBoom.v:73943 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:76570 Implicit port type (wire) for "io_enq_ready",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:74106 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:76739 Implicit port type (wire) for "io_enq_ready",
 there are 11 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:79042 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:81825 Implicit port type (wire) for "io_enq_ready",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:79118 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:81907 Implicit port type (wire) for "io_enq_ready",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:186935 Implicit port type (wire) for "debug_clockeddmi_dmi_req_ready",
+[NOTE :CP0309] SmallBoom.v:191760 Implicit port type (wire) for "debug_clockeddmi_dmi_req_ready",
 there are 68 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:107297 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:110402 Implicit port type (wire) for "io_req_ready",
 there are 93 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:98863 Implicit port type (wire) for "io_cmd".
+[NOTE :CP0309] SmallBoom.v:101920 Implicit port type (wire) for "io_cmd".
 
-[NOTE :CP0309] SmallBoom.v:102302 Implicit port type (wire) for "io_out_valid",
+[NOTE :CP0309] SmallBoom.v:105377 Implicit port type (wire) for "io_out_valid",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:101327 Implicit port type (wire) for "io_out_bits_lt",
+[NOTE :CP0309] SmallBoom.v:104396 Implicit port type (wire) for "io_out_bits_lt",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:102620 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:105701 Implicit port type (wire) for "io_resp_valid",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:109959 Implicit port type (wire) for "io_fu_types",
+[NOTE :CP0309] SmallBoom.v:113103 Implicit port type (wire) for "io_fu_types",
 there are 28 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:98742 Implicit port type (wire) for "io_out_valid",
+[NOTE :CP0309] SmallBoom.v:101793 Implicit port type (wire) for "io_out_valid",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:100652 Implicit port type (wire) for "io_out_valid",
+[NOTE :CP0309] SmallBoom.v:103715 Implicit port type (wire) for "io_out_valid",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:103200 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:106287 Implicit port type (wire) for "io_resp_valid",
 there are 92 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:68707 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:71229 Implicit port type (wire) for "io_enq_ready",
 there are 34 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:74337 Implicit port type (wire) for "io_imem_req_valid",
+[NOTE :CP0309] SmallBoom.v:76976 Implicit port type (wire) for "io_imem_req_valid",
 there are 67 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:67609 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:70113 Implicit port type (wire) for "io_enq_ready",
 there are 23 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:152382 Implicit port type (wire) for "io_forwarding_val",
+[NOTE :CP0309] SmallBoom.v:156625 Implicit port type (wire) for "io_forwarding_val",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:119136 Implicit port type (wire) for "io_dis_readys_0",
+[NOTE :CP0309] SmallBoom.v:122331 Implicit port type (wire) for "io_dis_readys_0",
 there are 32 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:14097 Implicit port type (wire) for "auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:14536 Implicit port type (wire) for "auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready",
 there are 20 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:79223 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:82018 Implicit port type (wire) for "io_resp_valid",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:82194 Implicit port type (wire) for "io_requestor_0_req_ready",
+[NOTE :CP0309] SmallBoom.v:85073 Implicit port type (wire) for "io_requestor_0_req_ready",
 there are 20 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:57680 Implicit port type (wire) for "auto_master_out_a_valid",
+[NOTE :CP0309] SmallBoom.v:60154 Implicit port type (wire) for "auto_master_out_a_valid",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:89686 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:92667 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:90199 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:93180 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:47494 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:49877 Implicit port type (wire) for "io_req_ready",
 there are 16 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:82163 Implicit port type (wire) for "auto_out_0".
+[NOTE :CP0309] SmallBoom.v:85042 Implicit port type (wire) for "auto_out_0".
 
-[NOTE :CP0309] SmallBoom.v:82180 Implicit port type (wire) for "auto_out_0",
+[NOTE :CP0309] SmallBoom.v:85059 Implicit port type (wire) for "auto_out_0",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:82188 Implicit port type (wire) for "auto_out_0".
+[NOTE :CP0309] SmallBoom.v:85067 Implicit port type (wire) for "auto_out_0".
 
-[NOTE :CP0309] SmallBoom.v:34693 Implicit port type (wire) for "auto_out_sync_0".
+[NOTE :CP0309] SmallBoom.v:36938 Implicit port type (wire) for "auto_out_sync_0".
 
-[NOTE :CP0309] SmallBoom.v:183297 Implicit port type (wire) for "auto_out_sync_0",
+[NOTE :CP0309] SmallBoom.v:187948 Implicit port type (wire) for "auto_out_sync_0",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:183320 Implicit port type (wire) for "auto_out_sync_0".
+[NOTE :CP0309] SmallBoom.v:187971 Implicit port type (wire) for "auto_out_sync_0".
 
-[NOTE :CP0309] SmallBoom.v:90593 Implicit port type (wire) for "io_out_valid",
+[NOTE :CP0309] SmallBoom.v:93574 Implicit port type (wire) for "io_out_valid",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:91436 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:94423 Implicit port type (wire) for "io_resp_valid",
 there are 10 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:64 Implicit port type (wire) for "auto_int_out_0",
+[NOTE :CP0309] SmallBoom.v:70 Implicit port type (wire) for "auto_int_out_0",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:44650 Implicit port type (wire) for "auto_int_out_0",
+[NOTE :CP0309] SmallBoom.v:46991 Implicit port type (wire) for "auto_int_out_0",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:183364 Implicit port type (wire) for "auto_int_out_0",
+[NOTE :CP0309] SmallBoom.v:188021 Implicit port type (wire) for "auto_int_out_0",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:111434 Implicit port type (wire) for "io_valid",
+[NOTE :CP0309] SmallBoom.v:114584 Implicit port type (wire) for "io_valid",
 there are 160 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:138549 Implicit port type (wire) for "io_valid",
+[NOTE :CP0309] SmallBoom.v:142668 Implicit port type (wire) for "io_valid",
 there are 164 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:112900 Implicit port type (wire) for "io_dis_readys_0",
+[NOTE :CP0309] SmallBoom.v:116062 Implicit port type (wire) for "io_dis_readys_0",
 there are 80 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:140262 Implicit port type (wire) for "io_dis_readys_0",
+[NOTE :CP0309] SmallBoom.v:144423 Implicit port type (wire) for "io_dis_readys_0",
 there are 23 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:143517 Implicit port type (wire) for "io_dis_readys_0",
+[NOTE :CP0309] SmallBoom.v:147696 Implicit port type (wire) for "io_dis_readys_0",
 there are 82 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:54676 Implicit port type (wire) for "io_read_ready",
+[NOTE :CP0309] SmallBoom.v:57114 Implicit port type (wire) for "io_read_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:32474 Implicit port type (wire) for "io_plic_valid".
+[NOTE :CP0309] SmallBoom.v:34647 Implicit port type (wire) for "io_plic_valid".
 
-[NOTE :CP0309] SmallBoom.v:151004 Implicit port type (wire) for "io_valid",
+[NOTE :CP0309] SmallBoom.v:155223 Implicit port type (wire) for "io_valid",
 there are 15 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:152465 Implicit port type (wire) for "io_new_ldq_idx",
+[NOTE :CP0309] SmallBoom.v:156708 Implicit port type (wire) for "io_new_ldq_idx",
 there are 52 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:45467 Implicit port type (wire) for "io_req_pri_rdy",
+[NOTE :CP0309] SmallBoom.v:47838 Implicit port type (wire) for "io_req_pri_rdy",
 there are 29 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:48004 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:50399 Implicit port type (wire) for "io_req_ready",
 there are 44 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:46463 Implicit port type (wire) for "io_req_pri_rdy",
+[NOTE :CP0309] SmallBoom.v:48840 Implicit port type (wire) for "io_req_pri_rdy",
 there are 29 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:85059 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:87974 Implicit port type (wire) for "io_resp_valid",
 there are 24 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:24915 Implicit port type (wire) for "auto_coupler_from_coherence_manager_binder_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:26920 Implicit port type (wire) for "auto_coupler_from_coherence_manager_binder_in_a_ready",
 there are 34 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:107148 Implicit port type (wire) for "io_result_s3".
+[NOTE :CP0309] SmallBoom.v:110247 Implicit port type (wire) for "io_result_s3".
 
-[NOTE :CP0309] SmallBoom.v:98414 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:101459 Implicit port type (wire) for "io_out",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:100324 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:103381 Implicit port type (wire) for "io_out",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:96785 Implicit port type (wire) for "io_invalidExc",
+[NOTE :CP0309] SmallBoom.v:99830 Implicit port type (wire) for "io_invalidExc",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:99219 Implicit port type (wire) for "io_invalidExc",
+[NOTE :CP0309] SmallBoom.v:102276 Implicit port type (wire) for "io_invalidExc",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:96406 Implicit port type (wire) for "io_mulAddA",
+[NOTE :CP0309] SmallBoom.v:99451 Implicit port type (wire) for "io_mulAddA",
 there are 18 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:98908 Implicit port type (wire) for "io_mulAddA",
+[NOTE :CP0309] SmallBoom.v:101965 Implicit port type (wire) for "io_mulAddA",
 there are 18 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:92335 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:95356 Implicit port type (wire) for "io_req_ready",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:32505 Implicit port type (wire) for "io_dev",
+[NOTE :CP0309] SmallBoom.v:34684 Implicit port type (wire) for "io_dev",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:49473 Implicit port type (wire) for "io_r",
+[NOTE :CP0309] SmallBoom.v:51899 Implicit port type (wire) for "io_r",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:82400 Implicit port type (wire) for "io_requestor_0_req_ready",
+[NOTE :CP0309] SmallBoom.v:85291 Implicit port type (wire) for "io_requestor_0_req_ready",
 there are 223 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:31295 Implicit port type (wire) for "auto_coupler_to_bootrom_fragmenter_out_a_valid",
+[NOTE :CP0309] SmallBoom.v:33468 Implicit port type (wire) for "auto_coupler_to_bootrom_fragmenter_out_a_valid",
 there are 38 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:88275 Implicit port type (wire) for "io_resp_valid",
+[NOTE :CP0309] SmallBoom.v:91250 Implicit port type (wire) for "io_resp_valid",
 there are 91 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:88070 Implicit port type (wire) for "io_resp_bits_data".
+[NOTE :CP0309] SmallBoom.v:91039 Implicit port type (wire) for "io_resp_bits_data".
 
-[NOTE :CP0309] SmallBoom.v:23897 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:25902 Implicit port type (wire) for "auto_in_a_ready",
 there are 16 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:44847 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:47194 Implicit port type (wire) for "io_req_ready",
 there are 20 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:2108 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:2211 Implicit port type (wire) for "io_enq_ready",
 there are 10 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:2348 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:2457 Implicit port type (wire) for "io_enq_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:189722 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:194577 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:191527 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:196412 Implicit port type (wire) for "io_enq_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:191902 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:196793 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:3933 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:4084 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:2468 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:2583 Implicit port type (wire) for "io_enq_ready",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:5319 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:5554 Implicit port type (wire) for "io_enq_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:5427 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:5668 Implicit port type (wire) for "io_enq_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:9266 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:9591 Implicit port type (wire) for "io_enq_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:9486 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:9817 Implicit port type (wire) for "io_enq_ready",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:10436 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:10779 Implicit port type (wire) for "io_enq_ready",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:10564 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:10913 Implicit port type (wire) for "io_enq_ready",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:11598 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:11995 Implicit port type (wire) for "io_enq_ready",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:11960 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:12375 Implicit port type (wire) for "io_enq_ready",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:14542 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:14981 Implicit port type (wire) for "io_enq_ready",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:2568 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:2689 Implicit port type (wire) for "io_enq_ready",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:3049 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:3176 Implicit port type (wire) for "io_enq_ready",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:3101 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:3234 Implicit port type (wire) for "io_enq_ready",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:16188 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:16645 Implicit port type (wire) for "io_enq_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:26637 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:28672 Implicit port type (wire) for "io_enq_ready",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:26817 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:28858 Implicit port type (wire) for "io_enq_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:28668 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:30733 Implicit port type (wire) for "io_enq_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:28923 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:31000 Implicit port type (wire) for "io_enq_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:32532 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:34711 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:45254 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:47613 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:45414 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:47779 Implicit port type (wire) for "io_enq_ready",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:76773 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:79520 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:76933 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:79686 Implicit port type (wire) for "io_enq_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:81035 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:83878 Implicit port type (wire) for "io_enq_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:81255 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:84104 Implicit port type (wire) for "io_enq_ready",
 there are 8 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:81455 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:84310 Implicit port type (wire) for "io_enq_ready",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:81593 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:84454 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:81753 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:84620 Implicit port type (wire) for "io_enq_ready",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:184431 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:189088 Implicit port type (wire) for "io_enq_ready",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:189068 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:193905 Implicit port type (wire) for "io_enq_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:189188 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:194031 Implicit port type (wire) for "io_enq_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:189308 Implicit port type (wire) for "io_enq_ready",
+[NOTE :CP0309] SmallBoom.v:194157 Implicit port type (wire) for "io_enq_ready",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:82291 Implicit port type (wire) for "io_in_0_ready",
+[NOTE :CP0309] SmallBoom.v:85176 Implicit port type (wire) for "io_in_0_ready",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:73102 Implicit port type (wire) for "io_out_bits",
+[NOTE :CP0309] SmallBoom.v:75690 Implicit port type (wire) for "io_out_bits",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:100911 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:103980 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:101131 Implicit port type (wire) for "io_intExceptionFlags".
+[NOTE :CP0309] SmallBoom.v:104200 Implicit port type (wire) for "io_intExceptionFlags".
 
-[NOTE :CP0309] SmallBoom.v:102222 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:105297 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:104700 Implicit port type (wire) for "io_out".
+[NOTE :CP0309] SmallBoom.v:107793 Implicit port type (wire) for "io_out".
 
-[NOTE :CP0309] SmallBoom.v:116790 Implicit port type (wire) for "io_read_ports_0_data",
+[NOTE :CP0309] SmallBoom.v:119964 Implicit port type (wire) for "io_read_ports_0_data",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:147639 Implicit port type (wire) for "io_read_ports_0_data",
+[NOTE :CP0309] SmallBoom.v:151836 Implicit port type (wire) for "io_read_ports_0_data",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:117470 Implicit port type (wire) for "io_rf_read_ports_0_addr",
+[NOTE :CP0309] SmallBoom.v:120659 Implicit port type (wire) for "io_rf_read_ports_0_addr",
 there are 94 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:116973 Implicit port type (wire) for "io_rrd_valid",
+[NOTE :CP0309] SmallBoom.v:120162 Implicit port type (wire) for "io_rrd_valid",
 there are 88 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:147898 Implicit port type (wire) for "io_rrd_valid",
+[NOTE :CP0309] SmallBoom.v:152111 Implicit port type (wire) for "io_rrd_valid",
 there are 23 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:148039 Implicit port type (wire) for "io_rrd_valid",
+[NOTE :CP0309] SmallBoom.v:152252 Implicit port type (wire) for "io_rrd_valid",
 there are 90 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:148789 Implicit port type (wire) for "io_rf_read_ports_0_addr",
+[NOTE :CP0309] SmallBoom.v:153002 Implicit port type (wire) for "io_rf_read_ports_0_addr",
 there are 118 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:126723 Implicit port type (wire) for "io_can_allocate_0",
+[NOTE :CP0309] SmallBoom.v:130392 Implicit port type (wire) for "io_can_allocate_0",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:125967 Implicit port type (wire) for "io_req_pregs_0",
+[NOTE :CP0309] SmallBoom.v:129630 Implicit port type (wire) for "io_req_pregs_0",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:134096 Implicit port type (wire) for "io_can_allocate_0",
+[NOTE :CP0309] SmallBoom.v:138161 Implicit port type (wire) for "io_can_allocate_0",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:123271 Implicit port type (wire) for "io_values_0_prs1",
+[NOTE :CP0309] SmallBoom.v:126526 Implicit port type (wire) for "io_values_0_prs1",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:123198 Implicit port type (wire) for "io_element".
+[NOTE :CP0309] SmallBoom.v:126447 Implicit port type (wire) for "io_element".
 
-[NOTE :CP0309] SmallBoom.v:131364 Implicit port type (wire) for "io_values_0_prs1",
+[NOTE :CP0309] SmallBoom.v:135045 Implicit port type (wire) for "io_values_0_prs1",
 there are 3 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:137075 Implicit port type (wire) for "io_inst_can_proceed_0",
+[NOTE :CP0309] SmallBoom.v:141152 Implicit port type (wire) for "io_inst_can_proceed_0",
 there are 105 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:29317 Implicit port type (wire) for "io_full",
+[NOTE :CP0309] SmallBoom.v:31400 Implicit port type (wire) for "io_full",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:29835 Implicit port type (wire) for "io_full",
+[NOTE :CP0309] SmallBoom.v:31942 Implicit port type (wire) for "io_full",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:30353 Implicit port type (wire) for "io_full",
+[NOTE :CP0309] SmallBoom.v:32484 Implicit port type (wire) for "io_full",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:30871 Implicit port type (wire) for "io_full",
+[NOTE :CP0309] SmallBoom.v:33026 Implicit port type (wire) for "io_full",
 there are 6 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:43490 Implicit port type (wire) for "io_sync_reset".
+[NOTE :CP0309] SmallBoom.v:45795 Implicit port type (wire) for "io_sync_reset".
 
-[NOTE :CP0309] SmallBoom.v:164792 Implicit port type (wire) for "io_curr_rob_tail_idx",
+[NOTE :CP0309] SmallBoom.v:169161 Implicit port type (wire) for "io_curr_rob_tail_idx",
 there are 36 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:89564 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:92545 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:90077 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:93058 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:97864 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:100909 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:99870 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:102927 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:101832 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:104907 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:104642 Implicit port type (wire) for "io_out".
+[NOTE :CP0309] SmallBoom.v:107735 Implicit port type (wire) for "io_out".
 
-[NOTE :CP0309] SmallBoom.v:106517 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:109616 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:98369 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:101414 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:100279 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:103336 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:106969 Implicit port type (wire) for "io_out",
+[NOTE :CP0309] SmallBoom.v:110068 Implicit port type (wire) for "io_out",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:190699 Implicit port type (wire) for "io_axi4_0_aw_ready",
+[NOTE :CP0309] SmallBoom.v:195578 Implicit port type (wire) for "io_axi4_0_aw_ready",
 there are 10 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:192879 Implicit port type (wire) for "io_axi4_0_aw_ready",
+[NOTE :CP0309] SmallBoom.v:197794 Implicit port type (wire) for "io_axi4_0_aw_ready",
 there are 10 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:193865 Implicit port type (wire) for "debug_req_valid",
+[NOTE :CP0309] SmallBoom.v:198788 Implicit port type (wire) for "debug_req_valid",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:1684 Implicit port type (wire) for "auto_buffer_out_a_valid",
+[NOTE :CP0309] SmallBoom.v:1787 Implicit port type (wire) for "auto_buffer_out_a_valid",
 there are 31 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:6513 Implicit port type (wire) for "auto_buffer_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:6838 Implicit port type (wire) for "auto_buffer_in_a_ready",
 there are 35 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:30227 Implicit port type (wire) for "auto_fragmenter_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:32358 Implicit port type (wire) for "auto_fragmenter_in_a_ready",
 there are 13 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:30745 Implicit port type (wire) for "auto_fragmenter_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:32900 Implicit port type (wire) for "auto_fragmenter_in_a_ready",
 there are 13 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:31197 Implicit port type (wire) for "auto_fragmenter_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:33370 Implicit port type (wire) for "auto_fragmenter_in_a_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:7813 Implicit port type (wire) for "auto_widget_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:8138 Implicit port type (wire) for "auto_widget_in_a_ready",
 there are 19 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:8036 Implicit port type (wire) for "auto_widget_out_a_valid",
+[NOTE :CP0309] SmallBoom.v:8361 Implicit port type (wire) for "auto_widget_out_a_valid",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:13135 Implicit port type (wire) for "auto_axi4index_in_aw_ready",
+[NOTE :CP0309] SmallBoom.v:13574 Implicit port type (wire) for "auto_axi4index_in_aw_ready",
 there are 20 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:23953 Implicit port type (wire) for "auto_picker_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:25958 Implicit port type (wire) for "auto_picker_in_a_ready",
 there are 34 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:24772 Implicit port type (wire) for "auto_binder_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:26777 Implicit port type (wire) for "auto_binder_in_a_ready",
 there are 16 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:29180 Implicit port type (wire) for "auto_buffer_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:31263 Implicit port type (wire) for "auto_buffer_in_a_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:29709 Implicit port type (wire) for "auto_fragmenter_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:31816 Implicit port type (wire) for "auto_fragmenter_in_a_ready",
 there are 13 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:43512 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:45817 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:82143 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:85016 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:183343 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:187994 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:35084 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:37335 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:42943 Implicit port type (wire) for "io_q".
+[NOTE :CP0309] SmallBoom.v:45236 Implicit port type (wire) for "io_q".
 
-[NOTE :CP0309] SmallBoom.v:8186 Implicit port type (wire) for "auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:8511 Implicit port type (wire) for "auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready",
 there are 74 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:43333 Implicit port type (wire) for "auto_in_a_ridx",
+[NOTE :CP0309] SmallBoom.v:45638 Implicit port type (wire) for "auto_in_a_ridx",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:35300 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:37557 Implicit port type (wire) for "auto_in_a_ready",
 there are 19 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:27202 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:29249 Implicit port type (wire) for "auto_in_a_ready",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:50374 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:52800 Implicit port type (wire) for "io_req_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:58329 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:60815 Implicit port type (wire) for "io_req_ready",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:185475 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:190258 Implicit port type (wire) for "auto_in_a_ready",
 there are 21 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:184532 Implicit port type (wire) for "io_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:189195 Implicit port type (wire) for "io_in_a_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:184768 Implicit port type (wire) for "io_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:189461 Implicit port type (wire) for "io_in_a_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:185004 Implicit port type (wire) for "io_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:189727 Implicit port type (wire) for "io_in_a_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:185240 Implicit port type (wire) for "io_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:189993 Implicit port type (wire) for "io_in_a_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:1485 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:1588 Implicit port type (wire) for "auto_in_a_ready",
 there are 31 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:81830 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:84703 Implicit port type (wire) for "auto_in_a_ready",
 there are 34 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:9666 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:10003 Implicit port type (wire) for "auto_in_a_ready",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:23843 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:25848 Implicit port type (wire) for "auto_in_a_ready",
 there are 16 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:27037 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:29084 Implicit port type (wire) for "auto_in_a_ready",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:29043 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:31126 Implicit port type (wire) for "auto_in_a_ready",
 there are 14 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:44042 Implicit port type (wire) for "auto_dmInner_dmInner_tl_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:46359 Implicit port type (wire) for "auto_dmInner_dmInner_tl_in_a_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:36044 Implicit port type (wire) for "auto_tl_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:38307 Implicit port type (wire) for "auto_tl_in_a_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:43716 Implicit port type (wire) for "auto_dmiXing_in_a_ridx",
+[NOTE :CP0309] SmallBoom.v:46027 Implicit port type (wire) for "auto_dmiXing_in_a_ridx",
 there are 18 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:34492 Implicit port type (wire) for "auto_dmi_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:36737 Implicit port type (wire) for "auto_dmi_in_a_ready",
 there are 10 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:35627 Implicit port type (wire) for "auto_asource_out_a_mem_0_opcode",
+[NOTE :CP0309] SmallBoom.v:37890 Implicit port type (wire) for "auto_asource_out_a_mem_0_opcode",
 there are 22 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:28760 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:30831 Implicit port type (wire) for "auto_in_a_ready",
 there are 5 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:1584 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:1687 Implicit port type (wire) for "auto_in_a_ready",
 there are 31 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:9831 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:10168 Implicit port type (wire) for "auto_in_a_ready",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:25318 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:27323 Implicit port type (wire) for "auto_in_a_ready",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:29399 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:31488 Implicit port type (wire) for "auto_in_a_ready",
 there are 13 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:29917 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:32030 Implicit port type (wire) for "auto_in_a_ready",
 there are 13 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:30435 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:32572 Implicit port type (wire) for "auto_in_a_ready",
 there are 13 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:30945 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:33106 Implicit port type (wire) for "auto_in_a_ready",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:32666 Implicit port type (wire) for "auto_int_out_1_0",
+[NOTE :CP0309] SmallBoom.v:34851 Implicit port type (wire) for "auto_int_out_1_0",
 there are 7 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:183383 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:188040 Implicit port type (wire) for "auto_in_a_ready",
 there are 4 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:5690 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:5937 Implicit port type (wire) for "auto_in_a_ready",
 there are 35 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:16451 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:16914 Implicit port type (wire) for "auto_in_a_ready",
 there are 35 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:6454 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:6779 Implicit port type (wire) for "auto_in_a_ready",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:7750 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:8075 Implicit port type (wire) for "auto_in_a_ready",
 there are 19 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:7978 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:8303 Implicit port type (wire) for "auto_in_a_ready",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:73 Implicit port type (wire) for "auto_in_1_a_ready",
+[NOTE :CP0309] SmallBoom.v:79 Implicit port type (wire) for "auto_in_1_a_ready",
 there are 56 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:9207 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:9532 Implicit port type (wire) for "auto_in_a_ready",
 there are 17 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:14486 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:14925 Implicit port type (wire) for "auto_in_a_ready",
 there are 16 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:25967 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:27978 Implicit port type (wire) for "auto_in_a_ready",
 there are 19 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:26032 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:28043 Implicit port type (wire) for "auto_in_a_ready",
 there are 44 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:33614 Implicit port type (wire) for "auto_in_a_ready",
+[NOTE :CP0309] SmallBoom.v:35835 Implicit port type (wire) for "auto_in_a_ready",
 there are 16 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:44317 Implicit port type (wire) for "auto_in_1_a_ready",
+[NOTE :CP0309] SmallBoom.v:46634 Implicit port type (wire) for "auto_in_1_a_ready",
 there are 39 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:193284 Implicit port type (wire) for "io_success".
+[NOTE :CP0309] SmallBoom.v:198199 Implicit port type (wire) for "io_success".
 
-[NOTE :CP0309] SmallBoom.v:104607 Implicit port type (wire) for "io_sigs_singleIn",
+[NOTE :CP0309] SmallBoom.v:107700 Implicit port type (wire) for "io_sigs_singleIn",
 there are 2 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:89396 Implicit port type (wire) for "io_sigs_ren2",
+[NOTE :CP0309] SmallBoom.v:92377 Implicit port type (wire) for "io_sigs_ren2",
 there are 9 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:44665 Implicit port type (wire) for "io_req_ready",
+[NOTE :CP0309] SmallBoom.v:47006 Implicit port type (wire) for "io_req_ready",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:49385 Implicit port type (wire) for "io_y_ppn",
+[NOTE :CP0309] SmallBoom.v:51811 Implicit port type (wire) for "io_y_ppn",
 there are 12 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:82363 Implicit port type (wire) for "io_y".
+[NOTE :CP0309] SmallBoom.v:85254 Implicit port type (wire) for "io_y".
 
-[NOTE :CP0309] SmallBoom.v:82377 Implicit port type (wire) for "io_y_ppn",
+[NOTE :CP0309] SmallBoom.v:85268 Implicit port type (wire) for "io_y_ppn",
 there are 8 more instances of this message.
 
-[NOTE :CP0309] SmallBoom.v:193845 Implicit port type (wire) for "out".
+[NOTE :CP0309] SmallBoom.v:198766 Implicit port type (wire) for "out".
 
 [INFO :EL0526] Design Elaboration...
 
-[NOTE :EL0503] SmallBoom.v:193281 Top level module "work@TestHarness".
+[NOTE :EL0503] SmallBoom.v:198196 Top level module "work@TestHarness".
 
-[NOTE :EL0503] SmallBoom.v:193844 Top level module "work@plusarg_reader".
+[NOTE :EL0503] SmallBoom.v:198765 Top level module "work@plusarg_reader".
 
 [NOTE :EL0504] Multiple top level modules in design.
 
diff --git a/third_party/tests/YosysDsp/YosysDsp.log b/third_party/tests/YosysDsp/YosysDsp.log
index 8f75df8..c22001a 100644
--- a/third_party/tests/YosysDsp/YosysDsp.log
+++ b/third_party/tests/YosysDsp/YosysDsp.log
@@ -30,7 +30,7 @@
 
 [WARNI:PA0205] iiravg.v:41 No timescale set for "iiravg".
 
-[WARNI:PA0205] lfsr.v:43 No timescale set for "lfsr".
+[WARNI:PA0205] lfsr.v:44 No timescale set for "lfsr".
 
 [WARNI:PA0205] lfsr_fib.v:41 No timescale set for "lfsr_fib".
 
@@ -70,7 +70,7 @@
 
 [INFO :CP0303] iiravg.v:41 Compile module "work@iiravg".
 
-[INFO :CP0303] lfsr.v:43 Compile module "work@lfsr".
+[INFO :CP0303] lfsr.v:44 Compile module "work@lfsr".
 
 [INFO :CP0303] lfsr_fib.v:41 Compile module "work@lfsr_fib".
 
@@ -112,7 +112,7 @@
 
 [NOTE :EL0503] iiravg.v:41 Top level module "work@iiravg".
 
-[NOTE :EL0503] lfsr.v:43 Top level module "work@lfsr".
+[NOTE :EL0503] lfsr.v:44 Top level module "work@lfsr".
 
 [NOTE :EL0503] lfsr_fib.v:41 Top level module "work@lfsr_fib".