commit | 58c278f2b5f720b9ad3c471b38dbd212bc358afe | [log] [tgz] |
---|---|---|
author | Alain Dargelas <5085492+alainmarcel@users.noreply.github.com> | Thu Nov 28 23:16:29 2019 -1000 |
committer | GitHub <noreply@github.com> | Thu Nov 28 23:16:29 2019 -1000 |
tree | c795c7a0c9a28bdc6bea2979c202fe37d91c6ab1 | |
parent | ca734e9dab3897f7602b5b5eb6385a24e88a21a2 [diff] | |
parent | b84179db6b45b27b2b2cc851fbcf4bb953541ed5 [diff] |
Merge pull request #113 from alainmarcel/alainmarcel-patch-1 test update
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models.
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALL
make make install (/usr/local/bin and /usr/local/lib/surelog by default, use DESTDIR= for alternative locations)
For more build/test options and system requirements for building see src/README
file.
The executable is located here (If not installed in:
STANDARD VERILOG COMMAND LINE:
FLOWS OPTIONS:
TRACES OPTIONS:
OUTPUT OPTIONS:
RETURN CODE
The file slformatmsg.py
illustrates how messages can be reformated.
The file src/API/slSV3_1aPythonListener.py
illustrates how a listener can be created to listen to the Parser AST.
A simple example of creating a new error message and generating errors can be found here: python_listener.py
A simple example for design-level data model exploration can be found here: myscriptPerDesign.py
The complete Python API is described in the following files: SLAPI.h
vobjecttypes
Waivers can be installed in slwaivers.py files in the execution directory or install directory /usr/local/lib/surelog/python
src/README
file.