diff --git a/tests/regression.tcl b/tests/regression.tcl
index c611d93..62e63bd 100755
--- a/tests/regression.tcl
+++ b/tests/regression.tcl
@@ -92,7 +92,6 @@
 set LONG_TESTS(YosysOldI2c) 1
 set LONG_TESTS(YosysOldSimpleSpi) 1
 set LONG_TESTS(YosysOldAes) 1
-set LONG_TESTS(YosysOldSpi) 1
 
 if [regexp {show_diff}  $argv] {
     regsub "show_diff" $argv "" argv
@@ -305,11 +304,12 @@
     set w2 8
     set w4 8
     set w3 18
-    set w5 12
+    set w5 8
+    set w6 6
     set MEM 0
-    set sep +-[string repeat - $w1]-+-[string repeat - $w2]-+-[string repeat - $w2]-+-[string repeat - $w4]-+-[string repeat - $w2]-+-[string repeat - $w4]-+-[string repeat - $w2]-+-[string repeat - $w5]-+-[string repeat - $w5]-+
+    set sep +-[string repeat - $w1]-+-[string repeat - $w2]-+-[string repeat - $w6]-+-[string repeat - $w4]-+-[string repeat - $w2]-+-[string repeat - $w4]-+-[string repeat - $w2]-+-[string repeat - $w5]-+-[string repeat - $w5]-+
     log $sep
-    log [format "| %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s |" $w1 "TESTNAME" $w2 "STATUS"  $w2 "FATAL"  $w2 "SYNTAX" $w4 "ERROR" $w2 "WARNING"  $w4 "NOTE"  $w5 "ELAPSED TIME" $w5 "MEM(Mb)"]
+    log [format "| %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s |" $w1 "TESTNAME" $w2 "STATUS" $w6 "FATAL"  $w2 "SYNTAX" $w4 "ERROR" $w2 "WARNING"  $w4 "NOTE"  $w5 "TIME" $w5 "MEM(Mb)"]
     log $sep
 
     foreach testname [array names TESTS] {
@@ -492,12 +492,12 @@
 		set PRIOR_MAX_TIME $prior_elapsed
 	    }
 	    if [expr ($elapsed > $prior_elapsed) && ($no_previous_time_content == 0)] {
-		set SPEED [format "%-*s %-*s " 4 "${elapsed}s" 5 "(+[expr $elapsed - $prior_elapsed]s)"]
+		set SPEED [format "%-*s %-*s " 2 "${elapsed}s" 4 "(+[expr $elapsed - $prior_elapsed])"]
 		set FASTER_OR_SLOWER 1
 	    } elseif [expr ($elapsed == $prior_elapsed) || ($no_previous_time_content)] {
 		set SPEED [format "%-*s " 4 "${elapsed}s"]
 	    } else {
-		set SPEED [format "%-*s %-*s " 4 "${elapsed}s" 5 "(-[expr $prior_elapsed - $elapsed]s)"]
+		set SPEED [format "%-*s %-*s " 2 "${elapsed}s" 4 "(-[expr $prior_elapsed - $elapsed])"]
 		set FASTER_OR_SLOWER 1
 	    }
 	
@@ -508,12 +508,12 @@
 		set PRIOR_MAX_MEM $prior_mem
 	    }
 	    if [expr ($mem > $prior_mem)  && ($no_previous_time_content == 0)] {
-		set MEM  [format "%-*s %-*s " 4 "${mem}" 5 "(+[expr $mem - $prior_mem])"]
+		set MEM  [format "%-*s %-*s " 3 "${mem}" 3 "(+[expr $mem - $prior_mem])"]
 		set DIFF_MEM 1
 	    } elseif  [expr ($mem == $prior_mem) || ($no_previous_time_content)] {
 		set MEM [format "%-*s " 4 "${mem}"]
 	    } else {
-		set MEM  [format "%-*s %-*s " 4 "${mem}" 5 "(-[expr $prior_mem - $mem])"]
+		set MEM  [format "%-*s %-*s " 3 "${mem}" 3 "(-[expr $prior_mem - $mem])"]
 		set DIFF_MEM 1
 	    }
 
@@ -550,7 +550,7 @@
 	    set fatals "SEGFAULT"
 	}
 
-	log [format " %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s |" $w2 $passstatus $w2 $fatals $w2 $syntax $w4 $errors $w2 $warnings $w4 $notes $w5 $SPEED $w5 $MEM ]
+	log [format " %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s | %-*s |" $w2 $passstatus $w6 $fatals $w2 $syntax $w4 $errors $w2 $warnings $w4 $notes $w5 $SPEED $w5 $MEM ]
 	flush stdout
 	if {$SHOW_DETAILS == 1} {
 	    log "Log:\n"
diff --git a/third_party/tests/YosysOldTests/spi/YosysOldSpi.log b/third_party/tests/YosysOldTests/spi/YosysOldSpi.log
index aef128c..0dd2bcc 100644
--- a/third_party/tests/YosysOldTests/spi/YosysOldSpi.log
+++ b/third_party/tests/YosysOldTests/spi/YosysOldSpi.log
@@ -1,267 +1,28 @@
-********************************************
-*  SURELOG System Verilog Compiler/Linter  *
-********************************************
-
-[INFO :CM0023] Creating log file ../../../build/tests/YosysOldSpi/slpp_unit/surelog.log.
-
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[ERROR:PP0101] rtl/spi_top.v:42 Cannot open include file "spi_defines.v".
-
-[ERROR:PP0101] rtl/spi_top.v:43 Cannot open include file "timescale.v".
-
-[ERROR:PP0102] rtl/spi_top.v:72 Unknown macro "SPI_SS_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:82 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PP0102] rtl/spi_top.v:83 Unknown macro "SPI_CTRL_BIT_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:84 Unknown macro "SPI_SS_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:86 Unknown macro "SPI_MAX_CHAR".
-
-[ERROR:PP0102] rtl/spi_top.v:89 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:104 Unknown macro "SPI_OFS_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:104 Unknown macro "SPI_DEVIDE".
-
-[ERROR:PP0102] rtl/spi_top.v:105 Unknown macro "SPI_OFS_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:105 Unknown macro "SPI_CTRL".
-
-[ERROR:PP0102] rtl/spi_top.v:106 Unknown macro "SPI_OFS_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:106 Unknown macro "SPI_TX_0".
-
-[ERROR:PP0102] rtl/spi_top.v:107 Unknown macro "SPI_OFS_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:107 Unknown macro "SPI_TX_1".
-
-[ERROR:PP0102] rtl/spi_top.v:108 Unknown macro "SPI_OFS_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:108 Unknown macro "SPI_TX_2".
-
-[ERROR:PP0102] rtl/spi_top.v:109 Unknown macro "SPI_OFS_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:109 Unknown macro "SPI_TX_3".
-
-[ERROR:PP0102] rtl/spi_top.v:110 Unknown macro "SPI_OFS_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:110 Unknown macro "SPI_SS".
-
-[ERROR:PP0102] rtl/spi_top.v:115 Unknown macro "SPI_OFS_BITS".
-
-[ERROR:PP0102] rtl/spi_top.v:128 Unknown macro "SPI_RX_0".
-
-[ERROR:PP0102] rtl/spi_top.v:128 Unknown macro "SPI_MAX_CHAR".
-
-[ERROR:PP0102] rtl/spi_top.v:129 Unknown macro "SPI_RX_1".
-
-[ERROR:PP0102] rtl/spi_top.v:130 Unknown macro "SPI_RX_2".
-
-[ERROR:PP0102] rtl/spi_top.v:131 Unknown macro "SPI_RX_3".
-
-[ERROR:PP0102] rtl/spi_top.v:134 Unknown macro "SPI_CTRL".
-
-[ERROR:PP0102] rtl/spi_top.v:134 Unknown macro "SPI_CTRL_BIT_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:135 Unknown macro "SPI_DEVIDE".
-
-[ERROR:PP0102] rtl/spi_top.v:135 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PP0102] rtl/spi_top.v:136 Unknown macro "SPI_SS".
-
-[ERROR:PP0102] rtl/spi_top.v:136 Unknown macro "SPI_SS_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:177 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PP0102] rtl/spi_top.v:215 Unknown macro "SPI_CTRL_BIT_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:221 Unknown macro "SPI_CTRL_BIT_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:224 Unknown macro "SPI_CTRL_GO".
-
-[ERROR:PP0102] rtl/spi_top.v:227 Unknown macro "SPI_CTRL_RX_NEGEDGE".
-
-[ERROR:PP0102] rtl/spi_top.v:228 Unknown macro "SPI_CTRL_TX_NEGEDGE".
-
-[ERROR:PP0102] rtl/spi_top.v:229 Unknown macro "SPI_CTRL_GO".
-
-[ERROR:PP0102] rtl/spi_top.v:230 Unknown macro "SPI_CTRL_CHAR_LEN".
-
-[ERROR:PP0102] rtl/spi_top.v:231 Unknown macro "SPI_CTRL_LSB".
-
-[ERROR:PP0102] rtl/spi_top.v:232 Unknown macro "SPI_CTRL_IE".
-
-[ERROR:PP0102] rtl/spi_top.v:233 Unknown macro "SPI_CTRL_ASS".
-
-[ERROR:PP0102] rtl/spi_top.v:239 Unknown macro "SPI_SS_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:273 Unknown macro "SPI_SS_NB".
-
-[ERROR:PP0102] rtl/spi_top.v:279 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0101] rtl/spi_shift.v:41 Cannot open include file "spi_defines.v".
-
-[ERROR:PP0101] rtl/spi_shift.v:42 Cannot open include file "timescale.v".
-
-[ERROR:PP0102] rtl/spi_shift.v:55 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:65 Unknown macro "SPI_MAX_CHAR".
-
-[ERROR:PP0102] rtl/spi_shift.v:73 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:74 Unknown macro "SPI_MAX_CHAR".
-
-[ERROR:PP0102] rtl/spi_shift.v:75 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:76 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:82 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:83 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:84 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:95 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:99 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:101 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:122 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0102] rtl/spi_shift.v:129 Unknown macro "SPI_MAX_CHAR".
-
-[ERROR:PP0102] rtl/spi_shift.v:234 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PP0101] rtl/spi_clgen.v:41 Cannot open include file "spi_defines.v".
-
-[ERROR:PP0101] rtl/spi_clgen.v:42 Cannot open include file "timescale.v".
-
-[ERROR:PP0102] rtl/spi_clgen.v:53 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PP0102] rtl/spi_clgen.v:62 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PP0102] rtl/spi_clgen.v:67 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PP0102] rtl/spi_clgen.v:68 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PP0102] rtl/spi_clgen.v:74 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PP0102] rtl/spi_clgen.v:80 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PA0207] rtl/spi_top.v:70 Syntax error: no viable alternative at input 'output          [SURELOG_MACRO_NOT_DEFINED:SPI_SS_NB!!!',
-  output          [SURELOG_MACRO_NOT_DEFINED:SPI_SS_NB!!! -1:0] ss_pad_o;         // slave select
-                   ^-- ../../../build/tests/YosysOldSpi/slpp_unit/work/rtl/spi_top.v:70 col:19.
-
-[ERROR:PA0203] rtl/spi_top.v:70 Unknown macro "SPI_SS_NB".
-
-[ERROR:PA0203] rtl/spi_top.v:102 Unknown macro "SPI_DEVIDE".
-
-[ERROR:PA0203] rtl/spi_top.v:103 Unknown macro "SPI_CTRL".
-
-[ERROR:PA0203] rtl/spi_top.v:104 Unknown macro "SPI_TX_0".
-
-[ERROR:PA0203] rtl/spi_top.v:105 Unknown macro "SPI_TX_1".
-
-[ERROR:PA0203] rtl/spi_top.v:106 Unknown macro "SPI_TX_2".
-
-[ERROR:PA0203] rtl/spi_top.v:107 Unknown macro "SPI_TX_3".
-
-[ERROR:PA0203] rtl/spi_top.v:108 Unknown macro "SPI_SS".
-
-[ERROR:PA0203] rtl/spi_top.v:114 Unknown macro "SPI_RX_0".
-
-[ERROR:PA0203] rtl/spi_top.v:114 Unknown macro "SPI_MAX_CHAR".
-
-[ERROR:PA0203] rtl/spi_top.v:115 Unknown macro "SPI_RX_1".
-
-[ERROR:PA0203] rtl/spi_top.v:116 Unknown macro "SPI_RX_2".
-
-[ERROR:PA0203] rtl/spi_top.v:117 Unknown macro "SPI_RX_3".
-
-[ERROR:PA0203] rtl/spi_top.v:118 Unknown macro "SPI_CTRL".
-
-[ERROR:PA0203] rtl/spi_top.v:119 Unknown macro "SPI_DEVIDE".
-
-[ERROR:PA0203] rtl/spi_top.v:120 Unknown macro "SPI_SS".
-
-[ERROR:PA0203] rtl/spi_top.v:161 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PA0203] rtl/spi_top.v:171 Unknown macro "SPI_CTRL_BIT_NB".
-
-[ERROR:PA0203] rtl/spi_top.v:195 Unknown macro "SPI_SS_NB".
-
-[ERROR:PA0203] rtl/spi_top.v:201 Unknown macro "SPI_SS_NB".
-
-[ERROR:PA0207] timescale.v:13 Syntax error: no viable alternative at input 'input [SURELOG_MACRO_NOT_DEFINED:SPI_CHAR_LEN_BITS!!!',
-  input [SURELOG_MACRO_NOT_DEFINED:SPI_CHAR_LEN_BITS!!! -1:0] len;          // data len in bits (minus one)
-         ^-- ../../../build/tests/YosysOldSpi/slpp_unit/work/rtl/spi_shift.v:53 col:9.
-
-[ERROR:PA0203] timescale.v:13 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PA0203] timescale.v:40 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PA0203] timescale.v:41 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PA0203] timescale.v:42 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PA0203] timescale.v:53 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PA0203] timescale.v:57 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PA0203] timescale.v:59 Unknown macro "SPI_CHAR_LEN_BITS".
-
-[ERROR:PA0203] timescale.v:87 Unknown macro "SPI_MAX_CHAR".
-
-[ERROR:PA0207] timescale.v:11 Syntax error: no viable alternative at input 'input     [SURELOG_MACRO_NOT_DEFINED:SPI_DIVIDER_LEN!!!',
-  input     [SURELOG_MACRO_NOT_DEFINED:SPI_DIVIDER_LEN!!! -1:0] divider;  // clock divider (output clock is divided by this value)
-             ^-- ../../../build/tests/YosysOldSpi/slpp_unit/work/rtl/spi_clgen.v:51 col:13.
-
-[ERROR:PA0203] timescale.v:11 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PA0203] timescale.v:25 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PA0203] timescale.v:26 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PA0203] timescale.v:32 Unknown macro "SPI_DIVIDER_LEN".
-
-[ERROR:PA0203] timescale.v:38 Unknown macro "SPI_DIVIDER_LEN".
-
-[WARNI:PA0205] cache/synth.v:1 No timescale set for "spi_clgen".
-
-[WARNI:PA0205] cache/synth.v:359 No timescale set for "spi_shift".
-
-[WARNI:PA0205] cache/synth.v:4166 No timescale set for "spi_top".
+[INFO :CM0023] Creating log file ../../../../build/tests/YosysOldSpi/slpp_all/surelog.log.
 
 [INFO :CP0300] Compilation...
 
-[INFO :CP0303] cache/synth.v:1 Compile module "work@spi_clgen".
+[INFO :CP0303] rtl/spi_clgen.v:43 Compile module "work@spi_clgen".
 
-[INFO :CP0303] cache/synth.v:359 Compile module "work@spi_shift".
+[INFO :CP0303] rtl/spi_shift.v:43 Compile module "work@spi_shift".
 
-[INFO :CP0303] cache/synth.v:4166 Compile module "work@spi_top".
+[INFO :CP0303] rtl/spi_top.v:44 Compile module "work@spi_top".
 
-[NOTE :CP0309] cache/synth.v:359 Implicit port type (wire) for "last",
+[INFO :CP0302] builtin.sv:4 Compile class "work@mailbox".
+
+[INFO :CP0302] builtin.sv:33 Compile class "work@process".
+
+[INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
+
+[NOTE :CP0309] rtl/spi_shift.v:45 Implicit port type (wire) for "last",
 there are 1 more instances of this message.
 
-[NOTE :CP0309] cache/synth.v:4166 Implicit port type (wire) for "wb_err_o",
+[NOTE :CP0309] rtl/spi_top.v:48 Implicit port type (wire) for "wb_err_o",
 there are 3 more instances of this message.
 
 [INFO :EL0526] Design Elaboration...
 
-[NOTE :EL0503] cache/synth.v:4166 Top level module "work@spi_top".
-
-[WARNI:EL0505] timescale.v:2 Multiply defined module "work@spi_clgen",
-               cache/synth.v:1 previous definition.
-
-[WARNI:EL0505] timescale.v:2 Multiply defined module "work@spi_shift",
-               cache/synth.v:359 previous definition.
-
-[WARNI:EL0505] rtl/spi_top.v:43 Multiply defined module "work@spi_top",
-               cache/synth.v:4166 previous definition.
+[NOTE :EL0503] rtl/spi_top.v:44 Top level module "work@spi_top".
 
 [NOTE :EL0508] Nb Top level modules: 1.
 
@@ -269,16 +30,11 @@
 
 [NOTE :EL0510] Nb instances: 3.
 
-[NOTE :EL0511] Nb leaf instances: 2.
+[NOTE :EL0511] Nb leaf instances: 0.
 
 [  FATAL] : 0
-[  ERROR] : 109
-[WARNING] : 6
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 0
 [   NOTE] : 7
 
-********************************************
-*   End SURELOG SVerilog Compiler/Linter   *
-********************************************
-
-2.43user 0.04system 0:02.48elapsed 99%CPU (0avgtext+0avgdata 119652maxresident)k
-432inputs+392outputs (0major+29881minor)pagefaults 0swaps
diff --git a/third_party/tests/YosysOldTests/spi/YosysOldSpi.sl b/third_party/tests/YosysOldTests/spi/YosysOldSpi.sl
index 23bd568..d7b681c 100644
--- a/third_party/tests/YosysOldTests/spi/YosysOldSpi.sl
+++ b/third_party/tests/YosysOldTests/spi/YosysOldSpi.sl
@@ -1 +1 @@
-  -writepp -parse   -mt  max  -nopython -fileunit  */*.v +incdir+. -nobuiltin -nocache
+-parse  rtl/spi_clgen.v rtl/spi_defines.v rtl/spi_shift.v rtl/spi_top.v +incdir+rtl/+. -nocache