| commit | 061462f2b9ae814ea80dedf1fea331ab1192ad24 | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Mon Nov 18 14:55:41 2019 -0800 |
| committer | Henner Zeller <h.zeller@acm.org> | Mon Nov 18 14:56:34 2019 -0800 |
| tree | 74ef60d77411c1cc9c7494742e44eb42ec8dd64a | |
| parent | 55913e9a1eb0be5450a79c790585e6857ea4e37c [diff] |
Have all includes absolute from the built-root. This simplifies the compile command, makes everything more readable and is according to the style recommendations in https://google.github.io/styleguide/cppguide.html#Names_and_Order_of_Includes Signed-off-by: Henner Zeller <h.zeller@acm.org>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.
The executable is located here:
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
`default_nettype in pre-processor's output