| commit | 37a2bd86b2e6da7c4722b8bc419e63ac66da06e8 | [log] [tgz] |
|---|---|---|
| author | Alain <alainmarcel@yahoo.com> | Sun Nov 17 18:05:02 2019 -0800 |
| committer | Alain <alainmarcel@yahoo.com> | Sun Nov 17 18:05:09 2019 -0800 |
| tree | 5cb278db0a1b7154924de7d3e72b2359aa81e30f | |
| parent | 8c7aeafa434cc7415632a897ff6b55cf53d155a2 [diff] |
Fix incorrect regression flag Signed-off-by: Alain <alainmarcel@yahoo.com>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.
The executable is located here:
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
`default_nettype in pre-processor's output