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foss-fpga-tools/third_party/Surelog/36edd2bd845c2e56e36b75d2696ae7a98914e2a8/./SVIncCompil/Testcases/YosysTests/frontends/read_verilog_generate
tree: e73f7f63c4403fc4c182b39bf366699330404fc0
  1. testbench.v
  2. top.v