diff --git a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/surelog.log b/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/surelog.log
deleted file mode 100644
index 097fa38..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/surelog.log
+++ /dev/null
@@ -1,51 +0,0 @@
-********************************************
-*  SURELOG System Verilog Compiler/Linter  *
-********************************************
-
-Copyright (c) 2017-2019 ACE Cloud,
-Authorized used only.
-
-VERSION: 0.05
-BUILT  : Nov  3 2019
-DATE   : 2019-11-03.21:37:16
-COMMAND: -writepp -parse -mt max -nopython -fileunit rtl/aes_cipher_top.v rtl/aes_key_expand_128.v rtl/aes_rcon.v rtl/aes_sbox.v sim/bench.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
-
-[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
-
-[INFO :CM0024] Executing with 4 threads.
-
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[INFO :CP0300] Compilation...
-
-[INFO :CP0303] rtl/aes_cipher_top.v:48 Compile module "work@aes_cipher_top".
-
-[INFO :CP0303] rtl/aes_rcon.v:42 Compile module "work@aes_rcon".
-
-[INFO :CP0303] rtl/aes_key_expand_128.v:42 Compile module "work@aes_key_expand_128".
-
-[INFO :CP0303] rtl/aes_sbox.v:43 Compile module "work@aes_sbox".
-
-[INFO :CP0303] sim/bench.v:70 Compile module "work@testbench".
-
-[INFO :EL0526] Design Elaboration...
-
-[NOTE :EL0503] sim/bench.v:70 Top level module "work@testbench".
-
-[NOTE :EL0508] Nb Top level modules: 1.
-
-[NOTE :EL0509] Max instance depth: 4.
-
-[NOTE :EL0510] Nb instances: 44.
-
-[NOTE :EL0511] Nb leaf instances: 40.
-
-[  FATAL] : 0
-[  ERROR] : 0
-[WARNING] : 0
-[   NOTE] : 5
-
-********************************************
-*   End SURELOG SVerilog Compiler/Linter   *
-********************************************
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_cipher_top.v b/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_cipher_top.v
deleted file mode 100644
index ff20ec6..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_cipher_top.v
+++ /dev/null
@@ -1,482 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  AES Cipher Top Level                                       ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
-////                         www.asics.ws                        ////
-////                         rudi@asics.ws                       ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
- 
-//// Modified to achieve 5 cycles - stage  functionality 	     ////
-//// By Tariq Bashir Ahmad					     				 //// 	
-////  tariq.bashir@gmail.com					     			 ////
-////  http://www.ecs.umass.edu/~tbashir				    		 ////
-
-
-
-`timescale 1 ns/1 ps
-
-module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out);
-
-input		clk, rst;
-input		ld;
-output		done;
-input	[127:0]	key;
-input	[127:0]	text_in;
-output	[127:0]	text_out;
-
-
-////////////////////////////////////////////////////////////////////
-//
-// Local Wires
-//
-
-wire	[31:0]	w0, w1, w2, w3, w4, w5, w6, w7;
-/*wire	[127:0]	key_odd,key_even;
-*/
-reg	[127:0]	text_in_r;
-reg	[127:0]	text_out;
-
-reg	[127:0]	text_out_temp;
-
-reg	[7:0]	sa00, sa01, sa02, sa03;
-reg	[7:0]	sa10, sa11, sa12, sa13;
-reg	[7:0]	sa20, sa21, sa22, sa23;
-reg	[7:0]	sa30, sa31, sa32, sa33;
-
-wire	[7:0]	sa00_next, sa01_next, sa02_next, sa03_next;
-wire	[7:0]	sa10_next, sa11_next, sa12_next, sa13_next;
-wire	[7:0]	sa20_next, sa21_next, sa22_next, sa23_next;
-wire	[7:0]	sa30_next, sa31_next, sa32_next, sa33_next;
-
-wire	[7:0]	sa00_sub, sa01_sub, sa02_sub, sa03_sub;
-wire	[7:0]	sa10_sub, sa11_sub, sa12_sub, sa13_sub;
-wire  [7:0]	sa20_sub, sa21_sub, sa22_sub, sa23_sub;
-wire	[7:0]	sa30_sub, sa31_sub, sa32_sub, sa33_sub;
-
-wire	[7:0]	sa00_sr, sa01_sr, sa02_sr, sa03_sr;
-wire	[7:0]	sa10_sr, sa11_sr, sa12_sr, sa13_sr;
-wire	[7:0]	sa20_sr, sa21_sr, sa22_sr, sa23_sr;
-wire	[7:0]	sa30_sr, sa31_sr, sa32_sr, sa33_sr;
-
-wire	[7:0]	sa00_mc, sa01_mc, sa02_mc, sa03_mc;
-wire	[7:0]	sa10_mc, sa11_mc, sa12_mc, sa13_mc;
-wire	[7:0]	sa20_mc, sa21_mc, sa22_mc, sa23_mc;
-wire	[7:0]	sa30_mc, sa31_mc, sa32_mc, sa33_mc;
-
-
-wire	[7:0]	sa00_next_round2, sa01_next_round2, sa02_next_round2, sa03_next_round2;
-wire	[7:0]	sa10_next_round2, sa11_next_round2, sa12_next_round2, sa13_next_round2;
-wire	[7:0]	sa20_next_round2, sa21_next_round2, sa22_next_round2, sa23_next_round2;
-wire	[7:0]	sa30_next_round2, sa31_next_round2, sa32_next_round2, sa33_next_round2;
-
-wire	[7:0]	sa00_sub_round2, sa01_sub_round2, sa02_sub_round2, sa03_sub_round2;
-wire	[7:0]	sa10_sub_round2, sa11_sub_round2, sa12_sub_round2, sa13_sub_round2;
-wire  [7:0]	sa20_sub_round2, sa21_sub_round2, sa22_sub_round2, sa23_sub_round2;
-wire	[7:0]	sa30_sub_round2, sa31_sub_round2, sa32_sub_round2, sa33_sub_round2;
-
-wire	[7:0]	sa00_sr_round2, sa01_sr_round2, sa02_sr_round2, sa03_sr_round2;
-wire	[7:0]	sa10_sr_round2, sa11_sr_round2, sa12_sr_round2, sa13_sr_round2;
-wire	[7:0]	sa20_sr_round2, sa21_sr_round2, sa22_sr_round2, sa23_sr_round2;
-wire	[7:0]	sa30_sr_round2, sa31_sr_round2, sa32_sr_round2, sa33_sr_round2;
-
-wire	[7:0]	sa00_mc_round2, sa01_mc_round2, sa02_mc_round2, sa03_mc_round2;
-wire	[7:0]	sa10_mc_round2, sa11_mc_round2, sa12_mc_round2, sa13_mc_round2;
-wire	[7:0]	sa20_mc_round2, sa21_mc_round2, sa22_mc_round2, sa23_mc_round2;
-wire	[7:0]	sa30_mc_round2, sa31_mc_round2, sa32_mc_round2, sa33_mc_round2;
-
-
-
-
-reg		done, ld_r;
-reg	[3:0]	dcnt;
-reg 		done2;
-
-////////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-always @(posedge clk)
-begin
-	if(~rst)	begin dcnt <=  4'h0;	 end
-	else
-	if(ld)	begin	dcnt <=  4'h6;	 end
-	else
-	if(|dcnt) begin	dcnt <=  dcnt - 4'h1;  end
-
-end
-
-always @(posedge clk) done <=  !(|dcnt[3:1]) & dcnt[0] & !ld;
-always @(posedge clk) if(ld) text_in_r <=  text_in;
-always @(posedge clk) ld_r <=  ld;
-
-
-
-////////////////////////////////////////////////////////////////////
-// key expansion
-
-
-aes_key_expand_128 u0(
-	.clk(		clk	),
-	.kld(		ld_r	),
-	.key(		key	),
-	.w0(		w0	),
-	.w1(		w1	),
-	.w2(		w2	),
-	.w3(		w3	),
-	.w4_reg(		w4	),
-	.w5_reg(		w5	),
-	.w6_reg(		w6	),
-	.w7_reg(		w7	)
-							);
-/*assign key_odd  = {w0,w1,w2,w3};
-assign key_even = {w4,w5,w6,w7};
-*/
-
-/*assign {w0,w1,w2,w3} = 128'h0;
-
-assign {w4,w5,w6,w7} = 128'h62636363626363636263636362636363;
-*/							
-// Initial Permutation (AddRoundKey)
-//
-/*
-always @(posedge clk)
-begin
-  w0 <= w0_net;
-  w1 <= w1_net;
-  w2 <= w2_net;
-  w3 <= w3_net;
-  w4 <= w4_net;
-  w5 <= w5_net;
-  w6 <= w6_net;
-  w7 <= w7_net;
-end
-*/
-always @(posedge clk) 
-begin
-   	sa33 <=  ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_mc_round2 ^ w3[07:00];
-    	sa23 <=  ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_mc_round2 ^ w3[15:08];
-    	sa13 <=  ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_mc_round2 ^ w3[23:16];
-    	sa03 <=  ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_mc_round2 ^ w3[31:24];
-    	sa32 <=  ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_mc_round2 ^ w2[07:00];
-    	sa22 <=  ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_mc_round2 ^ w2[15:08];
-    	sa12 <=  ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_mc_round2 ^ w2[23:16];
-    	sa02 <=  ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_mc_round2 ^ w2[31:24];
-    	sa31 <=  ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_mc_round2 ^ w1[07:00];
-    	sa21 <=  ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_mc_round2 ^ w1[15:08];
-    	sa11 <=  ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_mc_round2 ^ w1[23:16];
-    	sa01 <=  ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_mc_round2 ^ w1[31:24];
-    	sa30 <=  ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_mc_round2 ^ w0[07:00];
-    	sa20 <=  ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_mc_round2 ^ w0[15:08];
-    	sa10 <=  ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_mc_round2 ^ w0[23:16];
-    	sa00 <=  ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_mc_round2 ^ w0[31:24];
-		
-		/*$strobe($time,": roundkeyodd = %h\n",{w0,w1,w2,w3});
-		$strobe($time,": state is %h\n",{sa00, sa01, sa02, sa03,
-													 sa10, sa11, sa12, sa13,
-													 sa20, sa21, sa22, sa23,
-													 sa30, sa31, sa32, sa33});*/
-		
-end
-
-////////////////////////////////////////////////////////////////////
-//
-// Modules instantiation
-//
-
-//sbox lookup
-aes_sbox us00(	.a(	sa00	), .d(	sa00_sub	));
-aes_sbox us01(	.a(	sa01	), .d(	sa01_sub	));
-aes_sbox us02(	.a(	sa02	), .d(	sa02_sub	));
-aes_sbox us03(	.a(	sa03	), .d(	sa03_sub	));
-aes_sbox us10(	.a(	sa10	), .d(	sa10_sub	));
-aes_sbox us11(	.a(	sa11	), .d(	sa11_sub	));
-aes_sbox us12(	.a(	sa12	), .d(	sa12_sub	));
-aes_sbox us13(	.a(	sa13	), .d(	sa13_sub	));
-aes_sbox us20(	.a(	sa20	), .d(	sa20_sub	));
-aes_sbox us21(	.a(	sa21	), .d(	sa21_sub	));
-aes_sbox us22(	.a(	sa22	), .d(	sa22_sub	));
-aes_sbox us23(	.a(	sa23	), .d(	sa23_sub	));
-aes_sbox us30(	.a(	sa30	), .d(	sa30_sub	));
-aes_sbox us31(	.a(	sa31	), .d(	sa31_sub	));
-aes_sbox us32(	.a(	sa32	), .d(	sa32_sub	));
-aes_sbox us33(	.a(	sa33	), .d(	sa33_sub	));
-
-////////////////////////////////////////////////////////////////////
-//
-// Round Permutations
-//
-
-assign sa00_sr = sa00_sub;		//
-assign sa01_sr = sa01_sub;		//no shift
-assign sa02_sr = sa02_sub;		//
-assign sa03_sr = sa03_sub;		//
-
-assign sa10_sr = sa11_sub;		//
-assign sa11_sr = sa12_sub;		// left shift by 1
-assign sa12_sr = sa13_sub;		//
-assign sa13_sr = sa10_sub;		//
-
-assign sa20_sr = sa22_sub;		//
-assign sa21_sr = sa23_sub;		//	left shift by 2
-assign sa22_sr = sa20_sub;		//
-assign sa23_sr = sa21_sub;		//
-
-assign sa30_sr = sa33_sub;		//
-assign sa31_sr = sa30_sub;		// left shift by 3
-assign sa32_sr = sa31_sub;		//
-assign sa33_sr = sa32_sub;		//
-
-// mix column operation
-assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc}  = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
-assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc}  = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
-assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc}  = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
-assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc}  = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
-
-//// add round key
-assign sa00_next_round2 = sa00_mc ^ w4[31:24];		
-assign sa01_next_round2 = sa01_mc ^ w5[31:24];
-assign sa02_next_round2 = sa02_mc ^ w6[31:24];
-assign sa03_next_round2 = sa03_mc ^ w7[31:24];
-assign sa10_next_round2 = sa10_mc ^ w4[23:16];
-assign sa11_next_round2 = sa11_mc ^ w5[23:16];
-assign sa12_next_round2 = sa12_mc ^ w6[23:16];
-assign sa13_next_round2 = sa13_mc ^ w7[23:16];
-assign sa20_next_round2 = sa20_mc ^ w4[15:08];
-assign sa21_next_round2 = sa21_mc ^ w5[15:08];
-assign sa22_next_round2 = sa22_mc ^ w6[15:08];
-assign sa23_next_round2 = sa23_mc ^ w7[15:08];
-assign sa30_next_round2 = sa30_mc ^ w4[07:00];
-assign sa31_next_round2 = sa31_mc ^ w5[07:00];
-assign sa32_next_round2 = sa32_mc ^ w6[07:00];
-assign sa33_next_round2 = sa33_mc ^ w7[07:00];
-
-
-always @(posedge clk)
-begin 
-	  
-	 /* $strobe($time,": roundkeyodd = %h, text_out_odd is %h\n",{w0,w1,w2,w3},text_out_temp);
-	  $strobe($time,": roundkeyeven is %h\n",{w4,w5,w6,w7}); 	*/
-	  text_out_temp[127:120] <=  sa00_sr ^ w4[31:24];	 
-	  text_out_temp[095:088] <=  sa01_sr ^ w5[31:24];	 
-          text_out_temp[063:056] <=  sa02_sr ^ w6[31:24];	 
-	  text_out_temp[031:024] <=  sa03_sr ^ w7[31:24];	 
-	  text_out_temp[119:112] <=  sa10_sr ^ w4[23:16];	 
-	  text_out_temp[087:080] <=  sa11_sr ^ w5[23:16];	 
-	  text_out_temp[055:048] <=  sa12_sr ^ w6[23:16];	 
-	  text_out_temp[023:016] <=  sa13_sr ^ w7[23:16];	 
-	  text_out_temp[111:104] <=  sa20_sr ^ w4[15:08];	 
-	  text_out_temp[079:072] <=  sa21_sr ^ w5[15:08];	 
-	  text_out_temp[047:040] <=  sa22_sr ^ w6[15:08];	 
-	  text_out_temp[015:008] <=  sa23_sr ^ w7[15:08];	 
-	  text_out_temp[103:096] <=  sa30_sr ^ w4[07:00];	 
-	  text_out_temp[071:064] <=  sa31_sr ^ w5[07:00];	 
-	  text_out_temp[039:032] <=  sa32_sr ^ w6[07:00];	 
-	  text_out_temp[007:000] <=  sa33_sr ^ w7[07:00];    
-end
-
-
-
-
-//////////////////////  round i + 1 //////////////////////////////////
-//sbox lookup
-aes_sbox us00_round2(	.a(	sa00_next_round2	), .d(	sa00_sub_round2	));
-aes_sbox us01_round2(	.a(	sa01_next_round2	), .d(	sa01_sub_round2	));
-aes_sbox us02_round2(	.a(	sa02_next_round2	), .d(	sa02_sub_round2	));
-aes_sbox us03_round2(	.a(	sa03_next_round2	), .d(	sa03_sub_round2	));
-aes_sbox us10_round2(	.a(	sa10_next_round2	), .d(	sa10_sub_round2	));
-aes_sbox us11_round2(	.a(	sa11_next_round2	), .d(	sa11_sub_round2	));
-aes_sbox us12_round2(	.a(	sa12_next_round2	), .d(	sa12_sub_round2	));
-aes_sbox us13_round2(	.a(	sa13_next_round2	), .d(	sa13_sub_round2	));
-aes_sbox us20_round2(	.a(	sa20_next_round2	), .d(	sa20_sub_round2	));
-aes_sbox us21_round2(	.a(	sa21_next_round2	), .d(	sa21_sub_round2	));
-aes_sbox us22_round2(	.a(	sa22_next_round2	), .d(	sa22_sub_round2	));
-aes_sbox us23_round2(	.a(	sa23_next_round2	), .d(	sa23_sub_round2	));
-aes_sbox us30_round2(	.a(	sa30_next_round2	), .d(	sa30_sub_round2	));
-aes_sbox us31_round2(	.a(	sa31_next_round2	), .d(	sa31_sub_round2	));
-aes_sbox us32_round2(	.a(	sa32_next_round2	), .d(	sa32_sub_round2	));
-aes_sbox us33_round2(	.a(	sa33_next_round2	), .d(	sa33_sub_round2	));
-
-
-// Round Permutations
-//
-
-assign sa00_sr_round2 = sa00_sub_round2;		//
-assign sa01_sr_round2 = sa01_sub_round2;		//no shift
-assign sa02_sr_round2 = sa02_sub_round2;		//
-assign sa03_sr_round2 = sa03_sub_round2;		//
-
-assign sa10_sr_round2 = sa11_sub_round2;		//
-assign sa11_sr_round2 = sa12_sub_round2;		// left shift by 1
-assign sa12_sr_round2 = sa13_sub_round2;		//
-assign sa13_sr_round2 = sa10_sub_round2;		//
-
-assign sa20_sr_round2 = sa22_sub_round2;		//
-assign sa21_sr_round2 = sa23_sub_round2;		//	left shift by 2
-assign sa22_sr_round2 = sa20_sub_round2;		//
-assign sa23_sr_round2 = sa21_sub_round2;		//
-
-assign sa30_sr_round2 = sa33_sub_round2;		//
-assign sa31_sr_round2 = sa30_sub_round2;		// left shift by 3
-assign sa32_sr_round2 = sa31_sub_round2;		//
-assign sa33_sr_round2 = sa32_sub_round2;		//
-
-// mix column operation
-assign {sa00_mc_round2, sa10_mc_round2, sa20_mc_round2, sa30_mc_round2}  = mix_col(sa00_sr_round2,sa10_sr_round2,sa20_sr_round2,sa30_sr_round2);
-assign {sa01_mc_round2, sa11_mc_round2, sa21_mc_round2, sa31_mc_round2}  = mix_col(sa01_sr_round2,sa11_sr_round2,sa21_sr_round2,sa31_sr_round2);
-assign {sa02_mc_round2, sa12_mc_round2, sa22_mc_round2, sa32_mc_round2}  = mix_col(sa02_sr_round2,sa12_sr_round2,sa22_sr_round2,sa32_sr_round2);
-assign {sa03_mc_round2, sa13_mc_round2, sa23_mc_round2, sa33_mc_round2}  = mix_col(sa03_sr_round2,sa13_sr_round2,sa23_sr_round2,sa33_sr_round2);
-
-////////////////////////////////////////////////////////////////////
-//
-// Final text output
-//
-
-
-always @(posedge clk)
- begin 
-		/*  $strobe($time,": round_key2 is %h\n",{w4,w5,w6,w7});
-		  $strobe($time,": roundkeyeven = %h, text_out_even is %h\n",{w4,w5,w6,w7},text_out);*/
-		  text_out[127:120] <=  sa00_sr_round2 ^ w0[31:24];	 
-		  text_out[095:088] <=  sa01_sr_round2 ^ w1[31:24];	 
-		  text_out[063:056] <=  sa02_sr_round2 ^ w2[31:24];	 
-		  text_out[031:024] <=  sa03_sr_round2 ^ w3[31:24];	 
-		  text_out[119:112] <=  sa10_sr_round2 ^ w0[23:16];	 
-		  text_out[087:080] <=  sa11_sr_round2 ^ w1[23:16];	 
-		  text_out[055:048] <=  sa12_sr_round2 ^ w2[23:16];	 
-		  text_out[023:016] <=  sa13_sr_round2 ^ w3[23:16];	 
-		  text_out[111:104] <=  sa20_sr_round2 ^ w0[15:08];	 
-		  text_out[079:072] <=  sa21_sr_round2 ^ w1[15:08];	 
-		  text_out[047:040] <=  sa22_sr_round2 ^ w2[15:08];	 
-		  text_out[015:008] <=  sa23_sr_round2 ^ w3[15:08];	 
-		  text_out[103:096] <=  sa30_sr_round2 ^ w0[07:00];	 
-		  text_out[071:064] <=  sa31_sr_round2 ^ w1[07:00];	 
-		  text_out[039:032] <=  sa32_sr_round2 ^ w2[07:00];	 
-		  text_out[007:000] <=  sa33_sr_round2 ^ w3[07:00];
-	end
-
-
-/* -----\/----- EXCLUDED -----\/-----
-always @(posedge clk)
-	begin
-/-*	$strobe($time,": text_out_temp is %h\n",text_out_temp);
-
-
-*-/	/-*
-	$strobe($time,": subbytes is %h\n",{sa00_sub, sa01_sub, sa02_sub, sa03_sub,
-													 sa10_sub, sa11_sub, sa12_sub, sa13_sub,
-													 sa20_sub, sa21_sub, sa22_sub, sa23_sub,
-													 sa30_sub, sa31_sub, sa32_sub, sa33_sub});
-													 
-	$strobe($time,": shiftrows is %h\n",{sa00_sr, sa01_sr, sa02_sr, sa03_sr,
-													  sa10_sr, sa11_sr, sa12_sr, sa13_sr,
-													  sa20_sr, sa21_sr, sa22_sr, sa23_sr,
-													  sa30_sr, sa31_sr, sa32_sr, sa33_sr});
-													  
-	$strobe($time,": mixcolumn is %h\n",{sa00_mc, sa01_mc, sa02_mc, sa03_mc,
-													  sa10_mc, sa11_mc, sa12_mc, sa13_mc,
-													  sa20_mc, sa21_mc, sa22_mc, sa23_mc,
-													  sa30_mc, sa31_mc, sa32_mc, sa33_mc});
-	
-	$strobe($time,": sa_next_into_even is %h\n",{sa00_next_round2, sa01_next_round2, sa02_next_round2, sa03_next_round2,
-																 sa10_next_round2, sa11_next_round2, sa12_next_round2, sa13_next_round2,
-																 sa20_next_round2, sa21_next_round2, sa22_next_round2, sa23_next_round2,
-																 sa30_next_round2, sa31_next_round2, sa32_next_round2, sa33_next_round2});
-																 
-	$strobe($time,": subbytes_e is %h\n",{sa00_sub_round2, sa01_sub_round2, sa02_sub_round2, sa03_sub_round2,
-													 sa10_sub_round2, sa11_sub_round2, sa12_sub_round2, sa13_sub_round2,
-													 sa20_sub_round2, sa21_sub_round2, sa22_sub_round2, sa23_sub_round2,
-													 sa30_sub_round2, sa31_sub_round2, sa32_sub_round2, sa33_sub_round2});
-													 
-	$strobe($time,": shiftrows_e is %h\n",{sa00_sr_round2, sa01_sr_round2, sa02_sr_round2, sa03_sr_round2,
-													  sa10_sr_round2, sa11_sr_round2, sa12_sr_round2, sa13_sr_round2,
-													  sa20_sr_round2, sa21_sr_round2, sa22_sr_round2, sa23_sr_round2,
-													  sa30_sr_round2, sa31_sr_round2, sa32_sr_round2, sa33_sr_round2});
-													  
-	$strobe($time,": mixcolumn_e is %h\n",{sa00_mc_round2, sa01_mc_round2, sa02_mc_round2, sa03_mc_round2,
-													  sa10_mc_round2, sa11_mc_round2, sa12_mc_round2, sa13_mc_round2,
-													  sa20_mc_round2, sa21_mc_round2, sa22_mc_round2, sa23_mc_round2,
-													  sa30_mc_round2, sa31_mc_round2, sa32_mc_round2, sa33_mc_round2});																
-	*-/															 
-	end
-	
-	
-/-*
-always @(posedge clk)
-       begin
-				if(done)
-						begin
-							text_out_64 <= text_out[127:64];
-//							done2 <= 1;
-						end
-				else if(~done)
-							text_out_64 <= text_out[63:0];
-		end
-	*-/	 
-		 
-/-*
-always @(posedge clk)
-			 begin
-				if(done2)
-					begin
-						text_out_64 <= text_out[63:0];
-					end	
-		 end
-*-/		 
- -----/\----- EXCLUDED -----/\----- */
-////////////////////////////////////////////////////////////////////
-//
-// Generic Functions
-//
-
-function [31:0] mix_col;
-input	[7:0]	s0,s1,s2,s3;
-//reg	[7:0]	s0_o,s1_o,s2_o,s3_o;
-begin
-mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
-mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
-mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
-mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
-end
-endfunction
-
-function [7:0] xtime;
-input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
-endfunction
-
-
-
-endmodule
-
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_key_expand_128.v b/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_key_expand_128.v
deleted file mode 100644
index 21d302c..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_key_expand_128.v
+++ /dev/null
@@ -1,110 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  AES Key Expand Block (for 128 bit keys)                    ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
-////                         www.asics.ws                        ////
-////                         rudi@asics.ws                       ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-
-`timescale 1 ns/1 ps
-
-module aes_key_expand_128(clk, kld, key, w0,w1,w2,w3,w4_reg,w5_reg,w6_reg,w7_reg);
-input		clk;
-input		kld;
-input	[127:0]	key;
-output reg	[31:0]	w0,w1,w2,w3;
-		 reg [31:0]	   w4,w5,w6,w7;
-
-output reg   [31:0]   w4_reg,w5_reg,w6_reg,w7_reg;
-wire	[31:0]	tmp_w,tmp_w2;
-wire	[31:0]	subword, subword2;
-wire	[31:0]	rcon, rcon2;			//round constant
-
-
-
-always @(posedge clk)
-begin
-	w4_reg <=  w4;
-	w5_reg <=  w5;
-	w6_reg <=  w6;
-	w7_reg <=  w7;
-/*   $strobe($time,": next round_key is %h\n",{w4_reg,w5_reg,w6_reg,w7_reg}); 
-*/end
-
-		
-always @*
-begin
- 
-w0 =  kld ? key[127:096] :w4_reg^subword2^{rcon[31:24],24'b0};
-w1 =  kld ? key[095:064] :w5_reg^w4_reg^subword2^{rcon[31:24],24'b0};
-w2 =  kld ? key[063:032] :w6_reg^w5_reg^w4_reg^subword2^{rcon[31:24],24'b0};
-w3 =  kld ? key[031:000] :w7_reg^w6_reg^w5_reg^w4_reg^subword2^{rcon[31:24],24'b0};
-
-w4 =  (1'b0)? key[127:096]^subword^{8'h01,24'b0} : w0^subword^{rcon2[31:24],24'b0};
-w5 =  (1'b0)? key[095:064]^key[127:096]^subword^{8'h01,24'b0} :w1^w0^subword^{rcon2[31:24],24'b0};
-w6 =  (1'b0)? key[063:032]^key[095:064]^key[127:096]^subword^{8'h01,24'b0} : w2^w1^w0^subword^{rcon2[31:24],24'b0}; 
-w7 =  (1'b0)? key[127:096]^key[095:064]^key[063:032]^key[031:000]^subword^{8'h01,24'b0} : w3^w2^w1^w0^subword^{rcon2[31:24],24'b0};
-
-/*$display($time,": rcon is %d, rcon2 is %d\n",rcon[31:24],rcon2[31:24]);*/
-/*$display($time,": round_key is %h\n",{w0,w1,w2,w3}); 	
-$display($time,": next_round_key is %h\n",{w4,w5,w6,w7});*/
-end
-
-
-/*assign tmp_w =  w3;  //subword
-assign tmp_w2 = w7 ;  //subword2
-*/
-/*
-assign subword[31:24]     = aes_sbox(tmp_w[23:16]);
-assign subword[23:16]	  = aes_sbox(tmp_w[15:08]);
-assign subword[15:08]	  = aes_sbox(tmp_w[07:00]);
-assign subword[07:00]     = aes_sbox(tmp_w[31:24]);
-*/
-
-aes_sbox inst1(	.a(w3[23:16]), .d(subword[31:24]));
-aes_sbox inst2(	.a(w3[15:08]), .d(subword[23:16]));
-aes_sbox inst3(	.a(w3[07:00]), .d(subword[15:08]));
-aes_sbox inst4(	.a(w3[31:24]), .d(subword[07:00])); 
-aes_rcon inst5(.clk(clk), .kld(kld), .out(rcon[31:24]), .out2(rcon2[31:24]));
-
-
-aes_sbox u4(	.a(w7_reg[23:16]), .d(subword2[31:24]));
-aes_sbox u5(	.a(w7_reg[15:08]), .d(subword2[23:16]));
-aes_sbox u6(	.a(w7_reg[07:00]), .d(subword2[15:08]));
-aes_sbox u7(	.a(w7_reg[31:24]), .d(subword2[07:00])); 
-
-
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_rcon.v b/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_rcon.v
deleted file mode 100644
index 7c11e12..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_rcon.v
+++ /dev/null
@@ -1,90 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  AES RCON Block                                             ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
-////                         www.asics.ws                        ////
-////                         rudi@asics.ws                       ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-
-`timescale 1 ns/1 ps
-
-module aes_rcon(clk, kld,out,out2);
-
-input		clk;
-input		kld;
-
-output reg  [7:0] out,out2;
-
-reg	[3:0]	rcnt_reg;
-wire	[3:0]	rcnt_next;
-
-
-assign rcnt_next = (kld) ? 0 : rcnt_reg+2;
-
-
-always @*
-begin
-		out  = kld ? 8'h01:frcon(rcnt_next-1);
-		out2 = kld ? 8'h01:frcon(rcnt_next); 
-end		 
-
-
-always @(posedge clk)
-begin
-
-		rcnt_reg <= rcnt_next;
-/*		$strobe($time,": out is %h, out2 is %h\n",out,out2);
-*/	
-end	
-
-
-
-function [7:0]	frcon;
-input	[3:0]	i;
-case(i)	// synopsys parallel_case
-   4'h0: frcon=8'h01;		//1
-   4'h1: frcon=8'h02;		//x
-   4'h2: frcon=8'h04;		//x^2
-   4'h3: frcon=8'h08;		//x^3
-   4'h4: frcon=8'h10;		//x^4
-   4'h5: frcon=8'h20;		//x^5
-   4'h6: frcon=8'h40;		//x^6
-   4'h7: frcon=8'h80;		//x^7
-   4'h8: frcon=8'h1b;		//x^8
-   4'h9: frcon=8'h36;		//x^9
-   default: frcon=8'h00;
-endcase
-endfunction
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_sbox.v b/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_sbox.v
deleted file mode 100644
index 251f6bf..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/rtl/aes_sbox.v
+++ /dev/null
@@ -1,310 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-////  AES SBOX (ROM)                                             ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
-////                         www.asics.ws                        ////
-////                         rudi@asics.ws                       ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-
-`timescale 1 ns/1 ps
-
-
-module aes_sbox(a,d);
-input	[7:0]	a;
-output	[7:0]	d;
-reg	[7:0]	d;
-
-always @(a)
-	case(a)		// synopsys full_case parallel_case
-	   8'h00: d=8'h63;
-	   8'h01: d=8'h7c;
-	   8'h02: d=8'h77;
-	   8'h03: d=8'h7b;
-	   8'h04: d=8'hf2;
-	   8'h05: d=8'h6b;
-	   8'h06: d=8'h6f;
-	   8'h07: d=8'hc5;
-	   8'h08: d=8'h30;
-	   8'h09: d=8'h01;
-	   8'h0a: d=8'h67;
-	   8'h0b: d=8'h2b;
-	   8'h0c: d=8'hfe;
-	   8'h0d: d=8'hd7;
-	   8'h0e: d=8'hab;
-	   8'h0f: d=8'h76;
-	   8'h10: d=8'hca;
-	   8'h11: d=8'h82;
-	   8'h12: d=8'hc9;
-	   8'h13: d=8'h7d;
-	   8'h14: d=8'hfa;
-	   8'h15: d=8'h59;
-	   8'h16: d=8'h47;
-	   8'h17: d=8'hf0;
-	   8'h18: d=8'had;
-	   8'h19: d=8'hd4;
-	   8'h1a: d=8'ha2;
-	   8'h1b: d=8'haf;
-	   8'h1c: d=8'h9c;
-	   8'h1d: d=8'ha4;
-	   8'h1e: d=8'h72;
-	   8'h1f: d=8'hc0;
-	   8'h20: d=8'hb7;
-	   8'h21: d=8'hfd;
-	   8'h22: d=8'h93;
-	   8'h23: d=8'h26;
-	   8'h24: d=8'h36;
-	   8'h25: d=8'h3f;
-	   8'h26: d=8'hf7;
-	   8'h27: d=8'hcc;
-	   8'h28: d=8'h34;
-	   8'h29: d=8'ha5;
-	   8'h2a: d=8'he5;
-	   8'h2b: d=8'hf1;
-	   8'h2c: d=8'h71;
-	   8'h2d: d=8'hd8;
-	   8'h2e: d=8'h31;
-	   8'h2f: d=8'h15;
-	   8'h30: d=8'h04;
-	   8'h31: d=8'hc7;
-	   8'h32: d=8'h23;
-	   8'h33: d=8'hc3;
-	   8'h34: d=8'h18;
-	   8'h35: d=8'h96;
-	   8'h36: d=8'h05;
-	   8'h37: d=8'h9a;
-	   8'h38: d=8'h07;
-	   8'h39: d=8'h12;
-	   8'h3a: d=8'h80;
-	   8'h3b: d=8'he2;
-	   8'h3c: d=8'heb;
-	   8'h3d: d=8'h27;
-	   8'h3e: d=8'hb2;
-	   8'h3f: d=8'h75;
-	   8'h40: d=8'h09;
-	   8'h41: d=8'h83;
-	   8'h42: d=8'h2c;
-	   8'h43: d=8'h1a;
-	   8'h44: d=8'h1b;
-	   8'h45: d=8'h6e;
-	   8'h46: d=8'h5a;
-	   8'h47: d=8'ha0;
-	   8'h48: d=8'h52;
-	   8'h49: d=8'h3b;
-	   8'h4a: d=8'hd6;
-	   8'h4b: d=8'hb3;
-	   8'h4c: d=8'h29;
-	   8'h4d: d=8'he3;
-	   8'h4e: d=8'h2f;
-	   8'h4f: d=8'h84;
-	   8'h50: d=8'h53;
-	   8'h51: d=8'hd1;
-	   8'h52: d=8'h00;
-	   8'h53: d=8'hed;
-	   8'h54: d=8'h20;
-	   8'h55: d=8'hfc;
-	   8'h56: d=8'hb1;
-	   8'h57: d=8'h5b;
-	   8'h58: d=8'h6a;
-	   8'h59: d=8'hcb;
-	   8'h5a: d=8'hbe;
-	   8'h5b: d=8'h39;
-	   8'h5c: d=8'h4a;
-	   8'h5d: d=8'h4c;
-	   8'h5e: d=8'h58;
-	   8'h5f: d=8'hcf;
-	   8'h60: d=8'hd0;
-	   8'h61: d=8'hef;
-	   8'h62: d=8'haa;
-	   8'h63: d=8'hfb;
-	   8'h64: d=8'h43;
-	   8'h65: d=8'h4d;
-	   8'h66: d=8'h33;
-	   8'h67: d=8'h85;
-	   8'h68: d=8'h45;
-	   8'h69: d=8'hf9;
-	   8'h6a: d=8'h02;
-	   8'h6b: d=8'h7f;
-	   8'h6c: d=8'h50;
-	   8'h6d: d=8'h3c;
-	   8'h6e: d=8'h9f;
-	   8'h6f: d=8'ha8;
-	   8'h70: d=8'h51;
-	   8'h71: d=8'ha3;
-	   8'h72: d=8'h40;
-	   8'h73: d=8'h8f;
-	   8'h74: d=8'h92;
-	   8'h75: d=8'h9d;
-	   8'h76: d=8'h38;
-	   8'h77: d=8'hf5;
-	   8'h78: d=8'hbc;
-	   8'h79: d=8'hb6;
-	   8'h7a: d=8'hda;
-	   8'h7b: d=8'h21;
-	   8'h7c: d=8'h10;
-	   8'h7d: d=8'hff;
-	   8'h7e: d=8'hf3;
-	   8'h7f: d=8'hd2;
-	   8'h80: d=8'hcd;
-	   8'h81: d=8'h0c;
-	   8'h82: d=8'h13;
-	   8'h83: d=8'hec;
-	   8'h84: d=8'h5f;
-	   8'h85: d=8'h97;
-	   8'h86: d=8'h44;
-	   8'h87: d=8'h17;
-	   8'h88: d=8'hc4;
-	   8'h89: d=8'ha7;
-	   8'h8a: d=8'h7e;
-	   8'h8b: d=8'h3d;
-	   8'h8c: d=8'h64;
-	   8'h8d: d=8'h5d;
-	   8'h8e: d=8'h19;
-	   8'h8f: d=8'h73;
-	   8'h90: d=8'h60;
-	   8'h91: d=8'h81;
-	   8'h92: d=8'h4f;
-	   8'h93: d=8'hdc;
-	   8'h94: d=8'h22;
-	   8'h95: d=8'h2a;
-	   8'h96: d=8'h90;
-	   8'h97: d=8'h88;
-	   8'h98: d=8'h46;
-	   8'h99: d=8'hee;
-	   8'h9a: d=8'hb8;
-	   8'h9b: d=8'h14;
-	   8'h9c: d=8'hde;
-	   8'h9d: d=8'h5e;
-	   8'h9e: d=8'h0b;
-	   8'h9f: d=8'hdb;
-	   8'ha0: d=8'he0;
-	   8'ha1: d=8'h32;
-	   8'ha2: d=8'h3a;
-	   8'ha3: d=8'h0a;
-	   8'ha4: d=8'h49;
-	   8'ha5: d=8'h06;
-	   8'ha6: d=8'h24;
-	   8'ha7: d=8'h5c;
-	   8'ha8: d=8'hc2;
-	   8'ha9: d=8'hd3;
-	   8'haa: d=8'hac;
-	   8'hab: d=8'h62;
-	   8'hac: d=8'h91;
-	   8'had: d=8'h95;
-	   8'hae: d=8'he4;
-	   8'haf: d=8'h79;
-	   8'hb0: d=8'he7;
-	   8'hb1: d=8'hc8;
-	   8'hb2: d=8'h37;
-	   8'hb3: d=8'h6d;
-	   8'hb4: d=8'h8d;
-	   8'hb5: d=8'hd5;
-	   8'hb6: d=8'h4e;
-	   8'hb7: d=8'ha9;
-	   8'hb8: d=8'h6c;
-	   8'hb9: d=8'h56;
-	   8'hba: d=8'hf4;
-	   8'hbb: d=8'hea;
-	   8'hbc: d=8'h65;
-	   8'hbd: d=8'h7a;
-	   8'hbe: d=8'hae;
-	   8'hbf: d=8'h08;
-	   8'hc0: d=8'hba;
-	   8'hc1: d=8'h78;
-	   8'hc2: d=8'h25;
-	   8'hc3: d=8'h2e;
-	   8'hc4: d=8'h1c;
-	   8'hc5: d=8'ha6;
-	   8'hc6: d=8'hb4;
-	   8'hc7: d=8'hc6;
-	   8'hc8: d=8'he8;
-	   8'hc9: d=8'hdd;
-	   8'hca: d=8'h74;
-	   8'hcb: d=8'h1f;
-	   8'hcc: d=8'h4b;
-	   8'hcd: d=8'hbd;
-	   8'hce: d=8'h8b;
-	   8'hcf: d=8'h8a;
-	   8'hd0: d=8'h70;
-	   8'hd1: d=8'h3e;
-	   8'hd2: d=8'hb5;
-	   8'hd3: d=8'h66;
-	   8'hd4: d=8'h48;
-	   8'hd5: d=8'h03;
-	   8'hd6: d=8'hf6;
-	   8'hd7: d=8'h0e;
-	   8'hd8: d=8'h61;
-	   8'hd9: d=8'h35;
-	   8'hda: d=8'h57;
-	   8'hdb: d=8'hb9;
-	   8'hdc: d=8'h86;
-	   8'hdd: d=8'hc1;
-	   8'hde: d=8'h1d;
-	   8'hdf: d=8'h9e;
-	   8'he0: d=8'he1;
-	   8'he1: d=8'hf8;
-	   8'he2: d=8'h98;
-	   8'he3: d=8'h11;
-	   8'he4: d=8'h69;
-	   8'he5: d=8'hd9;
-	   8'he6: d=8'h8e;
-	   8'he7: d=8'h94;
-	   8'he8: d=8'h9b;
-	   8'he9: d=8'h1e;
-	   8'hea: d=8'h87;
-	   8'heb: d=8'he9;
-	   8'hec: d=8'hce;
-	   8'hed: d=8'h55;
-	   8'hee: d=8'h28;
-	   8'hef: d=8'hdf;
-	   8'hf0: d=8'h8c;
-	   8'hf1: d=8'ha1;
-	   8'hf2: d=8'h89;
-	   8'hf3: d=8'h0d;
-	   8'hf4: d=8'hbf;
-	   8'hf5: d=8'he6;
-	   8'hf6: d=8'h42;
-	   8'hf7: d=8'h68;
-	   8'hf8: d=8'h41;
-	   8'hf9: d=8'h99;
-	   8'hfa: d=8'h2d;
-	   8'hfb: d=8'h0f;
-	   8'hfc: d=8'hb0;
-	   8'hfd: d=8'h54;
-	   8'hfe: d=8'hbb;
-	   8'hff: d=8'h16;
-	endcase
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/sim/bench.v b/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/sim/bench.v
deleted file mode 100644
index e2411d7..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/aes_5cycle_2stage/slpp_unit/work/sim/bench.v
+++ /dev/null
@@ -1,509 +0,0 @@
-
-///////////////////////////////////////////////////////////////////
-////                                                             ////
-////  AES Test Bench                                             ////
-////                                                             ////
-////                                                             ////
-////  Author: Rudolf Usselmann                                   ////
-////          rudi@asics.ws                                      ////
-////                                                             ////
-////                                                             ////
-////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-////                                                             ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
-////                         www.asics.ws                        ////
-////                         rudi@asics.ws                       ////
-////                                                             ////
-//// This source file may be used and distributed without        ////
-//// restriction provided that this copyright statement is not   ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-////                                                             ////
-////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
-//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
-//// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
-/////////////////////////////////////////////////////////////////////
-
-//  CVS Log
-//
-//  $Id: test_bench_top.v,v 1.1.1.1 2005/08/03 14:59:38 kesava Exp $
-//
-//  $Date: 2005/08/03 14:59:38 $
-//  $Revision: 1.1.1.1 $
-//  $Author: kesava $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: test_bench_top.v,v $
-//               Revision 1.1.1.1  2005/08/03 14:59:38  kesava
-//               ssi3Aug05
-//
-//               Revision 1.2  2002/11/12 16:10:12  rudi
-//
-//               Improved test bench, added missing timescale file.
-//
-//               Revision 1.1.1.1  2002/11/09 11:22:56  rudi
-//               Initial Checkin
-//
-//
-//
-//
-//
-//
-`timescale 1ns/1ps
-//`include "timescale.v"
-//`delay_mode_path
-module testbench;
-
-  reg		clk;
-  reg		rst;
-
-  reg [383:0]   tv[512:0];	// Test vectors
-  wire [383:0]  tmp;
-  reg		kld;
-  wire [127:0]  key, plain, ciph;
-  wire [127:0]  text_in;
-  wire [127:0]  text_out;
-  wire [127:0]  text_out2;
-  reg [127:0]   text_exp;
-  wire		done, done2;
-  integer       n, error_cnt;
-
-
-  initial
-    begin
-      $display("\n\n");
-      $display("*****************************************************");
-      $display("* AES Test bench ...");
-      $display("*****************************************************");
-      $display("\n");
-      
-      // while(1)
-        begin
-	  kld = 0;
-	  rst = 0;
-	  error_cnt = 0;
-	  repeat(4)	@(posedge clk);
-	  rst = 1;
-	  repeat(20)	@(posedge clk);
-
-	  $display("");
-	  $display("");
-	  $display("Started random test ...");
-
-          tv[0]= 384'h00000000000000000000000000000000f34481ec3cc627bacd5dc3fb08f273e60336763e966d92595a567cc9ce537f5e;
-          tv[1]= 384'h000000000000000000000000000000009798c4640bad75c7c3227db910174e72a9a1631bf4996954ebc093957b234589;
-          tv[2]= 384'h0000000000000000000000000000000096ab5c2ff612d9dfaae8c31f30c42168ff4f8391a6a40ca5b25d23bedd44a597;
-          tv[3]= 384'h000000000000000000000000000000006a118a874519e64e9963798a503f1d35dc43be40be0e53712f7e2bf5ca707209;
-          tv[4]= 384'h00000000000000000000000000000000cb9fceec81286ca3e989bd979b0cb28492beedab1895a94faa69b632e5cc47ce;
-          tv[5]= 384'h00000000000000000000000000000000b26aeb1874e47ca8358ff22378f09144459264f4798f6a78bacb89c15ed3d601;
-          tv[6]= 384'h0000000000000000000000000000000058c8e00b2631686d54eab84b91f0aca108a4e2efec8a8e3312ca7460b9040bbf;
-          tv[7]= 384'h10a58869d74be5a374cf867cfb473859000000000000000000000000000000006d251e6944b051e04eaa6fb4dbf78465;
-          tv[8]= 384'hcaea65cdbb75e9169ecd22ebe6e54675000000000000000000000000000000006e29201190152df4ee058139def610bb;
-          tv[9]= 384'ha2e2fa9baf7d20822ca9f0542f764a4100000000000000000000000000000000c3b44b95d9d2f25670eee9a0de099fa3;
-          tv[10]= 384'hb6364ac4e1de1e285eaf144a2415f7a0000000000000000000000000000000005d9b05578fc944b3cf1ccf0e746cd581;
-          tv[11]= 384'h64cf9c7abc50b888af65f49d521944b200000000000000000000000000000000f7efc89d5dba578104016ce5ad659c05;
-          tv[12]= 384'h47d6742eefcc0465dc96355e851b64d9000000000000000000000000000000000306194f666d183624aa230a8b264ae7;
-          tv[13]= 384'h3eb39790678c56bee34bbcdeccf6cdb500000000000000000000000000000000858075d536d79ccee571f7d7204b1f67;
-          tv[14]= 384'h64110a924f0743d500ccadae72c134270000000000000000000000000000000035870c6a57e9e92314bcb8087cde72ce;
-          tv[15]= 384'h18d8126516f8a12ab1a36d9f04d68e51000000000000000000000000000000006c68e9be5ec41e22c825b7c7affb4363;
-          tv[16]= 384'hf530357968578480b398a3c251cd109300000000000000000000000000000000f5df39990fc688f1b07224cc03e86cea;
-          tv[17]= 384'hda84367f325d42d601b4326964802e8e00000000000000000000000000000000bba071bcb470f8f6586e5d3add18bc66;
-          tv[18]= 384'he37b1c6aa2846f6fdb413f238b089f230000000000000000000000000000000043c9f7e62f5d288bb27aa40ef8fe1ea8;
-          tv[19]= 384'h6c002b682483e0cabcc731c253be5674000000000000000000000000000000003580d19cff44f1014a7c966a69059de5;
-          tv[20]= 384'h143ae8ed6555aba96110ab58893a8ae100000000000000000000000000000000806da864dd29d48deafbe764f8202aef;
-          tv[21]= 384'hb69418a85332240dc82492353956ae0c00000000000000000000000000000000a303d940ded8f0baff6f75414cac5243;
-          tv[22]= 384'h71b5c08a1993e1362e4d0ce9b22b78d500000000000000000000000000000000c2dabd117f8a3ecabfbb11d12194d9d0;
-          tv[23]= 384'he234cdca2606b81f29408d5f6da2120600000000000000000000000000000000fff60a4740086b3b9c56195b98d91a7b;
-          tv[24]= 384'h13237c49074a3da078dc1d828bb78c6f000000000000000000000000000000008146a08e2357f0caa30ca8c94d1a0544;
-          tv[25]= 384'h3071a2a48fe6cbd04f1a129098e308f8000000000000000000000000000000004b98e06d356deb07ebb824e5713f7be3;
-          tv[26]= 384'h90f42ec0f68385f2ffc5dfc03a654dce000000000000000000000000000000007a20a53d460fc9ce0423a7a0764c6cf2;
-          tv[27]= 384'hfebd9a24d8b65c1c787d50a4ed3619a900000000000000000000000000000000f4a70d8af877f9b02b4c40df57d45b17;
-          tv[28]= 384'h80000000000000000000000000000000000000000000000000000000000000000edd33d3c621e546455bd8ba1418bec8;
-          tv[29]= 384'hc0000000000000000000000000000000000000000000000000000000000000004bc3f883450c113c64ca42e1112a9e87;
-          tv[30]= 384'he00000000000000000000000000000000000000000000000000000000000000072a1da770f5d7ac4c9ef94d822affd97;
-          tv[31]= 384'hf000000000000000000000000000000000000000000000000000000000000000970014d634e2b7650777e8e84d03ccd8;
-          tv[32]= 384'hf800000000000000000000000000000000000000000000000000000000000000f17e79aed0db7e279e955b5f493875a7;
-          tv[33]= 384'hfc000000000000000000000000000000000000000000000000000000000000009ed5a75136a940d0963da379db4af26a;
-          tv[34]= 384'hfe00000000000000000000000000000000000000000000000000000000000000c4295f83465c7755e8fa364bac6a7ea5;
-          tv[35]= 384'hff00000000000000000000000000000000000000000000000000000000000000b1d758256b28fd850ad4944208cf1155;
-          tv[36]= 384'hff8000000000000000000000000000000000000000000000000000000000000042ffb34c743de4d88ca38011c990890b;
-          tv[37]= 384'hffc00000000000000000000000000000000000000000000000000000000000009958f0ecea8b2172c0c1995f9182c0f3;
-          tv[38]= 384'hffe0000000000000000000000000000000000000000000000000000000000000956d7798fac20f82a8823f984d06f7f5;
-          tv[39]= 384'hfff0000000000000000000000000000000000000000000000000000000000000a01bf44f2d16be928ca44aaf7b9b106b;
-          tv[40]= 384'hfff8000000000000000000000000000000000000000000000000000000000000b5f1a33e50d40d103764c76bd4c6b6f8;
-          tv[41]= 384'hfffc0000000000000000000000000000000000000000000000000000000000002637050c9fc0d4817e2d69de878aee8d;
-          tv[42]= 384'hfffe000000000000000000000000000000000000000000000000000000000000113ecbe4a453269a0dd26069467fb5b5;
-          tv[43]= 384'hffff00000000000000000000000000000000000000000000000000000000000097d0754fe68f11b9e375d070a608c884;
-          tv[44]= 384'hffff800000000000000000000000000000000000000000000000000000000000c6a0b3e998d05068a5399778405200b4;
-          tv[45]= 384'hffffc00000000000000000000000000000000000000000000000000000000000df556a33438db87bc41b1752c55e5e49;
-          tv[46]= 384'hffffe0000000000000000000000000000000000000000000000000000000000090fb128d3a1af6e548521bb962bf1f05;
-          tv[47]= 384'hfffff0000000000000000000000000000000000000000000000000000000000026298e9c1db517c215fadfb7d2a8d691;
-          tv[48]= 384'hfffff80000000000000000000000000000000000000000000000000000000000a6cb761d61f8292d0df393a279ad0380;
-          tv[49]= 384'hfffffc000000000000000000000000000000000000000000000000000000000012acd89b13cd5f8726e34d44fd486108;
-          tv[50]= 384'hfffffe000000000000000000000000000000000000000000000000000000000095b1703fc57ba09fe0c3580febdd7ed4;
-          tv[51]= 384'hffffff0000000000000000000000000000000000000000000000000000000000de11722d893e9f9121c381becc1da59a;
-          tv[52]= 384'hffffff80000000000000000000000000000000000000000000000000000000006d114ccb27bf391012e8974c546d9bf2;
-          tv[53]= 384'hffffffc0000000000000000000000000000000000000000000000000000000005ce37e17eb4646ecfac29b9cc38d9340;
-          tv[54]= 384'hffffffe00000000000000000000000000000000000000000000000000000000018c1b6e2157122056d0243d8a165cddb;
-          tv[55]= 384'hfffffff00000000000000000000000000000000000000000000000000000000099693e6a59d1366c74d823562d7e1431;
-          tv[56]= 384'hfffffff8000000000000000000000000000000000000000000000000000000006c7c64dc84a8bba758ed17eb025a57e3;
-          tv[57]= 384'hfffffffc00000000000000000000000000000000000000000000000000000000e17bc79f30eaab2fac2cbbe3458d687a;
-          tv[58]= 384'hfffffffe000000000000000000000000000000000000000000000000000000001114bc2028009b923f0b01915ce5e7c4;
-          tv[59]= 384'hffffffff000000000000000000000000000000000000000000000000000000009c28524a16a1e1c1452971caa8d13476;
-          tv[60]= 384'hffffffff80000000000000000000000000000000000000000000000000000000ed62e16363638360fdd6ad62112794f0;
-          tv[61]= 384'hffffffffc00000000000000000000000000000000000000000000000000000005a8688f0b2a2c16224c161658ffd4044;
-          tv[62]= 384'hffffffffe000000000000000000000000000000000000000000000000000000023f710842b9bb9c32f26648c786807ca;
-          tv[63]= 384'hfffffffff000000000000000000000000000000000000000000000000000000044a98bf11e163f632c47ec6a49683a89;
-          tv[64]= 384'hfffffffff80000000000000000000000000000000000000000000000000000000f18aff94274696d9b61848bd50ac5e5;
-          tv[65]= 384'hfffffffffc00000000000000000000000000000000000000000000000000000082408571c3e2424540207f833b6dda69;
-          tv[66]= 384'hfffffffffe000000000000000000000000000000000000000000000000000000303ff996947f0c7d1f43c8f3027b9b75;
-          tv[67]= 384'hffffffffff0000000000000000000000000000000000000000000000000000007df4daf4ad29a3615a9b6ece5c99518a;
-          tv[68]= 384'hffffffffff800000000000000000000000000000000000000000000000000000c72954a48d0774db0b4971c526260415;
-          tv[69]= 384'hffffffffffc000000000000000000000000000000000000000000000000000001df9b76112dc6531e07d2cfda04411f0;
-          tv[70]= 384'hffffffffffe000000000000000000000000000000000000000000000000000008e4d8e699119e1fc87545a647fb1d34f;
-          tv[71]= 384'hfffffffffff00000000000000000000000000000000000000000000000000000e6c4807ae11f36f091c57d9fb68548d1;
-          tv[72]= 384'hfffffffffff800000000000000000000000000000000000000000000000000008ebf73aad49c82007f77a5c1ccec6ab4;
-          tv[73]= 384'hfffffffffffc00000000000000000000000000000000000000000000000000004fb288cc2040049001d2c7585ad123fc;
-          tv[74]= 384'hfffffffffffe000000000000000000000000000000000000000000000000000004497110efb9dceb13e2b13fb4465564;
-          tv[75]= 384'hffffffffffff000000000000000000000000000000000000000000000000000075550e6cb5a88e49634c9ab69eda0430;
-          tv[76]= 384'hffffffffffff8000000000000000000000000000000000000000000000000000b6768473ce9843ea66a81405dd50b345;
-          tv[77]= 384'hffffffffffffc000000000000000000000000000000000000000000000000000cb2f430383f9084e03a653571e065de6;
-          tv[78]= 384'hffffffffffffe000000000000000000000000000000000000000000000000000ff4e66c07bae3e79fb7d210847a3b0ba;
-          tv[79]= 384'hfffffffffffff0000000000000000000000000000000000000000000000000007b90785125505fad59b13c186dd66ce3;
-          tv[80]= 384'hfffffffffffff8000000000000000000000000000000000000000000000000008b527a6aebdaec9eaef8eda2cb7783e5;
-          tv[81]= 384'hfffffffffffffc0000000000000000000000000000000000000000000000000043fdaf53ebbc9880c228617d6a9b548b;
-          tv[82]= 384'hfffffffffffffe0000000000000000000000000000000000000000000000000053786104b9744b98f052c46f1c850d0b;
-          tv[83]= 384'hffffffffffffff00000000000000000000000000000000000000000000000000b5ab3013dd1e61df06cbaf34ca2aee78;
-          tv[84]= 384'hffffffffffffff800000000000000000000000000000000000000000000000007470469be9723030fdcc73a8cd4fbb10;
-          tv[85]= 384'hffffffffffffffc0000000000000000000000000000000000000000000000000a35a63f5343ebe9ef8167bcb48ad122e;
-          tv[86]= 384'hffffffffffffffe0000000000000000000000000000000000000000000000000fd8687f0757a210e9fdf181204c30863;
-          tv[87]= 384'hfffffffffffffff00000000000000000000000000000000000000000000000007a181e84bd5457d26a88fbae96018fb0;
-          tv[88]= 384'hfffffffffffffff8000000000000000000000000000000000000000000000000653317b9362b6f9b9e1a580e68d494b5;
-          tv[89]= 384'hfffffffffffffffc000000000000000000000000000000000000000000000000995c9dc0b689f03c45867b5faa5c18d1;
-          tv[90]= 384'hfffffffffffffffe00000000000000000000000000000000000000000000000077a4d96d56dda398b9aabecfc75729fd;
-          tv[91]= 384'hffffffffffffffff00000000000000000000000000000000000000000000000084be19e053635f09f2665e7bae85b42d;
-          tv[92]= 384'hffffffffffffffff80000000000000000000000000000000000000000000000032cd652842926aea4aa6137bb2be2b5e;
-          tv[93]= 384'hffffffffffffffffc00000000000000000000000000000000000000000000000493d4a4f38ebb337d10aa84e9171a554;
-          tv[94]= 384'hffffffffffffffffe00000000000000000000000000000000000000000000000d9bff7ff454b0ec5a4a2a69566e2cb84;
-          tv[95]= 384'hfffffffffffffffff000000000000000000000000000000000000000000000003535d565ace3f31eb249ba2cc6765d7a;
-          tv[96]= 384'hfffffffffffffffff80000000000000000000000000000000000000000000000f60e91fc3269eecf3231c6e9945697c6;
-          tv[97]= 384'hfffffffffffffffffc0000000000000000000000000000000000000000000000ab69cfadf51f8e604d9cc37182f6635a;
-          tv[98]= 384'hfffffffffffffffffe00000000000000000000000000000000000000000000007866373f24a0b6ed56e0d96fcdafb877;
-          tv[99]= 384'hffffffffffffffffff00000000000000000000000000000000000000000000001ea448c2aac954f5d812e9d78494446a;
-          tv[100]= 384'hffffffffffffffffff8000000000000000000000000000000000000000000000acc5599dd8ac02239a0fef4a36dd1668;
-          tv[101]= 384'hffffffffffffffffffc000000000000000000000000000000000000000000000d8764468bb103828cf7e1473ce895073;
-          tv[102]= 384'hffffffffffffffffffe0000000000000000000000000000000000000000000001b0d02893683b9f180458e4aa6b73982;
-          tv[103]= 384'hfffffffffffffffffff00000000000000000000000000000000000000000000096d9b017d302df410a937dcdb8bb6e43;
-          tv[104]= 384'hfffffffffffffffffff800000000000000000000000000000000000000000000ef1623cc44313cff440b1594a7e21cc6;
-          tv[105]= 384'hfffffffffffffffffffc00000000000000000000000000000000000000000000284ca2fa35807b8b0ae4d19e11d7dbd7;
-          tv[106]= 384'hfffffffffffffffffffe00000000000000000000000000000000000000000000f2e976875755f9401d54f36e2a23a594;
-          tv[107]= 384'hffffffffffffffffffff00000000000000000000000000000000000000000000ec198a18e10e532403b7e20887c8dd80;
-          tv[108]= 384'hffffffffffffffffffff80000000000000000000000000000000000000000000545d50ebd919e4a6949d96ad47e46a80;
-          tv[109]= 384'hffffffffffffffffffffc0000000000000000000000000000000000000000000dbdfb527060e0a71009c7bb0c68f1d44;
-          tv[110]= 384'hffffffffffffffffffffe00000000000000000000000000000000000000000009cfa1322ea33da2173a024f2ff0d896d;
-          tv[111]= 384'hfffffffffffffffffffff00000000000000000000000000000000000000000008785b1a75b0f3bd958dcd0e29318c521;
-          tv[112]= 384'hfffffffffffffffffffff800000000000000000000000000000000000000000038f67b9e98e4a97b6df030a9fcdd0104;
-          tv[113]= 384'hfffffffffffffffffffffc000000000000000000000000000000000000000000192afffb2c880e82b05926d0fc6c448b;
-          tv[114]= 384'hfffffffffffffffffffffe0000000000000000000000000000000000000000006a7980ce7b105cf530952d74daaf798c;
-          tv[115]= 384'hffffffffffffffffffffff000000000000000000000000000000000000000000ea3695e1351b9d6858bd958cf513ef6c;
-          tv[116]= 384'hffffffffffffffffffffff8000000000000000000000000000000000000000006da0490ba0ba0343b935681d2cce5ba1;
-          tv[117]= 384'hffffffffffffffffffffffc00000000000000000000000000000000000000000f0ea23af08534011c60009ab29ada2f1;
-          tv[118]= 384'hffffffffffffffffffffffe00000000000000000000000000000000000000000ff13806cf19cc38721554d7c0fcdcd4b;
-          tv[119]= 384'hfffffffffffffffffffffff000000000000000000000000000000000000000006838af1f4f69bae9d85dd188dcdf0688;
-          tv[120]= 384'hfffffffffffffffffffffff8000000000000000000000000000000000000000036cf44c92d550bfb1ed28ef583ddf5d7;
-          tv[121]= 384'hfffffffffffffffffffffffc0000000000000000000000000000000000000000d06e3195b5376f109d5c4ec6c5d62ced;
-          tv[122]= 384'hfffffffffffffffffffffffe0000000000000000000000000000000000000000c440de014d3d610707279b13242a5c36;
-          tv[123]= 384'hffffffffffffffffffffffff0000000000000000000000000000000000000000f0c5c6ffa5e0bd3a94c88f6b6f7c16b9;
-          tv[124]= 384'hffffffffffffffffffffffff80000000000000000000000000000000000000003e40c3901cd7effc22bffc35dee0b4d9;
-          tv[125]= 384'hffffffffffffffffffffffffc000000000000000000000000000000000000000b63305c72bedfab97382c406d0c49bc6;
-          tv[126]= 384'hffffffffffffffffffffffffe00000000000000000000000000000000000000036bbaab22a6bd4925a99a2b408d2dbae;
-          tv[127]= 384'hfffffffffffffffffffffffff000000000000000000000000000000000000000307c5b8fcd0533ab98bc51e27a6ce461;
-          tv[128]= 384'hfffffffffffffffffffffffff800000000000000000000000000000000000000829c04ff4c07513c0b3ef05c03e337b5;
-          tv[129]= 384'hfffffffffffffffffffffffffc00000000000000000000000000000000000000f17af0e895dda5eb98efc68066e84c54;
-          tv[130]= 384'hfffffffffffffffffffffffffe00000000000000000000000000000000000000277167f3812afff1ffacb4a934379fc3;
-          tv[131]= 384'hffffffffffffffffffffffffff000000000000000000000000000000000000002cb1dc3a9c72972e425ae2ef3eb597cd;
-          tv[132]= 384'hffffffffffffffffffffffffff8000000000000000000000000000000000000036aeaa3a213e968d4b5b679d3a2c97fe;
-          tv[133]= 384'hffffffffffffffffffffffffffc00000000000000000000000000000000000009241daca4fdd034a82372db50e1a0f3f;
-          tv[134]= 384'hffffffffffffffffffffffffffe0000000000000000000000000000000000000c14574d9cd00cf2b5a7f77e53cd57885;
-          tv[135]= 384'hfffffffffffffffffffffffffff0000000000000000000000000000000000000793de39236570aba83ab9b737cb521c9;
-          tv[136]= 384'hfffffffffffffffffffffffffff800000000000000000000000000000000000016591c0f27d60e29b85a96c33861a7ef;
-          tv[137]= 384'hfffffffffffffffffffffffffffc00000000000000000000000000000000000044fb5c4d4f5cb79be5c174a3b1c97348;
-          tv[138]= 384'hfffffffffffffffffffffffffffe000000000000000000000000000000000000674d2b61633d162be59dde04222f4740;
-          tv[139]= 384'hffffffffffffffffffffffffffff000000000000000000000000000000000000b4750ff263a65e1f9e924ccfd98f3e37;
-          tv[140]= 384'hffffffffffffffffffffffffffff80000000000000000000000000000000000062d0662d6eaeddedebae7f7ea3a4f6b6;
-          tv[141]= 384'hffffffffffffffffffffffffffffc0000000000000000000000000000000000070c46bb30692be657f7eaa93ebad9897;
-          tv[142]= 384'hffffffffffffffffffffffffffffe00000000000000000000000000000000000323994cfb9da285a5d9642e1759b224a;
-          tv[143]= 384'hfffffffffffffffffffffffffffff000000000000000000000000000000000001dbf57877b7b17385c85d0b54851e371;
-          tv[144]= 384'hfffffffffffffffffffffffffffff80000000000000000000000000000000000dfa5c097cdc1532ac071d57b1d28d1bd;
-          tv[145]= 384'hfffffffffffffffffffffffffffffc00000000000000000000000000000000003a0c53fa37311fc10bd2a9981f513174;
-          tv[146]= 384'hfffffffffffffffffffffffffffffe0000000000000000000000000000000000ba4f970c0a25c41814bdae2e506be3b4;
-          tv[147]= 384'hffffffffffffffffffffffffffffff00000000000000000000000000000000002dce3acb727cd13ccd76d425ea56e4f6;
-          tv[148]= 384'hffffffffffffffffffffffffffffff80000000000000000000000000000000005160474d504b9b3eefb68d35f245f4b3;
-          tv[149]= 384'hffffffffffffffffffffffffffffffc00000000000000000000000000000000041a8a947766635dec37553d9a6c0cbb7;
-          tv[150]= 384'hffffffffffffffffffffffffffffffe00000000000000000000000000000000025d6cfe6881f2bf497dd14cd4ddf445b;
-          tv[151]= 384'hfffffffffffffffffffffffffffffff00000000000000000000000000000000041c78c135ed9e98c096640647265da1e;
-          tv[152]= 384'hfffffffffffffffffffffffffffffff8000000000000000000000000000000005a4d404d8917e353e92a21072c3b2305;
-          tv[153]= 384'hfffffffffffffffffffffffffffffffc0000000000000000000000000000000002bc96846b3fdc71643f384cd3cc3eaf;
-          tv[154]= 384'hfffffffffffffffffffffffffffffffe000000000000000000000000000000009ba4a9143f4e5d4048521c4f8877d88e;
-          tv[155]= 384'hffffffffffffffffffffffffffffffff00000000000000000000000000000000a1f6258c877d5fcd8964484538bfc92c;
-          tv[156]= 384'h00000000000000000000000000000000800000000000000000000000000000003ad78e726c1ec02b7ebfe92b23d9ec34;
-          tv[157]= 384'h00000000000000000000000000000000c0000000000000000000000000000000aae5939c8efdf2f04e60b9fe7117b2c2;
-          tv[158]= 384'h00000000000000000000000000000000e0000000000000000000000000000000f031d4d74f5dcbf39daaf8ca3af6e527;
-          tv[159]= 384'h00000000000000000000000000000000f000000000000000000000000000000096d9fd5cc4f07441727df0f33e401a36;
-          tv[160]= 384'h00000000000000000000000000000000f800000000000000000000000000000030ccdb044646d7e1f3ccea3dca08b8c0;
-          tv[161]= 384'h00000000000000000000000000000000fc00000000000000000000000000000016ae4ce5042a67ee8e177b7c587ecc82;
-          tv[162]= 384'h00000000000000000000000000000000fe000000000000000000000000000000b6da0bb11a23855d9c5cb1b4c6412e0a;
-          tv[163]= 384'h00000000000000000000000000000000ff000000000000000000000000000000db4f1aa530967d6732ce4715eb0ee24b;
-          tv[164]= 384'h00000000000000000000000000000000ff800000000000000000000000000000a81738252621dd180a34f3455b4baa2f;
-          tv[165]= 384'h00000000000000000000000000000000ffc0000000000000000000000000000077e2b508db7fd89234caf7939ee5621a;
-          tv[166]= 384'h00000000000000000000000000000000ffe00000000000000000000000000000b8499c251f8442ee13f0933b688fcd19;
-          tv[167]= 384'h00000000000000000000000000000000fff00000000000000000000000000000965135f8a81f25c9d630b17502f68e53;
-          tv[168]= 384'h00000000000000000000000000000000fff800000000000000000000000000008b87145a01ad1c6cede995ea3670454f;
-          tv[169]= 384'h00000000000000000000000000000000fffc00000000000000000000000000008eae3b10a0c8ca6d1d3b0fa61e56b0b2;
-          tv[170]= 384'h00000000000000000000000000000000fffe000000000000000000000000000064b4d629810fda6bafdf08f3b0d8d2c5;
-          tv[171]= 384'h00000000000000000000000000000000ffff0000000000000000000000000000d7e5dbd3324595f8fdc7d7c571da6c2a;
-          tv[172]= 384'h00000000000000000000000000000000ffff8000000000000000000000000000f3f72375264e167fca9de2c1527d9606;
-          tv[173]= 384'h00000000000000000000000000000000ffffc0000000000000000000000000008ee79dd4f401ff9b7ea945d86666c13b;
-          tv[174]= 384'h00000000000000000000000000000000ffffe000000000000000000000000000dd35cea2799940b40db3f819cb94c08b;
-          tv[175]= 384'h00000000000000000000000000000000fffff0000000000000000000000000006941cb6b3e08c2b7afa581ebdd607b87;
-          tv[176]= 384'h00000000000000000000000000000000fffff8000000000000000000000000002c20f439f6bb097b29b8bd6d99aad799;
-          tv[177]= 384'h00000000000000000000000000000000fffffc00000000000000000000000000625d01f058e565f77ae86378bd2c49b3;
-          tv[178]= 384'h00000000000000000000000000000000fffffe00000000000000000000000000c0b5fd98190ef45fbb4301438d095950;
-          tv[179]= 384'h00000000000000000000000000000000ffffff0000000000000000000000000013001ff5d99806efd25da34f56be854b;
-          tv[180]= 384'h00000000000000000000000000000000ffffff800000000000000000000000003b594c60f5c8277a5113677f94208d82;
-          tv[181]= 384'h00000000000000000000000000000000ffffffc0000000000000000000000000e9c0fc1818e4aa46bd2e39d638f89e05;
-          tv[182]= 384'h00000000000000000000000000000000ffffffe0000000000000000000000000f8023ee9c3fdc45a019b4e985c7e1a54;
-          tv[183]= 384'h00000000000000000000000000000000fffffff000000000000000000000000035f40182ab4662f3023baec1ee796b57;
-          tv[184]= 384'h00000000000000000000000000000000fffffff80000000000000000000000003aebbad7303649b4194a6945c6cc3694;
-          tv[185]= 384'h00000000000000000000000000000000fffffffc000000000000000000000000a2124bea53ec2834279bed7f7eb0f938;
-          tv[186]= 384'h00000000000000000000000000000000fffffffe000000000000000000000000b9fb4399fa4facc7309e14ec98360b0a;
-          tv[187]= 384'h00000000000000000000000000000000ffffffff000000000000000000000000c26277437420c5d634f715aea81a9132;
-          tv[188]= 384'h00000000000000000000000000000000ffffffff800000000000000000000000171a0e1b2dd424f0e089af2c4c10f32f;
-          tv[189]= 384'h00000000000000000000000000000000ffffffffc000000000000000000000007cadbe402d1b208fe735edce00aee7ce;
-          tv[190]= 384'h00000000000000000000000000000000ffffffffe0000000000000000000000043b02ff929a1485af6f5c6d6558baa0f;
-          tv[191]= 384'h00000000000000000000000000000000fffffffff00000000000000000000000092faacc9bf43508bf8fa8613ca75dea;
-          tv[192]= 384'h00000000000000000000000000000000fffffffff80000000000000000000000cb2bf8280f3f9742c7ed513fe802629c;
-          tv[193]= 384'h00000000000000000000000000000000fffffffffc0000000000000000000000215a41ee442fa992a6e323986ded3f68;
-          tv[194]= 384'h00000000000000000000000000000000fffffffffe0000000000000000000000f21e99cf4f0f77cea836e11a2fe75fb1;
-          tv[195]= 384'h00000000000000000000000000000000ffffffffff000000000000000000000095e3a0ca9079e646331df8b4e70d2cd6;
-          tv[196]= 384'h00000000000000000000000000000000ffffffffff80000000000000000000004afe7f120ce7613f74fc12a01a828073;
-          tv[197]= 384'h00000000000000000000000000000000ffffffffffc000000000000000000000827f000e75e2c8b9d479beed913fe678;
-          tv[198]= 384'h00000000000000000000000000000000ffffffffffe00000000000000000000035830c8e7aaefe2d30310ef381cbf691;
-          tv[199]= 384'h00000000000000000000000000000000fffffffffff000000000000000000000191aa0f2c8570144f38657ea4085ebe5;
-          tv[200]= 384'h00000000000000000000000000000000fffffffffff80000000000000000000085062c2c909f15d9269b6c18ce99c4f0;
-          tv[201]= 384'h00000000000000000000000000000000fffffffffffc00000000000000000000678034dc9e41b5a560ed239eeab1bc78;
-          tv[202]= 384'h00000000000000000000000000000000fffffffffffe00000000000000000000c2f93a4ce5ab6d5d56f1b93cf19911c1;
-          tv[203]= 384'h00000000000000000000000000000000ffffffffffff000000000000000000001c3112bcb0c1dcc749d799743691bf82;
-          tv[204]= 384'h00000000000000000000000000000000ffffffffffff8000000000000000000000c55bd75c7f9c881989d3ec1911c0d4;
-          tv[205]= 384'h00000000000000000000000000000000ffffffffffffc0000000000000000000ea2e6b5ef182b7dff3629abd6a12045f;
-          tv[206]= 384'h00000000000000000000000000000000ffffffffffffe000000000000000000022322327e01780b17397f24087f8cc6f;
-          tv[207]= 384'h00000000000000000000000000000000fffffffffffff0000000000000000000c9cacb5cd11692c373b2411768149ee7;
-          tv[208]= 384'h00000000000000000000000000000000fffffffffffff8000000000000000000a18e3dbbca577860dab6b80da3139256;
-          tv[209]= 384'h00000000000000000000000000000000fffffffffffffc00000000000000000079b61c37bf328ecca8d743265a3d425c;
-          tv[210]= 384'h00000000000000000000000000000000fffffffffffffe000000000000000000d2d99c6bcc1f06fda8e27e8ae3f1ccc7;
-          tv[211]= 384'h00000000000000000000000000000000ffffffffffffff0000000000000000001bfd4b91c701fd6b61b7f997829d663b;
-          tv[212]= 384'h00000000000000000000000000000000ffffffffffffff80000000000000000011005d52f25f16bdc9545a876a63490a;
-          tv[213]= 384'h00000000000000000000000000000000ffffffffffffffc000000000000000003a4d354f02bb5a5e47d39666867f246a;
-          tv[214]= 384'h00000000000000000000000000000000ffffffffffffffe00000000000000000d451b8d6e1e1a0ebb155fbbf6e7b7dc3;
-          tv[215]= 384'h00000000000000000000000000000000fffffffffffffff000000000000000006898d4f42fa7ba6a10ac05e87b9f2080;
-          tv[216]= 384'h00000000000000000000000000000000fffffffffffffff80000000000000000b611295e739ca7d9b50f8e4c0e754a3f;
-          tv[217]= 384'h00000000000000000000000000000000fffffffffffffffc00000000000000007d33fc7d8abe3ca1936759f8f5deaf20;
-          tv[218]= 384'h00000000000000000000000000000000fffffffffffffffe00000000000000003b5e0f566dc96c298f0c12637539b25c;
-          tv[219]= 384'h00000000000000000000000000000000ffffffffffffffff0000000000000000f807c3e7985fe0f5a50e2cdb25c5109e;
-          tv[220]= 384'h00000000000000000000000000000000ffffffffffffffff800000000000000041f992a856fb278b389a62f5d274d7e9;
-          tv[221]= 384'h00000000000000000000000000000000ffffffffffffffffc00000000000000010d3ed7a6fe15ab4d91acbc7d0767ab1;
-          tv[222]= 384'h00000000000000000000000000000000ffffffffffffffffe00000000000000021feecd45b2e675973ac33bf0c5424fc;
-          tv[223]= 384'h00000000000000000000000000000000fffffffffffffffff0000000000000001480cb3955ba62d09eea668f7c708817;
-          tv[224]= 384'h00000000000000000000000000000000fffffffffffffffff80000000000000066404033d6b72b609354d5496e7eb511;
-          tv[225]= 384'h00000000000000000000000000000000fffffffffffffffffc000000000000001c317a220a7d700da2b1e075b00266e1;
-          tv[226]= 384'h00000000000000000000000000000000fffffffffffffffffe00000000000000ab3b89542233f1271bf8fd0c0f403545;
-          tv[227]= 384'h00000000000000000000000000000000ffffffffffffffffff00000000000000d93eae966fac46dca927d6b114fa3f9e;
-          tv[228]= 384'h00000000000000000000000000000000ffffffffffffffffff800000000000001bdec521316503d9d5ee65df3ea94ddf;
-          tv[229]= 384'h00000000000000000000000000000000ffffffffffffffffffc0000000000000eef456431dea8b4acf83bdae3717f75f;
-          tv[230]= 384'h00000000000000000000000000000000ffffffffffffffffffe000000000000006f2519a2fafaa596bfef5cfa15c21b9;
-          tv[231]= 384'h00000000000000000000000000000000fffffffffffffffffff0000000000000251a7eac7e2fe809e4aa8d0d7012531a;
-          tv[232]= 384'h00000000000000000000000000000000fffffffffffffffffff80000000000003bffc16e4c49b268a20f8d96a60b4058;
-          tv[233]= 384'h00000000000000000000000000000000fffffffffffffffffffc000000000000e886f9281999c5bb3b3e8862e2f7c988;
-          tv[234]= 384'h00000000000000000000000000000000fffffffffffffffffffe000000000000563bf90d61beef39f48dd625fcef1361;
-          tv[235]= 384'h00000000000000000000000000000000ffffffffffffffffffff0000000000004d37c850644563c69fd0acd9a049325b;
-          tv[236]= 384'h00000000000000000000000000000000ffffffffffffffffffff800000000000b87c921b91829ef3b13ca541ee1130a6;
-          tv[237]= 384'h00000000000000000000000000000000ffffffffffffffffffffc000000000002e65eb6b6ea383e109accce8326b0393;
-          tv[238]= 384'h00000000000000000000000000000000ffffffffffffffffffffe000000000009ca547f7439edc3e255c0f4d49aa8990;
-          tv[239]= 384'h00000000000000000000000000000000fffffffffffffffffffff00000000000a5e652614c9300f37816b1f9fd0c87f9;
-          tv[240]= 384'h00000000000000000000000000000000fffffffffffffffffffff8000000000014954f0b4697776f44494fe458d814ed;
-          tv[241]= 384'h00000000000000000000000000000000fffffffffffffffffffffc00000000007c8d9ab6c2761723fe42f8bb506cbcf7;
-          tv[242]= 384'h00000000000000000000000000000000fffffffffffffffffffffe0000000000db7e1932679fdd99742aab04aa0d5a80;
-          tv[243]= 384'h00000000000000000000000000000000ffffffffffffffffffffff00000000004c6a1c83e568cd10f27c2d73ded19c28;
-          tv[244]= 384'h00000000000000000000000000000000ffffffffffffffffffffff800000000090ecbe6177e674c98de412413f7ac915;
-          tv[245]= 384'h00000000000000000000000000000000ffffffffffffffffffffffc00000000090684a2ac55fe1ec2b8ebd5622520b73;
-          tv[246]= 384'h00000000000000000000000000000000ffffffffffffffffffffffe0000000007472f9a7988607ca79707795991035e6;
-          tv[247]= 384'h00000000000000000000000000000000fffffffffffffffffffffff00000000056aff089878bf3352f8df172a3ae47d8;
-          tv[248]= 384'h00000000000000000000000000000000fffffffffffffffffffffff80000000065c0526cbe40161b8019a2a3171abd23;
-          tv[249]= 384'h00000000000000000000000000000000fffffffffffffffffffffffc00000000377be0be33b4e3e310b4aabda173f84f;
-          tv[250]= 384'h00000000000000000000000000000000fffffffffffffffffffffffe000000009402e9aa6f69de6504da8d20c4fcaa2f;
-          tv[251]= 384'h00000000000000000000000000000000ffffffffffffffffffffffff00000000123c1f4af313ad8c2ce648b2e71fb6e1;
-          tv[252]= 384'h00000000000000000000000000000000ffffffffffffffffffffffff800000001ffc626d30203dcdb0019fb80f726cf4;
-          tv[253]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffc000000076da1fbe3a50728c50fd2e621b5ad885;
-          tv[254]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffe0000000082eb8be35f442fb52668e16a591d1d6;
-          tv[255]= 384'h00000000000000000000000000000000fffffffffffffffffffffffff0000000e656f9ecf5fe27ec3e4a73d00c282fb3;
-          tv[256]= 384'h00000000000000000000000000000000fffffffffffffffffffffffff80000002ca8209d63274cd9a29bb74bcd77683a;
-          tv[257]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffc00000079bf5dce14bb7dd73a8e3611de7ce026;
-          tv[258]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffe0000003c849939a5d29399f344c4a0eca8a576;
-          tv[259]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffff000000ed3c0a94d59bece98835da7aa4f07ca2;
-          tv[260]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffff80000063919ed4ce10196438b6ad09d99cd795;
-          tv[261]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffc000007678f3a833f19fea95f3c6029e2bc610;
-          tv[262]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffe000003aa426831067d36b92be7c5f81c13c56;
-          tv[263]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffff000009272e2d2cdd11050998c845077a30ea0;
-          tv[264]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffff80000088c4b53f5ec0ff814c19adae7f6246c;
-          tv[265]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffc00004010a5e401fdf0a0354ddbcc0d012b17;
-          tv[266]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffe0000a87a385736c0a6189bd6589bd8445a93;
-          tv[267]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffff0000545f2b83d9616dccf60fa9830e9cd287;
-          tv[268]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffff80004b706f7f92406352394037a6d4f4688d;
-          tv[269]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffc000b7972b3941c44b90afa7b264bfba7387;
-          tv[270]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffe0006f45732cf10881546f0fd23896d2bb60;
-          tv[271]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffff0002e3579ca15af27f64b3c955a5bfc30ba;
-          tv[272]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffff80034a2c5a91ae2aec99b7d1b5fa6780447;
-          tv[273]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffc00a4d6616bd04f87335b0e53351227a9ee;
-          tv[274]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffe007f692b03945867d16179a8cefc83ea3f;
-          tv[275]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffff003bd141ee84a0e6414a26e7a4f281f8a2;
-          tv[276]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffff80d1788f572d98b2b16ec5d5f3922b99bc;
-          tv[277]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffffc00833ff6f61d98a57b288e8c3586b85a6;
-          tv[278]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffffe08568261797de176bf0b43becc6285afb;
-          tv[279]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffff0f9b0fda0c4a898f5b9e6f661c4ce4d07;
-          tv[280]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffff88ade895913685c67c5269f8aae42983e;
-          tv[281]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffffc39bde67d5c8ed8a8b1c37eb8fa9f5ac0;
-          tv[282]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffffe5c005e72c1418c44f569f2ea33ba54f3;
-          tv[283]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffffff3f5b8cc9ea855a0afa7347d23e8d664e;
-          
-          
-          // for(n=0;n<284;n=n+1)
-          for(n=0;n<28;n=n+1)
-            begin
-	      @(posedge clk);
-	      #1;
-	      kld = 1;
-	      @(posedge clk);
-	      #1;
-	      kld = 0;
-	      @(posedge clk);
-
-	      while(!done)	@(posedge clk);
-
-	      // $display("INFO: (a) Vector %3d/284: xpected %x, Got %x %t", n, ciph, text_out, $time);
-	      $display("INFO: (a) Vector %2d/28: xpected %x, Got %x %t", n, ciph, text_out, $time);
-
-	      if(text_out != ciph | (|text_out)==1'bx)
-	        begin
-		  $display("ERROR: (a) Vector %0d mismatch. Expected %x, Got %x",
-			   n, ciph, text_out);
-		  error_cnt = error_cnt + 1;
-	        end
-
-
-/* -----\/----- EXCLUDED -----\/-----
-	      while(!done2)	@(posedge clk);
-
-	      //$display("INFO: (b) Vector %0d: xpected %x, Got %x", n, plain, text_out2);
-
-	      if(text_out2 != plain | (|text_out2)==1'bx)
-	        begin
-		  $display("ERROR: (b) Vector %0d mismatch. Expected %x, Got %x",
-			   n, plain, text_out2);
-		  error_cnt = error_cnt + 1;
-	        end
- -----/\----- EXCLUDED -----/\----- */
-              
-
-	      $fflush;
-	      @(posedge clk);
-	      #1;
-            end // for (n=0;n<284;n=n+1)
-          
-
-
-	  $display("");
-	  $display("");
-	  $display("Test Done. Found %0d Errors.", error_cnt);
-	  $display("");
-	  $display("");
-	  repeat(10)	@(posedge clk);
-        end // while (1)
-      
-      	$finish;
-    end // initial begin
-  
-
-  assign tmp = tv[n];
-  assign key     = tmp[383:256]; //kld ? tmp[383:256] : 128'hx;
-  assign text_in = tmp[255:128]; //kld ? tmp[255:128] : 128'hx;
-  assign plain   = tmp[255:128];
-  assign ciph    = tmp[127:0];
-
-  initial begin
-    clk <= 0;
-    forever begin
-      // $display("CLK: %b", clk);
-      #5; clk <= ~clk;
-    end
-  end
-
-  aes_cipher_top	 u0
-    (
-     .clk(		clk		),
-     .rst(		rst		),
-     .ld(		kld		),
-     .done(		done		),
-     .key(		key		),
-     .text_in(	text_in		),
-     .text_out(	text_out	)
-     );
-
-/*
-  initial 
-    begin
-      #107000000
-        $finish;
-    end
-*/
-  
-/* -----\/----- EXCLUDED -----\/-----
-  initial
-    begin
-      $vcdpluson;
-    end
- -----/\----- EXCLUDED -----/\----- */
-  
-  integer cycle = 0;
-  always @(posedge clk) begin
-  	cycle = cycle + 1;
-	// $display("CYCLE %d", cycle);
-	if (cycle == 10000) begin
-		$display("Reached limit of 10000 cycles.");
-		$finish;
-	end
-  end
-
-  initial begin
-    // $dumpfile("bench.vcd");
-    // $dumpvars(0, testbench);
-  end
-  
-endmodule
-// Local Variables:
-// verilog-library-directories:("." "./gl")
-// End:
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/surelog.log b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/surelog.log
deleted file mode 100644
index 8cf1427..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/surelog.log
+++ /dev/null
@@ -1,163 +0,0 @@
-********************************************
-*  SURELOG System Verilog Compiler/Linter  *
-********************************************
-
-Copyright (c) 2017-2019 ACE Cloud,
-Authorized used only.
-
-VERSION: 0.05
-BUILT  : Nov  3 2019
-DATE   : 2019-11-03.21:40:17
-COMMAND: -writepp -parse -mt max -nopython -fileunit rtl/a23_alu.v rtl/a23_barrel_shift.v rtl/a23_barrel_shift_fpga.v rtl/a23_cache.v rtl/a23_config_defines.v rtl/a23_coprocessor.v rtl/a23_core.v rtl/a23_decode.v rtl/a23_decompile.v rtl/a23_execute.v rtl/a23_fetch.v rtl/a23_functions.v rtl/a23_localparams.v rtl/a23_multiply.v rtl/a23_ram_register_bank.v rtl/a23_register_bank.v rtl/a23_wishbone.v rtl/debug_functions.v rtl/generic_sram_byte_en.v rtl/generic_sram_line_en.v rtl/global_defines.v rtl/memory_configuration.v sim/bench.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
-
-[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
-
-[INFO :CM0024] Executing with 4 threads.
-
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[ERROR:PA0207] rtl/a23_decode.v:174 Syntax error: mismatched input 'type' expecting {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier},
-reg     [3:0]          type;
-                       ^-- ./slpp_unit/work/rtl/a23_decode.v:518 col:23.
-
-[WARNI:PA0205] rtl/a23_barrel_shift.v:42 No timescale set for "a23_barrel_shift".
-
-[WARNI:PA0205] rtl/a23_decompile.v:44 No timescale set for "a23_decompile".
-
-[WARNI:PA0205] rtl/a23_alu.v:43 No timescale set for "a23_alu".
-
-[WARNI:PA0205] rtl/a23_fetch.v:45 No timescale set for "a23_fetch".
-
-[WARNI:PA0205] rtl/a23_coprocessor.v:41 No timescale set for "a23_coprocessor".
-
-[WARNI:PA0205] rtl/a23_barrel_shift_fpga.v:46 No timescale set for "a23_barrel_shift_fpga".
-
-[WARNI:PA0205] rtl/a23_core.v:43 No timescale set for "a23_core".
-
-[WARNI:PA0205] rtl/a23_multiply.v:56 No timescale set for "a23_multiply".
-
-[WARNI:PA0205] rtl/a23_execute.v:45 No timescale set for "a23_execute".
-
-[WARNI:PA0205] rtl/a23_register_bank.v:44 No timescale set for "a23_register_bank".
-
-[WARNI:PA0205] rtl/generic_sram_byte_en.v:43 No timescale set for "generic_sram_byte_en".
-
-[WARNI:PA0205] rtl/a23_wishbone.v:58 No timescale set for "a23_wishbone".
-
-[WARNI:PA0205] rtl/generic_sram_line_en.v:42 No timescale set for "generic_sram_line_en".
-
-[WARNI:PA0205] rtl/a23_decode.v:43 No timescale set for "a23_decode".
-
-[WARNI:PA0205] sim/bench.v:2 No timescale set for "testbench".
-
-[WARNI:PA0205] rtl/a23_cache.v:47 No timescale set for "a23_cache".
-
-[WARNI:PA0205] rtl/a23_ram_register_bank.v:44 No timescale set for "a23_ram_register_bank".
-
-[INFO :CP0300] Compilation...
-
-[INFO :CP0303] rtl/a23_alu.v:43 Compile module "work@a23_alu".
-
-[INFO :CP0303] rtl/a23_barrel_shift_fpga.v:46 Compile module "work@a23_barrel_shift_fpga".
-
-[INFO :CP0303] rtl/a23_barrel_shift.v:42 Compile module "work@a23_barrel_shift".
-
-[INFO :CP0303] rtl/a23_coprocessor.v:41 Compile module "work@a23_coprocessor".
-
-[INFO :CP0303] rtl/a23_cache.v:47 Compile module "work@a23_cache".
-
-[INFO :CP0303] rtl/a23_execute.v:45 Compile module "work@a23_execute".
-
-[INFO :CP0303] rtl/a23_decode.v:43 Compile module "work@a23_decode".
-
-[INFO :CP0303] rtl/a23_decompile.v:44 Compile module "work@a23_decompile".
-
-[INFO :CP0303] rtl/a23_core.v:43 Compile module "work@a23_core".
-
-[INFO :CP0303] rtl/a23_ram_register_bank.v:44 Compile module "work@a23_ram_register_bank".
-
-[INFO :CP0303] rtl/a23_fetch.v:45 Compile module "work@a23_fetch".
-
-[INFO :CP0303] rtl/a23_register_bank.v:44 Compile module "work@a23_register_bank".
-
-[INFO :CP0303] rtl/a23_wishbone.v:58 Compile module "work@a23_wishbone".
-
-[INFO :CP0303] rtl/generic_sram_line_en.v:42 Compile module "work@generic_sram_line_en".
-
-[INFO :CP0303] sim/bench.v:2 Compile module "work@testbench".
-
-[INFO :CP0303] rtl/a23_multiply.v:56 Compile module "work@a23_multiply".
-
-[INFO :CP0303] rtl/generic_sram_byte_en.v:43 Compile module "work@generic_sram_byte_en".
-
-[NOTE :CP0309] rtl/a23_alu.v:51 Implicit port type (wire) for "o_out",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_coprocessor.v:58 Implicit port type (wire) for "o_cache_enable",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_execute.v:63 Implicit port type (wire) for "o_address_nxt",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_register_bank.v:71 Implicit port type (wire) for "o_rm",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_barrel_shift.v:50 Implicit port type (wire) for "o_out",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_core.v:53 Implicit port type (wire) for "o_wb_adr",
-there are 5 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_fetch.v:54 Implicit port type (wire) for "o_read_data",
-there are 7 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_wishbone.v:70 Implicit port type (wire) for "o_stall".
-
-[NOTE :CP0309] rtl/a23_barrel_shift_fpga.v:54 Implicit port type (wire) for "o_out",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_decode.v:81 Implicit port type (wire) for "o_rm_sel_nxt",
-there are 8 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_multiply.v:65 Implicit port type (wire) for "o_out",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_cache.v:98 Implicit port type (wire) for "o_read_data",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/a23_ram_register_bank.v:69 Implicit port type (wire) for "o_rm",
-there are 4 more instances of this message.
-
-[INFO :EL0526] Design Elaboration...
-
-[NOTE :EL0503] rtl/a23_decompile.v:44 Top level module "work@a23_decompile".
-
-[NOTE :EL0503] rtl/a23_barrel_shift_fpga.v:46 Top level module "work@a23_barrel_shift_fpga".
-
-[NOTE :EL0503] sim/bench.v:2 Top level module "work@testbench".
-
-[NOTE :EL0503] rtl/a23_ram_register_bank.v:44 Top level module "work@a23_ram_register_bank".
-
-[NOTE :EL0504] Multiple top level modules in design.
-
-[ERROR:EL0514] rtl/a23_decode.v:806 Undefined variable: instruction.
-
-[ERROR:EL0514] rtl/a23_decode.v:832 Undefined variable: instruction.
-
-[NOTE :EL0508] Nb Top level modules: 4.
-
-[NOTE :EL0509] Max instance depth: 6.
-
-[NOTE :EL0510] Nb instances: 23.
-
-[NOTE :EL0511] Nb leaf instances: 3.
-
-[  FATAL] : 0
-[  ERROR] : 3
-[WARNING] : 17
-[   NOTE] : 22
-
-********************************************
-*   End SURELOG SVerilog Compiler/Linter   *
-********************************************
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_alu.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_alu.v
deleted file mode 100644
index 6359680..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_alu.v
+++ /dev/null
@@ -1,154 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Arithmetic Logic Unit (ALU) for Amber 2 Core                //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Supported functions: 32-bit add and subtract, AND, OR,      //
-//  XOR, NOT, Zero extent 8-bit numbers                         //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module a23_alu (
-
-input       [31:0]          i_a_in,
-input       [31:0]          i_b_in,
-input                       i_barrel_shift_carry,
-input                       i_status_bits_carry,
-input       [8:0]           i_function,
-
-output      [31:0]          o_out,
-output      [3:0]           o_flags
-);
-
-wire     [31:0]         a, b, b_not;
-wire     [31:0]         and_out, or_out, xor_out;
-wire     [31:0]         sign_ex8_out, sign_ex_16_out;
-wire     [31:0]         zero_ex8_out, zero_ex_16_out;
-wire     [32:0]         fadder_out;
-wire                    swap_sel;
-wire                    not_sel;
-wire     [1:0]          cin_sel;
-wire                    cout_sel;
-wire     [3:0]          out_sel;
-wire                    carry_in;
-wire                    carry_out;
-wire                    overflow_out;
-wire                    fadder_carry_out;
-
-assign  { swap_sel, not_sel, cin_sel, cout_sel, out_sel } = i_function;
-
-
-// ========================================================
-// A Select
-// ========================================================
-assign a     = (swap_sel ) ? i_b_in : i_a_in ;
-
-// ========================================================
-// B Select
-// ========================================================
-assign b     = (swap_sel ) ? i_a_in : i_b_in ;
-                             
-// ========================================================
-// Not Select
-// ========================================================
-assign b_not     = (not_sel ) ? ~b : b ;
-                             
-// ========================================================
-// Cin Select
-// ========================================================
-assign carry_in  = (cin_sel==2'd0 ) ? 1'd0 :
-                   (cin_sel==2'd1 ) ? 1'd1 :
-                                      i_status_bits_carry    ;  // add with carry
-
-// ========================================================
-// Cout Select
-// ========================================================
-assign carry_out = (cout_sel==1'd0 ) ? fadder_carry_out     :
-                                       i_barrel_shift_carry ;
-
-// For non-addition/subtractions that incorporate a shift 
-// operation, C is set to the last bit
-// shifted out of the value by the shifter.
-
-
-// ========================================================
-// Overflow out
-// ========================================================
-// Only assert the overflow flag when using the adder
-assign  overflow_out    = out_sel == 4'd1 &&
-                            // overflow if adding two positive numbers and get a negative number
-                          ( (!a[31] && !b_not[31] && fadder_out[31]) ||
-                            // or adding two negative numbers and get a positive number
-                            (a[31] && b_not[31] && !fadder_out[31])     );
-
-
-// ========================================================
-// ALU Operations
-// ========================================================
-
-assign fadder_out       = { 1'd0,a} + {1'd0,b_not} + {32'd0,carry_in};
-
-assign fadder_carry_out = fadder_out[32];
-assign and_out          = a & b_not;
-assign or_out           = a | b_not;
-assign xor_out          = a ^ b_not;
-assign zero_ex8_out     = {24'd0,  b_not[7:0]};
-assign zero_ex_16_out   = {16'd0,  b_not[15:0]};
-assign sign_ex8_out     = {{24{b_not[7]}},  b_not[7:0]};
-assign sign_ex_16_out   = {{16{b_not[15]}}, b_not[15:0]};
-                          
-// ========================================================
-// Out Select
-// ========================================================
-assign o_out = out_sel == 4'd0 ? b_not            : 
-               out_sel == 4'd1 ? fadder_out[31:0] : 
-               out_sel == 4'd2 ? zero_ex_16_out   :
-               out_sel == 4'd3 ? zero_ex8_out     :
-               out_sel == 4'd4 ? sign_ex_16_out   :
-               out_sel == 4'd5 ? sign_ex8_out     :
-               out_sel == 4'd6 ? xor_out          :
-               out_sel == 4'd7 ? or_out           :
-                                 and_out          ;
-
-assign o_flags       = {  o_out[31],      // negative
-                         |o_out == 1'd0,  // zero
-                         carry_out,       // carry
-                         overflow_out     // overflow
-                         };
-                         
-                                     
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_barrel_shift.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_barrel_shift.v
deleted file mode 100644
index 54cc19b..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_barrel_shift.v
+++ /dev/null
@@ -1,367 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Barrel Shifter for Amber 2 Core                             //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Provides 32-bit shifts LSL, LSR, ASR and ROR                //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module a23_barrel_shift (
-
-input       [31:0]          i_in,
-input                       i_carry_in,
-input       [7:0]           i_shift_amount,     // uses 8 LSBs of Rs, or a 5 bit immediate constant
-input                       i_shift_imm_zero,   // high when immediate shift value of zero selected
-input       [1:0]           i_function,
-
-output      [31:0]          o_out,
-output                      o_carry_out
-
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
-
-  // MSB is carry out
-wire [32:0] lsl_out;
-wire [32:0] lsr_out;
-wire [32:0] asr_out;
-wire [32:0] ror_out;
-
-
-// Logical shift right zero is redundant as it is the same as logical shift left zero, so
-// the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow
-// lsr #32 to be specified.
-
-// lsl #0 is a special case, where the shifter carry out is the old value of the status flags
-// C flag. The contents of Rm are used directly as the second operand.
-assign lsl_out = i_shift_imm_zero         ? {i_carry_in, i_in              } :  // fall through case 
-
-                 i_shift_amount == 8'd0 ? {i_carry_in, i_in              } :  // fall through case
-                 i_shift_amount == 8'd1 ? {i_in[31],   i_in[30: 0],  1'd0} :
-                 
-                 i_shift_amount == 8'd2 ? {i_in[30],   i_in[29: 0],  2'd0} :
-                 i_shift_amount == 8'd3 ? {i_in[29],   i_in[28: 0],  3'd0} :
-                 i_shift_amount == 8'd4 ? {i_in[28],   i_in[27: 0],  4'd0} :
-                 i_shift_amount == 8'd5 ? {i_in[27],   i_in[26: 0],  5'd0} :
-                 i_shift_amount == 8'd6 ? {i_in[26],   i_in[25: 0],  6'd0} :
-                 i_shift_amount == 8'd7 ? {i_in[25],   i_in[24: 0],  7'd0} :
-                 i_shift_amount == 8'd8 ? {i_in[24],   i_in[23: 0],  8'd0} :
-                 i_shift_amount == 8'd9 ? {i_in[23],   i_in[22: 0],  9'd0} :
-                 i_shift_amount == 8'd10 ? {i_in[22],   i_in[21: 0], 10'd0} :
-                 i_shift_amount == 8'd11 ? {i_in[21],   i_in[20: 0], 11'd0} :
-                    
-                 i_shift_amount == 8'd12 ? {i_in[20],   i_in[19: 0], 12'd0} :
-                 i_shift_amount == 8'd13 ? {i_in[19],   i_in[18: 0], 13'd0} :
-                 i_shift_amount == 8'd14 ? {i_in[18],   i_in[17: 0], 14'd0} :
-                 i_shift_amount == 8'd15 ? {i_in[17],   i_in[16: 0], 15'd0} :
-                 i_shift_amount == 8'd16 ? {i_in[16],   i_in[15: 0], 16'd0} :
-                 i_shift_amount == 8'd17 ? {i_in[15],   i_in[14: 0], 17'd0} :
-                 i_shift_amount == 8'd18 ? {i_in[14],   i_in[13: 0], 18'd0} :
-                 i_shift_amount == 8'd19 ? {i_in[13],   i_in[12: 0], 19'd0} :
-                 i_shift_amount == 8'd20 ? {i_in[12],   i_in[11: 0], 20'd0} :
-                 i_shift_amount == 8'd21 ? {i_in[11],   i_in[10: 0], 21'd0} :
-
-                 i_shift_amount == 8'd22 ? {i_in[10],   i_in[ 9: 0], 22'd0} :
-                 i_shift_amount == 8'd23 ? {i_in[ 9],   i_in[ 8: 0], 23'd0} :
-                 i_shift_amount == 8'd24 ? {i_in[ 8],   i_in[ 7: 0], 24'd0} :
-                 i_shift_amount == 8'd25 ? {i_in[ 7],   i_in[ 6: 0], 25'd0} :
-                 i_shift_amount == 8'd26 ? {i_in[ 6],   i_in[ 5: 0], 26'd0} :
-                 i_shift_amount == 8'd27 ? {i_in[ 5],   i_in[ 4: 0], 27'd0} :
-                 i_shift_amount == 8'd28 ? {i_in[ 4],   i_in[ 3: 0], 28'd0} :
-                 i_shift_amount == 8'd29 ? {i_in[ 3],   i_in[ 2: 0], 29'd0} :
-                 i_shift_amount == 8'd30 ? {i_in[ 2],   i_in[ 1: 0], 30'd0} :
-                 i_shift_amount == 8'd31 ? {i_in[ 1],   i_in[ 0: 0], 31'd0} :
-                 i_shift_amount == 8'd32 ? {i_in[ 0],   32'd0 } :  // 32
-                                            {1'd0,       32'd0 } ;  // > 32
-                                            
-
-// The form of the shift field which might be expected to correspond to LSR #0 is used
-// to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. 
-                                           // carry out, < -------- out ---------->
-assign lsr_out = i_shift_imm_zero         ? {i_in[31], 32'd0 } :
-
-                 i_shift_amount == 8'd0 ? {i_carry_in, i_in            } :  // fall through case
-                 i_shift_amount == 8'd1 ? {i_in[ 0],  1'd0, i_in[31: 1]} :
-                 i_shift_amount == 8'd2 ? {i_in[ 1],  2'd0, i_in[31: 2]} :
-                 i_shift_amount == 8'd3 ? {i_in[ 2],  3'd0, i_in[31: 3]} :
-                 i_shift_amount == 8'd4 ? {i_in[ 3],  4'd0, i_in[31: 4]} :
-                 i_shift_amount == 8'd5 ? {i_in[ 4],  5'd0, i_in[31: 5]} :
-                 i_shift_amount == 8'd6 ? {i_in[ 5],  6'd0, i_in[31: 6]} :
-                 i_shift_amount == 8'd7 ? {i_in[ 6],  7'd0, i_in[31: 7]} :
-                 i_shift_amount == 8'd8 ? {i_in[ 7],  8'd0, i_in[31: 8]} :
-                 i_shift_amount == 8'd9 ? {i_in[ 8],  9'd0, i_in[31: 9]} :
-                    
-                 i_shift_amount == 8'd10 ? {i_in[ 9], 10'd0, i_in[31:10]} :
-                 i_shift_amount == 8'd11 ? {i_in[10], 11'd0, i_in[31:11]} :
-                 i_shift_amount == 8'd12 ? {i_in[11], 12'd0, i_in[31:12]} :
-                 i_shift_amount == 8'd13 ? {i_in[12], 13'd0, i_in[31:13]} :
-                 i_shift_amount == 8'd14 ? {i_in[13], 14'd0, i_in[31:14]} :
-                 i_shift_amount == 8'd15 ? {i_in[14], 15'd0, i_in[31:15]} :
-                 i_shift_amount == 8'd16 ? {i_in[15], 16'd0, i_in[31:16]} :
-                 i_shift_amount == 8'd17 ? {i_in[16], 17'd0, i_in[31:17]} :
-                 i_shift_amount == 8'd18 ? {i_in[17], 18'd0, i_in[31:18]} :
-                 i_shift_amount == 8'd19 ? {i_in[18], 19'd0, i_in[31:19]} :
-
-                 i_shift_amount == 8'd20 ? {i_in[19], 20'd0, i_in[31:20]} :
-                 i_shift_amount == 8'd21 ? {i_in[20], 21'd0, i_in[31:21]} :
-                 i_shift_amount == 8'd22 ? {i_in[21], 22'd0, i_in[31:22]} :
-                 i_shift_amount == 8'd23 ? {i_in[22], 23'd0, i_in[31:23]} :
-                 i_shift_amount == 8'd24 ? {i_in[23], 24'd0, i_in[31:24]} :
-                 i_shift_amount == 8'd25 ? {i_in[24], 25'd0, i_in[31:25]} :
-                 i_shift_amount == 8'd26 ? {i_in[25], 26'd0, i_in[31:26]} :
-                 i_shift_amount == 8'd27 ? {i_in[26], 27'd0, i_in[31:27]} :
-                 i_shift_amount == 8'd28 ? {i_in[27], 28'd0, i_in[31:28]} :
-                 i_shift_amount == 8'd29 ? {i_in[28], 29'd0, i_in[31:29]} :
-
-                 i_shift_amount == 8'd30 ? {i_in[29], 30'd0, i_in[31:30]} :
-                 i_shift_amount == 8'd31 ? {i_in[30], 31'd0, i_in[31 ]} :
-                 i_shift_amount == 8'd32 ? {i_in[31], 32'd0 } :
-                                            {1'd0,     32'd0 } ;  // > 32
-
-
-// The form of the shift field which might be expected to give ASR #0 is used to encode
-// ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is
-// also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to
-// the value of bit 31 of Rm.
-
-                                          // carry out, < -------- out ---------->
-assign asr_out = i_shift_imm_zero         ? {i_in[31], {32{i_in[31]}}             } :
-
-                 i_shift_amount == 8'd0 ? {i_carry_in, i_in                     } :  // fall through case
-                 i_shift_amount == 8'd1 ? {i_in[ 0], { 2{i_in[31]}}, i_in[30: 1]} :
-                 i_shift_amount == 8'd2 ? {i_in[ 1], { 3{i_in[31]}}, i_in[30: 2]} :
-                 i_shift_amount == 8'd3 ? {i_in[ 2], { 4{i_in[31]}}, i_in[30: 3]} :
-                 i_shift_amount == 8'd4 ? {i_in[ 3], { 5{i_in[31]}}, i_in[30: 4]} :
-                 i_shift_amount == 8'd5 ? {i_in[ 4], { 6{i_in[31]}}, i_in[30: 5]} :
-                 i_shift_amount == 8'd6 ? {i_in[ 5], { 7{i_in[31]}}, i_in[30: 6]} :
-                 i_shift_amount == 8'd7 ? {i_in[ 6], { 8{i_in[31]}}, i_in[30: 7]} :
-                 i_shift_amount == 8'd8 ? {i_in[ 7], { 9{i_in[31]}}, i_in[30: 8]} :
-                 i_shift_amount == 8'd9 ? {i_in[ 8], {10{i_in[31]}}, i_in[30: 9]} :
-                    
-                 i_shift_amount == 8'd10 ? {i_in[ 9], {11{i_in[31]}}, i_in[30:10]} :
-                 i_shift_amount == 8'd11 ? {i_in[10], {12{i_in[31]}}, i_in[30:11]} :
-                 i_shift_amount == 8'd12 ? {i_in[11], {13{i_in[31]}}, i_in[30:12]} :
-                 i_shift_amount == 8'd13 ? {i_in[12], {14{i_in[31]}}, i_in[30:13]} :
-                 i_shift_amount == 8'd14 ? {i_in[13], {15{i_in[31]}}, i_in[30:14]} :
-                 i_shift_amount == 8'd15 ? {i_in[14], {16{i_in[31]}}, i_in[30:15]} :
-                 i_shift_amount == 8'd16 ? {i_in[15], {17{i_in[31]}}, i_in[30:16]} :
-                 i_shift_amount == 8'd17 ? {i_in[16], {18{i_in[31]}}, i_in[30:17]} :
-                 i_shift_amount == 8'd18 ? {i_in[17], {19{i_in[31]}}, i_in[30:18]} :
-                 i_shift_amount == 8'd19 ? {i_in[18], {20{i_in[31]}}, i_in[30:19]} :
-
-                 i_shift_amount == 8'd20 ? {i_in[19], {21{i_in[31]}}, i_in[30:20]} :
-                 i_shift_amount == 8'd21 ? {i_in[20], {22{i_in[31]}}, i_in[30:21]} :
-                 i_shift_amount == 8'd22 ? {i_in[21], {23{i_in[31]}}, i_in[30:22]} :
-                 i_shift_amount == 8'd23 ? {i_in[22], {24{i_in[31]}}, i_in[30:23]} :
-                 i_shift_amount == 8'd24 ? {i_in[23], {25{i_in[31]}}, i_in[30:24]} :
-                 i_shift_amount == 8'd25 ? {i_in[24], {26{i_in[31]}}, i_in[30:25]} :
-                 i_shift_amount == 8'd26 ? {i_in[25], {27{i_in[31]}}, i_in[30:26]} :
-                 i_shift_amount == 8'd27 ? {i_in[26], {28{i_in[31]}}, i_in[30:27]} :
-                 i_shift_amount == 8'd28 ? {i_in[27], {29{i_in[31]}}, i_in[30:28]} :
-                 i_shift_amount == 8'd29 ? {i_in[28], {30{i_in[31]}}, i_in[30:29]} :
-
-                 i_shift_amount == 8'd30 ? {i_in[29], {31{i_in[31]}}, i_in[30 ]} :
-                 i_shift_amount == 8'd31 ? {i_in[30], {32{i_in[31]}}             } :
-                                            {i_in[31], {32{i_in[31]}}             } ; // >= 32
-                                            
-
-                                          // carry out, < ------- out --------->
-assign ror_out = i_shift_imm_zero              ? {i_in[ 0], i_carry_in,  i_in[31: 1]} :  // RXR, (ROR w/ imm 0)
-
-                 i_shift_amount[7:0] == 8'd0 ? {i_carry_in, i_in                  } :  // fall through case
-                 
-                 i_shift_amount[4:0] == 5'd0 ? {i_in[31], i_in                    } :  // Rs > 31
-                 i_shift_amount[4:0] == 5'd1 ? {i_in[ 0], i_in[    0], i_in[31: 1]} :
-                 i_shift_amount[4:0] == 5'd2 ? {i_in[ 1], i_in[ 1: 0], i_in[31: 2]} :
-                 i_shift_amount[4:0] == 5'd3 ? {i_in[ 2], i_in[ 2: 0], i_in[31: 3]} :
-                 i_shift_amount[4:0] == 5'd4 ? {i_in[ 3], i_in[ 3: 0], i_in[31: 4]} :
-                 i_shift_amount[4:0] == 5'd5 ? {i_in[ 4], i_in[ 4: 0], i_in[31: 5]} :
-                 i_shift_amount[4:0] == 5'd6 ? {i_in[ 5], i_in[ 5: 0], i_in[31: 6]} :
-                 i_shift_amount[4:0] == 5'd7 ? {i_in[ 6], i_in[ 6: 0], i_in[31: 7]} :
-                 i_shift_amount[4:0] == 5'd8 ? {i_in[ 7], i_in[ 7: 0], i_in[31: 8]} :
-                 i_shift_amount[4:0] == 5'd9 ? {i_in[ 8], i_in[ 8: 0], i_in[31: 9]} :
-                    
-                 i_shift_amount[4:0] == 5'd10 ? {i_in[ 9], i_in[ 9: 0], i_in[31:10]} :
-                 i_shift_amount[4:0] == 5'd11 ? {i_in[10], i_in[10: 0], i_in[31:11]} :
-                 i_shift_amount[4:0] == 5'd12 ? {i_in[11], i_in[11: 0], i_in[31:12]} :
-                 i_shift_amount[4:0] == 5'd13 ? {i_in[12], i_in[12: 0], i_in[31:13]} :
-                 i_shift_amount[4:0] == 5'd14 ? {i_in[13], i_in[13: 0], i_in[31:14]} :
-                 i_shift_amount[4:0] == 5'd15 ? {i_in[14], i_in[14: 0], i_in[31:15]} :
-                 i_shift_amount[4:0] == 5'd16 ? {i_in[15], i_in[15: 0], i_in[31:16]} :
-                 i_shift_amount[4:0] == 5'd17 ? {i_in[16], i_in[16: 0], i_in[31:17]} :
-                 i_shift_amount[4:0] == 5'd18 ? {i_in[17], i_in[17: 0], i_in[31:18]} :
-                 i_shift_amount[4:0] == 5'd19 ? {i_in[18], i_in[18: 0], i_in[31:19]} :
-
-                 i_shift_amount[4:0] == 5'd20 ? {i_in[19], i_in[19: 0], i_in[31:20]} :
-                 i_shift_amount[4:0] == 5'd21 ? {i_in[20], i_in[20: 0], i_in[31:21]} :
-                 i_shift_amount[4:0] == 5'd22 ? {i_in[21], i_in[21: 0], i_in[31:22]} :
-                 i_shift_amount[4:0] == 5'd23 ? {i_in[22], i_in[22: 0], i_in[31:23]} :
-                 i_shift_amount[4:0] == 5'd24 ? {i_in[23], i_in[23: 0], i_in[31:24]} :
-                 i_shift_amount[4:0] == 5'd25 ? {i_in[24], i_in[24: 0], i_in[31:25]} :
-                 i_shift_amount[4:0] == 5'd26 ? {i_in[25], i_in[25: 0], i_in[31:26]} :
-                 i_shift_amount[4:0] == 5'd27 ? {i_in[26], i_in[26: 0], i_in[31:27]} :
-                 i_shift_amount[4:0] == 5'd28 ? {i_in[27], i_in[27: 0], i_in[31:28]} :
-                 i_shift_amount[4:0] == 5'd29 ? {i_in[28], i_in[28: 0], i_in[31:29]} :
-
-                 i_shift_amount[4:0] == 5'd30 ? {i_in[29], i_in[29: 0], i_in[31:30]} :
-                                                 {i_in[30], i_in[30: 0], i_in[31:31]} ;
-                 
-
- 
-assign {o_carry_out, o_out} = i_function == LSL ? lsl_out :
-                              i_function == LSR ? lsr_out :
-                              i_function == ASR ? asr_out :
-                                                  ror_out ;
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_barrel_shift_fpga.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_barrel_shift_fpga.v
deleted file mode 100644
index 9ffc3e6..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_barrel_shift_fpga.v
+++ /dev/null
@@ -1,417 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Barrel Shifter for Amber 2 Core                             //
-//                                                              //
-//  The design is optimized for Altera family of FPGAs,         //
-//  and it can be used directly or adapted other N-to-1 LUT     //
-//  FPGA platforms.                                             //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Provides 32-bit shifts LSL, LSR, ASR and ROR                //
-//                                                              //
-//  Author(s):                                                  //
-//      - Dmitry Tarnyagin, dmitry.tarnyagin@lockless.no        //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010-2013 Authors and OPENCORES.ORG            //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module a23_barrel_shift_fpga (
-
-input       [31:0]          i_in,
-input                       i_carry_in,
-input       [7:0]           i_shift_amount,     // uses 8 LSBs of Rs, or a 5 bit immediate constant
-input                       i_shift_imm_zero,   // high when immediate shift value of zero selected
-input       [1:0]           i_function,
-
-output      [31:0]          o_out,
-output                      o_carry_out
-
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
-
-wire [31:0] rot_prod;                           // Input rotated by the shift amount
-
-wire [1:0]  lsl_out;                            // LSL: {carry, bit_31}
-wire [1:0]  lsr_out;                            // LSR: {carry, bit_31}
-wire [1:0]  asr_out;                            // ASR: {carry, bit_31}
-wire [1:0]  ror_out;                            // ROR: {carry, bit_31}
-
-reg [32:0]  lsl_mask;                           // Left-hand mask
-reg [32:0]  lsr_mask;                           // Right-hand mask
-reg [15:0]  low_mask;                           // Mask calculation helper
-
-reg [4:0]   shift_amount;                       // Shift amount for the low-level shifter
-
-reg [2:0]   lsl_selector;                       // Left shift {shift_32, shift_over, shift_amount[4]}
-reg [2:0]   lsr_selector;                       // Right shift {shift_32, shift_over, shift_amount[4]}
-reg [3:0]   low_selector;                       // {shift_amount[3:0]}
-
-reg         shift_nzero;                        // Amount is not zero
-reg         shift_over;                         // Amount is 32 or higher
-reg         shift_32;                           // Amount is exactly 32
-reg         asr_sign;                           // Sign for ASR shift
-reg         direction;                          // Shift direction
-
-wire [31:0] p_r;                                // 1 bit rotated rot_prod
-wire [31:0] p_l;                                // Alias for the rot_prod 
-
-
-// Implementation details:
-// Design is based on masking of rotated input by a left- and right- hand masks.
-// Rotated product calculation requires 5 levels of combinational logic, and masks
-// must be ready before the product is ready. In fact masks require just 3 to 4 levels
-// of logic cells using 4-to-1/2x3-to-1 Altera.
-
-always @*
-begin
-	shift_32 = i_shift_amount == 32;
-
-	shift_over = |i_shift_amount[7:5];
-
-	shift_nzero = |i_shift_amount[7:0];
-
-	shift_amount = i_shift_amount[4:0];
-
-	if (i_shift_imm_zero) begin
-		if (i_function == LSR || i_function == ASR) begin
-			// The form of the shift field which might be
-			// expected to correspond to LSR #0 is used
-			// to encode LSR #32, which has a zero result
-			// with bit 31 of Rm as the carry output. 
-			shift_nzero = 1'b1;
-			shift_over = 1'b1;
-			// Redundant and can be optimized out
-			// shift_32 = 1'b1;
-		end else if (i_function == ROR) begin
-			// RXR, (ROR w/ imm 0)
-			shift_amount[0] = 1'b1;
-			shift_nzero = 1'b1;
-		end
-	end
-
-	// LSB sub-selector calculation. Usually it is taken
-	// directly from the shift_amount, but ROR requires
-	// no masking at all.
-	case (i_function)
-		LSL: low_selector = shift_amount[3:0];
-		LSR: low_selector = shift_amount[3:0];
-		ASR: low_selector = shift_amount[3:0];
-		ROR: low_selector = 4'b0000;
-	endcase
-
-	// Left-hand MSB sub-selector calculation. Opaque for every function but LSL.
-	case (i_function)
-		LSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
-		LSR: lsl_selector = 3'b0_1_0; // Opaque mask selector
-		ASR: lsl_selector = 3'b0_1_0; // Opaque mask selector
-		ROR: lsl_selector = 3'b0_1_0; // Opaque mask selector
-	endcase
-
-	// Right-hand MSB sub-selector calculation. Opaque for LSL, transparent for ROR.
-	case (i_function)
-		LSL: lsr_selector = 3'b0_1_0; // Opaque mask selector
-		LSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
-		ASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
-		ROR: lsr_selector = 3'b0_0_0; // Transparent mask selector
-	endcase
-
-	// Direction
-	case (i_function)
-		LSL: direction = 1'b0; // Left shift
-		LSR: direction = 1'b1; // Right shift
-		ASR: direction = 1'b1; // Right shift
-		ROR: direction = 1'b1; // Right shift
-	endcase
-
-	// Sign for ASR shift
-	asr_sign = 1'b0;
-	if (i_function == ASR && i_in[31])
-		asr_sign = 1'b1;
-end
-
-// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
-// Practically a bit higher due to high fanout of "direction".
-generate
-genvar i, j;
-	for (i = 0; i < 5; i = i + 1)
-	begin : netgen
-		wire [31:0] in;
-		reg [31:0] out;
-		for (j = 0; j < 32; j = j + 1)
-		begin : net
-			always @*
-				out[j] = in[j] & (~shift_amount[i] ^ direction) |
-					 in[wrap(j, i)] & (shift_amount[i] ^ direction);
-		end
-	end
-
-	// Order is reverted with respect to volatile shift_amount[0]
-	assign netgen[4].in = i_in;
-	for (i = 1; i < 5; i = i + 1)
-	begin : router
-		assign netgen[i-1].in = netgen[i].out;
-	end
-endgenerate
-
-// Aliasing
-assign rot_prod = netgen[0].out;
-
-// Submask calculated from LSB sub-selector.
-// Cost: 16 4-to-1 LUTs.
-always @*
-case (low_selector) // synthesis full_case parallel_case
-	4'b0000:	low_mask = 16'hffff;
-	4'b0001:	low_mask = 16'hfffe;
-	4'b0010:	low_mask = 16'hfffc;
-	4'b0011:	low_mask = 16'hfff8;
-	4'b0100:	low_mask = 16'hfff0;
-	4'b0101:	low_mask = 16'hffe0;
-	4'b0110:	low_mask = 16'hffc0;
-	4'b0111:	low_mask = 16'hff80;
-	4'b1000:	low_mask = 16'hff00;
-	4'b1001:	low_mask = 16'hfe00;
-	4'b1010:	low_mask = 16'hfc00;
-	4'b1011:	low_mask = 16'hf800;
-	4'b1100:	low_mask = 16'hf000;
-	4'b1101:	low_mask = 16'he000;
-	4'b1110:	low_mask = 16'hc000;
-	4'b1111:	low_mask = 16'h8000;
-endcase
-
-// Left-hand mask calculation.
-// Cost: 33 4-to-1 LUTs.
-always @*
-casez (lsl_selector) // synthesis full_case parallel_case
-	7'b1??:	lsl_mask =  33'h1_0000_0000;
-	7'b01?:	lsl_mask =  33'h0_0000_0000;
-	7'b001:	lsl_mask = { 1'h1, low_mask, 16'h0000};
-	7'b000:	lsl_mask = {17'h1_ffff, low_mask};
-endcase
-
-// Right-hand mask calculation.
-// Cost: 33 4-to-1 LUTs.
-always @*
-casez (lsr_selector) // synthesis full_case parallel_case
-	7'b1??:	lsr_mask =  33'h1_0000_0000;
-	7'b01?:	lsr_mask =  33'h0_0000_0000;
-	7'b000:	lsr_mask = { 1'h1, bit_swap(low_mask), 16'hffff};
-	7'b001:	lsr_mask = {17'h1_0000, bit_swap(low_mask)};
-endcase
-
-// Alias: right-rotated
-assign p_r = {rot_prod[30:0], rot_prod[31]};
-
-// Alias: left-rotated
-assign p_l = rot_prod[31:0];
-
-// ROR MSB, handling special cases
-assign ror_out[0] = i_shift_imm_zero ?	i_carry_in :
-					p_r[31];
-
-// ROR carry, handling special cases
-assign ror_out[1] = i_shift_imm_zero ?	i_in[0] :
-			shift_nzero ?	p_r[31] :
-					i_carry_in;
-
-// LSL MSB
-assign lsl_out[0] = 	p_l[31] & lsl_mask[31];
-
-// LSL carry, handling special cases
-assign lsl_out[1] = 	shift_nzero ?	p_l[0] & lsl_mask[32]:
-					i_carry_in;
-
-// LSR MSB
-assign lsr_out[0] = 	p_r[31] & lsr_mask[31];
-
-// LSR carry, handling special cases
-assign lsr_out[1] = i_shift_imm_zero ?	i_in[31] :
-			shift_nzero ?	p_r[31] & lsr_mask[32]:
-					i_carry_in;
-
-// ASR MSB
-assign asr_out[0] = 	i_in[31] ?	i_in[31] :
-					p_r[31] & lsr_mask[31] ;
-
-// LSR carry, handling special cases
-assign asr_out[1] =	shift_over ?	i_in[31] :
-			shift_nzero ?	p_r[31] :
-					i_carry_in;
-
-// Carry and MSB are calculated as above
-assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
-                              i_function == LSR ? lsr_out :
-                              i_function == ASR ? asr_out :
-                                                  ror_out ;
-
-// And the rest of result is the masked rotated input.
-assign o_out[30:0] =	(p_l[30:0] & lsl_mask[30:0]) |
-			(p_r[30:0] & lsr_mask[30:0]) |
-			(~lsr_mask[30:0] & {31{asr_sign}});
-
-// Rotate: calculate bit pos for level "level" and offset "pos"
-function [4:0] wrap;
-input integer pos;
-input integer level;
-integer out;
-begin
-	out = pos - (1 << level);
-	wrap = out[4:0];
-end
-endfunction
-
-// Swap bits in the input 16-bit value
-function [15:0] bit_swap;
-input [15:0] value;
-integer i;
-begin
-	for (i = 0; i < 16; i = i + 1)
-		bit_swap[i] = value[15 - i];
-end
-endfunction
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_cache.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_cache.v
deleted file mode 100644
index 45792bb..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_cache.v
+++ /dev/null
@@ -1,1296 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  L1 Cache for Amber 2 Core                                   //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Synthesizable L1 Unified Data and Instruction Cache         //
-//  Cache is 4-way, 256 line and 16 bytes per line for          //
-//  a total of 16KB. The cache policy is write-through and      //
-//  read allocate. For swap instructions (SWP and SWPB) the     //
-//  location is evicted from the cache and read from main       //
-//  memory.                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Global testbench defines                                    //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains a set of defines for each module so if the module  //
-//  hierarchy changes, hierarchical references to signals       //
-//  will still work as long as this file is updated.            //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-// ---------------------------------------------------------------
-// Module hierarchy defines
-// ---------------------------------------------------------------
-
-    
-
-
-        // ---------------------------------------------------------------
-
-
-
-// Simplified Main Memory Model
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Amber Configuration and Debug for the AMber 2 Core          //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains a set of defines used to configure and debug       //
-//  the Amber core                                              //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Cache Ways
-// Changing this parameter is the recommended
-// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported.
-//   2 ways -> 8KB  cache
-//   3 ways -> 12KB cache
-//   4 ways -> 16KB cache
-//   8 ways -> 32KB cache
-
-// Use ram-based register bank implementation
-// `define A23_RAM_REGISTER_BANK
-
-// --------------------------------------------------------------------
-// Debug switches 
-// --------------------------------------------------------------------
-
-// Enable the decompiler. The default output file is amber.dis
-//`define A23_DECOMPILE
-
-// Co-processor 15 debug. Registers in here control the cache
-//`define A23_COPRO15_DEBUG
-
-// Cache debug
-//`define A23_CACHE_DEBUG
-
-// --------------------------------------------------------------------
-
-
-// --------------------------------------------------------------------
-// File Names
-// --------------------------------------------------------------------
-    
-
-
-module a23_cache 
-#(
-
-// ---------------------------------------------------------
-// Cache Configuration
-
-// Limited to Linux 4k page sizes -> 256 lines
-parameter CACHE_LINES          = 256,  
-
-// This cannot be changed without some major surgeory on
-// this module                                       
-parameter CACHE_WORDS_PER_LINE = 4,
-
-// Changing this parameter is the recommended
-// way to change the overall cache size; 2, 4 and 8 ways are supported.
-//   2 ways -> 8KB  cache
-//   4 ways -> 16KB cache
-//   8 ways -> 32KB cache
-parameter WAYS              = 4 ,
-
-// derived configuration parameters
-parameter CACHE_ADDR_WIDTH  = 8, // log2 ( CACHE_LINES ),                  // = 8
-parameter WORD_SEL_WIDTH    = 2, // log2 ( CACHE_WORDS_PER_LINE ),         // = 2
-parameter TAG_ADDR_WIDTH    = 32 - CACHE_ADDR_WIDTH - WORD_SEL_WIDTH - 2,  // = 20
-parameter TAG_WIDTH         = TAG_ADDR_WIDTH + 1,                          // = 21, including Valid flag
-parameter CACHE_LINE_WIDTH  = CACHE_WORDS_PER_LINE * 32,                   // = 128
-parameter TAG_ADDR32_LSB    = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2,       // = 12
-parameter CACHE_ADDR32_MSB  = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2 - 1,   // = 11
-parameter CACHE_ADDR32_LSB  =                    WORD_SEL_WIDTH + 2 ,   // = 4
-parameter WORD_SEL_MSB      = WORD_SEL_WIDTH + 2 - 1,                      // = 3
-parameter WORD_SEL_LSB      =                  2 // = 2
-// ---------------------------------------------------------
-)
-
-
-(
-input                               i_clk,
-
-// Read / Write requests from core
-input                               i_select,
-input                               i_exclusive,        // exclusive access, part of swap instruction
-input      [31:0]                   i_write_data,
-input                               i_write_enable,     // core issued write request
-input      [31:0]                   i_address,          // registered address from execute
-input      [31:0]                   i_address_nxt,      // un-registered version of address from execute stage
-input      [3:0]                    i_byte_enable,
-input                               i_cache_enable,     // from co-processor 15 configuration register
-input                               i_cache_flush,      // from co-processor 15 register
-
-output      [31:0]                  o_read_data,                                                       
-input                               i_core_stall,
-output                              o_stall,
-
-// WB Read Request                                                          
-output                              o_wb_req,          // Read Request
-input      [31:0]                   i_wb_address,      // wb bus                                 
-input      [31:0]                   i_wb_read_data,    // wb bus                              
-input                               i_wb_stall         // wb_stb && !wb_ack
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Functions for Amber 2 Core                                  //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Functions used in more than one module                      //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// ========================================================
-// PC Filter - Remove the status bits 
-// ========================================================
-function [31:0] pcf;
-input [31:0] pc_reg;
-    begin
-    pcf = {6'd0, pc_reg[25:2], 2'd0};
-    end
-endfunction
-
-
-// ========================================================
-// 4-bit to 16-bit 1-hot decode
-// ========================================================
-function [14:0] decode;
-input [3:0] reg_sel;
-begin
-case ( reg_sel )
-    4'h0:    decode = 15'h0001;
-    4'h1:    decode = 15'h0002;
-    4'h2:    decode = 15'h0004;
-    4'h3:    decode = 15'h0008;
-    4'h4:    decode = 15'h0010;
-    4'h5:    decode = 15'h0020;
-    4'h6:    decode = 15'h0040;
-    4'h7:    decode = 15'h0080;
-    4'h8:    decode = 15'h0100;
-    4'h9:    decode = 15'h0200;
-    4'ha:    decode = 15'h0400;
-    4'hb:    decode = 15'h0800;
-    4'hc:    decode = 15'h1000;
-    4'hd:    decode = 15'h2000;
-    4'he:    decode = 15'h4000;
-    default: decode = 15'h0000;
-endcase
-end
-endfunction
-
-
-// ========================================================
-// Convert Stats Bits Mode to one-hot encoded version
-// ========================================================
-function [3:0] oh_status_bits_mode;
-input [1:0] fn_status_bits_mode;
-begin
-oh_status_bits_mode = 
-    fn_status_bits_mode == SVC  ? 1'd1 << OH_SVC  :
-    fn_status_bits_mode == IRQ  ? 1'd1 << OH_IRQ  :
-    fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ :
-                                  1'd1 << OH_USR  ;
-end
-endfunction
-
-// ========================================================
-// Convert mode into ascii name
-// ========================================================
-function [(14*8)-1:0]  mode_name;
-input [4:0] mode;
-begin
-
-mode_name    = mode == USR  ? "User          " :
-               mode == SVC  ? "Supervisor    " :
-               mode == IRQ  ? "Interrupt     " :
-               mode == FIRQ ? "Fast Interrupt" :
-                              "UNKNOWN       " ;
-end
-endfunction
-
-
-// ========================================================
-// Conditional Execution Function
-// ========================================================
-// EQ Z set
-// NE Z clear
-// CS C set
-// CC C clear
-// MI N set
-// PL N clear
-// VS V set
-// VC V clear
-// HI C set and Z clear
-// LS C clear or Z set
-// GE N == V
-// LT N != V
-// GT Z == 0,N == V
-// LE Z == 1 or N != V
-// AL Always (unconditional)
-// NV Never
-
-function conditional_execute;
-input [3:0] condition;
-input [3:0] flags;
-begin
-conditional_execute  
-               = ( condition == AL                                        ) ||
-                 ( condition == EQ  &&  flags[2]                          ) ||
-                 ( condition == NE  && !flags[2]                          ) ||
-                 ( condition == CS  &&  flags[1]                          ) ||
-                 ( condition == CC  && !flags[1]                          ) ||
-                 ( condition == MI  &&  flags[3]                          ) ||
-                 ( condition == PL  && !flags[3]                          ) ||
-                 ( condition == VS  &&  flags[0]                          ) ||
-                 ( condition == VC  && !flags[0]                          ) ||
-            
-                 ( condition == HI  &&    flags[1] && !flags[2]           ) ||
-                 ( condition == LS  &&  (!flags[1] ||  flags[2])          ) ||
-            
-                 ( condition == GE  &&  flags[3] == flags[0]              ) ||
-                 ( condition == LT  &&  flags[3] != flags[0]              ) ||
-
-                 ( condition == GT  &&  !flags[2] && flags[3] == flags[0] ) ||
-                 ( condition == LE  &&  (flags[2] || flags[3] != flags[0])) ;
-            
-end
-endfunction
-
-
-// ========================================================
-// Log 2
-// ========================================================
-
-function [31:0] log2;
-input    [31:0] num;
-integer i;
-integer out;
-begin
-  out = 32'd0;
-  for (i=0; i<30; i=i+1)
-    if ((2**i > num) && (out == 0))
-      out = i-1;
-  log2 = out;
-end
-endfunction
-
-// One-hot encoded
-localparam       C_INIT   = 0,
-                 C_CORE   = 1,
-                 C_FILL   = 2,
-                 C_INVA   = 3,
-                 C_STATES = 4;
-                 
-localparam [3:0] CS_INIT            = 4'd0,
-                 CS_IDLE            = 4'd1,
-                 CS_FILL1           = 4'd2,
-                 CS_FILL2           = 4'd3,
-                 CS_FILL3           = 4'd4,
-                 CS_FILL4           = 4'd5,
-                 CS_FILL_COMPLETE   = 4'd6,
-                 CS_TURN_AROUND     = 4'd7,
-                 CS_WRITE_HIT1      = 4'd8,
-                 CS_EX_DELETE       = 4'd9;
-                 
-
-reg  [3:0]                  c_state    = CS_IDLE;
-reg  [C_STATES-1:0]         source_sel = 1'd1 << C_CORE;
-reg  [CACHE_ADDR_WIDTH:0]   init_count = 'd0;
-                 
-wire [TAG_WIDTH-1:0]        tag_rdata_way [WAYS-1:0];
-wire [CACHE_LINE_WIDTH-1:0] data_rdata_way[WAYS-1:0];
-wire [WAYS-1:0]             data_wenable_way;
-wire [WAYS-1:0]             data_hit_way;
-wire [WAYS-1:0]             tag_wenable_way;
-reg  [WAYS-1:0]             select_way = 'd0;
-wire [WAYS-1:0]             next_way;
-reg  [WAYS-1:0]             valid_bits_r = 'd0;
-
-reg  [3:0]                  random_num = 4'hf;
-
-wire [CACHE_ADDR_WIDTH-1:0] tag_address;
-wire [TAG_WIDTH-1:0]        tag_wdata;
-wire                        tag_wenable;
-
-wire [CACHE_LINE_WIDTH-1:0] read_miss_wdata;
-wire [CACHE_LINE_WIDTH-1:0] write_hit_wdata;
-wire [CACHE_LINE_WIDTH-1:0] data_wdata;
-wire [CACHE_ADDR_WIDTH-1:0] data_address;
-wire [31:0]                 write_data_word;
-
-wire                        hit;
-wire                        read_miss;
-wire                        write_miss;
-wire                        write_hit;
-
-reg  [31:0]                 miss_address = 'd0;
-wire [CACHE_LINE_WIDTH-1:0] hit_rdata;
-
-wire                        write_stall;
-wire                        cache_busy_stall;
-wire                        read_stall;
-
-wire                        enable;
-wire [CACHE_ADDR_WIDTH-1:0] address;
-
-reg  [CACHE_LINE_WIDTH-1:0] wb_rdata_burst = 'd0;
-reg                         wb_read_buf_valid = 'd0;
-reg  [31:0]                 wb_read_buf_address = 'd0;
-reg  [31:0]                 wb_read_buf_data = 'd0;
-wire                        wb_read_buf_hit;
-
-wire                        exclusive_access;
-wire                        ex_read_hit;
-reg                         ex_read_hit_r = 'd0;
-reg  [WAYS-1:0]             ex_read_hit_way = 'd0;
-reg  [CACHE_ADDR_WIDTH-1:0] ex_read_address;
-wire                        ex_read_hit_clear;
-wire                        ex_read_cache_busy;
-
-genvar                      i;
-
-// ======================================
-// Address to use for cache access
-// ======================================
-// If currently stalled then the address for the next
-// cycle will be the same as it is in the current cycle
-//
-assign address = i_core_stall ? i_address    [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
-                                i_address_nxt[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ;
-
-// ======================================
-// Outputs
-// ======================================
-assign o_read_data      = wb_read_buf_hit                              ? wb_read_buf_data   :
-                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd0 ? hit_rdata [31:0]   :
-                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd1 ? hit_rdata [63:32]  :
-                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd2 ? hit_rdata [95:64]  :
-                                                                         hit_rdata [127:96] ;
-
-// Don't allow the cache to stall the wb i/f for an exclusive access
-// The cache needs a couple of cycles to flush a potential copy of the exclusive
-// address, but the wb can do the access in parallel. So there is no
-// stall in the state CS_EX_DELETE, even though the cache is out of action. 
-// This works fine as long as the wb is stalling the core
-assign o_stall          = read_stall || write_stall || cache_busy_stall || ex_read_cache_busy;
-
-assign o_wb_req        = (( read_miss || write_miss ) && c_state == CS_IDLE ) || 
-                          c_state == CS_WRITE_HIT1;
-
-     
-// ======================================
-// Cache State Machine
-// ======================================
-
-// Little State Machine to Flush Tag RAMS
-always @ ( posedge i_clk )
-    if ( i_cache_flush )
-        begin
-        c_state     <= C_INIT;
-        source_sel  <= 1'd1 << C_INIT;
-        init_count  <= 'd0;
-                end
-    else    
-        case ( c_state )
-            CS_INIT :
-                if ( init_count < CACHE_LINES [CACHE_ADDR_WIDTH:0] )
-                    begin
-                    init_count  <= init_count + 1'd1;
-                    source_sel  <= 1'd1 << C_INIT;
-                    end
-                else
-                    begin
-                    source_sel  <= 1'd1 << C_CORE;
-                    c_state     <= CS_TURN_AROUND;
-                    end 
-                       
-             CS_IDLE :
-                begin
-                source_sel  <= 1'd1 << C_CORE;
-                
-                if ( ex_read_hit || ex_read_hit_r )
-                    begin
-                    select_way  <= data_hit_way | ex_read_hit_way;
-                    c_state     <= CS_EX_DELETE;        
-                    source_sel  <= 1'd1 << C_INVA;
-                    end
-                else if ( read_miss ) 
-                    begin
-                    // wb read request asserted, wait for ack
-                    if ( !i_wb_stall )   
-                        c_state <= CS_FILL1; 
-                    end           
-                else if ( write_hit )
-                    c_state <= CS_WRITE_HIT1;        
-               end
-                   
-                   
-             CS_FILL1 :
-                begin
-                // wb read request asserted, wait for ack
-                if ( !i_wb_stall )
-                    c_state <= CS_FILL2;
-                end
-                
-                
-             CS_FILL2 :
-                // first read of burst of 4
-                // wb read request asserted, wait for ack
-                if ( !i_wb_stall )
-                    c_state <= CS_FILL3;
-
-
-             CS_FILL3 :
-                // second read of burst of 4
-                // wb read request asserted, wait for ack
-                if ( !i_wb_stall )
-                    c_state <= CS_FILL4;
-                
-                
-             CS_FILL4 :
-                // third read of burst of 4
-                // wb read request asserted, wait for ack
-                if ( !i_wb_stall ) 
-                    begin
-                    c_state     <= CS_FILL_COMPLETE;
-                    source_sel  <= 1'd1 << C_FILL;
-                
-                    // Pick a way to write the cache update into
-                    // Either pick one of the invalid caches, or if all are valid, then pick
-                    // one randomly
-                    
-                    select_way  <= next_way; 
-                    random_num  <= {random_num[2], random_num[1], random_num[0], 
-                                     random_num[3]^random_num[2]};
-                    end
-
-
-             // Write the read fetch data in this cycle
-             CS_FILL_COMPLETE : 
-                // fourth read of burst of 4
-                // wb read request asserted, wait for ack
-                if ( !i_wb_stall )
-                    begin
-                    // Back to normal cache operations, but
-                    // use physical address for first read as
-                    // address moved before the stall was asserted for the read_miss
-                    // However don't use it if its a non-cached address!
-                    source_sel  <= 1'd1 << C_CORE;              
-                    c_state     <= CS_TURN_AROUND;    
-                    end                                 
-                                                        
-
-             // Ignore the tag read data in this cycle   
-             // Wait 1 cycle to pre-read the cache and return to normal operation                 
-             CS_TURN_AROUND : 
-                begin
-                c_state     <= CS_IDLE;
-                end
-                
-
-             // Flush the entry matching an exclusive access         
-             CS_EX_DELETE:       
-                begin
-                                c_state    <= CS_TURN_AROUND;
-                source_sel <= 1'd1 << C_CORE;
-                end
-                
-                                 
-             CS_WRITE_HIT1:
-                begin
-                // wait for an ack on the wb bus to complete the write
-                if ( !i_wb_stall )           
-                    c_state     <= CS_IDLE;
-                    
-                end
-        endcase                       
-
-
-// ======================================
-// Capture WB Block Read - burst of 4 words
-// ======================================
-always @ ( posedge i_clk )
-    if ( !i_wb_stall )
-        wb_rdata_burst <= {i_wb_read_data, wb_rdata_burst[127:32]};
-
-
-// ======================================
-// WB Read Buffer
-// ======================================
-always @ ( posedge i_clk )
-    begin
-    if ( c_state == CS_FILL1 || c_state == CS_FILL2 || 
-         c_state == CS_FILL3 || c_state == CS_FILL4 )
-        begin
-        if ( !i_wb_stall )
-            begin
-            wb_read_buf_valid   <= 1'd1;
-            wb_read_buf_address <= i_wb_address;
-            wb_read_buf_data    <= i_wb_read_data;
-            end
-        end
-    else    
-        wb_read_buf_valid   <= 1'd0;
-    end
-        
-
-// ======================================
-// Miss Address
-// ======================================
-always @ ( posedge i_clk )
-    if ( o_wb_req )
-        miss_address <= i_address;
-        
-
-// ======================================
-// Remember Read-Modify-Write Hit
-// ======================================
-assign ex_read_hit_clear = c_state == CS_EX_DELETE;
-
-always @ ( posedge i_clk )
-    if ( ex_read_hit_clear )
-        begin
-        ex_read_hit_r   <= 1'd0;
-        ex_read_hit_way <= 'd0;
-        end
-    else if ( ex_read_hit )
-        begin
-        
-                
-        ex_read_hit_r   <= 1'd1;
-        ex_read_hit_way <= data_hit_way;
-        end
-    else if ( c_state == CS_FILL_COMPLETE && ex_read_hit_r )
-        ex_read_hit_way <= select_way;
-
-        
-always @ (posedge i_clk)
-    if ( ex_read_hit )
-        ex_read_address <= i_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB];
-
-
-assign tag_address      = source_sel[C_FILL] ? miss_address      [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
-                          source_sel[C_INVA] ? ex_read_address                                       :
-                          source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0]                      :
-                          source_sel[C_CORE] ? address                                               :
-                                               {CACHE_ADDR_WIDTH{1'd0}}                              ;
-
-
-assign data_address     = write_hit          ? i_address   [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
-                          source_sel[C_FILL] ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : 
-                          source_sel[C_CORE] ? address                                         :
-                                               {CACHE_ADDR_WIDTH{1'd0}}                        ;
-
-                                                          
-assign tag_wdata        = source_sel[C_FILL] ? {1'd1, miss_address[31:TAG_ADDR32_LSB]} :
-                                               {TAG_WIDTH{1'd0}}                       ;
-
-
-    // Data comes in off the WB bus in wrap4 with the missed data word first
-assign data_wdata       = write_hit && c_state == CS_IDLE ? write_hit_wdata : read_miss_wdata;
-
-assign read_miss_wdata  = miss_address[3:2] == 2'd0 ? wb_rdata_burst                              :
-                          miss_address[3:2] == 2'd1 ? { wb_rdata_burst[95:0], wb_rdata_burst[127:96] }:
-                          miss_address[3:2] == 2'd2 ? { wb_rdata_burst[63:0], wb_rdata_burst[127:64] }:
-                                                      { wb_rdata_burst[31:0], wb_rdata_burst[127:32] };
-
-
-assign write_hit_wdata  = i_address[3:2] == 2'd0 ? {hit_rdata[127:32], write_data_word                   } :
-                          i_address[3:2] == 2'd1 ? {hit_rdata[127:64], write_data_word, hit_rdata[31:0]  } :
-                          i_address[3:2] == 2'd2 ? {hit_rdata[127:96], write_data_word, hit_rdata[63:0]  } :
-                                                   {                   write_data_word, hit_rdata[95:0]  } ;
-
-// Use Byte Enables
-assign write_data_word  = i_byte_enable == 4'b0001 ? { o_read_data[31: 8], i_write_data[ 7: 0]                   } :
-                          i_byte_enable == 4'b0010 ? { o_read_data[31:16], i_write_data[15: 8], o_read_data[ 7:0]} :
-                          i_byte_enable == 4'b0100 ? { o_read_data[31:24], i_write_data[23:16], o_read_data[15:0]} :
-                          i_byte_enable == 4'b1000 ? {                     i_write_data[31:24], o_read_data[23:0]} :
-                          i_byte_enable == 4'b0011 ? { o_read_data[31:16], i_write_data[15: 0]                   } :
-                          i_byte_enable == 4'b1100 ? {                     i_write_data[31:16], o_read_data[15:0]} :
-                                                     i_write_data                                                  ;
-                          
-
-assign tag_wenable      = source_sel[C_INVA] ? 1'd1 :
-                          source_sel[C_FILL] ? 1'd1 :
-                          source_sel[C_INIT] ? 1'd1 :
-                          source_sel[C_CORE] ? 1'd0 :
-                                               1'd0 ;
-
-                          
-assign enable           = i_select && i_cache_enable;
-
-assign exclusive_access = i_exclusive && i_cache_enable;
-
-
-                          // the wb read buffer returns data directly from the wb bus to the
-                          // core during a read miss operation
-assign wb_read_buf_hit  = enable && wb_read_buf_address == i_address && wb_read_buf_valid;
-
-assign hit              = |data_hit_way;
-
-assign write_hit        = enable &&  i_write_enable && hit;
-                                                           
-assign write_miss       = enable &&  i_write_enable && !hit && c_state != CS_WRITE_HIT1;
-                                                           
-assign read_miss        = enable && !i_write_enable && !(hit || wb_read_buf_hit);
-
-                          // Exclusive read hit
-assign ex_read_hit      = exclusive_access && !i_write_enable && (hit || wb_read_buf_hit);
-
-                          // Added to fix rare swap bug which occurs when the cache starts
-                          // a fill just as the swap instruction starts to execute. The cache
-                          // fails to check for a read hit on the swap read cycle.
-                          // This signal stalls the core in that case until after the
-                          // fill has completed.
-assign ex_read_cache_busy = exclusive_access && !i_write_enable && c_state != CS_IDLE;
-
-                          // Need to stall for a write miss to wait for the current wb 
-                          // read miss access to complete. Also for a write hit, need 
-                          // to stall for 1 cycle while the data cache is being written to
-assign write_stall      = ( write_hit  && c_state != CS_WRITE_HIT1 ) ||
-                          ( write_miss && ( c_state != CS_IDLE ) )   ||
-                           i_wb_stall                                ;
-
-assign read_stall       = read_miss;
-
-                          // Core may or may not be trying to access cache memory during
-                          // this phase of the read fetch. It could be doing e.g. a wb access
-assign cache_busy_stall = ((c_state == CS_TURN_AROUND || c_state == CS_FILL1) && enable) ||
-                           c_state == CS_INIT;
-
-
-// ======================================
-// Instantiate RAMS
-// ======================================
-
-generate
-    for ( i=0; i<WAYS;i=i+1 ) begin : rams
-
-        // Tag RAMs 
-        
-        
-                generic_sram_line_en 
-        
-            #(
-            .DATA_WIDTH                 ( TAG_WIDTH             ),
-            .INITIALIZE_TO_ZERO         ( 1 ),
-            .ADDRESS_WIDTH              ( CACHE_ADDR_WIDTH      ))
-        u_tag (
-            .i_clk                      ( i_clk                 ),
-            .i_write_data               ( tag_wdata             ),
-            .i_write_enable             ( tag_wenable_way[i]    ),
-            .i_address                  ( tag_address           ),
-
-            .o_read_data                ( tag_rdata_way[i]      )
-            );
-            
-        // Data RAMs 
-        
-        
-                generic_sram_byte_en
-        
-            #(
-            .DATA_WIDTH    ( CACHE_LINE_WIDTH) ,
-            .ADDRESS_WIDTH ( CACHE_ADDR_WIDTH) )
-        u_data (
-            .i_clk                      ( i_clk                         ),
-            .i_write_data               ( data_wdata                    ),
-            .i_write_enable             ( data_wenable_way[i]           ),
-            .i_address                  ( data_address                  ),
-            .i_byte_enable              ( {CACHE_LINE_WIDTH/8{1'd1}}    ),
-            .o_read_data                ( data_rdata_way[i]             )
-            );                                                     
-
-
-        // Per tag-ram write-enable
-        assign tag_wenable_way[i]  = tag_wenable && ( select_way[i] || source_sel[C_INIT] );
-
-        // Per data-ram write-enable
-        assign data_wenable_way[i] = (source_sel[C_FILL] && select_way[i]) || 
-                                     (write_hit && data_hit_way[i] && c_state == CS_IDLE);
-        // Per data-ram hit flag
-        assign data_hit_way[i]     = tag_rdata_way[i][TAG_WIDTH-1] &&                                                  
-                                     tag_rdata_way[i][TAG_ADDR_WIDTH-1:0] == i_address[31:TAG_ADDR32_LSB] &&  
-                                     c_state == CS_IDLE;                                                               
-    end                                                         
-endgenerate
-
-
-// ======================================
-// Register Valid Bits
-// ======================================
-generate
-if ( WAYS == 2 ) begin : valid_bits_2ways
-
-    always @ ( posedge i_clk )
-        if ( c_state == CS_IDLE )
-            valid_bits_r <= {tag_rdata_way[1][TAG_WIDTH-1], 
-                             tag_rdata_way[0][TAG_WIDTH-1]};
-                           
-end
-else if ( WAYS == 3 ) begin : valid_bits_3ways
-
-    always @ ( posedge i_clk )
-        if ( c_state == CS_IDLE )
-            valid_bits_r <= {tag_rdata_way[2][TAG_WIDTH-1], 
-                             tag_rdata_way[1][TAG_WIDTH-1], 
-                             tag_rdata_way[0][TAG_WIDTH-1]};
-                           
-end
-else if ( WAYS == 4 ) begin : valid_bits_4ways
-
-    always @ ( posedge i_clk )
-        if ( c_state == CS_IDLE )
-            valid_bits_r <= {tag_rdata_way[3][TAG_WIDTH-1], 
-                             tag_rdata_way[2][TAG_WIDTH-1], 
-                             tag_rdata_way[1][TAG_WIDTH-1], 
-                             tag_rdata_way[0][TAG_WIDTH-1]};
-                           
-end
-else begin : valid_bits_8ways
-
-    always @ ( posedge i_clk )
-        if ( c_state == CS_IDLE )
-            valid_bits_r <= {tag_rdata_way[7][TAG_WIDTH-1], 
-                             tag_rdata_way[6][TAG_WIDTH-1], 
-                             tag_rdata_way[5][TAG_WIDTH-1], 
-                             tag_rdata_way[4][TAG_WIDTH-1], 
-                             tag_rdata_way[3][TAG_WIDTH-1], 
-                             tag_rdata_way[2][TAG_WIDTH-1], 
-                             tag_rdata_way[1][TAG_WIDTH-1], 
-                             tag_rdata_way[0][TAG_WIDTH-1]};
-                           
-end
-endgenerate
-
-
-// ======================================
-// Select read hit data
-// ======================================
-generate
-if ( WAYS == 2 ) begin : read_data_2ways
-
-    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
-                          data_hit_way[1] ? data_rdata_way[1] :
-                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
-                           
-end
-else if ( WAYS == 3 ) begin : read_data_3ways
-
-    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
-                          data_hit_way[1] ? data_rdata_way[1] :
-                          data_hit_way[2] ? data_rdata_way[2] :
-                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
-                           
-end
-else if ( WAYS == 4 ) begin : read_data_4ways
-
-    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
-                          data_hit_way[1] ? data_rdata_way[1] :
-                          data_hit_way[2] ? data_rdata_way[2] :
-                          data_hit_way[3] ? data_rdata_way[3] :
-                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
-                           
-end
-else begin : read_data_8ways
-
-    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
-                          data_hit_way[1] ? data_rdata_way[1] :
-                          data_hit_way[2] ? data_rdata_way[2] :
-                          data_hit_way[3] ? data_rdata_way[3] :
-                          data_hit_way[4] ? data_rdata_way[4] :
-                          data_hit_way[5] ? data_rdata_way[5] :
-                          data_hit_way[6] ? data_rdata_way[6] :
-                          data_hit_way[7] ? data_rdata_way[7] :
-                                     {CACHE_LINE_WIDTH{1'd1}} ;  // all 1's for debug
-                           
-end
-endgenerate
-
-
-// ======================================
-// Function to select the way to use
-// for fills
-// ======================================
-generate
-if ( WAYS == 2 ) begin : pick_way_2ways
-
-    assign next_way = pick_way ( valid_bits_r, random_num );
-
-    function [WAYS-1:0] pick_way;
-    input [WAYS-1:0] valid_bits;
-    input [3:0]      random_num;
-    begin
-        if (      valid_bits[0] == 1'd0 )
-            // way 0 not occupied so use it
-            pick_way     = 2'b01;
-        else if ( valid_bits[1] == 1'd0 )
-            // way 1 not occupied so use it
-            pick_way     = 2'b10;
-        else
-            begin
-            // All ways occupied so pick one randomly
-            case (random_num[3:1])
-                3'd0, 3'd3,
-                3'd5, 3'd6: pick_way = 2'b10;
-                default:    pick_way = 2'b01;
-            endcase
-            end
-    end
-    endfunction
-                                                      
-end
-else if ( WAYS == 3 ) begin : pick_way_3ways
-
-    assign next_way = pick_way ( valid_bits_r, random_num );
-
-    function [WAYS-1:0] pick_way;
-    input [WAYS-1:0] valid_bits;
-    input [3:0]      random_num;
-    begin
-        if (      valid_bits[0] == 1'd0 )
-            // way 0 not occupied so use it
-            pick_way     = 3'b001;
-        else if ( valid_bits[1] == 1'd0 )
-            // way 1 not occupied so use it
-            pick_way     = 3'b010;
-        else if ( valid_bits[2] == 1'd0 )
-            // way 2 not occupied so use it
-            pick_way     = 3'b100;
-        else
-            begin
-            // All ways occupied so pick one randomly
-            case (random_num[3:1])
-                3'd0, 3'd1, 3'd2: pick_way = 3'b010;
-                3'd2, 3'd3, 3'd4: pick_way = 3'b100;
-                default:          pick_way = 3'b001;
-            endcase
-            end
-    end
-    endfunction
-                           
-end
-else if ( WAYS == 4 ) begin : pick_way_4ways
-
-    assign next_way = pick_way ( valid_bits_r, random_num );
-
-    function [WAYS-1:0] pick_way;
-    input [WAYS-1:0] valid_bits;
-    input [3:0]      random_num;
-    begin
-        if (      valid_bits[0] == 1'd0 )
-            // way 0 not occupied so use it
-            pick_way     = 4'b0001;
-        else if ( valid_bits[1] == 1'd0 )
-            // way 1 not occupied so use it
-            pick_way     = 4'b0010;
-        else if ( valid_bits[2] == 1'd0 )
-            // way 2 not occupied so use it
-            pick_way     = 4'b0100;
-        else if ( valid_bits[3] == 1'd0 )
-            // way 3 not occupied so use it
-            pick_way     = 4'b1000;
-        else
-            begin
-            // All ways occupied so pick one randomly
-            case (random_num[3:1])
-                3'd0, 3'd1: pick_way = 4'b0100;
-                3'd2, 3'd3: pick_way = 4'b1000;
-                3'd4, 3'd5: pick_way = 4'b0001;
-                default:    pick_way = 4'b0010;
-            endcase
-            end
-    end
-    endfunction
-                           
-end
-else begin : pick_way_8ways
-
-    assign next_way = pick_way ( valid_bits_r, random_num );
-
-    function [WAYS-1:0] pick_way;
-    input [WAYS-1:0] valid_bits;
-    input [3:0]      random_num;
-    begin
-        if (      valid_bits[0] == 1'd0 )
-            // way 0 not occupied so use it
-            pick_way     = 8'b00000001;
-        else if ( valid_bits[1] == 1'd0 )
-            // way 1 not occupied so use it
-            pick_way     = 8'b00000010;
-        else if ( valid_bits[2] == 1'd0 )
-            // way 2 not occupied so use it
-            pick_way     = 8'b00000100;
-        else if ( valid_bits[3] == 1'd0 )
-            // way 3 not occupied so use it
-            pick_way     = 8'b00001000;
-        else if ( valid_bits[4] == 1'd0 )
-            // way 3 not occupied so use it
-            pick_way     = 8'b00010000;
-        else if ( valid_bits[5] == 1'd0 )
-            // way 3 not occupied so use it
-            pick_way     = 8'b00100000;
-        else if ( valid_bits[6] == 1'd0 )
-            // way 3 not occupied so use it
-            pick_way     = 8'b01000000;
-        else if ( valid_bits[7] == 1'd0 )
-            // way 3 not occupied so use it
-            pick_way     = 8'b10000000;
-        else
-            begin
-            // All ways occupied so pick one randomly
-            case (random_num[3:1])
-                3'd0:       pick_way = 8'b00010000;
-                3'd1:       pick_way = 8'b00100000;
-                3'd2:       pick_way = 8'b01000000;
-                3'd3:       pick_way = 8'b10000000;
-                3'd4:       pick_way = 8'b00000001;
-                3'd5:       pick_way = 8'b00000010;
-                3'd6:       pick_way = 8'b00000100;
-                default:    pick_way = 8'b00001000;
-            endcase
-            end
-    end
-    endfunction
-                           
-end
-endgenerate
-
-
-// ========================================================
-// Debug WB bus - not synthesizable
-// ========================================================
-//synopsys translate_off
-wire    [(6*8)-1:0]     xSOURCE_SEL;
-wire    [(20*8)-1:0]    xC_STATE;
-
-assign xSOURCE_SEL = source_sel[C_CORE]            ? "C_CORE"           :
-                     source_sel[C_INIT]            ? "C_INIT"           :
-                     source_sel[C_FILL]            ? "C_FILL"           :
-                     source_sel[C_INVA]            ? "C_INVA"           :
-                                                     "UNKNON"           ;
- 
-assign xC_STATE    = c_state == CS_INIT            ? "CS_INIT"          :
-                     c_state == CS_IDLE            ? "CS_IDLE"          :
-                     c_state == CS_FILL1           ? "CS_FILL1"         :
-                     c_state == CS_FILL2           ? "CS_FILL2"         :
-                     c_state == CS_FILL3           ? "CS_FILL3"         :
-                     c_state == CS_FILL4           ? "CS_FILL4"         :
-                     c_state == CS_FILL_COMPLETE   ? "CS_FILL_COMPLETE" :
-                     c_state == CS_EX_DELETE       ? "CS_EX_DELETE"     :
-                     c_state == CS_TURN_AROUND     ? "CS_TURN_AROUND"   :
-                     c_state == CS_WRITE_HIT1      ? "CS_WRITE_HIT1"    :
-                                                     "UNKNOWN"          ;
-
-
-generate
-if ( WAYS == 2 ) begin : check_hit_2ways
-
-    always @( posedge i_clk )
-        if ( (data_hit_way[0] + data_hit_way[1] ) > 4'd1 )
-            begin
-            $display("FATAL ERROR"); $stop;
-            $display("Hit in more than one cache ways!");                                                  
-            end
-                                                      
-end
-else if ( WAYS == 3 ) begin : check_hit_3ways
-
-    always @( posedge i_clk )
-        if ( (data_hit_way[0] + data_hit_way[1] + data_hit_way[2] ) > 4'd1 )
-            begin
-            $display("FATAL ERROR"); $stop;
-            $display("Hit in more than one cache ways!");                                                  
-            end
-                           
-end
-else if ( WAYS == 4 ) begin : check_hit_4ways
-
-    always @( posedge i_clk )
-        if ( (data_hit_way[0] + data_hit_way[1] + 
-              data_hit_way[2] + data_hit_way[3] ) > 4'd1 )
-            begin
-            $display("FATAL ERROR"); $stop;
-            $display("Hit in more than one cache ways!");                                                  
-            end
-                           
-end
-else if ( WAYS == 8 )  begin : check_hit_8ways
-
-    always @( posedge i_clk )
-        if ( (data_hit_way[0] + data_hit_way[1] + 
-              data_hit_way[2] + data_hit_way[3] +
-              data_hit_way[4] + data_hit_way[5] +
-              data_hit_way[6] + data_hit_way[7] ) > 4'd1 )
-            begin
-            $display("FATAL ERROR"); $stop;
-            $display("Hit in more than one cache ways!");                                                  
-            end
-                           
-end
-else begin : check_hit_nways
-
-    initial
-        begin
-        $display("FATAL ERROR"); $stop;
-        $display("Unsupported number of ways %0d", WAYS);
-        $display("Set A23_CACHE_WAYS in a23_config_defines.v to either 2,3,4 or 8");
-        end
-
-end
-endgenerate
-    
-//synopsys translate_on
-    
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_config_defines.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_config_defines.v
deleted file mode 100644
index 0888dde..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_config_defines.v
+++ /dev/null
@@ -1,74 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Amber Configuration and Debug for the AMber 2 Core          //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains a set of defines used to configure and debug       //
-//  the Amber core                                              //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Cache Ways
-// Changing this parameter is the recommended
-// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported.
-//   2 ways -> 8KB  cache
-//   3 ways -> 12KB cache
-//   4 ways -> 16KB cache
-//   8 ways -> 32KB cache
-
-// Use ram-based register bank implementation
-// `define A23_RAM_REGISTER_BANK
-
-// --------------------------------------------------------------------
-// Debug switches 
-// --------------------------------------------------------------------
-
-// Enable the decompiler. The default output file is amber.dis
-//`define A23_DECOMPILE
-
-// Co-processor 15 debug. Registers in here control the cache
-//`define A23_COPRO15_DEBUG
-
-// Cache debug
-//`define A23_CACHE_DEBUG
-
-// --------------------------------------------------------------------
-
-
-// --------------------------------------------------------------------
-// File Names
-// --------------------------------------------------------------------
-    
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_coprocessor.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_coprocessor.v
deleted file mode 100644
index 1e839c2..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_coprocessor.v
+++ /dev/null
@@ -1,156 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Co-processor module for Amber 2 Core                        //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Co_processor 15 registers and control signals               //                                                           //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module a23_coprocessor
-(
-input                       i_clk,
-input                       i_fetch_stall,    // stall all stages of the cpu at the same time
-input       [2:0]           i_copro_opcode1,
-input       [2:0]           i_copro_opcode2,
-input       [3:0]           i_copro_crn,      // Register Number 
-input       [3:0]           i_copro_crm,
-input       [3:0]           i_copro_num,
-input       [1:0]           i_copro_operation,
-input       [31:0]          i_copro_write_data,
-
-input                       i_fault,          // high to latch the fault address and status
-input       [7:0]           i_fault_status,
-input       [31:0]          i_fault_address,  // the address that caused the fault
-
-output reg  [31:0]          o_copro_read_data,
-output                      o_cache_enable,
-output                      o_cache_flush,
-output      [31:0]          o_cacheable_area 
-);
-
-// Bit 0 - Cache on(1)/off
-// Bit 1 - Shared (1) or seperate User/Supervisor address space
-// Bit 2 - address monitor mode(1)
-reg [2:0]  cache_control = 3'b000;
-
-// Bit 0 - 2MB memory from 0 to 0x01fffff cacheable(1)/not cachable
-// Bit 1 - next 2MB region etc.
-reg [31:0] cacheable_area = 32'h0;
-
-// Marks memory regions as read only so writes are ignored by the cache
-// Bit 0 - 2MB memory from 0 to 0x01fffff updateable(1)/not updateable
-// Bit 1 - next 2MB region etc.
-reg [31:0] updateable_area = 32'h0;
-
-// Accesses to a region with a flag set in this register cause the
-// cache to flush
-// Bit 0 - 2MB memory from 0 to 0x01fffff
-// Bit 1 - next 2MB region etc.
-reg [31:0] disruptive_area = 32'h0;
-
-
-reg [7:0]  fault_status  = 'd0;
-reg [31:0] fault_address = 'd0;  // the address that caused the fault
-
-wire       copro15_reg1_write;
-
-
-// ---------------------------
-// Outputs
-// ---------------------------
-assign o_cache_enable   = cache_control[0];
-assign o_cache_flush    = copro15_reg1_write;
-assign o_cacheable_area = cacheable_area;
-              
-// ---------------------------
-// Capture an access fault address and status
-// ---------------------------
-always @ ( posedge i_clk )
-    if ( !i_fetch_stall )
-        begin
-        if ( i_fault )
-            begin
-            
-                        fault_status    <= i_fault_status;
-            fault_address   <= i_fault_address;
-            end
-        end
-
-
-// ---------------------------
-// Register Writes
-// ---------------------------
-always @ ( posedge i_clk )
-    if ( !i_fetch_stall )         
-        begin
-        if ( i_copro_operation == 2'd2 )
-            case ( i_copro_crn )
-                4'd2: cache_control   <= i_copro_write_data[2:0];
-                4'd3: cacheable_area  <= i_copro_write_data[31:0];
-                4'd4: updateable_area <= i_copro_write_data[31:0];
-                4'd5: disruptive_area <= i_copro_write_data[31:0];
-            endcase
-        end
-
-// Flush the cache
-assign copro15_reg1_write = !i_fetch_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1;
-
-
-// ---------------------------
-// Register Reads   
-// ---------------------------
-always @ ( posedge i_clk )        
-    if ( !i_fetch_stall )
-        case ( i_copro_crn )
-            // ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision
-            4'd0:    o_copro_read_data <= 32'h4156_0300;
-            4'd2:    o_copro_read_data <= {29'd0, cache_control}; 
-            4'd3:    o_copro_read_data <= cacheable_area; 
-            4'd4:    o_copro_read_data <= updateable_area; 
-            4'd5:    o_copro_read_data <= disruptive_area; 
-            4'd6:    o_copro_read_data <= {24'd0, fault_status };
-            4'd7:    o_copro_read_data <= fault_address;
-            default: o_copro_read_data <= 32'd0;
-        endcase
-
-
-
-// ========================================================
-// Debug code - not synthesizable
-// ========================================================
-
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_core.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_core.v
deleted file mode 100644
index 021e0d8..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_core.v
+++ /dev/null
@@ -1,358 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Amber 2 Core top-Level module                               //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Instantiates the core consisting of fetch, instruction      //
-//  decode, execute, and co-processor.                          //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module a23_core
-(
-input                       i_clk,
-
-input                       i_irq,              // Interrupt request, active high
-input                       i_firq,             // Fast Interrupt request, active high
-
-input                       i_system_rdy,       // Amber is stalled when this is low
-
-// Wishbone Master I/F
-output      [31:0]          o_wb_adr,
-output      [3:0]           o_wb_sel,
-output                      o_wb_we,
-input       [31:0]          i_wb_dat,
-output      [31:0]          o_wb_dat,
-output                      o_wb_cyc,
-output                      o_wb_stb,
-input                       i_wb_ack,
-input                       i_wb_err,
-
-// Global Reset
-input                       globrst
-);
-
-wire      [31:0]          execute_address;
-wire                      execute_address_valid;
-wire      [31:0]          execute_address_nxt;  // un-registered version of execute_address to the cache rams
-wire      [31:0]          write_data;
-wire                      write_enable;
-wire      [31:0]          read_data;
-wire                      priviledged;
-wire                      exclusive_exec;
-wire                      data_access_exec;
-wire      [3:0]           byte_enable;
-wire                      data_access;          // high for data petch, low for instruction fetch
-wire                      exclusive;            // swap access
-wire                      cache_enable;         // Enabel the cache
-wire                      cache_flush;          // Flush the cache
-wire      [31:0]          cacheable_area;
-
-wire                      fetch_stall;          // when this is asserted all registers in all 3 pipeline 
-                                                // stages are held
-                                                // at their current values
-wire     [1:0]            status_bits_mode;               
-wire                      status_bits_irq_mask;           
-wire                      status_bits_firq_mask;           
-wire                      status_bits_flags_wen;          
-wire                      status_bits_mode_wen;           
-wire                      status_bits_irq_mask_wen;       
-wire                      status_bits_firq_mask_wen;       
-wire     [31:0]           execute_status_bits;
-                 
-wire     [31:0]           imm32;                   
-wire     [4:0]            imm_shift_amount; 
-wire                      shift_imm_zero;      
-wire     [3:0]            condition;               
-wire     [31:0]           read_data_s2;            
-wire     [4:0]            read_data_alignment;     
-
-wire     [3:0]            rm_sel;                  
-wire     [3:0]            rds_sel;                 
-wire     [3:0]            rn_sel;                  
-wire     [3:0]            rm_sel_nxt;
-wire     [3:0]            rds_sel_nxt;
-wire     [3:0]            rn_sel_nxt;
-wire     [1:0]            barrel_shift_amount_sel; 
-wire     [1:0]            barrel_shift_data_sel;   
-wire     [1:0]            barrel_shift_function;   
-wire     [8:0]            alu_function;            
-wire     [1:0]            multiply_function;       
-wire     [2:0]            interrupt_vector_sel;    
-wire     [3:0]            address_sel;             
-wire     [1:0]            pc_sel;                  
-wire     [1:0]            byte_enable_sel;         
-wire     [2:0]            status_bits_sel;                
-wire     [2:0]            reg_write_sel;           
-wire                      user_mode_regs_load;     
-wire                      user_mode_regs_store_nxt;    
-wire                      firq_not_user_mode;
-
-wire                      write_data_wen;          
-wire                      copro_write_data_wen;          
-wire                      base_address_wen;        
-wire                      pc_wen;                  
-wire     [14:0]           reg_bank_wen;            
-wire     [3:0]            reg_bank_wsel;            
-
-wire     [2:0]            copro_opcode1;
-wire     [2:0]            copro_opcode2;
-wire     [3:0]            copro_crn;    
-wire     [3:0]            copro_crm;
-wire     [3:0]            copro_num;
-wire     [1:0]            copro_operation;
-wire     [31:0]           copro_read_data;
-wire     [31:0]           copro_write_data;
-wire                      multiply_done;
-
-wire                      decode_fault;
-wire                      iabt_trigger;
-wire                      dabt_trigger;
-
-wire     [7:0]            decode_fault_status;
-wire     [7:0]            iabt_fault_status;
-wire     [7:0]            dabt_fault_status;
-
-wire     [31:0]           decode_fault_address;
-wire     [31:0]           iabt_fault_address;
-wire     [31:0]           dabt_fault_address;
-
-wire                      adex;
-
-
-// data abort has priority
-assign decode_fault_status  = dabt_trigger ? dabt_fault_status  : iabt_fault_status;
-assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
-assign decode_fault         = dabt_trigger | iabt_trigger;
-
-
-a23_fetch u_fetch (
-    .i_clk                              ( i_clk                             ),
-
-    .i_address                          ( {execute_address[31:2], 2'd0}     ),
-    .i_address_valid                    ( execute_address_valid             ), 
-    .i_address_nxt                      ( execute_address_nxt               ),
-    .i_write_data                       ( write_data                        ),
-    .i_write_enable                     ( write_enable                      ),
-    .o_read_data                        ( read_data                         ),
-    .i_priviledged                      ( priviledged                       ),
-    .i_byte_enable                      ( byte_enable                       ),
-    .i_data_access                      ( data_access                       ),      
-    .i_exclusive                        ( exclusive                         ),
-    .i_cache_enable                     ( cache_enable                      ),     
-    .i_cache_flush                      ( cache_flush                       ), 
-    .i_cacheable_area                   ( cacheable_area                    ),
-
-    .i_system_rdy                       ( i_system_rdy                      ),
-    .o_fetch_stall                      ( fetch_stall                       ),
-    
-    .o_wb_adr                           ( o_wb_adr                          ),
-    .o_wb_sel                           ( o_wb_sel                          ),
-    .o_wb_we                            ( o_wb_we                           ),
-    .i_wb_dat                           ( i_wb_dat                          ),
-    .o_wb_dat                           ( o_wb_dat                          ),
-    .o_wb_cyc                           ( o_wb_cyc                          ),
-    .o_wb_stb                           ( o_wb_stb                          ),
-    .i_wb_ack                           ( i_wb_ack                          ),
-    .i_wb_err                           ( i_wb_err                          )
-);
-
-
-a23_decode u_decode (
-    .i_clk                              ( i_clk                             ),
-    
-    // Instruction fetch or data read signals
-    .i_read_data                        ( read_data                         ),                                          
-    .i_execute_address                  ( execute_address                   ),
-    .i_adex                             ( adex                              ),
-    .i_iabt                             ( 1'd0 ),
-    .i_dabt                             ( 1'd0 ),
-    .i_abt_status                       ( 8'd0 ),                                          
-    
-    .o_read_data                        ( read_data_s2                      ),                                          
-    .o_read_data_alignment              ( read_data_alignment               ),                                          
-    
-    .i_irq                              ( i_irq                             ),                                          
-    .i_firq                             ( i_firq                            ),                                          
-    .i_fetch_stall                      ( fetch_stall                       ),                                          
-    .i_execute_status_bits              ( execute_status_bits               ),                                          
-    .i_multiply_done                    ( multiply_done                     ),                                          
-    
-    .o_status_bits_mode                 ( status_bits_mode                  ),
-    .o_status_bits_irq_mask             ( status_bits_irq_mask              ),  
-    .o_status_bits_firq_mask            ( status_bits_firq_mask             ),  
-    .o_imm32                            ( imm32                             ),
-    .o_imm_shift_amount                 ( imm_shift_amount                  ),
-    .o_shift_imm_zero                   ( shift_imm_zero                    ),
-    .o_condition                        ( condition                         ),
-    .o_exclusive_exec                   ( exclusive_exec                    ), 
-    .o_data_access_exec                 ( data_access_exec                  ),
-    .o_rm_sel                           ( rm_sel                            ),
-    .o_rds_sel                          ( rds_sel                           ),
-    .o_rn_sel                           ( rn_sel                            ),
-    .o_rm_sel_nxt                       ( rm_sel_nxt                        ),
-    .o_rds_sel_nxt                      ( rds_sel_nxt                       ),
-    .o_rn_sel_nxt                       ( rn_sel_nxt                        ),
-    .o_barrel_shift_amount_sel          ( barrel_shift_amount_sel           ),
-    .o_barrel_shift_data_sel            ( barrel_shift_data_sel             ),
-    .o_barrel_shift_function            ( barrel_shift_function             ),
-    .o_alu_function                     ( alu_function                      ),
-    .o_multiply_function                ( multiply_function                 ),
-    .o_interrupt_vector_sel             ( interrupt_vector_sel              ),
-    .o_address_sel                      ( address_sel                       ),
-    .o_pc_sel                           ( pc_sel                            ),
-    .o_byte_enable_sel                  ( byte_enable_sel                   ),
-    .o_status_bits_sel                  ( status_bits_sel                   ),
-    .o_reg_write_sel                    ( reg_write_sel                     ),
-    .o_user_mode_regs_load              ( user_mode_regs_load               ),
-    .o_user_mode_regs_store_nxt         ( user_mode_regs_store_nxt          ),
-    .o_firq_not_user_mode               ( firq_not_user_mode                ),
-    .o_write_data_wen                   ( write_data_wen                    ),
-    .o_base_address_wen                 ( base_address_wen                  ),
-    .o_pc_wen                           ( pc_wen                            ),
-    .o_reg_bank_wen                     ( reg_bank_wen                      ),
-    .o_reg_bank_wsel                    ( reg_bank_wsel                     ),
-    .o_status_bits_flags_wen            ( status_bits_flags_wen             ),
-    .o_status_bits_mode_wen             ( status_bits_mode_wen              ),
-    .o_status_bits_irq_mask_wen         ( status_bits_irq_mask_wen          ),
-    .o_status_bits_firq_mask_wen        ( status_bits_firq_mask_wen         ),
-    
-    .o_copro_opcode1                    ( copro_opcode1                     ),                                        
-    .o_copro_opcode2                    ( copro_opcode2                     ),                                        
-    .o_copro_crn                        ( copro_crn                         ),                                        
-    .o_copro_crm                        ( copro_crm                         ),                                        
-    .o_copro_num                        ( copro_num                         ),                                        
-    .o_copro_operation                  ( copro_operation                   ), 
-    .o_copro_write_data_wen             ( copro_write_data_wen              ),                                        
-    
-    .o_iabt_trigger                     ( iabt_trigger                      ),
-    .o_iabt_address                     ( iabt_fault_address                ),
-    .o_iabt_status                      ( iabt_fault_status                 ),
-    .o_dabt_trigger                     ( dabt_trigger                      ),
-    .o_dabt_address                     ( dabt_fault_address                ),
-    .o_dabt_status                      ( dabt_fault_status                 ) 
-);
-
-
-a23_execute u_execute (
-    .i_clk                              ( i_clk                             ),
-    
-    .i_read_data                        ( read_data_s2                      ),
-    .i_read_data_alignment              ( read_data_alignment               ), 
-    .i_copro_read_data                  ( copro_read_data                   ),
-    
-    .o_write_data                       ( write_data                        ),
-    .o_copro_write_data                 ( copro_write_data                  ),
-    .o_address                          ( execute_address                   ),
-    .o_address_valid                    ( execute_address_valid             ),
-    .o_address_nxt                      ( execute_address_nxt               ),
-    .o_adex                             ( adex                              ),
-
-    .o_byte_enable                      ( byte_enable                       ),
-    .o_data_access                      ( data_access                       ),
-    .o_write_enable                     ( write_enable                      ),
-    .o_exclusive                        ( exclusive                         ),
-    .o_priviledged                      ( priviledged                       ),
-    .o_status_bits                      ( execute_status_bits               ),
-    .o_multiply_done                    ( multiply_done                     ),
-
-    .i_fetch_stall                      ( fetch_stall                       ),   
-    .i_status_bits_mode                 ( status_bits_mode                  ),   
-    .i_status_bits_irq_mask             ( status_bits_irq_mask              ),   
-    .i_status_bits_firq_mask            ( status_bits_firq_mask             ),   
-    .i_imm32                            ( imm32                             ),   
-    .i_imm_shift_amount                 ( imm_shift_amount                  ),   
-    .i_shift_imm_zero                   ( shift_imm_zero                    ),   
-    .i_condition                        ( condition                         ),   
-    .i_exclusive_exec                   ( exclusive_exec                    ),   
-    .i_data_access_exec                 ( data_access_exec                  ),   
-    .i_rm_sel                           ( rm_sel                            ),   
-    .i_rds_sel                          ( rds_sel                           ),   
-    .i_rn_sel                           ( rn_sel                            ),   
-    .i_rm_sel_nxt                       ( rm_sel_nxt                        ),
-    .i_rds_sel_nxt                      ( rds_sel_nxt                       ),
-    .i_rn_sel_nxt                       ( rn_sel_nxt                        ),
-    .i_barrel_shift_amount_sel          ( barrel_shift_amount_sel           ),   
-    .i_barrel_shift_data_sel            ( barrel_shift_data_sel             ),   
-    .i_barrel_shift_function            ( barrel_shift_function             ),   
-    .i_alu_function                     ( alu_function                      ),   
-    .i_multiply_function                ( multiply_function                 ),   
-    .i_interrupt_vector_sel             ( interrupt_vector_sel              ),   
-    .i_address_sel                      ( address_sel                       ),   
-    .i_pc_sel                           ( pc_sel                            ),   
-    .i_byte_enable_sel                  ( byte_enable_sel                   ),   
-    .i_status_bits_sel                  ( status_bits_sel                   ),   
-    .i_reg_write_sel                    ( reg_write_sel                     ),   
-    .i_user_mode_regs_load              ( user_mode_regs_load               ),   
-    .i_user_mode_regs_store_nxt         ( user_mode_regs_store_nxt          ),   
-    .i_firq_not_user_mode               ( firq_not_user_mode                ),   
-    .i_write_data_wen                   ( write_data_wen                    ),   
-    .i_base_address_wen                 ( base_address_wen                  ),   
-    .i_pc_wen                           ( pc_wen                            ),   
-    .i_reg_bank_wen                     ( reg_bank_wen                      ),   
-    .i_reg_bank_wsel                    ( reg_bank_wsel                     ),
-    .i_status_bits_flags_wen            ( status_bits_flags_wen             ),   
-    .i_status_bits_mode_wen             ( status_bits_mode_wen              ),   
-    .i_status_bits_irq_mask_wen         ( status_bits_irq_mask_wen          ),   
-    .i_status_bits_firq_mask_wen        ( status_bits_firq_mask_wen         ),   
-    .i_copro_write_data_wen             ( copro_write_data_wen              )
-);
-
-
-a23_coprocessor u_coprocessor (
-    .i_clk                              ( i_clk                             ),
-    
-    .i_fetch_stall                      ( fetch_stall                       ),
-    .i_copro_opcode1                    ( copro_opcode1                     ),
-    .i_copro_opcode2                    ( copro_opcode2                     ),
-    .i_copro_crn                        ( copro_crn                         ),    
-    .i_copro_crm                        ( copro_crm                         ),
-    .i_copro_num                        ( copro_num                         ),
-    .i_copro_operation                  ( copro_operation                   ),
-    .i_copro_write_data                 ( copro_write_data                  ),
-    
-    .i_fault                            ( decode_fault                      ),
-    .i_fault_status                     ( decode_fault_status               ),
-    .i_fault_address                    ( decode_fault_address              ), 
-    
-    .o_copro_read_data                  ( copro_read_data                   ),
-    .o_cache_enable                     ( cache_enable                      ),
-    .o_cache_flush                      ( cache_flush                       ),
-    .o_cacheable_area                   ( cacheable_area                    )
-);
-
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_decode.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_decode.v
deleted file mode 100644
index 35f6d8e..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_decode.v
+++ /dev/null
@@ -1,1981 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Decode stage of Amber 2 Core                                //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  This module is the most complex part of the Amber core      //
-//  It decodes and sequences all instructions and handles all   //
-//  interrupts                                                  //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Global testbench defines                                    //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains a set of defines for each module so if the module  //
-//  hierarchy changes, hierarchical references to signals       //
-//  will still work as long as this file is updated.            //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-// ---------------------------------------------------------------
-// Module hierarchy defines
-// ---------------------------------------------------------------
-
-    
-
-
-        // ---------------------------------------------------------------
-
-
-
-// Simplified Main Memory Model
-
-
-module a23_decode
-(
-input                       i_clk,
-input       [31:0]          i_read_data,
-input                       i_fetch_stall,                  // stall all stages of the cpu at the same time
-input                       i_irq,                          // interrupt request
-input                       i_firq,                         // Fast interrupt request
-input                       i_dabt,                         // data abort interrupt request
-input                       i_iabt,                         // instruction pre-fetch abort flag
-input                       i_adex,                         // Address Exception
-input       [31:0]          i_execute_address,              // Registered address output by execute stage
-                                                            // 2 LSBs of read address used for calculating 
-                                                            // shift in LDRB ops
-input       [7:0]           i_abt_status,                   // Abort status
-input       [31:0]          i_execute_status_bits,          // current status bits values in execute stage
-input                       i_multiply_done,                // multiply unit is nearly done
-
-
-// --------------------------------------------------
-// Control signals to execute stage
-// --------------------------------------------------
-output reg  [31:0]          o_read_data = 1'd0,
-output reg  [4:0]           o_read_data_alignment = 1'd0,  // 2 LSBs of read address used for calculating shift in LDRB ops
-
-output reg  [31:0]          o_imm32 = 'd0,
-output reg  [4:0]           o_imm_shift_amount = 'd0,
-output reg                  o_shift_imm_zero = 'd0,
-output reg  [3:0]           o_condition = 4'he,             // 4'he = al
-output reg                  o_exclusive_exec = 'd0,         // exclusive access request ( swap instruction )
-output reg                  o_data_access_exec = 'd0,       // high means the memory access is a read 
-                                                            // read or write, low for instruction
-output reg  [1:0]           o_status_bits_mode = 2'b11,     // SVC
-output reg                  o_status_bits_irq_mask = 1'd1,
-output reg                  o_status_bits_firq_mask = 1'd1,
-
-output reg  [3:0]           o_rm_sel = 'd0,
-output reg  [3:0]           o_rds_sel = 'd0,
-output reg  [3:0]           o_rn_sel = 'd0,
-output      [3:0]           o_rm_sel_nxt,
-output      [3:0]           o_rds_sel_nxt,
-output      [3:0]           o_rn_sel_nxt,
-output reg  [1:0]           o_barrel_shift_amount_sel = 'd0,
-output reg  [1:0]           o_barrel_shift_data_sel = 'd0,
-output reg  [1:0]           o_barrel_shift_function = 'd0,
-output reg  [8:0]           o_alu_function = 'd0,
-output reg  [1:0]           o_multiply_function = 'd0,
-output reg  [2:0]           o_interrupt_vector_sel = 'd0,
-output reg  [3:0]           o_address_sel = 4'd2,
-output reg  [1:0]           o_pc_sel = 2'd2,
-output reg  [1:0]           o_byte_enable_sel = 'd0,        // byte, halfword or word write
-output reg  [2:0]           o_status_bits_sel = 'd0,
-output reg  [2:0]           o_reg_write_sel,
-output reg                  o_user_mode_regs_load,
-output reg                  o_user_mode_regs_store_nxt,
-output reg                  o_firq_not_user_mode,
-
-output reg                  o_write_data_wen = 'd0,
-output reg                  o_base_address_wen = 'd0,       // save LDM base address register
-                                                            // in case of data abort
-output reg                  o_pc_wen = 1'd1,
-output reg  [14:0]          o_reg_bank_wen = 'd0,
-output reg  [3:0]           o_reg_bank_wsel = 'd0,
-output reg                  o_status_bits_flags_wen = 'd0,
-output reg                  o_status_bits_mode_wen = 'd0,
-output reg                  o_status_bits_irq_mask_wen = 'd0,
-output reg                  o_status_bits_firq_mask_wen = 'd0,
-
-// --------------------------------------------------
-// Co-Processor interface
-// --------------------------------------------------
-output reg  [2:0]           o_copro_opcode1 = 'd0,
-output reg  [2:0]           o_copro_opcode2 = 'd0,
-output reg  [3:0]           o_copro_crn = 'd0,    
-output reg  [3:0]           o_copro_crm = 'd0,
-output reg  [3:0]           o_copro_num = 'd0,
-output reg  [1:0]           o_copro_operation = 'd0, // 0 = no operation, 
-                                                     // 1 = Move to Amber Core Register from Coprocessor
-                                                     // 2 = Move to Coprocessor from Amber Core Register
-output reg                  o_copro_write_data_wen = 'd0,
-output                      o_iabt_trigger,
-output      [31:0]          o_iabt_address,
-output      [7:0]           o_iabt_status,
-output                      o_dabt_trigger,
-output      [31:0]          o_dabt_address,
-output      [7:0]           o_dabt_status 
-
-
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Functions for Amber 2 Core                                  //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Functions used in more than one module                      //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// ========================================================
-// PC Filter - Remove the status bits 
-// ========================================================
-function [31:0] pcf;
-input [31:0] pc_reg;
-    begin
-    pcf = {6'd0, pc_reg[25:2], 2'd0};
-    end
-endfunction
-
-
-// ========================================================
-// 4-bit to 16-bit 1-hot decode
-// ========================================================
-function [14:0] decode;
-input [3:0] reg_sel;
-begin
-case ( reg_sel )
-    4'h0:    decode = 15'h0001;
-    4'h1:    decode = 15'h0002;
-    4'h2:    decode = 15'h0004;
-    4'h3:    decode = 15'h0008;
-    4'h4:    decode = 15'h0010;
-    4'h5:    decode = 15'h0020;
-    4'h6:    decode = 15'h0040;
-    4'h7:    decode = 15'h0080;
-    4'h8:    decode = 15'h0100;
-    4'h9:    decode = 15'h0200;
-    4'ha:    decode = 15'h0400;
-    4'hb:    decode = 15'h0800;
-    4'hc:    decode = 15'h1000;
-    4'hd:    decode = 15'h2000;
-    4'he:    decode = 15'h4000;
-    default: decode = 15'h0000;
-endcase
-end
-endfunction
-
-
-// ========================================================
-// Convert Stats Bits Mode to one-hot encoded version
-// ========================================================
-function [3:0] oh_status_bits_mode;
-input [1:0] fn_status_bits_mode;
-begin
-oh_status_bits_mode = 
-    fn_status_bits_mode == SVC  ? 1'd1 << OH_SVC  :
-    fn_status_bits_mode == IRQ  ? 1'd1 << OH_IRQ  :
-    fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ :
-                                  1'd1 << OH_USR  ;
-end
-endfunction
-
-// ========================================================
-// Convert mode into ascii name
-// ========================================================
-function [(14*8)-1:0]  mode_name;
-input [4:0] mode;
-begin
-
-mode_name    = mode == USR  ? "User          " :
-               mode == SVC  ? "Supervisor    " :
-               mode == IRQ  ? "Interrupt     " :
-               mode == FIRQ ? "Fast Interrupt" :
-                              "UNKNOWN       " ;
-end
-endfunction
-
-
-// ========================================================
-// Conditional Execution Function
-// ========================================================
-// EQ Z set
-// NE Z clear
-// CS C set
-// CC C clear
-// MI N set
-// PL N clear
-// VS V set
-// VC V clear
-// HI C set and Z clear
-// LS C clear or Z set
-// GE N == V
-// LT N != V
-// GT Z == 0,N == V
-// LE Z == 1 or N != V
-// AL Always (unconditional)
-// NV Never
-
-function conditional_execute;
-input [3:0] condition;
-input [3:0] flags;
-begin
-conditional_execute  
-               = ( condition == AL                                        ) ||
-                 ( condition == EQ  &&  flags[2]                          ) ||
-                 ( condition == NE  && !flags[2]                          ) ||
-                 ( condition == CS  &&  flags[1]                          ) ||
-                 ( condition == CC  && !flags[1]                          ) ||
-                 ( condition == MI  &&  flags[3]                          ) ||
-                 ( condition == PL  && !flags[3]                          ) ||
-                 ( condition == VS  &&  flags[0]                          ) ||
-                 ( condition == VC  && !flags[0]                          ) ||
-            
-                 ( condition == HI  &&    flags[1] && !flags[2]           ) ||
-                 ( condition == LS  &&  (!flags[1] ||  flags[2])          ) ||
-            
-                 ( condition == GE  &&  flags[3] == flags[0]              ) ||
-                 ( condition == LT  &&  flags[3] != flags[0]              ) ||
-
-                 ( condition == GT  &&  !flags[2] && flags[3] == flags[0] ) ||
-                 ( condition == LE  &&  (flags[2] || flags[3] != flags[0])) ;
-            
-end
-endfunction
-
-
-// ========================================================
-// Log 2
-// ========================================================
-
-function [31:0] log2;
-input    [31:0] num;
-integer i;
-integer out;
-begin
-  out = 32'd0;
-  for (i=0; i<30; i=i+1)
-    if ((2**i > num) && (out == 0))
-      out = i-1;
-  log2 = out;
-end
-endfunction
-
-localparam [4:0] RST_WAIT1      = 5'd0,
-                 RST_WAIT2      = 5'd1,
-                 INT_WAIT1      = 5'd2,
-                 INT_WAIT2      = 5'd3,
-                 EXECUTE        = 5'd4,
-                 PRE_FETCH_EXEC = 5'd5,  // Execute the Pre-Fetched Instruction
-                 MEM_WAIT1      = 5'd6,  // conditionally decode current instruction, in case
-                                         // previous instruction does not execute in S2
-                 MEM_WAIT2      = 5'd7,
-                 PC_STALL1      = 5'd8,  // Program Counter altered
-                                         // conditionally decude current instruction, in case
-                                         // previous instruction does not execute in S2
-                 PC_STALL2      = 5'd9,
-                 MTRANS_EXEC1   = 5'd10,
-                 MTRANS_EXEC2   = 5'd11,
-                 MTRANS_EXEC3   = 5'd12,
-                 MTRANS_EXEC3B  = 5'd13,
-                 MTRANS_EXEC4   = 5'd14,
-                 MTRANS5_ABORT  = 5'd15,
-                 MULT_PROC1     = 5'd16,  // first cycle, save pre fetch instruction
-                 MULT_PROC2     = 5'd17,  // do multiplication
-                 MULT_STORE     = 5'd19,  // save RdLo
-                 MULT_ACCUMU    = 5'd20,  // Accumulate add lower 32 bits
-                 SWAP_WRITE     = 5'd22,
-                 SWAP_WAIT1     = 5'd23,
-                 SWAP_WAIT2     = 5'd24,
-                 COPRO_WAIT     = 5'd25;
-                 
-                 
-// ========================================================
-// Internal signals
-// ========================================================
-wire    [31:0]         instruction;
-wire                   instruction_iabt;        // abort flag, follows the instruction
-wire                   instruction_adex;        // address exception flag, follows the instruction
-wire    [31:0]         instruction_address;     // instruction virtual address, follows 
-                                                // the instruction
-wire    [7:0]          instruction_iabt_status; // abort status, follows the instruction
-wire    [1:0]          instruction_sel;
-reg     [3:0]          type;
-wire    [3:0]          opcode;
-wire    [7:0]          imm8;
-wire    [31:0]         offset12;
-wire    [31:0]         offset24;
-wire    [4:0]          shift_imm;
-
-wire                   opcode_compare;
-wire                   mem_op;
-wire                   load_op;
-wire                   store_op;
-wire                   write_pc;
-wire                   immediate_shifter_operand;
-wire                   rds_use_rs;
-wire                   branch;
-wire                   mem_op_pre_indexed;
-wire                   mem_op_post_indexed;
-
-// Flop inputs
-wire    [31:0]         imm32_nxt;
-wire    [4:0]          imm_shift_amount_nxt;
-wire                   shift_imm_zero_nxt;
-wire    [3:0]          condition_nxt;
-reg                    exclusive_exec_nxt;
-reg                    data_access_exec_nxt;
-
-reg     [1:0]          barrel_shift_function_nxt;
-wire    [8:0]          alu_function_nxt;
-reg     [1:0]          multiply_function_nxt;
-reg     [1:0]          status_bits_mode_nxt;
-reg                    status_bits_irq_mask_nxt;
-reg                    status_bits_firq_mask_nxt;
-
-reg     [1:0]          barrel_shift_amount_sel_nxt;
-reg     [1:0]          barrel_shift_data_sel_nxt;
-reg     [3:0]          address_sel_nxt;
-reg     [1:0]          pc_sel_nxt;
-reg     [1:0]          byte_enable_sel_nxt;
-reg     [2:0]          status_bits_sel_nxt;
-reg     [2:0]          reg_write_sel_nxt;
-reg                    user_mode_regs_load_nxt;
-wire                   firq_not_user_mode_nxt;
-
-// ALU Function signals
-reg                    alu_swap_sel_nxt;
-reg                    alu_not_sel_nxt;
-reg     [1:0]          alu_cin_sel_nxt;
-reg                    alu_cout_sel_nxt;
-reg     [3:0]          alu_out_sel_nxt;
-
-reg                    write_data_wen_nxt;
-reg                    copro_write_data_wen_nxt;
-reg                    base_address_wen_nxt;
-reg                    pc_wen_nxt;
-reg     [3:0]          reg_bank_wsel_nxt;
-reg                    status_bits_flags_wen_nxt;
-reg                    status_bits_mode_wen_nxt;
-reg                    status_bits_irq_mask_wen_nxt;
-reg                    status_bits_firq_mask_wen_nxt;
-
-reg                    saved_current_instruction_wen;   // saved load instruction
-reg                    pre_fetch_instruction_wen;       // pre-fetch instruction
-
-reg     [4:0]          control_state = RST_WAIT1;
-reg     [4:0]          control_state_nxt;
-
-
-wire                   dabt;
-reg                    dabt_reg = 'd0;
-reg                    dabt_reg_d1;
-reg                    iabt_reg = 'd0;
-reg                    adex_reg = 'd0;
-reg     [31:0]         abt_address_reg = 'd0;
-reg     [7:0]          abt_status_reg = 'd0;
-reg     [31:0]         saved_current_instruction = 'd0;
-reg                    saved_current_instruction_iabt = 'd0;          // access abort flag
-reg                    saved_current_instruction_adex = 'd0;          // address exception
-reg     [31:0]         saved_current_instruction_address = 'd0;       // virtual address of abort instruction
-reg     [7:0]          saved_current_instruction_iabt_status = 'd0;   // status of abort instruction
-reg     [31:0]         pre_fetch_instruction = 'd0;
-reg                    pre_fetch_instruction_iabt = 'd0;              // access abort flag
-reg                    pre_fetch_instruction_adex = 'd0;              // address exception
-reg     [31:0]         pre_fetch_instruction_address = 'd0;           // virtual address of abort instruction
-reg     [7:0]          pre_fetch_instruction_iabt_status = 'd0;       // status of abort instruction
-
-wire                   instruction_valid;
-wire                   instruction_execute;
-
-reg     [3:0]          mtrans_reg;              // the current register being accessed as part of STM/LDM
-reg     [3:0]          mtrans_reg_d1 = 'd0;     // delayed by 1 period
-reg     [3:0]          mtrans_reg_d2 = 'd0;     // delayed by 2 periods
-reg     [31:0]         mtrans_instruction_nxt;
-
-wire   [31:0]          mtrans_base_reg_change;
-wire   [4:0]           mtrans_num_registers;
-wire                   use_saved_current_instruction;
-wire                   use_pre_fetch_instruction;
-wire                   interrupt;
-wire   [1:0]           interrupt_mode;
-wire   [2:0]           next_interrupt;
-reg                    irq = 'd0;
-reg                    firq = 'd0;
-wire                   firq_request;
-wire                   irq_request;
-wire                   swi_request;
-wire                   und_request;
-wire                   dabt_request;
-reg    [1:0]           copro_operation_nxt;
-reg                    mtrans_r15 = 'd0;
-reg                    mtrans_r15_nxt;
-reg                    restore_base_address = 'd0;
-reg                    restore_base_address_nxt;
-
-wire                   regop_set_flags;
-
-
-// ========================================================
-// Instruction Abort and Data Abort outputs
-// ========================================================
-
-assign o_iabt_trigger     = instruction_iabt && o_status_bits_mode == SVC && control_state == INT_WAIT1;
-assign o_iabt_address     = instruction_address;
-assign o_iabt_status      = instruction_iabt_status;
-
-assign o_dabt_trigger     = dabt_reg && !dabt_reg_d1;
-assign o_dabt_address     = abt_address_reg;
-assign o_dabt_status      = abt_status_reg;
-
-
-// ========================================================
-// Instruction Decode
-// ========================================================
-
-// for instructions that take more than one cycle
-// the instruction is saved in the 'saved_mem_instruction'
-// register and then that register is used for the rest of
-// the execution of the instruction.
-// But if the instruction does not execute because of the
-// condition, then need to select the next instruction to
-// decode
-assign use_saved_current_instruction =  instruction_execute &&
-                          ( control_state == MEM_WAIT1     ||
-                            control_state == MEM_WAIT2     ||
-                            control_state == MTRANS_EXEC1  ||
-                            control_state == MTRANS_EXEC2  || 
-                            control_state == MTRANS_EXEC3  ||
-                            control_state == MTRANS_EXEC3B ||
-                            control_state == MTRANS_EXEC4  ||
-                            control_state == MTRANS5_ABORT ||
-                            control_state == MULT_PROC1    ||
-                            control_state == MULT_PROC2    ||
-                            control_state == MULT_ACCUMU   ||
-                            control_state == MULT_STORE    ||
-                            control_state == INT_WAIT1     ||
-                            control_state == INT_WAIT2     ||
-                            control_state == SWAP_WRITE    ||
-                            control_state == SWAP_WAIT1    ||
-                            control_state == SWAP_WAIT2    ||
-                            control_state == COPRO_WAIT     );
-
-assign use_pre_fetch_instruction = control_state == PRE_FETCH_EXEC;
-
-
-assign instruction_sel  =         use_saved_current_instruction  ? 2'd1 :  // saved_current_instruction 
-                                  use_pre_fetch_instruction      ? 2'd2 :  // pre_fetch_instruction     
-                                                                   2'd0 ;  // o_read_data               
-
-assign instruction      =         instruction_sel == 2'd0 ? o_read_data               :
-                                  instruction_sel == 2'd1 ? saved_current_instruction :
-                                                            pre_fetch_instruction     ;
-
-// abort flag
-assign instruction_iabt =         instruction_sel == 2'd0 ? iabt_reg                       :
-                                  instruction_sel == 2'd1 ? saved_current_instruction_iabt :
-                                                            pre_fetch_instruction_iabt     ;
-                                                     
-assign instruction_address =      instruction_sel == 2'd0 ? abt_address_reg                   :
-                                  instruction_sel == 2'd1 ? saved_current_instruction_address :
-                                                            pre_fetch_instruction_address     ;
-
-assign instruction_iabt_status =  instruction_sel == 2'd0 ? abt_status_reg                        :
-                                  instruction_sel == 2'd1 ? saved_current_instruction_iabt_status :
-                                                            pre_fetch_instruction_iabt_status     ;
-
-// instruction address exception
-assign instruction_adex =         instruction_sel == 2'd0 ? adex_reg                       :
-                                  instruction_sel == 2'd1 ? saved_current_instruction_adex :
-                                                            pre_fetch_instruction_adex     ;
-
-// Instruction Decode - Order is important!
-always @*
-    casez ({instruction[27:20], instruction[7:4]})
-        12'b00010?001001 : type = SWAP;
-        12'b000000??1001 : type = MULT;
-        12'b00?????????? : type = REGOP;
-        12'b01?????????? : type = TRANS;   
-        12'b100????????? : type = MTRANS;  
-        12'b101????????? : type = BRANCH; 
-        12'b110????????? : type = CODTRANS;
-        12'b1110???????0 : type = COREGOP;         
-        12'b1110???????1 : type = CORTRANS;       
-        default:           type = SWI;
-    endcase
-
-    
-// ========================================================
-// Fixed fields within the instruction
-// ========================================================
-                       
-assign opcode        = instruction[24:21];
-assign condition_nxt = instruction[31:28];
-
-assign o_rm_sel_nxt    = instruction[3:0];
-                                                      
-assign o_rn_sel_nxt    = branch  ? 4'd15 : // Use PC to calculate branch destination
-                                 instruction[19:16] ;
-
-assign o_rds_sel_nxt   = control_state == SWAP_WRITE  ? instruction[3:0]   : // Rm gets written out to memory
-                       type == MTRANS               ? mtrans_reg      :
-                       branch                       ? 4'd15 : // Update the PC
-                       rds_use_rs                   ? instruction[11:8]  : 
-                                                      instruction[15:12] ;
-                                                     
-
-assign shift_imm     = instruction[11:7];
-assign offset12      = { 20'h0, instruction[11:0]};
-assign offset24      = {{6{instruction[23]}}, instruction[23:0], 2'd0 }; // sign extend
-assign imm8          = instruction[7:0];
-
-assign immediate_shifter_operand = instruction[25];
-assign rds_use_rs                = (type == REGOP && !instruction[25] && instruction[4]) ||
-                                   (type == MULT && 
-                                    (control_state == MULT_PROC1  || 
-                                     control_state == MULT_PROC2  ||
-                                     instruction_valid && !interrupt )) ;
-assign branch                    = type == BRANCH;
-assign opcode_compare =
-            opcode == CMP || 
-            opcode == CMN || 
-            opcode == TEQ || 
-            opcode == TST ;
-            
-            
-assign mem_op               = type == TRANS;
-assign load_op              = mem_op && instruction[20];
-assign store_op             = mem_op && !instruction[20];
-assign write_pc             = pc_wen_nxt && pc_sel_nxt != 2'd0;
-assign regop_set_flags      = type == REGOP && instruction[20]; 
-
-assign mem_op_pre_indexed   =  instruction[24] && instruction[21];
-assign mem_op_post_indexed  = !instruction[24];
-
-assign imm32_nxt            =  // add 0 to Rm
-                               type == MULT               ? {  32'd0 } :
-                               
-                               // 4 x number of registers
-                               type == MTRANS             ? {  mtrans_base_reg_change     } :
-                               type == BRANCH             ? {  offset24                   } :
-                               type == TRANS              ? {  offset12                   } :
-                               instruction[11:8] == 4'h0 ? {            24'h0, imm8[7:0] } :
-                               instruction[11:8] == 4'h1 ? { imm8[1:0], 24'h0, imm8[7:2] } :
-                               instruction[11:8] == 4'h2 ? { imm8[3:0], 24'h0, imm8[7:4] } :
-                               instruction[11:8] == 4'h3 ? { imm8[5:0], 24'h0, imm8[7:6] } :
-                               instruction[11:8] == 4'h4 ? { imm8[7:0], 24'h0 } :
-                               instruction[11:8] == 4'h5 ? { 2'h0,  imm8[7:0], 22'h0 } :
-                               instruction[11:8] == 4'h6 ? { 4'h0,  imm8[7:0], 20'h0 } :
-                               instruction[11:8] == 4'h7 ? { 6'h0,  imm8[7:0], 18'h0 } :
-                               instruction[11:8] == 4'h8 ? { 8'h0,  imm8[7:0], 16'h0 } :
-                               instruction[11:8] == 4'h9 ? { 10'h0, imm8[7:0], 14'h0 } :
-                               instruction[11:8] == 4'ha ? { 12'h0, imm8[7:0], 12'h0 } :
-                               instruction[11:8] == 4'hb ? { 14'h0, imm8[7:0], 10'h0 } :
-                               instruction[11:8] == 4'hc ? { 16'h0, imm8[7:0], 8'h0 } :
-                               instruction[11:8] == 4'hd ? { 18'h0, imm8[7:0], 6'h0 } :
-                               instruction[11:8] == 4'he ? { 20'h0, imm8[7:0], 4'h0 } :
-                                                            { 22'h0, imm8[7:0], 2'h0 } ;
-
-
-assign imm_shift_amount_nxt = shift_imm ;
-
-       // This signal is encoded in the decode stage because 
-       // it is on the critical path in the execute stage
-assign shift_imm_zero_nxt   = imm_shift_amount_nxt == 5'd0 &&       // immediate amount = 0
-                              barrel_shift_amount_sel_nxt == 2'd2;  // shift immediate amount
-
-assign alu_function_nxt     = { alu_swap_sel_nxt, 
-                                alu_not_sel_nxt, 
-                                alu_cin_sel_nxt,
-                                alu_cout_sel_nxt, 
-                                alu_out_sel_nxt  };
-                            
-                            
-// ========================================================
-// MTRANS Operations
-// ========================================================
-   
-   // Bit 15 = r15
-   // Bit 0  = R0
-   // In LDM and STM instructions R0 is loaded or stored first 
-always @*
-    casez (instruction[15:0])
-    16'b???????????????1 : mtrans_reg = 4'h0 ;
-    16'b??????????????10 : mtrans_reg = 4'h1 ;
-    16'b?????????????100 : mtrans_reg = 4'h2 ;
-    16'b????????????1000 : mtrans_reg = 4'h3 ;
-    16'b???????????10000 : mtrans_reg = 4'h4 ;
-    16'b??????????100000 : mtrans_reg = 4'h5 ;
-    16'b?????????1000000 : mtrans_reg = 4'h6 ;
-    16'b????????10000000 : mtrans_reg = 4'h7 ;
-    16'b???????100000000 : mtrans_reg = 4'h8 ;
-    16'b??????1000000000 : mtrans_reg = 4'h9 ;
-    16'b?????10000000000 : mtrans_reg = 4'ha ;
-    16'b????100000000000 : mtrans_reg = 4'hb ;
-    16'b???1000000000000 : mtrans_reg = 4'hc ;
-    16'b??10000000000000 : mtrans_reg = 4'hd ;
-    16'b?100000000000000 : mtrans_reg = 4'he ;
-    default              : mtrans_reg = 4'hf ;
-    endcase
-
-always @*
-    casez (instruction[15:0])
-    16'b???????????????1 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 1],  1'd0};
-    16'b??????????????10 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 2],  2'd0}; 
-    16'b?????????????100 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 3],  3'd0}; 
-    16'b????????????1000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 4],  4'd0}; 
-    16'b???????????10000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 5],  5'd0}; 
-    16'b??????????100000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 6],  6'd0}; 
-    16'b?????????1000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 7],  7'd0}; 
-    16'b????????10000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 8],  8'd0}; 
-    16'b???????100000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 9],  9'd0}; 
-    16'b??????1000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:10], 10'd0}; 
-    16'b?????10000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:11], 11'd0}; 
-    16'b????100000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:12], 12'd0}; 
-    16'b???1000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:13], 13'd0}; 
-    16'b??10000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:14], 14'd0}; 
-    16'b?100000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15 ], 15'd0}; 
-    default              : mtrans_instruction_nxt = {instruction[31:16],                     16'd0}; 
-    endcase
-
-
-// number of registers to be stored
-assign mtrans_num_registers =   {4'd0, instruction[15]} + 
-                                {4'd0, instruction[14]} + 
-                                {4'd0, instruction[13]} + 
-                                {4'd0, instruction[12]} +
-                                {4'd0, instruction[11]} +
-                                {4'd0, instruction[10]} +
-                                {4'd0, instruction[ 9]} +
-                                {4'd0, instruction[ 8]} +
-                                {4'd0, instruction[ 7]} +
-                                {4'd0, instruction[ 6]} +
-                                {4'd0, instruction[ 5]} +
-                                {4'd0, instruction[ 4]} +
-                                {4'd0, instruction[ 3]} +
-                                {4'd0, instruction[ 2]} +
-                                {4'd0, instruction[ 1]} +
-                                {4'd0, instruction[ 0]} ;
-                                
-// 4 x number of registers to be stored
-assign mtrans_base_reg_change = {25'd0, mtrans_num_registers, 2'd0};
-
-// ========================================================
-// Interrupts
-// ========================================================
-
-assign firq_request = firq && !i_execute_status_bits[26];
-assign irq_request  = irq  && !i_execute_status_bits[27];
-assign swi_request  = type == SWI;
-assign dabt_request = dabt_reg;
-
-// copro15 and copro13 only supports reg trans opcodes
-// all other opcodes involving co-processors cause an 
-// undefined instrution interrupt
-assign und_request  =   type == CODTRANS || 
-                        type == COREGOP  || 
-                      ( type == CORTRANS && instruction[11:8] != 4'd15 );
-
-
-  // in order of priority !!                 
-  // Highest 
-  // 1 Reset
-  // 2 Data Abort (including data TLB miss)
-  // 3 FIRQ
-  // 4 IRQ
-  // 5 Prefetch Abort (including prefetch TLB miss)
-  // 6 Undefined instruction, SWI
-  // Lowest                        
-assign next_interrupt = dabt_request     ? 3'd1 :  // Data Abort
-                        firq_request     ? 3'd2 :  // FIRQ
-                        irq_request      ? 3'd3 :  // IRQ
-                        instruction_adex ? 3'd4 :  // Address Exception 
-                        instruction_iabt ? 3'd5 :  // PreFetch Abort, only triggered 
-                                                   // if the instruction is used
-                        und_request      ? 3'd6 :  // Undefined Instruction
-                        swi_request      ? 3'd7 :  // SWI
-                                           3'd0 ;  // none             
-
-        // SWI and undefined instructions do not cause an interrupt in the decode
-        // stage. They only trigger interrupts if they arfe executed, so the
-        // interrupt is triggered if the execute condition is met in the execute stage
-assign interrupt      = next_interrupt != 3'd0 && 
-                        next_interrupt != 3'd7 &&  // SWI
-                        next_interrupt != 3'd6 ;   // undefined interrupt
-
-
-assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ :
-                        next_interrupt == 3'd3 ? IRQ  :
-                        next_interrupt == 3'd4 ? SVC  :
-                        next_interrupt == 3'd5 ? SVC  :
-                        next_interrupt == 3'd6 ? SVC  :
-                        next_interrupt == 3'd7 ? SVC  :
-                        next_interrupt == 3'd1 ? SVC  :
-                                                 USR  ;
-
-
-
-
-// ========================================================
-// Generate control signals
-// ========================================================
-always @*
-    begin
-    // default mode
-    status_bits_mode_nxt            = i_execute_status_bits[1:0];   // change to mode in execute stage get reflected
-                                                                    // back to this stage automatically
-    status_bits_irq_mask_nxt        = o_status_bits_irq_mask;
-    status_bits_firq_mask_nxt       = o_status_bits_firq_mask;
-    exclusive_exec_nxt              = 1'd0;
-    data_access_exec_nxt            = 1'd0;
-    copro_operation_nxt             = 'd0;
-    
-    // Save an instruction to use later
-    saved_current_instruction_wen   = 1'd0;
-    pre_fetch_instruction_wen       = 1'd0;
-    mtrans_r15_nxt                  = mtrans_r15;
-    restore_base_address_nxt        = restore_base_address;
-    
-    // default Mux Select values
-    barrel_shift_amount_sel_nxt     = 'd0;  // don't shift the input
-    barrel_shift_data_sel_nxt       = 'd0;  // immediate value
-    barrel_shift_function_nxt       = 'd0;
-    multiply_function_nxt           = 'd0;
-    address_sel_nxt                 = 'd0;  
-    pc_sel_nxt                      = 'd0;  
-    byte_enable_sel_nxt             = 'd0;  
-    status_bits_sel_nxt             = 'd0;  
-    reg_write_sel_nxt               = 'd0;  
-    user_mode_regs_load_nxt         = 'd0;
-    o_user_mode_regs_store_nxt      = 'd0;  
-           
-    // ALU Muxes
-    alu_swap_sel_nxt                = 'd0;  
-    alu_not_sel_nxt                 = 'd0;  
-    alu_cin_sel_nxt                 = 'd0;  
-    alu_cout_sel_nxt                = 'd0;  
-    alu_out_sel_nxt                 = 'd0;  
-    
-    // default Flop Write Enable values
-    write_data_wen_nxt              = 'd0;
-    copro_write_data_wen_nxt        = 'd0;
-    base_address_wen_nxt            = 'd0;
-    pc_wen_nxt                      = 'd1;
-    reg_bank_wsel_nxt               = 'hF;  // Don't select any
-    status_bits_flags_wen_nxt       = 'd0;
-    status_bits_mode_wen_nxt        = 'd0;
-    status_bits_irq_mask_wen_nxt    = 'd0;
-    status_bits_firq_mask_wen_nxt   = 'd0;
-    
-    if ( instruction_valid && !interrupt )
-        begin
-        if ( type == REGOP )
-            begin
-            if ( !opcode_compare )
-                begin
-                // Check is the load destination is the PC
-                if (instruction[15:12]  == 4'd15)
-                    begin
-                    pc_sel_nxt      = 2'd1; // alu_out
-                    address_sel_nxt = 4'd1; // alu_out
-                    end
-                else                     
-                    reg_bank_wsel_nxt = instruction[15:12];
-                end
-                
-            if ( !immediate_shifter_operand )
-                barrel_shift_function_nxt  = instruction[6:5];
-                          
-            if ( !immediate_shifter_operand )
-                barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
-                
-            if ( !immediate_shifter_operand && instruction[4] )
-                barrel_shift_amount_sel_nxt = 2'd1; // Shift amount from Rs registter
-                
-            if ( !immediate_shifter_operand && !instruction[4] ) 
-                barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount 
-                
-            if ( opcode == ADD || opcode == CMN )   // CMN is just like an ADD
-                begin
-                alu_out_sel_nxt  = 4'd1; // Add
-                end
-                
-            if ( opcode == ADC ) // Add with Carry
-                begin
-                alu_out_sel_nxt  = 4'd1; // Add
-                alu_cin_sel_nxt  = 2'd2; // carry in from status_bits
-                end
-                
-            if ( opcode == SUB || opcode == CMP ) // Subtract
-                begin
-                alu_out_sel_nxt  = 4'd1; // Add
-                alu_cin_sel_nxt  = 2'd1; // cin = 1
-                alu_not_sel_nxt  = 1'd1; // invert B
-                end
-                
-            // SBC (Subtract with Carry) subtracts the value of its 
-            // second operand and the value of NOT(Carry flag) from
-            // the value of its first operand.
-            //  Rd = Rn - shifter_operand - NOT(C Flag)
-            if ( opcode == SBC ) // Subtract with Carry
-                begin
-                alu_out_sel_nxt  = 4'd1; // Add
-                alu_cin_sel_nxt  = 2'd2; // carry in from status_bits
-                alu_not_sel_nxt  = 1'd1; // invert B
-                end
-                
-            if ( opcode == RSB ) // Reverse Subtract
-                begin
-                alu_out_sel_nxt  = 4'd1; // Add
-                alu_cin_sel_nxt  = 2'd1; // cin = 1
-                alu_not_sel_nxt  = 1'd1; // invert B
-                alu_swap_sel_nxt = 1'd1; // swap A and B
-                end
-                
-            if ( opcode == RSC ) // Reverse Subtract with carry
-                begin
-                alu_out_sel_nxt  = 4'd1; // Add
-                alu_cin_sel_nxt  = 2'd2; // carry in from status_bits
-                alu_not_sel_nxt  = 1'd1; // invert B
-                alu_swap_sel_nxt = 1'd1; // swap A and B
-                end
-                
-            if ( opcode == AND || opcode == TST ) // Logical AND, Test  (using AND operator)
-                begin
-                alu_out_sel_nxt  = 4'd8;  // AND
-                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
-                end
-                
-            if ( opcode == EOR || opcode == TEQ ) // Logical Exclusive OR, Test Equivalence (using EOR operator)
-                begin
-                alu_out_sel_nxt = 4'd6;  // XOR
-                alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
-                end
-
-            if ( opcode == ORR )
-                begin
-                alu_out_sel_nxt  = 4'd7; // OR
-                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
-                end
-                
-            if ( opcode == BIC ) // Bit Clear (using AND & NOT operators)
-                begin
-                alu_out_sel_nxt  = 4'd8;  // AND
-                alu_not_sel_nxt  = 1'd1;  // invert B
-                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
-                end
-                
-            if ( opcode == MOV ) // Move
-                begin
-                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
-                end
-                
-            if ( opcode == MVN ) // Move NOT
-                begin
-                alu_not_sel_nxt  = 1'd1; // invert B
-                alu_cout_sel_nxt = 1'd1;  // i_barrel_shift_carry
-                end
-            end
-        
-        // Load & Store instructions
-        if ( mem_op )
-            begin
-            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
-            pc_wen_nxt                      = 1'd0; // hold current PC value
-            data_access_exec_nxt            = 1'd1; // indicate that its a data read or write, 
-                                                    // rather than an instruction fetch
-            alu_out_sel_nxt                 = 4'd1; // Add
-            
-            if ( !instruction[23] )  // U: Subtract offset
-                begin
-                alu_cin_sel_nxt  = 2'd1; // cin = 1
-                alu_not_sel_nxt  = 1'd1; // invert B
-                end
-            
-            if ( store_op )
-                begin
-                write_data_wen_nxt = 1'd1;
-                if ( type == TRANS && instruction[22] )
-                    byte_enable_sel_nxt = 2'd1;         // Save byte
-                end
-                
-                // need to update the register holding the address ?
-                // This is Rn bits [19:16]
-            if ( mem_op_pre_indexed || mem_op_post_indexed )
-                begin
-                // Check is the load destination is the PC
-                if ( o_rn_sel_nxt  == 4'd15 )
-                    pc_sel_nxt = 2'd1; 
-                else                     
-                    reg_bank_wsel_nxt = o_rn_sel_nxt;
-                end
-                
-                // if post-indexed, then use Rn rather than ALU output, as address
-            if ( mem_op_post_indexed )
-               address_sel_nxt = 4'd4; // Rn
-            else   
-               address_sel_nxt = 4'd1; // alu out
-               
-            if ( instruction[25] && type ==  TRANS )
-                barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
-                
-            if ( type == TRANS && instruction[25] && shift_imm != 5'd0 ) 
-                begin   
-                barrel_shift_function_nxt   = instruction[6:5];
-                barrel_shift_amount_sel_nxt = 2'd2; // imm_shift_amount
-                end
-            end
-            
-        if ( type == BRANCH )
-            begin
-            pc_sel_nxt      = 2'd1; // alu_out
-            address_sel_nxt = 4'd1; // alu_out
-            alu_out_sel_nxt = 4'd1; // Add
-            
-            if ( instruction[24] ) // Link
-                begin
-                reg_bank_wsel_nxt  = 4'd14;  // Save PC to LR
-                reg_write_sel_nxt = 3'd1;            // pc - 32'd4
-                end
-            end
-            
-        if ( type == MTRANS )
-            begin
-            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
-            pc_wen_nxt                      = 1'd0; // hold current PC value
-            data_access_exec_nxt            = 1'd1; // indicate that its a data read or write, 
-                                                    // rather than an instruction fetch
-            alu_out_sel_nxt                 = 4'd1; // Add
-            mtrans_r15_nxt                  = instruction[15];  // load or save r15 ?
-            base_address_wen_nxt            = 1'd1; // Save the value of the register used for the base address,
-                                                    // in case of a data abort, and need to restore the value        
-
-            // The spec says -
-            // If the instruction would have overwritten the base with data 
-            // (that is, it has the base in the transfer list), the overwriting is prevented.
-            // This is true even when the abort occurs after the base word gets loaded
-            restore_base_address_nxt        = instruction[20] && 
-                                                (instruction[15:0] & (1'd1 << instruction[19:16]));
-
-            // Increment or Decrement
-            if ( instruction[23] ) // increment
-                begin
-                if ( instruction[24] )    // increment before
-                    address_sel_nxt = 4'd7; // Rn + 4
-                else    
-                    address_sel_nxt = 4'd4; // Rn
-                end
-            else // decrement
-                begin
-                alu_cin_sel_nxt  = 2'd1; // cin = 1
-                alu_not_sel_nxt  = 1'd1; // invert B
-                if ( !instruction[24] )    // decrement after
-                    address_sel_nxt  = 4'd6; // alu out + 4
-                else
-                    address_sel_nxt  = 4'd1; // alu out
-                end
-                
-            // Load or store ?
-            if ( !instruction[20] )  // Store
-                write_data_wen_nxt = 1'd1; 
-                
-            // LDM: load into user mode registers, when in priviledged mode  
-            // DOnt use mtrans_r15 here because its not loaded yet   
-            if ( {instruction[22:20],instruction[15]} == 4'b1010 )
-                user_mode_regs_load_nxt = 1'd1;
-                
-            // SDM: store the user mode registers, when in priviledged mode     
-            if ( {instruction[22:20]} == 3'b100 )  
-                o_user_mode_regs_store_nxt = 1'd1;
-                                
-            // update the base register ?
-            if ( instruction[21] )  // the W bit
-                reg_bank_wsel_nxt  = o_rn_sel_nxt;
-            end
-            
-            
-        if ( type == MULT )
-            begin
-            multiply_function_nxt[0]        = 1'd1; // set enable
-                                                    // some bits can be changed just below
-            saved_current_instruction_wen   = 1'd1; // Save the Multiply instruction to 
-                                                    // refer back to later
-            pc_wen_nxt                      = 1'd0; // hold current PC value
-            
-            if ( instruction[21] )
-                multiply_function_nxt[1]    = 1'd1; // accumulate
-            end
-                       
-            
-        // swp - do read part first
-        if ( type == SWAP )
-            begin
-            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
-            pc_wen_nxt                      = 1'd0; // hold current PC value
-            data_access_exec_nxt            = 1'd1; // indicate that its a data read or write, 
-                                                    // rather than an instruction fetch
-            barrel_shift_data_sel_nxt       = 2'd2; // Shift value from Rm register
-            address_sel_nxt                 = 4'd4; // Rn
-            exclusive_exec_nxt              = 1'd1; // signal an exclusive access
-            end
-
-
-        // mcr & mrc - takes two cycles
-        if ( type == CORTRANS && !und_request )
-            begin
-            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
-            pc_wen_nxt                      = 1'd0; // hold current PC value
-            address_sel_nxt                 = 4'd3; // pc  (not pc + 4)
-            
-            if ( instruction[20] ) // MRC
-                copro_operation_nxt         = 2'd1;  // Register transfer from Co-Processor
-            else // MCR
-                begin
-                 // Don't enable operation to Co-Processor until next period
-                 // So it gets the Rd value from the execution stage at the same time
-                copro_operation_nxt      = 2'd0;
-                copro_write_data_wen_nxt = 1'd1;  // Rd register value to co-processor
-                end
-            end
-
-        
-        if ( type == SWI || und_request )
-            begin
-            // save address of next instruction to Supervisor Mode LR
-            reg_write_sel_nxt               = 3'd1;            // pc -4
-            reg_bank_wsel_nxt               = 4'd14;  // LR
-        
-            address_sel_nxt                 = 4'd2;            // interrupt_vector
-            pc_sel_nxt                      = 2'd2;            // interrupt_vector
-        
-            status_bits_mode_nxt            = interrupt_mode;  // e.g. Supervisor mode
-            status_bits_mode_wen_nxt        = 1'd1;
-        
-            // disable normal interrupts
-            status_bits_irq_mask_nxt        = 1'd1;
-            status_bits_irq_mask_wen_nxt    = 1'd1;
-            end
-
-        
-        if ( regop_set_flags )
-            begin
-            status_bits_flags_wen_nxt = 1'd1;
-            
-            // If <Rd> is r15, the ALU output is copied to the Status Bits. 
-            // Not allowed to use r15 for mul or lma instructions           
-            if ( instruction[15:12] == 4'd15 )
-                begin
-                status_bits_sel_nxt       = 3'd1; // alu out
-                
-                // Priviledged mode? Then also update the other status bits
-                if ( i_execute_status_bits[1:0] != USR )
-                    begin
-                    status_bits_mode_wen_nxt      = 1'd1;
-                    status_bits_irq_mask_wen_nxt  = 1'd1;
-                    status_bits_firq_mask_wen_nxt = 1'd1;
-                    end
-                end
-            end
-            
-        end    
-
-    // Handle asynchronous interrupts.
-    // interrupts are processed only during execution states
-    // multicycle instructions must complete before the interrupt starts
-    // SWI, Address Exception and Undefined Instruction interrupts are only executed if the
-    // instruction that causes the interrupt is conditionally executed so
-    // its not handled here
-    if ( instruction_valid && interrupt &&  next_interrupt != 3'd6 )
-        begin
-        // Save the interrupt causing instruction to refer back to later
-        // This also saves the instruction abort vma and status, in the case of an
-        // instruction abort interrupt
-        saved_current_instruction_wen   = 1'd1; 
-        
-        // save address of next instruction to Supervisor Mode LR
-        // Address Exception ?
-        if ( next_interrupt == 3'd4 )
-            reg_write_sel_nxt               = 3'd7;            // pc
-        else
-            reg_write_sel_nxt               = 3'd1;            // pc -4
-            
-        reg_bank_wsel_nxt               = 4'd14;           // LR
-        
-        address_sel_nxt                 = 4'd2;            // interrupt_vector
-        pc_sel_nxt                      = 2'd2;            // interrupt_vector
-        
-        status_bits_mode_nxt            = interrupt_mode;  // e.g. Supervisor mode
-        status_bits_mode_wen_nxt        = 1'd1;
-        
-        // disable normal interrupts
-        status_bits_irq_mask_nxt        = 1'd1;
-        status_bits_irq_mask_wen_nxt    = 1'd1;
-
-        // disable fast interrupts
-        if ( next_interrupt == 3'd2 ) // FIRQ
-            begin
-            status_bits_firq_mask_nxt        = 1'd1;
-            status_bits_firq_mask_wen_nxt    = 1'd1;
-            end
-        end
-        
-
-    // previous instruction was either ldr or sdr
-    // if it is currently executing in the execute stage do the following    
-    if ( control_state == MEM_WAIT1 )
-        begin
-        // Save the next instruction to execute later
-        // Do this even if this instruction does not execute because of Condition
-        pre_fetch_instruction_wen   = 1'd1;
-        
-        if ( instruction_execute ) // conditional execution state
-            begin
-            address_sel_nxt             = 4'd3; // pc  (not pc + 4)
-            pc_wen_nxt                  = 1'd0; // hold current PC value
-            end
-        end
-            
-    
-    // completion of load operation        
-    if ( control_state == MEM_WAIT2 && load_op )
-        begin
-        barrel_shift_data_sel_nxt   = 2'd1;  // load word from memory
-        barrel_shift_amount_sel_nxt = 2'd3;  // shift by address[1:0] x 8
-        
-        // shift needed
-        if ( i_execute_address[1:0] != 2'd0 )
-            barrel_shift_function_nxt = ROR;
-            
-        // load a byte            
-        if ( type == TRANS && instruction[22] )
-            alu_out_sel_nxt             = 4'd3;  // zero_extend8
-            
-        if ( !dabt )  // dont load data there is an abort on the data read
-            begin    
-            // Check if the load destination is the PC
-            if (instruction[15:12]  == 4'd15)
-                begin
-                pc_sel_nxt      = 2'd1; // alu_out
-                address_sel_nxt = 4'd1; // alu_out
-                end
-            else                     
-                reg_bank_wsel_nxt = instruction[15:12];
-            end
-        end
-        
-        
-    // second cycle of multiple load or store
-    if ( control_state == MTRANS_EXEC1 )
-        begin
-        // Save the next instruction to execute later
-        // Do this even if this instruction does not execute because of Condition
-        pre_fetch_instruction_wen   = 1'd1;
-        
-        if ( instruction_execute ) // conditional execution state
-            begin
-            address_sel_nxt             = 4'd5;  // o_address
-            pc_wen_nxt                  = 1'd0;  // hold current PC value
-            data_access_exec_nxt        = 1'd1;  // indicate that its a data read or write, 
-                                                 // rather than an instruction fetch
-        
-            if ( !instruction[20] ) // Store
-                write_data_wen_nxt = 1'd1;
-                
-            // LDM: load into user mode registers, when in priviledged mode     
-            if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
-                user_mode_regs_load_nxt = 1'd1;
-                
-            // SDM: store the user mode registers, when in priviledged mode     
-            if ( {instruction[22:20]} == 3'b100 )  
-                o_user_mode_regs_store_nxt = 1'd1;
-            end    
-        end    
-       
-        
-        // third cycle of multiple load or store
-    if ( control_state == MTRANS_EXEC2 )
-        begin
-        address_sel_nxt             = 4'd5;  // o_address
-        pc_wen_nxt                  = 1'd0;  // hold current PC value
-        data_access_exec_nxt        = 1'd1;  // indicate that its a data read or write, 
-                                             // rather than an instruction fetch
-        barrel_shift_data_sel_nxt   = 2'd1;  // load word from memory
-        
-        // Load or Store
-        if ( instruction[20] ) // Load
-            begin
-            // Can never be loading the PC in this state, as the PC is always
-            // the last register in the set to be loaded
-            if ( !dabt )
-                reg_bank_wsel_nxt = mtrans_reg_d2;
-            end
-        else // Store
-            write_data_wen_nxt = 1'd1;
-            
-        // LDM: load into user mode registers, when in priviledged mode     
-        if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
-            user_mode_regs_load_nxt = 1'd1;
-            
-        // SDM: store the user mode registers, when in priviledged mode     
-        if ( {instruction[22:20]} == 3'b100 )  
-            o_user_mode_regs_store_nxt = 1'd1;
-        end
-        
-        
-        // second or fourth cycle of multiple load or store
-    if ( control_state == MTRANS_EXEC3 && instruction_execute )
-        begin
-        address_sel_nxt             = 4'd3; // pc  (not pc + 4)
-        pc_wen_nxt                  = 1'd0;  // hold current PC value
-        barrel_shift_data_sel_nxt   = 2'd1;  // load word from memory
-        
-        // Can never be loading the PC in this state, as the PC is always
-        // the last register in the set to be loaded
-        if ( instruction[20] && !dabt ) // Load
-            reg_bank_wsel_nxt = mtrans_reg_d2;
-            
-        // LDM: load into user mode registers, when in priviledged mode     
-        if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
-            user_mode_regs_load_nxt = 1'd1;
-           
-        // SDM: store the user mode registers, when in priviledged mode     
-        if ( {instruction[22:20]} == 3'b100 )  
-            o_user_mode_regs_store_nxt = 1'd1;
-       end
-
-    // state is used for LMD/STM of a single register
-    if ( control_state == MTRANS_EXEC3B && instruction_execute )
-        begin
-        // Save the next instruction to execute later
-        // Do this even if this instruction does not execute because of Condition
-        pre_fetch_instruction_wen   = 1'd1;
-            
-        address_sel_nxt             = 4'd3;  // pc  (not pc + 4)
-        pc_wen_nxt                  = 1'd0;  // hold current PC value
-        
-        // LDM: load into user mode registers, when in priviledged mode     
-        if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
-            user_mode_regs_load_nxt = 1'd1;
-            
-        // SDM: store the user mode registers, when in priviledged mode     
-        if ( {instruction[22:20]} == 3'b100 )  
-            o_user_mode_regs_store_nxt = 1'd1;
-        end
-          
-    if ( control_state == MTRANS_EXEC4 )
-        begin
-        barrel_shift_data_sel_nxt   = 2'd1;  // load word from memory
-        
-        if ( instruction[20] ) // Load
-            begin
-            if (!dabt) // dont overwrite registers or status if theres a data abort
-                begin
-                if ( mtrans_reg_d2 == 4'd15 ) // load new value into PC
-                    begin
-                    address_sel_nxt = 4'd1; // alu_out - read instructions using new PC value
-                    pc_sel_nxt      = 2'd1; // alu_out
-                    pc_wen_nxt      = 1'd1; // write PC
-                    
-                    // ldm with S bit and pc: the Status bits are updated
-                    // Node this must be done only at the end
-                    // so the register set is the set in the mode before it
-                    // gets changed. 
-                    if ( instruction[22] ) 
-                         begin
-                         status_bits_sel_nxt           = 3'd1; // alu out
-                         status_bits_flags_wen_nxt     = 1'd1;
-                         
-                         // Can't change the mode or mask bits in User mode
-                         if ( i_execute_status_bits[1:0] != USR ) 
-                            begin
-                            status_bits_mode_wen_nxt      = 1'd1;
-                            status_bits_irq_mask_wen_nxt  = 1'd1;
-                            status_bits_firq_mask_wen_nxt = 1'd1;
-                            end
-                         end
-                    end
-                else
-                    begin
-                    reg_bank_wsel_nxt = mtrans_reg_d2;
-                    end
-                end
-            end
-           
-           // we have a data abort interrupt
-        if ( dabt )
-            begin    
-            pc_wen_nxt = 1'd0;  // hold current PC value
-            end
-            
-        // LDM: load into user mode registers, when in priviledged mode     
-        if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
-            user_mode_regs_load_nxt = 1'd1;
-            
-        // SDM: store the user mode registers, when in priviledged mode     
-        if ( {instruction[22:20]} == 3'b100 )  
-            o_user_mode_regs_store_nxt = 1'd1;
-        end
-        
-        
-    // state is for when a data abort interrupt is triggered during an LDM
-    if ( control_state == MTRANS5_ABORT )
-        begin
-        // Restore the Base Address, if the base register is included in the
-        // list of registers being loaded
-        if (restore_base_address) // LDM with base address in register list
-            begin
-            reg_write_sel_nxt = 3'd6;                        // write base_register
-            reg_bank_wsel_nxt  = instruction[19:16];         // to Rn
-            end
-        end
-        
-        
-        // Multiply or Multiply-Accumulate
-    if ( control_state == MULT_PROC1 && instruction_execute )
-        begin
-        // Save the next instruction to execute later
-        // Do this even if this instruction does not execute because of Condition
-        pre_fetch_instruction_wen   = 1'd1;
-        pc_wen_nxt                  = 1'd0;  // hold current PC value
-        multiply_function_nxt       = o_multiply_function;
-        end
-
-        
-        // Multiply or Multiply-Accumulate
-        // Do multiplication
-        // Wait for done or accumulate signal
-    if ( control_state == MULT_PROC2 )
-        begin
-        // Save the next instruction to execute later
-        // Do this even if this instruction does not execute because of Condition
-        pc_wen_nxt              = 1'd0;  // hold current PC value
-        address_sel_nxt         = 4'd3;  // pc  (not pc + 4)
-        multiply_function_nxt   = o_multiply_function;
-        end
-
-                
-    // Save RdLo
-    // always last cycle of all multiply or multiply accumulate operations
-    if ( control_state == MULT_STORE )
-        begin
-        reg_write_sel_nxt     = 3'd2; // multiply_out
-        multiply_function_nxt = o_multiply_function;
-        
-        if ( type == MULT ) // 32-bit
-            reg_bank_wsel_nxt      = instruction[19:16]; // Rd
-        else  // 64-bit / Long
-            reg_bank_wsel_nxt      = instruction[15:12]; // RdLo
-            
-        if ( instruction[20] )  // the 'S' bit
-            begin
-            status_bits_sel_nxt       = 3'd4; // { multiply_flags, status_bits_flags[1:0] } 
-            status_bits_flags_wen_nxt = 1'd1;
-            end
-        end
-        
-        // Add lower 32 bits to multiplication product
-    if ( control_state == MULT_ACCUMU )
-        begin
-        multiply_function_nxt = o_multiply_function;
-        pc_wen_nxt            = 1'd0;  // hold current PC value
-        address_sel_nxt       = 4'd3;  // pc  (not pc + 4)
-        end
-                
-    // swp - do write request in 2nd cycle
-    if ( control_state == SWAP_WRITE && instruction_execute )
-        begin
-        barrel_shift_data_sel_nxt       = 2'd2; // Shift value from Rm register
-        address_sel_nxt                 = 4'd4; // Rn
-        write_data_wen_nxt              = 1'd1;
-        data_access_exec_nxt            = 1'd1; // indicate that its a data read or write, 
-                                                // rather than an instruction fetch
-        
-        if ( instruction[22] )
-            byte_enable_sel_nxt = 2'd1;         // Save byte
-            
-        if ( instruction_execute )                         // conditional execution state
-            pc_wen_nxt                  = 1'd0; // hold current PC value
-            
-        // Save the next instruction to execute later
-        // Do this even if this instruction does not execute because of Condition
-        pre_fetch_instruction_wen   = 1'd1;
-        
-        end
-
-           
-    // swp - receive read response in 3rd cycle
-    if ( control_state == SWAP_WAIT1 ) 
-        begin
-        barrel_shift_data_sel_nxt   = 2'd1;  // load word from memory
-        barrel_shift_amount_sel_nxt = 2'd3;  // shift by address[1:0] x 8
-        
-        // shift needed
-        if ( i_execute_address[1:0] != 2'd0 )
-            barrel_shift_function_nxt = ROR;
-        
-        if ( instruction_execute ) // conditional execution state
-            begin
-            address_sel_nxt             = 4'd3; // pc  (not pc + 4)
-            pc_wen_nxt                  = 1'd0; // hold current PC value
-            end
-            
-        // load a byte            
-        if ( instruction[22] )
-            alu_out_sel_nxt = 4'd3;  // zero_extend8
-        
-        if ( !dabt )
-            begin    
-            // Check is the load destination is the PC
-            if ( instruction[15:12]  == 4'd15 )
-                begin
-                pc_sel_nxt      = 2'd1; // alu_out
-                address_sel_nxt = 4'd1; // alu_out
-                end
-            else                     
-                reg_bank_wsel_nxt = instruction[15:12];
-            end
-        end
-        
-    // 1 cycle delay for Co-Processor Register access
-    if ( control_state == COPRO_WAIT && instruction_execute )
-        begin
-        pre_fetch_instruction_wen = 1'd1;
-        
-        if ( instruction[20] ) // mrc instruction
-            begin
-            // Check is the load destination is the PC
-            if ( instruction[15:12]  == 4'd15 )
-                begin
-                // If r15 is specified for <Rd>, the condition code flags are 
-                // updated instead of a general-purpose register.
-                status_bits_sel_nxt           = 3'd3;  // i_copro_data
-                status_bits_flags_wen_nxt     = 1'd1;
-                
-                // Can't change these in USR mode
-                if ( i_execute_status_bits[1:0] != USR )
-                   begin
-                   status_bits_mode_wen_nxt      = 1'd1;
-                   status_bits_irq_mask_wen_nxt  = 1'd1;
-                   status_bits_firq_mask_wen_nxt = 1'd1;
-                   end
-                end
-            else                     
-                reg_bank_wsel_nxt = instruction[15:12];
-                        
-            reg_write_sel_nxt = 3'd5;     // i_copro_data
-            end
-        else // mcr instruction
-            begin
-            copro_operation_nxt      = 2'd2;  // Register transfer to Co-Processor 
-            end 
-        end
-        
-
-    // Have just changed the status_bits mode but this
-    // creates a 1 cycle gap with the old mode
-    // coming back from execute into instruction_decode
-    // So squash that old mode value during this
-    // cycle of the interrupt transition    
-    if ( control_state == INT_WAIT1 ) 
-        status_bits_mode_nxt            = o_status_bits_mode;   // Supervisor mode
-
-    end
-
-
-// Speed up the long path from u_decode/o_read_data to u_register_bank/r8_firq
-// This pre-encodes the firq_s3 signal thats used in u_register_bank
-assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ;
-
-
-// ========================================================
-// Next State Logic
-// ========================================================
-
-// this replicates the current value of the execute signal in the execute stage
-assign instruction_execute = conditional_execute ( o_condition, i_execute_status_bits[31:28] );
-
-assign instruction_valid = (control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
-                     // when last instruction was multi-cycle instruction but did not execute
-                     // because condition was false then act like you're in the execute state
-                    (!instruction_execute && (control_state == PC_STALL1    || 
-                                              control_state == MEM_WAIT1    ||
-                                              control_state == COPRO_WAIT   ||
-                                              control_state == SWAP_WRITE   ||
-                                              control_state == MULT_PROC1   ||
-                                              control_state == MTRANS_EXEC1 ||
-                                              control_state == MTRANS_EXEC3 ||
-                                              control_state == MTRANS_EXEC3B  ) );
-
-
- always @*
-    begin
-    // default is to hold the current state
-    control_state_nxt = control_state;
-    
-    // Note: The order is important here
-    if ( control_state == RST_WAIT1 )     control_state_nxt = RST_WAIT2;
-    if ( control_state == RST_WAIT2 )     control_state_nxt = EXECUTE;
-    if ( control_state == INT_WAIT1 )     control_state_nxt = INT_WAIT2;
-    if ( control_state == INT_WAIT2 )     control_state_nxt = EXECUTE;
-    if ( control_state == COPRO_WAIT )    control_state_nxt = PRE_FETCH_EXEC;
-    if ( control_state == PC_STALL1 )     control_state_nxt = PC_STALL2;
-    if ( control_state == PC_STALL2 )     control_state_nxt = EXECUTE; 
-    if ( control_state == SWAP_WRITE )    control_state_nxt = SWAP_WAIT1; 
-    if ( control_state == SWAP_WAIT1 )    control_state_nxt = SWAP_WAIT2; 
-    if ( control_state == MULT_STORE )    control_state_nxt = PRE_FETCH_EXEC;  
-    if ( control_state == MTRANS5_ABORT ) control_state_nxt = PRE_FETCH_EXEC;
-
-    if ( control_state == MEM_WAIT1 )
-        control_state_nxt = MEM_WAIT2;
-
-    if ( control_state == MEM_WAIT2   || 
-        control_state == SWAP_WAIT2    )
-        begin
-        if ( write_pc ) // writing to the PC!! 
-            control_state_nxt = PC_STALL1;
-        else
-            control_state_nxt = PRE_FETCH_EXEC;
-        end
-        
-    if ( control_state == MTRANS_EXEC1 )  
-        begin 
-        if (mtrans_instruction_nxt[15:0] != 16'd0)
-            control_state_nxt = MTRANS_EXEC2;
-        else   // if the register list holds a single register 
-            control_state_nxt = MTRANS_EXEC3;
-        end
-        
-        // Stay in State MTRANS_EXEC2 until the full list of registers to
-        // load or store has been processed
-    if ( control_state == MTRANS_EXEC2 && mtrans_num_registers == 5'd1 )
-        control_state_nxt = MTRANS_EXEC3;
-        
-    if ( control_state == MTRANS_EXEC3 )     control_state_nxt = MTRANS_EXEC4; 
-    
-    if ( control_state == MTRANS_EXEC3B )    control_state_nxt = MTRANS_EXEC4;
-
-    if ( control_state == MTRANS_EXEC4  )
-        begin
-        if ( dabt ) // data abort
-            control_state_nxt = MTRANS5_ABORT;
-        else if (write_pc) // writing to the PC!! 
-            control_state_nxt = PC_STALL1;
-        else
-            control_state_nxt = PRE_FETCH_EXEC;
-        end
-    
-    if ( control_state == MULT_PROC1 )
-        begin
-        if (!instruction_execute)
-            control_state_nxt = PRE_FETCH_EXEC;
-        else
-            control_state_nxt = MULT_PROC2;
-        end
-        
-    if ( control_state == MULT_PROC2 )
-        begin
-        if ( i_multiply_done )
-            if      ( o_multiply_function[1] )  // Accumulate ?
-                control_state_nxt = MULT_ACCUMU;
-            else    
-                control_state_nxt = MULT_STORE;
-        end
-        
-        
-    if ( control_state == MULT_ACCUMU )
-        begin
-        control_state_nxt = MULT_STORE;
-        end
-        
-            
-    // This should come at the end, so that conditional execution works
-    // correctly
-    if ( instruction_valid )
-        begin
-        // default is to stay in execute state, or to move into this
-        // state from a conditional execute state
-        control_state_nxt = EXECUTE;
-        
-        if ( mem_op )  // load or store word or byte
-             control_state_nxt = MEM_WAIT1;
-        if ( write_pc )     
-             control_state_nxt = PC_STALL1;
-        if ( type == MTRANS )
-            begin
-            if ( mtrans_num_registers != 5'd0 )
-                begin
-                // check for LDM/STM of a single register
-                if ( mtrans_num_registers == 5'd1 )
-                    control_state_nxt = MTRANS_EXEC3B;
-                else
-                    control_state_nxt = MTRANS_EXEC1;
-                end
-            else    
-                control_state_nxt = MTRANS_EXEC3;
-            end
-
-        if ( type == MULT )
-                control_state_nxt = MULT_PROC1;
-
-        if ( type == SWAP )        
-                control_state_nxt = SWAP_WRITE;
-
-        if ( type == CORTRANS && !und_request )        
-                control_state_nxt = COPRO_WAIT;
-                
-         // interrupt overrides everything else so its last       
-        if ( interrupt )        
-                control_state_nxt = INT_WAIT1;
-        end
-    end
-
-
-// ========================================================
-// Register Update
-// ========================================================
-always @ ( posedge i_clk )
-    if (!i_fetch_stall) 
-        begin                                                                                                                 
-        o_read_data                 <= i_read_data;
-        o_read_data_alignment       <= {i_execute_address[1:0], 3'd0};  
-        abt_address_reg             <= i_execute_address;
-        iabt_reg                    <= i_iabt;
-        adex_reg                    <= i_adex;
-        abt_status_reg              <= i_abt_status;
-        o_status_bits_mode          <= status_bits_mode_nxt;
-        o_status_bits_irq_mask      <= status_bits_irq_mask_nxt;
-        o_status_bits_firq_mask     <= status_bits_firq_mask_nxt;
-        o_imm32                     <= imm32_nxt;
-        o_imm_shift_amount          <= imm_shift_amount_nxt;
-        o_shift_imm_zero            <= shift_imm_zero_nxt;
-        
-                                        // when have an interrupt, execute the interrupt operation
-                                        // unconditionally in the execute stage
-                                        // ensures that status_bits register gets updated correctly
-                                        // Likewise when in middle of multi-cycle instructions
-                                        // execute them unconditionally
-        o_condition                 <= instruction_valid && !interrupt ? condition_nxt : AL;
-        o_exclusive_exec            <= exclusive_exec_nxt;
-        o_data_access_exec          <= data_access_exec_nxt;
-        
-        o_rm_sel                    <= o_rm_sel_nxt;
-        o_rds_sel                   <= o_rds_sel_nxt;
-        o_rn_sel                    <= o_rn_sel_nxt;
-        o_barrel_shift_amount_sel   <= barrel_shift_amount_sel_nxt;
-        o_barrel_shift_data_sel     <= barrel_shift_data_sel_nxt;
-        o_barrel_shift_function     <= barrel_shift_function_nxt;
-        o_alu_function              <= alu_function_nxt;
-        o_multiply_function         <= multiply_function_nxt;
-        o_interrupt_vector_sel      <= next_interrupt;
-        o_address_sel               <= address_sel_nxt;
-        o_pc_sel                    <= pc_sel_nxt;
-        o_byte_enable_sel           <= byte_enable_sel_nxt;
-        o_status_bits_sel           <= status_bits_sel_nxt;
-        o_reg_write_sel             <= reg_write_sel_nxt;
-        o_user_mode_regs_load       <= user_mode_regs_load_nxt;
-        o_firq_not_user_mode        <= firq_not_user_mode_nxt;
-        o_write_data_wen            <= write_data_wen_nxt;
-        o_base_address_wen          <= base_address_wen_nxt;
-        o_pc_wen                    <= pc_wen_nxt;
-        o_reg_bank_wsel             <= reg_bank_wsel_nxt;
-        o_reg_bank_wen              <= decode ( reg_bank_wsel_nxt );
-        o_status_bits_flags_wen     <= status_bits_flags_wen_nxt;
-        o_status_bits_mode_wen      <= status_bits_mode_wen_nxt;
-        o_status_bits_irq_mask_wen  <= status_bits_irq_mask_wen_nxt;
-        o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt;
-        
-        o_copro_opcode1             <= instruction[23:21];
-        o_copro_opcode2             <= instruction[7:5];
-        o_copro_crn                 <= instruction[19:16];
-        o_copro_crm                 <= instruction[3:0];
-        o_copro_num                 <= instruction[11:8];
-        o_copro_operation           <= copro_operation_nxt;
-        o_copro_write_data_wen      <= copro_write_data_wen_nxt;
-        mtrans_r15                  <= mtrans_r15_nxt;
-        restore_base_address        <= restore_base_address_nxt;
-        control_state               <= control_state_nxt;
-        mtrans_reg_d1               <= mtrans_reg;
-        mtrans_reg_d2               <= mtrans_reg_d1;
-        end
-
-
-
-always @ ( posedge i_clk )
-    if ( !i_fetch_stall )
-        begin
-        // sometimes this is a pre-fetch instruction
-        // e.g. two ldr instructions in a row. The second ldr will be saved
-        // to the pre-fetch instruction register
-        // then when its decoded, a copy is saved to the saved_current_instruction
-        // register
-        if      (type == MTRANS)
-            begin           
-            saved_current_instruction              <= mtrans_instruction_nxt;
-            saved_current_instruction_iabt         <= instruction_iabt;
-            saved_current_instruction_adex         <= instruction_adex;
-            saved_current_instruction_address      <= instruction_address;
-            saved_current_instruction_iabt_status  <= instruction_iabt_status;
-            end
-        else if (saved_current_instruction_wen) 
-            begin           
-            saved_current_instruction              <= instruction;
-            saved_current_instruction_iabt         <= instruction_iabt;
-            saved_current_instruction_adex         <= instruction_adex;
-            saved_current_instruction_address      <= instruction_address;
-            saved_current_instruction_iabt_status  <= instruction_iabt_status;
-            end
-
-        if      (pre_fetch_instruction_wen)     
-            begin
-            pre_fetch_instruction                  <= o_read_data;      
-            pre_fetch_instruction_iabt             <= iabt_reg; 
-            pre_fetch_instruction_adex             <= adex_reg; 
-            pre_fetch_instruction_address          <= abt_address_reg; 
-            pre_fetch_instruction_iabt_status      <= abt_status_reg; 
-            end       
-        end
-
-
-        
-always @ ( posedge i_clk )
-    if ( !i_fetch_stall )
-        begin
-        irq   <= i_irq;  
-        firq  <= i_firq; 
-        
-        if ( control_state == INT_WAIT1 && o_status_bits_mode == SVC )
-            begin
-            dabt_reg  <= 1'd0;
-            end
-        else
-            begin
-            dabt_reg  <= dabt_reg || i_dabt;  
-            end
-        
-        dabt_reg_d1  <= dabt_reg;   
-        end  
-
-assign dabt = dabt_reg || i_dabt;
-
-// ========================================================
-// Decompiler for debugging core - not synthesizable
-// ========================================================
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_decompile.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_decompile.v
deleted file mode 100644
index e06a930..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_decompile.v
+++ /dev/null
@@ -1,308 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Decompiler for Amber 2 Core                                  //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Decompiler for debugging core - not synthesizable           //
-//  Shows instruction in Execute Stage at last clock of         //
-//  the instruction                                             //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Global testbench defines                                    //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains a set of defines for each module so if the module  //
-//  hierarchy changes, hierarchical references to signals       //
-//  will still work as long as this file is updated.            //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-// ---------------------------------------------------------------
-// Module hierarchy defines
-// ---------------------------------------------------------------
-
-    
-
-
-        // ---------------------------------------------------------------
-
-
-
-// Simplified Main Memory Model
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Amber Configuration and Debug for the AMber 2 Core          //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains a set of defines used to configure and debug       //
-//  the Amber core                                              //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Cache Ways
-// Changing this parameter is the recommended
-// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported.
-//   2 ways -> 8KB  cache
-//   3 ways -> 12KB cache
-//   4 ways -> 16KB cache
-//   8 ways -> 32KB cache
-
-// Use ram-based register bank implementation
-// `define A23_RAM_REGISTER_BANK
-
-// --------------------------------------------------------------------
-// Debug switches 
-// --------------------------------------------------------------------
-
-// Enable the decompiler. The default output file is amber.dis
-//`define A23_DECOMPILE
-
-// Co-processor 15 debug. Registers in here control the cache
-//`define A23_COPRO15_DEBUG
-
-// Cache debug
-//`define A23_CACHE_DEBUG
-
-// --------------------------------------------------------------------
-
-
-// --------------------------------------------------------------------
-// File Names
-// --------------------------------------------------------------------
-    
-
-
-module a23_decompile
-(
-input                       i_clk,
-input                       i_fetch_stall,
-input       [31:0]          i_instruction,
-input                       i_instruction_valid,
-input                       i_instruction_undefined,
-input                       i_instruction_execute,
-input       [2:0]           i_interrupt,            // non-zero value means interrupt triggered
-input                       i_interrupt_state,
-input       [31:0]          i_instruction_address,
-input       [1:0]           i_pc_sel,
-input                       i_pc_wen
-
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
-        
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_execute.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_execute.v
deleted file mode 100644
index ae6c24b..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_execute.v
+++ /dev/null
@@ -1,914 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Execute stage of Amber 2 Core                               //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Executes instructions. Instantiates the register file, ALU  //
-//  multiplication unit and barrel shifter. This stage is       //
-//  relitively simple. All the complex stuff is done in the     //
-//  decode stage.                                               //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Amber Configuration and Debug for the AMber 2 Core          //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains a set of defines used to configure and debug       //
-//  the Amber core                                              //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Cache Ways
-// Changing this parameter is the recommended
-// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported.
-//   2 ways -> 8KB  cache
-//   3 ways -> 12KB cache
-//   4 ways -> 16KB cache
-//   8 ways -> 32KB cache
-
-// Use ram-based register bank implementation
-// `define A23_RAM_REGISTER_BANK
-
-// --------------------------------------------------------------------
-// Debug switches 
-// --------------------------------------------------------------------
-
-// Enable the decompiler. The default output file is amber.dis
-//`define A23_DECOMPILE
-
-// Co-processor 15 debug. Registers in here control the cache
-//`define A23_COPRO15_DEBUG
-
-// Cache debug
-//`define A23_CACHE_DEBUG
-
-// --------------------------------------------------------------------
-
-
-// --------------------------------------------------------------------
-// File Names
-// --------------------------------------------------------------------
-    
-
-
-module a23_execute (
-
-input                       i_clk,
-input       [31:0]          i_read_data,
-input       [4:0]           i_read_data_alignment,  // 2 LSBs of address in [4:3], appended 
-                                                    // with 3 zeros
-input       [31:0]          i_copro_read_data,      // From Co-Processor, to either Register 
-                                                    // or Memory
-input                       i_data_access_exec,     // from Instruction Decode stage
-                                                    // high means the memory access is a read 
-                                                    // read or write, low for instruction
-
-output reg  [31:0]          o_copro_write_data = 'd0,
-output reg  [31:0]          o_write_data = 'd0,
-output reg  [31:0]          o_address = 32'hdead_dead,
-output reg                  o_adex = 'd0,           // Address Exception
-output reg                  o_address_valid = 'd0,  // Prevents the reset address value being a 
-                                                    // wishbone access
-output      [31:0]          o_address_nxt,          // un-registered version of address to the 
-                                                    // cache rams address ports
-output reg                  o_priviledged = 'd0,    // Priviledged access
-output reg                  o_exclusive = 'd0,      // swap access
-output reg                  o_write_enable = 'd0,
-output reg  [3:0]           o_byte_enable = 'd0,
-output reg                  o_data_access = 'd0,    // To Fetch stage. high = data fetch, 
-                                                    // low = instruction fetch
-output      [31:0]          o_status_bits,          // Full PC will all status bits, but PC part zero'ed out
-output                      o_multiply_done,
-
-
-// --------------------------------------------------
-// Control signals from Instruction Decode stage
-// --------------------------------------------------
-input                       i_fetch_stall,          // stall all stages of the cpu at the same time
-input      [1:0]            i_status_bits_mode,
-input                       i_status_bits_irq_mask,
-input                       i_status_bits_firq_mask,
-input      [31:0]           i_imm32,
-input      [4:0]            i_imm_shift_amount,
-input                       i_shift_imm_zero,
-input      [3:0]            i_condition,
-input                       i_exclusive_exec,       // swap access
-
-input      [3:0]            i_rm_sel,
-input      [3:0]            i_rds_sel,
-input      [3:0]            i_rn_sel,
-input      [3:0]            i_rm_sel_nxt,
-input      [3:0]            i_rds_sel_nxt,
-input      [3:0]            i_rn_sel_nxt,
-input      [1:0]            i_barrel_shift_amount_sel,
-input      [1:0]            i_barrel_shift_data_sel,
-input      [1:0]            i_barrel_shift_function,
-input      [8:0]            i_alu_function,
-input      [1:0]            i_multiply_function,
-input      [2:0]            i_interrupt_vector_sel,
-input      [3:0]            i_address_sel,
-input      [1:0]            i_pc_sel,
-input      [1:0]            i_byte_enable_sel,
-input      [2:0]            i_status_bits_sel,
-input      [2:0]            i_reg_write_sel,
-input                       i_user_mode_regs_load,
-input                       i_user_mode_regs_store_nxt,
-input                       i_firq_not_user_mode,
-input                       i_firq_not_user_mode_nxt,
-
-input                       i_write_data_wen,
-input                       i_base_address_wen,     // save LDM base address register, 
-                                                    // in case of data abort
-input                       i_pc_wen,
-input      [14:0]           i_reg_bank_wen,
-input      [3:0]            i_reg_bank_wsel,
-input                       i_status_bits_flags_wen,
-input                       i_status_bits_mode_wen,
-input                       i_status_bits_irq_mask_wen,
-input                       i_status_bits_firq_mask_wen,
-input                       i_copro_write_data_wen
-
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Functions for Amber 2 Core                                  //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Functions used in more than one module                      //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// ========================================================
-// PC Filter - Remove the status bits 
-// ========================================================
-function [31:0] pcf;
-input [31:0] pc_reg;
-    begin
-    pcf = {6'd0, pc_reg[25:2], 2'd0};
-    end
-endfunction
-
-
-// ========================================================
-// 4-bit to 16-bit 1-hot decode
-// ========================================================
-function [14:0] decode;
-input [3:0] reg_sel;
-begin
-case ( reg_sel )
-    4'h0:    decode = 15'h0001;
-    4'h1:    decode = 15'h0002;
-    4'h2:    decode = 15'h0004;
-    4'h3:    decode = 15'h0008;
-    4'h4:    decode = 15'h0010;
-    4'h5:    decode = 15'h0020;
-    4'h6:    decode = 15'h0040;
-    4'h7:    decode = 15'h0080;
-    4'h8:    decode = 15'h0100;
-    4'h9:    decode = 15'h0200;
-    4'ha:    decode = 15'h0400;
-    4'hb:    decode = 15'h0800;
-    4'hc:    decode = 15'h1000;
-    4'hd:    decode = 15'h2000;
-    4'he:    decode = 15'h4000;
-    default: decode = 15'h0000;
-endcase
-end
-endfunction
-
-
-// ========================================================
-// Convert Stats Bits Mode to one-hot encoded version
-// ========================================================
-function [3:0] oh_status_bits_mode;
-input [1:0] fn_status_bits_mode;
-begin
-oh_status_bits_mode = 
-    fn_status_bits_mode == SVC  ? 1'd1 << OH_SVC  :
-    fn_status_bits_mode == IRQ  ? 1'd1 << OH_IRQ  :
-    fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ :
-                                  1'd1 << OH_USR  ;
-end
-endfunction
-
-// ========================================================
-// Convert mode into ascii name
-// ========================================================
-function [(14*8)-1:0]  mode_name;
-input [4:0] mode;
-begin
-
-mode_name    = mode == USR  ? "User          " :
-               mode == SVC  ? "Supervisor    " :
-               mode == IRQ  ? "Interrupt     " :
-               mode == FIRQ ? "Fast Interrupt" :
-                              "UNKNOWN       " ;
-end
-endfunction
-
-
-// ========================================================
-// Conditional Execution Function
-// ========================================================
-// EQ Z set
-// NE Z clear
-// CS C set
-// CC C clear
-// MI N set
-// PL N clear
-// VS V set
-// VC V clear
-// HI C set and Z clear
-// LS C clear or Z set
-// GE N == V
-// LT N != V
-// GT Z == 0,N == V
-// LE Z == 1 or N != V
-// AL Always (unconditional)
-// NV Never
-
-function conditional_execute;
-input [3:0] condition;
-input [3:0] flags;
-begin
-conditional_execute  
-               = ( condition == AL                                        ) ||
-                 ( condition == EQ  &&  flags[2]                          ) ||
-                 ( condition == NE  && !flags[2]                          ) ||
-                 ( condition == CS  &&  flags[1]                          ) ||
-                 ( condition == CC  && !flags[1]                          ) ||
-                 ( condition == MI  &&  flags[3]                          ) ||
-                 ( condition == PL  && !flags[3]                          ) ||
-                 ( condition == VS  &&  flags[0]                          ) ||
-                 ( condition == VC  && !flags[0]                          ) ||
-            
-                 ( condition == HI  &&    flags[1] && !flags[2]           ) ||
-                 ( condition == LS  &&  (!flags[1] ||  flags[2])          ) ||
-            
-                 ( condition == GE  &&  flags[3] == flags[0]              ) ||
-                 ( condition == LT  &&  flags[3] != flags[0]              ) ||
-
-                 ( condition == GT  &&  !flags[2] && flags[3] == flags[0] ) ||
-                 ( condition == LE  &&  (flags[2] || flags[3] != flags[0])) ;
-            
-end
-endfunction
-
-
-// ========================================================
-// Log 2
-// ========================================================
-
-function [31:0] log2;
-input    [31:0] num;
-integer i;
-integer out;
-begin
-  out = 32'd0;
-  for (i=0; i<30; i=i+1)
-    if ((2**i > num) && (out == 0))
-      out = i-1;
-  log2 = out;
-end
-endfunction
-
-// ========================================================
-// Internal signals
-// ========================================================
-wire [31:0]         write_data_nxt;
-wire [3:0]          byte_enable_nxt;
-wire [31:0]         pc_plus4;
-wire [31:0]         pc_minus4;
-wire [31:0]         address_plus4;
-wire [31:0]         alu_plus4;
-wire [31:0]         rn_plus4;
-wire [31:0]         alu_out;
-wire [3:0]          alu_flags;
-wire [31:0]         rm;
-wire [31:0]         rs;
-wire [31:0]         rd;
-wire [31:0]         rn;
-wire [31:0]         pc;
-wire [31:0]         pc_nxt;
-wire                write_enable_nxt;
-wire [31:0]         interrupt_vector;
-wire [7:0]          shift_amount;
-wire [31:0]         barrel_shift_in;
-wire [31:0]         barrel_shift_out;
-wire                barrel_shift_carry;
-
-wire [3:0]          status_bits_flags_nxt;
-reg  [3:0]          status_bits_flags = 'd0;
-wire [1:0]          status_bits_mode_nxt;
-wire [1:0]          status_bits_mode_nr;
-reg  [1:0]          status_bits_mode = SVC;
-                    // raw rs select
-wire [1:0]          status_bits_mode_rds_nxt;
-wire [1:0]          status_bits_mode_rds_nr;
-reg  [1:0]          status_bits_mode_rds;
-                    // one-hot encoded rs select
-wire [3:0]          status_bits_mode_rds_oh_nxt;
-reg  [3:0]          status_bits_mode_rds_oh = 1'd1 << OH_SVC;
-wire                status_bits_mode_rds_oh_update;
-wire                status_bits_irq_mask_nxt;
-reg                 status_bits_irq_mask = 1'd1;
-wire                status_bits_firq_mask_nxt;
-reg                 status_bits_firq_mask = 1'd1;
-
-wire                execute;           // high when condition execution is true
-wire [31:0]         reg_write_nxt;
-wire                pc_wen;
-wire [14:0]         reg_bank_wen;
-wire [3:0]          reg_bank_wsel;
-wire [31:0]         multiply_out;
-wire [1:0]          multiply_flags;
-reg  [31:0]         base_address = 'd0;    // Saves base address during LDM instruction in 
-                                           // case of data abort
-
-wire                priviledged_nxt;      
-wire                priviledged_update;
-wire                address_update;
-wire                base_address_update;
-wire                write_data_update;
-wire                copro_write_data_update;
-wire                byte_enable_update;
-wire                data_access_update;
-wire                write_enable_update;
-wire                exclusive_update;
-wire                status_bits_flags_update;
-wire                status_bits_mode_update;
-wire                status_bits_irq_mask_update;
-wire                status_bits_firq_mask_update;
-
-wire [31:0]         alu_out_pc_filtered;
-wire                adex_nxt;
-
-// ========================================================
-// Status Bits in PC register
-// ========================================================
-wire [1:0] status_bits_out;
-assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1) ? 
-                            alu_out[1:0] : status_bits_mode ;
-
-
-assign o_status_bits = {   status_bits_flags,           // 31:28
-                           status_bits_irq_mask,        // 7
-                           status_bits_firq_mask,       // 6
-                           24'd0,
-                           status_bits_out};          // 1:0 = mode
-
-// ========================================================
-// Status Bits Select
-// ========================================================
-assign status_bits_flags_nxt     = i_status_bits_sel == 3'd0 ? alu_flags                           :
-                                   i_status_bits_sel == 3'd1 ? alu_out          [31:28]            :
-                                   i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28]            :
-                                   // 4 = update flags after a multiply operation
-                                                        { multiply_flags, status_bits_flags[1:0] } ;
-
-assign status_bits_mode_nxt      = i_status_bits_sel == 3'd0 ? i_status_bits_mode       :
-                                   i_status_bits_sel == 3'd1 ? alu_out            [1:0] :
-                                                               i_copro_read_data  [1:0] ;
-
-
-// Used for the Rds output of register_bank - this special version of
-// status_bits_mode speeds up the critical path from status_bits_mode through the
-// register_bank, barrel_shifter and alu. It moves a mux needed for the
-// i_user_mode_regs_store_nxt signal back into the previous stage -
-// so its really part of the decode stage even though the logic is right here
-// In addition the signal is one-hot encoded to further speed up the logic
-// Raw version is also kept for ram-based register bank implementation.
-
-assign status_bits_mode_rds_nxt  = i_user_mode_regs_store_nxt ? USR                  :
-                                   status_bits_mode_update    ? status_bits_mode_nxt :
-                                                                status_bits_mode     ;
-
-assign status_bits_mode_rds_oh_nxt    = oh_status_bits_mode(status_bits_mode_rds_nxt);
-
-
-assign status_bits_irq_mask_nxt  = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask      :
-                                   i_status_bits_sel == 3'd1 ? alu_out                [27] :
-                                                               i_copro_read_data      [27] ;
-                            
-assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask     :
-                                   i_status_bits_sel == 3'd1 ? alu_out                [26] :
-                                                               i_copro_read_data      [26] ;
-
-
-
-// ========================================================
-// Adders
-// ========================================================
-assign pc_plus4      = pc        + 32'd4;
-assign pc_minus4     = pc        - 32'd4;
-assign address_plus4 = o_address + 32'd4;
-assign alu_plus4     = alu_out   + 32'd4;
-assign rn_plus4      = rn        + 32'd4;
-
-// ========================================================
-// Barrel Shift Amount Select
-// ========================================================
-// An immediate shift value of 0 is translated into 32
-assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0 :
-                      i_barrel_shift_amount_sel == 2'd1 ? rs[7:0]                       :
-                      i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount    } :
-                                                          {3'd0, i_read_data_alignment } ;
-
-// ========================================================
-// Barrel Shift Data Select
-// ========================================================
-assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32       :
-                         i_barrel_shift_data_sel == 2'd1 ? i_read_data   :
-                                                           rm            ;
-                            
-// ========================================================
-// Interrupt vector Select
-// ========================================================
-
-assign interrupt_vector = // Reset vector
-                          (i_interrupt_vector_sel == 3'd0) ? 32'h00000000 :  
-                          // Data abort interrupt vector                 
-                          (i_interrupt_vector_sel == 3'd1) ? 32'h00000010 :
-                          // Fast interrupt vector  
-                          (i_interrupt_vector_sel == 3'd2) ? 32'h0000001c :
-                          // Regular interrupt vector
-                          (i_interrupt_vector_sel == 3'd3) ? 32'h00000018 :
-                          // Prefetch abort interrupt vector
-                          (i_interrupt_vector_sel == 3'd5) ? 32'h0000000c :
-                          // Undefined instruction interrupt vector
-                          (i_interrupt_vector_sel == 3'd6) ? 32'h00000004 :
-                          // Software (SWI) interrupt vector
-                          (i_interrupt_vector_sel == 3'd7) ? 32'h00000008 :
-                          // Default is the address exception interrupt
-                                                             32'h00000014 ;
-
-
-// ========================================================
-// Address Select
-// ========================================================
-
-// If rd is the pc, then seperate the address bits from the status bits for
-// generating the next address to fetch
-assign alu_out_pc_filtered = pc_wen && i_pc_sel == 2'd1 ? pcf(alu_out) : alu_out;
-
-// if current instruction does not execute because it does not meet the condition
-// then address advances to next instruction
-assign o_address_nxt = (!execute)              ? pc_plus4              : 
-                       (i_address_sel == 4'd0) ? pc_plus4              :
-                       (i_address_sel == 4'd1) ? alu_out_pc_filtered   :
-                       (i_address_sel == 4'd2) ? interrupt_vector      :
-                       (i_address_sel == 4'd3) ? pc                    :
-                       (i_address_sel == 4'd4) ? rn                    :
-                       (i_address_sel == 4'd5) ? address_plus4         :  // MTRANS address incrementer
-                       (i_address_sel == 4'd6) ? alu_plus4             :  // MTRANS decrement after
-                                                 rn_plus4              ;  // MTRANS increment before
-
-// Data accesses use 32-bit address space, but instruction
-// accesses are restricted to 26 bit space
-assign adex_nxt      = |o_address_nxt[31:26] && !i_data_access_exec;
-
-// ========================================================
-// Program Counter Select
-// ========================================================
-// If current instruction does not execute because it does not meet the condition
-// then PC advances to next instruction
-assign pc_nxt = (!execute)       ? pc_plus4              :
-                i_pc_sel == 2'd0 ? pc_plus4              :
-                i_pc_sel == 2'd1 ? alu_out               :
-                                   interrupt_vector      ;
-
-
-// ========================================================
-// Register Write Select
-// ========================================================
-wire [31:0] save_int_pc;
-wire [31:0] save_int_pc_m4;
-
-assign save_int_pc    = { status_bits_flags, 
-                          status_bits_irq_mask, 
-                          status_bits_firq_mask, 
-                          pc[25:2], 
-                          status_bits_mode      };
-
-
-assign save_int_pc_m4 = { status_bits_flags, 
-                          status_bits_irq_mask, 
-                          status_bits_firq_mask, 
-                          pc_minus4[25:2], 
-                          status_bits_mode      };
-
-
-assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out               :
-                       // save pc to lr on an interrupt                    
-                       i_reg_write_sel == 3'd1 ? save_int_pc_m4        :
-                       // to update Rd at the end of Multiplication
-                       i_reg_write_sel == 3'd2 ? multiply_out          :
-                       i_reg_write_sel == 3'd3 ? o_status_bits         :
-                       i_reg_write_sel == 3'd5 ? i_copro_read_data     :  // mrc
-                       i_reg_write_sel == 3'd6 ? base_address          :
-                                                 save_int_pc           ;  
-
-
-// ========================================================
-// Byte Enable Select
-// ========================================================
-assign byte_enable_nxt = i_byte_enable_sel == 2'd0 ? 4'b1111 :  // word write
-                         i_byte_enable_sel == 2'd2 ?            // halfword write
-                         ( o_address_nxt[1] == 1'd0 ? 4'b0011 : 
-                                                      4'b1100 ) :
-                           
-                         o_address_nxt[1:0] == 2'd0 ? 4'b0001 :  // byte write
-                         o_address_nxt[1:0] == 2'd1 ? 4'b0010 :
-                         o_address_nxt[1:0] == 2'd2 ? 4'b0100 :
-                                                      4'b1000 ;
-
-
-// ========================================================
-// Write Data Select
-// ========================================================
-assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd            :
-                                                    {4{rd[ 7:0]}} ;
-
-
-// ========================================================
-// Conditional Execution
-// ========================================================
-assign execute = conditional_execute ( i_condition, status_bits_flags );
-            
-// allow the PC to increment to the next instruction when current
-// instruction does not execute
-assign pc_wen       = i_pc_wen || !execute;
-
-// only update register bank if current instruction executes
-assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
-
-assign reg_bank_wsel = {{4{~execute}} | i_reg_bank_wsel};
-
-
-// ========================================================
-// Priviledged output flag
-// ========================================================
-// Need to look at status_bits_mode_nxt so switch to priviledged mode
-// at the same time as assert interrupt vector address
-assign priviledged_nxt  = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ;
-
-
-// ========================================================
-// Write Enable
-// ========================================================
-// This must be de-asserted when execute is fault
-assign write_enable_nxt = execute && i_write_data_wen;
-
-
-// ========================================================
-// Register Update
-// ========================================================
-
-assign priviledged_update              = !i_fetch_stall;       
-assign data_access_update              = !i_fetch_stall && execute;
-assign write_enable_update             = !i_fetch_stall;
-assign write_data_update               = !i_fetch_stall && execute && i_write_data_wen;
-assign exclusive_update                = !i_fetch_stall && execute;
-assign address_update                  = !i_fetch_stall;
-assign byte_enable_update              = !i_fetch_stall && execute && i_write_data_wen;
-assign copro_write_data_update         = !i_fetch_stall && execute && i_copro_write_data_wen;
-
-assign base_address_update             = !i_fetch_stall && execute && i_base_address_wen; 
-assign status_bits_flags_update        = !i_fetch_stall && execute && i_status_bits_flags_wen;
-assign status_bits_mode_update         = !i_fetch_stall && execute && i_status_bits_mode_wen;
-assign status_bits_mode_rds_oh_update  = !i_fetch_stall;
-assign status_bits_irq_mask_update     = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
-assign status_bits_firq_mask_update    = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
-
-assign status_bits_mode_rds_nr         =  status_bits_mode_rds_oh_update ? status_bits_mode_rds_nxt :
-                                                                           status_bits_mode_rds     ;
-
-assign status_bits_mode_nr             =  status_bits_mode_update        ? status_bits_mode_nxt     :
-                                                                           status_bits_mode         ;
-
-always @( posedge i_clk )
-    begin                                                                                                             
-    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
-    o_exclusive             <= exclusive_update               ? i_exclusive_exec             : o_exclusive;
-    o_data_access           <= data_access_update             ? i_data_access_exec           : o_data_access;
-    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
-    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data; 
-    o_address               <= address_update                 ? o_address_nxt                : o_address;    
-    o_adex                  <= address_update                 ? adex_nxt                     : o_adex;    
-    o_address_valid         <= address_update                 ? 1'd1 : o_address_valid;
-    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
-    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data; 
-
-    base_address            <= base_address_update            ? rn                           : base_address;    
-
-    status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
-    status_bits_mode        <=  status_bits_mode_nr;
-    status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt  : status_bits_mode_rds_oh;
-    status_bits_mode_rds    <= status_bits_mode_rds_nr;
-    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
-    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
-    end
-
-
-// ========================================================
-// Instantiate Barrel Shift
-// ========================================================
-a23_barrel_shift u_barrel_shift  (
-    .i_in             ( barrel_shift_in           ),
-    .i_carry_in       ( status_bits_flags[1]      ),
-    .i_shift_amount   ( shift_amount              ),
-    .i_shift_imm_zero ( i_shift_imm_zero          ),
-    .i_function       ( i_barrel_shift_function   ),
-
-    .o_out            ( barrel_shift_out          ),
-    .o_carry_out      ( barrel_shift_carry        )
-);
-
-
-// ========================================================
-// Instantiate ALU
-// ========================================================
-a23_alu u_alu (
-    .i_a_in                 ( rn                    ),
-    .i_b_in                 ( barrel_shift_out      ),
-    .i_barrel_shift_carry   ( barrel_shift_carry    ),
-    .i_status_bits_carry    ( status_bits_flags[1]  ),
-    .i_function             ( i_alu_function        ),
-
-    .o_out                  ( alu_out               ),
-    .o_flags                ( alu_flags             )
-);
-
-
-// ========================================================
-// Instantiate Booth 64-bit Multiplier-Accumulator
-// ========================================================
-a23_multiply u_multiply (
-    .i_clk          ( i_clk                 ),
-    .i_fetch_stall  ( i_fetch_stall         ),
-    .i_a_in         ( rs                    ),
-    .i_b_in         ( rm                    ),
-    .i_function     ( i_multiply_function   ),
-    .i_execute      ( execute               ),
-    .o_out          ( multiply_out          ),
-    .o_flags        ( multiply_flags        ),  // [1] = N, [0] = Z
-    .o_done         ( o_multiply_done       )     
-);
-
-
-// ========================================================
-// Instantiate Register Bank
-// ========================================================
-a23_register_bank u_register_bank(
-    .i_clk                   ( i_clk                     ),
-    .i_fetch_stall           ( i_fetch_stall             ),
-    .i_rm_sel                ( i_rm_sel                  ),
-    .i_rds_sel               ( i_rds_sel                 ),
-    .i_rn_sel                ( i_rn_sel                  ),
-    .i_pc_wen                ( pc_wen                    ),
-    .i_reg_bank_wen          ( reg_bank_wen              ),
-    .i_pc                    ( pc_nxt[25:2]              ),
-    .i_reg                   ( reg_write_nxt             ),
-    .i_mode_idec             ( i_status_bits_mode        ),
-    .i_mode_exec             ( status_bits_mode          ),
-
-    .i_status_bits_flags     ( status_bits_flags         ),
-    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
-    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
-
-    // pre-encoded in decode stage to speed up long path
-    .i_firq_not_user_mode    ( i_firq_not_user_mode      ),
-    
-    // use one-hot version for speed, combine with i_user_mode_regs_store
-    .i_mode_rds_exec         ( status_bits_mode_rds_oh   ),  
-    
-    .i_user_mode_regs_load   ( i_user_mode_regs_load     ),
-    .o_rm                    ( rm                        ),
-    .o_rs                    ( rs                        ),
-    .o_rd                    ( rd                        ),
-    .o_rn                    ( rn                        ),
-    .o_pc                    ( pc                        )
-);
-
-// ========================================================
-// Debug - non-synthesizable code
-// ========================================================
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_fetch.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_fetch.v
deleted file mode 100644
index 93c8227..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_fetch.v
+++ /dev/null
@@ -1,331 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Fetch - Instantiates the fetch stage sub-modules of         //
-//  the Amber 2 Core                                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Instantiates the Cache and Wishbone I/F                     //
-//  Also contains a little bit of logic to decode memory        //
-//  accesses to decide if they are cached or not                //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module a23_fetch
-(
-input                       i_clk,
-
-input       [31:0]          i_address,
-input                       i_address_valid,
-input       [31:0]          i_address_nxt,      // un-registered version of address to the cache rams
-input       [31:0]          i_write_data,
-input                       i_write_enable,
-output       [31:0]         o_read_data,
-input                       i_priviledged,
-input                       i_exclusive,        // high for read part of swap access
-input       [3:0]           i_byte_enable,
-input                       i_data_access,      // high for data petch, low for instruction fetch
-input                       i_cache_enable,     // cache enable
-input                       i_cache_flush,      // cache flush
-input       [31:0]          i_cacheable_area,   // each bit corresponds to 2MB address space
-input                       i_system_rdy,
-output                      o_fetch_stall,      // when this is asserted all registers 
-                                                // in all 3 pipeline stages are held
-                                                // at their current values
-
-// Wishbone Master I/F
-output      [31:0]          o_wb_adr,
-output      [3:0]           o_wb_sel,
-output                      o_wb_we,
-input       [31:0]          i_wb_dat,
-output      [31:0]          o_wb_dat,
-output                      o_wb_cyc,
-output                      o_wb_stb,
-input                       i_wb_ack,
-input                       i_wb_err
-
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Memory configuration and Wishbone address decoding          //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  This module provides a set of functions that are used to    //
-//  decode memory addresses so other modules know if an address //
-//  is for example in main memory, or boot memory, or a UART    //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-// e.g. 24 for 32MBytes, 26 for 128MBytes
-localparam MAIN_MSB             = 26; 
-
-// e.g. 13 for 4k words
-localparam BOOT_MSB             = 13;  
-
-localparam MAIN_BASE            = 32'h0000_0000; /*  Main Memory            */
-localparam BOOT_BASE            = 32'h0000_0000; /*  Cachable Boot Memory   */
-localparam AMBER_TM_BASE        = 16'h1300;      /*  Timers Module          */
-localparam AMBER_IC_BASE        = 16'h1400;      /*  Interrupt Controller   */
-localparam AMBER_UART0_BASE     = 16'h1600;      /*  UART 0                 */
-localparam AMBER_UART1_BASE     = 16'h1700;      /*  UART 1                 */
-localparam ETHMAC_BASE          = 16'h2000;      /*  Ethernet MAC           */
-localparam HIBOOT_BASE          = 32'h2800_0000; /*  Uncachable Boot Memory */
-localparam TEST_BASE            = 16'hf000;      /*  Test Module            */
-
-
-
-function in_loboot_mem;
-    input [31:0] address;
-begin
-in_loboot_mem  = (address >= BOOT_BASE   && 
-                 address < (BOOT_BASE   + 2**(BOOT_MSB+1)-1));
-end
-endfunction
-
-
-function in_hiboot_mem;
-    input [31:0] address;
-begin
-in_hiboot_mem  = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]);
-end
-endfunction
-
-
-function in_boot_mem;
-    input [31:0] address;
-begin
-in_boot_mem  =  in_loboot_mem(address) || in_hiboot_mem(address);
-end
-endfunction
-
-
-function in_main_mem;
-    input [31:0] address;
-begin
-in_main_mem  = (address >= MAIN_BASE   && 
-                address < (MAIN_BASE   + 2**(MAIN_MSB+1)-1)) &&
-                !in_boot_mem ( address );
-end
-endfunction
-
-
-// UART 0 address space
-function in_uart0;
-    input [31:0] address;
-begin
-    in_uart0 = address [31:16] == AMBER_UART0_BASE;
-end
-endfunction
-
-
-// UART 1 address space
-function in_uart1;
-    input [31:0] address;
-begin
-    in_uart1 = address [31:16] == AMBER_UART1_BASE;
-end
-endfunction
-
-
-// Interrupt Controller address space
-function in_ic;
-    input [31:0] address;
-begin
-    in_ic = address [31:16] == AMBER_IC_BASE;
-end
-endfunction
-
-
-// Timer Module address space
-function in_tm;
-    input [31:0] address;
-begin
-    in_tm = address [31:16] == AMBER_TM_BASE;
-end
-endfunction
-
-
-// Test module
-function in_test;
-    input [31:0] address;
-begin
-    in_test = address [31:16] == TEST_BASE;
-end
-endfunction
-
-
-// Ethernet MAC
-function in_ethmac;
-    input [31:0] address;
-begin
-    in_ethmac = address [31:16] == ETHMAC_BASE;
-end
-endfunction
-
-
-// Used in fetch.v and l2cache.v to allow accesses to these addresses
-// to be cached
-function in_cachable_mem;
-    input [31:0] address;
-begin
-    in_cachable_mem = in_loboot_mem     ( address ) || 
-                      in_main_mem       ( address ) ; 
-end
-endfunction
-
-
-wire                        cache_stall;
-wire                        wb_stall;
-wire    [31:0]              cache_read_data;
-wire                        sel_cache;
-wire                        sel_wb;
-wire                        cache_wb_req;
-wire                        address_cachable;
-
-// ======================================
-// Memory Decode
-// ======================================
-assign address_cachable  = in_cachable_mem( i_address ) && i_cacheable_area[i_address[25:21]];
-
-assign sel_cache         = address_cachable && i_address_valid && i_cache_enable &&  !i_exclusive;
-
-// Don't start wishbone transfers when the cache is stalling the core
-// The cache stalls the core during its initialization sequence
-assign sel_wb            = !sel_cache && i_address_valid && !(cache_stall);
-
-// Return read data either from the wishbone bus or the cache
-assign o_read_data       = sel_cache  ? cache_read_data : 
-                           sel_wb     ? i_wb_dat        :
-                                        32'hffeeddcc ;
-
-// Stall the instruction decode and execute stages of the core
-// when the fetch stage needs more than 1 cycle to return the requested
-// read data
-assign o_fetch_stall     = !i_system_rdy || wb_stall || cache_stall;
-
-
-// ======================================
-// L1 Cache (Unified Instruction and Data)
-// ======================================
-a23_cache u_cache (
-    .i_clk                      ( i_clk                 ),
-     
-    .i_select                   ( sel_cache             ),
-    .i_exclusive                ( i_exclusive           ),
-    .i_write_data               ( i_write_data          ),
-    .i_write_enable             ( i_write_enable        ),
-    .i_address                  ( i_address             ),
-    .i_address_nxt              ( i_address_nxt         ),
-    .i_byte_enable              ( i_byte_enable         ),
-    .i_cache_enable             ( i_cache_enable        ),
-    .i_cache_flush              ( i_cache_flush         ),
-    .o_read_data                ( cache_read_data       ),
-    
-    .o_stall                    ( cache_stall           ),
-    .i_core_stall               ( o_fetch_stall         ),
-    .o_wb_req                   ( cache_wb_req          ),
-    .i_wb_address               ( o_wb_adr              ),
-    .i_wb_read_data             ( i_wb_dat              ),
-    .i_wb_stall                 ( o_wb_stb & ~i_wb_ack  )
-);
-
-
-
-// ======================================
-//  Wishbone Master I/F
-// ======================================
-a23_wishbone u_wishbone (
-    // CPU Side
-    .i_clk                      ( i_clk                 ),
-    
-    // Core Accesses to Wishbone bus
-    .i_select                   ( sel_wb                ),
-    .i_write_data               ( i_write_data          ),
-    .i_write_enable             ( i_write_enable        ),
-    .i_byte_enable              ( i_byte_enable         ),
-    .i_data_access              ( i_data_access         ),
-    .i_exclusive                ( i_exclusive           ),
-    .i_address                  ( i_address             ),
-    .o_stall                    ( wb_stall              ),
-
-    // Cache Accesses to Wishbone bus 
-    // L1 Cache enable - used for hprot
-    .i_cache_req                ( cache_wb_req          ),
-
-    .o_wb_adr                   ( o_wb_adr              ),
-    .o_wb_sel                   ( o_wb_sel              ),
-    .o_wb_we                    ( o_wb_we               ),
-    .i_wb_dat                   ( i_wb_dat              ),
-    .o_wb_dat                   ( o_wb_dat              ),
-    .o_wb_cyc                   ( o_wb_cyc              ),
-    .o_wb_stb                   ( o_wb_stb              ),
-    .i_wb_ack                   ( i_wb_ack              ),
-    .i_wb_err                   ( i_wb_err              )
-);
-
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_functions.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_functions.v
deleted file mode 100644
index b4d9081..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_functions.v
+++ /dev/null
@@ -1,174 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Functions for Amber 2 Core                                  //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Functions used in more than one module                      //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// ========================================================
-// PC Filter - Remove the status bits 
-// ========================================================
-function [31:0] pcf;
-input [31:0] pc_reg;
-    begin
-    pcf = {6'd0, pc_reg[25:2], 2'd0};
-    end
-endfunction
-
-
-// ========================================================
-// 4-bit to 16-bit 1-hot decode
-// ========================================================
-function [14:0] decode;
-input [3:0] reg_sel;
-begin
-case ( reg_sel )
-    4'h0:    decode = 15'h0001;
-    4'h1:    decode = 15'h0002;
-    4'h2:    decode = 15'h0004;
-    4'h3:    decode = 15'h0008;
-    4'h4:    decode = 15'h0010;
-    4'h5:    decode = 15'h0020;
-    4'h6:    decode = 15'h0040;
-    4'h7:    decode = 15'h0080;
-    4'h8:    decode = 15'h0100;
-    4'h9:    decode = 15'h0200;
-    4'ha:    decode = 15'h0400;
-    4'hb:    decode = 15'h0800;
-    4'hc:    decode = 15'h1000;
-    4'hd:    decode = 15'h2000;
-    4'he:    decode = 15'h4000;
-    default: decode = 15'h0000;
-endcase
-end
-endfunction
-
-
-// ========================================================
-// Convert Stats Bits Mode to one-hot encoded version
-// ========================================================
-function [3:0] oh_status_bits_mode;
-input [1:0] fn_status_bits_mode;
-begin
-oh_status_bits_mode = 
-    fn_status_bits_mode == SVC  ? 1'd1 << OH_SVC  :
-    fn_status_bits_mode == IRQ  ? 1'd1 << OH_IRQ  :
-    fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ :
-                                  1'd1 << OH_USR  ;
-end
-endfunction
-
-// ========================================================
-// Convert mode into ascii name
-// ========================================================
-function [(14*8)-1:0]  mode_name;
-input [4:0] mode;
-begin
-
-mode_name    = mode == USR  ? "User          " :
-               mode == SVC  ? "Supervisor    " :
-               mode == IRQ  ? "Interrupt     " :
-               mode == FIRQ ? "Fast Interrupt" :
-                              "UNKNOWN       " ;
-end
-endfunction
-
-
-// ========================================================
-// Conditional Execution Function
-// ========================================================
-// EQ Z set
-// NE Z clear
-// CS C set
-// CC C clear
-// MI N set
-// PL N clear
-// VS V set
-// VC V clear
-// HI C set and Z clear
-// LS C clear or Z set
-// GE N == V
-// LT N != V
-// GT Z == 0,N == V
-// LE Z == 1 or N != V
-// AL Always (unconditional)
-// NV Never
-
-function conditional_execute;
-input [3:0] condition;
-input [3:0] flags;
-begin
-conditional_execute  
-               = ( condition == AL                                        ) ||
-                 ( condition == EQ  &&  flags[2]                          ) ||
-                 ( condition == NE  && !flags[2]                          ) ||
-                 ( condition == CS  &&  flags[1]                          ) ||
-                 ( condition == CC  && !flags[1]                          ) ||
-                 ( condition == MI  &&  flags[3]                          ) ||
-                 ( condition == PL  && !flags[3]                          ) ||
-                 ( condition == VS  &&  flags[0]                          ) ||
-                 ( condition == VC  && !flags[0]                          ) ||
-            
-                 ( condition == HI  &&    flags[1] && !flags[2]           ) ||
-                 ( condition == LS  &&  (!flags[1] ||  flags[2])          ) ||
-            
-                 ( condition == GE  &&  flags[3] == flags[0]              ) ||
-                 ( condition == LT  &&  flags[3] != flags[0]              ) ||
-
-                 ( condition == GT  &&  !flags[2] && flags[3] == flags[0] ) ||
-                 ( condition == LE  &&  (flags[2] || flags[3] != flags[0])) ;
-            
-end
-endfunction
-
-
-// ========================================================
-// Log 2
-// ========================================================
-
-function [31:0] log2;
-input    [31:0] num;
-integer i;
-integer out;
-begin
-  out = 32'd0;
-  for (i=0; i<30; i=i+1)
-    if ((2**i > num) && (out == 0))
-      out = i-1;
-  log2 = out;
-end
-endfunction
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_localparams.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_localparams.v
deleted file mode 100644
index 33c8845..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_localparams.v
+++ /dev/null
@@ -1,117 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_multiply.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_multiply.v
deleted file mode 100644
index c6922ed..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_multiply.v
+++ /dev/null
@@ -1,160 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Multiplication Module for Amber 2 Core                      //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  64-bit Booth signed or unsigned multiply and                //
-//  multiply-accumulate supported. It takes about 38 clock      //
-//  cycles to complete an operation.                            //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-
-// bit 0 go, bit 1 accumulate
-// Command:
-//  4'b01 :  MUL   - 32 bit multiplication
-//  4'b11 :  MLA   - 32 bit multiply and accumulate
-//
-//  34-bit Booth adder
-//  The adder needs to be 34 bit to deal with signed and unsigned 32-bit
-//  multiplication inputs. This adds 1 extra bit. Then to deal with the
-//  case of two max negative numbers another bit is required.
-//
-
-module a23_multiply (
-input                       i_clk,
-input                       i_fetch_stall,
-
-input       [31:0]          i_a_in,         // Rds
-input       [31:0]          i_b_in,         // Rm
-input       [1:0]           i_function,
-input                       i_execute,
-
-output      [31:0]          o_out,
-output      [1:0]           o_flags,        // [1] = N, [0] = Z
-output reg                  o_done = 'd0 // goes high 2 cycles before completion                                          
-);
-
-
-wire        enable;
-wire        accumulate;
-wire [33:0] multiplier;
-wire [33:0] multiplier_bar;
-wire [33:0] sum;
-wire [33:0] sum34_b;
-
-reg  [5:0]  count = 'd0;
-reg  [5:0]  count_nxt;
-reg  [67:0] product = 'd0;
-reg  [67:0] product_nxt;
-reg  [1:0]  flags_nxt;
-wire [32:0] sum_acc1;           // the MSB is the carry out for the upper 32 bit addition
-
-
-assign enable         = i_function[0];
-assign accumulate     = i_function[1];
- 
-assign multiplier     =  { 2'd0, i_a_in} ;
-assign multiplier_bar = ~{ 2'd0, i_a_in} + 34'd1 ;
-
-assign sum34_b        =  product[1:0] == 2'b01 ? multiplier     :
-                         product[1:0] == 2'b10 ? multiplier_bar :
-                                                 34'd0 ;
-
-
-// Use DSP modules from Xilinx Spartan6 FPGA devices
- 
-    // -----------------------------------
-    // 34-bit adder - booth multiplication
-    // -----------------------------------
-    assign sum =  product[67:34] + sum34_b;
-     
-    // ------------------------------------
-    // 33-bit adder - accumulate operations
-    // ------------------------------------
-    assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in};
-     
-
-
-always @*
-    begin
-    // Defaults
-    count_nxt           = count;
-    product_nxt         = product;
-    
-    // update Negative and Zero flags
-    // Use registered value of product so this adds an extra cycle
-    // but this avoids having the 64-bit zero comparator on the
-    // main adder path
-    flags_nxt   = { product[32], product[32:1] == 32'd0 }; 
-    
-
-    if ( count == 6'd0 )
-        product_nxt = {33'd0, 1'd0, i_b_in, 1'd0 } ;
-    else if ( count <= 6'd33 )
-        product_nxt = { sum[33], sum, product[33:1]} ;
-    else if ( count == 6'd34 && accumulate )
-        begin
-        // Note that bit 0 is not part of the product. It is used during the booth
-        // multiplication algorithm
-        product_nxt         = { product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate
-        end
-        
-    // Multiplication state counter
-    if (count == 6'd0)  // start
-        count_nxt   = enable ? 6'd1 : 6'd0;
-    else if ((count == 6'd34 && !accumulate) ||  // MUL
-             (count == 6'd35 &&  accumulate)  )  // MLA
-        count_nxt   = 6'd0;
-    else
-        count_nxt   = count + 1'd1;
-    end
-
-
-always @ ( posedge i_clk )
-    if ( !i_fetch_stall )
-        begin
-        count           <= i_execute ? count_nxt          : count;           
-        product         <= i_execute ? product_nxt        : product;        
-        o_done          <= i_execute ? count == 6'd31 : o_done;          
-        end
-
-// Outputs
-assign o_out   = product[32:1]; 
-assign o_flags = flags_nxt;
-                     
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_ram_register_bank.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_ram_register_bank.v
deleted file mode 100644
index b5c97ac..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_ram_register_bank.v
+++ /dev/null
@@ -1,615 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  RAM-based register Bank for Amber Core                      //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains 37 32-bit registers, 16 of which are visible       //
-//  ina any one operating mode.                                 //
-//  The block is designed using syncronous RAM primitive,       //
-//  and fits well into an FPGA design                           //
-//                                                              //
-//  Author(s):                                                  //
-//      - Dmitry Tarnyagin, dmitry.tarnyagin@lockless.no        //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-module a23_ram_register_bank (
-
-input                       i_clk,
-input                       i_fetch_stall,
-
-input       [1:0]           i_mode_exec,            // registered cpu mode from execution stage
-input       [1:0]           i_mode_exec_nxt,        // 1 periods delayed from i_mode_idec
-                                                    // Used for register reads
-input       [1:0]           i_mode_rds_exec,        // Use raw version in this implementation,
-                                                    // includes i_user_mode_regs_store
-input                       i_user_mode_regs_load,
-input       [3:0]           i_rm_sel,
-input       [3:0]           i_rds_sel,
-input       [3:0]           i_rn_sel,
-
-input                       i_pc_wen,
-input       [3:0]           i_reg_bank_wsel,
-
-input       [23:0]          i_pc,                   // program counter [25:2]
-input       [31:0]          i_reg,
-
-input       [3:0]           i_status_bits_flags,
-input                       i_status_bits_irq_mask,
-input                       i_status_bits_firq_mask,
-
-output      [31:0]          o_rm,
-output      [31:0]          o_rs,
-output      [31:0]          o_rd,
-output      [31:0]          o_rn,
-output      [31:0]          o_pc
-
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Functions for Amber 2 Core                                  //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Functions used in more than one module                      //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// ========================================================
-// PC Filter - Remove the status bits 
-// ========================================================
-function [31:0] pcf;
-input [31:0] pc_reg;
-    begin
-    pcf = {6'd0, pc_reg[25:2], 2'd0};
-    end
-endfunction
-
-
-// ========================================================
-// 4-bit to 16-bit 1-hot decode
-// ========================================================
-function [14:0] decode;
-input [3:0] reg_sel;
-begin
-case ( reg_sel )
-    4'h0:    decode = 15'h0001;
-    4'h1:    decode = 15'h0002;
-    4'h2:    decode = 15'h0004;
-    4'h3:    decode = 15'h0008;
-    4'h4:    decode = 15'h0010;
-    4'h5:    decode = 15'h0020;
-    4'h6:    decode = 15'h0040;
-    4'h7:    decode = 15'h0080;
-    4'h8:    decode = 15'h0100;
-    4'h9:    decode = 15'h0200;
-    4'ha:    decode = 15'h0400;
-    4'hb:    decode = 15'h0800;
-    4'hc:    decode = 15'h1000;
-    4'hd:    decode = 15'h2000;
-    4'he:    decode = 15'h4000;
-    default: decode = 15'h0000;
-endcase
-end
-endfunction
-
-
-// ========================================================
-// Convert Stats Bits Mode to one-hot encoded version
-// ========================================================
-function [3:0] oh_status_bits_mode;
-input [1:0] fn_status_bits_mode;
-begin
-oh_status_bits_mode = 
-    fn_status_bits_mode == SVC  ? 1'd1 << OH_SVC  :
-    fn_status_bits_mode == IRQ  ? 1'd1 << OH_IRQ  :
-    fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ :
-                                  1'd1 << OH_USR  ;
-end
-endfunction
-
-// ========================================================
-// Convert mode into ascii name
-// ========================================================
-function [(14*8)-1:0]  mode_name;
-input [4:0] mode;
-begin
-
-mode_name    = mode == USR  ? "User          " :
-               mode == SVC  ? "Supervisor    " :
-               mode == IRQ  ? "Interrupt     " :
-               mode == FIRQ ? "Fast Interrupt" :
-                              "UNKNOWN       " ;
-end
-endfunction
-
-
-// ========================================================
-// Conditional Execution Function
-// ========================================================
-// EQ Z set
-// NE Z clear
-// CS C set
-// CC C clear
-// MI N set
-// PL N clear
-// VS V set
-// VC V clear
-// HI C set and Z clear
-// LS C clear or Z set
-// GE N == V
-// LT N != V
-// GT Z == 0,N == V
-// LE Z == 1 or N != V
-// AL Always (unconditional)
-// NV Never
-
-function conditional_execute;
-input [3:0] condition;
-input [3:0] flags;
-begin
-conditional_execute  
-               = ( condition == AL                                        ) ||
-                 ( condition == EQ  &&  flags[2]                          ) ||
-                 ( condition == NE  && !flags[2]                          ) ||
-                 ( condition == CS  &&  flags[1]                          ) ||
-                 ( condition == CC  && !flags[1]                          ) ||
-                 ( condition == MI  &&  flags[3]                          ) ||
-                 ( condition == PL  && !flags[3]                          ) ||
-                 ( condition == VS  &&  flags[0]                          ) ||
-                 ( condition == VC  && !flags[0]                          ) ||
-            
-                 ( condition == HI  &&    flags[1] && !flags[2]           ) ||
-                 ( condition == LS  &&  (!flags[1] ||  flags[2])          ) ||
-            
-                 ( condition == GE  &&  flags[3] == flags[0]              ) ||
-                 ( condition == LT  &&  flags[3] != flags[0]              ) ||
-
-                 ( condition == GT  &&  !flags[2] && flags[3] == flags[0] ) ||
-                 ( condition == LE  &&  (flags[2] || flags[3] != flags[0])) ;
-            
-end
-endfunction
-
-
-// ========================================================
-// Log 2
-// ========================================================
-
-function [31:0] log2;
-input    [31:0] num;
-integer i;
-integer out;
-begin
-  out = 32'd0;
-  for (i=0; i<30; i=i+1)
-    if ((2**i > num) && (out == 0))
-      out = i-1;
-  log2 = out;
-end
-endfunction
-
-wire  [1:0]  mode_idec;
-wire  [1:0]  mode_exec;
-wire  [1:0]  mode_rds;
-
-wire  [4:0]  rm_addr;
-wire  [4:0]  rds_addr;
-wire  [4:0]  rn_addr;
-wire  [4:0]  wr_addr;
-
-// Register pool in embedded ram memory
-reg   [31:0] reg_ram_n[31:0];
-reg   [31:0] reg_ram_m[31:0];
-reg   [31:0] reg_ram_ds[31:0];
-
-wire  [31:0] rds_out;
-wire  [31:0] rm_out;
-wire  [31:0] rn_out;
-
-// Synchronous ram input buffering
-reg   [4:0]  rm_addr_reg;
-reg   [4:0]  rds_addr_reg;
-reg   [4:0]  rn_addr_reg;
-
-// User Mode Registers
-reg   [23:0] r15 = 24'hc0_ffee;
-
-wire  [31:0] r15_out_rm;
-wire  [31:0] r15_out_rm_nxt;
-wire  [31:0] r15_out_rn;
-
-// r15 selectors
-reg          rn_15 = 1'b0;   
-reg          rm_15 = 1'b0;
-reg          rds_15 = 1'b0;
-
-// Write Enables from execute stage
-assign mode_idec = i_mode_exec_nxt & ~{2{i_user_mode_regs_load}};
-assign wr_addr = reg_addr(mode_idec, i_reg_bank_wsel);
-
-// Read Enables from stage 1 (fetch)
-assign mode_exec = i_mode_exec_nxt;
-assign rm_addr = reg_addr(mode_exec, i_rm_sel);
-assign rn_addr = reg_addr(mode_exec, i_rn_sel);
-
-// Rds
-assign mode_rds = i_mode_rds_exec;
-assign rds_addr = reg_addr(mode_rds, i_rds_sel);
-
-    
-// ========================================================
-// r15 Register Read based on Mode
-// ========================================================
-assign r15_out_rm     = { i_status_bits_flags, 
-                          i_status_bits_irq_mask, 
-                          i_status_bits_firq_mask, 
-                          r15, 
-                          i_mode_exec};
-
-assign r15_out_rm_nxt = { i_status_bits_flags, 
-                          i_status_bits_irq_mask, 
-                          i_status_bits_firq_mask, 
-                          i_pc, 
-                          i_mode_exec};
-                      
-assign r15_out_rn     = {6'd0, r15, 2'd0};
-
-
-// ========================================================
-// Program Counter out
-// ========================================================
-assign o_pc = r15_out_rn;
-
-// ========================================================
-// Rm Selector
-// ========================================================
-assign rm_out = reg_ram_m[rm_addr_reg];
-
-assign o_rm =	rm_15 ?				r15_out_rm :
-						rm_out;
-
-// ========================================================
-// Rds Selector
-// ========================================================
-assign rds_out = reg_ram_ds[rds_addr_reg];
-
-assign o_rs =	rds_15  ?			r15_out_rn :
-						rds_out;
-
-// ========================================================
-// Rd Selector
-// ========================================================
-assign o_rd =	rds_15  ? 			r15_out_rm_nxt :
-						rds_out;
-
-// ========================================================
-// Rn Selector
-// ========================================================
-assign rn_out = reg_ram_n[rn_addr_reg];
-
-assign o_rn =	rn_15  ?			r15_out_rn :
-						rn_out;
-// ========================================================
-// Register Update
-// ========================================================
-always @ ( posedge i_clk )
-    if (!i_fetch_stall)
-        begin
-
-        // Register write.
-        // Actually the code is synthesed as a syncronous ram
-        // with an additional  pass-through multiplexor for
-        // read-when-write handling.
-        reg_ram_n[wr_addr]      <= i_reg;
-        reg_ram_m[wr_addr]      <= i_reg;
-        reg_ram_ds[wr_addr]     <= i_reg;
-        r15                     <= i_pc_wen ? i_pc : r15;
-
-        // The latching is actually implemented in a hard block.
-        rn_addr_reg             <= rn_addr;
-        rm_addr_reg             <= rm_addr;
-        rds_addr_reg            <= rds_addr;
-
-        rn_15                   <= i_rn_sel == 4'hF;
-        rm_15                   <= i_rm_sel == 4'hF;
-        rds_15                  <= i_rds_sel == 4'hF;
-        end
-    
-// ========================================================
-// Register mapping:
-// ========================================================
-// 0xxxx : r0 - r14
-// 10xxx : r8_firq - r14_firq
-// 110xx : r13_irq - r14_irq
-// 111xx : r13_svc - r14_svc
-
-function [4:0] reg_addr;
-input [1:0] mode;
-input [3:0] sel;
-begin
-	casez ({mode, sel}) // synthesis full_case parallel_case
-		6'b??0???:	reg_addr = {1'b0, sel};		// r0 - r7
-		6'b1?1100:	reg_addr = {1'b0, sel};		// irq and svc r12
-		6'b001???:	reg_addr = {1'b0, sel};		// user r8 - r14
-		6'b011???:	reg_addr = {2'b10, sel[2:0]};	// fiq r8-r14
-		6'b1?10??:	reg_addr = {1'b0, sel};		// irq and svc r8-r11
-		6'b101101:	reg_addr = {3'b110, sel[1:0]};	// irq r13
-		6'b101110:	reg_addr = {3'b110, sel[1:0]};	// irq r14
-		6'b101111:	reg_addr = {3'b110, sel[1:0]};	// irq r15, just to make the case full
-		6'b111101:	reg_addr = {3'b111, sel[1:0]};	// svc r13
-		6'b111110:	reg_addr = {3'b111, sel[1:0]};	// svc r14
-		6'b111111:	reg_addr = {3'b111, sel[1:0]};	// svc r15, just to make the case full
-	endcase
-end
-endfunction
-
-// `ifdef A23_SIMULATION
-// synthesis translate_off
-// To be used as probes...
-wire [31:0] r0;
-wire [31:0] r1;
-wire [31:0] r2;
-wire [31:0] r3;
-wire [31:0] r4;
-wire [31:0] r5;
-wire [31:0] r6;
-wire [31:0] r7;
-wire [31:0] r8;
-wire [31:0] r9;
-wire [31:0] r10;
-wire [31:0] r11;
-wire [31:0] r12;
-wire [31:0] r13;
-wire [31:0] r14;
-wire [31:0] r13_svc;
-wire [31:0] r14_svc;
-wire [31:0] r13_irq;
-wire [31:0] r14_irq;
-wire [31:0] r8_firq;
-wire [31:0] r9_firq;
-wire [31:0] r10_firq;
-wire [31:0] r11_firq;
-wire [31:0] r12_firq;
-wire [31:0] r13_firq;
-wire [31:0] r14_firq;
-wire [31:0] r0_out;
-wire [31:0] r1_out;
-wire [31:0] r2_out;
-wire [31:0] r3_out;
-wire [31:0] r4_out;
-wire [31:0] r5_out;
-wire [31:0] r6_out;
-wire [31:0] r7_out;
-wire [31:0] r8_out;
-wire [31:0] r9_out;
-wire [31:0] r10_out;
-wire [31:0] r11_out;
-wire [31:0] r12_out;
-wire [31:0] r13_out;
-wire [31:0] r14_out;
-
-assign r0  = reg_ram_m[ 0];
-assign r1  = reg_ram_m[ 1];
-assign r2  = reg_ram_m[ 2];
-assign r3  = reg_ram_m[ 3];
-assign r4  = reg_ram_m[ 4];
-assign r5  = reg_ram_m[ 5];
-assign r6  = reg_ram_m[ 6];
-assign r7  = reg_ram_m[ 7];
-assign r8  = reg_ram_m[ 8];
-assign r9  = reg_ram_m[ 9];
-assign r10 = reg_ram_m[10];
-assign r11 = reg_ram_m[11];
-assign r12 = reg_ram_m[12];
-assign r13 = reg_ram_m[13];
-assign r14 = reg_ram_m[14];
-assign r13_svc  = reg_ram_m[29];
-assign r14_svc  = reg_ram_m[30];
-assign r13_irq  = reg_ram_m[25];
-assign r14_irq  = reg_ram_m[26];
-assign r8_firq  = reg_ram_m[16];
-assign r9_firq  = reg_ram_m[17];
-assign r10_firq = reg_ram_m[18];
-assign r11_firq = reg_ram_m[19];
-assign r12_firq = reg_ram_m[20];
-assign r13_firq = reg_ram_m[21];
-assign r14_firq = reg_ram_m[22];
-assign r0_out  = reg_ram_m[reg_addr(mode_exec,  0)];
-assign r1_out  = reg_ram_m[reg_addr(mode_exec,  1)];
-assign r2_out  = reg_ram_m[reg_addr(mode_exec,  2)];
-assign r3_out  = reg_ram_m[reg_addr(mode_exec,  3)];
-assign r4_out  = reg_ram_m[reg_addr(mode_exec,  4)];
-assign r5_out  = reg_ram_m[reg_addr(mode_exec,  5)];
-assign r6_out  = reg_ram_m[reg_addr(mode_exec,  6)];
-assign r7_out  = reg_ram_m[reg_addr(mode_exec,  7)];
-assign r8_out  = reg_ram_m[reg_addr(mode_exec,  8)];
-assign r9_out  = reg_ram_m[reg_addr(mode_exec,  9)];
-assign r10_out = reg_ram_m[reg_addr(mode_exec, 10)];
-assign r11_out = reg_ram_m[reg_addr(mode_exec, 11)];
-assign r12_out = reg_ram_m[reg_addr(mode_exec, 12)];
-assign r13_out = reg_ram_m[reg_addr(mode_exec, 13)];
-assign r14_out = reg_ram_m[reg_addr(mode_exec, 14)];
-// synthesis translate_on
-// `endif
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_register_bank.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_register_bank.v
deleted file mode 100644
index 8b2779f..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_register_bank.v
+++ /dev/null
@@ -1,663 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Register Bank for Amber Core                                //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains 37 32-bit registers, 16 of which are visible       //
-//  ina any one operating mode. Registers use real flipflops,   //
-//  rather than SRAM. This makes sense for an FPGA              //
-//  implementation, where flipflops are plentiful.              //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-module a23_register_bank (
-
-input                       i_clk,
-input                       i_fetch_stall,
-
-input       [1:0]           i_mode_idec,            // user, supervisor, irq_idec, firq_idec etc.
-                                                    // Used for register writes
-input       [1:0]           i_mode_exec,            // 1 periods delayed from i_mode_idec
-                                                    // Used for register reads
-input       [3:0]           i_mode_rds_exec,        // Use one-hot version specifically for rds, 
-                                                    // includes i_user_mode_regs_store
-input                       i_user_mode_regs_load,
-input                       i_firq_not_user_mode,
-input       [3:0]           i_rm_sel,
-input       [3:0]           i_rds_sel,
-input       [3:0]           i_rn_sel,
-
-input                       i_pc_wen,
-input       [14:0]          i_reg_bank_wen,
-
-input       [23:0]          i_pc,                   // program counter [25:2]
-input       [31:0]          i_reg,
-
-input       [3:0]           i_status_bits_flags,
-input                       i_status_bits_irq_mask,
-input                       i_status_bits_firq_mask,
-
-output      [31:0]          o_rm,
-output reg  [31:0]          o_rs,
-output reg  [31:0]          o_rd,
-output      [31:0]          o_rn,
-output      [31:0]          o_pc
-
-);
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Parameters file for Amber 2 Core                            //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Holds general parameters that are used is several core      //
-//  modules                                                     //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// Instruction Types
-localparam [3:0]    REGOP       = 4'h0, // Data processing
-                    MULT        = 4'h1, // Multiply
-                    SWAP        = 4'h2, // Single Data Swap
-                    TRANS       = 4'h3, // Single data transfer
-                    MTRANS      = 4'h4, // Multi-word data transfer
-                    BRANCH      = 4'h5, // Branch
-                    CODTRANS    = 4'h6, // Co-processor data transfer
-                    COREGOP     = 4'h7, // Co-processor data operation
-                    CORTRANS    = 4'h8, // Co-processor register transfer
-                    SWI         = 4'h9; // software interrupt
-
-
-// Opcodes
-localparam [3:0] AND = 4'h0,        // Logical AND
-                 EOR = 4'h1,        // Logical Exclusive OR
-                 SUB = 4'h2,        // Subtract
-                 RSB = 4'h3,        // Reverse Subtract
-                 ADD = 4'h4,        // Add
-                 ADC = 4'h5,        // Add with Carry
-                 SBC = 4'h6,        // Subtract with Carry
-                 RSC = 4'h7,        // Reverse Subtract with Carry
-                 TST = 4'h8,        // Test  (using AND operator)
-                 TEQ = 4'h9,        // Test Equivalence (using EOR operator)
-                 CMP = 4'ha,       // Compare (using Subtract operator)
-                 CMN = 4'hb,       // Compare Negated
-                 ORR = 4'hc,       // Logical OR
-                 MOV = 4'hd,       // Move
-                 BIC = 4'he,       // Bit Clear (using AND & NOT operators)
-                 MVN = 4'hf;       // Move NOT
-                 
-// Condition Encoding
-localparam [3:0] EQ  = 4'h0,        // Equal            / Z set
-                 NE  = 4'h1,        // Not equal        / Z clear
-                 CS  = 4'h2,        // Carry set        / C set
-                 CC  = 4'h3,        // Carry clear      / C clear
-                 MI  = 4'h4,        // Minus            / N set
-                 PL  = 4'h5,        // Plus             / N clear
-                 VS  = 4'h6,        // Overflow         / V set
-                 VC  = 4'h7,        // No overflow      / V clear
-                 HI  = 4'h8,        // Unsigned higher  / C set and Z clear
-                 LS  = 4'h9,        // Unsigned lower
-                                    // or same          / C clear or Z set
-                 GE  = 4'ha,        // Signed greater 
-                                    // than or equal    / N == V
-                 LT  = 4'hb,        // Signed less than / N != V
-                 GT  = 4'hc,        // Signed greater
-                                    // than             / Z == 0, N == V
-                 LE  = 4'hd,        // Signed less than
-                                    // or equal         / Z == 1, N != V
-                 AL  = 4'he,        // Always
-                 NV  = 4'hf;        // Never
-
-// Any instruction with a condition field of 0b1111 is UNPREDICTABLE.                
-                
-// Shift Types
-localparam [1:0] LSL = 2'h0,
-                 LSR = 2'h1,
-                 ASR = 2'h2,
-                 RRX = 2'h3,
-                 ROR = 2'h3; 
- 
-// Modes
-localparam [1:0] SVC  =  2'b11,  // Supervisor
-                 IRQ  =  2'b10,  // Interrupt
-                 FIRQ =  2'b01,  // Fast Interrupt
-                 USR  =  2'b00;  // User
-
-// One-Hot Mode encodings
-localparam [5:0] OH_USR  = 0,
-                 OH_IRQ  = 1,
-                 OH_FIRQ = 2,
-                 OH_SVC  = 3;
-
-
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Functions for Amber 2 Core                                  //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Functions used in more than one module                      //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-// ========================================================
-// PC Filter - Remove the status bits 
-// ========================================================
-function [31:0] pcf;
-input [31:0] pc_reg;
-    begin
-    pcf = {6'd0, pc_reg[25:2], 2'd0};
-    end
-endfunction
-
-
-// ========================================================
-// 4-bit to 16-bit 1-hot decode
-// ========================================================
-function [14:0] decode;
-input [3:0] reg_sel;
-begin
-case ( reg_sel )
-    4'h0:    decode = 15'h0001;
-    4'h1:    decode = 15'h0002;
-    4'h2:    decode = 15'h0004;
-    4'h3:    decode = 15'h0008;
-    4'h4:    decode = 15'h0010;
-    4'h5:    decode = 15'h0020;
-    4'h6:    decode = 15'h0040;
-    4'h7:    decode = 15'h0080;
-    4'h8:    decode = 15'h0100;
-    4'h9:    decode = 15'h0200;
-    4'ha:    decode = 15'h0400;
-    4'hb:    decode = 15'h0800;
-    4'hc:    decode = 15'h1000;
-    4'hd:    decode = 15'h2000;
-    4'he:    decode = 15'h4000;
-    default: decode = 15'h0000;
-endcase
-end
-endfunction
-
-
-// ========================================================
-// Convert Stats Bits Mode to one-hot encoded version
-// ========================================================
-function [3:0] oh_status_bits_mode;
-input [1:0] fn_status_bits_mode;
-begin
-oh_status_bits_mode = 
-    fn_status_bits_mode == SVC  ? 1'd1 << OH_SVC  :
-    fn_status_bits_mode == IRQ  ? 1'd1 << OH_IRQ  :
-    fn_status_bits_mode == FIRQ ? 1'd1 << OH_FIRQ :
-                                  1'd1 << OH_USR  ;
-end
-endfunction
-
-// ========================================================
-// Convert mode into ascii name
-// ========================================================
-function [(14*8)-1:0]  mode_name;
-input [4:0] mode;
-begin
-
-mode_name    = mode == USR  ? "User          " :
-               mode == SVC  ? "Supervisor    " :
-               mode == IRQ  ? "Interrupt     " :
-               mode == FIRQ ? "Fast Interrupt" :
-                              "UNKNOWN       " ;
-end
-endfunction
-
-
-// ========================================================
-// Conditional Execution Function
-// ========================================================
-// EQ Z set
-// NE Z clear
-// CS C set
-// CC C clear
-// MI N set
-// PL N clear
-// VS V set
-// VC V clear
-// HI C set and Z clear
-// LS C clear or Z set
-// GE N == V
-// LT N != V
-// GT Z == 0,N == V
-// LE Z == 1 or N != V
-// AL Always (unconditional)
-// NV Never
-
-function conditional_execute;
-input [3:0] condition;
-input [3:0] flags;
-begin
-conditional_execute  
-               = ( condition == AL                                        ) ||
-                 ( condition == EQ  &&  flags[2]                          ) ||
-                 ( condition == NE  && !flags[2]                          ) ||
-                 ( condition == CS  &&  flags[1]                          ) ||
-                 ( condition == CC  && !flags[1]                          ) ||
-                 ( condition == MI  &&  flags[3]                          ) ||
-                 ( condition == PL  && !flags[3]                          ) ||
-                 ( condition == VS  &&  flags[0]                          ) ||
-                 ( condition == VC  && !flags[0]                          ) ||
-            
-                 ( condition == HI  &&    flags[1] && !flags[2]           ) ||
-                 ( condition == LS  &&  (!flags[1] ||  flags[2])          ) ||
-            
-                 ( condition == GE  &&  flags[3] == flags[0]              ) ||
-                 ( condition == LT  &&  flags[3] != flags[0]              ) ||
-
-                 ( condition == GT  &&  !flags[2] && flags[3] == flags[0] ) ||
-                 ( condition == LE  &&  (flags[2] || flags[3] != flags[0])) ;
-            
-end
-endfunction
-
-
-// ========================================================
-// Log 2
-// ========================================================
-
-function [31:0] log2;
-input    [31:0] num;
-integer i;
-integer out;
-begin
-  out = 32'd0;
-  for (i=0; i<30; i=i+1)
-    if ((2**i > num) && (out == 0))
-      out = i-1;
-  log2 = out;
-end
-endfunction
-
-
-// User Mode Registers
-reg  [31:0] r0  = 32'hdead_beef;
-reg  [31:0] r1  = 32'hdead_beef;
-reg  [31:0] r2  = 32'hdead_beef;
-reg  [31:0] r3  = 32'hdead_beef;
-reg  [31:0] r4  = 32'hdead_beef;
-reg  [31:0] r5  = 32'hdead_beef;
-reg  [31:0] r6  = 32'hdead_beef;
-reg  [31:0] r7  = 32'hdead_beef;
-reg  [31:0] r8  = 32'hdead_beef;
-reg  [31:0] r9  = 32'hdead_beef;
-reg  [31:0] r10 = 32'hdead_beef;
-reg  [31:0] r11 = 32'hdead_beef;
-reg  [31:0] r12 = 32'hdead_beef;
-reg  [31:0] r13 = 32'hdead_beef;
-reg  [31:0] r14 = 32'hdead_beef;
-reg  [23:0] r15 = 24'hc0_ffee;
-
-wire  [31:0] r0_out;
-wire  [31:0] r1_out;
-wire  [31:0] r2_out;
-wire  [31:0] r3_out;
-wire  [31:0] r4_out;
-wire  [31:0] r5_out;
-wire  [31:0] r6_out;
-wire  [31:0] r7_out;
-wire  [31:0] r8_out;
-wire  [31:0] r9_out;
-wire  [31:0] r10_out;
-wire  [31:0] r11_out;
-wire  [31:0] r12_out;
-wire  [31:0] r13_out;
-wire  [31:0] r14_out;
-wire  [31:0] r15_out_rm;
-wire  [31:0] r15_out_rm_nxt;
-wire  [31:0] r15_out_rn;
-
-wire  [31:0] r8_rds;
-wire  [31:0] r9_rds;
-wire  [31:0] r10_rds;
-wire  [31:0] r11_rds;
-wire  [31:0] r12_rds;
-wire  [31:0] r13_rds;
-wire  [31:0] r14_rds;
-
-// Supervisor Mode Registers
-reg  [31:0] r13_svc = 32'hdead_beef;
-reg  [31:0] r14_svc = 32'hdead_beef;
-
-// Interrupt Mode Registers
-reg  [31:0] r13_irq = 32'hdead_beef;
-reg  [31:0] r14_irq = 32'hdead_beef;
-
-// Fast Interrupt Mode Registers
-reg  [31:0] r8_firq  = 32'hdead_beef;
-reg  [31:0] r9_firq  = 32'hdead_beef;
-reg  [31:0] r10_firq = 32'hdead_beef;
-reg  [31:0] r11_firq = 32'hdead_beef;
-reg  [31:0] r12_firq = 32'hdead_beef;
-reg  [31:0] r13_firq = 32'hdead_beef;
-reg  [31:0] r14_firq = 32'hdead_beef;
-
-wire        usr_exec;
-wire        svc_exec;
-wire        irq_exec;
-wire        firq_exec;
-
-wire        usr_idec;
-wire        svc_idec;
-wire        irq_idec;
-wire        firq_idec;
-
-    // Write Enables from execute stage
-assign usr_idec  =  i_user_mode_regs_load || i_mode_idec == USR;
-assign svc_idec  = !i_user_mode_regs_load && i_mode_idec == SVC;
-assign irq_idec  = !i_user_mode_regs_load && i_mode_idec == IRQ;
-
-// pre-encoded in decode stage to speed up long path
-assign firq_idec = i_firq_not_user_mode;
-
-    // Read Enables from stage 1 (fetch)
-assign usr_exec  = i_mode_exec == USR;
-assign svc_exec  = i_mode_exec == SVC;
-assign irq_exec  = i_mode_exec == IRQ;
-assign firq_exec = i_mode_exec == FIRQ;
-
-
-// ========================================================
-// Register Update
-// ========================================================
-always @ ( posedge i_clk )
-    if (!i_fetch_stall)
-        begin
-        r0       <=  i_reg_bank_wen[0 ]              ? i_reg : r0;  
-        r1       <=  i_reg_bank_wen[1 ]              ? i_reg : r1;  
-        r2       <=  i_reg_bank_wen[2 ]              ? i_reg : r2;  
-        r3       <=  i_reg_bank_wen[3 ]              ? i_reg : r3;  
-        r4       <=  i_reg_bank_wen[4 ]              ? i_reg : r4;  
-        r5       <=  i_reg_bank_wen[5 ]              ? i_reg : r5;  
-        r6       <=  i_reg_bank_wen[6 ]              ? i_reg : r6;  
-        r7       <=  i_reg_bank_wen[7 ]              ? i_reg : r7;  
-        
-        r8       <= (i_reg_bank_wen[8 ] && !firq_idec) ? i_reg : r8;  
-        r9       <= (i_reg_bank_wen[9 ] && !firq_idec) ? i_reg : r9;  
-        r10      <= (i_reg_bank_wen[10] && !firq_idec) ? i_reg : r10; 
-        r11      <= (i_reg_bank_wen[11] && !firq_idec) ? i_reg : r11; 
-        r12      <= (i_reg_bank_wen[12] && !firq_idec) ? i_reg : r12; 
-        
-        r8_firq  <= (i_reg_bank_wen[8 ] &&  firq_idec) ? i_reg : r8_firq;
-        r9_firq  <= (i_reg_bank_wen[9 ] &&  firq_idec) ? i_reg : r9_firq;
-        r10_firq <= (i_reg_bank_wen[10] &&  firq_idec) ? i_reg : r10_firq;
-        r11_firq <= (i_reg_bank_wen[11] &&  firq_idec) ? i_reg : r11_firq;
-        r12_firq <= (i_reg_bank_wen[12] &&  firq_idec) ? i_reg : r12_firq;
-
-        r13      <= (i_reg_bank_wen[13] &&  usr_idec)  ? i_reg : r13;
-        r14      <= (i_reg_bank_wen[14] &&  usr_idec)  ? i_reg : r14;
-     
-        r13_svc  <= (i_reg_bank_wen[13] &&  svc_idec)  ? i_reg : r13_svc;
-        r14_svc  <= (i_reg_bank_wen[14] &&  svc_idec)  ? i_reg : r14_svc;   
-       
-        r13_irq  <= (i_reg_bank_wen[13] &&  irq_idec)  ? i_reg : r13_irq;
-        r14_irq  <= (i_reg_bank_wen[14] &&  irq_idec)  ? i_reg : r14_irq;       
-      
-        r13_firq <= (i_reg_bank_wen[13] &&  firq_idec) ? i_reg : r13_firq;
-        r14_firq <= (i_reg_bank_wen[14] &&  firq_idec) ? i_reg : r14_firq;  
-        
-        r15      <=  i_pc_wen                          ?  i_pc : r15;
-        end
-    
-    
-// ========================================================
-// Register Read based on Mode
-// ========================================================
-assign r0_out = r0;
-assign r1_out = r1;
-assign r2_out = r2;
-assign r3_out = r3;
-assign r4_out = r4;
-assign r5_out = r5;
-assign r6_out = r6;
-assign r7_out = r7;
-
-assign r8_out  = firq_exec ? r8_firq  : r8;
-assign r9_out  = firq_exec ? r9_firq  : r9;
-assign r10_out = firq_exec ? r10_firq : r10;
-assign r11_out = firq_exec ? r11_firq : r11;
-assign r12_out = firq_exec ? r12_firq : r12;
-
-assign r13_out = usr_exec ? r13      :
-                 svc_exec ? r13_svc  :
-                 irq_exec ? r13_irq  :
-                          r13_firq ;
-                       
-assign r14_out = usr_exec ? r14      :
-                 svc_exec ? r14_svc  :
-                 irq_exec ? r14_irq  :
-                          r14_firq ;
- 
-
-assign r15_out_rm     = { i_status_bits_flags, 
-                          i_status_bits_irq_mask, 
-                          i_status_bits_firq_mask, 
-                          r15, 
-                          i_mode_exec};
-
-assign r15_out_rm_nxt = { i_status_bits_flags, 
-                          i_status_bits_irq_mask, 
-                          i_status_bits_firq_mask, 
-                          i_pc, 
-                          i_mode_exec};
-                      
-assign r15_out_rn     = {6'd0, r15, 2'd0};
-
-
-// rds outputs
-assign r8_rds  = i_mode_rds_exec[OH_FIRQ] ? r8_firq  : r8;
-assign r9_rds  = i_mode_rds_exec[OH_FIRQ] ? r9_firq  : r9;
-assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10;
-assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11;
-assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12;
-
-assign r13_rds = i_mode_rds_exec[OH_USR]  ? r13      :
-                 i_mode_rds_exec[OH_SVC]  ? r13_svc  :
-                 i_mode_rds_exec[OH_IRQ]  ? r13_irq  :
-                                            r13_firq ;
-                       
-assign r14_rds = i_mode_rds_exec[OH_USR]  ? r14      :
-                 i_mode_rds_exec[OH_SVC]  ? r14_svc  :
-                 i_mode_rds_exec[OH_IRQ]  ? r14_irq  :
-                                            r14_firq ;
-
-// ========================================================
-// Program Counter out
-// ========================================================
-assign o_pc = r15_out_rn;
-
-// ========================================================
-// Rm Selector
-// ========================================================
-assign o_rm = i_rm_sel == 4'd0 ? r0_out  :
-              i_rm_sel == 4'd1 ? r1_out  : 
-              i_rm_sel == 4'd2 ? r2_out  : 
-              i_rm_sel == 4'd3 ? r3_out  : 
-              i_rm_sel == 4'd4 ? r4_out  : 
-              i_rm_sel == 4'd5 ? r5_out  : 
-              i_rm_sel == 4'd6 ? r6_out  : 
-              i_rm_sel == 4'd7 ? r7_out  : 
-              i_rm_sel == 4'd8 ? r8_out  : 
-              i_rm_sel == 4'd9 ? r9_out  : 
-              i_rm_sel == 4'd10 ? r10_out : 
-              i_rm_sel == 4'd11 ? r11_out : 
-              i_rm_sel == 4'd12 ? r12_out : 
-              i_rm_sel == 4'd13 ? r13_out : 
-              i_rm_sel == 4'd14 ? r14_out : 
-                                  r15_out_rm ; 
-
-
-
-
-// ========================================================
-// Rds Selector
-// ========================================================
-always @*
-    case (i_rds_sel)
-       4'd0 :  o_rs = r0_out  ;
-       4'd1 :  o_rs = r1_out  ; 
-       4'd2 :  o_rs = r2_out  ; 
-       4'd3 :  o_rs = r3_out  ; 
-       4'd4 :  o_rs = r4_out  ; 
-       4'd5 :  o_rs = r5_out  ; 
-       4'd6 :  o_rs = r6_out  ; 
-       4'd7 :  o_rs = r7_out  ; 
-       4'd8 :  o_rs = r8_rds  ; 
-       4'd9 :  o_rs = r9_rds  ; 
-       4'd10 :  o_rs = r10_rds ; 
-       4'd11 :  o_rs = r11_rds ; 
-       4'd12 :  o_rs = r12_rds ; 
-       4'd13 :  o_rs = r13_rds ; 
-       4'd14 :  o_rs = r14_rds ; 
-       default: o_rs = r15_out_rn ; 
-    endcase
-
-                                    
-
-// ========================================================
-// Rd Selector
-// ========================================================
-always @*
-    case (i_rds_sel)
-       4'd0 :  o_rd = r0_out  ;
-       4'd1 :  o_rd = r1_out  ; 
-       4'd2 :  o_rd = r2_out  ; 
-       4'd3 :  o_rd = r3_out  ; 
-       4'd4 :  o_rd = r4_out  ; 
-       4'd5 :  o_rd = r5_out  ; 
-       4'd6 :  o_rd = r6_out  ; 
-       4'd7 :  o_rd = r7_out  ; 
-       4'd8 :  o_rd = r8_rds  ; 
-       4'd9 :  o_rd = r9_rds  ; 
-       4'd10 :  o_rd = r10_rds ; 
-       4'd11 :  o_rd = r11_rds ; 
-       4'd12 :  o_rd = r12_rds ; 
-       4'd13 :  o_rd = r13_rds ; 
-       4'd14 :  o_rd = r14_rds ; 
-       default: o_rd = r15_out_rm_nxt ; 
-    endcase
-
-                                    
-// ========================================================
-// Rn Selector
-// ========================================================
-assign o_rn = i_rn_sel == 4'd0 ? r0_out  :
-              i_rn_sel == 4'd1 ? r1_out  : 
-              i_rn_sel == 4'd2 ? r2_out  : 
-              i_rn_sel == 4'd3 ? r3_out  : 
-              i_rn_sel == 4'd4 ? r4_out  : 
-              i_rn_sel == 4'd5 ? r5_out  : 
-              i_rn_sel == 4'd6 ? r6_out  : 
-              i_rn_sel == 4'd7 ? r7_out  : 
-              i_rn_sel == 4'd8 ? r8_out  : 
-              i_rn_sel == 4'd9 ? r9_out  : 
-              i_rn_sel == 4'd10 ? r10_out : 
-              i_rn_sel == 4'd11 ? r11_out : 
-              i_rn_sel == 4'd12 ? r12_out : 
-              i_rn_sel == 4'd13 ? r13_out : 
-              i_rn_sel == 4'd14 ? r14_out : 
-                                  r15_out_rn ; 
-
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_wishbone.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_wishbone.v
deleted file mode 100644
index 40560f4..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/a23_wishbone.v
+++ /dev/null
@@ -1,292 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Wishbone master interface for the Amber core                //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Turns memory access requests from the execute stage and     //
-//  cache into wishbone bus cycles. For 4-word read requests    //
-//  from the cache and swap accesses ( read followed by write   //
-//  to the same address) from the execute stage,                //
-//  a block transfer is done. All other requests result in      //
-//  single word transfers.                                      //
-//                                                              //
-//  Write accesses can be done in a single clock cycle on       //
-//  the wishbone bus, is the destination allows it. The         //
-//  next transfer will begin immediately on the                 //
-//  next cycle on the bus. This looks like a block transfer     //
-//  and does hold ownership of the wishbone bus, preventing     //
-//  the other master ( the ethernet MAC) from gaining           //
-//  ownership between those two cycles. But otherwise it would  //
-//  be necessary to insert a wait cycle after every write,      //
-//  slowing down the performance of the core by around 5 to     //
-//  10%.                                                        //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module a23_wishbone
-(
-input                       i_clk,
-
-// Core Accesses to Wishbone bus
-input                       i_select,
-input       [31:0]          i_write_data,
-input                       i_write_enable,
-input       [3:0]           i_byte_enable,    // valid for writes only
-input                       i_data_access,
-input                       i_exclusive,      // high for read part of swap access
-input       [31:0]          i_address,
-output                      o_stall,
-
-// Cache Accesses to Wishbone bus
-input                       i_cache_req,
-
-// Wishbone Bus
-output reg  [31:0]          o_wb_adr = 'd0,
-output reg  [3:0]           o_wb_sel = 'd0,
-output reg                  o_wb_we  = 'd0,
-input       [31:0]          i_wb_dat,
-output reg  [31:0]          o_wb_dat = 'd0,
-output reg                  o_wb_cyc = 'd0,
-output reg                  o_wb_stb = 'd0,
-input                       i_wb_ack,
-input                       i_wb_err
-
-);
-
-
-localparam [3:0] WB_IDLE            = 3'd0,
-                 WB_BURST1          = 3'd1,
-                 WB_BURST2          = 3'd2,
-                 WB_BURST3          = 3'd3,
-                 WB_WAIT_ACK        = 3'd4;
-
-reg     [2:0]               wishbone_st = WB_IDLE;
-
-wire                        core_read_request;
-wire                        core_write_request;
-wire                        cache_read_request;
-wire                        cache_write_request;
-wire                        start_access;
-reg                         servicing_cache = 'd0;
-wire    [3:0]               byte_enable;
-reg                         exclusive_access = 'd0;
-wire                        read_ack;
-wire                        wait_write_ack;
-wire                        wb_wait;
-
-// Write buffer
-reg     [31:0]              wbuf_addr_r = 'd0;
-reg     [3:0]               wbuf_sel_r  = 'd0;
-reg                         wbuf_busy_r = 'd0;
-
-
-assign read_ack             = !o_wb_we && i_wb_ack;
-assign o_stall              = ( core_read_request  && !read_ack )       || 
-                              ( core_read_request  && servicing_cache ) ||
-                              ( core_write_request && servicing_cache ) ||
-                              ( core_write_request && wishbone_st == WB_WAIT_ACK) ||
-                              ( cache_write_request && wishbone_st == WB_WAIT_ACK) ||
-                              wbuf_busy_r;
-
-                              // Don't stall on writes
-                              // Wishbone is doing burst read so make core wait to execute the write
-                              // ( core_write_request && !i_wb_ack )  ;
-                              
-assign core_read_request    = i_select && !i_write_enable;
-assign core_write_request   = i_select &&  i_write_enable;
-
-assign cache_read_request   = i_cache_req && !i_write_enable;
-assign cache_write_request  = i_cache_req &&  i_write_enable;
-
-assign wb_wait              = o_wb_stb && !i_wb_ack;
-assign start_access         = (core_read_request || core_write_request || i_cache_req) && !wb_wait ;
-
-// For writes the byte enable is always 4'hf
-assign byte_enable          = wbuf_busy_r                                   ? wbuf_sel_r    :
-                              ( core_write_request || cache_write_request ) ? i_byte_enable : 
-                                                                              4'hf ;
-                                    
-
-
-// ======================================
-// Write buffer
-// ======================================
-
-
-always @( posedge i_clk )
-    if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
-        begin
-        wbuf_addr_r <= i_address;
-        wbuf_sel_r  <= i_byte_enable;
-        wbuf_busy_r <= 1'd1;
-        end
-    else if (!o_wb_stb)
-        wbuf_busy_r <= 1'd0;
-    
-// ======================================
-// Register Accesses
-// ======================================
-always @( posedge i_clk )
-    if ( start_access )
-        o_wb_dat <= i_write_data;
-
-
-assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
-
-
-always @( posedge i_clk )
-    case ( wishbone_st )
-        WB_IDLE :
-            begin 
-                
-            if ( start_access )
-                begin
-                o_wb_stb            <= 1'd1; 
-                o_wb_cyc            <= 1'd1; 
-                o_wb_sel            <= byte_enable;
-                end
-            else if ( !wait_write_ack )
-                begin
-                o_wb_stb            <= 1'd0;
-                
-                // Hold cyc high after an exclusive access
-                // to hold ownership of the wishbone bus
-                o_wb_cyc            <= exclusive_access;
-                end
-
-            // cache has priority over the core                     
-            servicing_cache <= cache_read_request && !wait_write_ack;
-
-            if ( wait_write_ack )
-                begin
-                // still waiting for last (write) access to complete
-                wishbone_st      <= WB_WAIT_ACK;
-                end  
-            // do a burst of 4 read to fill a cache line                   
-            else if ( cache_read_request )
-                begin
-                wishbone_st         <= WB_BURST1;
-                exclusive_access    <= 1'd0;
-                end                    
-            else if ( core_read_request )
-                begin
-                wishbone_st         <= WB_WAIT_ACK;
-                exclusive_access    <= i_exclusive;
-                end                    
-           // The core does not currently issue exclusive write requests
-           // but there's no reason why this might not be added some
-           // time in the future so allow for it here
-            else if ( core_write_request )
-                exclusive_access <= i_exclusive;
-
-                            
-            if ( start_access )
-                begin
-                if (wbuf_busy_r)
-                    begin
-                    o_wb_we              <= 1'd1;
-                    o_wb_adr[31:2]       <= wbuf_addr_r[31:2];
-                    end
-                else
-                    begin
-                    o_wb_we              <= core_write_request || cache_write_request;
-                    // only update these on new wb access to make debug easier
-                    o_wb_adr[31:2]       <= i_address[31:2];
-                    end
-                    
-                o_wb_adr[1:0]        <= byte_enable == 4'b0001 ? 2'd0 :
-                                        byte_enable == 4'b0010 ? 2'd1 :
-                                        byte_enable == 4'b0100 ? 2'd2 :
-                                        byte_enable == 4'b1000 ? 2'd3 :
-                                       
-                                        byte_enable == 4'b0011 ? 2'd0 :
-                                        byte_enable == 4'b1100 ? 2'd2 :
-                                       
-                                                                 2'd0 ;
-                end
-            end
-                    
-
-        // Read burst, wait for first ack
-        WB_BURST1:  
-            if ( i_wb_ack )
-                begin
-                // burst of 4 that wraps
-                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
-                wishbone_st     <= WB_BURST2;
-                end
-            
-            
-        // Read burst, wait for second ack
-        WB_BURST2:  
-            if ( i_wb_ack )
-                begin
-                // burst of 4 that wraps
-                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
-                wishbone_st     <= WB_BURST3;
-                end
-            
-            
-        // Read burst, wait for third ack
-        WB_BURST3:  
-            if ( i_wb_ack )
-                begin
-                // burst of 4 that wraps
-                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1'd1;
-                wishbone_st     <= WB_WAIT_ACK;
-                end
-
-
-        // Wait for the wishbone ack to be asserted
-        WB_WAIT_ACK:   
-            if ( i_wb_ack )
-                begin
-                wishbone_st         <= WB_IDLE;
-                o_wb_stb            <= 1'd0; 
-                o_wb_cyc            <= exclusive_access; 
-                o_wb_we             <= 1'd0;
-                servicing_cache     <= 1'd0;
-                end
-                         
-    endcase
-        
-        
-
-// ========================================================
-// Debug Wishbone bus - not synthesizable
-// ========================================================
-    
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/debug_functions.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/debug_functions.v
deleted file mode 100644
index dc20575..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/debug_functions.v
+++ /dev/null
@@ -1,228 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Debug Functions                                             //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  A bunch of non-synthesizable testbench functions            //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-// Testbench Functions used in more than one module
-
-
-function [31:0] hex_chars_to_32bits;
-input [8*8-1:0] hex_chars;
-begin
-hex_chars_to_32bits[31:28] = hex_chars_to_4bits (hex_chars[8*8-1:7*8]);
-hex_chars_to_32bits[27:24] = hex_chars_to_4bits (hex_chars[7*8-1:6*8]);
-hex_chars_to_32bits[23:20] = hex_chars_to_4bits (hex_chars[6*8-1:5*8]);
-hex_chars_to_32bits[19:16] = hex_chars_to_4bits (hex_chars[5*8-1:4*8]);
-hex_chars_to_32bits[15:12] = hex_chars_to_4bits (hex_chars[4*8-1:3*8]);
-hex_chars_to_32bits[11: 8] = hex_chars_to_4bits (hex_chars[3*8-1:2*8]);
-hex_chars_to_32bits[ 7: 4] = hex_chars_to_4bits (hex_chars[2*8-1:1*8]);
-hex_chars_to_32bits[ 3: 0] = hex_chars_to_4bits (hex_chars[1*8-1:  0]);
-end
-endfunction
-
-
-function [7:0] hex_chars_to_8bits;
-input [8*2-1:0] hex_chars;
-begin
-hex_chars_to_8bits[ 7: 4] = hex_chars_to_4bits (hex_chars[2*8-1:1*8]);
-hex_chars_to_8bits[ 3: 0] = hex_chars_to_4bits (hex_chars[1*8-1:  0]);
-end
-endfunction
-
-
-function [3:0] hex_chars_to_4bits;
-input [7:0] hex_chars;
-begin
-case (hex_chars)
-    "0" : hex_chars_to_4bits  = 4'h0;
-    "1" : hex_chars_to_4bits  = 4'h1;
-    "2" : hex_chars_to_4bits  = 4'h2;
-    "3" : hex_chars_to_4bits  = 4'h3;
-    "4" : hex_chars_to_4bits  = 4'h4;
-    "5" : hex_chars_to_4bits  = 4'h5;
-    "6" : hex_chars_to_4bits  = 4'h6;
-    "7" : hex_chars_to_4bits  = 4'h7;
-    "8" : hex_chars_to_4bits  = 4'h8;
-    "9" : hex_chars_to_4bits  = 4'h9;
-    "a" : hex_chars_to_4bits  = 4'ha;
-    "b" : hex_chars_to_4bits  = 4'hb;
-    "c" : hex_chars_to_4bits  = 4'hc;
-    "d" : hex_chars_to_4bits  = 4'hd;
-    "e" : hex_chars_to_4bits  = 4'he;
-    "f" : hex_chars_to_4bits  = 4'hf;
-    "A" : hex_chars_to_4bits  = 4'ha;
-    "B" : hex_chars_to_4bits  = 4'hb;
-    "C" : hex_chars_to_4bits  = 4'hc;
-    "D" : hex_chars_to_4bits  = 4'hd;
-    "E" : hex_chars_to_4bits  = 4'he;
-    "F" : hex_chars_to_4bits  = 4'hf;
-endcase
-end
-endfunction
-
-
-function [120*8-1:0] align_line;   
-input [120*8-1:0] line;
-begin
-case (1'd1)
-    line[1 *8-1:    0] == 8'd0 : align_line = 960'd0;
-    line[2 *8-1:1 *8] == 8'd0 : align_line = {line[1 *8-1:  0], 952'd0};
-    line[3 *8-1:2 *8] == 8'd0 : align_line = {line[2 *8-1:  0], 944'd0};
-    line[4 *8-1:3 *8] == 8'd0 : align_line = {line[3 *8-1:  0], 936'd0};
-    line[5 *8-1:4 *8] == 8'd0 : align_line = {line[4 *8-1:  0], 928'd0};
-    line[6 *8-1:5 *8] == 8'd0 : align_line = {line[5 *8-1:  0], 920'd0};
-    line[7 *8-1:6 *8] == 8'd0 : align_line = {line[6 *8-1:  0], 912'd0};
-    line[8 *8-1:7 *8] == 8'd0 : align_line = {line[7 *8-1:  0], 904'd0};
-    line[9 *8-1:8 *8] == 8'd0 : align_line = {line[8 *8-1:  0], 896'd0};
-    line[10 *8-1:9 *8] == 8'd0 : align_line = {line[9 *8-1:  0], 888'd0};
-    line[11 *8-1:10 *8] == 8'd0 : align_line = {line[10 *8-1:  0], 880'd0};
-    line[12 *8-1:11 *8] == 8'd0 : align_line = {line[11 *8-1:  0], 872'd0};
-    line[13 *8-1:12 *8] == 8'd0 : align_line = {line[12 *8-1:  0], 864'd0};
-    line[14 *8-1:13 *8] == 8'd0 : align_line = {line[13 *8-1:  0], 856'd0};
-    line[15 *8-1:14 *8] == 8'd0 : align_line = {line[14 *8-1:  0], 848'd0};
-    line[16 *8-1:15 *8] == 8'd0 : align_line = {line[15 *8-1:  0], 840'd0};
-    line[17 *8-1:16 *8] == 8'd0 : align_line = {line[16 *8-1:  0], 832'd0};
-    line[18 *8-1:17 *8] == 8'd0 : align_line = {line[17 *8-1:  0], 824'd0};
-    line[19 *8-1:18 *8] == 8'd0 : align_line = {line[18 *8-1:  0], 816'd0};
-    line[20 *8-1:19 *8] == 8'd0 : align_line = {line[19 *8-1:  0], 808'd0};
-    line[21 *8-1:20 *8] == 8'd0 : align_line = {line[20 *8-1:  0], 800'd0};
-    line[22 *8-1:21 *8] == 8'd0 : align_line = {line[21 *8-1:  0], 792'd0};
-    line[23 *8-1:22 *8] == 8'd0 : align_line = {line[22 *8-1:  0], 784'd0};
-    line[24 *8-1:23 *8] == 8'd0 : align_line = {line[23 *8-1:  0], 776'd0};
-    line[25 *8-1:24 *8] == 8'd0 : align_line = {line[24 *8-1:  0], 768'd0};
-    line[26 *8-1:25 *8] == 8'd0 : align_line = {line[25 *8-1:  0], 760'd0};
-    line[27 *8-1:26 *8] == 8'd0 : align_line = {line[26 *8-1:  0], 752'd0};
-    line[28 *8-1:27 *8] == 8'd0 : align_line = {line[27 *8-1:  0], 744'd0};
-    line[29 *8-1:28 *8] == 8'd0 : align_line = {line[28 *8-1:  0], 736'd0};
-    line[30 *8-1:29 *8] == 8'd0 : align_line = {line[29 *8-1:  0], 728'd0};
-    line[31 *8-1:30 *8] == 8'd0 : align_line = {line[30 *8-1:  0], 720'd0};
-    line[32 *8-1:31 *8] == 8'd0 : align_line = {line[31 *8-1:  0], 712'd0};
-    line[33 *8-1:32 *8] == 8'd0 : align_line = {line[32 *8-1:  0], 704'd0};
-    line[34 *8-1:33 *8] == 8'd0 : align_line = {line[33 *8-1:  0], 696'd0};
-    line[35 *8-1:34 *8] == 8'd0 : align_line = {line[34 *8-1:  0], 688'd0};
-    line[36 *8-1:35 *8] == 8'd0 : align_line = {line[35 *8-1:  0], 680'd0};
-    line[37 *8-1:36 *8] == 8'd0 : align_line = {line[36 *8-1:  0], 672'd0};
-    line[38 *8-1:37 *8] == 8'd0 : align_line = {line[37 *8-1:  0], 664'd0};
-    line[39 *8-1:38 *8] == 8'd0 : align_line = {line[38 *8-1:  0], 656'd0};
-    line[40 *8-1:39 *8] == 8'd0 : align_line = {line[39 *8-1:  0], 648'd0};
-    line[41 *8-1:40 *8] == 8'd0 : align_line = {line[40 *8-1:  0], 640'd0};
-    line[42 *8-1:41 *8] == 8'd0 : align_line = {line[41 *8-1:  0], 632'd0};
-    line[43 *8-1:42 *8] == 8'd0 : align_line = {line[42 *8-1:  0], 624'd0};
-    line[44 *8-1:43 *8] == 8'd0 : align_line = {line[43 *8-1:  0], 616'd0};
-    line[45 *8-1:44 *8] == 8'd0 : align_line = {line[44 *8-1:  0], 608'd0};
-    line[46 *8-1:45 *8] == 8'd0 : align_line = {line[45 *8-1:  0], 600'd0};
-    line[47 *8-1:46 *8] == 8'd0 : align_line = {line[46 *8-1:  0], 592'd0};
-    line[48 *8-1:47 *8] == 8'd0 : align_line = {line[47 *8-1:  0], 584'd0};
-    line[49 *8-1:48 *8] == 8'd0 : align_line = {line[48 *8-1:  0], 576'd0};
-    line[50 *8-1:49 *8] == 8'd0 : align_line = {line[49 *8-1:  0], 568'd0};
-    line[51 *8-1:50 *8] == 8'd0 : align_line = {line[50 *8-1:  0], 560'd0};
-    line[52 *8-1:51 *8] == 8'd0 : align_line = {line[51 *8-1:  0], 552'd0};
-    line[53 *8-1:52 *8] == 8'd0 : align_line = {line[52 *8-1:  0], 544'd0};
-    line[54 *8-1:53 *8] == 8'd0 : align_line = {line[53 *8-1:  0], 536'd0};
-    line[55 *8-1:54 *8] == 8'd0 : align_line = {line[54 *8-1:  0], 528'd0};
-    line[56 *8-1:55 *8] == 8'd0 : align_line = {line[55 *8-1:  0], 520'd0};
-    line[57 *8-1:56 *8] == 8'd0 : align_line = {line[56 *8-1:  0], 512'd0};
-    line[58 *8-1:57 *8] == 8'd0 : align_line = {line[57 *8-1:  0], 504'd0};
-    line[59 *8-1:58 *8] == 8'd0 : align_line = {line[58 *8-1:  0], 496'd0};
-    line[60 *8-1:59 *8] == 8'd0 : align_line = {line[59 *8-1:  0], 488'd0};
-    line[61 *8-1:60 *8] == 8'd0 : align_line = {line[60 *8-1:  0], 480'd0};
-    line[62 *8-1:61 *8] == 8'd0 : align_line = {line[61 *8-1:  0], 472'd0};
-    line[63 *8-1:62 *8] == 8'd0 : align_line = {line[62 *8-1:  0], 464'd0};
-    line[64 *8-1:63 *8] == 8'd0 : align_line = {line[63 *8-1:  0], 456'd0};
-    line[65 *8-1:64 *8] == 8'd0 : align_line = {line[64 *8-1:  0], 448'd0};
-    line[66 *8-1:65 *8] == 8'd0 : align_line = {line[65 *8-1:  0], 440'd0};
-    line[67 *8-1:66 *8] == 8'd0 : align_line = {line[66 *8-1:  0], 432'd0};
-    line[68 *8-1:67 *8] == 8'd0 : align_line = {line[67 *8-1:  0], 424'd0};
-    line[69 *8-1:68 *8] == 8'd0 : align_line = {line[68 *8-1:  0], 416'd0};
-    line[70 *8-1:69 *8] == 8'd0 : align_line = {line[69 *8-1:  0], 408'd0};
-    line[71 *8-1:70 *8] == 8'd0 : align_line = {line[70 *8-1:  0], 400'd0};
-    line[72 *8-1:71 *8] == 8'd0 : align_line = {line[71 *8-1:  0], 392'd0};
-    line[73 *8-1:72 *8] == 8'd0 : align_line = {line[72 *8-1:  0], 384'd0};
-    line[74 *8-1:73 *8] == 8'd0 : align_line = {line[73 *8-1:  0], 376'd0};
-    line[75 *8-1:74 *8] == 8'd0 : align_line = {line[74 *8-1:  0], 368'd0};
-    line[76 *8-1:75 *8] == 8'd0 : align_line = {line[75 *8-1:  0], 360'd0};
-    line[77 *8-1:76 *8] == 8'd0 : align_line = {line[76 *8-1:  0], 352'd0};
-    line[78 *8-1:77 *8] == 8'd0 : align_line = {line[77 *8-1:  0], 344'd0};
-    line[79 *8-1:78 *8] == 8'd0 : align_line = {line[78 *8-1:  0], 336'd0};
-    line[80 *8-1:79 *8] == 8'd0 : align_line = {line[79 *8-1:  0], 328'd0};
-    line[81 *8-1:80 *8] == 8'd0 : align_line = {line[80 *8-1:  0], 320'd0};
-    line[82 *8-1:81 *8] == 8'd0 : align_line = {line[81 *8-1:  0], 312'd0};
-    line[83 *8-1:82 *8] == 8'd0 : align_line = {line[82 *8-1:  0], 304'd0};
-    line[84 *8-1:83 *8] == 8'd0 : align_line = {line[83 *8-1:  0], 296'd0};
-    line[85 *8-1:84 *8] == 8'd0 : align_line = {line[84 *8-1:  0], 288'd0};
-    line[86 *8-1:85 *8] == 8'd0 : align_line = {line[85 *8-1:  0], 280'd0};
-    line[87 *8-1:86 *8] == 8'd0 : align_line = {line[86 *8-1:  0], 272'd0};
-    line[88 *8-1:87 *8] == 8'd0 : align_line = {line[87 *8-1:  0], 264'd0};
-    line[89 *8-1:88 *8] == 8'd0 : align_line = {line[88 *8-1:  0], 256'd0};
-    line[90 *8-1:89 *8] == 8'd0 : align_line = {line[89 *8-1:  0], 248'd0};
-    line[91 *8-1:90 *8] == 8'd0 : align_line = {line[90 *8-1:  0], 240'd0};
-    line[92 *8-1:91 *8] == 8'd0 : align_line = {line[91 *8-1:  0], 232'd0};
-    line[93 *8-1:92 *8] == 8'd0 : align_line = {line[92 *8-1:  0], 224'd0};
-    line[94 *8-1:93 *8] == 8'd0 : align_line = {line[93 *8-1:  0], 216'd0};
-    line[95 *8-1:94 *8] == 8'd0 : align_line = {line[94 *8-1:  0], 208'd0};
-    line[96 *8-1:95 *8] == 8'd0 : align_line = {line[95 *8-1:  0], 200'd0};
-    line[97 *8-1:96 *8] == 8'd0 : align_line = {line[96 *8-1:  0], 192'd0};
-    line[98 *8-1:97 *8] == 8'd0 : align_line = {line[97 *8-1:  0], 184'd0};
-    line[99 *8-1:98 *8] == 8'd0 : align_line = {line[98 *8-1:  0], 176'd0};
-    line[100*8-1:99 *8] == 8'd0 : align_line = {line[99 *8-1:  0], 168'd0};
-    line[101*8-1:100*8] == 8'd0 : align_line = {line[100*8-1:  0], 160'd0};
-    line[102*8-1:101*8] == 8'd0 : align_line = {line[101*8-1:  0], 152'd0};
-    line[103*8-1:102*8] == 8'd0 : align_line = {line[102*8-1:  0], 144'd0};
-    line[104*8-1:103*8] == 8'd0 : align_line = {line[103*8-1:  0], 136'd0};
-    line[105*8-1:104*8] == 8'd0 : align_line = {line[104*8-1:  0], 128'd0};
-    line[106*8-1:105*8] == 8'd0 : align_line = {line[105*8-1:  0], 120'd0};
-    line[107*8-1:106*8] == 8'd0 : align_line = {line[106*8-1:  0], 112'd0};
-    line[108*8-1:107*8] == 8'd0 : align_line = {line[107*8-1:  0], 104'd0};
-    line[109*8-1:108*8] == 8'd0 : align_line = {line[108*8-1:  0], 96'd0};
-    line[110*8-1:109*8] == 8'd0 : align_line = {line[109*8-1:  0], 88'd0};
-    line[111*8-1:110*8] == 8'd0 : align_line = {line[110*8-1:  0], 80'd0};
-    line[112*8-1:111*8] == 8'd0 : align_line = {line[111*8-1:  0], 72'd0};
-    line[113*8-1:112*8] == 8'd0 : align_line = {line[112*8-1:  0], 64'd0};
-    line[114*8-1:113*8] == 8'd0 : align_line = {line[113*8-1:  0], 56'd0};
-    line[115*8-1:114*8] == 8'd0 : align_line = {line[114*8-1:  0], 48'd0};
-    line[116*8-1:115*8] == 8'd0 : align_line = {line[115*8-1:  0], 40'd0};
-    line[117*8-1:116*8] == 8'd0 : align_line = {line[116*8-1:  0], 32'd0};
-    line[118*8-1:117*8] == 8'd0 : align_line = {line[117*8-1:  0], 24'd0};
-    line[119*8-1:118*8] == 8'd0 : align_line = {line[118*8-1:  0], 16'd0};
-    line[120*8-1:119*8] == 8'd0 : align_line = {line[119*8-1:  0], 8'd0};
-
-    default:                      align_line = 960'd0;
-endcase
-end
-endfunction
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/generic_sram_byte_en.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/generic_sram_byte_en.v
deleted file mode 100644
index 5f5f0f4..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/generic_sram_byte_en.v
+++ /dev/null
@@ -1,82 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Generic Library SRAM with per byte write enable             //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Configurable depth and width. The DATA_WIDTH must be a      //
-//  multiple of 8.                                              //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module generic_sram_byte_en
-#(
-parameter DATA_WIDTH    = 128,
-parameter ADDRESS_WIDTH = 7
-)
-
-(
-input                           i_clk,
-input      [DATA_WIDTH-1:0]     i_write_data,
-input                           i_write_enable,
-input      [ADDRESS_WIDTH-1:0]  i_address,
-input      [DATA_WIDTH/8-1:0]   i_byte_enable,
-output reg [DATA_WIDTH-1:0]     o_read_data
-    );                                                     
-
-reg [DATA_WIDTH-1:0]   mem  [0:2**ADDRESS_WIDTH-1];
-integer i;
-
-always @(posedge i_clk)
-    begin
-    // read
-    o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
-
-    // write
-    if (i_write_enable)
-        for (i=0;i<DATA_WIDTH/8;i=i+1)
-            begin
-            mem[i_address][i*8+0] <= i_byte_enable[i] ? i_write_data[i*8+0] : mem[i_address][i*8+0] ;
-            mem[i_address][i*8+1] <= i_byte_enable[i] ? i_write_data[i*8+1] : mem[i_address][i*8+1] ;
-            mem[i_address][i*8+2] <= i_byte_enable[i] ? i_write_data[i*8+2] : mem[i_address][i*8+2] ;
-            mem[i_address][i*8+3] <= i_byte_enable[i] ? i_write_data[i*8+3] : mem[i_address][i*8+3] ;
-            mem[i_address][i*8+4] <= i_byte_enable[i] ? i_write_data[i*8+4] : mem[i_address][i*8+4] ;
-            mem[i_address][i*8+5] <= i_byte_enable[i] ? i_write_data[i*8+5] : mem[i_address][i*8+5] ;
-            mem[i_address][i*8+6] <= i_byte_enable[i] ? i_write_data[i*8+6] : mem[i_address][i*8+6] ;
-            mem[i_address][i*8+7] <= i_byte_enable[i] ? i_write_data[i*8+7] : mem[i_address][i*8+7] ;
-            end                                                 
-    end
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/generic_sram_line_en.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/generic_sram_line_en.v
deleted file mode 100644
index 13954d2..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/generic_sram_line_en.v
+++ /dev/null
@@ -1,84 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Generic Library SRAM with single write enable               //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Configurable depth and width.                               //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-
-module generic_sram_line_en
-#(
-parameter DATA_WIDTH            = 128,
-parameter ADDRESS_WIDTH         = 7,
-parameter INITIALIZE_TO_ZERO    = 0
-)
-
-(
-input                           i_clk,
-input      [DATA_WIDTH-1:0]     i_write_data,
-input                           i_write_enable,
-input      [ADDRESS_WIDTH-1:0]  i_address,
-output reg [DATA_WIDTH-1:0]     o_read_data
-);                                                     
-
-reg [DATA_WIDTH-1:0]   mem  [0:2**ADDRESS_WIDTH-1];
-
-generate
-if ( INITIALIZE_TO_ZERO ) begin : init0
-integer i;
-initial
-    begin
-    for (i=0;i<2**ADDRESS_WIDTH;i=i+1)
-        mem[i] <= 'd0;
-    end
-end
-endgenerate
-
-    
-always @(posedge i_clk)
-    begin
-    // read
-    o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
-
-    // write
-    if (i_write_enable)
-        mem[i_address] <= i_write_data;
-    end
-    
-    
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/global_defines.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/global_defines.v
deleted file mode 100644
index a7b1173..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/global_defines.v
+++ /dev/null
@@ -1,55 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Global testbench defines                                    //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  Contains a set of defines for each module so if the module  //
-//  hierarchy changes, hierarchical references to signals       //
-//  will still work as long as this file is updated.            //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-// ---------------------------------------------------------------
-// Module hierarchy defines
-// ---------------------------------------------------------------
-
-    
-
-
-        // ---------------------------------------------------------------
-
-
-
-// Simplified Main Memory Model
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/memory_configuration.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/memory_configuration.v
deleted file mode 100644
index 50738ea..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/rtl/memory_configuration.v
+++ /dev/null
@@ -1,159 +0,0 @@
-//////////////////////////////////////////////////////////////////
-//                                                              //
-//  Memory configuration and Wishbone address decoding          //
-//                                                              //
-//  This file is part of the Amber project                      //
-//  http://www.opencores.org/project,amber                      //
-//                                                              //
-//  Description                                                 //
-//  This module provides a set of functions that are used to    //
-//  decode memory addresses so other modules know if an address //
-//  is for example in main memory, or boot memory, or a UART    //
-//                                                              //
-//  Author(s):                                                  //
-//      - Conor Santifort, csantifort.amber@gmail.com           //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-//                                                              //
-// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
-//                                                              //
-// This source file may be used and distributed without         //
-// restriction provided that this copyright statement is not    //
-// removed from the file and that any derivative work contains  //
-// the original copyright notice and the associated disclaimer. //
-//                                                              //
-// This source file is free software; you can redistribute it   //
-// and/or modify it under the terms of the GNU Lesser General   //
-// Public License as published by the Free Software Foundation; //
-// either version 2.1 of the License, or (at your option) any   //
-// later version.                                               //
-//                                                              //
-// This source is distributed in the hope that it will be       //
-// useful, but WITHOUT ANY WARRANTY; without even the implied   //
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
-// PURPOSE.  See the GNU Lesser General Public License for more //
-// details.                                                     //
-//                                                              //
-// You should have received a copy of the GNU Lesser General    //
-// Public License along with this source; if not, download it   //
-// from http://www.opencores.org/lgpl.shtml                     //
-//                                                              //
-//////////////////////////////////////////////////////////////////
-
-// e.g. 24 for 32MBytes, 26 for 128MBytes
-localparam MAIN_MSB             = 26; 
-
-// e.g. 13 for 4k words
-localparam BOOT_MSB             = 13;  
-
-localparam MAIN_BASE            = 32'h0000_0000; /*  Main Memory            */
-localparam BOOT_BASE            = 32'h0000_0000; /*  Cachable Boot Memory   */
-localparam AMBER_TM_BASE        = 16'h1300;      /*  Timers Module          */
-localparam AMBER_IC_BASE        = 16'h1400;      /*  Interrupt Controller   */
-localparam AMBER_UART0_BASE     = 16'h1600;      /*  UART 0                 */
-localparam AMBER_UART1_BASE     = 16'h1700;      /*  UART 1                 */
-localparam ETHMAC_BASE          = 16'h2000;      /*  Ethernet MAC           */
-localparam HIBOOT_BASE          = 32'h2800_0000; /*  Uncachable Boot Memory */
-localparam TEST_BASE            = 16'hf000;      /*  Test Module            */
-
-
-
-function in_loboot_mem;
-    input [31:0] address;
-begin
-in_loboot_mem  = (address >= BOOT_BASE   && 
-                 address < (BOOT_BASE   + 2**(BOOT_MSB+1)-1));
-end
-endfunction
-
-
-function in_hiboot_mem;
-    input [31:0] address;
-begin
-in_hiboot_mem  = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]);
-end
-endfunction
-
-
-function in_boot_mem;
-    input [31:0] address;
-begin
-in_boot_mem  =  in_loboot_mem(address) || in_hiboot_mem(address);
-end
-endfunction
-
-
-function in_main_mem;
-    input [31:0] address;
-begin
-in_main_mem  = (address >= MAIN_BASE   && 
-                address < (MAIN_BASE   + 2**(MAIN_MSB+1)-1)) &&
-                !in_boot_mem ( address );
-end
-endfunction
-
-
-// UART 0 address space
-function in_uart0;
-    input [31:0] address;
-begin
-    in_uart0 = address [31:16] == AMBER_UART0_BASE;
-end
-endfunction
-
-
-// UART 1 address space
-function in_uart1;
-    input [31:0] address;
-begin
-    in_uart1 = address [31:16] == AMBER_UART1_BASE;
-end
-endfunction
-
-
-// Interrupt Controller address space
-function in_ic;
-    input [31:0] address;
-begin
-    in_ic = address [31:16] == AMBER_IC_BASE;
-end
-endfunction
-
-
-// Timer Module address space
-function in_tm;
-    input [31:0] address;
-begin
-    in_tm = address [31:16] == AMBER_TM_BASE;
-end
-endfunction
-
-
-// Test module
-function in_test;
-    input [31:0] address;
-begin
-    in_test = address [31:16] == TEST_BASE;
-end
-endfunction
-
-
-// Ethernet MAC
-function in_ethmac;
-    input [31:0] address;
-begin
-    in_ethmac = address [31:16] == ETHMAC_BASE;
-end
-endfunction
-
-
-// Used in fetch.v and l2cache.v to allow accesses to these addresses
-// to be cached
-function in_cachable_mem;
-    input [31:0] address;
-begin
-    in_cachable_mem = in_loboot_mem     ( address ) || 
-                      in_main_mem       ( address ) ; 
-end
-endfunction
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/sim/bench.v b/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/sim/bench.v
deleted file mode 100644
index e325f19..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/amber23/slpp_unit/work/sim/bench.v
+++ /dev/null
@@ -1,183 +0,0 @@
-
-module testbench;
-
-// Generic Inputs
-reg clk;
-reg i_irq;              // Interrupt request, active high
-reg i_firq;             // Fast Interrupt request, active high
-reg i_system_rdy;       // Amber is stalled when this is low
-reg globrst;
-
-// Wishbone Inputs
-reg [31:0] i_wb_dat;
-wire       i_wb_ack;
-wire       i_wb_err;
-
-// Wishbone Outputs
-wire [31:0] o_wb_adr;
-wire [ 3:0] o_wb_sel;
-wire        o_wb_we;
-wire [31:0] o_wb_dat;
-wire        o_wb_cyc;
-wire        o_wb_stb;
-
-
-a23_core UUT (
-	clk,
-	i_irq,
-	i_firq,
-	i_system_rdy,
-	o_wb_adr,
-	o_wb_sel,
-	o_wb_we,
-	i_wb_dat,
-	o_wb_dat,
-	o_wb_cyc,
-	o_wb_stb,
-	i_wb_ack,
-	i_wb_err,
-	globrst
-);
-
-
-initial begin
-	clk <= 0;
-	#100;
-	forever begin
-		clk <= ~clk;
-		#50;
-	end
-end
-
-initial begin
-	i_irq <= 0;
-	i_firq <= 0;
-	i_wb_dat <= 0;
-	i_system_rdy <= 0;
-	globrst <= 0;
-	repeat (5) @(posedge clk);
-	globrst <= 1;
-	repeat (2) @(posedge clk);
-	globrst <= 0;
-	repeat (3) @(posedge clk);
-	i_system_rdy <= 1;
-	repeat (5000) @(posedge clk);
-	$display("Reached limit of 5000 cpu cycles.");
-	$finish;
-end
-
-integer output_idx;
-reg [7:0] output_buf [1023:0];
-event output_eof;
-
-localparam mem_size = 16*1024; // = 64kB
-reg [31:0] mem [0:mem_size-1];
-reg [31:0] tmp;
-integer i;
-
-initial begin
-	output_idx = 0;
-	for (i=0; i<mem_size; i=i+1)
-		mem[i] = 0;
-mem[   0] = 32'he3a00000;
-mem[   1] = 32'he13ff000;
-mem[   2] = 32'he3a00001;
-mem[   3] = 32'hee030f10;
-mem[   4] = 32'he3a00001;
-mem[   5] = 32'hee020f10;
-mem[   6] = 32'he3a0d801;
-mem[   7] = 32'heb000000;
-mem[   8] = 32'heafffffe;
-mem[   9] = 32'he3a01201;
-mem[  10] = 32'he3a03002;
-mem[  11] = 32'he59f0084;
-mem[  12] = 32'he92d40f0;
-mem[  13] = 32'he3a02003;
-mem[  14] = 32'he5813000;
-mem[  15] = 32'he3a0c001;
-mem[  16] = 32'he3a03000;
-mem[  17] = 32'he1a06001;
-mem[  18] = 32'he1a012a3;
-mem[  19] = 32'he7901101;
-mem[  20] = 32'he203401f;
-mem[  21] = 32'he011141c;
-mem[  22] = 32'h1a00000e;
-mem[  23] = 32'he5862000;
-mem[  24] = 32'he1a01082;
-mem[  25] = 32'he3110001;
-mem[  26] = 32'h0a000008;
-mem[  27] = 32'he2414003;
-mem[  28] = 32'he1a050a4;
-mem[  29] = 32'he355003f;
-mem[  30] = 32'h8a000006;
-mem[  31] = 32'he1a04324;
-mem[  32] = 32'he7907104;
-mem[  33] = 32'he205501f;
-mem[  34] = 32'he187551c;
-mem[  35] = 32'he7805104;
-mem[  36] = 32'he0811002;
-mem[  37] = 32'heafffff2;
-mem[  38] = 32'he2833001;
-mem[  39] = 32'he3530040;
-mem[  40] = 32'he2822002;
-mem[  41] = 32'h1affffe7;
-mem[  42] = 32'he3a00000;
-mem[  43] = 32'he3a03201;
-mem[  44] = 32'he5830000;
-mem[  45] = 32'he8bd80f0;
-mem[  46] = 32'h000000bc;
-mem[  47] = 32'h00000000;
-mem[  48] = 32'h00000000;
-end
-
-reg wb_start_read_d1;
-wire wb_start_write = o_wb_stb &&  o_wb_we && !wb_start_read_d1;
-wire wb_start_read  = o_wb_stb && !o_wb_we && !i_wb_ack;
-assign i_wb_ack = o_wb_stb && ( wb_start_write || wb_start_read_d1 );
-assign i_wb_err = 0;
-
-always @(posedge clk)
-	wb_start_read_d1 <= wb_start_read;
-
-always @(posedge clk) begin
-	if (wb_start_write || wb_start_read) begin
-		if (o_wb_adr < mem_size*4) begin
-			tmp = mem[o_wb_adr >> 2];
-			if (wb_start_write) begin
-				if (o_wb_sel[0]) tmp = { tmp[31:24], tmp[23:16], tmp[15:8], o_wb_dat[7:0] };
-				if (o_wb_sel[1]) tmp = { tmp[31:24], tmp[23:16], o_wb_dat[15:8], tmp[7:0] };
-				if (o_wb_sel[2]) tmp = { tmp[31:24], o_wb_dat[23:16], tmp[15:8], tmp[7:0] };
-				if (o_wb_sel[3]) tmp = { o_wb_dat[31:24], tmp[23:16], tmp[15:8], tmp[7:0] };
-				mem[o_wb_adr >> 2] <= tmp;
-			end
-			if (wb_start_read)
-				i_wb_dat <= tmp;
-			$display("%t MEM %s ADDR %08x: %08x (%b)", $time, o_wb_we ? "WRITE" : "READ ", o_wb_adr, tmp, o_wb_sel);
-		end
-		if (wb_start_write && o_wb_adr == 32'h10000000) begin
-			$display("%t OUTPUT %d", $time, o_wb_dat);
-			if (o_wb_dat == 0) begin
-				-> output_eof;
-			end else begin
-				output_buf[output_idx] = o_wb_dat;
-				output_idx = output_idx + 1;
-			end
-		end
-	end
-end
-
-always @(output_eof) begin
-	#1001;
-	$display("Got EOF marker on IO port.");
-	for (i = 0; i < output_idx; i = i + 1) begin
-		$display("+OUT+ %d", output_buf[i]);
-	end
-	$finish;
-end
-
-initial begin
-	// $dumpfile("bench.vcd");
-	// $dumpvars(0, testbench);
-end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/surelog.log b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/surelog.log
deleted file mode 100644
index 9d9c789..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/surelog.log
+++ /dev/null
@@ -1,208 +0,0 @@
-********************************************
-*  SURELOG System Verilog Compiler/Linter  *
-********************************************
-
-Copyright (c) 2017-2019 ACE Cloud,
-Authorized used only.
-
-VERSION: 0.05
-BUILT  : Nov  3 2019
-DATE   : 2019-11-03.21:41:27
-COMMAND: -writepp -parse -mt max -nopython -fileunit rtl/lm32_adder.v rtl/lm32_addsub.v rtl/lm32_config.v rtl/lm32_cpu.v rtl/lm32_dcache.v rtl/lm32_debug.v rtl/lm32_decoder.v rtl/lm32_dp_ram.v rtl/lm32_dtlb.v rtl/lm32_icache.v rtl/lm32_include.v rtl/lm32_instruction_unit.v rtl/lm32_interrupt.v rtl/lm32_itlb.v rtl/lm32_jtag.v rtl/lm32_load_store_unit.v rtl/lm32_logic_op.v rtl/lm32_mc_arithmetic.v rtl/lm32_multiplier.v rtl/lm32_ram.v rtl/lm32_shifter.v rtl/lm32_top.v sim/tb_lm32_system.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
-
-[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
-
-[INFO :CM0024] Executing with 4 threads.
-
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[ERROR:PP0107] rtl/lm32_dcache.v:118 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_dcache.v:119 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_dcache.v:129 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_dtlb.v:89 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_dtlb.v:90 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_icache.v:128 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_icache.v:129 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_icache.v:139 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_instruction_unit.v:196 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_itlb.v:88 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_itlb.v:89 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[ERROR:PP0107] rtl/lm32_load_store_unit.v:159 Too many arguments (1) for macro "CLOG2",
-               ./rtl/lm32_config.v:57 macro definition takes 0.
-
-[WARNI:PA0205] rtl/lm32_addsub.v:54 No timescale set for "lm32_addsub".
-
-[WARNI:PA0205] rtl/lm32_adder.v:55 No timescale set for "lm32_adder".
-
-[WARNI:PA0205] rtl/lm32_decoder.v:65 No timescale set for "lm32_decoder".
-
-[WARNI:PA0205] rtl/lm32_dcache.v:62 No timescale set for "lm32_dcache".
-
-[WARNI:PA0205] rtl/lm32_icache.v:67 No timescale set for "lm32_icache".
-
-[WARNI:PA0205] rtl/lm32_debug.v:61 No timescale set for "lm32_debug".
-
-[WARNI:PA0205] rtl/lm32_dp_ram.v:36 No timescale set for "lm32_dp_ram".
-
-[WARNI:PA0205] rtl/lm32_dtlb.v:41 No timescale set for "lm32_dtlb".
-
-[WARNI:PA0205] rtl/lm32_itlb.v:40 No timescale set for "lm32_itlb".
-
-[WARNI:PA0205] rtl/lm32_logic_op.v:55 No timescale set for "lm32_logic_op".
-
-[WARNI:PA0205] rtl/lm32_multiplier.v:55 No timescale set for "lm32_multiplier".
-
-[WARNI:PA0205] rtl/lm32_shifter.v:55 No timescale set for "lm32_shifter".
-
-[WARNI:PA0205] rtl/lm32_interrupt.v:55 No timescale set for "lm32_interrupt".
-
-[WARNI:PA0205] rtl/lm32_instruction_unit.v:76 No timescale set for "lm32_instruction_unit".
-
-[WARNI:PA0205] rtl/lm32_load_store_unit.v:68 No timescale set for "lm32_load_store_unit".
-
-[WARNI:PA0205] rtl/lm32_mc_arithmetic.v:56 No timescale set for "lm32_mc_arithmetic".
-
-[WARNI:PA0205] rtl/lm32_ram.v:60 No timescale set for "lm32_ram".
-
-[WARNI:PA0205] rtl/lm32_top.v:55 No timescale set for "lm32_top".
-
-[WARNI:PA0205] rtl/lm32_cpu.v:98 No timescale set for "lm32_cpu".
-
-[WARNI:PA0205] sim/tb_lm32_system.v:33 No timescale set for "testbench".
-
-[INFO :CP0300] Compilation...
-
-[INFO :CP0303] rtl/lm32_adder.v:55 Compile module "work@lm32_adder".
-
-[INFO :CP0303] rtl/lm32_cpu.v:98 Compile module "work@lm32_cpu".
-
-[INFO :CP0303] rtl/lm32_dcache.v:62 Compile module "work@lm32_dcache".
-
-[INFO :CP0303] rtl/lm32_addsub.v:54 Compile module "work@lm32_addsub".
-
-[INFO :CP0303] rtl/lm32_debug.v:61 Compile module "work@lm32_debug".
-
-[INFO :CP0303] rtl/lm32_decoder.v:65 Compile module "work@lm32_decoder".
-
-[INFO :CP0303] rtl/lm32_icache.v:67 Compile module "work@lm32_icache".
-
-[INFO :CP0303] rtl/lm32_dtlb.v:41 Compile module "work@lm32_dtlb".
-
-[INFO :CP0303] rtl/lm32_load_store_unit.v:68 Compile module "work@lm32_load_store_unit".
-
-[INFO :CP0303] rtl/lm32_itlb.v:40 Compile module "work@lm32_itlb".
-
-[INFO :CP0303] rtl/lm32_instruction_unit.v:76 Compile module "work@lm32_instruction_unit".
-
-[INFO :CP0303] rtl/lm32_multiplier.v:55 Compile module "work@lm32_multiplier".
-
-[INFO :CP0303] sim/tb_lm32_system.v:33 Compile module "work@testbench".
-
-[INFO :CP0303] rtl/lm32_dp_ram.v:36 Compile module "work@lm32_dp_ram".
-
-[INFO :CP0303] rtl/lm32_ram.v:60 Compile module "work@lm32_ram".
-
-[INFO :CP0303] rtl/lm32_interrupt.v:55 Compile module "work@lm32_interrupt".
-
-[INFO :CP0303] rtl/lm32_logic_op.v:55 Compile module "work@lm32_logic_op".
-
-[INFO :CP0303] rtl/lm32_mc_arithmetic.v:56 Compile module "work@lm32_mc_arithmetic".
-
-[INFO :CP0303] rtl/lm32_shifter.v:55 Compile module "work@lm32_shifter".
-
-[INFO :CP0303] rtl/lm32_top.v:55 Compile module "work@lm32_top".
-
-[NOTE :CP0309] rtl/lm32_adder.v:62 Implicit port type (wire) for "adder_result_x",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_debug.v:81 Implicit port type (wire) for "bp_match",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_icache.v:83 Implicit port type (wire) for "stall_request",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_load_store_unit.v:106 Implicit port type (wire) for "dcache_refill_request",
-there are 8 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_ram.v:72 Implicit port type (wire) for "read_data".
-
-[NOTE :CP0309] rtl/lm32_addsub.v:61 Implicit port type (wire) for "Result",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_decoder.v:80 Implicit port type (wire) for "x_bypass_enable",
-there are 28 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_instruction_unit.v:116 Implicit port type (wire) for "icache_stall_request",
-there are 11 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_shifter.v:65 Implicit port type (wire) for "shifter_result_m".
-
-[NOTE :CP0309] rtl/lm32_cpu.v:118 Implicit port type (wire) for "I_DAT_O",
-there are 17 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_dp_ram.v:49 Implicit port type (wire) for "do_a",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_interrupt.v:71 Implicit port type (wire) for "interrupt_exception".
-
-[NOTE :CP0309] rtl/lm32_mc_arithmetic.v:69 Implicit port type (wire) for "stall_request_x".
-
-[NOTE :CP0309] rtl/lm32_top.v:75 Implicit port type (wire) for "I_DAT_O",
-there are 17 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_dcache.v:80 Implicit port type (wire) for "stall_request",
-there are 1 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_dtlb.v:62 Implicit port type (wire) for "physical_load_store_address_m",
-there are 5 more instances of this message.
-
-[NOTE :CP0309] rtl/lm32_itlb.v:60 Implicit port type (wire) for "stall_request",
-there are 2 more instances of this message.
-
-[INFO :EL0526] Design Elaboration...
-
-[NOTE :EL0503] rtl/lm32_dp_ram.v:36 Top level module "work@lm32_dp_ram".
-
-[NOTE :EL0503] sim/tb_lm32_system.v:33 Top level module "work@testbench".
-
-[NOTE :EL0504] Multiple top level modules in design.
-
-[NOTE :EL0508] Nb Top level modules: 2.
-
-[NOTE :EL0509] Max instance depth: 8.
-
-[NOTE :EL0510] Nb instances: 27.
-
-[NOTE :EL0511] Nb leaf instances: 10.
-
-[  FATAL] : 0
-[  ERROR] : 12
-[WARNING] : 20
-[   NOTE] : 24
-
-********************************************
-*   End SURELOG SVerilog Compiler/Linter   *
-********************************************
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_adder.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_adder.v
deleted file mode 100644
index e20946b..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_adder.v
+++ /dev/null
@@ -1,298 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_adder.v
-// Title            : Integer adder / subtractor with comparison flag generation
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_adder (
-    // ----- Inputs -------
-    adder_op_x,
-    adder_op_x_n,
-    operand_0_x,
-    operand_1_x,
-    // ----- Outputs -------
-    adder_result_x,
-    adder_carry_n_x,
-    adder_overflow_x
-    );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
-input adder_op_x_n;                                     // Inverted version of adder_op_x
-input [(32-1):0] operand_0_x;                     // Operand to add, or subtract from
-input [(32-1):0] operand_1_x;                     // Opearnd to add, or subtract by
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [(32-1):0] adder_result_x;                 // Result of addition or subtraction
-wire   [(32-1):0] adder_result_x;
-output adder_carry_n_x;                                 // Inverted carry
-wire   adder_carry_n_x;
-output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
-reg    adder_overflow_x;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
-wire b_sign;                                            // Sign of operand 1
-wire result_sign;                                       // Sign of result
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-lm32_addsub addsub (
-    // ----- Inputs -----
-    .DataA          (operand_0_x),
-    .DataB          (operand_1_x),
-    .Cin            (adder_op_x),
-    .Add_Sub        (adder_op_x_n),
-    // ----- Ouputs -----
-    .Result         (adder_result_x),
-    .Cout           (adder_carry_n_x)
-    );
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-// Extract signs of operands and result
-
-assign a_sign = operand_0_x[32-1];
-assign b_sign = operand_1_x[32-1];
-assign result_sign = adder_result_x[32-1];
-
-// Determine whether an overflow occured when performing a subtraction
-
-always @(*)
-begin
-    //  +ve - -ve = -ve -> overflow
-    //  -ve - +ve = +ve -> overflow
-    if  (   (!a_sign & b_sign & result_sign)
-         || (a_sign & !b_sign & !result_sign)
-        )
-        adder_overflow_x = 1'b1;
-    else
-        adder_overflow_x = 1'b0;
-end
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_addsub.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_addsub.v
deleted file mode 100644
index c3290a9..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_addsub.v
+++ /dev/null
@@ -1,257 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_addsub.v
-// Title            : PMI adder/subtractor.
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_addsub (
-    // ----- Inputs -------
-    DataA,
-    DataB,
-    Cin,
-    Add_Sub,
-    // ----- Outputs -------
-    Result,
-    Cout
-    );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input [31:0] DataA;
-input [31:0] DataB;
-input Cin;
-input Add_Sub;
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [31:0] Result;
-wire   [31:0] Result;
-output Cout;
-wire   Cout;
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-// Modified for Milkymist: removed non-portable instantiated block
-wire [32:0] tmp_addResult = DataA + DataB + Cin;
-wire [32:0] tmp_subResult = DataA - DataB - !Cin;
-
-assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
-assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_config.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_config.v
deleted file mode 100644
index 95a31c2..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_config.v
+++ /dev/null
@@ -1,13 +0,0 @@
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_cpu.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_cpu.v
deleted file mode 100644
index 659ecc9..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_cpu.v
+++ /dev/null
@@ -1,2172 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   Copyright (c) 2011-2012 Yann Sionneau <yann.sionneau@gmail.com>
-//   Copyright (c) 2012 Michael Walle <michael@walle.cc>
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_cpu.v
-// Title            : Top-level of CPU.
-// Dependencies     : lm32_include.v
-//
-// Version 3.8
-// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO.
-// 2. Bug: EA now reports instruction that caused the data abort, rather than
-//    next instruction.
-//
-// Version 3.4
-// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were
-//    never serviced.
-//
-// Version 3.3
-// 1. Feature: Support for memory that is tightly coupled to processor core, and
-//    has a single-cycle access latency (same as caches). Instruction port has
-//    access to a dedicated physically-mapped memory. Data port has access to
-//    a dedicated physically-mapped memory. In order to be able to manipulate
-//    values in both these memories via the debugger, these memories also
-//    interface with the data port of LM32.
-// 2. Feature: Extended Configuration Register
-// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
-//    Verilog.
-//
-// Version 3.2
-// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
-//    hang. At the same time CPU fails to register data bus error exception. Bug
-//    is caused because (a) data bus error exception occurs after load/store has
-//    passed X stage and next sequential instruction (e.g., brk) is already in X
-//    stage, and (b) data bus error exception had lower priority than, say, brk
-//    exception.
-// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
-//    invalid location, CPU will fail to register data bus error exception. The
-//    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
-//    until load/store has completed.
-// 3. Feature: Enable precise identification of load/store that causes seg fault.
-// 4. SYNC resets used for register file when implemented in EBRs.
-//
-// Version 3.1
-// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
-//    instead of distributed memory by enabling the option in LM32 GUI.
-// 2. Feature: LM32 also adds a static branch predictor to improve branch
-//    performance. All immediate-based forward-pointing branches are predicted
-//    not-taken. All immediate-based backward-pointing branches are predicted taken.
-//
-// Version 7.0SP2, 3.0
-// No Change
-//
-// Version 6.1.17
-// Initial Release
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_cpu (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    // From external devices
-    interrupt,
-    // From user logic
-    ext_break,
-    // Instruction Wishbone master
-    I_DAT_I,
-    I_ACK_I,
-    I_ERR_I,
-    I_RTY_I,
-    // Data Wishbone master
-    D_DAT_I,
-    D_ACK_I,
-    D_ERR_I,
-    D_RTY_I,
-    // ----- Outputs -------
-    // Instruction Wishbone master
-    I_DAT_O,
-    I_ADR_O,
-    I_CYC_O,
-    I_SEL_O,
-    I_STB_O,
-    I_WE_O,
-    I_CTI_O,
-    I_LOCK_O,
-    I_BTE_O,
-    // Data Wishbone master
-    D_DAT_O,
-    D_ADR_O,
-    D_CYC_O,
-    D_SEL_O,
-    D_STB_O,
-    D_WE_O,
-    D_CTI_O,
-    D_LOCK_O,
-    D_BTE_O
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter eba_reset = 32'h0;                           // Reset value for EBA CSR
-parameter deba_reset = 32'h0;                         // Reset value for DEBA CSR
-
-parameter icache_associativity = 1;     // Associativity of the cache (Number of ways)
-parameter icache_sets = 256;                       // Number of sets
-parameter icache_bytes_per_line = 16;   // Number of bytes per cache line
-parameter icache_base_address = 32'h0;       // Base address of cachable memory
-parameter icache_limit = 32'h7fffffff;                     // Limit (highest address) of cachable memory
-
-parameter dcache_associativity = 1;     // Associativity of the cache (Number of ways)
-parameter dcache_sets = 256;                       // Number of sets
-parameter dcache_bytes_per_line = 16;   // Number of bytes per cache line
-parameter dcache_base_address = 32'h0;       // Base address of cachable memory
-parameter dcache_limit = 32'h7fffffff;                     // Limit (highest address) of cachable memory
-
-parameter watchpoints = 32'h4;                       // Number of h/w watchpoint CSRs
-parameter breakpoints = 32'h4;                       // Number of h/w breakpoint CSRs
-
-parameter interrupts = 32;                         // Number of interrupts
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                    // Clock
-input rst_i;                                    // Reset
-
-
-input [(32-1):0] interrupt;          // Interrupt pins
-
-
-
-input [(32-1):0] I_DAT_I;                 // Instruction Wishbone interface read data
-input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
-input I_ERR_I;                                  // Instruction Wishbone interface error
-input I_RTY_I;                                  // Instruction Wishbone interface retry
-
-input [(32-1):0] D_DAT_I;                 // Data Wishbone interface read data
-input D_ACK_I;                                  // Data Wishbone interface acknowledgement
-input D_ERR_I;                                  // Data Wishbone interface error
-input D_RTY_I;                                  // Data Wishbone interface retry
-
-input ext_break;
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-
-
-
-output [(32-1):0] I_DAT_O;                // Instruction Wishbone interface write data
-wire   [(32-1):0] I_DAT_O;
-output [(32-1):0] I_ADR_O;                // Instruction Wishbone interface address
-wire   [(32-1):0] I_ADR_O;
-output I_CYC_O;                                 // Instruction Wishbone interface cycle
-wire   I_CYC_O;
-output [(4-1):0] I_SEL_O;         // Instruction Wishbone interface byte select
-wire   [(4-1):0] I_SEL_O;
-output I_STB_O;                                 // Instruction Wishbone interface strobe
-wire   I_STB_O;
-output I_WE_O;                                  // Instruction Wishbone interface write enable
-wire   I_WE_O;
-output [(3-1):0] I_CTI_O;               // Instruction Wishbone interface cycle type
-wire   [(3-1):0] I_CTI_O;
-output I_LOCK_O;                                // Instruction Wishbone interface lock bus
-wire   I_LOCK_O;
-output [(2-1):0] I_BTE_O;               // Instruction Wishbone interface burst type
-wire   [(2-1):0] I_BTE_O;
-
-output [(32-1):0] D_DAT_O;                // Data Wishbone interface write data
-wire   [(32-1):0] D_DAT_O;
-output [(32-1):0] D_ADR_O;                // Data Wishbone interface address
-wire   [(32-1):0] D_ADR_O;
-output D_CYC_O;                                 // Data Wishbone interface cycle
-wire   D_CYC_O;
-output [(4-1):0] D_SEL_O;         // Data Wishbone interface byte select
-wire   [(4-1):0] D_SEL_O;
-output D_STB_O;                                 // Data Wishbone interface strobe
-wire   D_STB_O;
-output D_WE_O;                                  // Data Wishbone interface write enable
-wire   D_WE_O;
-output [(3-1):0] D_CTI_O;               // Data Wishbone interface cycle type
-wire   [(3-1):0] D_CTI_O;
-output D_LOCK_O;                                // Date Wishbone interface lock bus
-wire   D_LOCK_O;
-output [(2-1):0] D_BTE_O;               // Data Wishbone interface burst type
-wire   [(2-1):0] D_BTE_O;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-// Pipeline registers
-
-reg valid_a;                                    // Instruction in A stage is valid
-reg valid_f;                                    // Instruction in F stage is valid
-reg valid_d;                                    // Instruction in D stage is valid
-reg valid_x;                                    // Instruction in X stage is valid
-reg valid_m;                                    // Instruction in M stage is valid
-reg valid_w;                                    // Instruction in W stage is valid
-
-wire q_x;
-wire [(32-1):0] immediate_d;              // Immediate operand
-wire load_d;                                    // Indicates a load instruction
-reg load_x;
-reg load_m;
-wire load_q_x;
-wire store_q_x;
-wire store_d;                                   // Indicates a store instruction
-reg store_x;
-reg store_m;
-wire [1:0] size_d;                   // Size of load/store (byte, hword, word)
-reg [1:0] size_x;
-wire branch_d;                                  // Indicates a branch instruction
-wire branch_predict_d;                          // Indicates a branch is predicted
-wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
-wire [((32-2)+2-1):2] branch_predict_address_d;   // Address to which predicted branch jumps
-wire [((32-2)+2-1):2] branch_target_d;
-wire bi_unconditional;
-wire bi_conditional;
-reg branch_x;
-reg branch_predict_x;
-reg branch_predict_taken_x;
-reg branch_m;
-reg branch_predict_m;
-reg branch_predict_taken_m;
-wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
-wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
-wire branch_reg_d;                              // Branch to register or immediate
-wire [((32-2)+2-1):2] branch_offset_d;            // Branch offset for immediate branches
-reg [((32-2)+2-1):2] branch_target_x;             // Address to branch to
-reg [((32-2)+2-1):2] branch_target_m;
-wire [0:0] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
-wire [1:0] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
-
-wire x_result_sel_csr_d;                        // Select X stage result from CSRs
-reg x_result_sel_csr_x;
-wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
-reg x_result_sel_mc_arith_x;
-wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
-reg x_result_sel_sext_x;
-wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
-reg x_result_sel_logic_x;
-wire x_result_sel_add_d;                        // Select X stage result from adder
-reg x_result_sel_add_x;
-wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
-reg m_result_sel_compare_x;
-reg m_result_sel_compare_m;
-wire m_result_sel_shift_d;                      // Select M stage result from shifter
-reg m_result_sel_shift_x;
-reg m_result_sel_shift_m;
-wire w_result_sel_load_d;                       // Select W stage result from load/store unit
-reg w_result_sel_load_x;
-reg w_result_sel_load_m;
-reg w_result_sel_load_w;
-wire w_result_sel_mul_d;                        // Select W stage result from multiplier
-reg w_result_sel_mul_x;
-reg w_result_sel_mul_m;
-reg w_result_sel_mul_w;
-wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
-reg x_bypass_enable_x;
-wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
-reg m_bypass_enable_x;
-reg m_bypass_enable_m;
-wire sign_extend_d;                             // Whether to sign-extend or zero-extend
-reg sign_extend_x;
-wire write_enable_d;                            // Register file write enable
-reg write_enable_x;
-wire write_enable_q_x;
-reg write_enable_m;
-wire write_enable_q_m;
-reg write_enable_w;
-wire write_enable_q_w;
-wire read_enable_0_d;                           // Register file read enable 0
-wire [(5-1):0] read_idx_0_d;          // Register file read index 0
-wire read_enable_1_d;                           // Register file read enable 1
-wire [(5-1):0] read_idx_1_d;          // Register file read index 1
-wire [(5-1):0] write_idx_d;           // Register file write index
-reg [(5-1):0] write_idx_x;
-reg [(5-1):0] write_idx_m;
-reg [(5-1):0] write_idx_w;
-wire [(5-1):0] csr_d;                     // CSR read/write index
-reg  [(5-1):0] csr_x;
-wire [(3-1):0] condition_d;         // Branch condition
-reg [(3-1):0] condition_x;
-wire break_d;                                   // Indicates a break instruction
-reg break_x;
-wire scall_d;                                   // Indicates a scall instruction
-reg scall_x;
-wire eret_d;                                    // Indicates an eret instruction
-reg eret_x;
-wire eret_q_x;
-wire eret_k_q_x;
-reg eret_m;
-wire bret_d;                                    // Indicates a bret instruction
-reg bret_x;
-wire bret_q_x;
-wire bret_k_q_x;
-reg bret_m;
-wire csr_write_enable_d;                        // CSR write enable
-reg csr_write_enable_x;
-wire csr_write_enable_q_x;
-wire csr_write_enable_k_q_x;
-
-wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
-reg bus_error_x;
-reg data_bus_error_exception_m;
-reg [((32-2)+2-1):2] memop_pc_w;
-
-reg [(32-1):0] d_result_0;                // Result of instruction in D stage (operand 0)
-reg [(32-1):0] d_result_1;                // Result of instruction in D stage (operand 1)
-reg [(32-1):0] x_result;                  // Result of instruction in X stage
-reg [(32-1):0] m_result;                  // Result of instruction in M stage
-reg [(32-1):0] w_result;                  // Result of instruction in W stage
-
-reg [(32-1):0] operand_0_x;               // Operand 0 for X stage instruction
-reg [(32-1):0] operand_1_x;               // Operand 1 for X stage instruction
-reg [(32-1):0] store_operand_x;           // Data read from register to store
-reg [(32-1):0] operand_m;                 // Operand for M stage instruction
-reg [(32-1):0] operand_w;                 // Operand for W stage instruction
-
-// To/from register file
-reg [(32-1):0] reg_data_live_0;
-reg [(32-1):0] reg_data_live_1;
-reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
-reg [(32-1):0] reg_data_buf_0;
-reg [(32-1):0] reg_data_buf_1;
-wire [(32-1):0] reg_data_0;               // Register file read port 0 data
-wire [(32-1):0] reg_data_1;               // Register file read port 1 data
-reg [(32-1):0] bypass_data_0;             // Register value 0 after bypassing
-reg [(32-1):0] bypass_data_1;             // Register value 1 after bypassing
-wire reg_write_enable_q_w;
-
-reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
-
-wire stall_a;                                   // Stall instruction in A pipeline stage
-wire stall_f;                                   // Stall instruction in F pipeline stage
-wire stall_d;                                   // Stall instruction in D pipeline stage
-wire stall_x;                                   // Stall instruction in X pipeline stage
-wire stall_m;                                   // Stall instruction in M pipeline stage
-
-// To/from adder
-wire adder_op_d;                                // Whether to add or subtract
-reg adder_op_x;
-reg adder_op_x_n;                               // Inverted version of adder_op_x
-wire [(32-1):0] adder_result_x;           // Result from adder
-wire adder_overflow_x;                          // Whether a signed overflow occured
-wire adder_carry_n_x;                           // Whether a carry was generated
-
-// To/from logical operations unit
-wire [3:0] logic_op_d;           // Which operation to perform
-reg [3:0] logic_op_x;
-wire [(32-1):0] logic_result_x;           // Result of logical operation
-
-// From sign-extension unit
-wire [(32-1):0] sextb_result_x;           // Result of byte sign-extension
-wire [(32-1):0] sexth_result_x;           // Result of half-word sign-extenstion
-wire [(32-1):0] sext_result_x;            // Result of sign-extension specified by instruction
-
-// To/from shifter
-wire direction_d;                               // Which direction to shift in
-reg direction_x;
-wire [(32-1):0] shifter_result_m;         // Result of shifter
-
-// To/from multiplier
-wire [(32-1):0] multiplier_result_w;      // Result from multiplier
-
-// To/from divider
-wire divide_d;                                  // Indicates whether to perform a divider or not
-wire divide_q_d;
-wire modulus_d;
-wire modulus_q_d;
-wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
-
-// To from multi-cycle arithmetic unit
-wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
-wire [(32-1):0] mc_result_x;
-
-// From CSRs
-wire [(32-1):0] interrupt_csr_read_data_x;// Data read from interrupt CSRs
-wire [(32-1):0] cfg;                      // Configuration CSR
-wire [(32-1):0] cfg2;                     // Extended Configuration CSR
-wire [(32-1):0] psw;                      // Processor Status Word CSR
-reg [(32-1):0] csr_read_data_x;           // Data read from CSRs
-
-// To/from instruction unit
-wire [((32-2)+2-1):2] pc_f;                       // PC of instruction in F stage
-wire [((32-2)+2-1):2] pc_d;                       // PC of instruction in D stage
-wire [((32-2)+2-1):2] pc_x;                       // PC of instruction in X stage
-wire [((32-2)+2-1):2] pc_m;                       // PC of instruction in M stage
-wire [((32-2)+2-1):2] pc_w;                       // PC of instruction in W stage
-wire [(32-1):0] instruction_f;     // Instruction in F stage
-//pragma attribute instruction_d preserve_signal true
-//pragma attribute instruction_d preserve_driver true
-wire [(32-1):0] instruction_d;     // Instruction in D stage
-wire iflush;                                    // Flush instruction cache
-wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
-wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
-wire icache_refill_request;                     // Request to refill instruction cache
-wire icache_refilling;                          // Indicates the instruction cache is being refilled
-
-// To/from load/store unit
-wire dflush_x;                                  // Flush data cache
-reg dflush_m;
-wire dcache_stall_request;                      // Stall pipeline because data cache is busy
-wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
-wire dcache_refill_request;                     // Request to refill data cache
-wire dcache_refilling;                          // Indicates the data cache is being refilled
-wire [(32-1):0] load_data_w;              // Result of a load instruction
-wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
-
-// To/from JTAG interface
-
-// Hazzard detection
-wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
-wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
-wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
-wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
-wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
-wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
-
-// Control flow
-wire cmp_zero;                                  // Result of comparison is zero
-wire cmp_negative;                              // Result of comparison is negative
-wire cmp_overflow;                              // Comparison produced an overflow
-wire cmp_carry_n;                               // Comparison produced a carry, inverted
-reg condition_met_x;                            // Condition of branch instruction is met
-reg condition_met_m;
-wire branch_taken_m;                            // Branch is taken in M stage
-
-wire kill_f;                                    // Kill instruction in F stage
-wire kill_d;                                    // Kill instruction in D stage
-wire kill_x;                                    // Kill instruction in X stage
-wire kill_m;                                    // Kill instruction in M stage
-wire kill_w;                                    // Kill instruction in W stage
-
-reg [((32-2)+2-1):(4+3+2)] eba;                        // Exception Base Address (EBA) CSR
-reg [((32-2)+2-1):(4+3+2)] deba;                       // Debug Exception Base Address (DEBA) CSR
-reg [(4-1):0] eid_x;                      // Exception ID in X stage
-
-wire dc_ss;                                     // Is single-step enabled
-wire dc_re;                                     // Remap all exceptions
-wire exception_x;                               // An exception occured in the X stage
-reg exception_m;                                // An instruction that caused an exception is in the M stage
-wire debug_exception_x;                         // Indicates if a debug exception has occured
-reg debug_exception_m;
-reg debug_exception_w;
-wire debug_exception_q_w;
-wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
-reg non_debug_exception_m;
-reg non_debug_exception_w;
-wire non_debug_exception_q_w;
-
-wire interrupt_exception;                       // Indicates if an interrupt exception has occured
-wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
-wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
-wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
-wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
-wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
-wire system_call_exception;                     // Indicates if a system call exception has occured
-
-reg data_bus_error_seen;                        // Indicates if a data bus error was seen
-
-reg ext_break_r;
-
-reg itlbe;                                      // Instruction TLB enable
-reg dtlbe;                                      // Data TLB enable
-reg usr;                                        // User mode
-reg eitlbe;                                     // Exception instruction enable
-reg edtlbe;                                     // Exception data TLB enable
-reg eusr;                                       // Exception user mode
-reg bitlbe;                                     // Breakpoint instruction TLB enable
-reg bdtlbe;                                     // Breakpoint data TLB enable
-reg busr;                                       // Breakpoint user mode
-
-reg itlb_invalidate;                            // Invalidate an ITLB entry
-reg itlb_flush;                                 // Flush all ITLB entries
-reg itlb_update;                                // Update an ITLB entry
-reg dtlb_invalidate;                            // Invalidate a DTLB entry
-reg dtlb_flush;                                 // Flush all DTLB entries
-reg dtlb_update;                                // Update an DTLB entry
-reg [(32-1):0] tlbpaddr;                  // TLBPADDR CSR
-reg [(32-1):0] tlbvaddr;                  // TLBVADDR CSR
-reg [(32-1):0] tlbbadvaddr;               // TLBBADVADDR CSR
-wire [(32-1):0] dtlb_miss_vfn;            // VFN of the missed address
-wire [(32-1):0] itlb_miss_vfn;            // VFN of the missed instruction
-wire itlb_miss_x;                               // Indicates if an ITLB miss has occured in the X stage
-wire itlb_stall_request;                        // Stall pipeline because instruction TLB is busy
-wire dtlb_miss_x;                               // Indicates if an DTLB miss has occured in the X stage
-wire dtlb_fault_x;                              // Indicates if an DTLB fault has occured in the X stage
-wire dtlb_stall_request;                        // Stall pipeline because data TLB is busy
-
-wire itlb_miss_exception;                       // Indicates if an ITLB miss exception has occured
-wire itlb_exception;                            // Indicates if an ITLB exception has occured
-wire dtlb_miss_exception;                       // Indicates if a DTLB miss exception has occured
-wire dtlb_fault_exception;                      // Indicates if a DTLB fault exception has occured
-wire dtlb_exception;                            // Indicates if a DTLB exception has occured
-wire privilege_exception;                       // Indicates if a privilege exception has occured
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-// Instruction unit
-lm32_instruction_unit #(
-    .eba_reset              (eba_reset),
-    .associativity          (icache_associativity),
-    .sets                   (icache_sets),
-    .bytes_per_line         (icache_bytes_per_line),
-    .base_address           (icache_base_address),
-    .limit                  (icache_limit)
-  ) instruction_unit (
-    // ----- Inputs -------
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    // From pipeline
-    .stall_a                (stall_a),
-    .stall_f                (stall_f),
-    .stall_d                (stall_d),
-    .stall_x                (stall_x),
-    .stall_m                (stall_m),
-    .valid_f                (valid_f),
-    .valid_d                (valid_d),
-    .kill_f                 (kill_f),
-    .branch_predict_taken_d (branch_predict_taken_d),
-    .branch_predict_address_d (branch_predict_address_d),
-    .exception_m            (exception_m),
-    .branch_taken_m         (branch_taken_m),
-    .branch_mispredict_taken_m (branch_mispredict_taken_m),
-    .branch_target_m        (branch_target_m),
-    .iflush                 (iflush),
-    .dcache_restart_request (dcache_restart_request),
-    .dcache_refill_request  (dcache_refill_request),
-    .dcache_refilling       (dcache_refilling),
-    .itlb_enable            (itlbe),
-    .tlbpaddr               (tlbpaddr),
-    .tlbvaddr               (tlbvaddr),
-    .itlb_update            (itlb_update),
-    .itlb_flush             (itlb_flush),
-    .itlb_invalidate        (itlb_invalidate),
-    // From Wishbone
-    .i_dat_i                (I_DAT_I),
-    .i_ack_i                (I_ACK_I),
-    .i_err_i                (I_ERR_I),
-    // ----- Outputs -------
-    // To pipeline
-    .pc_f                   (pc_f),
-    .pc_d                   (pc_d),
-    .pc_x                   (pc_x),
-    .pc_m                   (pc_m),
-    .pc_w                   (pc_w),
-    .icache_stall_request   (icache_stall_request),
-    .icache_restart_request (icache_restart_request),
-    .icache_refill_request  (icache_refill_request),
-    .icache_refilling       (icache_refilling),
-    .itlb_stall_request     (itlb_stall_request),
-    .itlb_miss_vfn          (itlb_miss_vfn),
-    .itlb_miss_x            (itlb_miss_x),
-    // To Wishbone
-    .i_dat_o                (I_DAT_O),
-    .i_adr_o                (I_ADR_O),
-    .i_cyc_o                (I_CYC_O),
-    .i_sel_o                (I_SEL_O),
-    .i_stb_o                (I_STB_O),
-    .i_we_o                 (I_WE_O),
-    .i_cti_o                (I_CTI_O),
-    .i_lock_o               (I_LOCK_O),
-    .i_bte_o                (I_BTE_O),
-    .bus_error_d            (bus_error_d),
-    .instruction_f          (instruction_f),
-    .instruction_d          (instruction_d)
-    );
-
-// Instruction decoder
-lm32_decoder decoder (
-    // ----- Inputs -------
-    .instruction            (instruction_d),
-    // ----- Outputs -------
-    .d_result_sel_0         (d_result_sel_0_d),
-    .d_result_sel_1         (d_result_sel_1_d),
-    .x_result_sel_csr       (x_result_sel_csr_d),
-    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
-    .x_result_sel_sext      (x_result_sel_sext_d),
-    .x_result_sel_logic     (x_result_sel_logic_d),
-    .x_result_sel_add       (x_result_sel_add_d),
-    .m_result_sel_compare   (m_result_sel_compare_d),
-    .m_result_sel_shift     (m_result_sel_shift_d),
-    .w_result_sel_load      (w_result_sel_load_d),
-    .w_result_sel_mul       (w_result_sel_mul_d),
-    .x_bypass_enable        (x_bypass_enable_d),
-    .m_bypass_enable        (m_bypass_enable_d),
-    .read_enable_0          (read_enable_0_d),
-    .read_idx_0             (read_idx_0_d),
-    .read_enable_1          (read_enable_1_d),
-    .read_idx_1             (read_idx_1_d),
-    .write_enable           (write_enable_d),
-    .write_idx              (write_idx_d),
-    .immediate              (immediate_d),
-    .branch_offset          (branch_offset_d),
-    .load                   (load_d),
-    .store                  (store_d),
-    .size                   (size_d),
-    .sign_extend            (sign_extend_d),
-    .adder_op               (adder_op_d),
-    .logic_op               (logic_op_d),
-    .direction              (direction_d),
-    .divide                 (divide_d),
-    .modulus                (modulus_d),
-    .branch                 (branch_d),
-    .bi_unconditional       (bi_unconditional),
-    .bi_conditional         (bi_conditional),
-    .branch_reg             (branch_reg_d),
-    .condition              (condition_d),
-    .break_opcode           (break_d),
-    .scall                  (scall_d),
-    .eret                   (eret_d),
-    .bret                   (bret_d),
-    .csr_write_enable       (csr_write_enable_d)
-    );
-
-// Load/store unit
-lm32_load_store_unit #(
-    .associativity          (dcache_associativity),
-    .sets                   (dcache_sets),
-    .bytes_per_line         (dcache_bytes_per_line),
-    .base_address           (dcache_base_address),
-    .limit                  (dcache_limit)
-  ) load_store_unit (
-    // ----- Inputs -------
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    // From pipeline
-    .stall_a                (stall_a),
-    .stall_x                (stall_x),
-    .stall_m                (stall_m),
-    .kill_m                 (kill_m),
-    .exception_m            (exception_m),
-    .store_operand_x        (store_operand_x),
-    .load_store_address_x   (adder_result_x),
-    .load_store_address_m   (operand_m),
-    .load_store_address_w   (operand_w[1:0]),
-    .load_d                 (load_d),
-    .store_d                (store_d),
-    .load_x                 (load_x),
-    .store_x                (store_x),
-    .load_q_x               (load_q_x),
-    .store_q_x              (store_q_x),
-    .load_q_m               (load_q_m),
-    .store_q_m              (store_q_m),
-    .sign_extend_x          (sign_extend_x),
-    .size_x                 (size_x),
-    .dflush                 (dflush_m),
-    .dtlb_enable            (dtlbe),
-    .tlbpaddr               (tlbpaddr),
-    .tlbvaddr               (tlbvaddr),
-    .dtlb_update            (dtlb_update),
-    .dtlb_flush             (dtlb_flush),
-    .dtlb_invalidate        (dtlb_invalidate),
-    // From Wishbone
-    .d_dat_i                (D_DAT_I),
-    .d_ack_i                (D_ACK_I),
-    .d_err_i                (D_ERR_I),
-    .d_rty_i                (D_RTY_I),
-    // ----- Outputs -------
-    // To pipeline
-    .dcache_refill_request  (dcache_refill_request),
-    .dcache_restart_request (dcache_restart_request),
-    .dcache_stall_request   (dcache_stall_request),
-    .dcache_refilling       (dcache_refilling),
-    .load_data_w            (load_data_w),
-    .stall_wb_load          (stall_wb_load),
-    .dtlb_stall_request     (dtlb_stall_request),
-    .dtlb_miss_vfn          (dtlb_miss_vfn),
-    .dtlb_miss_x            (dtlb_miss_x),
-    .dtlb_fault_x           (dtlb_fault_x),
-    // To Wishbone
-    .d_dat_o                (D_DAT_O),
-    .d_adr_o                (D_ADR_O),
-    .d_cyc_o                (D_CYC_O),
-    .d_sel_o                (D_SEL_O),
-    .d_stb_o                (D_STB_O),
-    .d_we_o                 (D_WE_O),
-    .d_cti_o                (D_CTI_O),
-    .d_lock_o               (D_LOCK_O),
-    .d_bte_o                (D_BTE_O)
-    );
-
-// Adder
-lm32_adder adder (
-    // ----- Inputs -------
-    .adder_op_x             (adder_op_x),
-    .adder_op_x_n           (adder_op_x_n),
-    .operand_0_x            (operand_0_x),
-    .operand_1_x            (operand_1_x),
-    // ----- Outputs -------
-    .adder_result_x         (adder_result_x),
-    .adder_carry_n_x        (adder_carry_n_x),
-    .adder_overflow_x       (adder_overflow_x)
-    );
-
-// Logic operations
-lm32_logic_op logic_op (
-    // ----- Inputs -------
-    .logic_op_x             (logic_op_x),
-    .operand_0_x            (operand_0_x),
-
-    .operand_1_x            (operand_1_x),
-    // ----- Outputs -------
-    .logic_result_x         (logic_result_x)
-    );
-
-// Pipelined barrel-shifter
-lm32_shifter shifter (
-    // ----- Inputs -------
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    .stall_x                (stall_x),
-    .direction_x            (direction_x),
-    .sign_extend_x          (sign_extend_x),
-    .operand_0_x            (operand_0_x),
-    .operand_1_x            (operand_1_x),
-    // ----- Outputs -------
-    .shifter_result_m       (shifter_result_m)
-    );
-
-// Pipeline fixed-point multiplier
-lm32_multiplier multiplier (
-    // ----- Inputs -------
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    .stall_x                (stall_x),
-    .stall_m                (stall_m),
-    .operand_0              (d_result_0),
-    .operand_1              (d_result_1),
-    // ----- Outputs -------
-    .result                 (multiplier_result_w)
-    );
-
-// Multi-cycle arithmetic
-lm32_mc_arithmetic mc_arithmetic (
-    // ----- Inputs -------
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    .stall_d                (stall_d),
-    .kill_x                 (kill_x),
-    .divide_d               (divide_q_d),
-    .modulus_d              (modulus_q_d),
-    .operand_0_d            (d_result_0),
-    .operand_1_d            (d_result_1),
-    // ----- Outputs -------
-    .result_x               (mc_result_x),
-    .divide_by_zero_x       (divide_by_zero_x),
-    .stall_request_x        (mc_stall_request_x)
-    );
-
-// Interrupt unit
-lm32_interrupt interrupt_unit (
-    // ----- Inputs -------
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    // From external devices
-    .interrupt              (interrupt),
-    // From pipeline
-    .stall_x                (stall_x),
-    .non_debug_exception    (non_debug_exception_q_w),
-    .debug_exception        (debug_exception_q_w),
-    .eret_q_x               (eret_k_q_x),
-    .bret_q_x               (bret_k_q_x),
-    .csr                    (csr_x),
-    .csr_write_data         (operand_1_x),
-    .csr_write_enable       (csr_write_enable_k_q_x),
-    // ----- Outputs -------
-    .interrupt_exception    (interrupt_exception),
-    // To pipeline
-    .csr_read_data          (interrupt_csr_read_data_x)
-    );
-
-
-// Debug unit
-lm32_debug #(
-    .breakpoints            (breakpoints),
-    .watchpoints            (watchpoints)
-  ) hw_debug (
-    // ----- Inputs -------
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    .pc_x                   (pc_x),
-    .load_x                 (load_x),
-    .store_x                (store_x),
-    .load_store_address_x   (adder_result_x),
-    .csr_write_enable_x     (csr_write_enable_k_q_x),
-    .csr_write_data         (operand_1_x),
-    .csr_x                  (csr_x),
-    .eret_q_x               (eret_k_q_x),
-    .bret_q_x               (bret_k_q_x),
-    .stall_x                (stall_x),
-    .exception_x            (exception_x),
-    .q_x                    (q_x),
-    .dcache_refill_request  (dcache_refill_request),
-    // ----- Outputs -------
-    .dc_ss                  (dc_ss),
-    .dc_re                  (dc_re),
-    .bp_match               (bp_match),
-    .wp_match               (wp_match)
-    );
-
-// Register file
-
-   /*----------------------------------------------------------------------
-    Register File is implemented using EBRs. There can be three accesses to
-    the register file in each cycle: two reads and one write. On-chip block
-    RAM has two read/write ports. To accomodate three accesses, two on-chip
-    block RAMs are used (each register file "write" is made to both block
-    RAMs).
-
-    One limitation of the on-chip block RAMs is that one cannot perform a
-    read and write to same location in a cycle (if this is done, then the
-    data read out is indeterminate).
-    ----------------------------------------------------------------------*/
-   wire [31:0] regfile_data_0, regfile_data_1;
-   reg [31:0]  w_result_d;
-   reg         regfile_raw_0, regfile_raw_0_nxt;
-   reg         regfile_raw_1, regfile_raw_1_nxt;
-
-   /*----------------------------------------------------------------------
-    Check if read and write is being performed to same register in current
-    cycle? This is done by comparing the read and write IDXs.
-    ----------------------------------------------------------------------*/
-   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
-     begin
-        if (reg_write_enable_q_w
-            && (write_idx_w == instruction_f[25:21]))
-          regfile_raw_0_nxt = 1'b1;
-        else
-          regfile_raw_0_nxt = 1'b0;
-
-        if (reg_write_enable_q_w
-            && (write_idx_w == instruction_f[20:16]))
-          regfile_raw_1_nxt = 1'b1;
-        else
-          regfile_raw_1_nxt = 1'b0;
-     end
-
-   /*----------------------------------------------------------------------
-    Select latched (delayed) write value or data from register file. If
-    read in previous cycle was performed to register written to in same
-    cycle, then latched (delayed) write value is selected.
-    ----------------------------------------------------------------------*/
-   always @(regfile_raw_0 or w_result_d or regfile_data_0)
-     if (regfile_raw_0)
-       reg_data_live_0 = w_result_d;
-     else
-       reg_data_live_0 = regfile_data_0;
-
-   /*----------------------------------------------------------------------
-    Select latched (delayed) write value or data from register file. If
-    read in previous cycle was performed to register written to in same
-    cycle, then latched (delayed) write value is selected.
-    ----------------------------------------------------------------------*/
-   always @(regfile_raw_1 or w_result_d or regfile_data_1)
-     if (regfile_raw_1)
-       reg_data_live_1 = w_result_d;
-     else
-       reg_data_live_1 = regfile_data_1;
-
-   /*----------------------------------------------------------------------
-    Latch value written to register file
-    ----------------------------------------------------------------------*/
-   always @(posedge clk_i )
-     if (rst_i == 1'b1)
-       begin
-          regfile_raw_0 <= 1'b0;
-          regfile_raw_1 <= 1'b0;
-          w_result_d <= 32'b0;
-       end
-     else
-       begin
-          regfile_raw_0 <= regfile_raw_0_nxt;
-          regfile_raw_1 <= regfile_raw_1_nxt;
-          w_result_d <= w_result;
-       end
-
-   /*----------------------------------------------------------------------
-    Register file instantiation as Pseudo-Dual Port EBRs.
-    ----------------------------------------------------------------------*/
-   // Modified by GSI: removed non-portable RAM instantiation
-   lm32_ram
-     #(
-       // ----- Parameters -----
-       .data_width(32),
-       .address_width(5)
-       )
-   reg_0
-     (
-      // ----- Inputs -----
-      .read_clk      (clk_i),
-      .write_clk     (clk_i),
-      .reset         (rst_i),
-      .enable_read   (1'b1),
-      .read_address  (instruction_f[25:21]),
-      .enable_write  (1'b1),
-      .write_address (write_idx_w),
-      .write_data    (w_result),
-      .write_enable  (reg_write_enable_q_w),
-      // ----- Outputs -----
-      .read_data     (regfile_data_0)
-      );
-
-   lm32_ram
-     #(
-       .data_width(32),
-       .address_width(5)
-       )
-   reg_1
-     (
-      // ----- Inputs -----
-      .read_clk      (clk_i),
-      .write_clk     (clk_i),
-      .reset         (rst_i),
-      .enable_read   (1'b1),
-      .read_address  (instruction_f[20:16]),
-      .enable_write  (1'b1),
-      .write_address (write_idx_w),
-      .write_data    (w_result),
-      .write_enable  (reg_write_enable_q_w),
-      // ----- Outputs -----
-      .read_data     (regfile_data_1)
-      );
-
-
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-// Select between buffered and live data from register file
-assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
-assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
-
-// Detect read-after-write hazzards
-assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
-assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
-assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
-assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
-assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
-assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
-
-// Interlock detection - Raise an interlock for RAW hazzards
-always @(*)
-begin
-    if (   (   (x_bypass_enable_x == 1'b0)
-            && (   ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
-                || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
-               )
-           )
-        || (   (m_bypass_enable_m == 1'b0)
-            && (   ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
-                || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
-               )
-           )
-       )
-        interlock = 1'b1;
-    else
-        interlock = 1'b0;
-end
-
-// Bypass for reg port 0
-always @(*)
-begin
-    if (raw_x_0 == 1'b1)
-        bypass_data_0 = x_result;
-    else if (raw_m_0 == 1'b1)
-        bypass_data_0 = m_result;
-    else if (raw_w_0 == 1'b1)
-        bypass_data_0 = w_result;
-    else
-        bypass_data_0 = reg_data_0;
-end
-
-// Bypass for reg port 1
-always @(*)
-begin
-    if (raw_x_1 == 1'b1)
-        bypass_data_1 = x_result;
-    else if (raw_m_1 == 1'b1)
-        bypass_data_1 = m_result;
-    else if (raw_w_1 == 1'b1)
-        bypass_data_1 = w_result;
-    else
-        bypass_data_1 = reg_data_1;
-end
-
-   /*----------------------------------------------------------------------
-    Branch prediction is performed in D stage of pipeline. Only PC-relative
-    branches are predicted: forward-pointing conditional branches are not-
-    taken, while backward-pointing conditional branches are taken.
-    Unconditional branches are always predicted taken!
-    ----------------------------------------------------------------------*/
-   assign branch_predict_d = bi_unconditional | bi_conditional;
-   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
-
-   // Compute branch target address: Branch PC PLUS Offset
-   assign branch_target_d = pc_d + branch_offset_d;
-
-   // Compute fetch address. Address of instruction sequentially after the
-   // branch if branch is not taken. Target address of branch is branch is
-   // taken
-   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
-
-// D stage result selection
-always @(*)
-begin
-    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
-    case (d_result_sel_1_d)
-    2'b00:      d_result_1 = {32{1'b0}};
-    2'b01:     d_result_1 = bypass_data_1;
-    2'b10: d_result_1 = immediate_d;
-    default:                        d_result_1 = {32{1'bx}};
-    endcase
-end
-
-
-// Sign-extension
-assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
-assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
-assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
-
-// Condition evaluation
-assign cmp_zero = operand_0_x == operand_1_x;
-assign cmp_negative = adder_result_x[32-1];
-assign cmp_overflow = adder_overflow_x;
-assign cmp_carry_n = adder_carry_n_x;
-always @(*)
-begin
-    case (condition_x)
-    3'b000:   condition_met_x = 1'b1;
-    3'b110:   condition_met_x = 1'b1;
-    3'b001:    condition_met_x = cmp_zero;
-    3'b111:   condition_met_x = !cmp_zero;
-    3'b010:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
-    3'b101:   condition_met_x = cmp_carry_n && !cmp_zero;
-    3'b011:   condition_met_x = cmp_negative == cmp_overflow;
-    3'b100:  condition_met_x = cmp_carry_n;
-    default:              condition_met_x = 1'bx;
-    endcase
-end
-
-// X stage result selection
-always @(*)
-begin
-    x_result =   x_result_sel_add_x ? adder_result_x
-               : x_result_sel_csr_x ? csr_read_data_x
-               : x_result_sel_sext_x ? sext_result_x
-               : x_result_sel_mc_arith_x ? mc_result_x
-               : logic_result_x;
-end
-
-// M stage result selection
-always @(*)
-begin
-    m_result =   m_result_sel_compare_m ? {{32-1{1'b0}}, condition_met_m}
-               : m_result_sel_shift_m ? shifter_result_m
-               : operand_m;
-end
-
-// W stage result selection
-always @(*)
-begin
-    w_result =    w_result_sel_load_w ? load_data_w
-                : w_result_sel_mul_w ? multiplier_result_w
-                : operand_w;
-end
-
-
-// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
-assign branch_taken_m =      (stall_m == 1'b0)
-                          && (   (   (branch_m == 1'b1)
-                                  && (valid_m == 1'b1)
-                                  && (   (   (condition_met_m == 1'b1)
-                                          && (branch_predict_taken_m == 1'b0)
-                                         )
-                                      || (   (condition_met_m == 1'b0)
-                                          && (branch_predict_m == 1'b1)
-                                          && (branch_predict_taken_m == 1'b1)
-                                         )
-                                     )
-                                 )
-                              || (exception_m == 1'b1)
-                             );
-
-// Indicate when a branch in M stage is mispredicted as being taken
-assign branch_mispredict_taken_m =    (condition_met_m == 1'b0)
-                                   && (branch_predict_m == 1'b1)
-                                   && (branch_predict_taken_m == 1'b1);
-
-// Indicate when a branch in M stage will cause flush in X stage
-assign branch_flushX_m =    (stall_m == 1'b0)
-                         && (   (   (branch_m == 1'b1)
-                                 && (valid_m == 1'b1)
-                                 && (   (condition_met_m == 1'b1)
-                                     || (   (condition_met_m == 1'b0)
-                                         && (branch_predict_m == 1'b1)
-                                         && (branch_predict_taken_m == 1'b1)
-                                        )
-                                    )
-                                )
-                             || (exception_m == 1'b1)
-                            );
-
-// Generate signal that will kill instructions in each pipeline stage when necessary
-assign kill_f =    (   (valid_d == 1'b1)
-                    && (branch_predict_taken_d == 1'b1)
-                   )
-                || (branch_taken_m == 1'b1)
-                || (icache_refill_request == 1'b1)
-                || (dcache_refill_request == 1'b1)
-                || (itlb_miss_exception == 1'b1)
-                ;
-assign kill_d =    (branch_taken_m == 1'b1)
-                || (icache_refill_request == 1'b1)
-                || (dcache_refill_request == 1'b1)
-                || (itlb_miss_exception == 1'b1)
-                ;
-assign kill_x =    (branch_flushX_m == 1'b1)
-                || (dcache_refill_request == 1'b1)
-                ;
-assign kill_m =    1'b0
-                || (dcache_refill_request == 1'b1)
-                ;
-assign kill_w =    1'b0
-                || (dcache_refill_request == 1'b1)
-                ;
-
-// Exceptions
-
-assign breakpoint_exception =    (   (   (break_x == 1'b1)
-                                      || (bp_match == 1'b1)
-                                     )
-                                  && (valid_x == 1'b1)
-                                 )
-                              || (ext_break_r == 1'b1)
-                              ;
-
-assign watchpoint_exception = wp_match == 1'b1;
-
-assign instruction_bus_error_exception = (   (bus_error_x == 1'b1)
-                                          && (valid_x == 1'b1)
-                                         );
-assign data_bus_error_exception = data_bus_error_seen == 1'b1;
-
-assign divide_by_zero_exception = divide_by_zero_x == 1'b1;
-
-assign system_call_exception = (   (scall_x == 1'b1)
-                                && (valid_x == 1'b1)
-                               );
-
-assign itlb_miss_exception = (   (itlb_miss_x == 1'b1)
-                              && (itlbe == 1'b1)
-                              && (valid_x == 1'b1)
-                            );
-assign itlb_exception = (itlb_miss_exception == 1'b1);
-
-assign dtlb_miss_exception = (   (dtlb_miss_x == 1'b1)
-                              && (dtlbe == 1'b1)
-                              && (valid_x == 1'b1)
-                            );
-assign dtlb_fault_exception = (   (dtlb_fault_x == 1'b1)
-                               && (dtlbe == 1'b1)
-                               && (valid_x == 1'b1)
-                            );
-assign dtlb_exception = (dtlb_miss_exception == 1'b1) || (dtlb_fault_exception == 1'b1);
-
-assign privilege_exception = (   (usr == 1'b1)
-                              && (   (csr_write_enable_q_x == 1'b1)
-                                  || (eret_q_x == 1'b1)
-                                  || (bret_q_x == 1'b1)
-                                 )
-                             );
-
-assign debug_exception_x =  (breakpoint_exception == 1'b1)
-                         || (watchpoint_exception == 1'b1)
-                         ;
-
-assign non_debug_exception_x = (system_call_exception == 1'b1)
-                            || (instruction_bus_error_exception == 1'b1)
-                            || (data_bus_error_exception == 1'b1)
-                            || (divide_by_zero_exception == 1'b1)
-                            || (   (interrupt_exception == 1'b1)
-                                && (dc_ss == 1'b0)
-                                && (store_q_m == 1'b0)
-                                && (D_CYC_O == 1'b0)
-                               )
-                            || (itlb_exception == 1'b1)
-                            || (dtlb_exception == 1'b1)
-                            || (privilege_exception == 1'b1)
-                            ;
-
-assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
-
-// Exception ID
-always @(*)
-begin
-         if (data_bus_error_exception == 1'b1)
-        eid_x = 4'h4;
-    else
-         if (breakpoint_exception == 1'b1)
-        eid_x = 4'h1;
-    else
-         if (data_bus_error_exception == 1'b1)
-        eid_x = 4'h4;
-    else
-         if (instruction_bus_error_exception == 1'b1)
-        eid_x = 4'h2;
-    else
-         if (watchpoint_exception == 1'b1)
-        eid_x = 4'h3;
-    else
-         if (divide_by_zero_exception == 1'b1)
-        eid_x = 4'h5;
-    else
-         if (   (interrupt_exception == 1'b1)
-             && (dc_ss == 1'b0)
-            )
-        eid_x = 4'h6;
-    else
-         if (itlb_miss_exception == 1'b1)
-        eid_x = 4'h8;
-    else
-         if (dtlb_miss_exception == 1'b1)
-        eid_x = 4'h9;
-    else
-         if (dtlb_fault_exception == 1'b1)
-        eid_x = 4'ha;
-    else
-         if (privilege_exception == 1'b1)
-        eid_x = 4'hb;
-    else
-        eid_x = 4'h7;
-end
-
-// Stall generation
-
-assign stall_a = (stall_f == 1'b1);
-
-assign stall_f =   (stall_d == 1'b1)
-                // We need to stall for one cycle. Otherwise the icache
-                // starts one cycle earlier and the restart address will be
-                // wrong in case of a miss, that is one instruction is
-                // skipped.
-                || (   (itlbe == 1'b1)
-                    && (   (debug_exception_q_w == 1'b1)
-                        || (non_debug_exception_q_w == 1'b1)
-                       )
-                   )
-                ;
-
-assign stall_d =   (stall_x == 1'b1)
-                || (   (interlock == 1'b1)
-                    && (kill_d == 1'b0)
-                   )
-                || (   (   (eret_d == 1'b1)
-                        || (scall_d == 1'b1)
-                        || (bus_error_d == 1'b1)
-                       )
-                    && (   (load_q_x == 1'b1)
-                        || (load_q_m == 1'b1)
-                        || (store_q_x == 1'b1)
-                        || (store_q_m == 1'b1)
-                        || (D_CYC_O == 1'b1)
-                       )
-                    && (kill_d == 1'b0)
-                   )
-                || (   (   (break_d == 1'b1)
-                        || (bret_d == 1'b1)
-                       )
-                    && (   (load_q_x == 1'b1)
-                        || (store_q_x == 1'b1)
-                        || (load_q_m == 1'b1)
-                        || (store_q_m == 1'b1)
-                        || (D_CYC_O == 1'b1)
-                       )
-                    && (kill_d == 1'b0)
-                   )
-                || (   (csr_write_enable_d == 1'b1)
-                    && (load_q_x == 1'b1)
-                   )
-                ;
-
-assign stall_x =    (stall_m == 1'b1)
-                 || (   (mc_stall_request_x == 1'b1)
-                     && (kill_x == 1'b0)
-                    )
-                 ;
-
-assign stall_m =    (stall_wb_load == 1'b1)
-                 || (   (D_CYC_O == 1'b1)
-                     && (   (store_m == 1'b1)
-                         /*
-                          Bug: Following loop does not allow interrupts to be services since
-                          either D_CYC_O or store_m is always high during entire duration of
-                          loop.
-                          L1:   addi    r1, r1, 1
-                                sw      (r2,0), r1
-                                bi      L1
-
-                          Introduce a single-cycle stall when a wishbone cycle is in progress
-                          and a new store instruction is in Execute stage and a interrupt
-                          exception has occured. This stall will ensure that D_CYC_O and
-                          store_m will both be low for one cycle.
-                          */
-                         || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
-                         || (load_m == 1'b1)
-                         || (load_x == 1'b1)
-                        )
-                    )
-                 || (dcache_stall_request == 1'b1)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
-                 || (icache_stall_request == 1'b1)     // Pipeline needs to be stalled otherwise branches may be lost
-                 || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
-                 || (itlb_stall_request == 1'b1)       // ITLB is busy
-                 || (dtlb_stall_request == 1'b1)       // DTLB is busy or a lookup is in progress
-                 ;
-
-// Qualify state changing control signals
-assign q_d = (valid_d == 1'b1) && (kill_d == 1'b0);
-assign divide_q_d = (divide_d == 1'b1) && (q_d == 1'b1);
-assign modulus_q_d = (modulus_d == 1'b1) && (q_d == 1'b1);
-assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
-assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
-assign csr_write_enable_k_q_x = (csr_write_enable_q_x == 1'b1)
-               && (usr == 1'b0)
-                  ;
-assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-assign eret_k_q_x = (eret_q_x == 1'b1)
-               && (usr == 1'b0)
-                  ;
-assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
-assign bret_k_q_x = (bret_q_x == 1'b1)
-               && (usr == 1'b0)
-                  ;
-assign load_q_x = (load_x == 1'b1)
-               && (q_x == 1'b1)
-               && (bp_match == 1'b0)
-                  ;
-assign store_q_x = (store_x == 1'b1)
-               && (q_x == 1'b1)
-               && (bp_match == 1'b0)
-                  ;
-assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
-assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
-assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
-assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
-// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
-assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
-assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
-assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
-// The enable that actually does write the registers needs to be qualified with kill
-assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1) || rst_i;
-
-// Configuration (CFG) CSR
-assign cfg = {
-              6'h02,
-              watchpoints[3:0],
-              breakpoints[3:0],
-              interrupts[5:0],
-              1'b0,
-              1'b1,
-              1'b0,
-              1'b1,
-              1'b1,
-              1'b1,
-              1'b0,
-              1'b0,
-              1'b1,
-              1'b1,
-              1'b1,
-              1'b1
-              };
-
-assign cfg2 = {
-               1'b1,
-               29'b0,
-               1'b0,
-               1'b0
-               };
-
-assign psw = {
-              {32-12{1'b0}},
-              busr,
-              eusr,
-              usr,
-              bdtlbe,
-              edtlbe,
-              dtlbe,
-              bitlbe,
-              eitlbe,
-              itlbe,
-              interrupt_csr_read_data_x[2:0]
-              };
-
-// Cache flush
-assign iflush = (   (csr_write_enable_d == 1'b1)
-                 && (csr_d == 5'h3)
-                 && (stall_d == 1'b0)
-                 && (kill_d == 1'b0)
-                 && (valid_d == 1'b1))
-// Added by GSI: needed to flush cache after loading firmware per JTAG
-                 ;
-assign dflush_x = (   (csr_write_enable_q_x == 1'b1)
-                   && (csr_x == 5'h4))
-// Added by GSI: needed to flush cache after loading firmware per JTAG
-                   ;
-
-// Extract CSR index
-assign csr_d = read_idx_0_d[(5-1):0];
-
-// CSR reads
-always @(*)
-begin
-    case (csr_x)
-    5'h0,
-    5'h1,
-    5'h2:   csr_read_data_x = interrupt_csr_read_data_x;
-    5'h6:  csr_read_data_x = cfg;
-    5'h7:  csr_read_data_x = {eba, {(32-((32-2)-4-3)){1'b0}}};
-    5'h9: csr_read_data_x = {deba, {(32-((32-2)-4-3)){1'b0}}};
-    5'ha: csr_read_data_x = cfg2;
-    5'h1d:  csr_read_data_x = psw;
-    5'h1e: csr_read_data_x = tlbvaddr;
-    5'h1f : csr_read_data_x = tlbbadvaddr;
-
-    default:        csr_read_data_x = {32{1'bx}};
-    endcase
-end
-
-/////////////////////////////////////////////////////
-// Sequential Logic
-/////////////////////////////////////////////////////
-
-// Processor status word (PSW) handling
-always @(posedge clk_i )
-begin
-    if (rst_i)
-    begin
-        itlbe <= 1'b0;
-        eitlbe <= 1'b0;
-        dtlbe <= 1'b0;
-        edtlbe <= 1'b0;
-        usr <= 1'b0;
-        eusr <= 1'b0;
-        bitlbe <= 1'b0;
-        bdtlbe <= 1'b0;
-        busr <= 1'b0;
-    end
-    else
-    begin
-        if (non_debug_exception_q_w == 1'b1)
-        begin
-            // Save and then clear ITLB and DTLB enable
-            eitlbe <= itlbe;
-            itlbe <= 1'b0;
-            edtlbe <= dtlbe;
-            dtlbe <= 1'b0;
-            eusr <= usr;
-            usr <= 1'b0;
-        end
-        else if (debug_exception_q_w == 1'b1)
-        begin
-            // Save and then clear TLB enable
-            bitlbe <= itlbe;
-            itlbe <= 1'b0;
-            bdtlbe <= dtlbe;
-            dtlbe <= 1'b0;
-            busr <= usr;
-            usr <= 1'b0;
-        end
-
-        else if (stall_x == 1'b0)
-        begin
-            if (eret_k_q_x == 1'b1)
-            begin
-                // Restore ITLB and DTLB enable
-                itlbe <= eitlbe;
-                dtlbe <= edtlbe;
-                usr <= eusr;
-            end
-            else if (bret_k_q_x == 1'b1)
-            begin
-                // Restore ITLB and DTLB enable
-                itlbe <= bitlbe;
-                dtlbe <= bdtlbe;
-                usr <= busr;
-            end
-            else if (csr_write_enable_k_q_x == 1'b1)
-            begin
-                // Handle wcsr write
-                if (csr_x == 5'h1d)
-                begin
-                    // ie, eie and bie are shadowed from IE register
-                    itlbe  <= operand_1_x[3];
-                    eitlbe <= operand_1_x[4];
-                    dtlbe  <= operand_1_x[6];
-                    edtlbe <= operand_1_x[7];
-                    usr    <= operand_1_x[9];
-                    eusr   <= operand_1_x[10];
-                    bitlbe <= operand_1_x[5];
-                    bdtlbe <= operand_1_x[8];
-                    busr   <= operand_1_x[11];
-                end
-            end
-        end
-    end
-end
-
-// TLBVADDR CSR
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        itlb_flush <= 1'b0;
-        itlb_invalidate <= 1'b0;
-        dtlb_flush <= 1'b0;
-        dtlb_invalidate <= 1'b0;
-        tlbvaddr <= {32{1'b0}};
-    end
-    else
-    begin
-        itlb_flush <= 1'b0;
-        itlb_invalidate <= 1'b0;
-        dtlb_flush <= 1'b0;
-        dtlb_invalidate <= 1'b0;
-        if (stall_x == 1'b0)
-        begin
-            if (dtlb_exception == 1'b1)
-                tlbvaddr <= {dtlb_miss_vfn[32-1:1], 1'b1};
-            else if (itlb_exception == 1'b1)
-                tlbvaddr <= {itlb_miss_vfn[32-1:1], 1'b0};
-            else if ((csr_write_enable_k_q_x == 1'b1) && (csr_x == 5'h1e))
-            begin
-                tlbvaddr <= operand_1_x;
-                if (operand_1_x[0] == 1'b0)
-                begin
-                    case (operand_1_x[2:1])
-                    2'h1:      itlb_flush <= 1'b1;
-                    2'h2: itlb_invalidate <= 1'b1;
-                    endcase
-                end
-                if (operand_1_x[0] == 1'b1)
-                begin
-                    case (operand_1_x[2:1])
-                    2'h1:      dtlb_flush <= 1'b1;
-                    2'h2: dtlb_invalidate <= 1'b1;
-                    endcase
-                end
-            end
-        end
-    end
-end
-
-// TLBPADDR CSR
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        itlb_update <= 1'b0;
-        dtlb_update <= 1'b0;
-        tlbpaddr <= {32{1'b0}};
-    end
-    else
-    begin
-        itlb_update <= 1'b0;
-        dtlb_update <= 1'b0;
-        if ((csr_write_enable_k_q_x == 1'b1) && (csr_x == 5'h1f ) && (stall_x == 1'b0))
-        begin
-            /* updates take change in the M stage */
-            tlbpaddr <= operand_1_x;
-            if (operand_1_x[0] == 1'b0)
-                itlb_update <= 1'b1;
-            if (operand_1_x[0] == 1'b1)
-                dtlb_update <= 1'b1;
-        end
-    end
-end
-
-// TLBBADVADDR CSR
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        tlbbadvaddr <= {32{1'b0}};
-    else
-    begin
-        if (stall_x == 1'b0)
-        begin
-            if (dtlb_exception == 1'b1)
-                tlbbadvaddr <= adder_result_x;
-            else if (itlb_exception == 1'b1)
-                tlbbadvaddr <= {pc_x, {32-(32-2){1'b0}}};
-        end
-    end
-end
-
-// Exception Base Address (EBA) CSR
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        eba <= eba_reset[((32-2)+2-1):(4+3+2)];
-    else
-    begin
-        if ((csr_write_enable_k_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
-            eba <= operand_1_x[((32-2)+2-1):(4+3+2)];
-    end
-end
-
-// Debug Exception Base Address (DEBA) CSR
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        deba <= deba_reset[((32-2)+2-1):(4+3+2)];
-    else
-    begin
-        if ((csr_write_enable_k_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
-            deba <= operand_1_x[((32-2)+2-1):(4+3+2)];
-    end
-end
-
-// Cycle Counter (CC) CSR
-
-// Watch for data bus errors
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        data_bus_error_seen <= 1'b0;
-    else
-    begin
-        // Set flag when bus error is detected
-        if ((D_ERR_I == 1'b1) && (D_CYC_O == 1'b1))
-            data_bus_error_seen <= 1'b1;
-        // Clear flag when exception is taken
-        if ((exception_m == 1'b1) && (kill_m == 1'b0))
-            data_bus_error_seen <= 1'b0;
-    end
-end
-
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        ext_break_r <= 1'b0;
-    else
-    begin
-        if (ext_break == 1'b1)
-            ext_break_r <= 1'b1;
-        if (debug_exception_q_w == 1'b1)
-            ext_break_r <= 1'b0;
-    end
-end
-
-// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
-
-always @(*)
-begin
-    if (   (icache_refill_request == 1'b1)
-        || (dcache_refill_request == 1'b1)
-       )
-        valid_a = 1'b0;
-    else if (   (icache_restart_request == 1'b1)
-             || (dcache_restart_request == 1'b1)
-            )
-        valid_a = 1'b1;
-    else
-        valid_a = !icache_refilling && !dcache_refilling;
-end
-
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        valid_f <= 1'b0;
-        valid_d <= 1'b0;
-        valid_x <= 1'b0;
-        valid_m <= 1'b0;
-        valid_w <= 1'b0;
-    end
-    else
-    begin
-        if ((kill_f == 1'b1) || (stall_a == 1'b0))
-            valid_f <= valid_a;
-        else if (stall_f == 1'b0)
-            valid_f <= 1'b0;
-
-        if (kill_d == 1'b1)
-            valid_d <= 1'b0;
-        else if (stall_f == 1'b0)
-            valid_d <= valid_f & !kill_f;
-        else if (stall_d == 1'b0)
-            valid_d <= 1'b0;
-
-        if (stall_d == 1'b0)
-            valid_x <= valid_d & !kill_d;
-        else if (kill_x == 1'b1)
-            valid_x <= 1'b0;
-        else if (stall_x == 1'b0)
-            valid_x <= 1'b0;
-
-        if (kill_m == 1'b1)
-            valid_m <= 1'b0;
-        else if (stall_x == 1'b0)
-            valid_m <= valid_x & !kill_x;
-        else if (stall_m == 1'b0)
-            valid_m <= 1'b0;
-
-        if (stall_m == 1'b0)
-            valid_w <= valid_m & !kill_m;
-        else
-            valid_w <= 1'b0;
-    end
-end
-
-// Microcode pipeline registers
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        operand_0_x <= {32{1'b0}};
-        operand_1_x <= {32{1'b0}};
-        store_operand_x <= {32{1'b0}};
-        branch_target_x <= {(32-2){1'b0}};
-        x_result_sel_csr_x <= 1'b0;
-        x_result_sel_mc_arith_x <= 1'b0;
-        x_result_sel_sext_x <= 1'b0;
-        x_result_sel_logic_x <= 1'b0;
-        x_result_sel_add_x <= 1'b0;
-        m_result_sel_compare_x <= 1'b0;
-        m_result_sel_shift_x <= 1'b0;
-        w_result_sel_load_x <= 1'b0;
-        w_result_sel_mul_x <= 1'b0;
-        x_bypass_enable_x <= 1'b0;
-        m_bypass_enable_x <= 1'b0;
-        write_enable_x <= 1'b0;
-        write_idx_x <= {5{1'b0}};
-        csr_x <= {5{1'b0}};
-        load_x <= 1'b0;
-        store_x <= 1'b0;
-        size_x <= {2{1'b0}};
-        sign_extend_x <= 1'b0;
-        adder_op_x <= 1'b0;
-        adder_op_x_n <= 1'b0;
-        logic_op_x <= 4'h0;
-        direction_x <= 1'b0;
-        branch_x <= 1'b0;
-        branch_predict_x <= 1'b0;
-        branch_predict_taken_x <= 1'b0;
-        condition_x <= 3'b000;
-        break_x <= 1'b0;
-        scall_x <= 1'b0;
-        eret_x <= 1'b0;
-        bret_x <= 1'b0;
-        bus_error_x <= 1'b0;
-        data_bus_error_exception_m <= 1'b0;
-        csr_write_enable_x <= 1'b0;
-        operand_m <= {32{1'b0}};
-        branch_target_m <= {(32-2){1'b0}};
-        m_result_sel_compare_m <= 1'b0;
-        m_result_sel_shift_m <= 1'b0;
-        w_result_sel_load_m <= 1'b0;
-        w_result_sel_mul_m <= 1'b0;
-        m_bypass_enable_m <= 1'b0;
-        branch_m <= 1'b0;
-        branch_predict_m <= 1'b0;
-        branch_predict_taken_m <= 1'b0;
-        exception_m <= 1'b0;
-        load_m <= 1'b0;
-        store_m <= 1'b0;
-        write_enable_m <= 1'b0;
-        write_idx_m <= {5{1'b0}};
-        condition_met_m <= 1'b0;
-        dflush_m <= 1'b0;
-        debug_exception_m <= 1'b0;
-        non_debug_exception_m <= 1'b0;
-        operand_w <= {32{1'b0}};
-        w_result_sel_load_w <= 1'b0;
-        w_result_sel_mul_w <= 1'b0;
-        write_idx_w <= {5{1'b0}};
-        write_enable_w <= 1'b0;
-        debug_exception_w <= 1'b0;
-        non_debug_exception_w <= 1'b0;
-        memop_pc_w <= {(32-2){1'b0}};
-    end
-    else
-    begin
-        // D/X stage registers
-
-        if (stall_x == 1'b0)
-        begin
-            operand_0_x <= d_result_0;
-            operand_1_x <= d_result_1;
-            store_operand_x <= bypass_data_1;
-            branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[((32-2)+2-1):2] : branch_target_d;
-            x_result_sel_csr_x <= x_result_sel_csr_d;
-            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
-            x_result_sel_sext_x <= x_result_sel_sext_d;
-            x_result_sel_logic_x <= x_result_sel_logic_d;
-            x_result_sel_add_x <= x_result_sel_add_d;
-            m_result_sel_compare_x <= m_result_sel_compare_d;
-            m_result_sel_shift_x <= m_result_sel_shift_d;
-            w_result_sel_load_x <= w_result_sel_load_d;
-            w_result_sel_mul_x <= w_result_sel_mul_d;
-            x_bypass_enable_x <= x_bypass_enable_d;
-            m_bypass_enable_x <= m_bypass_enable_d;
-            load_x <= load_d;
-            store_x <= store_d;
-            branch_x <= branch_d;
-            branch_predict_x <= branch_predict_d;
-            branch_predict_taken_x <= branch_predict_taken_d;
-            write_idx_x <= write_idx_d;
-            csr_x <= csr_d;
-            size_x <= size_d;
-            sign_extend_x <= sign_extend_d;
-            adder_op_x <= adder_op_d;
-            adder_op_x_n <= ~adder_op_d;
-            logic_op_x <= logic_op_d;
-            direction_x <= direction_d;
-            condition_x <= condition_d;
-            csr_write_enable_x <= csr_write_enable_d;
-            break_x <= break_d;
-            scall_x <= scall_d;
-            bus_error_x <= bus_error_d;
-            eret_x <= eret_d;
-            bret_x <= bret_d;
-            write_enable_x <= write_enable_d;
-        end
-
-        // X/M stage registers
-
-        if (stall_m == 1'b0)
-        begin
-            operand_m <= x_result;
-            m_result_sel_compare_m <= m_result_sel_compare_x;
-            m_result_sel_shift_m <= m_result_sel_shift_x;
-            if (exception_x == 1'b1)
-            begin
-                w_result_sel_load_m <= 1'b0;
-                w_result_sel_mul_m <= 1'b0;
-            end
-            else
-            begin
-                w_result_sel_load_m <= w_result_sel_load_x;
-                w_result_sel_mul_m <= w_result_sel_mul_x;
-            end
-            m_bypass_enable_m <= m_bypass_enable_x;
-            load_m <= load_x;
-            store_m <= store_x;
-            branch_m <= branch_x;
-            branch_predict_m <= branch_predict_x;
-            branch_predict_taken_m <= branch_predict_taken_x;
-            // Data bus errors are generated by the wishbone and are
-            // made known to the processor only in next cycle (as a
-            // non-debug exception). A break instruction can be seen
-            // in same cycle (causing a debug exception). Handle non
-            // -debug exception first!
-            if (non_debug_exception_x == 1'b1)
-                write_idx_m <= 5'd30;
-            else if (debug_exception_x == 1'b1)
-                write_idx_m <= 5'd31;
-            else
-                write_idx_m <= write_idx_x;
-            condition_met_m <= condition_met_x;
-            if (exception_x == 1'b1)
-                if (   (dc_re == 1'b1)
-                    || (   (debug_exception_x == 1'b1)
-                        && (non_debug_exception_x == 1'b0))
-                   )
-                    branch_target_m <= {deba, eid_x, {3{1'b0}}};
-                else
-                    branch_target_m <= {eba, eid_x, {3{1'b0}}};
-            else
-                branch_target_m <= branch_target_x;
-            dflush_m <= dflush_x;
-            eret_m <= eret_k_q_x;
-            bret_m <= bret_k_q_x;
-            write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-            debug_exception_m <= debug_exception_x;
-            non_debug_exception_m <= non_debug_exception_x;
-        end
-
-        // State changing regs
-        if (stall_m == 1'b0)
-        begin
-            if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
-                exception_m <= 1'b1;
-            else
-                exception_m <= 1'b0;
-            data_bus_error_exception_m <=    (data_bus_error_exception == 1'b1)
-                                          ;
-        end
-
-        // M/W stage registers
-        operand_w <= exception_m == 1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
-        w_result_sel_load_w <= w_result_sel_load_m;
-        w_result_sel_mul_w <= w_result_sel_mul_m;
-        write_idx_w <= write_idx_m;
-        write_enable_w <= write_enable_m;
-        debug_exception_w <= debug_exception_m;
-        non_debug_exception_w <= non_debug_exception_m;
-        if (   (stall_m == 1'b0)
-            && (data_bus_error_exception == 1'b0)
-            && (   (load_q_m == 1'b1)
-                || (store_q_m == 1'b1)
-               )
-           )
-          memop_pc_w <= pc_m;
-    end
-end
-
-// Buffer data read from register file, in case a stall occurs, and watch for
-// any writes to the modified registers
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        use_buf <= 1'b0;
-        reg_data_buf_0 <= {32{1'b0}};
-        reg_data_buf_1 <= {32{1'b0}};
-    end
-    else
-    begin
-        if (stall_d == 1'b0)
-            use_buf <= 1'b0;
-        else if (use_buf == 1'b0)
-        begin
-            reg_data_buf_0 <= reg_data_live_0;
-            reg_data_buf_1 <= reg_data_live_1;
-            use_buf <= 1'b1;
-        end
-        if (reg_write_enable_q_w == 1'b1)
-        begin
-            if (write_idx_w == read_idx_0_d)
-                reg_data_buf_0 <= w_result;
-            if (write_idx_w == read_idx_1_d)
-                reg_data_buf_1 <= w_result;
-        end
-    end
-end
-
-
-
-/////////////////////////////////////////////////////
-// Behavioural Logic
-/////////////////////////////////////////////////////
-
-// synthesis translate_off
-
-// Reset register 0. Only needed for simulation.
-initial
-begin
-    reg_0.mem[0] = {32{1'b0}};
-    reg_1.mem[0] = {32{1'b0}};
-end
-
-// synthesis translate_on
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dcache.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dcache.v
deleted file mode 100644
index b8b47ab..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dcache.v
+++ /dev/null
@@ -1,674 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_dcache.v
-// Title            : Data cache
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : Support for user-selected resource usage when implementing
-//                  : cache memory. Additional parameters must be defined when
-//                  : invoking lm32_ram.v
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-
-
-
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_dcache (
-    // ----- Inputs -----
-    clk_i,
-    rst_i,
-    stall_a,
-    stall_x,
-    stall_m,
-    address_x,
-    address_m,
-    load_q_m,
-    store_q_m,
-    store_data,
-    store_byte_select,
-    refill_ready,
-    refill_data,
-    dflush,
-    dtlb_miss_x,
-    // ----- Outputs -----
-    stall_request,
-    restart_request,
-    refill_request,
-    refill_address,
-    refilling,
-    load_data
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter associativity = 1;                            // Associativity of the cache (Number of ways)
-parameter sets = 512;                                   // Number of sets
-parameter bytes_per_line = 16;                          // Number of bytes per cache line
-parameter base_address = 0;                             // Base address of cachable memory
-parameter limit = 0;                                    // Limit (highest address) of cachable memory
-
-localparam addr_offset_width = $clog2-2;
-localparam addr_set_width = $clog2;
-localparam addr_offset_lsb = 2;
-localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
-localparam addr_set_lsb = (addr_offset_msb+1);
-localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
-localparam addr_tag_lsb = (addr_offset_msb+1);
-localparam addr_tag_msb = $clog2;
-localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                            // Clock
-input rst_i;                                            // Reset
-
-input stall_a;                                          // Stall A stage
-input stall_x;                                          // Stall X stage
-input stall_m;                                          // Stall M stage
-
-input [(32-1):0] address_x;                       // X stage load/store address
-input [(32-1):0] address_m;                       // M stage load/store address
-input load_q_m;                                         // Load instruction in M stage
-input store_q_m;                                        // Store instruction in M stage
-input [(32-1):0] store_data;                      // Data to store
-input [(4-1):0] store_byte_select;        // Which bytes in store data should be modified
-
-input refill_ready;                                     // Indicates next word of refill data is ready
-input [(32-1):0] refill_data;                     // Refill data
-
-input dflush;                                           // Indicates cache should be flushed
-
-input dtlb_miss_x;                                      // Indicates if a DTLB miss has occured
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output stall_request;                                   // Request pipeline be stalled because cache is busy
-wire   stall_request;
-output restart_request;                                 // Request to restart instruction that caused the cache miss
-reg    restart_request;
-output refill_request;                                  // Request a refill
-reg    refill_request;
-output [(32-1):0] refill_address;                 // Address to refill from
-reg    [(32-1):0] refill_address;
-output refilling;                                       // Indicates if the cache is currently refilling
-reg    refilling;
-output [(32-1):0] load_data;                      // Data read from cache
-wire   [(32-1):0] load_data;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-wire read_port_enable;                                  // Cache memory read port clock enable
-wire write_port_enable;                                 // Cache memory write port clock enable
-wire [0:associativity-1] way_tmem_we;                   // Tag memory write enable
-wire [0:associativity-1] way_dmem_we;                   // Data memory write enable
-wire [(32-1):0] way_data[0:associativity-1];      // Data read from data memory
-wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];// Tag read from tag memory
-wire [0:associativity-1] way_valid;                     // Indicates which ways are valid
-wire [0:associativity-1] way_match;                     // Indicates which ways matched
-wire miss;                                              // Indicates no ways matched
-
-wire [(addr_set_width-1):0] tmem_read_address;        // Tag memory read address
-wire [(addr_set_width-1):0] tmem_write_address;       // Tag memory write address
-wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;        // Data memory read address
-wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;       // Data memory write address
-wire [((addr_tag_width+1)-1):0] tmem_write_data;               // Tag memory write data
-reg [(32-1):0] dmem_write_data;                   // Data memory write data
-
-reg [2:0] state;                         // Current state of FSM
-wire flushing;                                          // Indicates if cache is currently flushing
-wire check;                                             // Indicates if cache is currently checking for hits/misses
-wire refill;                                            // Indicates if cache is currently refilling
-
-wire valid_store;                                       // Indicates if there is a valid store instruction
-reg [associativity-1:0] refill_way_select;              // Which way should be refilled
-reg [addr_offset_msb:addr_offset_lsb] refill_offset;           // Which word in cache line should be refilled
-wire last_refill;                                       // Indicates when on last cycle of cache refill
-reg [(addr_set_width-1):0] flush_set;                 // Which set is currently being flushed
-
-genvar i, j;
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-   generate
-      for (i = 0; i < associativity; i = i + 1)
-        begin : memories
-           // Way data
-           if ((addr_offset_width+addr_set_width) < 11)
-             begin : data_memories
-                lm32_ram
-                  #(
-                    // ----- Parameters -------
-                    .data_width (32),
-                    .address_width ((addr_offset_width+addr_set_width))
-// Modified for Milkymist: removed non-portable RAM parameters
-                    ) way_0_data_ram
-                    (
-                     // ----- Inputs -------
-                     .read_clk (clk_i),
-                     .write_clk (clk_i),
-                     .reset (rst_i),
-                     .read_address (dmem_read_address),
-                     .enable_read (read_port_enable),
-                     .write_address (dmem_write_address),
-                     .enable_write (write_port_enable),
-                     .write_enable (way_dmem_we[i]),
-                     .write_data (dmem_write_data),
-                     // ----- Outputs -------
-                     .read_data (way_data[i])
-                     );
-             end
-           else
-             begin
-                for (j = 0; j < 4; j = j + 1)
-                  begin : byte_memories
-                     lm32_ram
-                       #(
-                         // ----- Parameters -------
-                         .data_width (8),
-                         .address_width ((addr_offset_width+addr_set_width))
-// Modified for Milkymist: removed non-portable RAM parameters
-                         ) way_0_data_ram
-                         (
-                          // ----- Inputs -------
-                          .read_clk (clk_i),
-                          .write_clk (clk_i),
-                          .reset (rst_i),
-                          .read_address (dmem_read_address),
-                          .enable_read (read_port_enable),
-                          .write_address (dmem_write_address),
-                          .enable_write (write_port_enable),
-                          .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
-                          .write_data (dmem_write_data[(j+1)*8-1:j*8]),
-                          // ----- Outputs -------
-                          .read_data (way_data[i][(j+1)*8-1:j*8])
-                          );
-                  end
-             end
-
-           // Way tags
-           lm32_ram
-             #(
-               // ----- Parameters -------
-               .data_width ((addr_tag_width+1)),
-               .address_width (addr_set_width)
-// Modified for Milkymist: removed non-portable RAM parameters
-               ) way_0_tag_ram
-               (
-                // ----- Inputs -------
-                .read_clk (clk_i),
-                .write_clk (clk_i),
-                .reset (rst_i),
-                .read_address (tmem_read_address),
-                .enable_read (read_port_enable),
-                .write_address (tmem_write_address),
-                .enable_write (1'b1),
-                .write_enable (way_tmem_we[i]),
-                .write_data (tmem_write_data),
-                // ----- Outputs -------
-                .read_data ({way_tag[i], way_valid[i]})
-                );
-        end
-
-   endgenerate
-
-/////////////////////////////////////////////////////
-// Combinational logic
-/////////////////////////////////////////////////////
-
-// Compute which ways in the cache match the address being read
-generate
-    for (i = 0; i < associativity; i = i + 1)
-    begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[addr_tag_msb:addr_tag_lsb], 1'b1});
-    end
-endgenerate
-
-// Select data from way that matched the address being read
-generate
-    if (associativity == 1)
-         begin : data_1
-assign load_data = way_data[0];
-    end
-    else if (associativity == 2)
-         begin : data_2
-assign load_data = way_match[0] ? way_data[0] : way_data[1];
-    end
-endgenerate
-
-generate
-    if ((addr_offset_width+addr_set_width) < 11)
-    begin
-// Select data to write to data memories
-always @(*)
-begin
-    if (refill == 1'b1)
-        dmem_write_data = refill_data;
-    else
-    begin
-        dmem_write_data[7:0] = store_byte_select[0] ? store_data[7:0] : load_data[7:0];
-        dmem_write_data[15:8] = store_byte_select[1] ? store_data[15:8] : load_data[15:8];
-        dmem_write_data[23:16] = store_byte_select[2] ? store_data[23:16] : load_data[23:16];
-        dmem_write_data[31:24] = store_byte_select[3] ? store_data[31:24] : load_data[31:24];
-    end
-end
-    end
-    else
-    begin
-// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
-always @(*)
-begin
-    if (refill == 1'b1)
-        dmem_write_data = refill_data;
-    else
-        dmem_write_data = store_data;
-end
-    end
-endgenerate
-
-// Compute address to use to index into the data memories
-generate
-     if (bytes_per_line > 4)
-assign dmem_write_address = (refill == 1'b1)
-                            ? {refill_address[addr_set_msb:addr_set_lsb], refill_offset}
-                            : address_m[addr_set_msb:addr_offset_lsb];
-    else
-assign dmem_write_address = (refill == 1'b1)
-                            ? refill_address[addr_set_msb:addr_set_lsb]
-                            : address_m[addr_set_msb:addr_offset_lsb];
-endgenerate
-assign dmem_read_address = address_x[addr_set_msb:addr_offset_lsb];
-// Compute address to use to index into the tag memories
-assign tmem_write_address = (flushing == 1'b1)
-                            ? flush_set
-                            : refill_address[addr_set_msb:addr_set_lsb];
-assign tmem_read_address = address_x[addr_set_msb:addr_set_lsb];
-
-// Compute signal to indicate when we are on the last refill accesses
-generate
-    if (bytes_per_line > 4)
-assign last_refill = refill_offset == {addr_offset_width{1'b1}};
-    else
-assign last_refill = 1'b1;
-endgenerate
-
-// Compute data and tag memory access enable
-assign read_port_enable = (stall_x == 1'b0);
-assign write_port_enable = (refill_ready == 1'b1) || !stall_m;
-
-// Determine when we have a valid store
-assign valid_store = (store_q_m == 1'b1) && (check == 1'b1);
-
-// Compute data and tag memory write enables
-generate
-    if (associativity == 1)
-    begin : we_1
-assign way_dmem_we[0] = (refill_ready == 1'b1) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
-assign way_tmem_we[0] = (refill_ready == 1'b1) || (flushing == 1'b1);
-    end
-    else
-    begin : we_2
-assign way_dmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
-assign way_dmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || ((valid_store == 1'b1) && (way_match[1] == 1'b1));
-assign way_tmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || (flushing == 1'b1);
-assign way_tmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || (flushing == 1'b1);
-    end
-endgenerate
-
-// On the last refill cycle set the valid bit, for all other writes it should be cleared
-assign tmem_write_data[0] = ((last_refill == 1'b1) || (valid_store == 1'b1)) && (flushing == 1'b0);
-assign tmem_write_data[((addr_tag_width+1)-1):1] = refill_address[addr_tag_msb:addr_tag_lsb];
-
-// Signals that indicate which state we are in
-assign flushing = state[0];
-assign check = state[1];
-assign refill = state[2];
-
-assign miss = (~(|way_match)) && (load_q_m == 1'b1) && (stall_m == 1'b0)
-        && (~dtlb_miss_x)
-        ;
-assign stall_request = (check == 1'b0);
-
-/////////////////////////////////////////////////////
-// Sequential logic
-/////////////////////////////////////////////////////
-
-// Record way selected for replacement on a cache miss
-generate
-    if (associativity >= 2)
-    begin : way_select
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
-    else
-    begin
-        if (refill_request == 1'b1)
-            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
-    end
-end
-    end
-endgenerate
-
-// Record whether we are currently refilling
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        refilling <= 1'b0;
-    else
-        refilling <= refill;
-end
-
-// Instruction cache control FSM
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        state <= 3'b001;
-        flush_set <= {addr_set_width{1'b1}};
-        refill_request <= 1'b0;
-        refill_address <= {32{1'bx}};
-        restart_request <= 1'b0;
-    end
-    else
-    begin
-        case (state)
-
-        // Flush the cache
-        3'b001:
-        begin
-            if (flush_set == {addr_set_width{1'b0}})
-                state <= 3'b010;
-            flush_set <= flush_set - 1'b1;
-        end
-
-        // Check for cache misses
-        3'b010:
-        begin
-            if (stall_a == 1'b0)
-                restart_request <= 1'b0;
-            if (miss == 1'b1)
-            begin
-                refill_request <= 1'b1;
-                refill_address <= address_m;
-                state <= 3'b100;
-            end
-            else if (dflush == 1'b1)
-                state <= 3'b001;
-        end
-
-        // Refill a cache line
-        3'b100:
-        begin
-            refill_request <= 1'b0;
-            if (refill_ready == 1'b1)
-            begin
-                if (last_refill == 1'b1)
-                begin
-                    restart_request <= 1'b1;
-                    state <= 3'b010;
-                end
-            end
-        end
-
-        endcase
-    end
-end
-
-generate
-    if (bytes_per_line > 4)
-    begin
-// Refill offset
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        refill_offset <= {addr_offset_width{1'b0}};
-    else
-    begin
-        case (state)
-
-        // Check for cache misses
-        3'b010:
-        begin
-            if (miss == 1'b1)
-                refill_offset <= {addr_offset_width{1'b0}};
-        end
-
-        // Refill a cache line
-        3'b100:
-        begin
-            if (refill_ready == 1'b1)
-                refill_offset <= refill_offset + 1'b1;
-        end
-
-        endcase
-    end
-end
-    end
-endgenerate
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_debug.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_debug.v
deleted file mode 100644
index 12984d7..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_debug.v
+++ /dev/null
@@ -1,477 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_debug.v
-// Title            : Hardware debug registers and associated logic.
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : Fixed simulation bug which flares up when number of
-//                  : watchpoints is zero.
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-
-// States for single-step FSM
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_debug (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    pc_x,
-    load_x,
-    store_x,
-    load_store_address_x,
-    csr_write_enable_x,
-    csr_write_data,
-    csr_x,
-    eret_q_x,
-    bret_q_x,
-    stall_x,
-    exception_x,
-    q_x,
-    dcache_refill_request,
-    // ----- Outputs -------
-    dc_ss,
-    dc_re,
-    bp_match,
-    wp_match
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter breakpoints = 0;                      // Number of breakpoint CSRs
-parameter watchpoints = 0;                      // Number of watchpoint CSRs
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                    // Clock
-input rst_i;                                    // Reset
-
-input [((32-2)+2-1):2] pc_x;                      // X stage PC
-input load_x;                                   // Load instruction in X stage
-input store_x;                                  // Store instruction in X stage
-input [(32-1):0] load_store_address_x;    // Load or store effective address
-input csr_write_enable_x;                       // wcsr instruction in X stage
-input [(32-1):0] csr_write_data;          // Data to write to CSR
-input [(5-1):0] csr_x;                    // Which CSR to write
-input eret_q_x;                                 // eret instruction in X stage
-input bret_q_x;                                 // bret instruction in X stage
-input stall_x;                                  // Instruction in X stage is stalled
-input exception_x;                              // An exception has occured in X stage
-input q_x;                                      // Indicates the instruction in the X stage is qualified
-input dcache_refill_request;                    // Indicates data cache wants to be refilled
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output dc_ss;                                   // Single-step enable
-reg    dc_ss;
-output dc_re;                                   // Remap exceptions
-reg    dc_re;
-output bp_match;                                // Indicates a breakpoint has matched
-wire   bp_match;
-output wp_match;                                // Indicates a watchpoint has matched
-wire   wp_match;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-genvar i;                                       // Loop index for generate statements
-
-// Debug CSRs
-
-reg [((32-2)+2-1):2] bp_a[0:breakpoints-1];       // Instruction breakpoint address
-reg bp_e[0:breakpoints-1];                      // Instruction breakpoint enable
-wire [0:breakpoints-1]bp_match_n;               // Indicates if a h/w instruction breakpoint matched
-
-reg [1:0] wpc_c[0:watchpoints-1];   // Watchpoint enable
-reg [(32-1):0] wp[0:watchpoints-1];       // Watchpoint address
-wire [0:watchpoints-1]wp_match_n;               // Indicates if a h/w data watchpoint matched
-
-wire debug_csr_write_enable;                    // Debug CSR write enable (from either a wcsr instruction of external debugger)
-wire [(32-1):0] debug_csr_write_data;     // Data to write to debug CSR
-wire [(5-1):0] debug_csr;                 // Debug CSR to write to
-
-// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
-//reg [`LM32_DEBUG_SS_STATE_RNG] state;           // State of single-step FSM
-integer state;                                  // State of single-step FSM
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-// Check for breakpoints
-generate
-    for (i = 0; i < breakpoints; i = i + 1)
-    begin : bp_comb
-assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
-    end
-endgenerate
-generate
-    if (breakpoints > 0)
-assign bp_match = (|bp_match_n) || (state == 3'b011);
-    else
-assign bp_match = state == 3'b011;
-endgenerate
-
-// Check for watchpoints
-generate
-    for (i = 0; i < watchpoints; i = i + 1)
-    begin : wp_comb
-assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
-    end
-endgenerate
-generate
-    if (watchpoints > 0)
-assign wp_match = |wp_match_n;
-    else
-assign wp_match = 1'b0;
-endgenerate
-
-assign debug_csr_write_enable = csr_write_enable_x;
-assign debug_csr_write_data = csr_write_data;
-assign debug_csr = csr_x;
-
-/////////////////////////////////////////////////////
-// Sequential Logic
-/////////////////////////////////////////////////////
-
-// Breakpoint address and enable CSRs
-generate
-    for (i = 0; i < breakpoints; i = i + 1)
-    begin : bp_seq
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        bp_a[i] <= {(32-2){1'bx}};
-        bp_e[i] <= 1'b0;
-    end
-    else
-    begin
-        if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
-        begin
-            bp_a[i] <= debug_csr_write_data[((32-2)+2-1):2];
-            bp_e[i] <= debug_csr_write_data[0];
-        end
-    end
-end
-    end
-endgenerate
-
-// Watchpoint address and control flags CSRs
-generate
-    for (i = 0; i < watchpoints; i = i + 1)
-    begin : wp_seq
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        wp[i] <= {32{1'bx}};
-        wpc_c[i] <= 2'b00;
-    end
-    else
-    begin
-        if (debug_csr_write_enable == 1'b1)
-        begin
-            if (debug_csr == 5'h8)
-                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
-            if (debug_csr == 5'h18 + i)
-                wp[i] <= debug_csr_write_data;
-        end
-    end
-end
-    end
-endgenerate
-
-// Remap exceptions control bit
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        dc_re <= 1'b0;
-    else
-    begin
-        if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
-            dc_re <= debug_csr_write_data[1];
-    end
-end
-
-// Single-step control flag
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        state <= 3'b000;
-        dc_ss <= 1'b0;
-    end
-    else
-    begin
-        if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
-        begin
-            dc_ss <= debug_csr_write_data[0];
-            if (debug_csr_write_data[0] == 1'b0)
-                state <= 3'b000;
-            else
-                state <= 3'b001;
-        end
-        case (state)
-        3'b001:
-        begin
-            // Wait for eret or bret instruction to be executed
-            if (   (   (eret_q_x == 1'b1)
-                    || (bret_q_x == 1'b1)
-                    )
-                && (stall_x == 1'b0)
-               )
-                state <= 3'b010;
-        end
-        3'b010:
-        begin
-            // Wait for an instruction to be executed
-            if ((q_x == 1'b1) && (stall_x == 1'b0))
-                state <= 3'b011;
-        end
-        3'b011:
-        begin
-            // Wait for exception to be raised
-            if (dcache_refill_request == 1'b1)
-                state <= 3'b010;
-            else
-                 if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
-            begin
-                dc_ss <= 1'b0;
-                state <= 3'b100;
-            end
-        end
-        3'b100:
-        begin
-            // Watch to see if stepped instruction is restarted due to a cache miss
-            if (dcache_refill_request == 1'b1)
-                state <= 3'b010;
-            else
-                state <= 3'b000;
-        end
-        endcase
-    end
-end
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_decoder.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_decoder.v
deleted file mode 100644
index d5babdd..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_decoder.v
+++ /dev/null
@@ -1,557 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_decoder.v
-// Title            : Instruction decoder
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : Support for static branch prediction. Information about
-//                  : branch type is generated and passed on to the predictor.
-// Version          : 3.2
-//                  : No change
-// Version          : 3.3
-//                  : Renamed port names that conflict with keywords reserved
-//                  : in System-Verilog.
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-// Index of opcode field in an instruction
-
-// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_decoder (
-    // ----- Inputs -------
-    instruction,
-    // ----- Outputs -------
-    d_result_sel_0,
-    d_result_sel_1,
-    x_result_sel_csr,
-    x_result_sel_mc_arith,
-    x_result_sel_sext,
-    x_result_sel_logic,
-    x_result_sel_add,
-    m_result_sel_compare,
-    m_result_sel_shift,
-    w_result_sel_load,
-    w_result_sel_mul,
-    x_bypass_enable,
-    m_bypass_enable,
-    read_enable_0,
-    read_idx_0,
-    read_enable_1,
-    read_idx_1,
-    write_enable,
-    write_idx,
-    immediate,
-    branch_offset,
-    load,
-    store,
-    size,
-    sign_extend,
-    adder_op,
-    logic_op,
-    direction,
-    divide,
-    modulus,
-    branch,
-    branch_reg,
-    condition,
-    bi_conditional,
-    bi_unconditional,
-    break_opcode,
-    scall,
-    eret,
-    bret,
-    csr_write_enable
-    );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input [(32-1):0] instruction;       // Instruction to decode
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [0:0] d_result_sel_0;
-reg    [0:0] d_result_sel_0;
-output [1:0] d_result_sel_1;
-reg    [1:0] d_result_sel_1;
-output x_result_sel_csr;
-reg    x_result_sel_csr;
-output x_result_sel_mc_arith;
-reg    x_result_sel_mc_arith;
-output x_result_sel_sext;
-reg    x_result_sel_sext;
-output x_result_sel_logic;
-reg    x_result_sel_logic;
-output x_result_sel_add;
-reg    x_result_sel_add;
-output m_result_sel_compare;
-reg    m_result_sel_compare;
-output m_result_sel_shift;
-reg    m_result_sel_shift;
-output w_result_sel_load;
-reg    w_result_sel_load;
-output w_result_sel_mul;
-reg    w_result_sel_mul;
-output x_bypass_enable;
-wire   x_bypass_enable;
-output m_bypass_enable;
-wire   m_bypass_enable;
-output read_enable_0;
-wire   read_enable_0;
-output [(5-1):0] read_idx_0;
-wire   [(5-1):0] read_idx_0;
-output read_enable_1;
-wire   read_enable_1;
-output [(5-1):0] read_idx_1;
-wire   [(5-1):0] read_idx_1;
-output write_enable;
-wire   write_enable;
-output [(5-1):0] write_idx;
-wire   [(5-1):0] write_idx;
-output [(32-1):0] immediate;
-wire   [(32-1):0] immediate;
-output [((32-2)+2-1):2] branch_offset;
-wire   [((32-2)+2-1):2] branch_offset;
-output load;
-wire   load;
-output store;
-wire   store;
-output [1:0] size;
-wire   [1:0] size;
-output sign_extend;
-wire   sign_extend;
-output adder_op;
-wire   adder_op;
-output [3:0] logic_op;
-wire   [3:0] logic_op;
-output direction;
-wire   direction;
-output divide;
-wire   divide;
-output modulus;
-wire   modulus;
-output branch;
-wire   branch;
-output branch_reg;
-wire   branch_reg;
-output [(3-1):0] condition;
-wire   [(3-1):0] condition;
-output bi_conditional;
-wire bi_conditional;
-output bi_unconditional;
-wire bi_unconditional;
-output break_opcode;
-wire   break_opcode;
-output scall;
-wire   scall;
-output eret;
-wire   eret;
-output bret;
-wire   bret;
-output csr_write_enable;
-wire   csr_write_enable;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-wire [(32-1):0] extended_immediate;       // Zero or sign extended immediate
-wire [(32-1):0] high_immediate;           // Immediate as high 16 bits
-wire [(32-1):0] call_immediate;           // Call immediate
-wire [(32-1):0] branch_immediate;         // Conditional branch immediate
-wire sign_extend_immediate;                     // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
-wire select_high_immediate;                     // Whether to select the high immediate
-wire select_call_immediate;                     // Whether to select the call immediate
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Combinational logic
-/////////////////////////////////////////////////////
-
-// Determine opcode
-assign op_add    = instruction[30:26] == 5'b01101;
-assign op_and    = instruction[30:26] == 5'b01000;
-assign op_andhi  = instruction[31:26] == 6'b011000;
-assign op_b      = instruction[31:26] == 6'b110000;
-assign op_bi     = instruction[31:26] == 6'b111000;
-assign op_be     = instruction[31:26] == 6'b010001;
-assign op_bg     = instruction[31:26] == 6'b010010;
-assign op_bge    = instruction[31:26] == 6'b010011;
-assign op_bgeu   = instruction[31:26] == 6'b010100;
-assign op_bgu    = instruction[31:26] == 6'b010101;
-assign op_bne    = instruction[31:26] == 6'b010111;
-assign op_call   = instruction[31:26] == 6'b110110;
-assign op_calli  = instruction[31:26] == 6'b111110;
-assign op_cmpe   = instruction[30:26] == 5'b11001;
-assign op_cmpg   = instruction[30:26] == 5'b11010;
-assign op_cmpge  = instruction[30:26] == 5'b11011;
-assign op_cmpgeu = instruction[30:26] == 5'b11100;
-assign op_cmpgu  = instruction[30:26] == 5'b11101;
-assign op_cmpne  = instruction[30:26] == 5'b11111;
-assign op_divu   = instruction[31:26] == 6'b100011;
-assign op_lb     = instruction[31:26] == 6'b000100;
-assign op_lbu    = instruction[31:26] == 6'b010000;
-assign op_lh     = instruction[31:26] == 6'b000111;
-assign op_lhu    = instruction[31:26] == 6'b001011;
-assign op_lw     = instruction[31:26] == 6'b001010;
-assign op_modu   = instruction[31:26] == 6'b110001;
-assign op_mul    = instruction[30:26] == 5'b00010;
-assign op_nor    = instruction[30:26] == 5'b00001;
-assign op_or     = instruction[30:26] == 5'b01110;
-assign op_orhi   = instruction[31:26] == 6'b011110;
-assign op_raise  = instruction[31:26] == 6'b101011;
-assign op_rcsr   = instruction[31:26] == 6'b100100;
-assign op_sb     = instruction[31:26] == 6'b001100;
-assign op_sextb  = instruction[31:26] == 6'b101100;
-assign op_sexth  = instruction[31:26] == 6'b110111;
-assign op_sh     = instruction[31:26] == 6'b000011;
-assign op_sl     = instruction[30:26] == 5'b01111;
-assign op_sr     = instruction[30:26] == 5'b00101;
-assign op_sru    = instruction[30:26] == 5'b00000;
-assign op_sub    = instruction[31:26] == 6'b110010;
-assign op_sw     = instruction[31:26] == 6'b010110;
-assign op_user   = instruction[31:26] == 6'b110011;
-assign op_wcsr   = instruction[31:26] == 6'b110100;
-assign op_xnor   = instruction[30:26] == 5'b01001;
-assign op_xor    = instruction[30:26] == 5'b00110;
-
-// Group opcodes by function
-assign arith = op_add | op_sub;
-assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
-assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
-assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
-assign bi_unconditional = op_bi;
-assign bra = op_b | bi_unconditional | bi_conditional;
-assign call = op_call | op_calli;
-assign shift = op_sl | op_sr | op_sru;
-assign sext = op_sextb | op_sexth;
-assign multiply = op_mul;
-assign divide = op_divu;
-assign modulus = op_modu;
-assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
-assign store = op_sb | op_sh | op_sw;
-
-// Select pipeline multiplexor controls
-always @(*)
-begin
-    // D stage
-    if (call)
-        d_result_sel_0 = 1'b1;
-    else
-        d_result_sel_0 = 1'b0;
-    if (call)
-        d_result_sel_1 = 2'b00;
-    else if ((instruction[31] == 1'b0) && !bra)
-        d_result_sel_1 = 2'b10;
-    else
-        d_result_sel_1 = 2'b01;
-    // X stage
-    x_result_sel_csr = 1'b0;
-    x_result_sel_mc_arith = 1'b0;
-    x_result_sel_sext = 1'b0;
-    x_result_sel_logic = 1'b0;
-    x_result_sel_add = 1'b0;
-    if (op_rcsr)
-        x_result_sel_csr = 1'b1;
-    else if (divide | modulus)
-        x_result_sel_mc_arith = 1'b1;
-    else if (sext)
-        x_result_sel_sext = 1'b1;
-    else if (logical)
-        x_result_sel_logic = 1'b1;
-    else
-        x_result_sel_add = 1'b1;
-
-    // M stage
-
-    m_result_sel_compare = cmp;
-    m_result_sel_shift = shift;
-
-    // W stage
-    w_result_sel_load = load;
-    w_result_sel_mul = op_mul;
-end
-
-// Set if result is valid at end of X stage
-assign x_bypass_enable =  arith
-                        | logical
-                        | divide
-                        | modulus
-                        | sext
-                        | op_rcsr
-                        ;
-// Set if result is valid at end of M stage
-assign m_bypass_enable = x_bypass_enable
-                        | shift
-                        | cmp
-                        ;
-// Register file read port 0
-assign read_enable_0 = ~(op_bi | op_calli);
-assign read_idx_0 = instruction[25:21];
-// Register file read port 1
-assign read_enable_1 = ~(op_bi | op_calli | load);
-assign read_idx_1 = instruction[20:16];
-// Register file write port
-assign write_enable = ~(bra | op_raise | store | op_wcsr);
-assign write_idx = call
-                    ? 5'd29
-                    : instruction[31] == 1'b0
-                        ? instruction[20:16]
-                        : instruction[15:11];
-
-// Size of load/stores
-assign size = instruction[27:26];
-// Whether to sign or zero extend
-assign sign_extend = instruction[28];
-// Set adder_op to 1 to perform a subtraction
-assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
-// Logic operation (and, or, etc)
-assign logic_op = instruction[29:26];
-// Shift direction
-assign direction = instruction[29];
-// Control flow microcodes
-assign branch = bra | call;
-assign branch_reg = op_call | op_b;
-assign condition = instruction[28:26];
-assign break_opcode = op_raise & ~instruction[2];
-assign scall = op_raise & instruction[2];
-assign eret = op_b & (instruction[25:21] == 5'd30);
-assign bret = op_b & (instruction[25:21] == 5'd31);
-// CSR read/write
-assign csr_write_enable = op_wcsr;
-
-// Extract immediate from instruction
-
-assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
-assign select_high_immediate = op_andhi | op_orhi;
-assign select_call_immediate = instruction[31];
-
-assign high_immediate = {instruction[15:0], 16'h0000};
-assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
-assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
-assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
-
-assign immediate = select_high_immediate == 1'b1
-                        ? high_immediate
-                        : extended_immediate;
-
-assign branch_offset = select_call_immediate == 1'b1
-                        ? call_immediate
-                        : branch_immediate;
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dp_ram.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dp_ram.v
deleted file mode 100644
index b33adcf..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dp_ram.v
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * LatticeMico32
- * True dual-ported RAM
- *
- * Copyright (c) 2012 Michael Walle <michael@walle.cc>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_dp_ram (
-    // ----- Inputs -------
-    clk_a,
-    clk_b,
-    ce_a,
-    ce_b,
-    addr_a,
-    addr_b,
-    di_a,
-    di_b,
-    we_a,
-    we_b,
-    // ----- Outputs -------
-    do_a,
-    do_b
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter data_width = 1;               // Width of the data ports
-parameter address_width = 1;            // Width of the address ports
-parameter init_file = "NONE";           // Initialization file
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_a;                            // Clock port A
-input clk_b;                            // Clock port B
-
-input ce_a;                             // Clock enable port A
-input ce_b;                             // Clock enable port B
-input [address_width-1:0] addr_a;       // Read/write address port A
-input [address_width-1:0] addr_b;       // Read/write address port B
-input [data_width-1:0] di_a;            // Data input port A
-input [data_width-1:0] di_b;            // Data input port B
-input we_a;                             // Write enable port A
-input we_b;                             // Write enable port B
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [data_width-1:0] do_a;           // Data output port A
-wire   [data_width-1:0] do_a;
-
-output [data_width-1:0] do_b;           // Data output port B
-wire   [data_width-1:0] do_b;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-reg [data_width-1:0]    mem[0:(1<<address_width)-1];
-reg [address_width-1:0] ra_a;           // Registered read address port A
-reg [address_width-1:0] ra_b;           // Registered read address port B
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Combinational logic
-/////////////////////////////////////////////////////
-
-// Read ports
-assign do_a = mem[ra_a];
-assign do_b = mem[ra_b];
-
-/////////////////////////////////////////////////////
-// Sequential logic
-/////////////////////////////////////////////////////
-
-// Write ports
-always @(posedge clk_a)
-    if ((ce_a == 1'b1) && (we_a == 1'b1))
-        mem[addr_a] <= di_a;
-
-always @(posedge clk_b)
-    if ((ce_b == 1'b1) && (we_b == 1'b1))
-        mem[addr_b] <= di_b;
-
-// Register read addresses for use on next cycle
-always @(posedge clk_a)
-    if (ce_a == 1'b1)
-        ra_a <= addr_a;
-
-always @(posedge clk_b)
-    if (ce_b == 1'b1)
-        ra_b <= addr_b;
-
-/////////////////////////////////////////////////////
-// Initialization
-/////////////////////////////////////////////////////
-
-generate
-    if (init_file != "NONE")
-    begin
-initial $readmemh(init_file, mem);
-    end
-endgenerate
-    
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dtlb.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dtlb.v
deleted file mode 100644
index 555c863..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_dtlb.v
+++ /dev/null
@@ -1,449 +0,0 @@
-/*
- * LatticeMico32
- * Data Translation Lookaside Buffer
- *
- * Copyright (c) 2011-2012 Yann Sionneau <yann.sionneau@gmail.com>
- * Copyright (c) 2012 Michael Walle <michael@walle.cc>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-
-
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_dtlb (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    enable,
-    stall_x,
-    stall_m,
-    address_x,
-    address_m,
-    load_d,
-    store_d,
-    load_q_x,
-    store_q_x,
-    load_q_m,
-    store_q_m,
-    tlbpaddr,
-    tlbvaddr,
-    update,
-    flush,
-    invalidate,
-    // ----- Outputs -----
-    physical_load_store_address_m,
-    stall_request,
-    miss_vfn,
-    miss_x,
-    fault_x,
-    cache_inhibit_x
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter entries = 1024;               // Number of entries in DTLB
-parameter page_size = 4096;             // DTLB page size
-
-localparam offset_width = $clog2;
-localparam index_width = $clog2;
-localparam offset_lsb = 0;
-localparam offset_msb = (offset_lsb+offset_width-1);
-localparam index_lsb = (offset_msb+1);
-localparam index_msb = (index_lsb+index_width-1);
-localparam tag_lsb = (index_msb+1);
-localparam tag_msb = (32-1);
-localparam tag_width = (tag_msb-tag_lsb+1);
-localparam vpfn_lsb = (offset_msb+1);
-localparam vpfn_msb = (32-1);
-localparam vpfn_width = (vpfn_msb-vpfn_lsb+1);
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                            // Clock
-input rst_i;                            // Reset
-
-input enable;                           // Data TLB enable
-
-input stall_x;                          // Stall X stage
-input stall_m;                          // Stall M stage
-
-input [(32-1):0] address_x;       // X stage load/store address
-input [(32-1):0] address_m;       // M stage load/store address
-input load_d;                           // Load instruction in D stage
-input store_d;                          // Store instruction in D stage
-input load_q_x;                         // Load instruction in X stage
-input store_q_x;                        // Store instruction in X stage
-input load_q_m;                         // Load instruction in M stage
-input store_q_m;                        // Store instruction in M stage
-
-input [(32-1):0] tlbpaddr;
-input [(32-1):0] tlbvaddr;
-input update;
-input flush;
-input invalidate;
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [(32-1):0] physical_load_store_address_m;
-wire   [(32-1):0] physical_load_store_address_m;
-output stall_request;
-wire   stall_request;
-output [(32-1):0] miss_vfn;
-wire   [(32-1):0] miss_vfn;
-output miss_x;
-wire   miss_x;
-output fault_x;
-wire   fault_x;
-output cache_inhibit_x;
-wire   cache_inhibit_x;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-wire [(index_width-1):0] read_address;
-wire [(index_width-1):0] write_address;
-wire [((vpfn_width+tag_width+3)  -1):0] write_data;
-wire [((vpfn_width+tag_width+3)  -1):0] tlbe;
-wire [((vpfn_width+tag_width+3)  -1):0] tlbe_inval;
-wire [tag_msb:tag_lsb] tlbe_tag_x;
-wire [vpfn_msb:vpfn_lsb] tlbe_pfn_x;
-wire tlbe_valid_x;
-wire tlbe_ro_x;
-wire tlbe_ci_x;
-wire checking;
-wire flushing;
-wire write_port_enable;
-
-reg [1:0] state;                         // Current state of FSM
-reg [(index_width-1):0] flush_set;
-reg [vpfn_msb:vpfn_lsb] tlbe_pfn_m;
-reg lookup;
-
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-lm32_ram
-  #(
-    // ----- Parameters -------
-    .data_width ((vpfn_width+tag_width+3)  ),
-    .address_width (index_width)
-// Modified for Milkymist: removed non-portable RAM parameters
-    ) data_ram
-    (
-     // ----- Inputs -------
-     .read_clk (clk_i),
-     .write_clk (clk_i),
-     .reset (rst_i),
-     .read_address (read_address),
-     .enable_read (lookup),
-     .write_address (write_address),
-     .enable_write (1'b1),
-     .write_enable (write_port_enable),
-     .write_data (write_data),
-     // ----- Outputs -------
-     .read_data ({tlbe_pfn_x, tlbe_tag_x, tlbe_ci_x, tlbe_ro_x, tlbe_valid_x})
-     );
-
-/////////////////////////////////////////////////////
-// Combinational logic
-/////////////////////////////////////////////////////
-
-// Compute address to use to index into the DTLB data memory
-assign read_address = address_x[index_msb:index_lsb];
-
-// tlb_update_address will receive data from a CSR register
-assign write_address = (flushing == 1'b1)
-                            ? flush_set
-                            : tlbvaddr[index_msb:index_lsb];
-
-assign write_port_enable = (update == 1'b1) || (invalidate == 1'b1) || (flushing == 1'b1);
-
-assign physical_load_store_address_m = (enable == 1'b0)
-                ? address_m
-                : {tlbe_pfn_m, address_m[offset_msb:offset_lsb]};
-
-assign tlbe = {
-        tlbpaddr[vpfn_msb:vpfn_lsb],     // pfn
-        tlbvaddr[tag_msb:tag_lsb],      // tag
-        tlbpaddr[2],                       // cache inhibit
-        tlbpaddr[1],                       // read only
-        1'b1};                            // valid
-assign tlbe_inval = {{(vpfn_width+tag_width+3)  -1{1'b0}}, 1'b0};
-assign write_data = ((invalidate == 1'b1) || (flushing)) ? tlbe_inval : tlbe;
-
-
-assign tlbe_match = ({tlbe_tag_x, tlbe_valid_x} == {address_x[tag_msb:tag_lsb], 1'b1});
-
-assign miss_vfn = {address_x[vpfn_msb:vpfn_lsb], {offset_width{1'b0}}};
-assign miss_x = ((enable == 1'b1) && ((load_q_x == 1'b1) || (store_q_x == 1'b1)) && (tlbe_match == 1'b0) && (lookup == 1'b0));
-assign cache_inhibit_x = ((enable == 1'b1) && (tlbe_ci_x == 1'b1));
-assign fault_x = ((enable == 1'b1) && (store_q_x == 1'b1) && (tlbe_match == 1'b1) && (tlbe_ro_x == 1'b1));
-
-assign checking = state[0];
-assign flushing = state[1];
-assign stall_request = (flushing == 1'b1) || (lookup == 1'b1);
-
-/////////////////////////////////////////////////////
-// Sequential logic
-/////////////////////////////////////////////////////
-
-// Lookup logic
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        lookup <= 1'b0;
-    else
-    begin
-        if ((enable == 1'b1) && (stall_x == 1'b0) && ((load_d == 1'b1) || (store_d == 1'b1)))
-            lookup <= 1'b1;
-        else
-            lookup <= 1'b0;
-    end
-end
-
-// X/M stage registers
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        tlbe_pfn_m <= {vpfn_width{1'bx}};
-    else if (stall_m == 1'b0)
-        tlbe_pfn_m <= tlbe_pfn_x;
-end
-
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        flush_set <= {index_width{1'b1}};
-        state <= 2'b10;
-    end
-    else
-    begin
-        case (state)
-
-        2'b01:
-        begin
-            if (flush == 1'b1) begin
-                flush_set <= {index_width{1'b1}};
-                state <= 2'b10;
-            end
-        end
-
-        2'b10:
-        begin
-            if (flush_set == {index_width{1'b0}})
-                state <= 2'b01;
-            flush_set <= flush_set - 1'b1;
-        end
-
-        endcase
-    end
-end
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_icache.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_icache.v
deleted file mode 100644
index da82343..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_icache.v
+++ /dev/null
@@ -1,621 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_icache.v
-// Title            : Instruction cache
-// Dependencies     : lm32_include.v
-//
-// Version 3.5
-// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
-//    cause segmentation fault due to incorrect fetches.
-//
-// Version 3.1
-// 1. Feature: Support for user-selected resource usage when implementing
-//    cache memory. Additional parameters must be defined when invoking module
-//    lm32_ram. Instruction cache miss mechanism is dependent on branch
-//    prediction being performed in D stage of pipeline.
-//
-// Version 7.0SP2, 3.0
-// No change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-
-
-
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_icache (
-    // ----- Inputs -----
-    clk_i,
-    rst_i,
-    stall_a,
-    stall_f,
-    address_a,
-    address_f,
-    physical_address_f,
-    read_enable_f,
-    refill_ready,
-    refill_data,
-    iflush,
-    valid_d,
-    branch_predict_taken_d,
-    // ----- Outputs -----
-    stall_request,
-    restart_request,
-    refill_request,
-    refill_address,
-    physical_refill_address,
-    refilling,
-    inst
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter associativity = 1;                            // Associativity of the cache (Number of ways)
-parameter sets = 512;                                   // Number of sets
-parameter bytes_per_line = 16;                          // Number of bytes per cache line
-parameter base_address = 0;                             // Base address of cachable memory
-parameter limit = 0;                                    // Limit (highest address) of cachable memory
-
-localparam addr_offset_width = $clog2-2;
-localparam addr_set_width = $clog2;
-localparam addr_offset_lsb = 2;
-localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
-localparam addr_set_lsb = (addr_offset_msb+1);
-localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
-localparam addr_tag_lsb = (addr_offset_msb+1);
-localparam addr_tag_msb = $clog2;
-localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                        // Clock
-input rst_i;                                        // Reset
-
-input stall_a;                                      // Stall instruction in A stage
-input stall_f;                                      // Stall instruction in F stage
-
-input valid_d;                                      // Valid instruction in D stage
-input branch_predict_taken_d;                       // Instruction in D stage is a branch and is predicted taken
-
-input [((32-2)+2-1):2] address_a;                     // Address of instruction in A stage
-input [((32-2)+2-1):2] address_f;                     // Address of instruction in F stage
-input [((32-2)+2-1):2] physical_address_f;            // Physical address of instruction in F stage
-input read_enable_f;                                // Indicates if cache access is valid
-
-input refill_ready;                                 // Next word of refill data is ready
-input [(32-1):0] refill_data;          // Data to refill the cache with
-
-input iflush;                                       // Flush the cache
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output stall_request;                               // Request to stall the pipeline
-wire   stall_request;
-output restart_request;                             // Request to restart instruction that caused the cache miss
-reg    restart_request;
-output refill_request;                              // Request to refill a cache line
-wire   refill_request;
-output [((32-2)+2-1):2] refill_address;               // Base address of cache refill
-reg    [((32-2)+2-1):2] refill_address;
-output [((32-2)+2-1):2] physical_refill_address;      // Physical base address of cache refill
-reg    [((32-2)+2-1):2] physical_refill_address;
-output refilling;                                   // Indicates the instruction cache is currently refilling
-reg    refilling;
-output [(32-1):0] inst;                // Instruction read from cache
-wire   [(32-1):0] inst;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-wire enable;
-wire [0:associativity-1] way_mem_we;
-wire [(32-1):0] way_data[0:associativity-1];
-wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
-wire [0:associativity-1] way_valid;
-wire [0:associativity-1] way_match;
-wire miss;
-
-wire [(addr_set_width-1):0] tmem_read_address;
-wire [(addr_set_width-1):0] tmem_write_address;
-wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [((addr_tag_width+1)-1):0] tmem_write_data;
-
-reg [3:0] state;
-wire flushing;
-wire check;
-wire refill;
-
-reg [associativity-1:0] refill_way_select;
-reg [addr_offset_msb:addr_offset_lsb] refill_offset;
-wire last_refill;
-reg [(addr_set_width-1):0] flush_set;
-
-genvar i;
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-   generate
-      for (i = 0; i < associativity; i = i + 1)
-        begin : memories
-
-           lm32_ram
-             #(
-               // ----- Parameters -------
-               .data_width                 (32),
-               .address_width              ((addr_offset_width+addr_set_width))
-// Modified for Milkymist: removed non-portable RAM parameters
-)
-           way_0_data_ram
-             (
-              // ----- Inputs -------
-              .read_clk                   (clk_i),
-              .write_clk                  (clk_i),
-              .reset                      (rst_i),
-              .read_address               (dmem_read_address),
-              .enable_read                (enable),
-              .write_address              (dmem_write_address),
-              .enable_write               (1'b1),
-              .write_enable               (way_mem_we[i]),
-              .write_data                 (refill_data),
-              // ----- Outputs -------
-              .read_data                  (way_data[i])
-              );
-
-           lm32_ram
-             #(
-               // ----- Parameters -------
-               .data_width                 ((addr_tag_width+1)),
-               .address_width              (addr_set_width)
-// Modified for Milkymist: removed non-portable RAM parameters
-               )
-           way_0_tag_ram
-             (
-              // ----- Inputs -------
-              .read_clk                   (clk_i),
-              .write_clk                  (clk_i),
-              .reset                      (rst_i),
-              .read_address               (tmem_read_address),
-              .enable_read                (enable | flushing),
-              .write_address              (tmem_write_address),
-              .enable_write               (1'b1),
-              .write_enable               (way_mem_we[i] | flushing),
-              .write_data                 (tmem_write_data),
-              // ----- Outputs -------
-              .read_data                  ({way_tag[i], way_valid[i]})
-              );
-
-        end
-endgenerate
-
-/////////////////////////////////////////////////////
-// Combinational logic
-/////////////////////////////////////////////////////
-
-// Compute which ways in the cache match the address address being read
-generate
-    for (i = 0; i < associativity; i = i + 1)
-    begin : match
-assign way_match[i] =
-        ({way_tag[i], way_valid[i]} == {physical_address_f[addr_tag_msb:addr_tag_lsb], 1'b1});
-    end
-endgenerate
-
-// Select data from way that matched the address being read
-generate
-    if (associativity == 1)
-    begin : inst_1
-assign inst = way_match[0] ? way_data[0] : 32'b0;
-    end
-    else if (associativity == 2)
-         begin : inst_2
-assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
-    end
-endgenerate
-
-// Compute address to use to index into the data memories
-generate
-    if (bytes_per_line > 4)
-assign dmem_write_address = {refill_address[addr_set_msb:addr_set_lsb], refill_offset};
-    else
-assign dmem_write_address = refill_address[addr_set_msb:addr_set_lsb];
-endgenerate
-
-assign dmem_read_address = address_a[addr_set_msb:addr_offset_lsb];
-
-// Compute address to use to index into the tag memories
-assign tmem_read_address = address_a[addr_set_msb:addr_set_lsb];
-assign tmem_write_address = flushing
-                                ? flush_set
-                                : refill_address[addr_set_msb:addr_set_lsb];
-
-// Compute signal to indicate when we are on the last refill accesses
-generate
-    if (bytes_per_line > 4)
-assign last_refill = refill_offset == {addr_offset_width{1'b1}};
-    else
-assign last_refill = 1'b1;
-endgenerate
-
-// Compute data and tag memory access enable
-assign enable = (stall_a == 1'b0);
-
-// Compute data and tag memory write enables
-generate
-    if (associativity == 1)
-    begin : we_1
-assign way_mem_we[0] = (refill_ready == 1'b1);
-    end
-    else
-    begin : we_2
-assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
-assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
-    end
-endgenerate
-
-// On the last refill cycle set the valid bit, for all other writes it should be cleared
-assign tmem_write_data[0] = last_refill & !flushing;
-assign tmem_write_data[((addr_tag_width+1)-1):1] =
-       physical_refill_address[addr_tag_msb:addr_tag_lsb];
-
-// Signals that indicate which state we are in
-assign flushing = |state[1:0];
-assign check = state[2];
-assign refill = state[3];
-
-assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
-assign stall_request = (check == 1'b0);
-assign refill_request = (refill == 1'b1);
-
-/////////////////////////////////////////////////////
-// Sequential logic
-/////////////////////////////////////////////////////
-
-// Record way selected for replacement on a cache miss
-generate
-    if (associativity >= 2)
-    begin : way_select
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
-    else
-    begin
-        if (miss == 1'b1)
-            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
-    end
-end
-    end
-endgenerate
-
-// Record whether we are refilling
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        refilling <= 1'b0;
-    else
-        refilling <= refill;
-end
-
-// Instruction cache control FSM
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        state <= 4'b0001;
-        flush_set <= {addr_set_width{1'b1}};
-        refill_address <= {(32-2){1'b0}};
-        physical_refill_address <= {(32-2){1'b0}};
-        restart_request <= 1'b0;
-    end
-    else
-    begin
-        case (state)
-
-        // Flush the cache for the first time after reset
-        4'b0001:
-        begin
-            if (flush_set == {addr_set_width{1'b0}})
-                state <= 4'b0100;
-            flush_set <= flush_set - 1'b1;
-        end
-
-        // Flush the cache in response to an write to the ICC CSR
-        4'b0010:
-        begin
-            if (flush_set == {addr_set_width{1'b0}})
-                state <= 4'b0100;
-
-            flush_set <= flush_set - 1'b1;
-        end
-
-        // Check for cache misses
-        4'b0100:
-        begin
-            if (stall_a == 1'b0)
-                restart_request <= 1'b0;
-            if (iflush == 1'b1)
-            begin
-                physical_refill_address <= physical_address_f;
-                refill_address <= address_f;
-                state <= 4'b0010;
-            end
-            else if (miss == 1'b1)
-            begin
-                physical_refill_address <= physical_address_f;
-                refill_address <= address_f;
-                state <= 4'b1000;
-            end
-        end
-
-        // Refill a cache line
-        4'b1000:
-        begin
-            if (refill_ready == 1'b1)
-            begin
-                if (last_refill == 1'b1)
-                begin
-                    restart_request <= 1'b1;
-                    state <= 4'b0100;
-                end
-            end
-        end
-
-        endcase
-    end
-end
-
-generate
-    if (bytes_per_line > 4)
-    begin
-// Refill offset
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        refill_offset <= {addr_offset_width{1'b0}};
-    else
-    begin
-        case (state)
-
-        // Check for cache misses
-        4'b0100:
-        begin
-            if (iflush == 1'b1)
-                refill_offset <= {addr_offset_width{1'b0}};
-            else if (miss == 1'b1)
-                refill_offset <= {addr_offset_width{1'b0}};
-        end
-
-        // Refill a cache line
-        4'b1000:
-        begin
-            if (refill_ready == 1'b1)
-                refill_offset <= refill_offset + 1'b1;
-        end
-
-        endcase
-    end
-end
-    end
-endgenerate
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_include.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_include.v
deleted file mode 100644
index e03c77f..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_include.v
+++ /dev/null
@@ -1,163 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_instruction_unit.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_instruction_unit.v
deleted file mode 100644
index dd1dc9f..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_instruction_unit.v
+++ /dev/null
@@ -1,714 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project      : LatticeMico32
-// File         : lm32_instruction_unit.v
-// Title        : Instruction unit
-// Dependencies : lm32_include.v
-// Version      : 6.1.17
-//              : Initial Release
-// Version      : 7.0SP2, 3.0
-//              : No Change
-// Version      : 3.1
-//              : Support for static branch prediction is added. Fetching of
-//              : instructions can also be altered by branches predicted in D
-//              : stage of pipeline, and mispredicted branches in the X and M
-//              : stages of the pipeline.
-// Version      : 3.2
-//              : EBRs use SYNC resets instead of ASYNC resets.
-// Version      : 3.3
-//              : Support for a non-cacheable Instruction Memory that has a
-//              : single-cycle access latency. This memory can be accessed by
-//              : data port of LM32 (so that debugger has access to it).
-// Version      : 3.4
-//              : No change
-// Version      : 3.5
-//              : Bug fix: Inline memory is correctly generated if it is not a
-//              : power-of-two.
-//              : Bug fix: Fixed a bug that caused LM32 (configured without
-//              : instruction cache) to lock up in to an infinite loop due to a
-//              : instruction bus error when EBA was set to instruction inline
-//              : memory.
-// Version      : 3.8
-//              : Feature: Support for dynamically switching EBA to DEBA via a
-//              : GPIO.
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_instruction_unit (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    // From pipeline
-    stall_a,
-    stall_f,
-    stall_d,
-    stall_x,
-    stall_m,
-    valid_f,
-    valid_d,
-    kill_f,
-    branch_predict_taken_d,
-    branch_predict_address_d,
-    exception_m,
-    branch_taken_m,
-    branch_mispredict_taken_m,
-    branch_target_m,
-    iflush,
-    dcache_restart_request,
-    dcache_refill_request,
-    dcache_refilling,
-    itlb_enable,
-    tlbpaddr,
-    tlbvaddr,
-    itlb_update,
-    itlb_flush,
-    itlb_invalidate,
-    // From Wishbone
-    i_dat_i,
-    i_ack_i,
-    i_err_i,
-    // ----- Outputs -------
-    // To pipeline
-    pc_f,
-    pc_d,
-    pc_x,
-    pc_m,
-    pc_w,
-    icache_stall_request,
-    icache_restart_request,
-    icache_refill_request,
-    icache_refilling,
-    itlb_stall_request,
-    itlb_miss_vfn,
-    itlb_miss_x,
-    // To Wishbone
-    i_dat_o,
-    i_adr_o,
-    i_cyc_o,
-    i_sel_o,
-    i_stb_o,
-    i_we_o,
-    i_cti_o,
-    i_lock_o,
-    i_bte_o,
-    bus_error_d,
-    instruction_f,
-    instruction_d
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter eba_reset = 32'h0;
-parameter associativity = 1;                            // Associativity of the cache (Number of ways)
-parameter sets = 512;                                   // Number of sets
-parameter bytes_per_line = 16;                          // Number of bytes per cache line
-parameter base_address = 0;                             // Base address of cachable memory
-parameter limit = 0;                                    // Limit (highest address) of cachable memory
-
-// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
-localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2-2;
-localparam addr_offset_lsb = 2;
-localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                            // Clock
-input rst_i;                                            // Reset
-
-
-input stall_a;                                          // Stall A stage instruction
-input stall_f;                                          // Stall F stage instruction
-input stall_d;                                          // Stall D stage instruction
-input stall_x;                                          // Stall X stage instruction
-input stall_m;                                          // Stall M stage instruction
-input valid_f;                                          // Instruction in F stage is valid
-input valid_d;                                          // Instruction in D stage is valid
-input kill_f;                                           // Kill instruction in F stage
-
-input branch_predict_taken_d;                           // Branch is predicted taken in D stage
-input [((32-2)+2-1):2] branch_predict_address_d;          // Branch target address
-
-input exception_m;
-input branch_taken_m;                                   // Branch instruction in M stage is taken
-input branch_mispredict_taken_m;                        // Branch instruction in M stage is mispredicted as taken
-input [((32-2)+2-1):2] branch_target_m;                   // Target PC of M stage branch instruction
-
-input iflush;                                           // Flush instruction cache
-input dcache_restart_request;                           // Restart instruction that caused a data cache miss
-input dcache_refill_request;                            // Request to refill data cache
-input dcache_refilling;
-
-
-input itlb_enable;                                      // Instruction TLB enable
-input [(32-1):0] tlbpaddr;                        // TLBPADDR CSR
-input [(32-1):0] tlbvaddr;                        // TLBVADDR CSR
-input itlb_update;                                      // Instruction TLB update request
-input itlb_flush;                                       // Instruction TLB flush request
-input itlb_invalidate;                                  // Instruction TLB invalidate request
-
-input [(32-1):0] i_dat_i;                         // Instruction Wishbone interface read data
-input i_ack_i;                                          // Instruction Wishbone interface acknowledgement
-input i_err_i;                                          // Instruction Wishbone interface error
-
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [((32-2)+2-1):2] pc_f;                             // F stage PC
-reg    [((32-2)+2-1):2] pc_f;
-output [((32-2)+2-1):2] pc_d;                             // D stage PC
-reg    [((32-2)+2-1):2] pc_d;
-output [((32-2)+2-1):2] pc_x;                             // X stage PC
-reg    [((32-2)+2-1):2] pc_x;
-output [((32-2)+2-1):2] pc_m;                             // M stage PC
-reg    [((32-2)+2-1):2] pc_m;
-output [((32-2)+2-1):2] pc_w;                             // W stage PC
-reg    [((32-2)+2-1):2] pc_w;
-
-output icache_stall_request;                            // Instruction cache stall request
-wire   icache_stall_request;
-output icache_restart_request;                          // Request to restart instruction that cached instruction cache miss
-wire   icache_restart_request;
-output icache_refill_request;                           // Instruction cache refill request
-wire   icache_refill_request;
-output icache_refilling;                                // Indicates the icache is refilling
-wire   icache_refilling;
-
-
-output itlb_stall_request;                              // Instruction TLB stall request
-wire   itlb_stall_request;
-output [(32-1):0] itlb_miss_vfn;                  // Virtual frame number of missed instruction
-wire   [(32-1):0] itlb_miss_vfn;
-output itlb_miss_x;                                     // Indicates if an instruction TLB miss occured in X stage
-wire   itlb_miss_x;
-
-output [(32-1):0] i_dat_o;                        // Instruction Wishbone interface write data
-wire   [(32-1):0] i_dat_o;
-output [(32-1):0] i_adr_o;                        // Instruction Wishbone interface address
-reg    [(32-1):0] i_adr_o;
-output i_cyc_o;                                         // Instruction Wishbone interface cycle
-reg    i_cyc_o;
-output [(4-1):0] i_sel_o;                 // Instruction Wishbone interface byte select
-wire   [(4-1):0] i_sel_o;
-output i_stb_o;                                         // Instruction Wishbone interface strobe
-reg    i_stb_o;
-output i_we_o;                                          // Instruction Wishbone interface write enable
-wire   i_we_o;
-output [(3-1):0] i_cti_o;                       // Instruction Wishbone interface cycle type
-reg    [(3-1):0] i_cti_o;
-output i_lock_o;                                        // Instruction Wishbone interface lock bus
-reg    i_lock_o;
-output [(2-1):0] i_bte_o;                       // Instruction Wishbone interface burst type
-wire   [(2-1):0] i_bte_o;
-
-
-output bus_error_d;                                     // Indicates a bus error occured while fetching the instruction
-reg    bus_error_d;
-output [(32-1):0] instruction_f;           // F stage instruction (only to have register indices extracted from)
-wire   [(32-1):0] instruction_f;
-output [(32-1):0] instruction_d;           // D stage instruction to be decoded
-reg    [(32-1):0] instruction_d;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-reg [((32-2)+2-1):2] pc_a;                                // A stage PC
-
-reg [((32-2)+2-1):2] restart_address;                     // Address to restart from after a cache miss
-
-wire icache_read_enable_f;                              // Indicates if instruction cache miss is valid
-wire [((32-2)+2-1):2] icache_refill_address;              // Address that caused cache miss
-wire [((32-2)+2-1):2] icache_physical_refill_address;     // Physical address that caused cache miss
-reg icache_refill_ready;                                // Indicates when next word of refill data is ready to be written to cache
-reg [(32-1):0] icache_refill_data;         // Next word of refill data, fetched from Wishbone
-wire [(32-1):0] icache_data_f;             // Instruction fetched from instruction cache
-wire [(3-1):0] first_cycle_type;                // First Wishbone cycle type
-wire [(3-1):0] next_cycle_type;                 // Next Wishbone cycle type
-wire last_word;                                         // Indicates if this is the last word in the cache line
-wire [((32-2)+2-1):2] first_address;                      // First cache refill address
-reg bus_error_f;                                        // Indicates if a bus error occured while fetching the instruction in the F stage
-
-
-
-wire [((32-2)+2-1):2] physical_pc_f;                      // F stage physical PC
-wire itlb_miss_f;                                       // Indicates if an instruction TLB miss occured in F stage
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-// Instruction ROM
-
-// Instruction cache
-lm32_icache #(
-    .associativity          (associativity),
-    .sets                   (sets),
-    .bytes_per_line         (bytes_per_line),
-    .base_address           (base_address),
-    .limit                  (limit)
-    ) icache (
-    // ----- Inputs -----
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    .stall_a                (stall_a),
-    .stall_f                (stall_f),
-    .branch_predict_taken_d (branch_predict_taken_d),
-    .valid_d                (valid_d),
-    .address_a              (pc_a),
-    .address_f              (pc_f),
-    .physical_address_f     (physical_pc_f),
-    .read_enable_f          (icache_read_enable_f),
-    .refill_ready           (icache_refill_ready),
-    .refill_data            (icache_refill_data),
-    .iflush                 (iflush),
-    // ----- Outputs -----
-    .stall_request          (icache_stall_request),
-    .restart_request        (icache_restart_request),
-    .refill_request         (icache_refill_request),
-    .refill_address         (icache_refill_address),
-    .physical_refill_address(icache_physical_refill_address),
-    .refilling              (icache_refilling),
-    .inst                   (icache_data_f)
-    );
-
-// Instruction TLB
-lm32_itlb itlb (
-    // ----- Inputs -----
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    .enable                 (itlb_enable),
-    .stall_a                (stall_a),
-    .stall_f                (stall_f),
-    .stall_d                (stall_d),
-    .stall_x                (stall_x),
-    .pc_a                   (pc_a),
-    .pc_f                   (pc_f),
-    .pc_x                   (pc_x),
-    .read_enable_f          (icache_read_enable_f),
-    .tlbpaddr               (tlbpaddr),
-    .tlbvaddr               (tlbvaddr),
-    .update                 (itlb_update),
-    .flush                  (itlb_flush),
-    .invalidate             (itlb_invalidate),
-    // ----- Outputs -----
-    .physical_pc_f          (physical_pc_f),
-    .stall_request          (itlb_stall_request),
-    .miss_vfn               (itlb_miss_vfn),
-    .miss_f                 (itlb_miss_f),
-    .miss_x                 (itlb_miss_x)
-    );
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-// Generate signal that indicates when instruction cache misses are valid
-assign icache_read_enable_f =    (valid_f == 1'b1)
-                              && (kill_f == 1'b0)
-                              && (dcache_restart_request == 1'b0)
-                              && (itlb_miss_f == 1'b0)
-                              ;
-
-// Compute address of next instruction to fetch
-always @(*)
-begin
-    // The request from the latest pipeline stage must take priority
-    if (dcache_restart_request == 1'b1)
-        pc_a = restart_address;
-    else
-      if (branch_taken_m == 1'b1)
-        if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
-          pc_a = pc_x;
-        else
-          pc_a = branch_target_m;
-      else
-        if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
-          pc_a = branch_predict_address_d;
-        else
-          if (icache_restart_request == 1'b1)
-            pc_a = restart_address;
-          else
-            pc_a = pc_f + 1'b1;
-end
-
-// Select where instruction should be fetched from
-
-// Select instruction from selected source
-assign instruction_f = icache_data_f;
-
-// Unused/constant Wishbone signals
-assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
-assign i_sel_o = 4'b1111;
-assign i_bte_o = 2'b00;
-
-// Determine parameters for next cache refill Wishbone access
-generate
-    case (bytes_per_line)
-    4:
-    begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
-assign first_address = icache_physical_refill_address;
-    end
-    8:
-    begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
-assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
-assign first_address = {icache_physical_refill_address[(32-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
-    end
-    default:
-    begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = i_adr_o[addr_offset_msb:addr_offset_lsb+1] == {addr_offset_width-1{1'b1}} ? 3'b111 : 3'b010;
-assign last_word = (&i_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
-assign first_address = {icache_physical_refill_address[(32-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
-    end
-    endcase
-endgenerate
-
-/////////////////////////////////////////////////////
-// Sequential Logic
-/////////////////////////////////////////////////////
-
-// PC
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        pc_f <= (eba_reset-4)/4;
-        pc_d <= {(32-2){1'b0}};
-        pc_x <= {(32-2){1'b0}};
-        pc_m <= {(32-2){1'b0}};
-        pc_w <= {(32-2){1'b0}};
-    end
-    else
-    begin
-        if (stall_f == 1'b0)
-            pc_f <= pc_a;
-        if (stall_d == 1'b0)
-            pc_d <= pc_f;
-        if (stall_x == 1'b0)
-            pc_x <= pc_d;
-        if (stall_m == 1'b0)
-            pc_m <= pc_x;
-        pc_w <= pc_m;
-    end
-end
-
-// Address to restart from after a cache miss has been handled
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-        restart_address <= {(32-2){1'b0}};
-    else
-    begin
-            // D-cache restart address must take priority, otherwise instructions will be lost
-            if (dcache_refill_request == 1'b1)
-                restart_address <= pc_w;
-            else if ((icache_refill_request == 1'b1) && (!dcache_refilling) && (!dcache_restart_request))
-                restart_address <= icache_refill_address;
-    end
-end
-
-// Record where instruction was fetched from
-
-
-// Instruction Wishbone interface
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        i_cyc_o <= 1'b0;
-        i_stb_o <= 1'b0;
-        i_adr_o <= {32{1'b0}};
-        i_cti_o <= 3'b111;
-        i_lock_o <= 1'b0;
-        icache_refill_data <= {32{1'b0}};
-        icache_refill_ready <= 1'b0;
-        bus_error_f <= 1'b0;
-    end
-    else
-    begin
-        icache_refill_ready <= 1'b0;
-        // Is a cycle in progress?
-        if (i_cyc_o == 1'b1)
-        begin
-            // Has cycle completed?
-            if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
-            begin
-                begin
-                    if (last_word == 1'b1)
-                    begin
-                        // Cache line fill complete
-                        i_cyc_o <= 1'b0;
-                        i_stb_o <= 1'b0;
-                        i_lock_o <= 1'b0;
-                    end
-                    // Fetch next word in cache line
-                    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
-                    i_cti_o <= next_cycle_type;
-                    // Write fetched data into instruction cache
-                    icache_refill_ready <= 1'b1;
-                    icache_refill_data <= i_dat_i;
-                end
-            end
-            if (i_err_i == 1'b1)
-            begin
-                bus_error_f <= 1'b1;
-                $display ("Instruction bus error. Address: %x", i_adr_o);
-            end
-        end
-        else
-        begin
-            if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
-            begin
-                // Read first word of cache line
-                i_adr_o <= {first_address, 2'b00};
-                i_cyc_o <= 1'b1;
-                i_stb_o <= 1'b1;
-                i_cti_o <= first_cycle_type;
-                //i_lock_o <= `TRUE;
-                bus_error_f <= 1'b0;
-            end
-            // Clear bus error when exception taken, otherwise they would be
-            // continually generated if exception handler is cached
-            if (branch_taken_m == 1'b1)
-                bus_error_f <= 1'b0;
-        end
-    end
-end
-
-// Instruction register
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        instruction_d <= {32{1'b0}};
-        bus_error_d <= 1'b0;
-    end
-    else
-    begin
-        if (stall_d == 1'b0)
-        begin
-            instruction_d <= instruction_f;
-            bus_error_d <= bus_error_f;
-        end
-    end
-end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_interrupt.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_interrupt.v
deleted file mode 100644
index be45b70..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_interrupt.v
+++ /dev/null
@@ -1,467 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_interrupt.v
-// Title            : Interrupt logic
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_interrupt (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    // From external devices
-    interrupt,
-    // From pipeline
-    stall_x,
-    non_debug_exception,
-    debug_exception,
-    eret_q_x,
-    bret_q_x,
-    csr,
-    csr_write_data,
-    csr_write_enable,
-    // ----- Outputs -------
-    interrupt_exception,
-    // To pipeline
-    csr_read_data
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter interrupts = 32;         // Number of interrupts
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                    // Clock
-input rst_i;                                    // Reset
-
-input [interrupts-1:0] interrupt;               // Interrupt pins
-
-input stall_x;                                  // Stall X pipeline stage
-
-input non_debug_exception;                      // Non-debug related exception has been raised
-input debug_exception;                          // Debug-related exception has been raised
-input eret_q_x;                                 // Return from exception
-input bret_q_x;                                 // Return from breakpoint
-
-input [(5-1):0] csr;                      // CSR read/write index
-input [(32-1):0] csr_write_data;          // Data to write to specified CSR
-input csr_write_enable;                         // CSR write enable
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output interrupt_exception;                     // Request to raide an interrupt exception
-wire   interrupt_exception;
-
-output [(32-1):0] csr_read_data;          // Data read from CSR
-reg    [(32-1):0] csr_read_data;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
-//pragma attribute asserted preserve_signal true
-wire [interrupts-1:0] interrupt_n_exception;
-
-// Interrupt CSRs
-
-reg ie;                                         // Interrupt enable
-reg eie;                                        // Exception interrupt enable
-reg bie;                                        // Breakpoint interrupt enable
-reg [interrupts-1:0] ip;                        // Interrupt pending
-reg [interrupts-1:0] im;                        // Interrupt mask
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-// Determine which interrupts have occured and are unmasked
-assign interrupt_n_exception = ip & im;
-
-// Determine if any unmasked interrupts have occured
-assign interrupt_exception = (|interrupt_n_exception) & ie;
-
-// Determine which interrupts are currently being asserted or are already pending
-assign asserted = ip | interrupt;
-
-assign ie_csr_read_data = {{32-3{1'b0}},
-                           bie,
-                           eie,
-                           ie
-                          };
-assign ip_csr_read_data = ip;
-assign im_csr_read_data = im;
-generate
-    if (interrupts > 1)
-    begin
-// CSR read
-always @(*)
-begin
-    case (csr)
-    5'h1d,
-    5'h0:  csr_read_data = {{32-3{1'b0}},
-                                    bie,
-                                    eie,
-                                    ie
-                                   };
-    5'h2:  csr_read_data = ip;
-    5'h1:  csr_read_data = im;
-    default:       csr_read_data = {32{1'bx}};
-    endcase
-end
-    end
-    else
-    begin
-// CSR read
-always @(*)
-begin
-    case (csr)
-    5'h0:  csr_read_data = {{32-3{1'b0}},
-                                    bie,
-                                    eie,
-                                    ie
-                                   };
-    5'h2:  csr_read_data = ip;
-    default:       csr_read_data = {32{1'bx}};
-    endcase
-end
-    end
-endgenerate
-
-/////////////////////////////////////////////////////
-// Sequential Logic
-/////////////////////////////////////////////////////
-
-generate
-    if (interrupts > 1)
-    begin
-// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        ie <= 1'b0;
-        eie <= 1'b0;
-        bie <= 1'b0;
-        im <= {interrupts{1'b0}};
-        ip <= {interrupts{1'b0}};
-    end
-    else
-    begin
-        // Set IP bit when interrupt line is asserted
-        ip <= asserted;
-        if (non_debug_exception == 1'b1)
-        begin
-            // Save and then clear interrupt enable
-            eie <= ie;
-            ie <= 1'b0;
-        end
-        else if (debug_exception == 1'b1)
-        begin
-            // Save and then clear interrupt enable
-            bie <= ie;
-            ie <= 1'b0;
-        end
-        else if (stall_x == 1'b0)
-        begin
-            if (eret_q_x == 1'b1)
-                // Restore interrupt enable
-                ie <= eie;
-            else if (bret_q_x == 1'b1)
-                // Restore interrupt enable
-                ie <= bie;
-            else if (csr_write_enable == 1'b1)
-            begin
-                // Handle wcsr write
-                if (   (csr == 5'h0)
-                    || (csr == 5'h1d)
-                   )
-                begin
-                    ie <= csr_write_data[0];
-                    eie <= csr_write_data[1];
-                    bie <= csr_write_data[2];
-                end
-                if (csr == 5'h1)
-                    im <= csr_write_data[interrupts-1:0];
-                if (csr == 5'h2)
-                    ip <= asserted & ~csr_write_data[interrupts-1:0];
-            end
-        end
-    end
-end
-    end
-else
-    begin
-// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        ie <= 1'b0;
-        eie <= 1'b0;
-        bie <= 1'b0;
-        ip <= {interrupts{1'b0}};
-    end
-    else
-    begin
-        // Set IP bit when interrupt line is asserted
-        ip <= asserted;
-        if (non_debug_exception == 1'b1)
-        begin
-            // Save and then clear interrupt enable
-            eie <= ie;
-            ie <= 1'b0;
-        end
-        else if (debug_exception == 1'b1)
-        begin
-            // Save and then clear interrupt enable
-            bie <= ie;
-            ie <= 1'b0;
-        end
-        else if (stall_x == 1'b0)
-        begin
-            if (eret_q_x == 1'b1)
-                // Restore interrupt enable
-                ie <= eie;
-            else if (bret_q_x == 1'b1)
-                // Restore interrupt enable
-                ie <= bie;
-            else if (csr_write_enable == 1'b1)
-            begin
-                // Handle wcsr write
-                if (   (csr == 5'h0)
-                    || (csr == 5'h1d)
-                   )
-                begin
-                    ie <= csr_write_data[0];
-                    eie <= csr_write_data[1];
-                    bie <= csr_write_data[2];
-                end
-                if (csr == 5'h2)
-                    ip <= asserted & ~csr_write_data[interrupts-1:0];
-            end
-        end
-    end
-end
-    end
-endgenerate
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_itlb.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_itlb.v
deleted file mode 100644
index 0c897fd..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_itlb.v
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * LatticeMico32
- * Instruction Translation Lookaside Buffer
- *
- * Copyright (c) 2011-2012 Yann Sionneau <yann.sionneau@gmail.com>
- * Copyright (c) 2012 Michael Walle <michael@walle.cc>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-
-
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-module lm32_itlb (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    enable,
-    stall_a,
-    stall_f,
-    stall_d,
-    stall_x,
-    pc_a,
-    pc_f,
-    pc_x,
-    read_enable_f,
-    tlbpaddr,
-    tlbvaddr,
-    update,
-    flush,
-    invalidate,
-    // ----- Outputs -------
-    physical_pc_f,
-    stall_request,
-    miss_vfn,
-    miss_f,
-    miss_x
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter entries = 1024;               // Number of entires in ITLB
-parameter page_size = 4096;             // ITLB page size
-
-localparam offset_width = ($clog2-2);
-localparam index_width = $clog2;
-localparam offset_lsb = 2;
-localparam offset_msb = (offset_lsb+offset_width-1);
-localparam index_lsb = (offset_msb+1);
-localparam index_msb = (index_lsb+index_width-1);
-localparam tag_lsb = (index_msb+1);
-localparam tag_msb = (32-1);
-localparam tag_width = (tag_msb-tag_lsb+1);
-localparam vpfn_lsb = (offset_msb+1);
-localparam vpfn_msb = (32-1);
-localparam vpfn_width = (vpfn_msb-vpfn_lsb+1);
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                            // Clock
-input rst_i;                            // Reset
-
-input enable;                           // Instruction TLB enable
-input stall_a;                          // Stall instruction in A stage
-input stall_f;                          // Stall instruction in F stage
-input stall_d;                          // Stall instruction in D stage
-input stall_x;                          // Stall instruction in X stage
-
-input [((32-2)+2-1):2] pc_a;              // Address of instruction in A stage
-input [((32-2)+2-1):2] pc_f;              // Address of instruction in F stage
-input [((32-2)+2-1):2] pc_x;              // Address of instruction in X stage
-
-input read_enable_f;                    // Indicates if cache access is valid
-
-input [(32-1):0] tlbpaddr;
-input [(32-1):0] tlbvaddr;
-input update;
-input flush;
-input invalidate;
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-output [((32-2)+2-1):2] physical_pc_f;
-reg    [((32-2)+2-1):2] physical_pc_f;
-output stall_request;
-wire   stall_request;
-output [(32-1):0] miss_vfn;
-wire   [(32-1):0] miss_vfn;
-output miss_f;
-wire   miss_f;
-output miss_x;
-reg    miss_x;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-wire [(index_width-1):0] read_address;
-wire [(index_width-1):0] write_address;
-wire read_port_enable;
-wire write_port_enable;
-wire [((vpfn_width+tag_width+1)-1):0] write_data;
-reg [1:0] state;
-reg [(index_width-1):0] flush_set;
-
-wire [tag_msb:tag_lsb] tlbe_tag_f;
-wire [vpfn_msb:vpfn_lsb] tlbe_pfn_f;
-wire tlbe_valid_f;
-
-reg miss_d;
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-lm32_ram
-  #(
-    // ----- Parameters -------
-    .data_width ((vpfn_width+tag_width+1)),
-    .address_width (index_width)
-// Modified for Milkymist: removed non-portable RAM parameters
-    ) data_ram
-    (
-     // ----- Inputs -------
-     .read_clk (clk_i),
-     .write_clk (clk_i),
-     .reset (rst_i),
-     .read_address (read_address),
-     .enable_read (read_port_enable),
-     .write_address (write_address),
-     .enable_write (1'b1),
-     .write_enable (write_port_enable),
-     .write_data (write_data),
-     // ----- Outputs -------
-     .read_data ({tlbe_pfn_f, tlbe_tag_f, tlbe_valid_f})
-     );
-
-/////////////////////////////////////////////////////
-// Combinational logic
-/////////////////////////////////////////////////////
-
-// Compute address to use to index into the ITLB memory
-assign read_address = pc_a[index_msb:index_lsb];
-assign write_address = (flushing == 1'b1) ? flush_set : tlbvaddr[index_msb:index_lsb];
-
-assign read_port_enable = (stall_a == 1'b0);
-assign write_port_enable = (update == 1'b1) || (invalidate == 1'b1) || (flushing == 1'b1);
-
-assign write_data = ((invalidate == 1'b1) || (flushing == 1'b1))
-             ? {{(vpfn_width+tag_width+1)-1{1'b0}}, 1'b0}
-             : {tlbpaddr[vpfn_msb:vpfn_lsb], tlbvaddr[tag_msb:tag_lsb], 1'b1};
-
-assign tlbe_match_f = ({tlbe_tag_f, tlbe_valid_f} == {pc_f[tag_msb:tag_lsb], 1'b1});
-
-assign miss_vfn = {pc_x[vpfn_msb:vpfn_lsb], {offset_width{1'b0}}, 2'b0};
-assign miss_f = (enable == 1'b1) && (tlbe_match_f == 1'b0) && (stall_f == 1'b0);
-
-assign flushing = state[1];
-assign stall_request = (flushing == 1'b1);
-
-always @(*)
-begin
-    if (enable == 1'b1)
-    begin
-        if (tlbe_match_f == 1'b1)
-            physical_pc_f = {tlbe_pfn_f, pc_f[offset_msb:offset_lsb]};
-        else
-            physical_pc_f = {(32-2){1'b0}};
-    end
-    else
-        physical_pc_f = pc_f;
-end
-
-/////////////////////////////////////////////////////
-// Sequential logic
-/////////////////////////////////////////////////////
-
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        miss_d <= 1'b0;
-        miss_x <= 1'b0;
-    end
-    else
-    begin
-        if (stall_d == 1'b0)
-            miss_d <= miss_f;
-        if (stall_x == 1'b0)
-            miss_x <= miss_d;
-    end
-end
-
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        flush_set <= {index_width{1'b1}};
-        state <= 2'b10;
-    end
-    else
-    begin
-        case (state)
-
-        2'b01:
-        begin
-            if (flush == 1'b1)
-            begin
-                flush_set <= {index_width{1'b1}};
-                state <= 2'b10;
-            end
-        end
-
-        2'b10:
-        begin
-            if (flush_set == {index_width{1'b0}})
-                state <= 2'b01;
-            flush_set <= flush_set - 1'b1;
-        end
-
-        endcase
-    end
-end
-
-endmodule
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_jtag.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_jtag.v
deleted file mode 100644
index fb7e34d..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_jtag.v
+++ /dev/null
@@ -1,213 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_jtag.v
-// Title            : JTAG interface
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_load_store_unit.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_load_store_unit.v
deleted file mode 100644
index 67c9209..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_load_store_unit.v
+++ /dev/null
@@ -1,775 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project      : LatticeMico32
-// File         : lm32_load_store_unit.v
-// Title        : Load and store unit
-// Dependencies : lm32_include.v
-// Version      : 6.1.17
-//              : Initial Release
-// Version      : 7.0SP2, 3.0
-//              : No Change
-// Version      : 3.1
-//              : Instead of disallowing an instruction cache miss on a data cache
-//              : miss, both can now occur at the same time. If both occur at same
-//              : time, then restart address is the address of instruction that
-//              : caused data cache miss.
-// Version      : 3.2
-//              : EBRs use SYNC resets instead of ASYNC resets.
-// Version      : 3.3
-//              : Support for new non-cacheable Data Memory that is accessible by
-//              : the data port and has a one cycle access latency.
-// Version      : 3.4
-//              : No change
-// Version      : 3.5
-//              : Bug fix: Inline memory is correctly generated if it is not a
-//              : power-of-two
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_load_store_unit (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    // From pipeline
-    stall_a,
-    stall_x,
-    stall_m,
-    kill_m,
-    exception_m,
-    store_operand_x,
-    load_store_address_x,
-    load_store_address_m,
-    load_store_address_w,
-    load_d,
-    store_d,
-    load_x,
-    store_x,
-    load_q_x,
-    store_q_x,
-    load_q_m,
-    store_q_m,
-    sign_extend_x,
-    size_x,
-    dflush,
-    dtlb_enable,
-    tlbpaddr,
-    tlbvaddr,
-    dtlb_update,
-    dtlb_flush,
-    dtlb_invalidate,
-    // From Wishbone
-    d_dat_i,
-    d_ack_i,
-    d_err_i,
-    d_rty_i,
-    // ----- Outputs -------
-    // To pipeline
-    dcache_refill_request,
-    dcache_restart_request,
-    dcache_stall_request,
-    dcache_refilling,
-    load_data_w,
-    stall_wb_load,
-    dtlb_stall_request,
-    dtlb_miss_vfn,
-    dtlb_miss_x,
-    dtlb_fault_x,
-    // To Wishbone
-    d_dat_o,
-    d_adr_o,
-    d_cyc_o,
-    d_sel_o,
-    d_stb_o,
-    d_we_o,
-    d_cti_o,
-    d_lock_o,
-    d_bte_o
-    );
-
-/////////////////////////////////////////////////////
-// Parameters
-/////////////////////////////////////////////////////
-
-parameter associativity = 1;                            // Associativity of the cache (Number of ways)
-parameter sets = 512;                                   // Number of sets
-parameter bytes_per_line = 16;                          // Number of bytes per cache line
-parameter base_address = 0;                             // Base address of cachable memory
-parameter limit = 0;                                    // Limit (highest address) of cachable memory
-
-// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
-localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2-2;
-localparam addr_offset_lsb = 2;
-localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                            // Clock
-input rst_i;                                            // Reset
-
-input stall_a;                                          // A stage stall
-input stall_x;                                          // X stage stall
-input stall_m;                                          // M stage stall
-input kill_m;                                           // Kill instruction in M stage
-input exception_m;                                      // An exception occured in the M stage
-
-input [(32-1):0] store_operand_x;                 // Data read from register to store
-input [(32-1):0] load_store_address_x;            // X stage load/store address
-input [(32-1):0] load_store_address_m;            // M stage load/store address
-input [1:0] load_store_address_w;                       // W stage load/store address (only least two significant bits are needed)
-input load_d;                                           // Load instruction in D stage
-input store_d;                                          // Store instruction in D stage
-input load_x;                                           // Load instruction in X stage
-input store_x;                                          // Store instruction in X stage
-input load_q_x;                                         // Load instruction in X stage
-input store_q_x;                                        // Store instruction in X stage
-input load_q_m;                                         // Load instruction in M stage
-input store_q_m;                                        // Store instruction in M stage
-input sign_extend_x;                                    // Whether load instruction in X stage should sign extend or zero extend
-input [1:0] size_x;                          // Size of load or store (byte, hword, word)
-
-input dflush;                                           // Flush the data cache
-
-
-input dtlb_enable;                                      // Data TLB enable
-input [(32-1):0] tlbpaddr;                        // TLBPADDR CSR
-input [(32-1):0] tlbvaddr;                        // TLBVADDR CSR
-input dtlb_update;                                      // Data TLB update
-input dtlb_flush;                                       // Data TLB flush
-input dtlb_invalidate;                                  // Data TLB invalidate
-
-input [(32-1):0] d_dat_i;                         // Data Wishbone interface read data
-input d_ack_i;                                          // Data Wishbone interface acknowledgement
-input d_err_i;                                          // Data Wishbone interface error
-input d_rty_i;                                          // Data Wishbone interface retry
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output dcache_refill_request;                           // Request to refill data cache
-wire   dcache_refill_request;
-output dcache_restart_request;                          // Request to restart the instruction that caused a data cache miss
-wire   dcache_restart_request;
-output dcache_stall_request;                            // Data cache stall request
-wire   dcache_stall_request;
-output dcache_refilling;
-wire   dcache_refilling;
-
-
-output [(32-1):0] load_data_w;                    // Result of a load instruction
-reg    [(32-1):0] load_data_w;
-output stall_wb_load;                                   // Request to stall pipeline due to a load from the Wishbone interface
-reg    stall_wb_load;
-
-output dtlb_stall_request;                              // Data TLB stall request
-wire   dtlb_stall_request;
-output [(32-1):0] dtlb_miss_vfn;                  // Virtual frame number of missed load or store address
-wire   [(32-1):0] dtlb_miss_vfn;
-output dtlb_miss_x;                                     // Indicates if a data TLB miss has occured
-wire   dtlb_miss_x;
-output dtlb_fault_x;                                    // Indicates if a data TLB fault has occured in X stage
-wire   dtlb_fault_x;
-
-output [(32-1):0] d_dat_o;                        // Data Wishbone interface write data
-reg    [(32-1):0] d_dat_o;
-output [(32-1):0] d_adr_o;                        // Data Wishbone interface address
-reg    [(32-1):0] d_adr_o;
-output d_cyc_o;                                         // Data Wishbone interface cycle
-reg    d_cyc_o;
-output [(4-1):0] d_sel_o;                 // Data Wishbone interface byte select
-reg    [(4-1):0] d_sel_o;
-output d_stb_o;                                         // Data Wishbone interface strobe
-reg    d_stb_o;
-output d_we_o;                                          // Data Wishbone interface write enable
-reg    d_we_o;
-output [(3-1):0] d_cti_o;                       // Data Wishbone interface cycle type
-reg    [(3-1):0] d_cti_o;
-output d_lock_o;                                        // Date Wishbone interface lock bus
-reg    d_lock_o;
-output [(2-1):0] d_bte_o;                       // Data Wishbone interface burst type
-wire   [(2-1):0] d_bte_o;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-// Microcode pipeline registers - See inputs for description
-reg [1:0] size_m;
-reg [1:0] size_w;
-reg sign_extend_m;
-reg sign_extend_w;
-reg [(32-1):0] store_data_x;
-reg [(32-1):0] store_data_m;
-reg [(4-1):0] byte_enable_x;
-reg [(4-1):0] byte_enable_m;
-wire [(32-1):0] data_m;
-reg [(32-1):0] data_w;
-
-wire dcache_select_x;                                   // Select data cache to load from / store to
-reg dcache_select_m;
-wire [(32-1):0] dcache_data_m;                    // Data read from cache
-wire [(32-1):0] dcache_refill_address;            // Address to refill data cache from
-reg dcache_refill_ready;                                // Indicates the next word of refill data is ready
-wire [(3-1):0] first_cycle_type;                // First Wishbone cycle type
-wire [(3-1):0] next_cycle_type;                 // Next Wishbone cycle type
-wire last_word;                                         // Indicates if this is the last word in the cache line
-wire [(32-1):0] first_address;                    // First cache refill address
-wire wb_select_x;                                       // Select Wishbone to load from / store to
-reg wb_select_m;
-reg [(32-1):0] wb_data_m;                         // Data read from Wishbone
-reg wb_load_complete;                                   // Indicates when a Wishbone load is complete
-wire [(32-1):0] physical_load_store_address_m;    // X stage physical load/store address
-wire cache_inhibit_x;                                   // Indicates if data cache should be bypassed
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-
-// Data cache
-lm32_dcache #(
-    .associativity          (associativity),
-    .sets                   (sets),
-    .bytes_per_line         (bytes_per_line),
-    .base_address           (base_address),
-    .limit                  (limit)
-    ) dcache (
-    // ----- Inputs -----
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    .stall_a                (stall_a),
-    .stall_x                (stall_x),
-    .stall_m                (stall_m),
-    .address_x              (load_store_address_x),
-    /* VIPT cache, address_m is (only) used for tag */
-    .address_m              (physical_load_store_address_m),
-    .load_q_m               (load_q_m & dcache_select_m),
-    .store_q_m              (store_q_m & dcache_select_m),
-    .store_data             (store_data_m),
-    .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
-    .refill_ready           (dcache_refill_ready),
-    .refill_data            (wb_data_m),
-    .dflush                 (dflush),
-    .dtlb_miss_x            (dtlb_miss_x),
-    // ----- Outputs -----
-    .stall_request          (dcache_stall_request),
-    .restart_request        (dcache_restart_request),
-    .refill_request         (dcache_refill_request),
-    .refill_address         (dcache_refill_address),
-    .refilling              (dcache_refilling),
-    .load_data              (dcache_data_m)
-    );
-
-// Data TLB
-lm32_dtlb dtlb (
-    // ----- Inputs -----
-    .clk_i                  (clk_i),
-    .rst_i                  (rst_i),
-    .enable                 (dtlb_enable),
-    .stall_x                (stall_x),
-    .stall_m                (stall_m),
-    .address_x              (load_store_address_x),
-    .address_m              (load_store_address_m),
-    .load_d                 (load_d),
-    .store_d                (store_d),
-    .load_q_x               (load_q_x),
-    .store_q_x              (store_q_x),
-    .tlbpaddr               (tlbpaddr),
-    .tlbvaddr               (tlbvaddr),
-    .update                 (dtlb_update),
-    .flush                  (dtlb_flush),
-    .invalidate             (dtlb_invalidate),
-    // ----- Outputs -----
-    .physical_load_store_address_m (physical_load_store_address_m),
-    .stall_request          (dtlb_stall_request),
-    .miss_vfn               (dtlb_miss_vfn),
-    .miss_x                 (dtlb_miss_x),
-    .fault_x                (dtlb_fault_x),
-    .cache_inhibit_x        (cache_inhibit_x)
-    );
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-// Select where data should be loaded from / stored to
-
-
-   assign dcache_select_x =    (load_store_address_x >= 32'h0)
-                            && (load_store_address_x <= 32'h7fffffff)
-                            && (cache_inhibit_x == 1'b0)
-                     ;
-
-   assign wb_select_x =    1'b1
-                        && !dcache_select_x
-                     ;
-
-// Make sure data to store is in correct byte lane
-always @(*)
-begin
-    case (size_x)
-    2'b00:  store_data_x = {4{store_operand_x[7:0]}};
-    2'b11: store_data_x = {2{store_operand_x[15:0]}};
-    2'b10:  store_data_x = store_operand_x;
-    default:          store_data_x = {32{1'bx}};
-    endcase
-end
-
-// Generate byte enable accoring to size of load or store and address being accessed
-always @(*)
-begin
-    casez ({size_x, load_store_address_x[1:0]})
-    {2'b00, 2'b11}:  byte_enable_x = 4'b0001;
-    {2'b00, 2'b10}:  byte_enable_x = 4'b0010;
-    {2'b00, 2'b01}:  byte_enable_x = 4'b0100;
-    {2'b00, 2'b00}:  byte_enable_x = 4'b1000;
-    {2'b11, 2'b1?}: byte_enable_x = 4'b0011;
-    {2'b11, 2'b0?}: byte_enable_x = 4'b1100;
-    {2'b10, 2'b??}:  byte_enable_x = 4'b1111;
-    default:                   byte_enable_x = 4'bxxxx;
-    endcase
-end
-
-
-
-
-      // WB + DC
-   assign data_m = wb_select_m == 1'b1
-                   ? wb_data_m
-                   : dcache_data_m;
-   
-// Sub-word selection and sign/zero-extension for loads
-always @(*)
-begin
-    casez ({size_w, load_store_address_w[1:0]})
-    {2'b00, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
-    {2'b00, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
-    {2'b00, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
-    {2'b00, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
-    {2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
-    {2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
-    {2'b10, 2'b??}:  load_data_w = data_w;
-    default:                   load_data_w = {32{1'bx}};
-    endcase
-end
-
-// Unused/constant Wishbone signals
-assign d_bte_o = 2'b00;
-
-// Generate signal to indicate last word in cache line
-generate
-    case (bytes_per_line)
-    4:
-    begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
-assign first_address = {dcache_refill_address[32-1:2], 2'b00};
-    end
-    8:
-    begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
-assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
-assign first_address = {dcache_refill_address[32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
-    end
-    default:
-    begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = d_adr_o[addr_offset_msb:addr_offset_lsb+1] == {addr_offset_width-1{1'b1}} ? 3'b111 : 3'b010;
-assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
-assign first_address = {dcache_refill_address[32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
-    end
-    endcase
-endgenerate
-
-/////////////////////////////////////////////////////
-// Sequential Logic
-/////////////////////////////////////////////////////
-
-// Data Wishbone interface
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        d_cyc_o <= 1'b0;
-        d_stb_o <= 1'b0;
-        d_dat_o <= {32{1'b0}};
-        d_adr_o <= {32{1'b0}};
-        d_sel_o <= {4{1'b0}};
-        d_we_o <= 1'b0;
-        d_cti_o <= 3'b111;
-        d_lock_o <= 1'b0;
-        wb_data_m <= {32{1'b0}};
-        wb_load_complete <= 1'b0;
-        stall_wb_load <= 1'b0;
-        dcache_refill_ready <= 1'b0;
-    end
-    else
-    begin
-        // Refill ready should only be asserted for a single cycle
-        dcache_refill_ready <= 1'b0;
-        // Is a Wishbone cycle already in progress?
-        if (d_cyc_o == 1'b1)
-        begin
-            // Is the cycle complete?
-            if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
-            begin
-                if ((dcache_refilling == 1'b1) && (!last_word))
-                begin
-                    // Fetch next word of cache line
-                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
-                end
-                else
-                begin
-                    // Refill/access complete
-                    d_cyc_o <= 1'b0;
-                    d_stb_o <= 1'b0;
-                    d_lock_o <= 1'b0;
-                end
-                d_cti_o <= next_cycle_type;
-                // If we are performing a refill, indicate to cache next word of data is ready
-                dcache_refill_ready <= dcache_refilling;
-                // Register data read from Wishbone interface
-                wb_data_m <= d_dat_i;
-                // Don't set when stores complete - otherwise we'll deadlock if load in m stage
-                wb_load_complete <= !d_we_o;
-            end
-            // synthesis translate_off
-            if (d_err_i == 1'b1)
-                $display ("Data bus error. Address: %x", d_adr_o);
-            // synthesis translate_on
-        end
-        else
-        begin
-            if (dcache_refill_request == 1'b1)
-            begin
-                // Start cache refill
-                d_adr_o <= first_address;
-                d_cyc_o <= 1'b1;
-                d_sel_o <= {32/8{1'b1}};
-                d_stb_o <= 1'b1;
-                d_we_o <= 1'b0;
-                d_cti_o <= first_cycle_type;
-                //d_lock_o <= `TRUE;
-            end
-            else
-                 if (   (store_q_m == 1'b1)
-                     && (stall_m == 1'b0)
-                    )
-            begin
-                // Data cache is write through, so all stores go to memory
-                d_dat_o <= store_data_m;
-                d_adr_o <=
-                    (dtlb_enable) ? physical_load_store_address_m :
-                    load_store_address_m;
-                d_cyc_o <= 1'b1;
-                d_sel_o <= byte_enable_m;
-                d_stb_o <= 1'b1;
-                d_we_o <= 1'b1;
-                d_cti_o <= 3'b111;
-            end
-            else if (   (load_q_m == 1'b1)
-                     && (wb_select_m == 1'b1)
-                     && (wb_load_complete == 1'b0)
-                     // stall_m will be TRUE, because stall_wb_load will be TRUE
-                    )
-            begin
-                // Read requested address
-                stall_wb_load <= 1'b0;
-                d_adr_o <=
-                    (dtlb_enable) ? physical_load_store_address_m :
-                    load_store_address_m;
-                d_cyc_o <= 1'b1;
-                d_sel_o <= byte_enable_m;
-                d_stb_o <= 1'b1;
-                d_we_o <= 1'b0;
-                d_cti_o <= 3'b111;
-            end
-        end
-        // Clear load/store complete flag when instruction leaves M stage
-        if (stall_m == 1'b0)
-            wb_load_complete <= 1'b0;
-        // When a Wishbone load first enters the M stage, we need to stall it
-        if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
-            stall_wb_load <= 1'b1;
-        // Clear stall request if load instruction is killed
-        if ((kill_m == 1'b1) || (exception_m == 1'b1))
-            stall_wb_load <= 1'b0;
-    end
-end
-
-// Pipeline registers
-
-// X/M stage pipeline registers
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        sign_extend_m <= 1'b0;
-        size_m <= 2'b00;
-        byte_enable_m <= 1'b0;
-        store_data_m <= {32{1'b0}};
-        dcache_select_m <= 1'b0;
-        wb_select_m <= 1'b0;
-    end
-    else
-    begin
-        if (stall_m == 1'b0)
-        begin
-            sign_extend_m <= sign_extend_x;
-            size_m <= size_x;
-            byte_enable_m <= byte_enable_x;
-            store_data_m <= store_data_x;
-            dcache_select_m <= dcache_select_x;
-            wb_select_m <= wb_select_x;
-        end
-    end
-end
-
-// M/W stage pipeline registers
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        size_w <= 2'b00;
-        data_w <= {32{1'b0}};
-        sign_extend_w <= 1'b0;
-    end
-    else
-    begin
-        size_w <= size_m;
-        data_w <= data_m;
-        sign_extend_w <= sign_extend_m;
-    end
-end
-
-/////////////////////////////////////////////////////
-// Behavioural Logic
-/////////////////////////////////////////////////////
-
-// synthesis translate_off
-
-// Check for non-aligned loads or stores
-always @(posedge clk_i)
-begin
-    if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
-    begin
-        if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
-            $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
-        if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
-            $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
-    end
-end
-
-// synthesis translate_on
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_logic_op.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_logic_op.v
deleted file mode 100644
index a06b2da..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_logic_op.v
+++ /dev/null
@@ -1,259 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_logic_op.v
-// Title            : Logic operations (and / or / not etc)
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_logic_op (
-    // ----- Inputs -------
-    logic_op_x,
-    operand_0_x,
-    operand_1_x,
-    // ----- Outputs -------
-    logic_result_x
-    );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input [3:0] logic_op_x;
-input [(32-1):0] operand_0_x;
-input [(32-1):0] operand_1_x;
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [(32-1):0] logic_result_x;
-reg    [(32-1):0] logic_result_x;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-integer logic_idx;
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-always @(*)
-begin
-    for(logic_idx = 0; logic_idx < 32; logic_idx = logic_idx + 1)
-        logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
-end
-
-endmodule
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_mc_arithmetic.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_mc_arithmetic.v
deleted file mode 100644
index e894a82..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_mc_arithmetic.v
+++ /dev/null
@@ -1,364 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm_mc_arithmetic.v
-// Title            : Multi-cycle arithmetic unit.
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_mc_arithmetic (
-    // ----- Inputs -----
-    clk_i,
-    rst_i,
-    stall_d,
-    kill_x,
-    divide_d,
-    modulus_d,
-    operand_0_d,
-    operand_1_d,
-    // ----- Ouputs -----
-    result_x,
-    divide_by_zero_x,
-    stall_request_x
-    );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                    // Clock
-input rst_i;                                    // Reset
-input stall_d;                                  // Stall instruction in D stage
-input kill_x;                                   // Kill instruction in X stage
-input divide_d;                                 // Perform divide
-input modulus_d;                                // Perform modulus
-input [(32-1):0] operand_0_d;
-input [(32-1):0] operand_1_d;
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [(32-1):0] result_x;               // Result of operation
-reg    [(32-1):0] result_x;
-output divide_by_zero_x;                        // A divide by zero was attempted
-reg    divide_by_zero_x;
-output stall_request_x;                         // Request to stall pipeline from X stage back
-wire   stall_request_x;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-reg [(32-1):0] p;                         // Temporary registers
-reg [(32-1):0] a;
-reg [(32-1):0] b;
-wire [32:0] t;
-
-reg [2:0] state;                 // Current state of FSM
-reg [5:0] cycles;                               // Number of cycles remaining in the operation
-
-
-/////////////////////////////////////////////////////
-// Combinational logic
-/////////////////////////////////////////////////////
-
-// Stall pipeline while any operation is being performed
-assign stall_request_x = state != 3'b000;
-
-// Subtraction
-assign t = {p[32-2:0], a[32-1]} - b;
-
-
-/////////////////////////////////////////////////////
-// Sequential logic
-/////////////////////////////////////////////////////
-
-// Perform right shift
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        cycles <= {6{1'b0}};
-        p <= {32{1'b0}};
-        a <= {32{1'b0}};
-        b <= {32{1'b0}};
-        divide_by_zero_x <= 1'b0;
-        result_x <= {32{1'b0}};
-        state <= 3'b000;
-    end
-    else
-    begin
-        divide_by_zero_x <= 1'b0;
-        case (state)
-        3'b000:
-        begin
-            if (stall_d == 1'b0)
-            begin
-                cycles <= 32;
-                p <= 32'b0;
-                a <= operand_0_d;
-                b <= operand_1_d;
-                if (divide_d == 1'b1)
-                    state <= 3'b011;
-                if (modulus_d == 1'b1)
-                    state <= 3'b010;
-            end
-        end
-        3'b011:
-        begin
-            if (t[32] == 1'b0)
-            begin
-                p <= t[31:0];
-                a <= {a[32-2:0], 1'b1};
-            end
-            else
-            begin
-                p <= {p[32-2:0], a[32-1]};
-                a <= {a[32-2:0], 1'b0};
-            end
-            result_x <= a;
-            if ((cycles == 32'd0) || (kill_x == 1'b1))
-            begin
-                // Check for divide by zero
-                divide_by_zero_x <= b == {32{1'b0}};
-                state <= 3'b000;
-            end
-            cycles <= cycles - 1'b1;
-        end
-        3'b010:
-        begin
-            if (t[32] == 1'b0)
-            begin
-                p <= t[31:0];
-                a <= {a[32-2:0], 1'b1};
-            end
-            else
-            begin
-                p <= {p[32-2:0], a[32-1]};
-                a <= {a[32-2:0], 1'b0};
-            end
-            result_x <= p;
-            if ((cycles == 32'd0) || (kill_x == 1'b1))
-            begin
-                // Check for divide by zero
-                divide_by_zero_x <= b == {32{1'b0}};
-                state <= 3'b000;
-            end
-            cycles <= cycles - 1'b1;
-        end
-        endcase
-    end
-end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_multiplier.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_multiplier.v
deleted file mode 100644
index 0866030..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_multiplier.v
+++ /dev/null
@@ -1,282 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_multiplier.v
-// Title            : Pipelined multiplier.
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_multiplier (
-    // ----- Inputs -----
-    clk_i,
-    rst_i,
-    stall_x,
-    stall_m,
-    operand_0,
-    operand_1,
-    // ----- Ouputs -----
-    result
-    );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                            // Clock
-input rst_i;                            // Reset
-input stall_x;                          // Stall instruction in X stage
-input stall_m;                          // Stall instruction in M stage
-input [(32-1):0] operand_0;       // Muliplicand
-input [(32-1):0] operand_1;       // Multiplier
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [(32-1):0] result;         // Product of multiplication
-reg    [(32-1):0] result;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-reg [(32-1):0] muliplicand;
-reg [(32-1):0] multiplier;
-reg [(32-1):0] product;
-
-/////////////////////////////////////////////////////
-// Sequential logic
-/////////////////////////////////////////////////////
-
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        muliplicand <= {32{1'b0}};
-        multiplier <= {32{1'b0}};
-        product <= {32{1'b0}};
-        result <= {32{1'b0}};
-    end
-    else
-    begin
-        if (stall_x == 1'b0)
-        begin
-            muliplicand <= operand_0;
-            multiplier <= operand_1;
-        end
-        if (stall_m == 1'b0)
-            product <= muliplicand * multiplier;
-        result <= product;
-    end
-end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_ram.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_ram.v
deleted file mode 100644
index de661a3..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_ram.v
+++ /dev/null
@@ -1,300 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_ram.v
-// Title            : Pseudo dual-port RAM.
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : Options added to select EBRs (True-DP, Psuedo-DP, DQ, or
-//                  : Distributed RAM).
-// Version          : 3.2
-//                  : EBRs use SYNC resets instead of ASYNC resets.
-// Version          : 3.5
-//                  : Added read-after-write hazard resolution when using true
-//                  : dual-port EBRs
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_ram (
-    // ----- Inputs -------
-    read_clk,
-    write_clk,
-    reset,
-    enable_read,
-    read_address,
-    enable_write,
-    write_address,
-    write_data,
-    write_enable,
-    // ----- Outputs -------
-    read_data
-    );
-
-/*----------------------------------------------------------------------
- Parameters
- ----------------------------------------------------------------------*/
-parameter data_width = 1;               // Width of the data ports
-parameter address_width = 1;            // Width of the address ports
-parameter init_file = "NONE";           // Initialization file
-
-/*----------------------------------------------------------------------
- Inputs
- ----------------------------------------------------------------------*/
-input read_clk;                         // Read clock
-input write_clk;                        // Write clock
-input reset;                            // Reset
-
-input enable_read;                      // Access enable
-input [address_width-1:0] read_address; // Read/write address
-input enable_write;                     // Access enable
-input [address_width-1:0] write_address;// Read/write address
-input [data_width-1:0] write_data;      // Data to write to specified address
-input write_enable;                     // Write enable
-
-/*----------------------------------------------------------------------
- Outputs
- ----------------------------------------------------------------------*/
-output [data_width-1:0] read_data;      // Data read from specified addess
-wire   [data_width-1:0] read_data;
-
-/*----------------------------------------------------------------------
- Internal nets and registers
- ----------------------------------------------------------------------*/
-reg [data_width-1:0]    mem[0:(1<<address_width)-1]; // The RAM
-reg [address_width-1:0] ra; // Registered read address
-
-/*----------------------------------------------------------------------
- Combinational Logic
- ----------------------------------------------------------------------*/
-// Read port
-assign read_data = mem[ra];
-
-/*----------------------------------------------------------------------
- Sequential Logic
- ----------------------------------------------------------------------*/
-// Write port
-always @(posedge write_clk)
-    if ((write_enable == 1'b1) && (enable_write == 1'b1))
-        mem[write_address] <= write_data;
-
-// Register read address for use on next cycle
-always @(posedge read_clk)
-    if (enable_read)
-        ra <= read_address;
-
-/*----------------------------------------------------------------------
- Initialization
- ----------------------------------------------------------------------*/
-generate
-	if (init_file != "NONE")
-	begin
-initial $readmemh(init_file, mem);
-	end
-endgenerate
-	
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_shifter.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_shifter.v
deleted file mode 100644
index 90ea751..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_shifter.v
+++ /dev/null
@@ -1,317 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_shifter.v
-// Title            : Barrel shifter
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_shifter (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    stall_x,
-    direction_x,
-    sign_extend_x,
-    operand_0_x,
-    operand_1_x,
-    // ----- Outputs -------
-    shifter_result_m
-    );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                // Clock
-input rst_i;                                // Reset
-input stall_x;                              // Stall instruction in X stage
-input direction_x;                          // Direction to shift
-input sign_extend_x;                        // Whether shift is arithmetic (1'b1) or logical (1'b0)
-input [(32-1):0] operand_0_x;         // Operand to shift
-input [(32-1):0] operand_1_x;         // Operand that specifies how many bits to shift by
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [(32-1):0] shifter_result_m;   // Result of shift
-wire   [(32-1):0] shifter_result_m;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-reg direction_m;
-reg [(32-1):0] left_shift_result;
-reg [(32-1):0] right_shift_result;
-reg [(32-1):0] left_shift_operand;
-wire [(32-1):0] right_shift_operand;
-wire fill_value;
-wire [(32-1):0] right_shift_in;
-
-integer shift_idx_0;
-integer shift_idx_1;
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-// Select operands - To perform a left shift, we reverse the bits and perform a right shift
-always @(*)
-begin
-    for (shift_idx_0 = 0; shift_idx_0 < 32; shift_idx_0 = shift_idx_0 + 1)
-        left_shift_operand[32-1-shift_idx_0] = operand_0_x[shift_idx_0];
-end
-assign right_shift_operand = direction_x == 1'b1 ? left_shift_operand : operand_0_x;
-
-// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
-assign fill_value = (sign_extend_x == 1'b1) && (direction_x == 1'b0)
-                      ? operand_0_x[32-1]
-                      : 1'b0;
-
-// Determine bits to shift in for right shift or rotate
-assign right_shift_in = {32{fill_value}};
-
-// Reverse bits to get left shift result
-always @(*)
-begin
-    for (shift_idx_1 = 0; shift_idx_1 < 32; shift_idx_1 = shift_idx_1 + 1)
-        left_shift_result[32-1-shift_idx_1] = right_shift_result[shift_idx_1];
-end
-
-// Select result
-assign shifter_result_m = direction_m == 1'b1 ? left_shift_result : right_shift_result;
-
-/////////////////////////////////////////////////////
-// Sequential Logic
-/////////////////////////////////////////////////////
-
-// Perform right shift
-always @(posedge clk_i )
-begin
-    if (rst_i == 1'b1)
-    begin
-        right_shift_result <= {32{1'b0}};
-        direction_m <= 1'b0;
-    end
-    else
-    begin
-        if (stall_x == 1'b0)
-        begin
-            right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[(5-1):0];
-            direction_m <= direction_x;
-        end
-    end
-end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_top.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_top.v
deleted file mode 100644
index 4f6c942..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/rtl/lm32_top.v
+++ /dev/null
@@ -1,383 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_top.v
-// Title            : Top-level of CPU.
-// Dependencies     : lm32_include.v
-// Version          : 6.1.17
-//                  : removed SPI - 04/12/07
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// =============================================================================
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_top (
-    // ----- Inputs -------
-    clk_i,
-    rst_i,
-    // From external devices
-    interrupt,
-    // From user logic
-    // Instruction Wishbone master
-    I_DAT_I,
-    I_ACK_I,
-    I_ERR_I,
-    I_RTY_I,
-    ext_break,
-    // Data Wishbone master
-    D_DAT_I,
-    D_ACK_I,
-    D_ERR_I,
-    D_RTY_I,
-    // ----- Outputs -------
-    // Instruction Wishbone master
-    I_DAT_O,
-    I_ADR_O,
-    I_CYC_O,
-    I_SEL_O,
-    I_STB_O,
-    I_WE_O,
-    I_CTI_O,
-    I_LOCK_O,
-    I_BTE_O,
-    // Data Wishbone master
-    D_DAT_O,
-    D_ADR_O,
-    D_CYC_O,
-    D_SEL_O,
-    D_STB_O,
-    D_WE_O,
-    D_CTI_O,
-    D_LOCK_O,
-    D_BTE_O
-    );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i;                                    // Clock
-input rst_i;                                    // Reset
-
-
-input [(32-1):0] interrupt;          // Interrupt pins
-
-
-input [(32-1):0] I_DAT_I;                 // Instruction Wishbone interface read data
-input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
-input I_ERR_I;                                  // Instruction Wishbone interface error
-input I_RTY_I;                                  // Instruction Wishbone interface retry
-
-input [(32-1):0] D_DAT_I;                 // Data Wishbone interface read data
-input D_ACK_I;                                  // Data Wishbone interface acknowledgement
-input D_ERR_I;                                  // Data Wishbone interface error
-input D_RTY_I;                                  // Data Wishbone interface retry
-
-input ext_break;
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-
-output [(32-1):0] I_DAT_O;                // Instruction Wishbone interface write data
-wire   [(32-1):0] I_DAT_O;
-output [(32-1):0] I_ADR_O;                // Instruction Wishbone interface address
-wire   [(32-1):0] I_ADR_O;
-output I_CYC_O;                                 // Instruction Wishbone interface cycle
-wire   I_CYC_O;
-output [(4-1):0] I_SEL_O;         // Instruction Wishbone interface byte select
-wire   [(4-1):0] I_SEL_O;
-output I_STB_O;                                 // Instruction Wishbone interface strobe
-wire   I_STB_O;
-output I_WE_O;                                  // Instruction Wishbone interface write enable
-wire   I_WE_O;
-output [(3-1):0] I_CTI_O;               // Instruction Wishbone interface cycle type
-wire   [(3-1):0] I_CTI_O;
-output I_LOCK_O;                                // Instruction Wishbone interface lock bus
-wire   I_LOCK_O;
-output [(2-1):0] I_BTE_O;               // Instruction Wishbone interface burst type
-wire   [(2-1):0] I_BTE_O;
-
-output [(32-1):0] D_DAT_O;                // Data Wishbone interface write data
-wire   [(32-1):0] D_DAT_O;
-output [(32-1):0] D_ADR_O;                // Data Wishbone interface address
-wire   [(32-1):0] D_ADR_O;
-output D_CYC_O;                                 // Data Wishbone interface cycle
-wire   D_CYC_O;
-output [(4-1):0] D_SEL_O;         // Data Wishbone interface byte select
-wire   [(4-1):0] D_SEL_O;
-output D_STB_O;                                 // Data Wishbone interface strobe
-wire   D_STB_O;
-output D_WE_O;                                  // Data Wishbone interface write enable
-wire   D_WE_O;
-output [(3-1):0] D_CTI_O;               // Data Wishbone interface cycle type
-wire   [(3-1):0] D_CTI_O;
-output D_LOCK_O;                                // Date Wishbone interface lock bus
-wire   D_LOCK_O;
-output [(2-1):0] D_BTE_O;               // Data Wishbone interface burst type
-wire   [(2-1):0] D_BTE_O;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-
-// TODO: get the trace signals out
-
-/////////////////////////////////////////////////////
-// Functions
-/////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-// LM32 CPU
-lm32_cpu cpu (
-    // ----- Inputs -------
-    .clk_i                 (clk_i),
-    .rst_i                 (rst_i),
-    // From external devices
-    .interrupt             (interrupt),
-    // From user logic
-    .ext_break             (ext_break),
-     // Instruction Wishbone master
-    .I_DAT_I               (I_DAT_I),
-    .I_ACK_I               (I_ACK_I),
-    .I_ERR_I               (I_ERR_I),
-    .I_RTY_I               (I_RTY_I),
-    // Data Wishbone master
-    .D_DAT_I               (D_DAT_I),
-    .D_ACK_I               (D_ACK_I),
-    .D_ERR_I               (D_ERR_I),
-    .D_RTY_I               (D_RTY_I),
-    // ----- Outputs -------
-    // Instruction Wishbone master
-    .I_DAT_O               (I_DAT_O),
-    .I_ADR_O               (I_ADR_O),
-    .I_CYC_O               (I_CYC_O),
-    .I_SEL_O               (I_SEL_O),
-    .I_STB_O               (I_STB_O),
-    .I_WE_O                (I_WE_O),
-    .I_CTI_O               (I_CTI_O),
-    .I_LOCK_O              (I_LOCK_O),
-    .I_BTE_O               (I_BTE_O),
-        // Data Wishbone master
-    .D_DAT_O               (D_DAT_O),
-    .D_ADR_O               (D_ADR_O),
-    .D_CYC_O               (D_CYC_O),
-    .D_SEL_O               (D_SEL_O),
-    .D_STB_O               (D_STB_O),
-    .D_WE_O                (D_WE_O),
-    .D_CTI_O               (D_CTI_O),
-    .D_LOCK_O              (D_LOCK_O),
-    .D_BTE_O               (D_BTE_O)
-    );
-
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/sim/tb_lm32_system.v b/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/sim/tb_lm32_system.v
deleted file mode 100644
index 3b97286..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/lm32/slpp_unit/work/sim/tb_lm32_system.v
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * LatticeMico32
- * System Test Bench
- *
- * Copyright (c) 2012 Michael Walle <michael@walle.cc>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-
-//
-// Common configuration options
-//
-
-
-
-
-
-
-// Enable Debugging
-//`define CFG_JTAG_ENABLED
-//`define CFG_JTAG_UART_ENABLED
-//`define CFG_HW_DEBUG_ENABLED
-
-// Enable MMU
-
-
-
-//
-// End of common configuration options
-//
-
-
-// Wishbone configuration
-
-// Data-path width
-
-// Register file size
-
-// Standard register numbers
-
-// Range of Program Counter. Two LSBs are always 0.
-
-// Range of an instruction
-
-// Adder operation
-
-// Shift direction
-
-// Bus errors
-
-// Derive macro that indicates whether we have single-stepping or not
-
-// Derive macro that indicates whether JTAG interface is required
-
-// Derive macro that indicates whether ROM debug is required
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-
-// Derive macro that indicates whether we have a multiplier or not
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-
-// Derive macro that indicates if we are using an EBR register file
-
-// Revision number
-
-// Logical operations - Function encoded directly in instruction
-
-// Conditions for conditional branches
-
-// Size of load or store instruction - Encoding corresponds to opcode
-
-// Width and range of a CSR index
-
-// CSR indices
-
-// Values for WPC CSR
-
-// TLB operation codes
-
-// Exception IDs
-
-// Exception Base Address
-
-// Pipeline result selection mux controls
-
-
-
-
-// Derive a macro to indicate if either of the caches are implemented
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-
-// Currently this is fixed to 32 and should not be changed
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-
-// Word sub-byte indicies
-
-// Word sub-halfword indices
-
-// Use a synchronous reset
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-
-// Wishbone burst types
-
-`timescale 1 ns / 1 ps
-
-module testbench();
-
-integer i;
-
-reg sys_rst;
-reg sys_clk;
-reg [31:0] interrupt;
-
-reg i_ack;
-wire [31:0] i_adr;
-wire i_cyc;
-wire [31:0] i_dat;
-wire i_stb;
-
-reg d_ack;
-wire [31:0] d_adr;
-wire d_cyc;
-wire [31:0] d_dat_i;
-wire [31:0] d_dat_o;
-wire [3:0] d_sel;
-wire d_stb;
-
-lm32_top lm32(
-	.clk_i(sys_clk),
-	.rst_i(sys_rst),
-
-	.interrupt(interrupt),
-	.ext_break(1'b0),
-
-	.I_ACK_I(i_ack),
-	.I_ADR_O(i_adr),
-	.I_BTE_O(),
-	.I_CTI_O(),
-	.I_CYC_O(i_cyc),
-	.I_DAT_I(i_dat),
-	.I_DAT_O(),
-	.I_ERR_I(1'b0),
-	.I_LOCK_O(),
-	.I_RTY_I(1'b0),
-	.I_SEL_O(),
-	.I_STB_O(i_stb),
-	.I_WE_O(),
-
-	.D_ACK_I(d_ack),
-	.D_ADR_O(d_adr),
-	.D_BTE_O(),
-	.D_CTI_O(),
-	.D_CYC_O(d_cyc),
-	.D_DAT_I(d_dat_i),
-	.D_DAT_O(d_dat_o),
-	.D_ERR_I(1'b0),
-	.D_LOCK_O(),
-	.D_RTY_I(1'b0),
-	.D_SEL_O(d_sel),
-	.D_STB_O(d_stb),
-	.D_WE_O(d_we)
-);
-
-// clock
-initial sys_clk = 1'b0;
-always #50 sys_clk = ~sys_clk;
-
-// reset
-initial begin
-	sys_rst = 1'b0;
-	repeat (500) @(posedge sys_clk);
-	sys_rst = 1'b1;
-	repeat (500) @(posedge sys_clk);
-	sys_rst = 1'b0;
-end
-
-// memory
-reg [7:0] mem[0:65535];
-initial begin
-	for(i=0;i<65536;i=i+1)
-		mem[i] = 8'b0;
-end
-
-// memory monitor bitmap
-reg mem_monitor_prog_rd[0:'h4000];
-reg mem_monitor_data_rd[0:'h4000];
-reg mem_monitor_data_wr[0:'h4000];
-initial begin
-	for(i=0;i<'h4000;i=i+1) begin
-		// print prog read (until icache is hot) and non-stack data writes
-		mem_monitor_prog_rd[i] = 1;
-		mem_monitor_data_rd[i] = 0;
-		mem_monitor_data_wr[i] = i < 'h3000;
-	end
-end
-
-wire [31:0] dmem_dat_i;
-reg [31:0] dmem_dat_o;
-wire [13:0] dmem_adr;
-wire [3:0] dmem_we;
-always @(posedge sys_clk) begin
-	if(dmem_we[0]) mem[{dmem_adr, 2'b11}] <= dmem_dat_i[7:0];
-	if(dmem_we[1]) mem[{dmem_adr, 2'b10}] <= dmem_dat_i[15:8];
-	if(dmem_we[2]) mem[{dmem_adr, 2'b01}] <= dmem_dat_i[23:16];
-	if(dmem_we[3]) mem[{dmem_adr, 2'b00}] <= dmem_dat_i[31:24];
-	dmem_dat_o[7:0]   <= mem[{dmem_adr, 2'b11}];
-	dmem_dat_o[15:8]  <= mem[{dmem_adr, 2'b10}];
-	dmem_dat_o[23:16] <= mem[{dmem_adr, 2'b01}];
-	dmem_dat_o[31:24] <= mem[{dmem_adr, 2'b00}];
-
-	if (dmem_we) begin
-		if (mem_monitor_data_wr[dmem_adr] && !d_ack)
-			$display("DATA WR: @%08x %02x%02x%02x%02x (%b)", {dmem_adr, 2'b00},
-					dmem_we[3] ? dmem_dat_i[31:24] : 8'bz,
-					dmem_we[2] ? dmem_dat_i[23:16] : 8'bz,
-					dmem_we[1] ? dmem_dat_i[15: 8] : 8'bz,
-					dmem_we[0] ? dmem_dat_i[ 7: 0] : 8'bz, dmem_we);
-	end else if (d_cyc) begin
-		if (mem_monitor_data_rd[dmem_adr] && !d_ack)
-			$display("DATA RD: @%08x %02x%02x%02x%02x", {dmem_adr, 2'b00}, 
-					mem[{dmem_adr, 2'b00}], mem[{dmem_adr, 2'b01}],
-					mem[{dmem_adr, 2'b10}], mem[{dmem_adr, 2'b11}]);
-	end
-end
-reg [31:0] pmem_dat_o;
-wire [13:0] pmem_adr;
-always @(posedge sys_clk) begin
-	pmem_dat_o[7:0]   <= mem[{pmem_adr, 2'b11}];
-	pmem_dat_o[15:8]  <= mem[{pmem_adr, 2'b10}];
-	pmem_dat_o[23:16] <= mem[{pmem_adr, 2'b01}];
-	pmem_dat_o[31:24] <= mem[{pmem_adr, 2'b00}];
-
-	if (i_cyc && !i_ack && mem_monitor_prog_rd[pmem_adr])
-		$display("PROG RD: @%08x %02x%02x%02x%02x", {pmem_adr, 2'b00}, 
-				mem[{pmem_adr, 2'b00}], mem[{pmem_adr, 2'b01}],
-				mem[{pmem_adr, 2'b10}], mem[{pmem_adr, 2'b11}]);
-end
-
-// uart
-always @(posedge sys_clk) begin
-	if(d_cyc & d_stb & d_we & d_ack) begin
-		if(d_adr == 32'hff000000)
-			$write("%c", d_dat_o[7:0]);
-		if(d_adr == 32'hff000004)
-			$display("OUT: %d", d_dat_o);
-	end
-end
-
-// wishbone interface for instruction bus
-always @(posedge sys_clk) begin
-	if(sys_rst)
-		i_ack <= 1'b0;
-	else begin
-		i_ack <= 1'b0;
-		if(i_cyc & i_stb & ~i_ack)
-			i_ack <= 1'b1;
-	end
-end
-
-integer clock_counter = 0;
-always @(posedge sys_clk) begin
-	clock_counter = clock_counter + 1;
-	if (clock_counter == 1000) begin
-		$display("-- 1000 sys_clk cycles --");
-		clock_counter = 0;
-	end
-end
-
-assign i_dat = pmem_dat_o;
-assign pmem_adr = i_adr[15:2];
-
-
-// wishbone interface for data bus
-always @(posedge sys_clk) begin
-	if(sys_rst)
-		d_ack <= 1'b0;
-	else begin
-		d_ack <= 1'b0;
-		if(d_cyc & d_stb & ~d_ack)
-			d_ack <= 1'b1;
-	end
-end
-
-assign d_dat_i = dmem_dat_o;
-assign dmem_dat_i = d_dat_o;
-assign dmem_adr = d_adr[15:2];
-assign dmem_we = {4{d_cyc & d_stb & d_we & ~|d_adr[31:16]}} & d_sel;
-
-// interrupts
-initial interrupt <= 32'b0;
-
-// simulation end request
-always @(posedge sys_clk) begin
-	if(d_cyc & d_stb & d_we & d_ack)
-		if(d_adr == 32'hdead0000 && d_dat_o == 32'hbeef)
-			$finish;
-end
-
-// traces
-
-
-// dump signals
-reg [256*8:0] vcdfile;
-initial begin
-	if($value$plusargs("dump=%s", vcdfile)) begin
-		$dumpfile(vcdfile);
-		$dumpvars(0, testbench);
-	end
-end
-
-// init memory
-reg [256*8:0] prog;
-initial begin
-	if(! $value$plusargs("prog=%s", prog)) begin
-		// $display("ERROR: please specify +prog=<file>.vh to start.");
-		// $finish;
-		prog = "lm32/sim/sieve.vh";
-	end
-end
-
-initial $readmemh(prog, mem);
-
-// trace pipeline
-
-initial begin
-	// $dumpfile("bench.vcd");
-	// @(posedge sys_rst);
-	// repeat (5) @(posedge sys_clk);
-	// $dumpvars(0, testbench);
-	// repeat (2500) @(posedge sys_clk);
-	// $finish;
-end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/surelog.log b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/surelog.log
deleted file mode 100644
index d11cdac..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/surelog.log
+++ /dev/null
@@ -1,235 +0,0 @@
-********************************************
-*  SURELOG System Verilog Compiler/Linter  *
-********************************************
-
-Copyright (c) 2017-2019 ACE Cloud,
-Authorized used only.
-
-VERSION: 0.05
-BUILT  : Nov  3 2019
-DATE   : 2019-11-03.21:39:57
-COMMAND: -writepp -parse -mt max -nopython -fileunit rtl/omsp_alu.v rtl/omsp_and_gate.v rtl/omsp_clock_gate.v rtl/omsp_clock_module.v rtl/omsp_clock_mux.v rtl/omsp_dbg.v rtl/omsp_dbg_hwbrk.v rtl/omsp_dbg_i2c.v rtl/omsp_dbg_uart.v rtl/omsp_execution_unit.v rtl/omsp_frontend.v rtl/omsp_mem_backbone.v rtl/omsp_multiplier.v rtl/omsp_register_file.v rtl/omsp_scan_mux.v rtl/omsp_sfr.v rtl/omsp_sync_cell.v rtl/omsp_sync_reset.v rtl/omsp_wakeup_cell.v rtl/omsp_watchdog.v rtl/openMSP430.v rtl/openMSP430_defines.v rtl/openMSP430_undefines.v sim/bench.v sim/sieve.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
-
-[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
-
-[INFO :CM0024] Executing with 4 threads.
-
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[WARNI:PP0103] ./rtl/openMSP430_undefines.v:249 Undefining an unknown macro "PMEM_CUSTOM_AWIDTH".
-
-[WARNI:PP0103] ./rtl/openMSP430_undefines.v:250 Undefining an unknown macro "PMEM_CUSTOM_SIZE".
-
-[WARNI:PP0103] ./rtl/openMSP430_undefines.v:251 Undefining an unknown macro "DMEM_CUSTOM_AWIDTH".
-
-[WARNI:PP0103] ./rtl/openMSP430_undefines.v:252 Undefining an unknown macro "DMEM_CUSTOM_SIZE".
-
-[WARNI:PP0103] ./rtl/openMSP430_undefines.v:253 Undefining an unknown macro "PER_CUSTOM_AWIDTH".
-
-[WARNI:PP0103] ./rtl/openMSP430_undefines.v:254 Undefining an unknown macro "PER_CUSTOM_SIZE".
-
-[ERROR:PP0102] ./rtl/openMSP430_defines.v:626 Unknown macro "PER_SIZE".
-
-[ERROR:PP0102] ./rtl/openMSP430_defines.v:629 Unknown macro "PMEM_AWIDTH".
-
-[ERROR:PP0102] ./rtl/openMSP430_defines.v:630 Unknown macro "DMEM_AWIDTH".
-
-[ERROR:PP0102] ./rtl/openMSP430_defines.v:631 Unknown macro "PER_AWIDTH".
-
-[ERROR:PP0102] ./rtl/openMSP430_defines.v:813 Unknown macro "DBG_DCO_FREQ".
-
-[ERROR:PP0102] ./rtl/openMSP430_defines.v:813 Unknown macro "DBG_UART_BAUD".
-
-[WARNI:PP0103] rtl/openMSP430_undefines.v:249 Undefining an unknown macro "PMEM_CUSTOM_AWIDTH".
-
-[WARNI:PP0103] rtl/openMSP430_undefines.v:250 Undefining an unknown macro "PMEM_CUSTOM_SIZE".
-
-[WARNI:PP0103] rtl/openMSP430_undefines.v:251 Undefining an unknown macro "DMEM_CUSTOM_AWIDTH".
-
-[WARNI:PP0103] rtl/openMSP430_undefines.v:252 Undefining an unknown macro "DMEM_CUSTOM_SIZE".
-
-[WARNI:PP0103] rtl/openMSP430_undefines.v:253 Undefining an unknown macro "PER_CUSTOM_AWIDTH".
-
-[WARNI:PP0103] rtl/openMSP430_undefines.v:254 Undefining an unknown macro "PER_CUSTOM_SIZE".
-
-[ERROR:PA0207] sim/sieve.v:1 Syntax error: missing {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier} at '[',
-pmem[ 512] = 16'h4031;
-    ^-- ./slpp_unit/work/sim/sieve.v:1 col:4.
-
-[WARNI:PA0205] rtl/omsp_and_gate.v:44 No timescale set for "omsp_and_gate".
-
-[WARNI:PA0205] rtl/omsp_clock_gate.v:44 No timescale set for "omsp_clock_gate".
-
-[WARNI:PA0205] rtl/omsp_clock_mux.v:44 No timescale set for "omsp_clock_mux".
-
-[WARNI:PA0205] rtl/omsp_dbg_hwbrk.v:46 No timescale set for "omsp_dbg_hwbrk".
-
-[WARNI:PA0205] rtl/omsp_clock_module.v:46 No timescale set for "omsp_clock_module".
-
-[WARNI:PA0205] rtl/omsp_alu.v:46 No timescale set for "omsp_alu".
-
-[WARNI:PA0205] rtl/omsp_dbg.v:46 No timescale set for "omsp_dbg".
-
-[WARNI:PA0205] rtl/omsp_execution_unit.v:46 No timescale set for "omsp_execution_unit".
-
-[WARNI:PA0205] rtl/omsp_dbg_uart.v:46 No timescale set for "omsp_dbg_uart".
-
-[WARNI:PA0205] rtl/omsp_register_file.v:46 No timescale set for "omsp_register_file".
-
-[WARNI:PA0205] rtl/openMSP430.v:46 No timescale set for "openMSP430".
-
-[WARNI:PA0205] rtl/omsp_dbg_i2c.v:46 No timescale set for "omsp_dbg_i2c".
-
-[WARNI:PA0205] rtl/omsp_mem_backbone.v:46 No timescale set for "omsp_mem_backbone".
-
-[WARNI:PA0205] rtl/omsp_sync_reset.v:44 No timescale set for "omsp_sync_reset".
-
-[WARNI:PA0205] rtl/omsp_wakeup_cell.v:46 No timescale set for "omsp_wakeup_cell".
-
-[WARNI:PA0205] rtl/omsp_multiplier.v:46 No timescale set for "omsp_multiplier".
-
-[WARNI:PA0205] rtl/omsp_sync_cell.v:44 No timescale set for "omsp_sync_cell".
-
-[WARNI:PA0205] rtl/omsp_watchdog.v:46 No timescale set for "omsp_watchdog".
-
-[WARNI:PA0205] rtl/omsp_frontend.v:46 No timescale set for "omsp_frontend".
-
-[WARNI:PA0205] rtl/omsp_scan_mux.v:44 No timescale set for "omsp_scan_mux".
-
-[WARNI:PA0205] rtl/omsp_sfr.v:47 No timescale set for "omsp_sfr".
-
-[INFO :CP0300] Compilation...
-
-[INFO :CP0303] rtl/omsp_alu.v:46 Compile module "work@omsp_alu".
-
-[INFO :CP0303] rtl/omsp_clock_gate.v:44 Compile module "work@omsp_clock_gate".
-
-[INFO :CP0303] rtl/omsp_clock_module.v:46 Compile module "work@omsp_clock_module".
-
-[INFO :CP0303] rtl/omsp_and_gate.v:44 Compile module "work@omsp_and_gate".
-
-[INFO :CP0303] rtl/omsp_dbg_hwbrk.v:46 Compile module "work@omsp_dbg_hwbrk".
-
-[INFO :CP0303] rtl/omsp_dbg.v:46 Compile module "work@omsp_dbg".
-
-[INFO :CP0303] rtl/omsp_clock_mux.v:44 Compile module "work@omsp_clock_mux".
-
-[INFO :CP0303] rtl/omsp_frontend.v:46 Compile module "work@omsp_frontend".
-
-[INFO :CP0303] rtl/omsp_dbg_uart.v:46 Compile module "work@omsp_dbg_uart".
-
-[INFO :CP0303] rtl/omsp_dbg_i2c.v:46 Compile module "work@omsp_dbg_i2c".
-
-[INFO :CP0303] rtl/omsp_multiplier.v:46 Compile module "work@omsp_multiplier".
-
-[INFO :CP0303] rtl/omsp_execution_unit.v:46 Compile module "work@omsp_execution_unit".
-
-[INFO :CP0303] rtl/omsp_mem_backbone.v:46 Compile module "work@omsp_mem_backbone".
-
-[INFO :CP0303] rtl/omsp_sync_cell.v:44 Compile module "work@omsp_sync_cell".
-
-[INFO :CP0303] rtl/openMSP430.v:46 Compile module "work@openMSP430".
-
-[INFO :CP0303] rtl/omsp_scan_mux.v:44 Compile module "work@omsp_scan_mux".
-
-[INFO :CP0303] rtl/omsp_sfr.v:47 Compile module "work@omsp_sfr".
-
-[INFO :CP0303] rtl/omsp_wakeup_cell.v:46 Compile module "work@omsp_wakeup_cell".
-
-[INFO :CP0303] rtl/omsp_register_file.v:46 Compile module "work@omsp_register_file".
-
-[INFO :CP0303] rtl/omsp_watchdog.v:46 Compile module "work@omsp_watchdog".
-
-[INFO :CP0303] rtl/omsp_sync_reset.v:44 Compile module "work@omsp_sync_reset".
-
-[INFO :CP0303] sim/bench.v:6 Compile module "work@testbench".
-
-[NOTE :CP0309] rtl/omsp_alu.v:49 Implicit port type (wire) for "alu_out",
-there are 3 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_clock_mux.v:47 Implicit port type (wire) for "clk_out".
-
-[NOTE :CP0309] rtl/omsp_dbg_uart.v:50 Implicit port type (wire) for "dbg_din",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_multiplier.v:49 Implicit port type (wire) for "per_dout".
-
-[NOTE :CP0309] rtl/omsp_sync_cell.v:47 Implicit port type (wire) for "data_out".
-
-[NOTE :CP0309] rtl/openMSP430.v:49 Implicit port type (wire) for "aclk",
-there are 25 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_and_gate.v:47 Implicit port type (wire) for "y".
-
-[NOTE :CP0309] rtl/omsp_dbg.v:49 Implicit port type (wire) for "dbg_cpu_reset",
-there are 9 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_execution_unit.v:49 Implicit port type (wire) for "cpuoff",
-there are 11 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_register_file.v:49 Implicit port type (wire) for "cpuoff",
-there are 9 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_sync_reset.v:47 Implicit port type (wire) for "rst_s".
-
-[NOTE :CP0309] rtl/omsp_clock_gate.v:47 Implicit port type (wire) for "gclk".
-
-[NOTE :CP0309] rtl/omsp_dbg_hwbrk.v:49 Implicit port type (wire) for "brk_halt",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_frontend.v:50 Implicit port type (wire) for "decode_noirq",
-there are 11 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_scan_mux.v:47 Implicit port type (wire) for "data_out".
-
-[NOTE :CP0309] rtl/omsp_clock_module.v:49 Implicit port type (wire) for "aclk",
-there are 14 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_dbg_i2c.v:50 Implicit port type (wire) for "dbg_din".
-
-[NOTE :CP0309] rtl/omsp_mem_backbone.v:49 Implicit port type (wire) for "dbg_mem_din",
-there are 15 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_sfr.v:50 Implicit port type (wire) for "cpu_id",
-there are 5 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_watchdog.v:49 Implicit port type (wire) for "per_dout",
-there are 3 more instances of this message.
-
-[INFO :EL0526] Design Elaboration...
-
-[NOTE :EL0503] rtl/omsp_and_gate.v:44 Top level module "work@omsp_and_gate".
-
-[NOTE :EL0503] rtl/omsp_clock_gate.v:44 Top level module "work@omsp_clock_gate".
-
-[NOTE :EL0503] rtl/omsp_clock_mux.v:44 Top level module "work@omsp_clock_mux".
-
-[NOTE :EL0503] rtl/omsp_dbg_hwbrk.v:46 Top level module "work@omsp_dbg_hwbrk".
-
-[NOTE :EL0503] rtl/omsp_dbg_i2c.v:46 Top level module "work@omsp_dbg_i2c".
-
-[NOTE :EL0503] rtl/omsp_wakeup_cell.v:46 Top level module "work@omsp_wakeup_cell".
-
-[NOTE :EL0503] sim/bench.v:6 Top level module "work@testbench".
-
-[NOTE :EL0503] rtl/omsp_scan_mux.v:44 Top level module "work@omsp_scan_mux".
-
-[NOTE :EL0504] Multiple top level modules in design.
-
-[NOTE :EL0508] Nb Top level modules: 8.
-
-[NOTE :EL0509] Max instance depth: 5.
-
-[NOTE :EL0510] Nb instances: 27.
-
-[NOTE :EL0511] Nb leaf instances: 17.
-
-[  FATAL] : 0
-[  ERROR] : 7
-[WARNING] : 33
-[   NOTE] : 33
-
-********************************************
-*   End SURELOG SVerilog Compiler/Linter   *
-********************************************
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_alu.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_alu.v
deleted file mode 100644
index 99d314b..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_alu.v
+++ /dev/null
@@ -1,1171 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_alu.v
-// 
-// *Module Description:
-//                       openMSP430 ALU
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 134 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_alu (
-
-// OUTPUTs
-    alu_out,                       // ALU output value
-    alu_out_add,                   // ALU adder output value
-    alu_stat,                      // ALU Status {V,N,Z,C}
-    alu_stat_wr,                   // ALU Status write {V,N,Z,C}
-
-// INPUTs
-    dbg_halt_st,                   // Halt/Run status from CPU
-    exec_cycle,                    // Instruction execution cycle
-    inst_alu,                      // ALU control signals
-    inst_bw,                       // Decoded Inst: byte width
-    inst_jmp,                      // Decoded Inst: Conditional jump
-    inst_so,                       // Single-operand arithmetic
-    op_dst,                        // Destination operand
-    op_src,                        // Source operand
-    status                         // R2 Status {V,N,Z,C}
-);
-
-// OUTPUTs
-//=========
-output       [15:0] alu_out;       // ALU output value
-output       [15:0] alu_out_add;   // ALU adder output value
-output        [3:0] alu_stat;      // ALU Status {V,N,Z,C}
-output        [3:0] alu_stat_wr;   // ALU Status write {V,N,Z,C}
-
-// INPUTs
-//=========
-input               dbg_halt_st;   // Halt/Run status from CPU
-input               exec_cycle;    // Instruction execution cycle
-input        [11:0] inst_alu;      // ALU control signals
-input               inst_bw;       // Decoded Inst: byte width
-input         [7:0] inst_jmp;      // Decoded Inst: Conditional jump
-input         [7:0] inst_so;       // Single-operand arithmetic
-input        [15:0] op_dst;        // Destination operand
-input        [15:0] op_src;        // Source operand
-input         [3:0] status;        // R2 Status {V,N,Z,C}
-
-
-//=============================================================================
-// 1)  FUNCTIONS
-//=============================================================================
-
-function [4:0] bcd_add;
-
-   input [3:0] X;
-   input [3:0] Y;
-   input       C_;
-
-   reg   [4:0] Z_;
-   begin
-      Z_ = {1'b0,X}+{1'b0,Y}+{4'b0,C_};
-      if (Z_<5'd10) bcd_add = Z_;
-      else          bcd_add = Z_+5'd6;
-   end
-
-endfunction
-
-
-//=============================================================================
-// 2)  INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE
-//=============================================================================
-// SINGLE-OPERAND ARITHMETIC:
-//-----------------------------------------------------------------------------
-//   Mnemonic   S-Reg,   Operation                               Status bits
-//              D-Reg,                                            V  N  Z  C
-//
-//   RRC         dst     C->MSB->...LSB->C                        *  *  *  *
-//   RRA         dst     MSB->MSB->...LSB->C                      0  *  *  *
-//   SWPB        dst     Swap bytes                               -  -  -  -
-//   SXT         dst     Bit7->Bit8...Bit15                       0  *  *  *
-//   PUSH        src     SP-2->SP, src->@SP                       -  -  -  -
-//   CALL        dst     SP-2->SP, PC+2->@SP, dst->PC             -  -  -  -
-//   RETI                TOS->SR, SP+2->SP, TOS->PC, SP+2->SP     *  *  *  *
-//
-//-----------------------------------------------------------------------------
-// TWO-OPERAND ARITHMETIC:
-//-----------------------------------------------------------------------------
-//   Mnemonic   S-Reg,   Operation                               Status bits
-//              D-Reg,                                            V  N  Z  C
-//
-//   MOV       src,dst    src            -> dst                   -  -  -  -
-//   ADD       src,dst    src +  dst     -> dst                   *  *  *  *
-//   ADDC      src,dst    src +  dst + C -> dst                   *  *  *  *
-//   SUB       src,dst    dst + ~src + 1 -> dst                   *  *  *  *
-//   SUBC      src,dst    dst + ~src + C -> dst                   *  *  *  *
-//   CMP       src,dst    dst + ~src + 1                          *  *  *  *
-//   DADD      src,dst    src +  dst + C -> dst (decimaly)        *  *  *  *
-//   BIT       src,dst    src &  dst                              0  *  *  *
-//   BIC       src,dst   ~src &  dst     -> dst                   -  -  -  -
-//   BIS       src,dst    src |  dst     -> dst                   -  -  -  -
-//   XOR       src,dst    src ^  dst     -> dst                   *  *  *  *
-//   AND       src,dst    src &  dst     -> dst                   0  *  *  *
-//
-//-----------------------------------------------------------------------------
-// * the status bit is affected
-// - the status bit is not affected
-// 0 the status bit is cleared
-// 1 the status bit is set
-//-----------------------------------------------------------------------------
-
-// Invert source for substract and compare instructions.
-wire        op_src_inv_cmd = exec_cycle & (inst_alu[0]);
-wire [15:0] op_src_inv     = {16{op_src_inv_cmd}} ^ op_src;
-
-
-// Mask the bit 8 for the Byte instructions for correct flags generation
-wire        op_bit8_msk     = ~exec_cycle | ~inst_bw;
-wire [16:0] op_src_in       = {1'b0, {op_src_inv[15:8] & {8{op_bit8_msk}}}, op_src_inv[7:0]};
-wire [16:0] op_dst_in       = {1'b0, {op_dst[15:8]     & {8{op_bit8_msk}}}, op_dst[7:0]};
-
-// Clear the source operand (= jump offset) for conditional jumps
-wire        jmp_not_taken  = (inst_jmp[6]  & ~(status[3]^status[2])) |
-                             (inst_jmp[5] &  (status[3]^status[2])) |
-                             (inst_jmp[4]  &  ~status[2])            |
-                             (inst_jmp[3]  &  ~status[0])            |
-                             (inst_jmp[2] &   status[0])            |
-                             (inst_jmp[1] &  ~status[1])            |
-                             (inst_jmp[0] &   status[1]);
-wire [16:0] op_src_in_jmp  = op_src_in & {17{~jmp_not_taken}};
-
-// Adder / AND / OR / XOR
-wire [16:0] alu_add        = op_src_in_jmp + op_dst_in;
-wire [16:0] alu_and        = op_src_in     & op_dst_in;
-wire [16:0] alu_or         = op_src_in     | op_dst_in;
-wire [16:0] alu_xor        = op_src_in     ^ op_dst_in;
-
-
-// Incrementer
-wire        alu_inc         = exec_cycle & ((inst_alu[2] & status[0]) |
-                                             inst_alu[1]);
-wire [16:0] alu_add_inc    = alu_add + {16'h0000, alu_inc};
-
-
-
-// Decimal adder (DADD)
-wire  [4:0] alu_dadd0      = bcd_add(op_src_in[3:0],   op_dst_in[3:0],  status[0]);
-wire  [4:0] alu_dadd1      = bcd_add(op_src_in[7:4],   op_dst_in[7:4],  alu_dadd0[4]);
-wire  [4:0] alu_dadd2      = bcd_add(op_src_in[11:8],  op_dst_in[11:8], alu_dadd1[4]);
-wire  [4:0] alu_dadd3      = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
-wire [16:0] alu_dadd       = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};
-
-
-// Shifter for rotate instructions (RRC & RRA)
-wire        alu_shift_msb  = inst_so[0] ? status[0]     :
-	                     inst_bw       ? op_src[7]     : op_src[15];
-wire        alu_shift_7    = inst_bw       ? alu_shift_msb : op_src[8];
-wire [16:0] alu_shift      = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};
-
-
-// Swap bytes / Extend Sign
-wire [16:0] alu_swpb       = {1'b0, op_src[7:0],op_src[15:8]};
-wire [16:0] alu_sxt        = {1'b0, {8{op_src[7]}},op_src[7:0]};
-
-
-// Combine short paths toghether to simplify final ALU mux
-wire        alu_short_thro = ~(inst_alu[4]   |
-                               inst_alu[5]    |
-                               inst_alu[6]   |
-                               inst_alu[10] |
-                               inst_so[1]       |
-                               inst_so[3]);
-
-wire [16:0] alu_short      = ({17{inst_alu[4]}}   & alu_and)   |
-                             ({17{inst_alu[5]}}    & alu_or)    |
-                             ({17{inst_alu[6]}}   & alu_xor)   |
-                             ({17{inst_alu[10]}} & alu_shift) |
-                             ({17{inst_so[1]}}       & alu_swpb)  |
-                             ({17{inst_so[3]}}        & alu_sxt)   |
-                             ({17{alu_short_thro}}       & op_src_in);
-
-
-// ALU output mux
-wire [16:0] alu_out_nxt    = (inst_so[7] | dbg_halt_st |
-                              inst_alu[3]) ? alu_add_inc :
-                              inst_alu[7] ? alu_dadd    : alu_short;
-
-assign      alu_out        =  alu_out_nxt[15:0];
-assign      alu_out_add    =  alu_add[15:0];
-
-
-//-----------------------------------------------------------------------------
-// STATUS FLAG GENERATION
-//-----------------------------------------------------------------------------
-
-wire    V_xor       = inst_bw ? (op_src_in[7]  & op_dst_in[7])  :
-                                (op_src_in[15] & op_dst_in[15]);
-
-wire    V           = inst_bw ? ((~op_src_in[7]  & ~op_dst_in[7]  &  alu_out[7])  |
-                                 ( op_src_in[7]  &  op_dst_in[7]  & ~alu_out[7])) :
-                                ((~op_src_in[15] & ~op_dst_in[15] &  alu_out[15]) |
-                                 ( op_src_in[15] &  op_dst_in[15] & ~alu_out[15]));
-
-wire    N           = inst_bw ?  alu_out[7]       : alu_out[15];
-wire    Z           = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
-wire    C           = inst_bw ?  alu_out[8]       : alu_out_nxt[16];
-
-assign  alu_stat    = inst_alu[10]  ? {1'b0, N,Z,op_src_in[0]} :
-                      inst_alu[8] ? {1'b0, N,Z,~Z}           :
-                      inst_alu[6]    ? {V_xor,N,Z,~Z}           : {V,N,Z,C};
-
-assign  alu_stat_wr = (inst_alu[9] & exec_cycle) ? 4'b1111 : 4'b0000;
-
-
-endmodule // omsp_alu
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_and_gate.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_and_gate.v
deleted file mode 100644
index 7ceeb8d..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_and_gate.v
+++ /dev/null
@@ -1,89 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_and_gate.v
-// 
-// *Module Description:
-//                       Generic AND gate cell for the openMSP430
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 103 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
-//----------------------------------------------------------------------------
-
-module  omsp_and_gate (
-
-// OUTPUTs
-    y,                         // AND gate output
-
-// INPUTs
-    a,                         // AND gate input A
-    b                          // AND gate input B
-);
-
-// OUTPUTs
-//=========
-output         y;              // AND gate output
-
-// INPUTs
-//=========
-input          a;              // AND gate input A
-input          b;              // AND gate input B
-
-
-//=============================================================================
-// 1)  SOME COMMENTS ON THIS MODULE
-//=============================================================================
-//
-//    In its ASIC version, some combinatorial pathes of the openMSP430 are
-// sensitive to glitches, in particular the ones generating the wakeup
-// signals.
-//    To prevent synthesis from optmizing combinatorial clouds into glitchy
-// logic, this AND gate module has been instanciated in the critical places.
-//
-//    Make sure that synthesis doesn't ungroup this module. As an alternative,
-// a standard cell from the library could also be directly instanciated here
-// (don't forget the "dont_touch" attribute)
-//
-//
-//=============================================================================
-// 2)  AND GATE
-//=============================================================================
-
-assign  y  =  a & b;
-
-
-endmodule // omsp_and_gate
-
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_gate.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_gate.v
deleted file mode 100644
index 8ffe8e0..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_gate.v
+++ /dev/null
@@ -1,86 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_clock_gate.v
-// 
-// *Module Description:
-//                       Generic clock gate cell for the openMSP430
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 103 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
-//----------------------------------------------------------------------------
-
-module  omsp_clock_gate (
-
-// OUTPUTs
-    gclk,                      // Gated clock
-
-// INPUTs
-    clk,                       // Clock
-    enable,                    // Clock enable
-    scan_enable                // Scan enable (active during scan shifting)
-);
-
-// OUTPUTs
-//=========
-output         gclk;           // Gated clock
-
-// INPUTs
-//=========
-input          clk;            // Clock
-input          enable;         // Clock enable
-input          scan_enable;    // Scan enable (active during scan shifting)
-
-
-//=============================================================================
-// CLOCK GATE: LATCH + AND
-//=============================================================================
-   
-// Enable clock gate during scan shift
-// (the gate itself is checked with the scan capture cycle)
-wire    enable_in =   (enable | scan_enable);
-
-// LATCH the enable signal
-reg     enable_latch;
-always @(clk or enable_in)
-  if (~clk)
-    enable_latch <= enable_in;
-
-// AND gate
-assign  gclk      =  (clk & enable_latch);
-
-
-endmodule // omsp_clock_gate
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_module.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_module.v
deleted file mode 100644
index 0d38ba0..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_module.v
+++ /dev/null
@@ -1,1411 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_clock_module.v
-// 
-// *Module Description:
-//                       Basic clock module implementation.
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_clock_module (
-
-// OUTPUTs
-    aclk,                         // ACLK
-    aclk_en,                      // ACLK enable
-    cpu_en_s,                     // Enable CPU code execution (synchronous)
-    dbg_clk,                      // Debug unit clock
-    dbg_en_s,                     // Debug interface enable (synchronous)
-    dbg_rst,                      // Debug unit reset
-    dco_enable,                   // Fast oscillator enable
-    dco_wkup,                     // Fast oscillator wake-up (asynchronous)
-    lfxt_enable,                  // Low frequency oscillator enable
-    lfxt_wkup,                    // Low frequency oscillator wake-up (asynchronous)
-    mclk,                         // Main system clock
-    per_dout,                     // Peripheral data output
-    por,                          // Power-on reset
-    puc_pnd_set,                  // PUC pending set for the serial debug interface
-    puc_rst,                      // Main system reset
-    smclk,                        // SMCLK
-    smclk_en,                     // SMCLK enable
-	     
-// INPUTs
-    cpu_en,                       // Enable CPU code execution (asynchronous)
-    cpuoff,                       // Turns off the CPU
-    dbg_cpu_reset,                // Reset CPU from debug interface
-    dbg_en,                       // Debug interface enable (asynchronous)
-    dco_clk,                      // Fast oscillator (fast clock)
-    lfxt_clk,                     // Low frequency oscillator (typ 32kHz)
-    mclk_enable,                  // Main System Clock enable
-    mclk_wkup,                    // Main System Clock wake-up (asynchronous)
-    oscoff,                       // Turns off LFXT1 clock input
-    per_addr,                     // Peripheral address
-    per_din,                      // Peripheral data input
-    per_en,                       // Peripheral enable (high active)
-    per_we,                       // Peripheral write enable (high active)
-    reset_n,                      // Reset Pin (low active, asynchronous)
-    scan_enable,                  // Scan enable (active during scan shifting)
-    scan_mode,                    // Scan mode
-    scg0,                         // System clock generator 1. Turns off the DCO
-    scg1,                         // System clock generator 1. Turns off the SMCLK
-    wdt_reset                     // Watchdog-timer reset
-);
-
-// OUTPUTs
-//=========
-output              aclk;         // ACLK
-output              aclk_en;      // ACLK enable
-output              cpu_en_s;     // Enable CPU code execution (synchronous)
-output              dbg_clk;      // Debug unit clock
-output              dbg_en_s;     // Debug unit enable (synchronous)
-output              dbg_rst;      // Debug unit reset
-output              dco_enable;   // Fast oscillator enable
-output              dco_wkup;     // Fast oscillator wake-up (asynchronous)
-output              lfxt_enable;  // Low frequency oscillator enable
-output              lfxt_wkup;    // Low frequency oscillator wake-up (asynchronous)
-output              mclk;         // Main system clock
-output       [15:0] per_dout;     // Peripheral data output
-output              por;          // Power-on reset
-output              puc_pnd_set;  // PUC pending set for the serial debug interface
-output              puc_rst;      // Main system reset
-output              smclk;        // SMCLK
-output              smclk_en;     // SMCLK enable
-
-// INPUTs
-//=========
-input               cpu_en;       // Enable CPU code execution (asynchronous)
-input               cpuoff;       // Turns off the CPU
-input               dbg_cpu_reset;// Reset CPU from debug interface
-input               dbg_en;       // Debug interface enable (asynchronous)
-input               dco_clk;      // Fast oscillator (fast clock)
-input               lfxt_clk;     // Low frequency oscillator (typ 32kHz)
-input               mclk_enable;  // Main System Clock enable
-input               mclk_wkup;    // Main System Clock wake-up (asynchronous)
-input               oscoff;       // Turns off LFXT1 clock input
-input        [13:0] per_addr;     // Peripheral address
-input        [15:0] per_din;      // Peripheral data input
-input               per_en;       // Peripheral enable (high active)
-input         [1:0] per_we;       // Peripheral write enable (high active)
-input               reset_n;      // Reset Pin (low active, asynchronous)
-input               scan_enable;  // Scan enable (active during scan shifting)
-input               scan_mode;    // Scan mode
-input               scg0;         // System clock generator 1. Turns off the DCO
-input               scg1;         // System clock generator 1. Turns off the SMCLK
-input               wdt_reset;    // Watchdog-timer reset
-
-
-//=============================================================================
-// 1)  WIRES & PARAMETER DECLARATION
-//=============================================================================
-
-// Register base address (must be aligned to decoder bit width)
-parameter       [14:0] BASE_ADDR   = 15'h0050;
-
-// Decoder bit width (defines how many bits are considered for address decoding)
-parameter              DEC_WD      =  4;
-
-// Register addresses offset
-parameter [DEC_WD-1:0] BCSCTL1     =  'h7,
-                       BCSCTL2     =  'h8;
-
-// Register one-hot decoder utilities
-parameter              DEC_SZ      =  (1 << DEC_WD);
-parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
-
-// Register one-hot decoder
-parameter [DEC_SZ-1:0] BCSCTL1_D   = (BASE_REG << BCSCTL1),
-                       BCSCTL2_D   = (BASE_REG << BCSCTL2);
-
-// Local wire declarations
-wire nodiv_mclk;
-wire nodiv_mclk_n;
-wire nodiv_smclk;
-
-
-//============================================================================
-// 2)  REGISTER DECODER
-//============================================================================
-
-// Local register selection
-wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
-
-// Register local address
-wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};
-
-// Register address decode
-wire [DEC_SZ-1:0] reg_dec      = (BCSCTL1_D  &  {DEC_SZ{(reg_addr==(BCSCTL1 >>1))}}) |
-                                 (BCSCTL2_D  &  {DEC_SZ{(reg_addr==(BCSCTL2 >>1))}});
-
-// Read/Write probes
-wire              reg_lo_write =  per_we[0] & reg_sel;
-wire              reg_hi_write =  per_we[1] & reg_sel;
-wire              reg_read     = ~|per_we   & reg_sel;
-
-// Read/Write vectors
-wire [DEC_SZ-1:0] reg_hi_wr    = reg_dec & {DEC_SZ{reg_hi_write}};
-wire [DEC_SZ-1:0] reg_lo_wr    = reg_dec & {DEC_SZ{reg_lo_write}};
-wire [DEC_SZ-1:0] reg_rd       = reg_dec & {DEC_SZ{reg_read}};
-
-
-//============================================================================
-// 3) REGISTERS
-//============================================================================
-
-// BCSCTL1 Register
-//--------------
-reg  [7:0] bcsctl1;
-wire       bcsctl1_wr  = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
-wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8]      : per_din[7:0];
-
-wire [7:0] divax_mask = 8'h30;
-
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)          bcsctl1  <=  8'h00;
-  else if (bcsctl1_wr)  bcsctl1  <=  bcsctl1_nxt & divax_mask; // Mask unused bits
-
-
-// BCSCTL2 Register
-//--------------
-reg  [7:0] bcsctl2;
-wire       bcsctl2_wr    = BCSCTL2[0] ? reg_hi_wr[BCSCTL2] : reg_lo_wr[BCSCTL2];
-wire [7:0] bcsctl2_nxt   = BCSCTL2[0] ? per_din[15:8]      : per_din[7:0];
-
-wire [7:0] selmx_mask = 8'h00;
-wire [7:0] divmx_mask = 8'h00;
-wire [7:0] sels_mask  = 8'h08;
-wire [7:0] divsx_mask = 8'h06;
-
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)          bcsctl2  <=  8'h00;
-  else if (bcsctl2_wr)  bcsctl2  <=  bcsctl2_nxt & ( sels_mask  | divsx_mask |
-                                                     selmx_mask | divmx_mask); // Mask unused bits
-
-
-//============================================================================
-// 4) DATA OUTPUT GENERATION
-//============================================================================
-
-// Data output mux
-wire [15:0] bcsctl1_rd   = {8'h00, (bcsctl1  & {8{reg_rd[BCSCTL1]}})}  << (8 & {4{BCSCTL1[0]}});
-wire [15:0] bcsctl2_rd   = {8'h00, (bcsctl2  & {8{reg_rd[BCSCTL2]}})}  << (8 & {4{BCSCTL2[0]}});
-
-wire [15:0] per_dout =  bcsctl1_rd   |
-                        bcsctl2_rd;
-
-
-//=============================================================================
-// 5)  DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
-//=============================================================================
-
-
-//-----------------------------------------------------------
-// 5.1) HIGH SPEED SYSTEM CLOCK GENERATOR (DCO_CLK)
-//-----------------------------------------------------------
-// Note1: switching off the DCO osillator is only
-//        supported in ASIC mode with SCG0 low power mode
-//
-// Note2: unlike the original MSP430 specification,
-//        we allow to switch off the DCO even
-//        if it is selected by MCLK or SMCLK.
-
-wire por_a;
-wire dco_wkup;
-wire cpu_en_wkup;
-
-   assign dco_enable    = 1'b1;
-   assign dco_wkup      = 1'b1;
-
-
-//-----------------------------------------------------------
-// 5.2) LOW FREQUENCY CRYSTAL CLOCK GENERATOR (LFXT_CLK)
-//-----------------------------------------------------------
-
-// ASIC MODE
-//------------------------------------------------
-// Note: unlike the original MSP430 specification,
-//       we allow to switch off the LFXT even
-//       if it is selected by MCLK or SMCLK.
-
-wire lfxt_clk_s;
-
-omsp_sync_cell sync_cell_lfxt_clk (
-    .data_out  (lfxt_clk_s),
-    .data_in   (lfxt_clk),
-    .clk       (mclk),
-    .rst       (por)
-);
-
-reg  lfxt_clk_dly;
-   
-always @ (posedge mclk or posedge por)
-  if (por) lfxt_clk_dly <=  1'b0;
-  else     lfxt_clk_dly <=  lfxt_clk_s;    
-
-wire   lfxt_clk_en = (lfxt_clk_s & ~lfxt_clk_dly) & ~(oscoff & ~bcsctl2[3]);
-assign lfxt_enable = 1'b1;
-assign lfxt_wkup   = 1'b0;
-
-   
-//=============================================================================
-// 6)  CLOCK GENERATION
-//=============================================================================
-
-//-----------------------------------------------------------
-// 6.1) GLOBAL CPU ENABLE
-//-----------------------------------------------------------
-// ACLK and SMCLK are directly switched-off
-// with the cpu_en pin (after synchronization).
-// MCLK will be switched off once the CPU reaches
-// its IDLE state (through the mclk_enable signal)
-
-
-// Synchronize CPU_EN signal to the MCLK domain
-//----------------------------------------------
-   assign cpu_en_s    = cpu_en;
-   assign cpu_en_wkup = 1'b0;
-
-// Synchronize CPU_EN signal to the ACLK domain
-//----------------------------------------------
-   wire   cpu_en_aux_s    = cpu_en_s;
-
-// Synchronize CPU_EN signal to the SMCLK domain
-//----------------------------------------------
-// Note: the synchronizer is only required if there is a SMCLK_MUX
-
-
-//-----------------------------------------------------------
-// 6.2) MCLK GENERATION
-//-----------------------------------------------------------
-
-// Clock MUX
-//----------------------------
-assign nodiv_mclk   =  dco_clk;
-assign nodiv_mclk_n = ~nodiv_mclk;
-   
-
-// Wakeup synchronizer
-//----------------------------
-wire mclk_wkup_s;
-
-   assign mclk_wkup_s = 1'b0;
-
-
-// Clock Divider
-//----------------------------
-// No need for extra synchronizer as bcsctl2
-// comes from the same clock domain.
-
-wire mclk_active = 1'b1;
-   
-  wire  mclk_div_en = mclk_active;
-
-
-// Generate main system clock
-//----------------------------
-   assign mclk   = nodiv_mclk;
-
-
-//-----------------------------------------------------------
-// 6.3) ACLK GENERATION
-//-----------------------------------------------------------
-
-// ASIC MODE
-//----------------------------
-  reg       aclk_en;
-  reg [2:0] aclk_div;
-  wire      aclk_en_nxt =  lfxt_clk_en & ((bcsctl1[5:4]==2'b00) ?  1'b1 :
-                                          (bcsctl1[5:4]==2'b01) ?  aclk_div[0]   :
-                                          (bcsctl1[5:4]==2'b10) ? &aclk_div[1:0] :
-                                                                     &aclk_div[2:0]);
-
-  always @ (posedge mclk or posedge puc_rst)
-    if (puc_rst)                                     aclk_div <=  3'h0;
-    else if ((bcsctl1[5:4]!=2'b00) & lfxt_clk_en) aclk_div <=  aclk_div+3'h1;
-
-  always @ (posedge mclk or posedge puc_rst)
-    if (puc_rst)  aclk_en <=  1'b0;
-    else          aclk_en <=  aclk_en_nxt & cpu_en_s;
-
-  assign  aclk   = mclk;
-   
-//-----------------------------------------------------------
-// 6.4) SMCLK GENERATION
-//-----------------------------------------------------------
-
-// Clock MUX
-//----------------------------
-assign nodiv_smclk = dco_clk;
-
-
-// ASIC MODE
-//----------------------------
-reg       smclk_en;
-reg [2:0] smclk_div;
-
-wire      smclk_in     = ~scg1 & (bcsctl2[3] ? lfxt_clk_en : 1'b1);
-
-wire      smclk_en_nxt = smclk_in & ((bcsctl2[2:1]==2'b00) ?  1'b1 :
-                                     (bcsctl2[2:1]==2'b01) ?  smclk_div[0]   :
-                                     (bcsctl2[2:1]==2'b10) ? &smclk_div[1:0] :
-                                                                &smclk_div[2:0]);
-   
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)  smclk_en <=  1'b0;
-  else          smclk_en <=  smclk_en_nxt & cpu_en_s;
-
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)                                  smclk_div <=  3'h0;
-  else if ((bcsctl2[2:1]!=2'b00) & smclk_in) smclk_div <=  smclk_div+3'h1;
-
-wire  smclk  = mclk;
-
-
-//-----------------------------------------------------------
-// 6.5) DEBUG INTERFACE CLOCK GENERATION (DBG_CLK)
-//-----------------------------------------------------------
-
-// Synchronize DBG_EN signal to MCLK domain
-//------------------------------------------
-    assign dbg_en_s    =  dbg_en;
-    wire   dbg_rst_nxt = ~dbg_en;
-
-
-// Serial Debug Interface Clock gate
-//------------------------------------------------
-       assign dbg_clk = dco_clk;
-  
-
-//=============================================================================
-// 7)  RESET GENERATION
-//=============================================================================
-//
-// Whenever the reset pin (reset_n) is deasserted, the internal resets of the
-// openMSP430 will be released in the following order:
-//                1- POR
-//                2- DBG_RST (if the sdi interface is enabled, i.e. dbg_en=1)
-//                3- PUC
-//
-// Note: releasing the DBG_RST before PUC is particularly important in order
-//       to allow the sdi interface to halt the cpu immediately after a PUC.
-//
-   
-// Generate synchronized POR to MCLK domain
-//------------------------------------------
-
-// Asynchronous reset source
-assign    por_a         =  !reset_n;
-wire      por_noscan;
-
-// Reset Synchronizer
-omsp_sync_reset sync_reset_por (
-    .rst_s        (por_noscan),
-    .clk          (nodiv_mclk),
-    .rst_a        (por_a)
-);
-
-// Scan Reset Mux
- assign por = por_noscan;
-
-// Generate synchronized reset for the SDI
-//------------------------------------------
-
-// Reset Generation
-reg  dbg_rst_noscan;
-always @ (posedge mclk or posedge por)
-  if (por)  dbg_rst_noscan <=  1'b1;
-  else      dbg_rst_noscan <=  dbg_rst_nxt;
-
-  // Scan Reset Mux
-     assign dbg_rst = dbg_rst_noscan;
-  
-
-
-// Generate main system reset (PUC_RST)
-//--------------------------------------
-wire puc_noscan_n;
-wire puc_a_scan;
-
-// Asynchronous PUC reset
-wire puc_a = por | wdt_reset;
-
-// Synchronous PUC reset
-wire puc_s = dbg_cpu_reset |                              // With the debug interface command
-
-            (dbg_en_s & dbg_rst_noscan & ~puc_noscan_n);  // Sequencing making sure PUC is released
-                                                          // after DBG_RST if the debug interface is
-                                                          // enabled at power-on-reset time
-// Scan Reset Mux
-  assign puc_a_scan = puc_a;
-
-// Reset Synchronizer
-// (required because of the asynchronous watchdog reset)
-omsp_sync_cell sync_cell_puc (
-    .data_out  (puc_noscan_n),
-    .data_in   (~puc_s),
-    .clk       (mclk),
-    .rst       (puc_a_scan)
-);
-
-// Scan Reset Mux
-  assign puc_rst = ~puc_noscan_n;
-
-// PUC pending set the serial debug interface
-assign puc_pnd_set = ~puc_noscan_n;
-
-
-endmodule // omsp_clock_module
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_mux.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_mux.v
deleted file mode 100644
index 5f8406a..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_clock_mux.v
+++ /dev/null
@@ -1,192 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_clock_mux.v
-// 
-// *Module Description:
-//                       Standard clock mux for the openMSP430
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 103 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
-//----------------------------------------------------------------------------
-
-module  omsp_clock_mux (
-
-// OUTPUTs
-    clk_out,                   // Clock output
-
-// INPUTs
-    clk_in0,                   // Clock input 0
-    clk_in1,                   // Clock input 1
-    reset,                     // Reset
-    scan_mode,                 // Scan mode (clk_in0 is selected in scan mode)
-    select                     // Clock selection
-);
-
-// OUTPUTs
-//=========
-output         clk_out;        // Clock output
-
-// INPUTs
-//=========
-input          clk_in0;        // Clock input 0
-input          clk_in1;        // Clock input 1
-input          reset;          // Reset
-input          scan_mode;      // Scan mode (clk_in0 is selected in scan mode)
-input          select;         // Clock selection
-
-
-//===========================================================================================================================//
-// 1)  CLOCK MUX                                                                                                             //
-//===========================================================================================================================//
-//                                                                                                                           //
-//    The following (glitch free) clock mux is implemented as following:                                                     //
-//                                                                                                                           //
-//                                                                                                                           //
-//                                                                                                                           //
-//                                                                                                                           //
-//                                   +-----.     +--------+   +--------+                                                     //
-//       select >>----+-------------O|      \    |        |   |        |          +-----.                                    //
-//                    |              |       |---| D    Q |---| D    Q |--+-------|      \                                   //
-//                    |     +-------O|      /    |        |   |        |  |       |       |O-+                               //
-//                    |     |        +-----'     |        |   |        |  |   +--O|      /   |                               //
-//                    |     |                    |   /\   |   |   /\   |  |   |   +-----'    |                               //
-//                    |     |                    +--+--+--+   +--+--+--+  |   |              |                               //
-//                    |     |                        O            |       |   |              |                               //
-//                    |     |                        |            |       |   |              |  +-----.                      //
-//       clk_in0 >>----------------------------------+------------+-----------+              +--|      \                     //
-//                    |     |                                             |                     |       |----<< clk_out      //
-//                    |     |     +---------------------------------------+                  +--|      /                     //
-//                    |     |     |                                                          |  +-----'                      //
-//                    |     +---------------------------------------------+                  |                               //
-//                    |           |                                       |                  |                               //
-//                    |           |  +-----.     +--------+   +--------+  |                  |                               //
-//                    |           +-O|      \    |        |   |        |  |       +-----.    |                               //
-//                    |              |       |---| D    Q |---| D    Q |--+-------|      \   |                               //
-//                    +--------------|      /    |        |   |        |          |       |O-+                               //
-//                                   +-----'     |        |   |        |      +--O|      /                                   //
-//                                               |   /\   |   |   /\   |      |   +-----'                                    //
-//                                               +--+--+--+   +--+--+--+      |                                              //
-//                                                   O            |           |                                              //
-//                                                   |            |           |                                              //
-//       clk_in1 >>----------------------------------+------------+-----------+                                              //
-//                                                                                                                           //
-//                                                                                                                           //
-//===========================================================================================================================//
-
-//-----------------------------------------------------------------------------
-// Wire declarations
-//-----------------------------------------------------------------------------
-   
-wire in0_select;
-reg  in0_select_s;
-reg  in0_select_ss;
-wire in0_enable;
-
-wire in1_select;
-reg  in1_select_s;
-reg  in1_select_ss;
-wire in1_enable;
-
-wire clk_in0_inv;
-wire clk_in1_inv;
-wire gated_clk_in0;
-wire gated_clk_in1;
-
-
-//-----------------------------------------------------------------------------
-// CLK_IN0 Selection
-//-----------------------------------------------------------------------------
-   
-assign in0_select = ~select & ~in1_select_ss;
-   
-always @ (posedge clk_in0_inv or posedge reset)
-  if (reset) in0_select_s  <=  1'b1;
-  else       in0_select_s  <=  in0_select;
-
-always @ (posedge clk_in0     or posedge reset)
-  if (reset) in0_select_ss <=  1'b1;
-  else       in0_select_ss <=  in0_select_s;
-
-assign in0_enable = in0_select_ss | scan_mode;
-
-
-//-----------------------------------------------------------------------------
-// CLK_IN1 Selection
-//-----------------------------------------------------------------------------
-   
-assign in1_select =  select & ~in0_select_ss;
-   
-always @ (posedge clk_in1_inv or posedge reset)
-  if (reset) in1_select_s  <=  1'b0;
-  else       in1_select_s  <=  in1_select;
-
-always @ (posedge clk_in1     or posedge reset)
-  if (reset) in1_select_ss <=  1'b0;
-  else       in1_select_ss <=  in1_select_s;
-
-assign in1_enable = in1_select_ss & ~scan_mode;
-
-   
-//-----------------------------------------------------------------------------
-// Clock MUX
-//-----------------------------------------------------------------------------
-//
-// IMPORTANT NOTE:
-//                  Because the clock network is a critical part of the design,
-//                 the following combinatorial logic should be replaced with
-//                 direct instanciation of standard cells from target library.
-//                  Don't forget the "dont_touch" attribute to make sure
-//                 synthesis won't mess it up.
-//
-
-// Replace with standard cell INVERTER
-assign clk_in0_inv   = ~clk_in0;
-assign clk_in1_inv   = ~clk_in1;
-
-
-// Replace with standard cell NAND2
-assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
-assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
-   
-
-// Replace with standard cell AND2
-assign clk_out       =  (gated_clk_in0 & gated_clk_in1);
-
-
-
-endmodule // omsp_clock_gate
-
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg.v
deleted file mode 100644
index 5c505fa..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg.v
+++ /dev/null
@@ -1,1522 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_dbg.v
-// 
-// *Module Description:
-//                       Debug interface
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 175 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Wed, 30 Jan 2013) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_dbg (
-
-// OUTPUTs
-    dbg_cpu_reset,                     // Reset CPU from debug interface
-    dbg_freeze,                        // Freeze peripherals
-    dbg_halt_cmd,                      // Halt CPU command
-    dbg_i2c_sda_out,                   // Debug interface: I2C SDA OUT
-    dbg_mem_addr,                      // Debug address for rd/wr access
-    dbg_mem_dout,                      // Debug unit data output
-    dbg_mem_en,                        // Debug unit memory enable
-    dbg_mem_wr,                        // Debug unit memory write
-    dbg_reg_wr,                        // Debug unit CPU register write
-    dbg_uart_txd,                      // Debug interface: UART TXD
-			     
-// INPUTs
-    cpu_en_s,                          // Enable CPU code execution (synchronous)
-    cpu_id,                            // CPU ID
-    cpu_nr_inst,                       // Current oMSP instance number
-    cpu_nr_total,                      // Total number of oMSP instances-1
-    dbg_clk,                           // Debug unit clock
-    dbg_en_s,                          // Debug interface enable (synchronous)
-    dbg_halt_st,                       // Halt/Run status from CPU
-    dbg_i2c_addr,                      // Debug interface: I2C Address
-    dbg_i2c_broadcast,                 // Debug interface: I2C Broadcast Address (for multicore systems)
-    dbg_i2c_scl,                       // Debug interface: I2C SCL
-    dbg_i2c_sda_in,                    // Debug interface: I2C SDA IN
-    dbg_mem_din,                       // Debug unit Memory data input
-    dbg_reg_din,                       // Debug unit CPU register data input
-    dbg_rst,                           // Debug unit reset
-    dbg_uart_rxd,                      // Debug interface: UART RXD (asynchronous)
-    decode_noirq,                      // Frontend decode instruction
-    eu_mab,                            // Execution-Unit Memory address bus
-    eu_mb_en,                          // Execution-Unit Memory bus enable
-    eu_mb_wr,                          // Execution-Unit Memory bus write transfer
-    fe_mdb_in,                         // Frontend Memory data bus input
-    pc,                                // Program counter
-    puc_pnd_set                        // PUC pending set for the serial debug interface
-);
-
-// OUTPUTs
-//=========
-output              dbg_cpu_reset;     // Reset CPU from debug interface
-output              dbg_freeze;        // Freeze peripherals
-output              dbg_halt_cmd;      // Halt CPU command
-output              dbg_i2c_sda_out;   // Debug interface: I2C SDA OUT
-output       [15:0] dbg_mem_addr;      // Debug address for rd/wr access
-output       [15:0] dbg_mem_dout;      // Debug unit data output
-output              dbg_mem_en;        // Debug unit memory enable
-output        [1:0] dbg_mem_wr;        // Debug unit memory write
-output              dbg_reg_wr;        // Debug unit CPU register write
-output              dbg_uart_txd;      // Debug interface: UART TXD
-
-// INPUTs
-//=========
-input               cpu_en_s;          // Enable CPU code execution (synchronous)
-input        [31:0] cpu_id;            // CPU ID
-input         [7:0] cpu_nr_inst;       // Current oMSP instance number
-input         [7:0] cpu_nr_total;      // Total number of oMSP instances-1
-input               dbg_clk;           // Debug unit clock
-input               dbg_en_s;          // Debug interface enable (synchronous)
-input               dbg_halt_st;       // Halt/Run status from CPU
-input         [6:0] dbg_i2c_addr;      // Debug interface: I2C Address
-input         [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
-input               dbg_i2c_scl;       // Debug interface: I2C SCL
-input               dbg_i2c_sda_in;    // Debug interface: I2C SDA IN
-input        [15:0] dbg_mem_din;       // Debug unit Memory data input
-input        [15:0] dbg_reg_din;       // Debug unit CPU register data input
-input               dbg_rst;           // Debug unit reset
-input               dbg_uart_rxd;      // Debug interface: UART RXD (asynchronous)
-input               decode_noirq;      // Frontend decode instruction
-input        [15:0] eu_mab;            // Execution-Unit Memory address bus
-input               eu_mb_en;          // Execution-Unit Memory bus enable
-input         [1:0] eu_mb_wr;          // Execution-Unit Memory bus write transfer
-input        [15:0] fe_mdb_in;         // Frontend Memory data bus input
-input        [15:0] pc;                // Program counter
-input               puc_pnd_set;       // PUC pending set for the serial debug interface
-
-
-//=============================================================================
-// 1)  WIRE & PARAMETER DECLARATION
-//=============================================================================
-
-// Diverse wires and registers
-wire  [5:0] dbg_addr;
-wire [15:0] dbg_din;
-wire        dbg_wr;
-reg 	    mem_burst;
-wire        dbg_reg_rd;
-wire        dbg_mem_rd;
-reg         dbg_mem_rd_dly;
-wire        dbg_swbrk;
-wire        dbg_rd;
-reg         dbg_rd_rdy;
-wire        mem_burst_rd;
-wire        mem_burst_wr;
-wire        brk0_halt;
-wire        brk0_pnd;
-wire [15:0] brk0_dout;
-wire        brk1_halt;
-wire        brk1_pnd;
-wire [15:0] brk1_dout;
-wire        brk2_halt;
-wire        brk2_pnd;
-wire [15:0] brk2_dout;
-wire        brk3_halt;
-wire        brk3_pnd;
-wire [15:0] brk3_dout;
-    
-// Number of registers
-parameter           NR_REG       = 25;
-
-// Register addresses
-parameter           CPU_ID_LO    = 6'h00;
-parameter           CPU_ID_HI    = 6'h01;
-parameter           CPU_CTL      = 6'h02;
-parameter           CPU_STAT     = 6'h03;
-parameter           MEM_CTL      = 6'h04;
-parameter           MEM_ADDR     = 6'h05;
-parameter           MEM_DATA     = 6'h06;
-parameter           MEM_CNT      = 6'h07;
-parameter           CPU_NR       = 6'h18;
-
-// Register one-hot decoder
-parameter           BASE_D       = {{NR_REG-1{1'b0}}, 1'b1};
-parameter           CPU_ID_LO_D  = (BASE_D << CPU_ID_LO);
-parameter           CPU_ID_HI_D  = (BASE_D << CPU_ID_HI);
-parameter           CPU_CTL_D    = (BASE_D << CPU_CTL);
-parameter           CPU_STAT_D   = (BASE_D << CPU_STAT);
-parameter           MEM_CTL_D    = (BASE_D << MEM_CTL);
-parameter           MEM_ADDR_D   = (BASE_D << MEM_ADDR);
-parameter           MEM_DATA_D   = (BASE_D << MEM_DATA);
-parameter           MEM_CNT_D    = (BASE_D << MEM_CNT);
-parameter           CPU_NR_D     = (BASE_D << CPU_NR);
-
-
-//============================================================================
-// 2)  REGISTER DECODER
-//============================================================================
-
-// Select Data register during a burst
-wire  [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
-
-// Register address decode
-reg  [NR_REG-1:0]  reg_dec; 
-always @(dbg_addr_in)
-  case (dbg_addr_in)
-    CPU_ID_LO :  reg_dec  =  CPU_ID_LO_D;
-    CPU_ID_HI :  reg_dec  =  CPU_ID_HI_D;
-    CPU_CTL   :  reg_dec  =  CPU_CTL_D;
-    CPU_STAT  :  reg_dec  =  CPU_STAT_D;
-    MEM_CTL   :  reg_dec  =  MEM_CTL_D;
-    MEM_ADDR  :  reg_dec  =  MEM_ADDR_D;
-    MEM_DATA  :  reg_dec  =  MEM_DATA_D;
-    MEM_CNT   :  reg_dec  =  MEM_CNT_D;
-    CPU_NR    :  reg_dec  =  CPU_NR_D;
-  // pragma coverage off
-    default:     reg_dec  =  {NR_REG{1'b0}};
-  // pragma coverage on
-  endcase
-
-// Read/Write probes
-wire               reg_write =  dbg_wr;
-wire               reg_read  =  1'b1;
-
-// Read/Write vectors
-wire  [NR_REG-1:0] reg_wr    = reg_dec & {NR_REG{reg_write}};
-wire  [NR_REG-1:0] reg_rd    = reg_dec & {NR_REG{reg_read}};
-
-
-//=============================================================================
-// 3)  REGISTER: CORE INTERFACE
-//=============================================================================
-
-// CPU_ID Register
-//-----------------   
-//              -------------------------------------------------------------------
-// CPU_ID_LO:  | 15  14  13  12  11  10  9  |  8  7  6  5  4  |  3   |   2  1  0   |
-//             |----------------------------+-----------------+------+-------------|
-//             |        PER_SPACE           |   USER_VERSION  | ASIC | CPU_VERSION |
-//              --------------------------------------------------------------------
-// CPU_ID_HI:  |   15  14  13  12  11  10   |   9  8  7  6  5  4  3  2  1   |   0  |
-//             |----------------------------+-------------------------------+------|
-//             |         PMEM_SIZE          |            DMEM_SIZE          |  MPY |
-//              -------------------------------------------------------------------
-
-// This register is assigned in the SFR module
-
-
-// CPU_NR Register
-//-----------------
-//    -------------------------------------------------------------------
-//   | 15  14  13  12  11  10   9   8  |  7   6   5   4   3   2   1   0  |
-//   |---------------------------------+---------------------------------|
-//   |            CPU_TOTAL_NR         |           CPU_INST_NR           |
-//    -------------------------------------------------------------------
-
-wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
-
-
-// CPU_CTL Register
-//-----------------------------------------------------------------------------
-//       7         6          5          4           3        2     1    0
-//   Reserved   CPU_RST  RST_BRK_EN  FRZ_BRK_EN  SW_BRK_EN  ISTEP  RUN  HALT
-//-----------------------------------------------------------------------------
-reg   [6:3] cpu_ctl;
-
-wire        cpu_ctl_wr = reg_wr[CPU_CTL];
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)         cpu_ctl <=  4'h6;
-  else if (cpu_ctl_wr) cpu_ctl <=  dbg_din[6:3];
-
-wire  [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
-
-wire        halt_cpu = cpu_ctl_wr & dbg_din[0]  & ~dbg_halt_st;
-wire        run_cpu  = cpu_ctl_wr & dbg_din[1]   &  dbg_halt_st;
-wire        istep    = cpu_ctl_wr & dbg_din[2] &  dbg_halt_st;
-
-   
-// CPU_STAT Register
-//------------------------------------------------------------------------------------
-//      7           6          5           4           3         2      1       0
-// HWBRK3_PND  HWBRK2_PND  HWBRK1_PND  HWBRK0_PND  SWBRK_PND  PUC_PND  Res.  HALT_RUN
-//------------------------------------------------------------------------------------
-reg   [3:2] cpu_stat;
-
-wire        cpu_stat_wr  = reg_wr[CPU_STAT];
-wire  [3:2] cpu_stat_set = {dbg_swbrk, puc_pnd_set};
-wire  [3:2] cpu_stat_clr = ~dbg_din[3:2];
-
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)          cpu_stat <=  2'b00;
-  else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
-  else                  cpu_stat <=  (cpu_stat                 | cpu_stat_set);
-
-wire  [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
-                             cpu_stat, 1'b0, dbg_halt_st};
-
-   
-//=============================================================================
-// 4)  REGISTER: MEMORY INTERFACE
-//=============================================================================
-
-// MEM_CTL Register
-//-----------------------------------------------------------------------------
-//       7     6     5     4          3        2         1       0
-//            Reserved               B/W    MEM/REG    RD/WR   START
-//
-// START  :  -  0 : Do nothing.
-//           -  1 : Initiate memory transfer.
-//
-// RD/WR  :  -  0 : Read access.
-//           -  1 : Write access.
-//
-// MEM/REG:  -  0 : Memory access.
-//           -  1 : CPU Register access.
-//
-// B/W    :  -  0 : 16 bit access.
-//           -  1 :  8 bit access (not valid for CPU Registers).
-//
-//-----------------------------------------------------------------------------
-reg   [3:1] mem_ctl;
-
-wire        mem_ctl_wr = reg_wr[MEM_CTL];
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)         mem_ctl <=  3'h0;
-  else if (mem_ctl_wr) mem_ctl <=  dbg_din[3:1];
-
-wire  [7:0] mem_ctl_full  = {4'b0000, mem_ctl, 1'b0};
-
-reg         mem_start;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)  mem_start <=  1'b0;
-  else          mem_start <=  mem_ctl_wr & dbg_din[0];
-
-wire        mem_bw    = mem_ctl[3];
-   
-// MEM_DATA Register
-//------------------   
-reg  [15:0] mem_data;
-reg  [15:0] mem_addr;
-wire        mem_access;
-   
-wire        mem_data_wr = reg_wr[MEM_DATA];
-
-wire [15:0] dbg_mem_din_bw = ~mem_bw      ? dbg_mem_din                :
-	                      mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
-	                                    {8'h00, dbg_mem_din[7:0]};
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)             mem_data <=  16'h0000;
-  else if (mem_data_wr)    mem_data <=  dbg_din;
-  else if (dbg_reg_rd)     mem_data <=  dbg_reg_din;
-  else if (dbg_mem_rd_dly) mem_data <=  dbg_mem_din_bw;
-
-   
-// MEM_ADDR Register
-//------------------   
-reg  [15:0] mem_cnt;
-
-wire        mem_addr_wr  = reg_wr[MEM_ADDR];
-wire        dbg_mem_acc  = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
-wire        dbg_reg_acc  = ( dbg_reg_wr | (dbg_rd_rdy &  mem_ctl[2]));
-   
-wire [15:0] mem_addr_inc = (mem_cnt==16'h0000)                       ? 16'h0000 : 
-                           (mem_burst &  dbg_mem_acc & ~mem_bw)      ? 16'h0002 : 
-                           (mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'h0001 : 16'h0000; 
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)          mem_addr <=  16'h0000;
-  else if (mem_addr_wr) mem_addr <=  dbg_din;
-  else                  mem_addr <=  mem_addr + mem_addr_inc;
-   
-// MEM_CNT Register
-//------------------   
-
-wire        mem_cnt_wr  = reg_wr[MEM_CNT];
-
-wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000)                       ? 16'h0000 :
-                          (mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'hffff : 16'h0000;
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)         mem_cnt <=  16'h0000;
-  else if (mem_cnt_wr) mem_cnt <=  dbg_din;
-  else                 mem_cnt <=  mem_cnt + mem_cnt_dec;
-
-
-//=============================================================================
-// 5)  BREAKPOINTS / WATCHPOINTS
-//=============================================================================
-
-assign brk0_halt =  1'b0;
-assign brk0_pnd  =  1'b0;
-assign brk0_dout = 16'h0000;
-
-assign brk1_halt =  1'b0;
-assign brk1_pnd  =  1'b0;
-assign brk1_dout = 16'h0000;
-
- assign brk2_halt =  1'b0;
-assign brk2_pnd  =  1'b0;
-assign brk2_dout = 16'h0000;
-
-assign brk3_halt =  1'b0;
-assign brk3_pnd  =  1'b0;
-assign brk3_dout = 16'h0000;
-
-
-//============================================================================
-// 6) DATA OUTPUT GENERATION
-//============================================================================
-
-wire [15:0] cpu_id_lo_rd = cpu_id[15:0]           & {16{reg_rd[CPU_ID_LO]}};
-wire [15:0] cpu_id_hi_rd = cpu_id[31:16]          & {16{reg_rd[CPU_ID_HI]}};
-wire [15:0] cpu_ctl_rd   = {8'h00, cpu_ctl_full}  & {16{reg_rd[CPU_CTL]}};
-wire [15:0] cpu_stat_rd  = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
-wire [15:0] mem_ctl_rd   = {8'h00, mem_ctl_full}  & {16{reg_rd[MEM_CTL]}};
-wire [15:0] mem_data_rd  = mem_data               & {16{reg_rd[MEM_DATA]}};
-wire [15:0] mem_addr_rd  = mem_addr               & {16{reg_rd[MEM_ADDR]}};
-wire [15:0] mem_cnt_rd   = mem_cnt                & {16{reg_rd[MEM_CNT]}};
-wire [15:0] cpu_nr_rd    = cpu_nr                 & {16{reg_rd[CPU_NR]}};
-
-wire [15:0] dbg_dout = cpu_id_lo_rd |
-                       cpu_id_hi_rd |
-                       cpu_ctl_rd   |
-                       cpu_stat_rd  |
-                       mem_ctl_rd   |
-                       mem_data_rd  |
-                       mem_addr_rd  |
-                       mem_cnt_rd   |
-                       brk0_dout    |
-                       brk1_dout    |
-                       brk2_dout    |
-                       brk3_dout    |
-                       cpu_nr_rd;
-
-// Tell UART/I2C interface that the data is ready to be read
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)                       dbg_rd_rdy  <=  1'b0;
-  else if (mem_burst | mem_burst_rd) dbg_rd_rdy  <= (dbg_reg_rd | dbg_mem_rd_dly);
-  else                               dbg_rd_rdy  <=  dbg_rd;
-
-
-//============================================================================
-// 7) CPU CONTROL
-//============================================================================
-
-// Reset CPU
-//--------------------------
-wire dbg_cpu_reset  = cpu_ctl[6];
-
-   
-// Break after reset
-//--------------------------
-wire halt_rst = cpu_ctl[5] & dbg_en_s & puc_pnd_set;
-
-   
-// Freeze peripherals
-//--------------------------
-wire dbg_freeze = dbg_halt_st & (cpu_ctl[4] | ~cpu_en_s);
-
-
-// Software break
-//--------------------------
-assign dbg_swbrk = (fe_mdb_in==16'h4343) & decode_noirq & cpu_ctl[3];
-
-
-// Single step
-//--------------------------
-reg [1:0] inc_step;
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)    inc_step <= 2'b00;
-  else if (istep) inc_step <= 2'b11;
-  else            inc_step <= {inc_step[0], 1'b0};
-
-   
-// Run / Halt
-//--------------------------
-reg   halt_flag;
-
-wire  mem_halt_cpu;
-wire  mem_run_cpu;
-
-wire  halt_flag_clr = run_cpu   | mem_run_cpu;
-wire  halt_flag_set = halt_cpu  | halt_rst  | dbg_swbrk | mem_halt_cpu |
-                      brk0_halt | brk1_halt | brk2_halt | brk3_halt;
-
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)            halt_flag <= 1'b0;
-  else if (halt_flag_clr) halt_flag <= 1'b0;
-  else if (halt_flag_set) halt_flag <= 1'b1;
-
-wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
-
-     
-//============================================================================
-// 8) MEMORY CONTROL
-//============================================================================
-
-// Control Memory bursts
-//------------------------------
-
-wire mem_burst_start = (mem_start             &  |mem_cnt);
-wire mem_burst_end   = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
-
-// Detect when burst is on going
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)              mem_burst <= 1'b0;
-  else if (mem_burst_start) mem_burst <= 1'b1;
-  else if (mem_burst_end)   mem_burst <= 1'b0;
-
-// Control signals for UART/I2C interface
-assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
-assign mem_burst_wr = (mem_burst_start &  mem_ctl[1]);
-
-// Trigger CPU Register or memory access during a burst
-reg        mem_startb;   
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) mem_startb <= 1'b0;
-  else         mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
-
-// Combine single and burst memory start of sequence
-wire       mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
-
-   
-// Memory access state machine
-//------------------------------
-reg  [1:0] mem_state;
-reg  [1:0] mem_state_nxt;
-
-// State machine definition
-parameter  M_IDLE       = 2'h0;
-parameter  M_SET_BRK    = 2'h1;
-parameter  M_ACCESS_BRK = 2'h2;
-parameter  M_ACCESS     = 2'h3;
-
-// State transition
-always @(mem_state or mem_seq_start or dbg_halt_st)
-  case (mem_state)
-    M_IDLE       : mem_state_nxt = ~mem_seq_start ? M_IDLE       : 
-                                    dbg_halt_st   ? M_ACCESS     : M_SET_BRK;
-    M_SET_BRK    : mem_state_nxt =  dbg_halt_st   ? M_ACCESS_BRK : M_SET_BRK;
-    M_ACCESS_BRK : mem_state_nxt =  M_IDLE;
-    M_ACCESS     : mem_state_nxt =  M_IDLE;
-  // pragma coverage off
-    default      : mem_state_nxt =  M_IDLE;
-  // pragma coverage on
-  endcase
-
-// State machine
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) mem_state <= M_IDLE;
-  else         mem_state <= mem_state_nxt;
-
-// Utility signals
-assign mem_halt_cpu = (mem_state==M_IDLE)       & (mem_state_nxt==M_SET_BRK);
-assign mem_run_cpu  = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
-assign mem_access   = (mem_state==M_ACCESS)     | (mem_state==M_ACCESS_BRK);
-
-
-// Interface to CPU Registers and Memory bacbkone
-//------------------------------------------------
-assign      dbg_mem_addr   =  mem_addr;
-assign      dbg_mem_dout   = ~mem_bw      ? mem_data               :
-                              mem_addr[0] ? {mem_data[7:0], 8'h00} :
-                                            {8'h00, mem_data[7:0]};
-
-assign      dbg_reg_wr     = mem_access &  mem_ctl[1] &  mem_ctl[2];
-assign      dbg_reg_rd     = mem_access & ~mem_ctl[1] &  mem_ctl[2];
-
-assign      dbg_mem_en     = mem_access & ~mem_ctl[2];
-assign      dbg_mem_rd     = dbg_mem_en & ~mem_ctl[1];
-
-wire  [1:0] dbg_mem_wr_msk = ~mem_bw      ? 2'b11 :
-                              mem_addr[0] ? 2'b10 : 2'b01;
-assign      dbg_mem_wr     = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
-
-
-// It takes one additional cycle to read from Memory as from registers
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) dbg_mem_rd_dly <= 1'b0;
-  else         dbg_mem_rd_dly <= dbg_mem_rd;
-
-      
-//=============================================================================
-// 9)  UART COMMUNICATION
-//=============================================================================
-omsp_dbg_uart dbg_uart_0 (
-
-// OUTPUTs
-    .dbg_addr         (dbg_addr),         // Debug register address
-    .dbg_din          (dbg_din),          // Debug register data input
-    .dbg_rd           (dbg_rd),           // Debug register data read
-    .dbg_uart_txd     (dbg_uart_txd),     // Debug interface: UART TXD
-    .dbg_wr           (dbg_wr),           // Debug register data write
-			     
-// INPUTs
-    .dbg_clk          (dbg_clk),          // Debug unit clock
-    .dbg_dout         (dbg_dout),         // Debug register data output
-    .dbg_rd_rdy       (dbg_rd_rdy),       // Debug register data is ready for read
-    .dbg_rst          (dbg_rst),          // Debug unit reset
-    .dbg_uart_rxd     (dbg_uart_rxd),     // Debug interface: UART RXD
-    .mem_burst        (mem_burst),        // Burst on going
-    .mem_burst_end    (mem_burst_end),    // End TX/RX burst
-    .mem_burst_rd     (mem_burst_rd),     // Start TX burst
-    .mem_burst_wr     (mem_burst_wr),     // Start RX burst
-    .mem_bw           (mem_bw)            // Burst byte width
-);
-
-
-//=============================================================================
-// 10)  I2C COMMUNICATION
-//=============================================================================
-    assign dbg_i2c_sda_out =  1'b1;
-
-endmodule // omsp_dbg
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_hwbrk.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_hwbrk.v
deleted file mode 100644
index b534c03..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_hwbrk.v
+++ /dev/null
@@ -1,1172 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_dbg_hwbrk.v
-// 
-// *Module Description:
-//                       Hardware Breakpoint / Watchpoint module
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 175 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Wed, 30 Jan 2013) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_dbg_hwbrk (
-
-// OUTPUTs
-    brk_halt,                // Hardware breakpoint command
-    brk_pnd,                 // Hardware break/watch-point pending
-    brk_dout,                // Hardware break/watch-point register data input
-			     
-// INPUTs
-    brk_reg_rd,              // Hardware break/watch-point register read select
-    brk_reg_wr,              // Hardware break/watch-point register write select
-    dbg_clk,                 // Debug unit clock
-    dbg_din,                 // Debug register data input
-    dbg_rst,                 // Debug unit reset
-    decode_noirq,            // Frontend decode instruction
-    eu_mab,                  // Execution-Unit Memory address bus
-    eu_mb_en,                // Execution-Unit Memory bus enable
-    eu_mb_wr,                // Execution-Unit Memory bus write transfer
-    pc                       // Program counter
-);
-
-// OUTPUTs
-//=========
-output         brk_halt;     // Hardware breakpoint command
-output         brk_pnd;      // Hardware break/watch-point pending
-output  [15:0] brk_dout;     // Hardware break/watch-point register data input
-
-// INPUTs
-//=========
-input    [3:0] brk_reg_rd;   // Hardware break/watch-point register read select
-input    [3:0] brk_reg_wr;   // Hardware break/watch-point register write select
-input          dbg_clk;      // Debug unit clock
-input   [15:0] dbg_din;      // Debug register data input
-input          dbg_rst;      // Debug unit reset
-input          decode_noirq; // Frontend decode instruction
-input   [15:0] eu_mab;       // Execution-Unit Memory address bus
-input          eu_mb_en;     // Execution-Unit Memory bus enable
-input    [1:0] eu_mb_wr;     // Execution-Unit Memory bus write transfer
-input   [15:0] pc;           // Program counter
-
-
-//=============================================================================
-// 1)  WIRE & PARAMETER DECLARATION
-//=============================================================================
-
-wire      range_wr_set;
-wire      range_rd_set;
-wire      addr1_wr_set;
-wire      addr1_rd_set;
-wire      addr0_wr_set;
-wire      addr0_rd_set;
-
-   
-parameter BRK_CTL   = 0,
-          BRK_STAT  = 1,
-          BRK_ADDR0 = 2,
-          BRK_ADDR1 = 3;
-
-   
-//=============================================================================
-// 2)  CONFIGURATION REGISTERS
-//=============================================================================
-
-// BRK_CTL Register
-//-----------------------------------------------------------------------------
-//       7   6   5        4            3          2            1  0
-//        Reserved    RANGE_MODE    INST_EN    BREAK_EN    ACCESS_MODE
-//
-// ACCESS_MODE: - 00 : Disabled
-//              - 01 : Detect read access
-//              - 10 : Detect write access
-//              - 11 : Detect read/write access
-//              NOTE: '10' & '11' modes are not supported on the instruction flow
-//
-// BREAK_EN:    -  0 : Watchmode enable
-//              -  1 : Break enable
-//
-// INST_EN:     -  0 : Checks are done on the execution unit (data flow)
-//              -  1 : Checks are done on the frontend (instruction flow)
-//
-// RANGE_MODE:  -  0 : Address match on BRK_ADDR0 or BRK_ADDR1
-//              -  1 : Address match on BRK_ADDR0->BRK_ADDR1 range
-//
-//-----------------------------------------------------------------------------
-reg   [4:0] brk_ctl;
-
-wire        brk_ctl_wr = brk_reg_wr[BRK_CTL];
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)         brk_ctl <=  5'h00;
-  else if (brk_ctl_wr) brk_ctl <=  {1'b0 & dbg_din[4], dbg_din[3:0]};
-
-wire  [7:0] brk_ctl_full = {3'b000, brk_ctl};
-
-   
-// BRK_STAT Register
-//-----------------------------------------------------------------------------
-//     7    6       5         4         3         2         1         0
-//    Reserved  RANGE_WR  RANGE_RD  ADDR1_WR  ADDR1_RD  ADDR0_WR  ADDR0_RD
-//-----------------------------------------------------------------------------
-reg   [5:0] brk_stat;
-
-wire        brk_stat_wr  = brk_reg_wr[BRK_STAT];
-wire  [5:0] brk_stat_set = {range_wr_set & 1'b0,
-                            range_rd_set & 1'b0,
-			    addr1_wr_set, addr1_rd_set,
-			    addr0_wr_set, addr0_rd_set};
-wire  [5:0] brk_stat_clr = ~dbg_din[5:0];
-
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)          brk_stat <=  6'h00;
-  else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
-  else                  brk_stat <=  (brk_stat                 | brk_stat_set);
-
-wire  [7:0] brk_stat_full = {2'b00, brk_stat};
-wire        brk_pnd       = |brk_stat;
-
-
-// BRK_ADDR0 Register
-//-----------------------------------------------------------------------------
-reg  [15:0] brk_addr0;
-
-wire        brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)           brk_addr0 <=  16'h0000;
-  else if (brk_addr0_wr) brk_addr0 <=  dbg_din;
-
-   
-// BRK_ADDR1/DATA0 Register
-//-----------------------------------------------------------------------------
-reg  [15:0] brk_addr1;
-
-wire        brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)           brk_addr1 <=  16'h0000;
-  else if (brk_addr1_wr) brk_addr1 <=  dbg_din;
-
-   
-//============================================================================
-// 3) DATA OUTPUT GENERATION
-//============================================================================
-
-wire [15:0] brk_ctl_rd   = {8'h00, brk_ctl_full}  & {16{brk_reg_rd[BRK_CTL]}};
-wire [15:0] brk_stat_rd  = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
-wire [15:0] brk_addr0_rd = brk_addr0              & {16{brk_reg_rd[BRK_ADDR0]}};
-wire [15:0] brk_addr1_rd = brk_addr1              & {16{brk_reg_rd[BRK_ADDR1]}};
-
-wire [15:0] brk_dout = brk_ctl_rd   |
-                       brk_stat_rd  |
-                       brk_addr0_rd |
-                       brk_addr1_rd;
-
-   
-//============================================================================
-// 4) BREAKPOINT / WATCHPOINT GENERATION
-//============================================================================
-
-// Comparators
-//---------------------------
-// Note: here the comparison logic is instanciated several times in order
-//       to improve the timings, at the cost of a bit more area.
-   
-wire        equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[4];
-wire        equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[4];
-wire        equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & 
-                          brk_ctl[4] & 1'b0;
-
-
-wire        equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[4];
-wire        equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[4];
-wire        equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
-                          brk_ctl[4] & 1'b0;
-
-
-// Detect accesses
-//---------------------------
-
-// Detect Instruction read access
-wire i_addr0_rd =  equ_i_addr0 &  brk_ctl[3];
-wire i_addr1_rd =  equ_i_addr1 &  brk_ctl[3];
-wire i_range_rd =  equ_i_range &  brk_ctl[3];
-
-// Detect Execution-Unit write access
-wire d_addr0_wr =  equ_d_addr0 & ~brk_ctl[3] &  |eu_mb_wr;
-wire d_addr1_wr =  equ_d_addr1 & ~brk_ctl[3] &  |eu_mb_wr;
-wire d_range_wr =  equ_d_range & ~brk_ctl[3] &  |eu_mb_wr;
-
-// Detect DATA read access
-wire d_addr0_rd =  equ_d_addr0 & ~brk_ctl[3] & ~|eu_mb_wr;
-wire d_addr1_rd =  equ_d_addr1 & ~brk_ctl[3] & ~|eu_mb_wr;
-wire d_range_rd =  equ_d_range & ~brk_ctl[3] & ~|eu_mb_wr;
-   
-// Set flags
-assign addr0_rd_set = brk_ctl[0] & (d_addr0_rd  | i_addr0_rd);
-assign addr0_wr_set = brk_ctl[1] &  d_addr0_wr;
-assign addr1_rd_set = brk_ctl[0] & (d_addr1_rd  | i_addr1_rd);
-assign addr1_wr_set = brk_ctl[1] &  d_addr1_wr;
-assign range_rd_set = brk_ctl[0] & (d_range_rd  | i_range_rd);
-assign range_wr_set = brk_ctl[1] &  d_range_wr;
-
-   
-// Break CPU
-assign brk_halt     = brk_ctl[2] & |brk_stat_set;
-   
-     
-endmodule // omsp_dbg_hwbrk
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_i2c.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_i2c.v
deleted file mode 100644
index 0410a38..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_i2c.v
+++ /dev/null
@@ -1,1381 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_dbg_i2c.v
-// 
-// *Module Description:
-//                       Debug I2C Slave communication interface
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 103 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_dbg_i2c (
-
-// OUTPUTs
-    dbg_addr,                          // Debug register address
-    dbg_din,                           // Debug register data input
-    dbg_i2c_sda_out,                   // Debug interface: I2C SDA OUT
-    dbg_rd,                            // Debug register data read
-    dbg_wr,                            // Debug register data write
-
-// INPUTs
-    dbg_clk,                           // Debug unit clock
-    dbg_dout,                          // Debug register data output
-    dbg_i2c_addr,                      // Debug interface: I2C ADDRESS
-    dbg_i2c_broadcast,                 // Debug interface: I2C Broadcast Address (for multicore systems)
-    dbg_i2c_scl,                       // Debug interface: I2C SCL
-    dbg_i2c_sda_in,                    // Debug interface: I2C SDA IN
-    dbg_rd_rdy,                        // Debug register data is ready for read
-    dbg_rst,                           // Debug unit reset
-    mem_burst,                         // Burst on going
-    mem_burst_end,                     // End TX/RX burst
-    mem_burst_rd,                      // Start TX burst
-    mem_burst_wr,                      // Start RX burst
-    mem_bw                             // Burst byte width
-);
-
-// OUTPUTs
-//=========
-output        [5:0] dbg_addr;          // Debug register address
-output       [15:0] dbg_din;           // Debug register data input
-output              dbg_i2c_sda_out;   // Debug interface: I2C SDA OUT
-output              dbg_rd;            // Debug register data read
-output              dbg_wr;            // Debug register data write
-
-// INPUTs
-//=========
-input               dbg_clk;           // Debug unit clock
-input        [15:0] dbg_dout;          // Debug register data output
-input         [6:0] dbg_i2c_addr;      // Debug interface: I2C ADDRESS
-input         [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
-input               dbg_i2c_scl;       // Debug interface: I2C SCL
-input               dbg_i2c_sda_in;    // Debug interface: I2C SDA IN
-input               dbg_rd_rdy;        // Debug register data is ready for read
-input               dbg_rst;           // Debug unit reset
-input               mem_burst;         // Burst on going
-input               mem_burst_end;     // End TX/RX burst
-input               mem_burst_rd;      // Start TX burst
-input               mem_burst_wr;      // Start RX burst
-input               mem_bw;            // Burst byte width
-
-
-//=============================================================================
-// 1) I2C RECEIVE LINE SYNCHRONIZTION & FILTERING
-//=============================================================================
-
-// Synchronize SCL/SDA inputs
-//--------------------------------
-
-wire scl_sync_n;
-omsp_sync_cell sync_cell_i2c_scl (
-    .data_out  (scl_sync_n),
-    .data_in   (~dbg_i2c_scl),
-    .clk       (dbg_clk),
-    .rst       (dbg_rst)
-);
-wire scl_sync = ~scl_sync_n;
-
-wire sda_in_sync_n;
-omsp_sync_cell sync_cell_i2c_sda (
-    .data_out  (sda_in_sync_n),
-    .data_in   (~dbg_i2c_sda_in),
-    .clk       (dbg_clk),
-    .rst       (dbg_rst)
-);
-wire sda_in_sync = ~sda_in_sync_n;
-
-    
-// SCL/SDA input buffers
-//--------------------------------
-
-reg  [1:0] scl_buf;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) scl_buf <=  2'h3;
-  else         scl_buf <=  {scl_buf[0], scl_sync};
-
-reg  [1:0] sda_in_buf;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) sda_in_buf <=  2'h3;
-  else         sda_in_buf <=  {sda_in_buf[0], sda_in_sync};
-
-
-// SCL/SDA Majority decision
-//------------------------------
-
-wire scl         =  (scl_sync      & scl_buf[0])    |
-                    (scl_sync      & scl_buf[1])    |
-                    (scl_buf[0]    & scl_buf[1]);
-   
-wire sda_in      =  (sda_in_sync   & sda_in_buf[0]) |
-                    (sda_in_sync   & sda_in_buf[1]) |
-                    (sda_in_buf[0] & sda_in_buf[1]);
-
-
-// SCL/SDA Edge detection
-//------------------------------
-
-// SDA Edge detection
-reg        sda_in_dly;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) sda_in_dly <=  1'b1;
-  else         sda_in_dly <=  sda_in;
-
-wire sda_in_fe   =  sda_in_dly & ~sda_in;
-wire sda_in_re   = ~sda_in_dly &  sda_in;
-wire sda_in_edge =  sda_in_dly ^  sda_in;
-
-// SCL Edge detection
-reg        scl_dly;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) scl_dly <=  1'b1;
-  else         scl_dly <=  scl;
-
-wire scl_fe      =  scl_dly    & ~scl;
-wire scl_re      = ~scl_dly    &  scl;
-wire scl_edge    =  scl_dly    ^  scl;
-
-
-// Delayed SCL Rising-Edge for SDA data sampling
-reg  [1:0] scl_re_dly;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) scl_re_dly <=  2'b00;
-  else         scl_re_dly <=  {scl_re_dly[0], scl_re};
-
-wire scl_sample  =  scl_re_dly[1];
-
-   
-//=============================================================================
-// 2) I2C START & STOP CONDITION DETECTION
-//=============================================================================
-
-//-----------------
-// Start condition
-//-----------------
-
-wire start_detect = sda_in_fe & scl;
-
-//-----------------
-// Stop condition
-//-----------------
-
- wire stop_detect = sda_in_re & scl;
-  
-//-----------------
-// I2C Slave Active
-//-----------------
-// The I2C logic will be activated whenever a start condition
-// is detected and will be disactivated if the slave address
-// doesn't match or if a stop condition is detected.
-
-wire i2c_addr_not_valid;
-
-reg  i2c_active_seq;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)                                 i2c_active_seq <= 1'b0;
-  else if (start_detect)                       i2c_active_seq <= 1'b1;
-  else if (stop_detect || i2c_addr_not_valid)  i2c_active_seq <= 1'b0;
-
-wire i2c_active =  i2c_active_seq & ~stop_detect;
-wire i2c_init   = ~i2c_active     |  start_detect;
-   
-
-//=============================================================================
-// 3) I2C STATE MACHINE
-//=============================================================================
-
-// State register/wires
-reg   [2:0] i2c_state;
-reg   [2:0] i2c_state_nxt;
-
-// Utility signals
-reg   [8:0] shift_buf;
-wire        shift_rx_done;
-wire        shift_tx_done;
-reg         dbg_rd;
-   
-// State machine definition
-parameter   RX_ADDR      =  3'h0;
-parameter   RX_ADDR_ACK  =  3'h1;
-parameter   RX_DATA      =  3'h2;
-parameter   RX_DATA_ACK  =  3'h3;
-parameter   TX_DATA      =  3'h4;
-parameter   TX_DATA_ACK  =  3'h5;
-
-// State transition
-always @(i2c_state or i2c_init or shift_rx_done or i2c_addr_not_valid or shift_tx_done or scl_fe or shift_buf or sda_in)
-  case (i2c_state)
-    RX_ADDR     : i2c_state_nxt =   i2c_init           ?  RX_ADDR      :
-                                   ~shift_rx_done      ?  RX_ADDR      :
-                                    i2c_addr_not_valid ?  RX_ADDR      :
-                                                          RX_ADDR_ACK;
-
-    RX_ADDR_ACK : i2c_state_nxt =   i2c_init           ?  RX_ADDR      :
-                                   ~scl_fe             ?  RX_ADDR_ACK  :
-                                    shift_buf[0]       ?  TX_DATA      :
-                                                          RX_DATA;
-
-    RX_DATA     : i2c_state_nxt =   i2c_init           ?  RX_ADDR      :
-                                   ~shift_rx_done      ?  RX_DATA      :
-                                                          RX_DATA_ACK;
-
-    RX_DATA_ACK : i2c_state_nxt =   i2c_init           ?  RX_ADDR      :
-                                   ~scl_fe             ?  RX_DATA_ACK  :
-                                                          RX_DATA;
-
-    TX_DATA     : i2c_state_nxt =   i2c_init           ?  RX_ADDR      :
-                                   ~shift_tx_done      ?  TX_DATA      :
-                                                          TX_DATA_ACK;
-
-    TX_DATA_ACK : i2c_state_nxt =   i2c_init           ?  RX_ADDR      :
-                                   ~scl_fe             ?  TX_DATA_ACK  :
-                                   ~sda_in             ?  TX_DATA      :
-                                                          RX_ADDR;
-  // pragma coverage off
-    default     : i2c_state_nxt =                         RX_ADDR;
-  // pragma coverage on
-  endcase
-   
-// State machine
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)       i2c_state <= RX_ADDR;
-  else               i2c_state <= i2c_state_nxt;
-
-
-//=============================================================================
-// 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
-//=============================================================================
-
-wire       shift_rx_en       = ((i2c_state==RX_ADDR) | (i2c_state    ==RX_DATA) | (i2c_state    ==RX_DATA_ACK));
-wire       shift_tx_en       =                         (i2c_state    ==TX_DATA) | (i2c_state    ==TX_DATA_ACK);
-wire       shift_tx_en_pre   =                         (i2c_state_nxt==TX_DATA) | (i2c_state_nxt==TX_DATA_ACK);
-
-assign     shift_rx_done     = shift_rx_en & scl_fe & shift_buf[8];
-assign     shift_tx_done     = shift_tx_en & scl_fe & (shift_buf==9'h100);
-
-wire       shift_buf_rx_init = i2c_init | ((i2c_state==RX_ADDR_ACK) & scl_fe & ~shift_buf[0]) |
-                                          ((i2c_state==RX_DATA_ACK) & scl_fe);
-wire       shift_buf_rx_en   = shift_rx_en     & scl_sample;
-
-wire       shift_buf_tx_init =            ((i2c_state==RX_ADDR_ACK) & scl_re &  shift_buf[0]) |
-                                          ((i2c_state==TX_DATA_ACK) & scl_re);
-wire       shift_buf_tx_en   = shift_tx_en_pre & scl_fe & (shift_buf!=9'h100);
-
-wire [7:0] shift_tx_val;
-   
-wire [8:0] shift_buf_nxt     = shift_buf_rx_init  ? 9'h001 : // RX Init 
-                               shift_buf_tx_init  ? {shift_tx_val,   1'b1}   : // TX Init 
-                               shift_buf_rx_en    ? {shift_buf[7:0], sda_in} : // RX Shift
-                               shift_buf_tx_en    ? {shift_buf[7:0], 1'b0}   : // TX Shift
-                                                     shift_buf[8:0];           // Hold
-
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) shift_buf <= 9'h001;
-  else         shift_buf <= shift_buf_nxt;
-
-// Detect when the received I2C device address is not valid
-assign i2c_addr_not_valid =  (i2c_state == RX_ADDR) && shift_rx_done && (
-                              (shift_buf[7:1] != dbg_i2c_addr[6:0]));
-
-// Utility signals
-wire        shift_rx_data_done = shift_rx_done & (i2c_state==RX_DATA); 
-wire        shift_tx_data_done = shift_tx_done; 
-
-
-//=============================================================================
-// 5) I2C TRANSMIT BUFFER
-//=============================================================================
-
-reg dbg_i2c_sda_out;
-
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)     dbg_i2c_sda_out <= 1'b1;
-  else if (scl_fe) dbg_i2c_sda_out <= ~((i2c_state_nxt==RX_ADDR_ACK) ||
-                                        (i2c_state_nxt==RX_DATA_ACK) ||
-                                       (shift_buf_tx_en & ~shift_buf[8]));
-   
-   
-//=============================================================================
-// 6) DEBUG INTERFACE STATE MACHINE
-//=============================================================================
-
-// State register/wires
-reg   [2:0] dbg_state;
-reg   [2:0] dbg_state_nxt;
-
-// Utility signals
-reg         dbg_bw;
-
-// State machine definition
-parameter  RX_CMD     = 3'h0;
-parameter  RX_BYTE_LO = 3'h1;
-parameter  RX_BYTE_HI = 3'h2;
-parameter  TX_BYTE_LO = 3'h3;
-parameter  TX_BYTE_HI = 3'h4;
-
-// State transition
-always @(dbg_state    or shift_rx_data_done or shift_tx_data_done or shift_buf     or dbg_bw or
-         mem_burst_wr or mem_burst_rd       or mem_burst          or mem_burst_end or mem_bw)
-  case (dbg_state)
-    RX_CMD     : dbg_state_nxt =  mem_burst_wr                ? RX_BYTE_LO  :
-                                  mem_burst_rd                ? TX_BYTE_LO  :
-                                  ~shift_rx_data_done         ? RX_CMD      :
-                                   shift_buf[7]               ? RX_BYTE_LO  :
-                                                                TX_BYTE_LO;
-
-    RX_BYTE_LO : dbg_state_nxt = (mem_burst &  mem_burst_end) ? RX_CMD      :
-                                  ~shift_rx_data_done         ? RX_BYTE_LO  :
-                                 (mem_burst & ~mem_burst_end) ?
-                                 (mem_bw                      ? RX_BYTE_LO  :
-                                                                RX_BYTE_HI) :
-                                  dbg_bw                      ? RX_CMD      :
-                                                                RX_BYTE_HI;
-
-    RX_BYTE_HI : dbg_state_nxt =  ~shift_rx_data_done         ? RX_BYTE_HI  :
-                                 (mem_burst & ~mem_burst_end) ? RX_BYTE_LO  :
-                                                                RX_CMD;
-
-    TX_BYTE_LO : dbg_state_nxt =  ~shift_tx_data_done         ? TX_BYTE_LO  :
-                                 ( mem_burst &  mem_bw)       ? TX_BYTE_LO  :
-                                 ( mem_burst & ~mem_bw)       ? TX_BYTE_HI  :
-                                  ~dbg_bw                     ? TX_BYTE_HI  :
-                                                                RX_CMD;
-
-    TX_BYTE_HI : dbg_state_nxt =  ~shift_tx_data_done         ? TX_BYTE_HI  :
-                                   mem_burst                  ? TX_BYTE_LO  :
-                                                                RX_CMD;
-
-  // pragma coverage off
-    default    : dbg_state_nxt =                                RX_CMD;
-  // pragma coverage on
-  endcase
-   
-// State machine
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) dbg_state <= RX_CMD;
-  else         dbg_state <= dbg_state_nxt;
-
-// Utility signals
-wire cmd_valid   = (dbg_state==RX_CMD)     & shift_rx_data_done;
-wire rx_lo_valid = (dbg_state==RX_BYTE_LO) & shift_rx_data_done;
-wire rx_hi_valid = (dbg_state==RX_BYTE_HI) & shift_rx_data_done;
-
-
-//=============================================================================
-// 7) REGISTER READ/WRITE ACCESS
-//=============================================================================
-
-parameter MEM_DATA = 6'h06;
-
-// Debug register address & bit width
-reg [5:0] dbg_addr;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)
-    begin
-       dbg_bw   <= 1'b0;
-       dbg_addr <= 6'h00;
-    end
-  else if (cmd_valid)
-    begin
-       dbg_bw   <= shift_buf[6];
-       dbg_addr <= shift_buf[5:0];
-    end
-  else if (mem_burst)
-    begin
-       dbg_bw   <= mem_bw;
-       dbg_addr <= MEM_DATA;
-    end
-
-
-// Debug register data input
-reg [7:0] dbg_din_lo;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)          dbg_din_lo <= 8'h00;
-  else if (rx_lo_valid) dbg_din_lo <= shift_buf[7:0];
-
-reg [7:0] dbg_din_hi;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)          dbg_din_hi <= 8'h00;
-  else if (rx_lo_valid) dbg_din_hi <= 8'h00;
-  else if (rx_hi_valid) dbg_din_hi <= shift_buf[7:0];
-   
-assign dbg_din = {dbg_din_hi, dbg_din_lo};
-
-
-// Debug register data write command
-reg  dbg_wr;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) dbg_wr <= 1'b0;
-  else         dbg_wr <= (mem_burst &  mem_bw) ? rx_lo_valid :
-                         (mem_burst & ~mem_bw) ? rx_hi_valid :
-                         dbg_bw                ? rx_lo_valid :
-                                                 rx_hi_valid;
-
-
-// Debug register data read command
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) dbg_rd <= 1'b0;
-  else         dbg_rd <= (mem_burst &  mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_LO)) :
-                         (mem_burst & ~mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_HI)) :        
-                         cmd_valid             ?  ~shift_buf[7]                                 :
-                                                  1'b0;
-
-
-// Debug register data read value 
-assign shift_tx_val = (dbg_state==TX_BYTE_HI) ? dbg_dout[15:8] :
-                                                dbg_dout[7:0];
-
-endmodule
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_uart.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_uart.v
deleted file mode 100644
index a28a3ef..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_dbg_uart.v
+++ /dev/null
@@ -1,1203 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_dbg_uart.v
-// 
-// *Module Description:
-//                       Debug UART communication interface (8N1, Half-duplex)
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 134 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_dbg_uart (
-
-// OUTPUTs
-    dbg_addr,                       // Debug register address
-    dbg_din,                        // Debug register data input
-    dbg_rd,                         // Debug register data read
-    dbg_uart_txd,                   // Debug interface: UART TXD
-    dbg_wr,                         // Debug register data write
-			     
-// INPUTs
-    dbg_clk,                        // Debug unit clock
-    dbg_dout,                       // Debug register data output
-    dbg_rd_rdy,                     // Debug register data is ready for read
-    dbg_rst,                        // Debug unit reset
-    dbg_uart_rxd,                   // Debug interface: UART RXD
-    mem_burst,                      // Burst on going
-    mem_burst_end,                  // End TX/RX burst
-    mem_burst_rd,                   // Start TX burst
-    mem_burst_wr,                   // Start RX burst
-    mem_bw                          // Burst byte width
-);
-
-// OUTPUTs
-//=========
-output        [5:0] dbg_addr;       // Debug register address
-output       [15:0] dbg_din;        // Debug register data input
-output              dbg_rd;         // Debug register data read
-output              dbg_uart_txd;   // Debug interface: UART TXD
-output              dbg_wr;         // Debug register data write
-
-// INPUTs
-//=========
-input               dbg_clk;        // Debug unit clock
-input        [15:0] dbg_dout;       // Debug register data output
-input               dbg_rd_rdy;     // Debug register data is ready for read
-input               dbg_rst;        // Debug unit reset
-input               dbg_uart_rxd;   // Debug interface: UART RXD
-input               mem_burst;      // Burst on going
-input               mem_burst_end;  // End TX/RX burst
-input               mem_burst_rd;   // Start TX burst
-input               mem_burst_wr;   // Start RX burst
-input               mem_bw;         // Burst byte width
-
-
-//=============================================================================
-// 1)  UART RECEIVE LINE SYNCHRONIZTION & FILTERING
-//=============================================================================
-
-// Synchronize RXD input
-//--------------------------------
-
-    wire uart_rxd_n;
-
-    omsp_sync_cell sync_cell_uart_rxd (
-        .data_out  (uart_rxd_n),
-        .data_in   (~dbg_uart_rxd),
-        .clk       (dbg_clk),
-        .rst       (dbg_rst)
-    );
-    wire uart_rxd = ~uart_rxd_n;
-   
-// RXD input buffer
-//--------------------------------
-reg  [1:0] rxd_buf;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) rxd_buf <=  2'h3;
-  else         rxd_buf <=  {rxd_buf[0], uart_rxd};
-
-// Majority decision
-//------------------------
-reg        rxd_maj;
-
-wire       rxd_maj_nxt = (uart_rxd   & rxd_buf[0]) |
-			 (uart_rxd   & rxd_buf[1]) |
-			 (rxd_buf[0] & rxd_buf[1]);
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst) rxd_maj <=  1'b1;
-  else         rxd_maj <=  rxd_maj_nxt;
-
-wire rxd_s    =  rxd_maj;
-wire rxd_fe   =  rxd_maj & ~rxd_maj_nxt;
-wire rxd_re   = ~rxd_maj &  rxd_maj_nxt;
-wire rxd_edge =  rxd_maj ^  rxd_maj_nxt;
-   
-//=============================================================================
-// 2)  UART STATE MACHINE
-//=============================================================================
-
-// Receive state
-//------------------------
-reg   [2:0] uart_state;
-reg   [2:0] uart_state_nxt;
-
-wire        sync_done;
-wire        xfer_done;
-reg  [19:0] xfer_buf;
-wire [19:0] xfer_buf_nxt;
-
-// State machine definition
-parameter  RX_SYNC  = 3'h0;
-parameter  RX_CMD   = 3'h1;
-parameter  RX_DATA1 = 3'h2;
-parameter  RX_DATA2 = 3'h3;
-parameter  TX_DATA1 = 3'h4;
-parameter  TX_DATA2 = 3'h5;
-
-// State transition
-always @(uart_state or xfer_buf_nxt or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
-  case (uart_state)
-    RX_SYNC  : uart_state_nxt =  RX_CMD;
-    RX_CMD   : uart_state_nxt =  mem_burst_wr                ?
-                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
-                                 mem_burst_rd                ?
-                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
-                                (xfer_buf_nxt[18]  ?
-                                (xfer_buf_nxt[17]  ? RX_DATA2 : RX_DATA1) :
-                                (xfer_buf_nxt[17]  ? TX_DATA2 : TX_DATA1));
-    RX_DATA1 : uart_state_nxt =  RX_DATA2;
-    RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
-                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
-                                 RX_CMD;
-    TX_DATA1 : uart_state_nxt =  TX_DATA2;
-    TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
-                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
-                                 RX_CMD;
-  // pragma coverage off
-    default  : uart_state_nxt =  RX_CMD;
-  // pragma coverage on
-  endcase
-   
-// State machine
-always @(posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)                          uart_state <= RX_SYNC;
-  else if (xfer_done    | sync_done |
-           mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
-
-// Utility signals
-wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
-wire rx_active = (uart_state==RX_DATA1) | (uart_state==RX_DATA2) | (uart_state==RX_CMD);
-wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
-
-   
-//=============================================================================
-// 3)  UART SYNCHRONIZATION
-//=============================================================================
-// After DBG_RST, the host needs to fist send a synchronization character (0x80)
-// If this feature doesn't work properly, it is possible to disable it by
-// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
-
-reg        sync_busy;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)                             sync_busy <=  1'b0;
-  else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <=  1'b1;
-  else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <=  1'b0;
-
-assign sync_done =  (uart_state==RX_SYNC) & rxd_re & sync_busy;
-
-
-reg [16+2:0] sync_cnt;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)                                     sync_cnt <=  {{16{1'b1}}, 3'b000};
-  else if (sync_busy | (~sync_busy & sync_cnt[2])) sync_cnt <=  sync_cnt+{{16+2{1'b0}}, 1'b1};
-
-wire [16-1:0] bit_cnt_max = sync_cnt[16+2:3];
-   
-   
-//=============================================================================
-// 4)  UART RECEIVE / TRANSMIT
-//=============================================================================
-   
-// Transfer counter
-//------------------------
-reg                      [3:0] xfer_bit;
-reg [16-1:0] xfer_cnt;
-
-wire       txd_start    = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
-wire       rxd_start    = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
-wire       xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={16{1'b0}});
-assign     xfer_done    = rx_active ? (xfer_bit==4'ha) : (xfer_bit==4'hb);
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)                       xfer_bit <=  4'h0;
-  else if (txd_start | rxd_start)    xfer_bit <=  4'h1;
-  else if (xfer_done)                xfer_bit <=  4'h0;
-  else if (xfer_bit_inc)             xfer_bit <=  xfer_bit+4'h1;
-
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)                       xfer_cnt <=  {16{1'b0}};
-  else if (rx_active & rxd_edge)     xfer_cnt <=  {1'b0, bit_cnt_max[16-1:1]};
-  else if (txd_start | xfer_bit_inc) xfer_cnt <=  bit_cnt_max;
-  else if (|xfer_cnt)                xfer_cnt <=  xfer_cnt+{16{1'b1}};
-
-
-// Receive/Transmit buffer
-//-------------------------
-assign xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};
-
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)           xfer_buf <=  20'h00000;
-  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
-  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;
-
-
-// Generate TXD output
-//------------------------
-reg dbg_uart_txd;
-   
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)                       dbg_uart_txd <=  1'b1;
-  else if (xfer_bit_inc & tx_active) dbg_uart_txd <=  xfer_buf[0];
-
- 
-//=============================================================================
-// 5) INTERFACE TO DEBUG REGISTERS
-//=============================================================================
-
-reg [5:0] dbg_addr;
- always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)        dbg_addr <=  6'h00;
-  else if (cmd_valid) dbg_addr <=  xfer_buf_nxt[16:11];
-
-reg       dbg_bw;
-always @ (posedge dbg_clk or posedge dbg_rst)
-  if (dbg_rst)        dbg_bw   <=  1'b0;
-  else if (cmd_valid) dbg_bw   <=  xfer_buf_nxt[17];
-
-wire        dbg_din_bw =  mem_burst  ? mem_bw : dbg_bw;
-
-wire [15:0] dbg_din    =  dbg_din_bw ? {8'h00,           xfer_buf_nxt[18:11]} :
-                                       {xfer_buf_nxt[18:11], xfer_buf_nxt[9:2]};
-wire        dbg_wr     = (xfer_done & (uart_state==RX_DATA2));
-wire        dbg_rd     = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
-                                     (cmd_valid & ~xfer_buf_nxt[18]) | mem_burst_rd;
-
-	    
-   
-endmodule // omsp_dbg_uart
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_execution_unit.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_execution_unit.v
deleted file mode 100644
index 7224cf4..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_execution_unit.v
+++ /dev/null
@@ -1,1313 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_execution_unit.v
-// 
-// *Module Description:
-//                       openMSP430 Execution unit
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 190 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-07-30 22:19:34 +0200 (Tue, 30 Jul 2013) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_execution_unit (
-
-// OUTPUTs
-    cpuoff,                        // Turns off the CPU
-    dbg_reg_din,                   // Debug unit CPU register data input
-    gie,                           // General interrupt enable
-    mab,                           // Memory address bus
-    mb_en,                         // Memory bus enable
-    mb_wr,                         // Memory bus write transfer
-    mdb_out,                       // Memory data bus output
-    oscoff,                        // Turns off LFXT1 clock input
-    pc_sw,                         // Program counter software value
-    pc_sw_wr,                      // Program counter software write
-    scg0,                          // System clock generator 1. Turns off the DCO
-    scg1,                          // System clock generator 1. Turns off the SMCLK
-
-// INPUTs
-    dbg_halt_st,                   // Halt/Run status from CPU
-    dbg_mem_dout,                  // Debug unit data output
-    dbg_reg_wr,                    // Debug unit CPU register write
-    e_state,                       // Execution state
-    exec_done,                     // Execution completed
-    inst_ad,                       // Decoded Inst: destination addressing mode
-    inst_as,                       // Decoded Inst: source addressing mode
-    inst_alu,                      // ALU control signals
-    inst_bw,                       // Decoded Inst: byte width
-    inst_dest,                     // Decoded Inst: destination (one hot)
-    inst_dext,                     // Decoded Inst: destination extended instruction word
-    inst_irq_rst,                  // Decoded Inst: reset interrupt
-    inst_jmp,                      // Decoded Inst: Conditional jump
-    inst_mov,                      // Decoded Inst: mov instruction
-    inst_sext,                     // Decoded Inst: source extended instruction word
-    inst_so,                       // Decoded Inst: Single-operand arithmetic
-    inst_src,                      // Decoded Inst: source (one hot)
-    inst_type,                     // Decoded Instruction type
-    mclk,                          // Main system clock
-    mdb_in,                        // Memory data bus input
-    pc,                            // Program counter
-    pc_nxt,                        // Next PC value (for CALL & IRQ)
-    puc_rst,                       // Main system reset
-    scan_enable                    // Scan enable (active during scan shifting)
-);
-
-// OUTPUTs
-//=========
-output 	            cpuoff;        // Turns off the CPU
-output       [15:0] dbg_reg_din;   // Debug unit CPU register data input
-output 	            gie;           // General interrupt enable
-output       [15:0] mab;           // Memory address bus
-output              mb_en;         // Memory bus enable
-output        [1:0] mb_wr;         // Memory bus write transfer
-output       [15:0] mdb_out;       // Memory data bus output
-output 	            oscoff;        // Turns off LFXT1 clock input
-output       [15:0] pc_sw;         // Program counter software value
-output              pc_sw_wr;      // Program counter software write
-output              scg0;          // System clock generator 1. Turns off the DCO
-output              scg1;          // System clock generator 1. Turns off the SMCLK
-
-// INPUTs
-//=========
-input               dbg_halt_st;   // Halt/Run status from CPU
-input        [15:0] dbg_mem_dout;  // Debug unit data output
-input               dbg_reg_wr;    // Debug unit CPU register write
-input         [3:0] e_state;       // Execution state
-input               exec_done;     // Execution completed
-input         [7:0] inst_ad;       // Decoded Inst: destination addressing mode
-input         [7:0] inst_as;       // Decoded Inst: source addressing mode
-input        [11:0] inst_alu;      // ALU control signals
-input               inst_bw;       // Decoded Inst: byte width
-input        [15:0] inst_dest;     // Decoded Inst: destination (one hot)
-input        [15:0] inst_dext;     // Decoded Inst: destination extended instruction word
-input               inst_irq_rst;  // Decoded Inst: reset interrupt
-input         [7:0] inst_jmp;      // Decoded Inst: Conditional jump
-input               inst_mov;      // Decoded Inst: mov instruction
-input        [15:0] inst_sext;     // Decoded Inst: source extended instruction word
-input         [7:0] inst_so;       // Decoded Inst: Single-operand arithmetic
-input        [15:0] inst_src;      // Decoded Inst: source (one hot)
-input         [2:0] inst_type;     // Decoded Instruction type
-input               mclk;          // Main system clock
-input        [15:0] mdb_in;        // Memory data bus input
-input        [15:0] pc;            // Program counter
-input        [15:0] pc_nxt;        // Next PC value (for CALL & IRQ)
-input               puc_rst;       // Main system reset
-input               scan_enable;   // Scan enable (active during scan shifting)
-
-
-//=============================================================================
-// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
-//=============================================================================
-
-wire         [15:0] alu_out;
-wire         [15:0] alu_out_add;
-wire          [3:0] alu_stat;
-wire          [3:0] alu_stat_wr;
-wire         [15:0] op_dst;
-wire         [15:0] op_src;
-wire         [15:0] reg_dest;
-wire         [15:0] reg_src;
-wire         [15:0] mdb_in_bw;
-wire         [15:0] mdb_in_val;
-wire          [3:0] status;
-
-
-//=============================================================================
-// 2)  REGISTER FILE
-//=============================================================================
-
-wire reg_dest_wr  = ((e_state==4'hB) & (
-                     (inst_type[2] & inst_ad[0] & ~inst_alu[11])  |
-                     (inst_type[0] & inst_as[0] & ~(inst_so[4] | inst_so[5] | inst_so[6])) |
-                      inst_type[1])) | dbg_reg_wr;
-
-wire reg_sp_wr    = (((e_state==4'h1) | (e_state==4'h3)) & ~inst_irq_rst) |
-                     ((e_state==4'h9) & ((inst_so[4] | inst_so[5]) &  ~inst_as[1] & ~((inst_as[2] | inst_as[3]) & inst_src[1]))) |
-                     ((e_state==4'h5) & ((inst_so[4] | inst_so[5]) &  inst_as[1])) |
-                     ((e_state==4'h6) & ((inst_so[4] | inst_so[5]) &  ((inst_as[2] | inst_as[3]) & inst_src[1])));
-
-wire reg_sr_wr    =  (e_state==4'h9) & inst_so[6];
-
-wire reg_sr_clr   =  (e_state==4'h0);
-
-wire reg_pc_call  = ((e_state==4'hB)   & inst_so[5]) | 
-                    ((e_state==4'hA) & inst_so[6]);
-
-wire reg_incr     =  (exec_done          & inst_as[3]) |
-                    ((e_state==4'h6) & inst_so[6])    |
-                    ((e_state==4'hB)   & inst_so[6]);
-
-assign dbg_reg_din = reg_dest;
-
-
-omsp_register_file register_file_0 (
-
-// OUTPUTs
-    .cpuoff       (cpuoff),       // Turns off the CPU
-    .gie          (gie),          // General interrupt enable
-    .oscoff       (oscoff),       // Turns off LFXT1 clock input
-    .pc_sw        (pc_sw),        // Program counter software value
-    .pc_sw_wr     (pc_sw_wr),     // Program counter software write
-    .reg_dest     (reg_dest),     // Selected register destination content
-    .reg_src      (reg_src),      // Selected register source content
-    .scg0         (scg0),         // System clock generator 1. Turns off the DCO
-    .scg1         (scg1),         // System clock generator 1. Turns off the SMCLK
-    .status       (status),       // R2 Status {V,N,Z,C}
-
-// INPUTs
-    .alu_stat     (alu_stat),     // ALU Status {V,N,Z,C}
-    .alu_stat_wr  (alu_stat_wr),  // ALU Status write {V,N,Z,C}
-    .inst_bw      (inst_bw),      // Decoded Inst: byte width
-    .inst_dest    (inst_dest),    // Register destination selection
-    .inst_src     (inst_src),     // Register source selection
-    .mclk         (mclk),         // Main system clock
-    .pc           (pc),           // Program counter
-    .puc_rst      (puc_rst),      // Main system reset
-    .reg_dest_val (alu_out),      // Selected register destination value
-    .reg_dest_wr  (reg_dest_wr),  // Write selected register destination
-    .reg_pc_call  (reg_pc_call),  // Trigger PC update for a CALL instruction
-    .reg_sp_val   (alu_out_add),  // Stack Pointer next value
-    .reg_sp_wr    (reg_sp_wr),    // Stack Pointer write
-    .reg_sr_clr   (reg_sr_clr),   // Status register clear for interrupts
-    .reg_sr_wr    (reg_sr_wr),    // Status Register update for RETI instruction
-    .reg_incr     (reg_incr),     // Increment source register
-    .scan_enable  (scan_enable)   // Scan enable (active during scan shifting)
-);
-
-
-//=============================================================================
-// 3)  SOURCE OPERAND MUXING
-//=============================================================================
-// inst_as[`DIR]    : Register direct.   -> Source is in register
-// inst_as[`IDX]    : Register indexed.  -> Source is in memory, address is register+offset
-// inst_as[`INDIR]  : Register indirect.
-// inst_as[`INDIR_I]: Register indirect autoincrement.
-// inst_as[`SYMB]   : Symbolic (operand is in memory at address PC+x).
-// inst_as[`IMM]    : Immediate (operand is next word in the instruction stream).
-// inst_as[`ABS]    : Absolute (operand is in memory at address x).
-// inst_as[`CONST]  : Constant.
-
-wire src_reg_src_sel    =  (e_state==4'h2)                    |
-                           (e_state==4'h0)                    |
-                          ((e_state==4'h6) & ~inst_as[6]) |
-                          ((e_state==4'h7) & ~inst_as[6]) |
-                          ((e_state==4'hB)   &  inst_as[0] & ~inst_type[1]);
-
-wire src_reg_dest_sel   =  (e_state==4'h1)                    |
-                           (e_state==4'h3)                    |
-                          ((e_state==4'h9) & (inst_so[4] | inst_so[5])) |
-                          ((e_state==4'h5) & (inst_so[4] | inst_so[5]) & inst_as[1]);
-
-wire src_mdb_in_val_sel = ((e_state==4'h9) &  inst_so[6])                     |
-                          ((e_state==4'hB)   & (inst_as[2] | inst_as[3] |
-                                                   inst_as[1]   | inst_as[4]    |
-                                                   inst_as[6]));
-
-wire src_inst_dext_sel =  ((e_state==4'h9) & ~(inst_so[4] | inst_so[5])) |
-                          ((e_state==4'hA) & ~(inst_so[4] | inst_so[5]   |
-                                                    inst_so[6]));
-
-wire src_inst_sext_sel =  ((e_state==4'hB)   &  (inst_type[1] | inst_as[5] |
-                                                    inst_as[7]      | inst_so[6]));
-
-
-assign op_src = src_reg_src_sel     ?  reg_src    :
-                src_reg_dest_sel    ?  reg_dest   :
-                src_mdb_in_val_sel  ?  mdb_in_val :
-                src_inst_dext_sel   ?  inst_dext  :
-                src_inst_sext_sel   ?  inst_sext  : 16'h0000;
-
-
-//=============================================================================
-// 4)  DESTINATION OPERAND MUXING
-//=============================================================================
-// inst_ad[`DIR]    : Register direct.
-// inst_ad[`IDX]    : Register indexed.
-// inst_ad[`SYMB]   : Symbolic (operand is in memory at address PC+x).
-// inst_ad[`ABS]    : Absolute (operand is in memory at address x).
-
-
-wire dst_inst_sext_sel  = ((e_state==4'h6) & (inst_as[1] | inst_as[4] |
-                                                   inst_as[6]))                |
-                          ((e_state==4'h7) & (inst_as[1] | inst_as[4] |
-                                                   inst_as[6]));
-
-wire dst_mdb_in_bw_sel  = ((e_state==4'hA) &   inst_so[6]) |
-                          ((e_state==4'hB)   & ~(inst_ad[0] | inst_type[1] |
-                                                    inst_type[0]) & ~inst_so[6]);
-
-wire dst_fffe_sel       =  (e_state==4'h2)  |
-                           (e_state==4'h1)  |
-                           (e_state==4'h3)  |
-                          ((e_state==4'h9) & (inst_so[4] | inst_so[5]) & ~inst_so[6]) |
-                          ((e_state==4'h5) & (inst_so[4] | inst_so[5]) & inst_as[1]) |
-                          ((e_state==4'h6) & (inst_so[4] | inst_so[5]) & (inst_as[2] | inst_as[3]) & inst_src[1]);
-
-wire dst_reg_dest_sel   = ((e_state==4'h9) & ~(inst_so[4] | inst_so[5] | inst_ad[6] | inst_so[6])) |
-                          ((e_state==4'hA) &  ~inst_ad[6]) |
-                          ((e_state==4'hB)   &  (inst_ad[0] | inst_type[1] |
-                                                    inst_type[0]) & ~inst_so[6]);
-
-
-assign op_dst = dbg_halt_st        ? dbg_mem_dout  :
-                dst_inst_sext_sel  ? inst_sext     :
-                dst_mdb_in_bw_sel  ? mdb_in_bw     :
-                dst_reg_dest_sel   ? reg_dest      :
-                dst_fffe_sel       ? 16'hfffe : 16'h0000;
-
-
-//=============================================================================
-// 5)  ALU
-//=============================================================================
-
-wire exec_cycle = (e_state==4'hB);
-
-omsp_alu alu_0 (
-
-// OUTPUTs
-    .alu_out      (alu_out),      // ALU output value
-    .alu_out_add  (alu_out_add),  // ALU adder output value
-    .alu_stat     (alu_stat),     // ALU Status {V,N,Z,C}
-    .alu_stat_wr  (alu_stat_wr),  // ALU Status write {V,N,Z,C}
-
-// INPUTs
-    .dbg_halt_st  (dbg_halt_st),  // Halt/Run status from CPU
-    .exec_cycle   (exec_cycle),   // Instruction execution cycle
-    .inst_alu     (inst_alu),     // ALU control signals
-    .inst_bw      (inst_bw),      // Decoded Inst: byte width
-    .inst_jmp     (inst_jmp),     // Decoded Inst: Conditional jump
-    .inst_so      (inst_so),      // Single-operand arithmetic
-    .op_dst       (op_dst),       // Destination operand
-    .op_src       (op_src),       // Source operand
-    .status       (status)        // R2 Status {V,N,Z,C}
-);
-
-
-//=============================================================================
-// 6)  MEMORY INTERFACE
-//=============================================================================
-
-// Detect memory read/write access
-wire        mb_rd_det = ((e_state==4'h6) & ~inst_as[5])       |
-                        ((e_state==4'hB)   &  inst_so[6])      |
-                        ((e_state==4'h9) & ~inst_type[0]
-                                              & ~inst_mov);
-
-wire        mb_wr_det = ((e_state==4'h1)  & ~inst_irq_rst)        |
-                        ((e_state==4'h3)  & ~inst_irq_rst)        |
-                        ((e_state==4'hA) & ~inst_so[6])      |
-                         (e_state==4'h7);
-
-wire  [1:0] mb_wr_msk =  inst_alu[11]  ? 2'b00 :
-                        ~inst_bw                ? 2'b11 :
-                         alu_out_add[0]         ? 2'b10 : 2'b01;
-
-assign      mb_en     = mb_rd_det | (mb_wr_det & ~inst_alu[11]);
-
-assign      mb_wr     = ({2{mb_wr_det}}) & mb_wr_msk;
-
-
-
-// Memory address bus
-assign      mab       = alu_out_add[15:0];
-
-// Memory data bus output
-reg  [15:0] mdb_out_nxt;
-
-wire        mclk_mdb_out_nxt = mclk;
-
-always @(posedge mclk_mdb_out_nxt or posedge puc_rst)
-  if (puc_rst)                                        mdb_out_nxt <= 16'h0000;
-  else if (e_state==4'h9)                        mdb_out_nxt <= pc_nxt;
-  else if ((e_state==4'hB & ~inst_so[5]) |
-           (e_state==4'h2) | (e_state==4'h0)) mdb_out_nxt <= alu_out;
-
-assign      mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
-
-// Format memory data bus input depending on BW
-reg        mab_lsb;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)    mab_lsb <= 1'b0;
-  else if (mb_en) mab_lsb <= alu_out_add[0];
-
-assign mdb_in_bw  = ~inst_bw ? mdb_in :
-                     mab_lsb ? {2{mdb_in[15:8]}} : mdb_in;
-
-// Memory data bus input buffer (buffer after a source read)
-reg         mdb_in_buf_en;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)  mdb_in_buf_en <= 1'b0;
-  else          mdb_in_buf_en <= (e_state==4'h6);
-
-reg         mdb_in_buf_valid;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)               mdb_in_buf_valid <= 1'b0;
-  else if (e_state==4'hB) mdb_in_buf_valid <= 1'b0;
-  else if (mdb_in_buf_en)    mdb_in_buf_valid <= 1'b1;
-
-reg  [15:0] mdb_in_buf;
-
-wire        mclk_mdb_in_buf = mclk;
-
-always @(posedge mclk_mdb_in_buf or posedge puc_rst)
-  if (puc_rst)            mdb_in_buf <= 16'h0000;
-  else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
-
-assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
-
-
-endmodule // omsp_execution_unit
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_frontend.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_frontend.v
deleted file mode 100644
index 371c7ff..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_frontend.v
+++ /dev/null
@@ -1,1767 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_frontend.v
-// 
-// *Module Description:
-//                       openMSP430 Instruction fetch and decode unit
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 134 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_frontend (
-
-// OUTPUTs
-    dbg_halt_st,                   // Halt/Run status from CPU
-    decode_noirq,                  // Frontend decode instruction
-    e_state,                       // Execution state
-    exec_done,                     // Execution completed
-    inst_ad,                       // Decoded Inst: destination addressing mode
-    inst_as,                       // Decoded Inst: source addressing mode
-    inst_alu,                      // ALU control signals
-    inst_bw,                       // Decoded Inst: byte width
-    inst_dest,                     // Decoded Inst: destination (one hot)
-    inst_dext,                     // Decoded Inst: destination extended instruction word
-    inst_irq_rst,                  // Decoded Inst: Reset interrupt
-    inst_jmp,                      // Decoded Inst: Conditional jump
-    inst_mov,                      // Decoded Inst: mov instruction
-    inst_sext,                     // Decoded Inst: source extended instruction word
-    inst_so,                       // Decoded Inst: Single-operand arithmetic
-    inst_src,                      // Decoded Inst: source (one hot)
-    inst_type,                     // Decoded Instruction type
-    irq_acc,                       // Interrupt request accepted (one-hot signal)
-    mab,                           // Frontend Memory address bus
-    mb_en,                         // Frontend Memory bus enable
-    mclk_enable,                   // Main System Clock enable
-    mclk_wkup,                     // Main System Clock wake-up (asynchronous)
-    nmi_acc,                       // Non-Maskable interrupt request accepted
-    pc,                            // Program counter
-    pc_nxt,                        // Next PC value (for CALL & IRQ)
-
-// INPUTs
-    cpu_en_s,                      // Enable CPU code execution (synchronous)
-    cpuoff,                        // Turns off the CPU
-    dbg_halt_cmd,                  // Halt CPU command
-    dbg_reg_sel,                   // Debug selected register for rd/wr access
-    fe_pmem_wait,                  // Frontend wait for Instruction fetch
-    gie,                           // General interrupt enable
-    irq,                           // Maskable interrupts
-    mclk,                          // Main system clock
-    mdb_in,                        // Frontend Memory data bus input
-    nmi_pnd,                       // Non-maskable interrupt pending
-    nmi_wkup,                      // NMI Wakeup
-    pc_sw,                         // Program counter software value
-    pc_sw_wr,                      // Program counter software write
-    puc_rst,                       // Main system reset
-    scan_enable,                   // Scan enable (active during scan shifting)
-    wdt_irq,                       // Watchdog-timer interrupt
-    wdt_wkup,                      // Watchdog Wakeup
-    wkup                           // System Wake-up (asynchronous)
-);
-
-// OUTPUTs
-//=========
-output              dbg_halt_st;   // Halt/Run status from CPU
-output              decode_noirq;  // Frontend decode instruction
-output        [3:0] e_state;       // Execution state
-output              exec_done;     // Execution completed
-output        [7:0] inst_ad;       // Decoded Inst: destination addressing mode
-output        [7:0] inst_as;       // Decoded Inst: source addressing mode
-output       [11:0] inst_alu;      // ALU control signals
-output              inst_bw;       // Decoded Inst: byte width
-output       [15:0] inst_dest;     // Decoded Inst: destination (one hot)
-output       [15:0] inst_dext;     // Decoded Inst: destination extended instruction word
-output              inst_irq_rst;  // Decoded Inst: Reset interrupt
-output        [7:0] inst_jmp;      // Decoded Inst: Conditional jump
-output              inst_mov;      // Decoded Inst: mov instruction
-output       [15:0] inst_sext;     // Decoded Inst: source extended instruction word
-output        [7:0] inst_so;       // Decoded Inst: Single-operand arithmetic
-output       [15:0] inst_src;      // Decoded Inst: source (one hot)
-output        [2:0] inst_type;     // Decoded Instruction type
-output       [13:0] irq_acc;       // Interrupt request accepted (one-hot signal)
-output       [15:0] mab;           // Frontend Memory address bus
-output              mb_en;         // Frontend Memory bus enable
-output              mclk_enable;   // Main System Clock enable
-output              mclk_wkup;     // Main System Clock wake-up (asynchronous)
-output              nmi_acc;       // Non-Maskable interrupt request accepted
-output       [15:0] pc;            // Program counter
-output       [15:0] pc_nxt;        // Next PC value (for CALL & IRQ)
-
-// INPUTs
-//=========
-input               cpu_en_s;      // Enable CPU code execution (synchronous)
-input               cpuoff;        // Turns off the CPU
-input               dbg_halt_cmd;  // Halt CPU command
-input         [3:0] dbg_reg_sel;   // Debug selected register for rd/wr access
-input               fe_pmem_wait;  // Frontend wait for Instruction fetch
-input               gie;           // General interrupt enable
-input        [13:0] irq;           // Maskable interrupts
-input               mclk;          // Main system clock
-input        [15:0] mdb_in;        // Frontend Memory data bus input
-input               nmi_pnd;       // Non-maskable interrupt pending
-input               nmi_wkup;      // NMI Wakeup
-input        [15:0] pc_sw;         // Program counter software value
-input               pc_sw_wr;      // Program counter software write
-input               puc_rst;       // Main system reset
-input               scan_enable;   // Scan enable (active during scan shifting)
-input               wdt_irq;       // Watchdog-timer interrupt
-input               wdt_wkup;      // Watchdog Wakeup
-input               wkup;          // System Wake-up (asynchronous)
-
-
-//=============================================================================
-// 1)  UTILITY FUNCTIONS
-//=============================================================================
-
-// 16 bits one-hot decoder
-function [15:0] one_hot16;
-   input  [3:0] binary;
-   begin
-      one_hot16         = 16'h0000;
-      one_hot16[binary] =  1'b1;
-   end
-endfunction
-   
-// 8 bits one-hot decoder
-function [7:0] one_hot8;
-   input  [2:0] binary;
-   begin
-      one_hot8         = 8'h00;
-      one_hot8[binary] = 1'b1;
-   end
-endfunction
-   
-
-//=============================================================================
-// 2)  PARAMETER DEFINITIONS
-//=============================================================================
-
-//
-// 2.1) Instruction State machine definitons
-//-------------------------------------------
-
-parameter I_IRQ_FETCH = 3'h0;
-parameter I_IRQ_DONE  = 3'h1;
-parameter I_DEC       = 3'h2;        // New instruction ready for decode
-parameter I_EXT1      = 3'h3;       // 1st Extension word
-parameter I_EXT2      = 3'h4;       // 2nd Extension word
-parameter I_IDLE      = 3'h5;       // CPU is in IDLE mode
-
-//
-// 2.2) Execution State machine definitons
-//-------------------------------------------
-
-parameter E_IRQ_0     = 4'h2;
-parameter E_IRQ_1     = 4'h1;
-parameter E_IRQ_2     = 4'h0;
-parameter E_IRQ_3     = 4'h3;
-parameter E_IRQ_4     = 4'h4;
-parameter E_SRC_AD    = 4'h5;
-parameter E_SRC_RD    = 4'h6;
-parameter E_SRC_WR    = 4'h7;
-parameter E_DST_AD    = 4'h8;
-parameter E_DST_RD    = 4'h9;
-parameter E_DST_WR    = 4'hA;
-parameter E_EXEC      = 4'hB;
-parameter E_JUMP      = 4'hC;
-parameter E_IDLE      = 4'hD;
-
-
-//=============================================================================
-// 3)  FRONTEND STATE MACHINE
-//=============================================================================
-
-// The wire "conv" is used as state bits to calculate the next response
-reg  [2:0] i_state;
-reg  [2:0] i_state_nxt;
-
-reg  [1:0] inst_sz;
-wire [1:0] inst_sz_nxt;
-wire       irq_detect;
-wire [2:0] inst_type_nxt;
-wire       is_const;
-reg [15:0] sconst_nxt;
-reg  [3:0] e_state_nxt;
-           
-// CPU on/off through the debug interface or cpu_en port
-wire   cpu_halt_cmd = dbg_halt_cmd | ~cpu_en_s;
-   
-// States Transitions
-always @(i_state    or inst_sz  or inst_sz_nxt  or pc_sw_wr or exec_done or
-         irq_detect or cpuoff   or cpu_halt_cmd or e_state)
-    case(i_state)
-      I_IDLE     : i_state_nxt = (irq_detect & ~cpu_halt_cmd) ? I_IRQ_FETCH :
-                                 (~cpuoff    & ~cpu_halt_cmd) ? I_DEC       : I_IDLE;
-      I_IRQ_FETCH: i_state_nxt =  I_IRQ_DONE;
-      I_IRQ_DONE : i_state_nxt =  I_DEC;
-      I_DEC      : i_state_nxt =  irq_detect                  ? I_IRQ_FETCH :
-                          (cpuoff | cpu_halt_cmd) & exec_done ? I_IDLE      :
-                            cpu_halt_cmd & (e_state==E_IDLE)  ? I_IDLE      :
-                                  pc_sw_wr                    ? I_DEC       :
-                             ~exec_done & ~(e_state==E_IDLE)  ? I_DEC       :        // Wait in decode state
-                                  (inst_sz_nxt!=2'b00)        ? I_EXT1      : I_DEC; // until execution is completed
-      I_EXT1     : i_state_nxt =  pc_sw_wr                    ? I_DEC       : 
-                                  (inst_sz!=2'b01)            ? I_EXT2      : I_DEC;
-      I_EXT2     : i_state_nxt =  I_DEC;
-    // pragma coverage off
-      default    : i_state_nxt =  I_IRQ_FETCH;
-    // pragma coverage on
-    endcase
-
-// State machine
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst) i_state  <= I_IRQ_FETCH;
-  else         i_state  <= i_state_nxt;
-
-// Utility signals
-wire   decode_noirq =  ((i_state==I_DEC) &  (exec_done | (e_state==E_IDLE)));
-wire   decode       =  decode_noirq | irq_detect;
-wire   fetch        = ~((i_state==I_DEC) & ~(exec_done | (e_state==E_IDLE))) & ~(e_state_nxt==E_IDLE);
-
-// Debug interface cpu status
-reg    dbg_halt_st;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)  dbg_halt_st <= 1'b0;
-  else          dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE);
-
-
-//=============================================================================
-// 4)  INTERRUPT HANDLING & SYSTEM WAKEUP
-//=============================================================================
-
-//
-// 4.1) INTERRUPT HANDLING
-//-----------------------------------------
-
-// Detect reset interrupt
-reg         inst_irq_rst;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)                  inst_irq_rst <= 1'b1;
-  else if (exec_done)           inst_irq_rst <= 1'b0;
-
-//  Detect other interrupts
-assign  irq_detect = (nmi_pnd | ((|irq | wdt_irq) & gie)) & ~cpu_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
-
-wire       mclk_irq_num = mclk;
-
-// Select interrupt vector
-reg  [3:0] irq_num;
-always @(posedge mclk_irq_num or posedge puc_rst)
-  if (puc_rst)         irq_num <= 4'hf;
-  else if (irq_detect) irq_num <= nmi_pnd            ?  4'he :
-                                  irq[13]            ?  4'hd :
-                                  irq[12]            ?  4'hc :
-                                  irq[11]            ?  4'hb :
-                                 (irq[10] | wdt_irq) ?  4'ha :
-                                  irq[9]             ?  4'h9 :
-                                  irq[8]             ?  4'h8 :
-                                  irq[7]             ?  4'h7 :
-                                  irq[6]             ?  4'h6 :
-                                  irq[5]             ?  4'h5 :
-                                  irq[4]             ?  4'h4 :
-                                  irq[3]             ?  4'h3 :
-                                  irq[2]             ?  4'h2 :
-                                  irq[1]             ?  4'h1 :
-                                  irq[0]             ?  4'h0 : 4'hf;
-
-wire [15:0] irq_addr    = {11'h7ff, irq_num, 1'b0};
-
-// Interrupt request accepted
-wire [15:0] irq_acc_all = one_hot16(irq_num) & {16{(i_state==I_IRQ_FETCH)}};
-wire [13:0] irq_acc     = irq_acc_all[13:0];
-wire        nmi_acc     = irq_acc_all[14];
-
-//
-// 4.2) SYSTEM WAKEUP
-//-----------------------------------------
-
-// In the CPUOFF feature is disabled, the wake-up and enable signals are always 1
-assign  mclk_wkup   = 1'b1;
-assign  mclk_enable = 1'b1;
-
-//=============================================================================
-// 5)  FETCH INSTRUCTION
-//=============================================================================
-
-//
-// 5.1) PROGRAM COUNTER & MEMORY INTERFACE
-//-----------------------------------------
-
-// Program counter
-reg  [15:0] pc;
-
-// Compute next PC value
-wire [15:0] pc_incr = pc + {14'h0000, fetch, 1'b0};
-wire [15:0] pc_nxt  = pc_sw_wr               ? pc_sw    :
-                      (i_state==I_IRQ_FETCH) ? irq_addr :
-                      (i_state==I_IRQ_DONE)  ? mdb_in   :  pc_incr;
-
-wire       mclk_pc = mclk;
-
-always @(posedge mclk_pc or posedge puc_rst)
-  if (puc_rst)  pc <= 16'h0000;
-  else          pc <= pc_nxt;
-
-// Check if ROM has been busy in order to retry ROM access
-reg pmem_busy;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)  pmem_busy <= 1'b0;
-  else          pmem_busy <= fe_pmem_wait;
-   
-// Memory interface
-wire [15:0] mab      = pc_nxt;
-wire        mb_en    = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~cpu_halt_cmd);
-
-
-//
-// 5.2) INSTRUCTION REGISTER
-//--------------------------------
-
-// Instruction register
-wire [15:0] ir  = mdb_in;
-
-// Detect if source extension word is required
-wire is_sext = (inst_as[1] | inst_as[4] | inst_as[6] | inst_as[5]);
-
-// For the Symbolic addressing mode, add -2 to the extension word in order
-// to make up for the PC address
-wire [15:0] ext_incr = ((i_state==I_EXT1)     &  inst_as[4]) |
-                       ((i_state==I_EXT2)     &  inst_ad[4]) |
-                       ((i_state==I_EXT1)     & ~inst_as[4] &
-                       ~(i_state_nxt==I_EXT2) &  inst_ad[4])   ? 16'hfffe : 16'h0000;
-
-wire [15:0] ext_nxt  = ir + ext_incr;
-
-// Store source extension word
-reg [15:0] inst_sext;
-
-wire       mclk_inst_sext = mclk;
-
-always @(posedge mclk_inst_sext or posedge puc_rst)
-  if (puc_rst)                                 inst_sext <= 16'h0000;
-  else if (decode & is_const)                  inst_sext <= sconst_nxt;
-  else if (decode & inst_type_nxt[1])  inst_sext <= {{5{ir[9]}},ir[9:0],1'b0};
-  else if ((i_state==I_EXT1) & is_sext)        inst_sext <= ext_nxt;
-
-// Source extension word is ready
-wire inst_sext_rdy = (i_state==I_EXT1) & is_sext;
-
-
-// Store destination extension word
-reg [15:0] inst_dext;
-
-wire       mclk_inst_dext = mclk;
-
-always @(posedge mclk_inst_dext or posedge puc_rst)
-  if (puc_rst)                           inst_dext <= 16'h0000;
-  else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt;
-  else if  (i_state==I_EXT2)             inst_dext <= ext_nxt;
-
-// Destination extension word is ready
-wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2));
-
-
-//=============================================================================
-// 6)  DECODE INSTRUCTION
-//=============================================================================
-
-wire       mclk_decode = mclk;
-
-//
-// 6.1) OPCODE: INSTRUCTION TYPE
-//----------------------------------------
-// Instructions type is encoded in a one hot fashion as following:
-//
-// 3'b001: Single-operand arithmetic
-// 3'b010: Conditional jump
-// 3'b100: Two-operand arithmetic
-
-reg  [2:0] inst_type;
-assign     inst_type_nxt = {(ir[15:14]!=2'b00),
-                            (ir[15:13]==3'b001),
-                            (ir[15:13]==3'b000)} & {3{~irq_detect}};
-   
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)      inst_type <= 3'b000;
-  else if (decode)  inst_type <= inst_type_nxt;
-
-//
-// 6.2) OPCODE: SINGLE-OPERAND ARITHMETIC
-//----------------------------------------
-// Instructions are encoded in a one hot fashion as following:
-//
-// 8'b00000001: RRC
-// 8'b00000010: SWPB
-// 8'b00000100: RRA
-// 8'b00001000: SXT
-// 8'b00010000: PUSH
-// 8'b00100000: CALL
-// 8'b01000000: RETI
-// 8'b10000000: IRQ
-
-reg   [7:0] inst_so;
-wire  [7:0] inst_so_nxt = irq_detect ? 8'h80 : (one_hot8(ir[9:7]) & {8{inst_type_nxt[0]}});
-
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_so <= 8'h00;
-  else if (decode) inst_so <= inst_so_nxt;
-
-//
-// 6.3) OPCODE: CONDITIONAL JUMP
-//--------------------------------
-// Instructions are encoded in a one hot fashion as following:
-//
-// 8'b00000001: JNE/JNZ
-// 8'b00000010: JEQ/JZ
-// 8'b00000100: JNC/JLO
-// 8'b00001000: JC/JHS
-// 8'b00010000: JN
-// 8'b00100000: JGE
-// 8'b01000000: JL
-// 8'b10000000: JMP
-
-reg   [2:0] inst_jmp_bin;
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_jmp_bin <= 3'h0;
-  else if (decode) inst_jmp_bin <= ir[12:10];
-
-wire [7:0] inst_jmp = one_hot8(inst_jmp_bin) & {8{inst_type[1]}};
-
-
-//
-// 6.4) OPCODE: TWO-OPERAND ARITHMETIC
-//-------------------------------------
-// Instructions are encoded in a one hot fashion as following:
-//
-// 12'b000000000001: MOV
-// 12'b000000000010: ADD
-// 12'b000000000100: ADDC
-// 12'b000000001000: SUBC
-// 12'b000000010000: SUB
-// 12'b000000100000: CMP
-// 12'b000001000000: DADD
-// 12'b000010000000: BIT
-// 12'b000100000000: BIC
-// 12'b001000000000: BIS
-// 12'b010000000000: XOR
-// 12'b100000000000: AND
-
-wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[2]}};
-wire [11:0] inst_to_nxt  = inst_to_1hot[15:4];
-
-reg         inst_mov;
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_mov <= 1'b0;
-  else if (decode) inst_mov <= inst_to_nxt[0];
-
-
-//
-// 6.5) SOURCE AND DESTINATION REGISTERS
-//---------------------------------------
-
-// Destination register
-reg [3:0] inst_dest_bin;
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_dest_bin <= 4'h0;
-  else if (decode) inst_dest_bin <= ir[3:0];
-
-wire  [15:0] inst_dest = dbg_halt_st          ? one_hot16(dbg_reg_sel) :
-                         inst_type[1] ? 16'h0001 :
-                         inst_so[7]  |
-                         inst_so[4] |
-                         inst_so[5]       ? 16'h0002 :
-                                                one_hot16(inst_dest_bin);
-
-
-// Source register
-reg [3:0] inst_src_bin;
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_src_bin <= 4'h0;
-  else if (decode) inst_src_bin <= ir[11:8];
-
-wire  [15:0] inst_src = inst_type[2] ? one_hot16(inst_src_bin)  :
-                        inst_so[6]      ? 16'h0002 :
-                        inst_so[7]       ? 16'h0001 :
-                        inst_type[0] ? one_hot16(inst_dest_bin) : 16'h0000;
-
-
-//
-// 6.6) SOURCE ADDRESSING MODES
-//--------------------------------
-// Source addressing modes are encoded in a one hot fashion as following:
-//
-// 13'b0000000000001: Register direct.
-// 13'b0000000000010: Register indexed.
-// 13'b0000000000100: Register indirect.
-// 13'b0000000001000: Register indirect autoincrement.
-// 13'b0000000010000: Symbolic (operand is in memory at address PC+x).
-// 13'b0000000100000: Immediate (operand is next word in the instruction stream).
-// 13'b0000001000000: Absolute (operand is in memory at address x).
-// 13'b0000010000000: Constant 4.
-// 13'b0000100000000: Constant 8.
-// 13'b0001000000000: Constant 0.
-// 13'b0010000000000: Constant 1.
-// 13'b0100000000000: Constant 2.
-// 13'b1000000000000: Constant -1.
-
-reg [12:0] inst_as_nxt;
-
-wire [3:0] src_reg = inst_type_nxt[0] ? ir[3:0] : ir[11:8];
-
-always @(src_reg or ir or inst_type_nxt)
-  begin
-     if (inst_type_nxt[1])
-       inst_as_nxt =  13'b0000000000001;
-     else if (src_reg==4'h3) // Addressing mode using R3
-       case (ir[5:4])
-         2'b11 : inst_as_nxt =  13'b1000000000000;
-         2'b10 : inst_as_nxt =  13'b0100000000000;
-         2'b01 : inst_as_nxt =  13'b0010000000000;
-         default: inst_as_nxt =  13'b0001000000000;
-       endcase
-     else if (src_reg==4'h2) // Addressing mode using R2
-       case (ir[5:4])
-         2'b11 : inst_as_nxt =  13'b0000100000000;
-         2'b10 : inst_as_nxt =  13'b0000010000000;
-         2'b01 : inst_as_nxt =  13'b0000001000000;
-         default: inst_as_nxt =  13'b0000000000001;
-       endcase
-     else if (src_reg==4'h0) // Addressing mode using R0
-       case (ir[5:4])
-         2'b11 : inst_as_nxt =  13'b0000000100000;
-         2'b10 : inst_as_nxt =  13'b0000000000100;
-         2'b01 : inst_as_nxt =  13'b0000000010000;
-         default: inst_as_nxt =  13'b0000000000001;
-       endcase
-     else                    // General Addressing mode
-       case (ir[5:4])
-         2'b11 : inst_as_nxt =  13'b0000000001000;
-         2'b10 : inst_as_nxt =  13'b0000000000100;
-         2'b01 : inst_as_nxt =  13'b0000000000010;
-         default: inst_as_nxt =  13'b0000000000001;
-       endcase
-  end
-assign    is_const = |inst_as_nxt[12:7];
-
-reg [7:0] inst_as;
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_as <= 8'h00;
-  else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]};
-
-
-// 13'b0000010000000: Constant 4.
-// 13'b0000100000000: Constant 8.
-// 13'b0001000000000: Constant 0.
-// 13'b0010000000000: Constant 1.
-// 13'b0100000000000: Constant 2.
-// 13'b1000000000000: Constant -1.
-always @(inst_as_nxt)
-  begin
-     if (inst_as_nxt[7])        sconst_nxt = 16'h0004;
-     else if (inst_as_nxt[8])   sconst_nxt = 16'h0008;
-     else if (inst_as_nxt[9])   sconst_nxt = 16'h0000;
-     else if (inst_as_nxt[10])  sconst_nxt = 16'h0001;
-     else if (inst_as_nxt[11])  sconst_nxt = 16'h0002;
-     else if (inst_as_nxt[12])  sconst_nxt = 16'hffff;
-     else                       sconst_nxt = 16'h0000;
-  end
-
-
-//
-// 6.7) DESTINATION ADDRESSING MODES
-//-----------------------------------
-// Destination addressing modes are encoded in a one hot fashion as following:
-//
-// 8'b00000001: Register direct.
-// 8'b00000010: Register indexed.
-// 8'b00010000: Symbolic (operand is in memory at address PC+x).
-// 8'b01000000: Absolute (operand is in memory at address x).
-
-reg  [7:0] inst_ad_nxt;
-
-wire [3:0] dest_reg = ir[3:0];
-
-always @(dest_reg or ir or inst_type_nxt)
-  begin
-     if (~inst_type_nxt[2])
-       inst_ad_nxt =  8'b00000000;
-     else if (dest_reg==4'h2)   // Addressing mode using R2
-       case (ir[7])
-         1'b1 : inst_ad_nxt =  8'b01000000;
-         default: inst_ad_nxt =  8'b00000001;
-       endcase
-     else if (dest_reg==4'h0)   // Addressing mode using R0
-       case (ir[7])
-         1'b1 : inst_ad_nxt =  8'b00010000;
-         default: inst_ad_nxt =  8'b00000001;
-       endcase
-     else                       // General Addressing mode
-       case (ir[7])
-         1'b1 : inst_ad_nxt =  8'b00000010;
-         default: inst_ad_nxt =  8'b00000001;
-       endcase
-  end
-
-reg [7:0] inst_ad;
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_ad <= 8'h00;
-  else if (decode) inst_ad <= inst_ad_nxt;
-
-
-//
-// 6.8) REMAINING INSTRUCTION DECODING
-//-------------------------------------
-
-// Operation size
-reg       inst_bw;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)     inst_bw     <= 1'b0;
-  else if (decode) inst_bw     <= ir[6] & ~inst_type_nxt[1] & ~irq_detect & ~cpu_halt_cmd;
-
-// Extended instruction size
-assign    inst_sz_nxt = {1'b0,  (inst_as_nxt[1] | inst_as_nxt[4] | inst_as_nxt[6] | inst_as_nxt[5])} +
-                        {1'b0, ((inst_ad_nxt[1] | inst_ad_nxt[4] | inst_ad_nxt[6]) & ~inst_type_nxt[0])};
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_sz     <= 2'b00;
-  else if (decode) inst_sz     <= inst_sz_nxt;
-
-
-//=============================================================================
-// 7)  EXECUTION-UNIT STATE MACHINE
-//=============================================================================
-
-// State machine registers
-reg  [3:0] e_state;
-
-
-// State machine control signals
-//--------------------------------
-
-wire src_acalc_pre =  inst_as_nxt[1]   | inst_as_nxt[4]    | inst_as_nxt[6];
-wire src_rd_pre    =  inst_as_nxt[2] | inst_as_nxt[3] | inst_as_nxt[5]  | inst_so_nxt[6];
-wire dst_acalc_pre =  inst_ad_nxt[1]   | inst_ad_nxt[4]    | inst_ad_nxt[6];
-wire dst_acalc     =  inst_ad[1]       | inst_ad[4]        | inst_ad[6];
-wire dst_rd_pre    =  inst_ad_nxt[1]   | inst_so_nxt[4]    | inst_so_nxt[5] | inst_so_nxt[6];
-wire dst_rd        =  inst_ad[1]       | inst_so[4]        | inst_so[5]     | inst_so[6];
-
-wire inst_branch   =  (inst_ad_nxt[0] & (ir[3:0]==4'h0)) | inst_type_nxt[1] | inst_so_nxt[6];
-
-reg exec_jmp;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)                   exec_jmp <= 1'b0;
-  else if (inst_branch & decode) exec_jmp <= 1'b1;
-  else if (e_state==E_JUMP)      exec_jmp <= 1'b0;
-
-reg exec_dst_wr;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)                exec_dst_wr <= 1'b0;
-  else if (e_state==E_DST_RD) exec_dst_wr <= 1'b1;
-  else if (e_state==E_DST_WR) exec_dst_wr <= 1'b0;
-
-reg exec_src_wr;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)                                         exec_src_wr <= 1'b0;
-  else if (inst_type[0] & (e_state==E_SRC_RD))  exec_src_wr <= 1'b1;
-  else if ((e_state==E_SRC_WR) || (e_state==E_DST_WR)) exec_src_wr <= 1'b0;
-
-reg exec_dext_rdy;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)                exec_dext_rdy <= 1'b0;
-  else if (e_state==E_DST_RD) exec_dext_rdy <= 1'b0;
-  else if (inst_dext_rdy)     exec_dext_rdy <= 1'b1;
-
-// Execution first state
-wire [3:0] e_first_state = ~dbg_halt_st  & inst_so_nxt[7] ? E_IRQ_0  :
-                            cpu_halt_cmd | (i_state==I_IDLE) ? E_IDLE   :
-                            cpuoff                           ? E_IDLE   :
-                            src_acalc_pre                    ? E_SRC_AD :
-                            src_rd_pre                       ? E_SRC_RD :
-                            dst_acalc_pre                    ? E_DST_AD :
-                            dst_rd_pre                       ? E_DST_RD : E_EXEC;
-
-
-// State machine
-//--------------------------------
-
-// States Transitions
-always @(e_state       or dst_acalc     or dst_rd   or inst_sext_rdy or
-         inst_dext_rdy or exec_dext_rdy or exec_jmp or exec_dst_wr   or
-         e_first_state or exec_src_wr)
-    case(e_state)
-      E_IDLE   : e_state_nxt =  e_first_state;
-      E_IRQ_0  : e_state_nxt =  E_IRQ_1;
-      E_IRQ_1  : e_state_nxt =  E_IRQ_2;
-      E_IRQ_2  : e_state_nxt =  E_IRQ_3;
-      E_IRQ_3  : e_state_nxt =  E_IRQ_4;
-      E_IRQ_4  : e_state_nxt =  E_EXEC;
-
-      E_SRC_AD : e_state_nxt =  inst_sext_rdy     ? E_SRC_RD : E_SRC_AD;
-
-      E_SRC_RD : e_state_nxt =  dst_acalc         ? E_DST_AD : 
-                                 dst_rd           ? E_DST_RD : E_EXEC;
-
-      E_DST_AD : e_state_nxt =  (inst_dext_rdy |
-                                 exec_dext_rdy)   ? E_DST_RD : E_DST_AD;
-
-      E_DST_RD : e_state_nxt =  E_EXEC;
-
-      E_EXEC   : e_state_nxt =  exec_dst_wr       ? E_DST_WR :
-                                exec_jmp          ? E_JUMP   :
-                                exec_src_wr       ? E_SRC_WR : e_first_state;
-
-      E_JUMP   : e_state_nxt =  e_first_state;
-      E_DST_WR : e_state_nxt =  exec_jmp          ? E_JUMP   : e_first_state;
-      E_SRC_WR : e_state_nxt =  e_first_state;
-    // pragma coverage off
-      default  : e_state_nxt =  E_IRQ_0;
-    // pragma coverage on
-    endcase
-
-// State machine
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst) e_state  <= E_IRQ_1;
-  else         e_state  <= e_state_nxt;
-
-
-// Frontend State machine control signals
-//----------------------------------------
-
-wire exec_done = exec_jmp        ? (e_state==E_JUMP)   :
-                 exec_dst_wr     ? (e_state==E_DST_WR) :
-                 exec_src_wr     ? (e_state==E_SRC_WR) : (e_state==E_EXEC);
-
-
-//=============================================================================
-// 8)  EXECUTION-UNIT STATE CONTROL
-//=============================================================================
-
-//
-// 8.1) ALU CONTROL SIGNALS
-//-------------------------------------
-//
-// 12'b000000000001: Enable ALU source inverter
-// 12'b000000000010: Enable Incrementer
-// 12'b000000000100: Enable Incrementer on carry bit
-// 12'b000000001000: Select Adder
-// 12'b000000010000: Select AND
-// 12'b000000100000: Select OR
-// 12'b000001000000: Select XOR
-// 12'b000010000000: Select DADD
-// 12'b000100000000: Update N, Z & C (C=~Z)
-// 12'b001000000000: Update all status bits
-// 12'b010000000000: Update status bit for XOR instruction
-// 12'b100000000000: Don't write to destination
-
-reg  [11:0] inst_alu;
-
-wire        alu_src_inv   = inst_to_nxt[4]  | inst_to_nxt[3] |
-                            inst_to_nxt[5]  | inst_to_nxt[8] ;
-
-wire        alu_inc       = inst_to_nxt[4]  | inst_to_nxt[5];
-
-wire        alu_inc_c     = inst_to_nxt[2] | inst_to_nxt[6] |
-                            inst_to_nxt[3];
-
-wire        alu_add       = inst_to_nxt[1]  | inst_to_nxt[2]       |
-                            inst_to_nxt[4]  | inst_to_nxt[3]       |
-                            inst_to_nxt[5]  | inst_type_nxt[1] |
-                            inst_so_nxt[6];
-
- 
-wire        alu_and       = inst_to_nxt[11]  | inst_to_nxt[8]  |
-                            inst_to_nxt[7];
-
-wire        alu_or        = inst_to_nxt[9];
-
-wire        alu_xor       = inst_to_nxt[10];
-
-wire        alu_dadd      = inst_to_nxt[6];
-
-wire        alu_stat_7    = inst_to_nxt[7]  | inst_to_nxt[11]  |
-                            inst_so_nxt[3];
-
-wire        alu_stat_f    = inst_to_nxt[1]  | inst_to_nxt[2] |
-                            inst_to_nxt[4]  | inst_to_nxt[3] |
-                            inst_to_nxt[5]  | inst_to_nxt[6] |
-                            inst_to_nxt[7]  | inst_to_nxt[10]  |
-                            inst_to_nxt[11]  |
-                            inst_so_nxt[0]  | inst_so_nxt[2]  |
-                            inst_so_nxt[3];
-
-wire        alu_shift     = inst_so_nxt[0]  | inst_so_nxt[2];
-
-wire        exec_no_wr    = inst_to_nxt[5] | inst_to_nxt[7];
-
-wire [11:0] inst_alu_nxt  = {exec_no_wr,
-                             alu_shift,
-                             alu_stat_f,
-                             alu_stat_7,
-                             alu_dadd,
-                             alu_xor,
-                             alu_or,
-                             alu_and,
-                             alu_add,
-                             alu_inc_c,
-                             alu_inc,
-                             alu_src_inv};
-
-always @(posedge mclk_decode or posedge puc_rst)
-  if (puc_rst)     inst_alu <= 12'h000;
-  else if (decode) inst_alu <= inst_alu_nxt;
-
-
-endmodule // omsp_frontend
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_mem_backbone.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_mem_backbone.v
deleted file mode 100644
index 74d327f..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_mem_backbone.v
+++ /dev/null
@@ -1,1174 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_mem_backbone.v
-// 
-// *Module Description:
-//                       Memory interface backbone (decoder + arbiter)
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 151 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2012-07-23 00:24:11 +0200 (Mon, 23 Jul 2012) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_mem_backbone (
-
-// OUTPUTs
-    dbg_mem_din,                    // Debug unit Memory data input
-    dmem_addr,                      // Data Memory address
-    dmem_cen,                       // Data Memory chip enable (low active)
-    dmem_din,                       // Data Memory data input
-    dmem_wen,                       // Data Memory write enable (low active)
-    eu_mdb_in,                      // Execution Unit Memory data bus input
-    fe_mdb_in,                      // Frontend Memory data bus input
-    fe_pmem_wait,                   // Frontend wait for Instruction fetch
-    per_addr,                       // Peripheral address
-    per_din,                        // Peripheral data input
-    per_we,                         // Peripheral write enable (high active)
-    per_en,                         // Peripheral enable (high active)
-    pmem_addr,                      // Program Memory address
-    pmem_cen,                       // Program Memory chip enable (low active)
-    pmem_din,                       // Program Memory data input (optional)
-    pmem_wen,                       // Program Memory write enable (low active) (optional)
-
-// INPUTs
-    dbg_halt_st,                    // Halt/Run status from CPU
-    dbg_mem_addr,                   // Debug address for rd/wr access
-    dbg_mem_dout,                   // Debug unit data output
-    dbg_mem_en,                     // Debug unit memory enable
-    dbg_mem_wr,                     // Debug unit memory write
-    dmem_dout,                      // Data Memory data output
-    eu_mab,                         // Execution Unit Memory address bus
-    eu_mb_en,                       // Execution Unit Memory bus enable
-    eu_mb_wr,                       // Execution Unit Memory bus write transfer
-    eu_mdb_out,                     // Execution Unit Memory data bus output
-    fe_mab,                         // Frontend Memory address bus
-    fe_mb_en,                       // Frontend Memory bus enable
-    mclk,                           // Main system clock
-    per_dout,                       // Peripheral data output
-    pmem_dout,                      // Program Memory data output
-    puc_rst,                        // Main system reset
-    scan_enable                     // Scan enable (active during scan shifting)
-);
-
-// OUTPUTs
-//=========
-output        [15:0] dbg_mem_din;   // Debug unit Memory data input
-output [6-1:0] dmem_addr;     // Data Memory address
-output               dmem_cen;      // Data Memory chip enable (low active)
-output        [15:0] dmem_din;      // Data Memory data input
-output         [1:0] dmem_wen;      // Data Memory write enable (low active)
-output        [15:0] eu_mdb_in;     // Execution Unit Memory data bus input
-output        [15:0] fe_mdb_in;     // Frontend Memory data bus input
-output               fe_pmem_wait;  // Frontend wait for Instruction fetch
-output        [13:0] per_addr;      // Peripheral address
-output        [15:0] per_din;       // Peripheral data input
-output         [1:0] per_we;        // Peripheral write enable (high active)
-output               per_en;        // Peripheral enable (high active)
-output [10-1:0] pmem_addr;     // Program Memory address
-output               pmem_cen;      // Program Memory chip enable (low active)
-output        [15:0] pmem_din;      // Program Memory data input (optional)
-output         [1:0] pmem_wen;      // Program Memory write enable (low active) (optional)
-
-// INPUTs
-//=========
-input                dbg_halt_st;   // Halt/Run status from CPU
-input         [15:0] dbg_mem_addr;  // Debug address for rd/wr access
-input         [15:0] dbg_mem_dout;  // Debug unit data output
-input                dbg_mem_en;    // Debug unit memory enable
-input          [1:0] dbg_mem_wr;    // Debug unit memory write
-input         [15:0] dmem_dout;     // Data Memory data output
-input         [14:0] eu_mab;        // Execution Unit Memory address bus
-input                eu_mb_en;      // Execution Unit Memory bus enable
-input          [1:0] eu_mb_wr;      // Execution Unit Memory bus write transfer
-input         [15:0] eu_mdb_out;    // Execution Unit Memory data bus output
-input         [14:0] fe_mab;        // Frontend Memory address bus
-input                fe_mb_en;      // Frontend Memory bus enable
-input                mclk;          // Main system clock
-input         [15:0] per_dout;      // Peripheral data output
-input         [15:0] pmem_dout;     // Program Memory data output
-input                puc_rst;       // Main system reset
-input                scan_enable;   // Scan enable (active during scan shifting)
-
-
-//=============================================================================
-// 1)  DECODER
-//=============================================================================
-
-// RAM Interface
-//------------------
-
-// Execution unit access
-wire               eu_dmem_cen   = ~(eu_mb_en & (eu_mab>=(512>>1)) &
-                                                (eu_mab<((512+128)>>1)));
-wire        [15:0] eu_dmem_addr  = {1'b0, eu_mab}-(512>>1);
-
-// Debug interface access
-wire               dbg_dmem_cen  = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(512>>1)) &
-                                                  (dbg_mem_addr[15:1]<((512+128)>>1)));
-wire        [15:0] dbg_dmem_addr = {1'b0, dbg_mem_addr[15:1]}-(512>>1);
-
-   
-// RAM Interface
-wire [6-1:0] dmem_addr     = ~dbg_dmem_cen ? dbg_dmem_addr[6-1:0] : eu_dmem_addr[6-1:0];
-wire               dmem_cen      =  dbg_dmem_cen & eu_dmem_cen;
-wire         [1:0] dmem_wen      = ~(dbg_mem_wr | eu_mb_wr);
-wire        [15:0] dmem_din      = ~dbg_dmem_cen ? dbg_mem_dout : eu_mdb_out;
-
-
-// ROM Interface
-//------------------
-parameter          PMEM_OFFSET   = (16'hFFFF-2048+1);
-
-// Execution unit access (only read access are accepted)
-wire               eu_pmem_cen   = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(PMEM_OFFSET>>1)));
-wire        [15:0] eu_pmem_addr  = eu_mab-(PMEM_OFFSET>>1);
-
-// Front-end access
-wire               fe_pmem_cen   = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
-wire        [15:0] fe_pmem_addr  = fe_mab-(PMEM_OFFSET>>1);
-
-// Debug interface access
-wire               dbg_pmem_cen  = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
-wire        [15:0] dbg_pmem_addr = {1'b0, dbg_mem_addr[15:1]}-(PMEM_OFFSET>>1);
-
-   
-// ROM Interface (Execution unit has priority)
-wire [10-1:0] pmem_addr     = ~dbg_pmem_cen ? dbg_pmem_addr[10-1:0] :
-                                   ~eu_pmem_cen  ? eu_pmem_addr[10-1:0]  : fe_pmem_addr[10-1:0];
-wire               pmem_cen      =  fe_pmem_cen & eu_pmem_cen & dbg_pmem_cen;
-wire         [1:0] pmem_wen      = ~dbg_mem_wr;
-wire        [15:0] pmem_din      =  dbg_mem_dout;
-
-wire               fe_pmem_wait  = (~fe_pmem_cen & ~eu_pmem_cen);
-
-
-// Peripherals
-//--------------------
-wire              dbg_per_en   =  dbg_mem_en & (dbg_mem_addr[15:1]<(512>>1));
-wire              eu_per_en    =  eu_mb_en   & (eu_mab<(512>>1));
-
-wire       [15:0] per_din      =  dbg_mem_en ? dbg_mem_dout               : eu_mdb_out;
-wire        [1:0] per_we       =  dbg_mem_en ? dbg_mem_wr                 : eu_mb_wr;
-wire              per_en       =  dbg_mem_en ? dbg_per_en                 : eu_per_en;
-wire [8-1:0] per_addr_mux =  dbg_mem_en ? dbg_mem_addr[8-1+1:1] : eu_mab[8-1:0];
-wire       [14:0] per_addr_ful =  {{15-8{1'b0}}, per_addr_mux};
-wire       [13:0] per_addr     =   per_addr_ful[13:0];
-
-reg   [15:0] per_dout_val;
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)  per_dout_val <= 16'h0000;
-  else          per_dout_val <= per_dout;
-
-
-// Frontend data Mux
-//---------------------------------
-// Whenever the frontend doesn't access the ROM,  backup the data
-
-// Detect whenever the data should be backuped and restored
-reg 	    fe_pmem_cen_dly;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst) fe_pmem_cen_dly <=  1'b0;
-  else         fe_pmem_cen_dly <=  fe_pmem_cen;
-
-wire fe_pmem_save    = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
-wire fe_pmem_restore = (~fe_pmem_cen &  fe_pmem_cen_dly) |  dbg_halt_st;
-
-wire mclk_bckup = mclk;
-   
-reg  [15:0] pmem_dout_bckup;
-always @(posedge mclk_bckup or posedge puc_rst)
-  if (puc_rst)           pmem_dout_bckup     <=  16'h0000;
-  else if (fe_pmem_save) pmem_dout_bckup     <=  pmem_dout;
-
-// Mux between the ROM data and the backup
-reg         pmem_dout_bckup_sel;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)              pmem_dout_bckup_sel <=  1'b0;
-  else if (fe_pmem_save)    pmem_dout_bckup_sel <=  1'b1;
-  else if (fe_pmem_restore) pmem_dout_bckup_sel <=  1'b0;
-    
-assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
-
-
-// Execution-Unit data Mux
-//---------------------------------
-
-// Select between peripherals, RAM and ROM
-reg [1:0] eu_mdb_in_sel;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)  eu_mdb_in_sel <= 2'b00;
-  else          eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
-
-// Mux
-assign      eu_mdb_in      = eu_mdb_in_sel[1] ? pmem_dout    :
-                             eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
-
-// Debug interface  data Mux
-//---------------------------------
-
-// Select between peripherals, RAM and ROM
-reg   [1:0] dbg_mem_din_sel;
-always @(posedge mclk or posedge puc_rst)
-  if (puc_rst)  dbg_mem_din_sel <= 2'b00;
-  else          dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
-
-       
-// Mux
-assign      dbg_mem_din  = dbg_mem_din_sel[1] ? pmem_dout    :
-                           dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
-
-   
-endmodule // omsp_mem_backbone
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_multiplier.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_multiplier.v
deleted file mode 100644
index a9b368a..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_multiplier.v
+++ /dev/null
@@ -1,1247 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_multiplier.v
-// 
-// *Module Description:
-//                       16x16 Hardware multiplier.
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_multiplier (
-
-// OUTPUTs
-    per_dout,                       // Peripheral data output
-
-// INPUTs
-    mclk,                           // Main system clock
-    per_addr,                       // Peripheral address
-    per_din,                        // Peripheral data input
-    per_en,                         // Peripheral enable (high active)
-    per_we,                         // Peripheral write enable (high active)
-    puc_rst,                        // Main system reset
-    scan_enable                     // Scan enable (active during scan shifting)
-);
-
-// OUTPUTs
-//=========
-output       [15:0] per_dout;       // Peripheral data output
-
-// INPUTs
-//=========
-input               mclk;           // Main system clock
-input        [13:0] per_addr;       // Peripheral address
-input        [15:0] per_din;        // Peripheral data input
-input               per_en;         // Peripheral enable (high active)
-input         [1:0] per_we;         // Peripheral write enable (high active)
-input               puc_rst;        // Main system reset
-input               scan_enable;    // Scan enable (active during scan shifting)
-
-
-//=============================================================================
-// 1)  PARAMETER/REGISTERS & WIRE DECLARATION
-//=============================================================================
-
-// Register base address (must be aligned to decoder bit width)
-parameter       [14:0] BASE_ADDR   = 15'h0130;
-
-// Decoder bit width (defines how many bits are considered for address decoding)
-parameter              DEC_WD      =  4;
-
-// Register addresses offset
-parameter [DEC_WD-1:0] OP1_MPY     = 'h0,
-                       OP1_MPYS    = 'h2,
-                       OP1_MAC     = 'h4,
-                       OP1_MACS    = 'h6,
-                       OP2         = 'h8,
-                       RESLO       = 'hA,
-                       RESHI       = 'hC,
-                       SUMEXT      = 'hE;
-
-// Register one-hot decoder utilities
-parameter              DEC_SZ      =  (1 << DEC_WD);
-parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
-
-// Register one-hot decoder
-parameter [DEC_SZ-1:0] OP1_MPY_D   = (BASE_REG << OP1_MPY),
-                       OP1_MPYS_D  = (BASE_REG << OP1_MPYS),
-                       OP1_MAC_D   = (BASE_REG << OP1_MAC),
-                       OP1_MACS_D  = (BASE_REG << OP1_MACS),
-                       OP2_D       = (BASE_REG << OP2),
-                       RESLO_D     = (BASE_REG << RESLO),
-                       RESHI_D     = (BASE_REG << RESHI),
-                       SUMEXT_D    = (BASE_REG << SUMEXT);
-
-
-// Wire pre-declarations
-wire  result_wr;
-wire  result_clr;
-wire  early_read;
-
-
-//============================================================================
-// 2)  REGISTER DECODER
-//============================================================================
-
-// Local register selection
-wire              reg_sel     =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
-
-// Register local address
-wire [DEC_WD-1:0] reg_addr    =  {per_addr[DEC_WD-2:0], 1'b0};
-
-// Register address decode
-wire [DEC_SZ-1:0] reg_dec     =  (OP1_MPY_D   &  {DEC_SZ{(reg_addr == OP1_MPY  )}})  |
-                                 (OP1_MPYS_D  &  {DEC_SZ{(reg_addr == OP1_MPYS )}})  |
-                                 (OP1_MAC_D   &  {DEC_SZ{(reg_addr == OP1_MAC  )}})  |
-                                 (OP1_MACS_D  &  {DEC_SZ{(reg_addr == OP1_MACS )}})  |
-                                 (OP2_D       &  {DEC_SZ{(reg_addr == OP2      )}})  |
-                                 (RESLO_D     &  {DEC_SZ{(reg_addr == RESLO    )}})  |
-                                 (RESHI_D     &  {DEC_SZ{(reg_addr == RESHI    )}})  |
-                                 (SUMEXT_D    &  {DEC_SZ{(reg_addr == SUMEXT   )}});
-		   
-// Read/Write probes
-wire              reg_write   =  |per_we & reg_sel;
-wire              reg_read    = ~|per_we & reg_sel;
-
-// Read/Write vectors
-wire [DEC_SZ-1:0] reg_wr      = reg_dec & {DEC_SZ{reg_write}};
-wire [DEC_SZ-1:0] reg_rd      = reg_dec & {DEC_SZ{reg_read}};
-
-// Masked input data for byte access
-wire       [15:0] per_din_msk =  per_din & {{8{per_we[1]}}, 8'hff};
-
-//============================================================================
-// 3) REGISTERS
-//============================================================================
-
-// OP1 Register
-//-----------------   
-reg  [15:0] op1;
-
-wire        op1_wr = reg_wr[OP1_MPY]  |
-                     reg_wr[OP1_MPYS] |
-                     reg_wr[OP1_MAC]  |
-                     reg_wr[OP1_MACS];
-
-wire        mclk_op1 = mclk;
-
-always @ (posedge mclk_op1 or posedge puc_rst)
-  if (puc_rst)      op1 <=  16'h0000;
-  else if (op1_wr)  op1 <=  per_din_msk;
-
-wire [15:0] op1_rd  = op1;
-
-   
-// OP2 Register
-//-----------------   
-reg  [15:0] op2;
-
-wire        op2_wr = reg_wr[OP2];
-
-wire        mclk_op2 = mclk;
-
-always @ (posedge mclk_op2 or posedge puc_rst)
-  if (puc_rst)      op2 <=  16'h0000;
-  else if (op2_wr)  op2 <=  per_din_msk;
-
-wire [15:0] op2_rd  = op2;
-
-   
-// RESLO Register
-//-----------------   
-reg  [15:0] reslo;
-
-wire [15:0] reslo_nxt;
-wire        reslo_wr = reg_wr[RESLO];
-
-wire        mclk_reslo = mclk;
-
-always @ (posedge mclk_reslo or posedge puc_rst)
-  if (puc_rst)         reslo <=  16'h0000;
-  else if (reslo_wr)   reslo <=  per_din_msk;
-  else if (result_clr) reslo <=  16'h0000;
-  else if (result_wr)  reslo <=  reslo_nxt;
-
-wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
-
-
-// RESHI Register
-//-----------------   
-reg  [15:0] reshi;
-
-wire [15:0] reshi_nxt;
-wire        reshi_wr = reg_wr[RESHI];
-
-wire        mclk_reshi = mclk;
-
-always @ (posedge mclk_reshi or posedge puc_rst)
-  if (puc_rst)         reshi <=  16'h0000;
-  else if (reshi_wr)   reshi <=  per_din_msk;
-  else if (result_clr) reshi <=  16'h0000;
-  else if (result_wr)  reshi <=  reshi_nxt;
-
-wire [15:0] reshi_rd = early_read ? reshi_nxt  : reshi;
-
- 
-// SUMEXT Register
-//-----------------   
-reg  [1:0] sumext_s;
-
-wire [1:0] sumext_s_nxt;
-
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)         sumext_s <=  2'b00;
-  else if (op2_wr)     sumext_s <=  2'b00;
-  else if (result_wr)  sumext_s <=  sumext_s_nxt;
-
-wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt};
-wire [15:0] sumext     = {{14{sumext_s[1]}},     sumext_s};
-wire [15:0] sumext_rd  = early_read ? sumext_nxt : sumext;
-
-
-//============================================================================
-// 4) DATA OUTPUT GENERATION
-//============================================================================
-
-// Data output mux
-wire [15:0] op1_mux    = op1_rd     & {16{reg_rd[OP1_MPY]  |
-                                          reg_rd[OP1_MPYS] |
-                                          reg_rd[OP1_MAC]  |
-                                          reg_rd[OP1_MACS]}};
-wire [15:0] op2_mux    = op2_rd     & {16{reg_rd[OP2]}};
-wire [15:0] reslo_mux  = reslo_rd   & {16{reg_rd[RESLO]}};
-wire [15:0] reshi_mux  = reshi_rd   & {16{reg_rd[RESHI]}};
-wire [15:0] sumext_mux = sumext_rd  & {16{reg_rd[SUMEXT]}};
-
-wire [15:0] per_dout   = op1_mux    |
-                         op2_mux    |
-                         reslo_mux  |
-                         reshi_mux  |
-                         sumext_mux;
-
-
-//============================================================================
-// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
-//============================================================================
-
-// Multiplier configuration
-//--------------------------
-
-// Detect signed mode
-reg sign_sel;
-always @ (posedge mclk_op1 or posedge puc_rst)
-  if (puc_rst)     sign_sel <=  1'b0;
-  else if (op1_wr) sign_sel <=  reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
-
-
-// Detect accumulate mode
-reg acc_sel;
-always @ (posedge mclk_op1 or posedge puc_rst)
-  if (puc_rst)     acc_sel  <=  1'b0;
-  else if (op1_wr) acc_sel  <=  reg_wr[OP1_MAC]  | reg_wr[OP1_MACS];
-
-
-// Detect whenever the RESHI and RESLO registers should be cleared
-assign      result_clr = op2_wr & ~acc_sel;
-
-// Combine RESHI & RESLO 
-wire [31:0] result     = {reshi, reslo};
-
-   
-// 16x16 Multiplier (result computed in 1 clock cycle)
-//-----------------------------------------------------
-  
-// Detect start of a multiplication
-reg [1:0] cycle;
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst) cycle <=  2'b00;
-  else         cycle <=  {cycle[0], op2_wr};
-
-assign result_wr = |cycle;
-
-
-// Expand the operands to support signed & unsigned operations
-wire signed [16:0] op1_xp    = {sign_sel & op1[15], op1};
-wire signed  [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]};
-wire signed  [8:0] op2_lo_xp = {              1'b0, op2[7:0]};
-wire signed  [8:0] op2_xp    = cycle[0] ? op2_hi_xp : op2_lo_xp;
-
-     
-// 17x9 signed multiplication
-wire signed [25:0] product    = op1_xp * op2_xp;
-
-wire        [31:0] product_xp = cycle[0] ? {product[23:0], 8'h00} :
-                                           {{8{sign_sel & product[23]}}, product[23:0]};
-   
-// Accumulate
-wire [32:0] result_nxt  = {1'b0, result} + {1'b0, product_xp[31:0]};
-
-
-// Next register values
-assign reslo_nxt    = result_nxt[15:0];
-assign reshi_nxt    = result_nxt[31:16];
-assign sumext_s_nxt =  sign_sel ? {2{result_nxt[31]}} :
-                                  {1'b0, result_nxt[32] | sumext_s[0]};
-
-// Since the MAC is completed within 2 clock cycle,
-// an early read can happen during the second cycle.
-assign early_read   = cycle[1];
-
-
-
-endmodule // omsp_multiplier
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_register_file.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_register_file.v
deleted file mode 100644
index c24cb0e..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_register_file.v
+++ /dev/null
@@ -1,1336 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_register_file.v
-// 
-// *Module Description:
-//                       openMSP430 Register files
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_register_file (
-
-// OUTPUTs
-    cpuoff,                       // Turns off the CPU
-    gie,                          // General interrupt enable
-    oscoff,                       // Turns off LFXT1 clock input
-    pc_sw,                        // Program counter software value
-    pc_sw_wr,                     // Program counter software write
-    reg_dest,                     // Selected register destination content
-    reg_src,                      // Selected register source content
-    scg0,                         // System clock generator 1. Turns off the DCO
-    scg1,                         // System clock generator 1. Turns off the SMCLK
-    status,                       // R2 Status {V,N,Z,C}
-
-// INPUTs
-    alu_stat,                     // ALU Status {V,N,Z,C}
-    alu_stat_wr,                  // ALU Status write {V,N,Z,C}
-    inst_bw,                      // Decoded Inst: byte width
-    inst_dest,                    // Register destination selection
-    inst_src,                     // Register source selection
-    mclk,                         // Main system clock
-    pc,                           // Program counter
-    puc_rst,                      // Main system reset
-    reg_dest_val,                 // Selected register destination value
-    reg_dest_wr,                  // Write selected register destination
-    reg_pc_call,                  // Trigger PC update for a CALL instruction
-    reg_sp_val,                   // Stack Pointer next value
-    reg_sp_wr,                    // Stack Pointer write
-    reg_sr_wr,                    // Status register update for RETI instruction
-    reg_sr_clr,                   // Status register clear for interrupts
-    reg_incr,                     // Increment source register
-    scan_enable                   // Scan enable (active during scan shifting)
-);
-
-// OUTPUTs
-//=========
-output 	            cpuoff;       // Turns off the CPU
-output 	            gie;          // General interrupt enable
-output 	            oscoff;       // Turns off LFXT1 clock input
-output       [15:0] pc_sw;        // Program counter software value
-output              pc_sw_wr;     // Program counter software write
-output       [15:0] reg_dest;     // Selected register destination content
-output       [15:0] reg_src;      // Selected register source content
-output              scg0;         // System clock generator 1. Turns off the DCO
-output              scg1;         // System clock generator 1. Turns off the SMCLK
-output        [3:0] status;       // R2 Status {V,N,Z,C}
-
-// INPUTs
-//=========
-input         [3:0] alu_stat;     // ALU Status {V,N,Z,C}
-input         [3:0] alu_stat_wr;  // ALU Status write {V,N,Z,C}
-input               inst_bw;      // Decoded Inst: byte width
-input        [15:0] inst_dest;    // Register destination selection
-input        [15:0] inst_src;     // Register source selection
-input               mclk;         // Main system clock
-input        [15:0] pc;           // Program counter
-input               puc_rst;      // Main system reset
-input        [15:0] reg_dest_val; // Selected register destination value
-input               reg_dest_wr;  // Write selected register destination
-input               reg_pc_call;  // Trigger PC update for a CALL instruction
-input        [15:0] reg_sp_val;   // Stack Pointer next value
-input               reg_sp_wr;    // Stack Pointer write
-input               reg_sr_wr;    // Status register update for RETI instruction
-input               reg_sr_clr;   // Status register clear for interrupts
-input               reg_incr;     // Increment source register
-input               scan_enable;  // Scan enable (active during scan shifting)
-
-
-//=============================================================================
-// 1)  AUTOINCREMENT UNIT
-//=============================================================================
-
-wire [15:0] inst_src_in;
-wire [15:0] incr_op         = (inst_bw & ~inst_src_in[1]) ? 16'h0001 : 16'h0002;
-wire [15:0] reg_incr_val    = reg_src+incr_op;
-
-wire [15:0] reg_dest_val_in = inst_bw ? {8'h00,reg_dest_val[7:0]} : reg_dest_val;
-
-
-//=============================================================================
-// 2)  SPECIAL REGISTERS (R1/R2/R3)
-//=============================================================================
-
-// Source input selection mask (for interrupt support)
-//-----------------------------------------------------
-
-assign inst_src_in = reg_sr_clr ? 16'h0004 : inst_src;
-
-
-// R0: Program counter
-//---------------------
-
-wire [15:0] r0       = pc;
-
-wire [15:0] pc_sw    = reg_dest_val_in;
-wire        pc_sw_wr = (inst_dest[0] & reg_dest_wr) | reg_pc_call;
-
-
-// R1: Stack pointer
-//-------------------
-reg [15:0] r1;
-wire       r1_wr  = inst_dest[1] & reg_dest_wr;
-wire       r1_inc = inst_src_in[1]  & reg_incr;
-
-wire       mclk_r1 = mclk;
-
-always @(posedge mclk_r1 or posedge puc_rst)
-  if (puc_rst)        r1 <= 16'h0000;
-  else if (r1_wr)     r1 <= reg_dest_val_in & 16'hfffe;
-  else if (reg_sp_wr) r1 <= reg_sp_val      & 16'hfffe;
-  else if (r1_inc)    r1 <= reg_incr_val    & 16'hfffe;
-
-
-// R2: Status register
-//---------------------
-reg  [15:0] r2;
-wire        r2_wr  = (inst_dest[2] & reg_dest_wr) | reg_sr_wr;
-
-wire        r2_c   = alu_stat_wr[0] ? alu_stat[0]          :
-                     r2_wr          ? reg_dest_val_in[0]   : r2[0];              // C
-
-wire        r2_z   = alu_stat_wr[1] ? alu_stat[1]          :
-                     r2_wr          ? reg_dest_val_in[1]   : r2[1];              // Z
-
-wire        r2_n   = alu_stat_wr[2] ? alu_stat[2]          :
-                     r2_wr          ? reg_dest_val_in[2]   : r2[2];              // N
-
-wire  [7:3] r2_nxt = r2_wr          ? reg_dest_val_in[7:3] : r2[7:3];
-
-wire        r2_v   = alu_stat_wr[3] ? alu_stat[3]          :
-                     r2_wr          ? reg_dest_val_in[8]   : r2[8];              // V
-
-
-wire        mclk_r2 = mclk;
-
-   wire [15:0] cpuoff_mask = 16'h0010; // For the FPGA version: - the CPUOFF mode is emulated
-   wire [15:0] oscoff_mask = 16'h0020; //                       - the SCG1 mode is emulated
-   wire [15:0] scg0_mask   = 16'h0000; //                       - the SCG0 is not supported
-   wire [15:0] scg1_mask   = 16'h0080; //                       - the SCG1 mode is emulated
-   
-   wire [15:0] r2_mask     = cpuoff_mask | oscoff_mask | scg0_mask | scg1_mask | 16'h010f;
- 
-always @(posedge mclk_r2 or posedge puc_rst)
-  if (puc_rst)         r2 <= 16'h0000;
-  else if (reg_sr_clr) r2 <= 16'h0000;
-  else                 r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c} & r2_mask;
-
-assign status = {r2[8], r2[2:0]};
-assign gie    =  r2[3];
-assign cpuoff =  r2[4] | (r2_nxt[4] & r2_wr & cpuoff_mask[4]);
-assign oscoff =  r2[5];
-assign scg0   =  r2[6];
-assign scg1   =  r2[7];
-
-
-// R3: Constant generator
-//-------------------------------------------------------------
-// Note: the auto-increment feature is not implemented for R3
-//       because the @R3+ addressing mode is used for constant
-//       generation (#-1).
-reg [15:0] r3;
-wire       r3_wr  = inst_dest[3] & reg_dest_wr;
-
-wire       mclk_r3 = mclk;
-
-always @(posedge mclk_r3 or posedge puc_rst)
-  if (puc_rst)     r3 <= 16'h0000;
-  else if (r3_wr)  r3 <= reg_dest_val_in;
-
-
-//=============================================================================
-// 4)  GENERAL PURPOSE REGISTERS (R4...R15)
-//=============================================================================
-
-// R4
-//------------
-reg [15:0] r4;
-wire       r4_wr  = inst_dest[4] & reg_dest_wr;
-wire       r4_inc = inst_src_in[4]  & reg_incr;
-
-wire       mclk_r4 = mclk;
-
-always @(posedge mclk_r4 or posedge puc_rst)
-  if (puc_rst)      r4  <= 16'h0000;
-  else if (r4_wr)   r4  <= reg_dest_val_in;
-  else if (r4_inc)  r4  <= reg_incr_val;
-
-// R5
-//------------
-reg [15:0] r5;
-wire       r5_wr  = inst_dest[5] & reg_dest_wr;
-wire       r5_inc = inst_src_in[5]  & reg_incr;
-
-wire       mclk_r5 = mclk;
-
-always @(posedge mclk_r5 or posedge puc_rst)
-  if (puc_rst)      r5  <= 16'h0000;
-  else if (r5_wr)   r5  <= reg_dest_val_in;
-  else if (r5_inc)  r5  <= reg_incr_val;
-
-// R6
-//------------
-reg [15:0] r6;
-wire       r6_wr  = inst_dest[6] & reg_dest_wr;
-wire       r6_inc = inst_src_in[6]  & reg_incr;
-
-wire       mclk_r6 = mclk;
-
-always @(posedge mclk_r6 or posedge puc_rst)
-  if (puc_rst)      r6  <= 16'h0000;
-  else if (r6_wr)   r6  <= reg_dest_val_in;
-  else if (r6_inc)  r6  <= reg_incr_val;
-
-// R7
-//------------
-reg [15:0] r7;
-wire       r7_wr  = inst_dest[7] & reg_dest_wr;
-wire       r7_inc = inst_src_in[7]  & reg_incr;
-
-wire       mclk_r7 = mclk;
-
-always @(posedge mclk_r7 or posedge puc_rst)
-  if (puc_rst)      r7  <= 16'h0000;
-  else if (r7_wr)   r7  <= reg_dest_val_in;
-  else if (r7_inc)  r7  <= reg_incr_val;
-
-// R8
-//------------
-reg [15:0] r8;
-wire       r8_wr  = inst_dest[8] & reg_dest_wr;
-wire       r8_inc = inst_src_in[8]  & reg_incr;
-
-wire       mclk_r8 = mclk;
-
-always @(posedge mclk_r8 or posedge puc_rst)
-  if (puc_rst)      r8  <= 16'h0000;
-  else if (r8_wr)   r8  <= reg_dest_val_in;
-  else if (r8_inc)  r8  <= reg_incr_val;
-
-// R9
-//------------
-reg [15:0] r9;
-wire       r9_wr  = inst_dest[9] & reg_dest_wr;
-wire       r9_inc = inst_src_in[9]  & reg_incr;
-
-wire       mclk_r9 = mclk;
-
-always @(posedge mclk_r9 or posedge puc_rst)
-  if (puc_rst)      r9  <= 16'h0000;
-  else if (r9_wr)   r9  <= reg_dest_val_in;
-  else if (r9_inc)  r9  <= reg_incr_val;
-
-// R10
-//------------
-reg [15:0] r10;
-wire       r10_wr  = inst_dest[10] & reg_dest_wr;
-wire       r10_inc = inst_src_in[10]  & reg_incr;
-
-wire       mclk_r10 = mclk;
-
-always @(posedge mclk_r10 or posedge puc_rst)
-  if (puc_rst)      r10 <= 16'h0000;
-  else if (r10_wr)  r10 <= reg_dest_val_in;
-  else if (r10_inc) r10 <= reg_incr_val;
-
-// R11
-//------------
-reg [15:0] r11;
-wire       r11_wr  = inst_dest[11] & reg_dest_wr;
-wire       r11_inc = inst_src_in[11]  & reg_incr;
-
-wire       mclk_r11 = mclk;
-
-always @(posedge mclk_r11 or posedge puc_rst)
-  if (puc_rst)      r11 <= 16'h0000;
-  else if (r11_wr)  r11 <= reg_dest_val_in;
-  else if (r11_inc) r11 <= reg_incr_val;
-
-// R12
-//------------
-reg [15:0] r12;
-wire       r12_wr  = inst_dest[12] & reg_dest_wr;
-wire       r12_inc = inst_src_in[12]  & reg_incr;
-
-wire       mclk_r12 = mclk;
-
-always @(posedge mclk_r12 or posedge puc_rst)
-  if (puc_rst)      r12 <= 16'h0000;
-  else if (r12_wr)  r12 <= reg_dest_val_in;
-  else if (r12_inc) r12 <= reg_incr_val;
-
-// R13
-//------------
-reg [15:0] r13;
-wire       r13_wr  = inst_dest[13] & reg_dest_wr;
-wire       r13_inc = inst_src_in[13]  & reg_incr;
-
-wire       mclk_r13 = mclk;
-
-always @(posedge mclk_r13 or posedge puc_rst)
-  if (puc_rst)      r13 <= 16'h0000;
-  else if (r13_wr)  r13 <= reg_dest_val_in;
-  else if (r13_inc) r13 <= reg_incr_val;
-
-// R14
-//------------
-reg [15:0] r14;
-wire       r14_wr  = inst_dest[14] & reg_dest_wr;
-wire       r14_inc = inst_src_in[14]  & reg_incr;
-
-wire       mclk_r14 = mclk;
-
-always @(posedge mclk_r14 or posedge puc_rst)
-  if (puc_rst)      r14 <= 16'h0000;
-  else if (r14_wr)  r14 <= reg_dest_val_in;
-  else if (r14_inc) r14 <= reg_incr_val;
-
-// R15
-//------------
-reg [15:0] r15;
-wire       r15_wr  = inst_dest[15] & reg_dest_wr;
-wire       r15_inc = inst_src_in[15]  & reg_incr;
-
-wire       mclk_r15 = mclk;
-
-always @(posedge mclk_r15 or posedge puc_rst)
-  if (puc_rst)      r15 <= 16'h0000;
-  else if (r15_wr)  r15 <= reg_dest_val_in;
-  else if (r15_inc)  r15 <= reg_incr_val;
-
-
-//=============================================================================
-// 5)  READ MUX
-//=============================================================================
-
-assign reg_src  = (r0      & {16{inst_src_in[0]}})   | 
-                  (r1      & {16{inst_src_in[1]}})   | 
-                  (r2      & {16{inst_src_in[2]}})   | 
-                  (r3      & {16{inst_src_in[3]}})   | 
-                  (r4      & {16{inst_src_in[4]}})   | 
-                  (r5      & {16{inst_src_in[5]}})   | 
-                  (r6      & {16{inst_src_in[6]}})   | 
-                  (r7      & {16{inst_src_in[7]}})   | 
-                  (r8      & {16{inst_src_in[8]}})   | 
-                  (r9      & {16{inst_src_in[9]}})   | 
-                  (r10     & {16{inst_src_in[10]}})  | 
-                  (r11     & {16{inst_src_in[11]}})  | 
-                  (r12     & {16{inst_src_in[12]}})  | 
-                  (r13     & {16{inst_src_in[13]}})  | 
-                  (r14     & {16{inst_src_in[14]}})  | 
-                  (r15     & {16{inst_src_in[15]}});
-
-assign reg_dest = (r0      & {16{inst_dest[0]}})  | 
-                  (r1      & {16{inst_dest[1]}})  | 
-                  (r2      & {16{inst_dest[2]}})  | 
-                  (r3      & {16{inst_dest[3]}})  | 
-                  (r4      & {16{inst_dest[4]}})  | 
-                  (r5      & {16{inst_dest[5]}})  | 
-                  (r6      & {16{inst_dest[6]}})  | 
-                  (r7      & {16{inst_dest[7]}})  | 
-                  (r8      & {16{inst_dest[8]}})  | 
-                  (r9      & {16{inst_dest[9]}})  | 
-                  (r10     & {16{inst_dest[10]}}) | 
-                  (r11     & {16{inst_dest[11]}}) | 
-                  (r12     & {16{inst_dest[12]}}) | 
-                  (r13     & {16{inst_dest[13]}}) | 
-                  (r14     & {16{inst_dest[14]}}) | 
-                  (r15     & {16{inst_dest[15]}});
-
-
-endmodule // omsp_register_file
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_scan_mux.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_scan_mux.v
deleted file mode 100644
index 9a90647..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_scan_mux.v
+++ /dev/null
@@ -1,75 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_scan_mux.v
-// 
-// *Module Description:
-//                       Generic mux for scan mode
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 103 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
-//----------------------------------------------------------------------------
-
-module  omsp_scan_mux (
-
-// OUTPUTs
-    data_out,                      // Scan mux data output
-
-// INPUTs
-    data_in_scan,                  // Selected data input for scan mode
-    data_in_func,                  // Selected data input for functional mode
-    scan_mode                      // Scan mode
-);
-
-// OUTPUTs
-//=========
-output              data_out;      // Scan mux data output
-
-// INPUTs
-//=========
-input               data_in_scan;  // Selected data input for scan mode
-input               data_in_func;  // Selected data input for functional mode
-input               scan_mode;     // Scan mode
-
-
-//=============================================================================
-// 1)  SCAN MUX
-//=============================================================================
-
-assign  data_out  =  scan_mode ? data_in_scan : data_in_func;
-
-
-endmodule // omsp_scan_mux
-
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sfr.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sfr.v
deleted file mode 100644
index e063720..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sfr.v
+++ /dev/null
@@ -1,1225 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_sfr.v
-// 
-// *Module Description:
-//                       Processor Special function register
-//                       Non-Maskable Interrupt generation
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_sfr (
-
-// OUTPUTs
-    cpu_id,                       // CPU ID
-    nmi_pnd,                      // NMI Pending
-    nmi_wkup,                     // NMI Wakeup
-    per_dout,                     // Peripheral data output
-    wdtie,                        // Watchdog-timer interrupt enable
-    wdtifg_sw_clr,                // Watchdog-timer interrupt flag software clear
-    wdtifg_sw_set,                // Watchdog-timer interrupt flag software set
-
-// INPUTs
-    cpu_nr_inst,                  // Current oMSP instance number
-    cpu_nr_total,                 // Total number of oMSP instances-1
-    mclk,                         // Main system clock
-    nmi,                          // Non-maskable interrupt (asynchronous)
-    nmi_acc,                      // Non-Maskable interrupt request accepted
-    per_addr,                     // Peripheral address
-    per_din,                      // Peripheral data input
-    per_en,                       // Peripheral enable (high active)
-    per_we,                       // Peripheral write enable (high active)
-    puc_rst,                      // Main system reset
-    scan_mode,                    // Scan mode
-    wdtifg,                       // Watchdog-timer interrupt flag
-    wdtnmies                      // Watchdog-timer NMI edge selection
-);
-
-// OUTPUTs
-//=========
-output       [31:0] cpu_id;       // CPU ID
-output              nmi_pnd;      // NMI Pending
-output              nmi_wkup;     // NMI Wakeup
-output       [15:0] per_dout;     // Peripheral data output
-output              wdtie;        // Watchdog-timer interrupt enable
-output              wdtifg_sw_clr;// Watchdog-timer interrupt flag software clear
-output              wdtifg_sw_set;// Watchdog-timer interrupt flag software set
-
-// INPUTs
-//=========
-input         [7:0] cpu_nr_inst;  // Current oMSP instance number
-input         [7:0] cpu_nr_total; // Total number of oMSP instances-1
-input               mclk;         // Main system clock
-input               nmi;          // Non-maskable interrupt (asynchronous)
-input               nmi_acc;      // Non-Maskable interrupt request accepted
-input        [13:0] per_addr;     // Peripheral address
-input        [15:0] per_din;      // Peripheral data input
-input               per_en;       // Peripheral enable (high active)
-input         [1:0] per_we;       // Peripheral write enable (high active)
-input               puc_rst;      // Main system reset
-input               scan_mode;    // Scan mode
-input               wdtifg;       // Watchdog-timer interrupt flag
-input               wdtnmies;     // Watchdog-timer NMI edge selection
-
-
-//=============================================================================
-// 1)  PARAMETER DECLARATION
-//=============================================================================
-
-// Register base address (must be aligned to decoder bit width)
-parameter       [14:0] BASE_ADDR   = 15'h0000;
-
-// Decoder bit width (defines how many bits are considered for address decoding)
-parameter              DEC_WD      =  4;
-
-// Register addresses offset
-parameter [DEC_WD-1:0] IE1         =  'h0,
-                       IFG1        =  'h2,
-                       CPU_ID_LO   =  'h4,
-                       CPU_ID_HI   =  'h6,
-                       CPU_NR      =  'h8;
-
-// Register one-hot decoder utilities
-parameter              DEC_SZ      =  (1 << DEC_WD);
-parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
-
-// Register one-hot decoder
-parameter [DEC_SZ-1:0] IE1_D       = (BASE_REG << IE1),
-                       IFG1_D      = (BASE_REG << IFG1),
-                       CPU_ID_LO_D = (BASE_REG << CPU_ID_LO),
-                       CPU_ID_HI_D = (BASE_REG << CPU_ID_HI),
-                       CPU_NR_D    = (BASE_REG << CPU_NR);
-
-
-//============================================================================
-// 2)  REGISTER DECODER
-//============================================================================
-
-// Local register selection
-wire              reg_sel      =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
-
-// Register local address
-wire [DEC_WD-1:0] reg_addr     =  {1'b0, per_addr[DEC_WD-2:0]};
-
-// Register address decode
-wire [DEC_SZ-1:0] reg_dec      = (IE1_D        &  {DEC_SZ{(reg_addr==(IE1       >>1))}})  |
-                                 (IFG1_D       &  {DEC_SZ{(reg_addr==(IFG1      >>1))}})  |
-                                 (CPU_ID_LO_D  &  {DEC_SZ{(reg_addr==(CPU_ID_LO >>1))}})  |
-                                 (CPU_ID_HI_D  &  {DEC_SZ{(reg_addr==(CPU_ID_HI >>1))}})  |
-                                 (CPU_NR_D     &  {DEC_SZ{(reg_addr==(CPU_NR    >>1))}});
-
-// Read/Write probes
-wire              reg_lo_write =  per_we[0] & reg_sel;
-wire              reg_hi_write =  per_we[1] & reg_sel;
-wire              reg_read     = ~|per_we   & reg_sel;
-
-// Read/Write vectors
-wire [DEC_SZ-1:0] reg_hi_wr    = reg_dec & {DEC_SZ{reg_hi_write}};
-wire [DEC_SZ-1:0] reg_lo_wr    = reg_dec & {DEC_SZ{reg_lo_write}};
-wire [DEC_SZ-1:0] reg_rd       = reg_dec & {DEC_SZ{reg_read}};
-
-
-//============================================================================
-// 3) REGISTERS
-//============================================================================
-
-// IE1 Register
-//--------------
-wire [7:0] ie1;
-wire       ie1_wr  = IE1[0] ? reg_hi_wr[IE1] : reg_lo_wr[IE1];
-wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8]  : per_din[7:0];
-
-reg        nmie;
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)      nmie  <=  1'b0;
-  else if (nmi_acc) nmie  <=  1'b0; 
-  else if (ie1_wr)  nmie  <=  ie1_nxt[4];    
-
-reg        wdtie;
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)      wdtie <=  1'b0;
-  else if (ie1_wr)  wdtie <=  ie1_nxt[0];    
-
-assign  ie1 = {3'b000, nmie, 3'b000, wdtie};
-
-
-// IFG1 Register
-//---------------
-wire [7:0] ifg1;
-
-wire       ifg1_wr  = IFG1[0] ? reg_hi_wr[IFG1] : reg_lo_wr[IFG1];
-wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8]   : per_din[7:0];
-
-reg        nmiifg;
-wire       nmi_edge;
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)       nmiifg <=  1'b0;
-  else if (nmi_edge) nmiifg <=  1'b1;
-  else if (ifg1_wr)  nmiifg <=  ifg1_nxt[4];
-
-assign  wdtifg_sw_clr = ifg1_wr & ~ifg1_nxt[0];
-assign  wdtifg_sw_set = ifg1_wr &  ifg1_nxt[0];
-
-assign  ifg1 = {3'b000, nmiifg, 3'b000, wdtifg};
-
-
-// CPU_ID Register (READ ONLY)
-//-----------------------------
-//              -------------------------------------------------------------------
-// CPU_ID_LO:  | 15  14  13  12  11  10  9  |  8  7  6  5  4  |  3   |   2  1  0   |
-//             |----------------------------+-----------------+------+-------------|
-//             |        PER_SPACE           |   USER_VERSION  | ASIC | CPU_VERSION |
-//              --------------------------------------------------------------------
-// CPU_ID_HI:  |   15  14  13  12  11  10   |   9  8  7  6  5  4  3  2  1   |   0  |
-//             |----------------------------+-------------------------------+------|
-//             |         PMEM_SIZE          |            DMEM_SIZE          |  MPY |
-//              -------------------------------------------------------------------
-
-wire  [2:0] cpu_version  =  3'h2;
-wire        cpu_asic     =  1'b0;
-wire  [4:0] user_version =  5'b00000;
-wire  [6:0] per_space    = (512  >> 9);  // cpu_id_per  *  512 = peripheral space size
-wire        mpy_info     =  1'b1;
-wire  [8:0] dmem_size    = (128 >> 7);  // cpu_id_dmem *  128 = data memory size
-wire  [5:0] pmem_size    = (2048 >> 10); // cpu_id_pmem * 1024 = program memory size
-
-assign      cpu_id       = {pmem_size,
-			    dmem_size,
-			    mpy_info,
-			    per_space,
-			    user_version,
-			    cpu_asic,
-                            cpu_version};
-
-
-// CPU_NR Register (READ ONLY)
-//-----------------------------
-//    -------------------------------------------------------------------
-//   | 15  14  13  12  11  10   9   8  |  7   6   5   4   3   2   1   0  |
-//   |---------------------------------+---------------------------------|
-//   |            CPU_TOTAL_NR         |           CPU_INST_NR           |
-//    -------------------------------------------------------------------
-
-wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
-
-
-//============================================================================
-// 4) DATA OUTPUT GENERATION
-//============================================================================
-
-// Data output mux
-wire [15:0] ie1_rd        = {8'h00, (ie1  &  {8{reg_rd[IE1]}})}  << (8 & {4{IE1[0]}});
-wire [15:0] ifg1_rd       = {8'h00, (ifg1 &  {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}});
-wire [15:0] cpu_id_lo_rd  = cpu_id[15:0]  & {16{reg_rd[CPU_ID_LO]}};
-wire [15:0] cpu_id_hi_rd  = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
-wire [15:0] cpu_nr_rd     = cpu_nr        & {16{reg_rd[CPU_NR]}};
-
-wire [15:0] per_dout =  ie1_rd       |
-                        ifg1_rd      |
-                        cpu_id_lo_rd |
-                        cpu_id_hi_rd |
-                        cpu_nr_rd;
-
-
-//=============================================================================
-// 5)  NMI GENERATION
-//=============================================================================
-// NOTE THAT THE NMI INPUT IS ASSUMED TO BE NON-GLITCHY
-
-//-----------------------------------
-// Edge selection
-//-----------------------------------
-wire nmi_pol = nmi ^ wdtnmies;
-
-//-----------------------------------
-// Pulse capture and synchronization
-//-----------------------------------
-     wire   nmi_capture = nmi_pol;
-  
-   // Synchronization
-   wire   nmi_s;
-   omsp_sync_cell sync_cell_nmi (
-       .data_out  (nmi_s),
-       .data_in   (nmi_capture),
-       .clk       (mclk),
-       .rst       (puc_rst)
-   );
-
-
-//-----------------------------------
-// NMI Pending flag
-//-----------------------------------
-
-// Delay
-reg  nmi_dly;
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst) nmi_dly <= 1'b0;
-  else         nmi_dly <= nmi_s;
-
-// Edge detection
-assign      nmi_edge  = ~nmi_dly & nmi_s;
-
-// NMI pending
-wire        nmi_pnd   = nmiifg & nmie;
-
-// NMI wakeup
-wire        nmi_wkup  = 1'b0;
-
-
-endmodule // omsp_sfr
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sync_cell.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sync_cell.v
deleted file mode 100644
index ece0682..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sync_cell.v
+++ /dev/null
@@ -1,80 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_sync_cell.v
-// 
-// *Module Description:
-//                       Generic synchronizer for the openMSP430
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 103 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
-//----------------------------------------------------------------------------
-
-module  omsp_sync_cell (
-
-// OUTPUTs
-    data_out,                      // Synchronized data output
-
-// INPUTs
-    clk,                           // Receiving clock
-    data_in,                       // Asynchronous data input
-    rst                            // Receiving reset (active high)
-);
-
-// OUTPUTs
-//=========
-output              data_out;      // Synchronized data output
-
-// INPUTs
-//=========
-input               clk;          // Receiving clock
-input               data_in;      // Asynchronous data input
-input               rst;          // Receiving reset (active high)
-
-
-//=============================================================================
-// 1)  SYNCHRONIZER
-//=============================================================================
-
-reg  [1:0] data_sync;
-
-always @(posedge clk or posedge rst)
-  if (rst) data_sync <=  2'b00;
-  else     data_sync <=  {data_sync[0], data_in};
-
-assign     data_out   =   data_sync[1];
-
-
-endmodule // omsp_sync_cell
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sync_reset.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sync_reset.v
deleted file mode 100644
index 15a158b..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_sync_reset.v
+++ /dev/null
@@ -1,78 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_sync_reset.v
-// 
-// *Module Description:
-//                       Generic reset synchronizer for the openMSP430
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 103 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
-//----------------------------------------------------------------------------
-
-module  omsp_sync_reset (
-
-// OUTPUTs
-    rst_s,                        // Synchronized reset
-
-// INPUTs
-    clk,                          // Receiving clock
-    rst_a                         // Asynchronous reset
-);
-
-// OUTPUTs
-//=========
-output              rst_s;        // Synchronized reset
-
-// INPUTs
-//=========
-input               clk;          // Receiving clock
-input               rst_a;        // Asynchronous reset
-
-
-//=============================================================================
-// 1)  SYNCHRONIZER
-//=============================================================================
-
-reg    [1:0] data_sync;
-
-always @(posedge clk or posedge rst_a)
-  if (rst_a) data_sync <=  2'b11;
-  else       data_sync <=  {data_sync[0], 1'b0};
-
-assign       rst_s      =   data_sync[1];
-
-
-endmodule // omsp_sync_reset
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_wakeup_cell.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_wakeup_cell.v
deleted file mode 100644
index 4e3a64a..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_wakeup_cell.v
+++ /dev/null
@@ -1,1007 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_wakeup_cell.v
-// 
-// *Module Description:
-//                       Generic Wakeup cell
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 103 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_wakeup_cell (
-
-// OUTPUTs
-    wkup_out,                  // Wakup signal (asynchronous)
-
-// INPUTs
-    scan_clk,                  // Scan clock
-    scan_mode,                 // Scan mode
-    scan_rst,                  // Scan reset
-    wkup_clear,                // Glitch free wakeup event clear
-    wkup_event                 // Glitch free asynchronous wakeup event
-);
-
-// OUTPUTs
-//=========
-output         wkup_out;       // Wakup signal (asynchronous)
-
-// INPUTs
-//=========
-input          scan_clk;       // Scan clock
-input          scan_mode;      // Scan mode
-input          scan_rst;       // Scan reset
-input          wkup_clear;     // Glitch free wakeup event clear
-input          wkup_event;     // Glitch free asynchronous wakeup event
-
-
-//=============================================================================
-// 1)  AND GATE
-//=============================================================================
-
-// Scan stuff for the ASIC mode
-   wire wkup_rst  =  wkup_clear;
-   wire wkup_clk  =  wkup_event;
-
-// Wakeup capture
-reg    wkup_out;
-always @(posedge wkup_clk or posedge wkup_rst)
-  if (wkup_rst) wkup_out <= 1'b0;
-  else          wkup_out <= 1'b1;
-
-
-endmodule // omsp_wakeup_cell
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_watchdog.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_watchdog.v
deleted file mode 100644
index e305f1e..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/omsp_watchdog.v
+++ /dev/null
@@ -1,1187 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: omsp_watchdog.v
-// 
-// *Module Description:
-//                       Watchdog Timer
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  omsp_watchdog (
-
-// OUTPUTs
-    per_dout,                       // Peripheral data output
-    wdt_irq,                        // Watchdog-timer interrupt
-    wdt_reset,                      // Watchdog-timer reset
-    wdt_wkup,                       // Watchdog Wakeup
-    wdtifg,                         // Watchdog-timer interrupt flag
-    wdtnmies,                       // Watchdog-timer NMI edge selection
-
-// INPUTs
-    aclk,                           // ACLK
-    aclk_en,                        // ACLK enable
-    dbg_freeze,                     // Freeze Watchdog counter
-    mclk,                           // Main system clock
-    per_addr,                       // Peripheral address
-    per_din,                        // Peripheral data input
-    per_en,                         // Peripheral enable (high active)
-    per_we,                         // Peripheral write enable (high active)
-    por,                            // Power-on reset
-    puc_rst,                        // Main system reset
-    scan_enable,                    // Scan enable (active during scan shifting)
-    scan_mode,                      // Scan mode
-    smclk,                          // SMCLK
-    smclk_en,                       // SMCLK enable
-    wdtie,                          // Watchdog timer interrupt enable
-    wdtifg_irq_clr,                 // Watchdog-timer interrupt flag irq accepted clear
-    wdtifg_sw_clr,                  // Watchdog-timer interrupt flag software clear
-    wdtifg_sw_set                   // Watchdog-timer interrupt flag software set
-);
-
-// OUTPUTs
-//=========
-output       [15:0] per_dout;       // Peripheral data output
-output              wdt_irq;        // Watchdog-timer interrupt
-output              wdt_reset;      // Watchdog-timer reset
-output              wdt_wkup;       // Watchdog Wakeup
-output              wdtifg;         // Watchdog-timer interrupt flag
-output              wdtnmies;       // Watchdog-timer NMI edge selection
-
-// INPUTs
-//=========
-input               aclk;           // ACLK
-input               aclk_en;        // ACLK enable
-input               dbg_freeze;     // Freeze Watchdog counter
-input               mclk;           // Main system clock
-input        [13:0] per_addr;       // Peripheral address
-input        [15:0] per_din;        // Peripheral data input
-input               per_en;         // Peripheral enable (high active)
-input         [1:0] per_we;         // Peripheral write enable (high active)
-input               por;            // Power-on reset
-input               puc_rst;        // Main system reset
-input               scan_enable;    // Scan enable (active during scan shifting)
-input               scan_mode;      // Scan mode
-input               smclk;          // SMCLK
-input               smclk_en;       // SMCLK enable
-input               wdtie;          // Watchdog timer interrupt enable
-input               wdtifg_irq_clr; // Clear Watchdog-timer interrupt flag
-input               wdtifg_sw_clr;  // Watchdog-timer interrupt flag software clear
-input               wdtifg_sw_set;  // Watchdog-timer interrupt flag software set
-
-
-//=============================================================================
-// 1)  PARAMETER DECLARATION
-//=============================================================================
-
-// Register base address (must be aligned to decoder bit width)
-parameter       [14:0] BASE_ADDR   = 15'h0120;
-
-// Decoder bit width (defines how many bits are considered for address decoding)
-parameter              DEC_WD      =  2;
-
-// Register addresses offset
-parameter [DEC_WD-1:0] WDTCTL      = 'h0;
-
-// Register one-hot decoder utilities
-parameter              DEC_SZ      =  (1 << DEC_WD);
-parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
-
-// Register one-hot decoder
-parameter [DEC_SZ-1:0] WDTCTL_D    = (BASE_REG << WDTCTL);
-
-
-//============================================================================
-// 2)  REGISTER DECODER
-//============================================================================
-
-// Local register selection
-wire              reg_sel   =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
-
-// Register local address
-wire [DEC_WD-1:0] reg_addr  =  {per_addr[DEC_WD-2:0], 1'b0};
-
-// Register address decode
-wire [DEC_SZ-1:0] reg_dec   =  (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}});
-
-// Read/Write probes
-wire              reg_write =  |per_we & reg_sel;
-wire              reg_read  = ~|per_we & reg_sel;
-
-// Read/Write vectors
-wire [DEC_SZ-1:0] reg_wr    = reg_dec & {DEC_SZ{reg_write}};
-wire [DEC_SZ-1:0] reg_rd    = reg_dec & {DEC_SZ{reg_read}};
-
-
-//============================================================================
-// 3) REGISTERS
-//============================================================================
-
-// WDTCTL Register
-//-----------------
-// WDTNMI is not implemented and therefore masked
-   
-reg  [7:0] wdtctl;
-
-wire       wdtctl_wr = reg_wr[WDTCTL];
-
-wire       mclk_wdtctl = mclk;
-
-parameter [7:0] WDTNMIES_MASK = 8'h40;
-
-parameter [7:0] WDTSSEL_MASK  = 8'h04;
-
-parameter [7:0] WDTCTL_MASK   = (8'b1001_0011 | WDTSSEL_MASK | WDTNMIES_MASK);
-   
-always @ (posedge mclk_wdtctl or posedge puc_rst)
-  if (puc_rst)        wdtctl <=  8'h00;
-  else if (wdtctl_wr) wdtctl <=  per_din[7:0] & WDTCTL_MASK;
-
-wire       wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
-wire       wdttmsel    = wdtctl[4];
-wire       wdtnmies    = wdtctl[6];
-
-
-//============================================================================
-// 4) DATA OUTPUT GENERATION
-//============================================================================
-
-parameter [7:0] WDTNMI_RD_MASK  = 8'h20;
-  parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
-  parameter [7:0] WDTCTL_RD_MASK  = WDTNMI_RD_MASK | WDTSSEL_RD_MASK;
-
-// Data output mux
-wire [15:0] wdtctl_rd  = {8'h69, wdtctl | WDTCTL_RD_MASK} & {16{reg_rd[WDTCTL]}};
-wire [15:0] per_dout   =  wdtctl_rd;
-
-
-//=============================================================================
-// 5)  WATCHDOG TIMER (ASIC IMPLEMENTATION)
-//=============================================================================
-
-// Watchdog clock source selection
-//---------------------------------
-wire  clk_src_en = wdtctl[2] ? aclk_en : smclk_en;
-
-
-// Watchdog 16 bit counter
-//--------------------------
-reg [15:0] wdtcnt;
-
-wire        wdtifg_evt;
-wire        wdtcnt_clr  = (wdtctl_wr & per_din[3]) | wdtifg_evt;
-wire        wdtcnt_incr = ~wdtctl[7] & clk_src_en & ~dbg_freeze;
-
-wire [15:0] wdtcnt_nxt  = wdtcnt+16'h0001;
-
-always @ (posedge mclk or posedge puc_rst)
-  if (puc_rst)           wdtcnt <= 16'h0000;
-  else if (wdtcnt_clr)   wdtcnt <= 16'h0000;
-  else if (wdtcnt_incr)  wdtcnt <= wdtcnt_nxt;
-
-   
-// Interval selection mux
-//--------------------------
-reg        wdtqn;
-
-always @(wdtctl or wdtcnt_nxt)
-    case(wdtctl[1:0])
-      2'b00 : wdtqn =  wdtcnt_nxt[15];
-      2'b01 : wdtqn =  wdtcnt_nxt[13];
-      2'b10 : wdtqn =  wdtcnt_nxt[9];
-      default: wdtqn =  wdtcnt_nxt[6];
-    endcase
-
-
-// Watchdog event detection
-//-----------------------------
-
-assign     wdtifg_evt =  (wdtqn & wdtcnt_incr) | wdtpw_error;
-
-
-// Watchdog interrupt flag
-//------------------------------
-reg        wdtifg;
-
-wire       wdtifg_set =  wdtifg_evt                  |  wdtifg_sw_set;
-wire       wdtifg_clr =  (wdtifg_irq_clr & wdttmsel) |  wdtifg_sw_clr;
-
-always @ (posedge mclk or posedge por)
-  if (por)             wdtifg <=  1'b0;
-  else if (wdtifg_set) wdtifg <=  1'b1;
-  else if (wdtifg_clr) wdtifg <=  1'b0;
-
-
-// Watchdog interrupt generation
-//---------------------------------
-wire    wdt_irq       = wdttmsel & wdtifg & wdtie;
-wire    wdt_wkup      =  1'b0;
-
-
-// Watchdog reset generation
-//-----------------------------
-reg     wdt_reset;
-
-always @ (posedge mclk or posedge por)
-  if (por) wdt_reset <= 1'b0;
-  else     wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
-
-
-
-
-endmodule // omsp_watchdog
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430.v
deleted file mode 100644
index d6f2d26..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430.v
+++ /dev/null
@@ -1,1494 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-//
-// *File Name: openMSP430.v
-// 
-// *Module Description:
-//                       openMSP430 Top level file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 175 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Wed, 30 Jan 2013) $
-//----------------------------------------------------------------------------
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module  openMSP430 (
-
-// OUTPUTs
-    aclk,                               // ASIC ONLY: ACLK
-    aclk_en,                            // FPGA ONLY: ACLK enable
-    dbg_freeze,                         // Freeze peripherals
-    dbg_i2c_sda_out,                    // Debug interface: I2C SDA OUT
-    dbg_uart_txd,                       // Debug interface: UART TXD
-    dco_enable,                         // ASIC ONLY: Fast oscillator enable
-    dco_wkup,                           // ASIC ONLY: Fast oscillator wake-up (asynchronous)
-    dmem_addr,                          // Data Memory address
-    dmem_cen,                           // Data Memory chip enable (low active)
-    dmem_din,                           // Data Memory data input
-    dmem_wen,                           // Data Memory write enable (low active)
-    irq_acc,                            // Interrupt request accepted (one-hot signal)
-    lfxt_enable,                        // ASIC ONLY: Low frequency oscillator enable
-    lfxt_wkup,                          // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
-    mclk,                               // Main system clock
-    per_addr,                           // Peripheral address
-    per_din,                            // Peripheral data input
-    per_we,                             // Peripheral write enable (high active)
-    per_en,                             // Peripheral enable (high active)
-    pmem_addr,                          // Program Memory address
-    pmem_cen,                           // Program Memory chip enable (low active)
-    pmem_din,                           // Program Memory data input (optional)
-    pmem_wen,                           // Program Memory write enable (low active) (optional)
-    puc_rst,                            // Main system reset
-    smclk,                              // ASIC ONLY: SMCLK
-    smclk_en,                           // FPGA ONLY: SMCLK enable
-
-// INPUTs
-    cpu_en,                             // Enable CPU code execution (asynchronous and non-glitchy)
-    dbg_en,                             // Debug interface enable (asynchronous and non-glitchy)
-    dbg_i2c_addr,                       // Debug interface: I2C Address
-    dbg_i2c_broadcast,                  // Debug interface: I2C Broadcast Address (for multicore systems)
-    dbg_i2c_scl,                        // Debug interface: I2C SCL
-    dbg_i2c_sda_in,                     // Debug interface: I2C SDA IN
-    dbg_uart_rxd,                       // Debug interface: UART RXD (asynchronous)
-    dco_clk,                            // Fast oscillator (fast clock)
-    dmem_dout,                          // Data Memory data output
-    irq,                                // Maskable interrupts
-    lfxt_clk,                           // Low frequency oscillator (typ 32kHz)
-    nmi,                                // Non-maskable interrupt (asynchronous)
-    per_dout,                           // Peripheral data output
-    pmem_dout,                          // Program Memory data output
-    reset_n,                            // Reset Pin (low active, asynchronous and non-glitchy)
-    scan_enable,                        // ASIC ONLY: Scan enable (active during scan shifting)
-    scan_mode,                          // ASIC ONLY: Scan mode
-    wkup                                // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
-);
-
-// PARAMETERs
-//============
-parameter            INST_NR  = 8'h00;  // Current oMSP instance number     (for multicore systems)
-parameter            TOTAL_NR = 8'h00;  // Total number of oMSP instances-1 (for multicore systems)
-
-// OUTPUTs
-//============
-output               aclk;              // ASIC ONLY: ACLK
-output               aclk_en;           // FPGA ONLY: ACLK enable
-output               dbg_freeze;        // Freeze peripherals
-output               dbg_i2c_sda_out;   // Debug interface: I2C SDA OUT
-output               dbg_uart_txd;      // Debug interface: UART TXD
-output               dco_enable;        // ASIC ONLY: Fast oscillator enable
-output               dco_wkup;          // ASIC ONLY: Fast oscillator wake-up (asynchronous)
-output [6-1:0] dmem_addr;         // Data Memory address
-output               dmem_cen;          // Data Memory chip enable (low active)
-output        [15:0] dmem_din;          // Data Memory data input
-output         [1:0] dmem_wen;          // Data Memory write enable (low active)
-output        [13:0] irq_acc;           // Interrupt request accepted (one-hot signal)
-output               lfxt_enable;       // ASIC ONLY: Low frequency oscillator enable
-output               lfxt_wkup;         // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
-output               mclk;              // Main system clock
-output        [13:0] per_addr;          // Peripheral address
-output        [15:0] per_din;           // Peripheral data input
-output         [1:0] per_we;            // Peripheral write enable (high active)
-output               per_en;            // Peripheral enable (high active)
-output [10-1:0] pmem_addr;         // Program Memory address
-output               pmem_cen;          // Program Memory chip enable (low active)
-output        [15:0] pmem_din;          // Program Memory data input (optional)
-output         [1:0] pmem_wen;          // Program Memory write enable (low active) (optional)
-output               puc_rst;           // Main system reset
-output               smclk;             // ASIC ONLY: SMCLK
-output               smclk_en;          // FPGA ONLY: SMCLK enable
-
-
-// INPUTs
-//============
-input                cpu_en;            // Enable CPU code execution (asynchronous and non-glitchy)
-input                dbg_en;            // Debug interface enable (asynchronous and non-glitchy)
-input          [6:0] dbg_i2c_addr;      // Debug interface: I2C Address
-input          [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
-input                dbg_i2c_scl;       // Debug interface: I2C SCL
-input                dbg_i2c_sda_in;    // Debug interface: I2C SDA IN
-input                dbg_uart_rxd;      // Debug interface: UART RXD (asynchronous)
-input                dco_clk;           // Fast oscillator (fast clock)
-input         [15:0] dmem_dout;         // Data Memory data output
-input  	      [13:0] irq;               // Maskable interrupts
-input                lfxt_clk;          // Low frequency oscillator (typ 32kHz)
-input  	             nmi;               // Non-maskable interrupt (asynchronous and non-glitchy)
-input         [15:0] per_dout;          // Peripheral data output
-input         [15:0] pmem_dout;         // Program Memory data output
-input                reset_n;           // Reset Pin (active low, asynchronous and non-glitchy)
-input                scan_enable;       // ASIC ONLY: Scan enable (active during scan shifting)
-input                scan_mode;         // ASIC ONLY: Scan mode
-input                wkup;              // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
-
-
-
-//=============================================================================
-// 1)  INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
-//=============================================================================
-
-wire          [7:0] inst_ad;
-wire          [7:0] inst_as;
-wire         [11:0] inst_alu;
-wire                inst_bw;
-wire                inst_irq_rst;
-wire                inst_mov;
-wire         [15:0] inst_dest;
-wire         [15:0] inst_dext;
-wire         [15:0] inst_sext;
-wire          [7:0] inst_so;
-wire         [15:0] inst_src;
-wire          [2:0] inst_type;
-wire          [7:0] inst_jmp;
-wire          [3:0] e_state;
-wire                exec_done;
-wire                decode_noirq;
-wire                cpu_en_s;
-wire                cpuoff;
-wire                oscoff;
-wire                scg0;
-wire                scg1;
-wire                por;
-wire                gie;
-wire                mclk_enable;
-wire                mclk_wkup;
-wire         [31:0] cpu_id;
-wire          [7:0] cpu_nr_inst  = INST_NR;
-wire          [7:0] cpu_nr_total = TOTAL_NR;
-   
-wire         [15:0] eu_mab;
-wire         [15:0] eu_mdb_in;
-wire         [15:0] eu_mdb_out;
-wire          [1:0] eu_mb_wr;
-wire                eu_mb_en;
-wire         [15:0] fe_mab;
-wire         [15:0] fe_mdb_in;
-wire                fe_mb_en;
-wire                fe_pmem_wait;
-
-wire                pc_sw_wr;
-wire         [15:0] pc_sw;
-wire         [15:0] pc;
-wire         [15:0] pc_nxt;
-
-wire                nmi_acc;
-wire                nmi_pnd;
-wire                nmi_wkup;
-
-wire                wdtie;
-wire                wdtnmies;
-wire                wdtifg;
-wire                wdt_irq;
-wire                wdt_wkup;
-wire                wdt_reset;
-wire                wdtifg_sw_clr;
-wire                wdtifg_sw_set;
-
-wire                dbg_clk;
-wire                dbg_rst;
-wire                dbg_en_s;
-wire                dbg_halt_st;
-wire                dbg_halt_cmd;
-wire                dbg_mem_en;
-wire                dbg_reg_wr;
-wire                dbg_cpu_reset;
-wire         [15:0] dbg_mem_addr;
-wire         [15:0] dbg_mem_dout;
-wire         [15:0] dbg_mem_din;
-wire         [15:0] dbg_reg_din;
-wire          [1:0] dbg_mem_wr;
-wire                puc_pnd_set;
-   
-wire         [15:0] per_dout_or;
-wire         [15:0] per_dout_sfr;
-wire         [15:0] per_dout_wdog;
-wire         [15:0] per_dout_mpy;
-wire         [15:0] per_dout_clk;
-
-   
-//=============================================================================
-// 2)  GLOBAL CLOCK & RESET MANAGEMENT
-//=============================================================================
-
-omsp_clock_module clock_module_0 (
-
-// OUTPUTs
-    .aclk         (aclk),          // ACLK
-    .aclk_en      (aclk_en),       // ACLK enablex
-    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
-    .dbg_clk      (dbg_clk),       // Debug unit clock
-    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
-    .dbg_rst      (dbg_rst),       // Debug unit reset
-    .dco_enable   (dco_enable),    // Fast oscillator enable
-    .dco_wkup     (dco_wkup),      // Fast oscillator wake-up (asynchronous)
-    .lfxt_enable  (lfxt_enable),   // Low frequency oscillator enable
-    .lfxt_wkup    (lfxt_wkup),     // Low frequency oscillator wake-up (asynchronous)
-    .mclk         (mclk),          // Main system clock
-    .per_dout     (per_dout_clk),  // Peripheral data output
-    .por          (por),           // Power-on reset
-    .puc_pnd_set  (puc_pnd_set),   // PUC pending set for the serial debug interface
-    .puc_rst      (puc_rst),       // Main system reset
-    .smclk        (smclk),         // SMCLK
-    .smclk_en     (smclk_en),      // SMCLK enable
-	     
-// INPUTs
-    .cpu_en       (cpu_en),        // Enable CPU code execution (asynchronous)
-    .cpuoff       (cpuoff),        // Turns off the CPU
-    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
-    .dbg_en       (dbg_en),        // Debug interface enable (asynchronous)
-    .dco_clk      (dco_clk),       // Fast oscillator (fast clock)
-    .lfxt_clk     (lfxt_clk),      // Low frequency oscillator (typ 32kHz)
-    .mclk_enable  (mclk_enable),   // Main System Clock enable
-    .mclk_wkup    (mclk_wkup),     // Main System Clock wake-up (asynchronous)
-    .oscoff       (oscoff),        // Turns off LFXT1 clock input
-    .per_addr     (per_addr),      // Peripheral address
-    .per_din      (per_din),       // Peripheral data input
-    .per_en       (per_en),        // Peripheral enable (high active)
-    .per_we       (per_we),        // Peripheral write enable (high active)
-    .reset_n      (reset_n),       // Reset Pin (low active, asynchronous)
-    .scan_enable  (scan_enable),   // Scan enable (active during scan shifting)
-    .scan_mode    (scan_mode),     // Scan mode
-    .scg0         (scg0),          // System clock generator 1. Turns off the DCO
-    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
-    .wdt_reset    (wdt_reset)      // Watchdog-timer reset
-);
-
-   
-//=============================================================================
-// 3)  FRONTEND (<=> FETCH & DECODE)
-//=============================================================================
-
-omsp_frontend frontend_0 (
-
-// OUTPUTs
-    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
-    .decode_noirq (decode_noirq),  // Frontend decode instruction
-    .e_state      (e_state),       // Execution state
-    .exec_done    (exec_done),     // Execution completed
-    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
-    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
-    .inst_alu     (inst_alu),      // ALU control signals
-    .inst_bw      (inst_bw),       // Decoded Inst: byte width
-    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
-    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
-    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: Reset interrupt
-    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
-    .inst_mov     (inst_mov),      // Decoded Inst: mov instruction
-    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
-    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
-    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
-    .inst_type    (inst_type),     // Decoded Instruction type
-    .irq_acc      (irq_acc),       // Interrupt request accepted
-    .mab          (fe_mab),        // Frontend Memory address bus
-    .mb_en        (fe_mb_en),      // Frontend Memory bus enable
-    .mclk_enable  (mclk_enable),   // Main System Clock enable
-    .mclk_wkup    (mclk_wkup),     // Main System Clock wake-up (asynchronous)
-    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
-    .pc           (pc),            // Program counter
-    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
-			     
-// INPUTs
-    .cpu_en_s     (cpu_en_s),      // Enable CPU code execution (synchronous)
-    .cpuoff       (cpuoff),        // Turns off the CPU
-    .dbg_halt_cmd (dbg_halt_cmd),  // Halt CPU command
-    .dbg_reg_sel  (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
-    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
-    .gie          (gie),           // General interrupt enable
-    .irq          (irq),           // Maskable interrupts
-    .mclk         (mclk),          // Main system clock
-    .mdb_in       (fe_mdb_in),     // Frontend Memory data bus input
-    .nmi_pnd      (nmi_pnd),       // Non-maskable interrupt pending
-    .nmi_wkup     (nmi_wkup),      // NMI Wakeup
-    .pc_sw        (pc_sw),         // Program counter software value
-    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
-    .puc_rst      (puc_rst),       // Main system reset
-    .scan_enable  (scan_enable),   // Scan enable (active during scan shifting)
-    .wdt_irq      (wdt_irq),       // Watchdog-timer interrupt
-    .wdt_wkup     (wdt_wkup),      // Watchdog Wakeup
-    .wkup         (wkup)           // System Wake-up (asynchronous)
-);
-
-
-//=============================================================================
-// 4)  EXECUTION UNIT
-//=============================================================================
-
-omsp_execution_unit execution_unit_0 (
-
-// OUTPUTs
-    .cpuoff       (cpuoff),        // Turns off the CPU
-    .dbg_reg_din  (dbg_reg_din),   // Debug unit CPU register data input
-    .mab          (eu_mab),        // Memory address bus
-    .mb_en        (eu_mb_en),      // Memory bus enable
-    .mb_wr        (eu_mb_wr),      // Memory bus write transfer
-    .mdb_out      (eu_mdb_out),    // Memory data bus output
-    .oscoff       (oscoff),        // Turns off LFXT1 clock input
-    .pc_sw        (pc_sw),         // Program counter software value
-    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
-    .scg0         (scg0),          // System clock generator 1. Turns off the DCO
-    .scg1         (scg1),          // System clock generator 1. Turns off the SMCLK
-
-// INPUTs
-    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
-    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
-    .dbg_reg_wr   (dbg_reg_wr),    // Debug unit CPU register write
-    .e_state      (e_state),       // Execution state
-    .exec_done    (exec_done),     // Execution completed
-    .gie          (gie),           // General interrupt enable
-    .inst_ad      (inst_ad),       // Decoded Inst: destination addressing mode
-    .inst_as      (inst_as),       // Decoded Inst: source addressing mode
-    .inst_alu     (inst_alu),      // ALU control signals
-    .inst_bw      (inst_bw),       // Decoded Inst: byte width
-    .inst_dest    (inst_dest),     // Decoded Inst: destination (one hot)
-    .inst_dext    (inst_dext),     // Decoded Inst: destination extended instruction word
-    .inst_irq_rst (inst_irq_rst),  // Decoded Inst: reset interrupt
-    .inst_jmp     (inst_jmp),      // Decoded Inst: Conditional jump
-    .inst_mov     (inst_mov),      // Decoded Inst: mov instruction
-    .inst_sext    (inst_sext),     // Decoded Inst: source extended instruction word
-    .inst_so      (inst_so),       // Decoded Inst: Single-operand arithmetic
-    .inst_src     (inst_src),      // Decoded Inst: source (one hot)
-    .inst_type    (inst_type),     // Decoded Instruction type
-    .mclk         (mclk),          // Main system clock
-    .mdb_in       (eu_mdb_in),     // Memory data bus input
-    .pc           (pc),            // Program counter
-    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
-    .puc_rst      (puc_rst),       // Main system reset
-    .scan_enable  (scan_enable)    // Scan enable (active during scan shifting)
-);
-
-
-//=============================================================================
-// 5)  MEMORY BACKBONE
-//=============================================================================
-
-omsp_mem_backbone mem_backbone_0 (
-
-// OUTPUTs
-    .dbg_mem_din  (dbg_mem_din),   // Debug unit Memory data input
-    .dmem_addr    (dmem_addr),     // Data Memory address
-    .dmem_cen     (dmem_cen),      // Data Memory chip enable (low active)
-    .dmem_din     (dmem_din),      // Data Memory data input
-    .dmem_wen     (dmem_wen),      // Data Memory write enable (low active)
-    .eu_mdb_in    (eu_mdb_in),     // Execution Unit Memory data bus input
-    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
-    .fe_pmem_wait (fe_pmem_wait),  // Frontend wait for Instruction fetch
-    .per_addr     (per_addr),      // Peripheral address
-    .per_din      (per_din),       // Peripheral data input
-    .per_we       (per_we),        // Peripheral write enable (high active)
-    .per_en       (per_en),        // Peripheral enable (high active)
-    .pmem_addr    (pmem_addr),     // Program Memory address
-    .pmem_cen     (pmem_cen),      // Program Memory chip enable (low active)
-    .pmem_din     (pmem_din),      // Program Memory data input (optional)
-    .pmem_wen     (pmem_wen),      // Program Memory write enable (low active) (optional)
-			     
-// INPUTs
-    .dbg_halt_st  (dbg_halt_st),   // Halt/Run status from CPU
-    .dbg_mem_addr (dbg_mem_addr),  // Debug address for rd/wr access
-    .dbg_mem_dout (dbg_mem_dout),  // Debug unit data output
-    .dbg_mem_en   (dbg_mem_en),    // Debug unit memory enable
-    .dbg_mem_wr   (dbg_mem_wr),    // Debug unit memory write
-    .dmem_dout    (dmem_dout),     // Data Memory data output
-    .eu_mab       (eu_mab[15:1]),  // Execution Unit Memory address bus
-    .eu_mb_en     (eu_mb_en),      // Execution Unit Memory bus enable
-    .eu_mb_wr     (eu_mb_wr),      // Execution Unit Memory bus write transfer
-    .eu_mdb_out   (eu_mdb_out),    // Execution Unit Memory data bus output
-    .fe_mab       (fe_mab[15:1]),  // Frontend Memory address bus
-    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
-    .mclk         (mclk),          // Main system clock
-    .per_dout     (per_dout_or),   // Peripheral data output
-    .pmem_dout    (pmem_dout),     // Program Memory data output
-    .puc_rst      (puc_rst),       // Main system reset
-    .scan_enable  (scan_enable)    // Scan enable (active during scan shifting)
-);
-
-
-//=============================================================================
-// 6)  SPECIAL FUNCTION REGISTERS
-//=============================================================================
-omsp_sfr sfr_0 (
-
-// OUTPUTs
-    .cpu_id       (cpu_id),        // CPU ID
-    .nmi_pnd      (nmi_pnd),       // NMI Pending
-    .nmi_wkup     (nmi_wkup),      // NMI Wakeup
-    .per_dout     (per_dout_sfr),  // Peripheral data output
-    .wdtie        (wdtie),         // Watchdog-timer interrupt enable
-    .wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
-    .wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
-			     
-// INPUTs
-    .cpu_nr_inst  (cpu_nr_inst),   // Current oMSP instance number
-    .cpu_nr_total (cpu_nr_total),  // Total number of oMSP instances-1
-    .mclk         (mclk),          // Main system clock
-    .nmi          (nmi),           // Non-maskable interrupt (asynchronous)
-    .nmi_acc      (nmi_acc),       // Non-Maskable interrupt request accepted
-    .per_addr     (per_addr),      // Peripheral address
-    .per_din      (per_din),       // Peripheral data input
-    .per_en       (per_en),        // Peripheral enable (high active)
-    .per_we       (per_we),        // Peripheral write enable (high active)
-    .puc_rst      (puc_rst),       // Main system reset
-    .scan_mode    (scan_mode),     // Scan mode
-    .wdtifg       (wdtifg),        // Watchdog-timer interrupt flag
-    .wdtnmies     (wdtnmies)       // Watchdog-timer NMI edge selection
-);
-
-
-//=============================================================================
-// 7)  WATCHDOG TIMER
-//=============================================================================
-omsp_watchdog watchdog_0 (
-
-// OUTPUTs
-    .per_dout       (per_dout_wdog), // Peripheral data output
-    .wdt_irq        (wdt_irq),       // Watchdog-timer interrupt
-    .wdt_reset      (wdt_reset),     // Watchdog-timer reset
-    .wdt_wkup       (wdt_wkup),      // Watchdog Wakeup
-    .wdtifg         (wdtifg),        // Watchdog-timer interrupt flag
-    .wdtnmies       (wdtnmies),      // Watchdog-timer NMI edge selection
-			     
-// INPUTs
-    .aclk           (aclk),          // ACLK
-    .aclk_en        (aclk_en),       // ACLK enable
-    .dbg_freeze     (dbg_freeze),    // Freeze Watchdog counter
-    .mclk           (mclk),          // Main system clock
-    .per_addr       (per_addr),      // Peripheral address
-    .per_din        (per_din),       // Peripheral data input
-    .per_en         (per_en),        // Peripheral enable (high active)
-    .per_we         (per_we),        // Peripheral write enable (high active)
-    .por            (por),           // Power-on reset
-    .puc_rst        (puc_rst),       // Main system reset
-    .scan_enable    (scan_enable),   // Scan enable (active during scan shifting)
-    .scan_mode      (scan_mode),     // Scan mode
-    .smclk          (smclk),         // SMCLK
-    .smclk_en       (smclk_en),      // SMCLK enable
-    .wdtie          (wdtie),         // Watchdog-timer interrupt enable
-    .wdtifg_irq_clr (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
-    .wdtifg_sw_clr  (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
-    .wdtifg_sw_set  (wdtifg_sw_set)  // Watchdog-timer interrupt flag software set
-);
-
-
-//=============================================================================
-// 8)  HARDWARE MULTIPLIER
-//=============================================================================
-omsp_multiplier multiplier_0 (
-
-// OUTPUTs
-    .per_dout     (per_dout_mpy),  // Peripheral data output
-			     
-// INPUTs
-    .mclk         (mclk),          // Main system clock
-    .per_addr     (per_addr),      // Peripheral address
-    .per_din      (per_din),       // Peripheral data input
-    .per_en       (per_en),        // Peripheral enable (high active)
-    .per_we       (per_we),        // Peripheral write enable (high active)
-    .puc_rst      (puc_rst),       // Main system reset
-    .scan_enable  (scan_enable)    // Scan enable (active during scan shifting)
-);
-   
-//=============================================================================
-// 9)  PERIPHERALS' OUTPUT BUS
-//=============================================================================
-
-assign  per_dout_or  =  per_dout      |
-                        per_dout_clk  |
-                        per_dout_sfr  |
-                        per_dout_wdog |
-                        per_dout_mpy;
-
-   
-//=============================================================================
-// 10)  DEBUG INTERFACE
-//=============================================================================
-
-omsp_dbg dbg_0 (
-
-// OUTPUTs
-    .dbg_cpu_reset     (dbg_cpu_reset),     // Reset CPU from debug interface
-    .dbg_freeze        (dbg_freeze),        // Freeze peripherals
-    .dbg_halt_cmd      (dbg_halt_cmd),      // Halt CPU command
-    .dbg_i2c_sda_out   (dbg_i2c_sda_out),   // Debug interface: I2C SDA OUT
-    .dbg_mem_addr      (dbg_mem_addr),      // Debug address for rd/wr access
-    .dbg_mem_dout      (dbg_mem_dout),      // Debug unit data output
-    .dbg_mem_en        (dbg_mem_en),        // Debug unit memory enable
-    .dbg_mem_wr        (dbg_mem_wr),        // Debug unit memory write
-    .dbg_reg_wr        (dbg_reg_wr),        // Debug unit CPU register write
-    .dbg_uart_txd      (dbg_uart_txd),      // Debug interface: UART TXD
-			     
-// INPUTs
-    .cpu_en_s          (cpu_en_s),          // Enable CPU code execution (synchronous)
-    .cpu_id            (cpu_id),            // CPU ID
-    .cpu_nr_inst       (cpu_nr_inst),       // Current oMSP instance number
-    .cpu_nr_total      (cpu_nr_total),      // Total number of oMSP instances-1
-    .dbg_clk           (dbg_clk),           // Debug unit clock
-    .dbg_en_s          (dbg_en_s),          // Debug interface enable (synchronous)
-    .dbg_halt_st       (dbg_halt_st),       // Halt/Run status from CPU
-    .dbg_i2c_addr      (dbg_i2c_addr),      // Debug interface: I2C Address
-    .dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
-    .dbg_i2c_scl       (dbg_i2c_scl),       // Debug interface: I2C SCL
-    .dbg_i2c_sda_in    (dbg_i2c_sda_in),    // Debug interface: I2C SDA IN
-    .dbg_mem_din       (dbg_mem_din),       // Debug unit Memory data input
-    .dbg_reg_din       (dbg_reg_din),       // Debug unit CPU register data input
-    .dbg_rst           (dbg_rst),           // Debug unit reset
-    .dbg_uart_rxd      (dbg_uart_rxd),      // Debug interface: UART RXD (asynchronous)
-    .decode_noirq      (decode_noirq),      // Frontend decode instruction
-    .eu_mab            (eu_mab),            // Execution-Unit Memory address bus
-    .eu_mb_en          (eu_mb_en),          // Execution-Unit Memory bus enable
-    .eu_mb_wr          (eu_mb_wr),          // Execution-Unit Memory bus write transfer
-    .fe_mdb_in         (fe_mdb_in),         // Frontend Memory data bus input
-    .pc                (pc),                // Program counter
-    .puc_pnd_set       (puc_pnd_set)        // PUC pending set for the serial debug interface
-);
-
-
-   
-endmodule // openMSP430
-
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-
-// Data Memory sizes
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include Debug interface
-
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-
-// Include/Exclude Watchdog timer
-
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-
-// Input synchronizers
-
-
-// Peripheral Memory Space:
-
-
-// Let the CPU break after a PUC occurrence by default
-
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-
-
-// Data Memory Size
-
-
-
-// Peripheral Memory Size
-
-
-
-// Data Memory Base Adresses
-
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-
-
-
-// Instructions type
-
-
-
-
-// Single-operand arithmetic
-
-
-
-
-
-
-
-
-
-// Conditional jump
-
-
-
-
-
-
-
-
-
-// Two-operand arithmetic
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Addressing modes
-
-
-
-
-
-
-
-
-
-// Instruction state machine
-
-
-
-
-
-
-
-// Execution state machine
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// ALU control signals
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Debug interface
-
-
-
-
-// Debug interface CPU_CTL register
-
-
-
-
-
-
-
-
-// Debug interface CPU_STAT register
-
-
-
-
-
-
-// Debug interface BRKx_CTL register
-
-
-
-
-
-
-
-// Basic clock module: BCSCTL1 Control Register
-
-
-// Basic clock module: BCSCTL2 Control Register
-
-
-
-
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-
-// Debug interface: Software breakpoint opcode
-
-
-// Debug UART interface auto data synchronization
-
-
-// Debug UART interface data rate
-
-
-
-
-// Debug interface input synchronizer
-
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-
-// Counter width for the debug interface UART
-
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430_defines.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430_defines.v
deleted file mode 100644
index c3f098c..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430_defines.v
+++ /dev/null
@@ -1,594 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
\ No newline at end of file
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430_undefines.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430_undefines.v
deleted file mode 100644
index 41c3220..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/rtl/openMSP430_undefines.v
+++ /dev/null
@@ -1,201 +0,0 @@
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/sim/bench.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/sim/bench.v
deleted file mode 100644
index 4060008..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/sim/bench.v
+++ /dev/null
@@ -1,939 +0,0 @@
-
-`timescale 1ns/1ps
-
-// for memory layout
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_defines.v
-// 
-// *Module Description:
-//                      openMSP430 Configuration file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 180 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
-//----------------------------------------------------------------------------
-//`define OMSP_NO_INCLUDE
-//----------------------------------------------------------------------------
-// Copyright (C) 2009 , Olivier Girard
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//     * Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in the
-//       documentation and/or other materials provided with the distribution.
-//     * Neither the name of the authors nor the names of its contributors
-//       may be used to endorse or promote products derived from this software
-//       without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-// THE POSSIBILITY OF SUCH DAMAGE
-//
-//----------------------------------------------------------------------------
-// 
-// *File Name: openMSP430_undefines.v
-// 
-// *Module Description:
-//                      openMSP430 Verilog `undef file
-//
-// *Author(s):
-//              - Olivier Girard,    olgirard@gmail.com
-//
-//----------------------------------------------------------------------------
-// $Rev: 23 $
-// $LastChangedBy: olivier.girard $
-// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
-//----------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------
-// BASIC SYSTEM CONFIGURATION
-//----------------------------------------------------------------------------
-
-// Program Memory sizes
-
-// Data Memory sizes
-
-// Include/Exclude Hardware Multiplier
-
-// Include Debug interface
-
-
-//----------------------------------------------------------------------------
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//----------------------------------------------------------------------------
-
-// Custom user version number
-
-// Include/Exclude Watchdog timer
-
-// Include/Exclude Non-Maskable-Interrupt support
-
-// Input synchronizers
-
-// Peripheral Memory Space:
-
-// Let the CPU break after a PUC occurrence by default
-
-
-//----------------------------------------------------------------------------
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// Serial Debug interface protocol
-
-// Enable the I2C broadcast address
-
-// Number of hardware breakpoint units
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Custom Program/Data and Peripheral Memory Spaces
-
-
-
-
-
-
-
-// ASIC version
-
-
-//----------------------------------------------------------------------------
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//----------------------------------------------------------------------------
-
-// ASIC/FPGA-like clocking
-
-// Fine grained clock gating
-
-// LFXT clock domain
-
-// MCLK: Clock Mux
-
-// SMCLK: Clock Mux
-
-// WATCHDOG: Clock Mux
-
-// MCLK: Clock divider
-
-// SMCLK: Clock divider (/1/2/4/8)
-
-// ACLK: Clock divider (/1/2/4/8)
-
-// LOW POWER MODE: CPUOFF
-
-// LOW POWER MODE: SCG0
-
-// LOW POWER MODE: SCG1
-
-// LOW POWER MODE: OSCOFF
-
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-// Program Memory Size
-
-// Data Memory Size
-
-// Peripheral Memory Size
-
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-
-// Debug UART interface data rate
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
-
-// Counter width for the debug interface UART
-
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-
-//============================================================================
-//============================================================================
-// BASIC SYSTEM CONFIGURATION
-//============================================================================
-//============================================================================
-//
-// Note: the sum of program, data and peripheral memory spaces must not
-//      exceed 64 kB
-//
-
-// Program Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define PMEM_SIZE_CUSTOM
-//`define PMEM_SIZE_59_KB
-//`define PMEM_SIZE_55_KB
-//`define PMEM_SIZE_54_KB
-//`define PMEM_SIZE_51_KB
-//`define PMEM_SIZE_48_KB
-//`define PMEM_SIZE_41_KB
-//`define PMEM_SIZE_32_KB
-//`define PMEM_SIZE_24_KB
-//`define PMEM_SIZE_16_KB
-//`define PMEM_SIZE_12_KB
-//`define PMEM_SIZE_8_KB
-//`define PMEM_SIZE_4_KB
-//`define PMEM_SIZE_1_KB
-
-
-// Data Memory Size:
-//                     Uncomment the required memory size
-//-------------------------------------------------------
-//`define DMEM_SIZE_CUSTOM
-//`define DMEM_SIZE_32_KB
-//`define DMEM_SIZE_24_KB
-//`define DMEM_SIZE_16_KB
-//`define DMEM_SIZE_10_KB
-//`define DMEM_SIZE_8_KB
-//`define DMEM_SIZE_5_KB
-//`define DMEM_SIZE_4_KB
-//`define DMEM_SIZE_2p5_KB
-//`define DMEM_SIZE_2_KB
-//`define DMEM_SIZE_1_KB
-//`define DMEM_SIZE_512_B
-//`define DMEM_SIZE_256_B
-
-
-// Include/Exclude Hardware Multiplier
-
-
-// Include/Exclude Serial Debug interface
-
-
-//============================================================================
-//============================================================================
-// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
-//============================================================================
-//============================================================================
-
-//-------------------------------------------------------
-// Custom user version number
-//-------------------------------------------------------
-// This 5 bit field can be freely used in order to allow
-// custom identification of the system through the debug
-// interface.
-// (see CPU_ID.USER_VERSION field in the documentation)
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Watchdog timer
-//-------------------------------------------------------
-// When excluded, the following functionality will be
-// lost:
-//        - Watchog (both interval and watchdog modes)
-//        - NMI interrupt edge selection
-//        - Possibility to generate a software PUC reset
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Include/Exclude Non-Maskable-Interrupt support
-//-------------------------------------------------------
-
-
-//-------------------------------------------------------
-// Input synchronizers
-//-------------------------------------------------------
-// In some cases, the asynchronous input ports might
-// already be synchronized externally.
-// If an extensive CDC design review showed that this
-// is really the case,  the individual synchronizers
-// can be disabled with the following defines.
-//
-// Notes:
-//        - all three signals are all sampled in the MCLK domain
-//
-//        - the dbg_en signal reset the debug interface
-//         when 0. Therefore make sure it is glitch free.
-//
-//-------------------------------------------------------
-//`define SYNC_CPU_EN
-//`define SYNC_DBG_EN
-
-
-//-------------------------------------------------------
-// Peripheral Memory Space:
-//-------------------------------------------------------
-// The original MSP430 architecture map the peripherals
-// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
-// The following defines allow you to expand this space
-// up to 32 kB (i.e. from 0x0000 to 0x7fff).
-// As a consequence, the data memory mapping will be
-// shifted up and a custom linker script will therefore
-// be required by the GCC compiler.
-//-------------------------------------------------------
-//`define PER_SIZE_CUSTOM
-//`define PER_SIZE_32_KB
-//`define PER_SIZE_16_KB
-//`define PER_SIZE_8_KB
-//`define PER_SIZE_4_KB
-//`define PER_SIZE_2_KB
-//`define PER_SIZE_1_KB
-
-
-//-------------------------------------------------------
-// Defines the debugger CPU_CTL.RST_BRK_EN reset value
-// (CPU break on PUC reset)
-//-------------------------------------------------------
-// When defined, the CPU will automatically break after
-// a PUC occurrence by default. This is typically useful
-// when the program memory can only be initialized through
-// the serial debug interface.
-//-------------------------------------------------------
-
-
-//============================================================================
-//============================================================================
-// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
-//============================================================================
-//============================================================================
-//
-// IMPORTANT NOTE:  Please update following configuration options ONLY if
-//                 you have a good reason to do so... and if you know what
-//                 you are doing :-P
-//
-//============================================================================
-
-//-------------------------------------------------------
-// Select serial debug interface protocol
-//-------------------------------------------------------
-//    DBG_UART -> Enable UART (8N1) debug interface
-//    DBG_I2C  -> Enable I2C debug interface
-//-------------------------------------------------------
-//`define DBG_I2C
-
-
-//-------------------------------------------------------
-// Enable the I2C broadcast address
-//-------------------------------------------------------
-// For multicore systems, a common I2C broadcast address
-// can be given to all oMSP cores in order to
-// synchronously RESET, START, STOP, or STEP all CPUs
-// at once with a single I2C command.
-// If you have a single openMSP430 in your system,
-// this option can stay commented-out.
-//-------------------------------------------------------
-//`define DBG_I2C_BROADCAST
-
-
-//-------------------------------------------------------
-// Number of hardware breakpoint/watchpoint units
-// (each unit contains two hardware addresses available
-// for breakpoints or watchpoints):
-//   - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
-//   - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
-//   - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
-//   - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
-//-------------------------------------------------------
-// Please keep in mind that hardware breakpoints only
-// make sense whenever the program memory is not an SRAM
-// (i.e. Flash/OTP/ROM/...) or when you are interested
-// in data breakpoints.
-//-------------------------------------------------------
-//`define  DBG_HWBRK_0
-//`define  DBG_HWBRK_1
-//`define  DBG_HWBRK_2
-//`define  DBG_HWBRK_3
-
-
-//-------------------------------------------------------
-// Enable/Disable the hardware breakpoint RANGE mode
-//-------------------------------------------------------
-// When enabled this feature allows the hardware breakpoint
-// units to stop the cpu whenever an instruction or data
-// access lays within an address range.
-// Note that this feature is not supported by GDB.
-//-------------------------------------------------------
-//`define DBG_HWBRK_RANGE
-
-
-//-------------------------------------------------------
-// Custom Program/Data and Peripheral Memory Spaces
-//-------------------------------------------------------
-// The following values are valid only if the
-// corresponding *_SIZE_CUSTOM defines are uncommented:
-//
-//  - *_SIZE   : size of the section in bytes.
-//  - *_AWIDTH : address port width, this value must allow
-//               to address all WORDS of the section
-//               (i.e. the *_SIZE divided by 2)
-//-------------------------------------------------------
-
-// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
-
-// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)
-
-// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)
-
-
-//-------------------------------------------------------
-// ASIC version
-//-------------------------------------------------------
-// When uncommented, this define will enable the
-// ASIC system configuration section (see below) and
-// will activate scan support for production test.
-//
-// WARNING: if you target an FPGA, leave this define
-//          commented.
-//-------------------------------------------------------
-//`define ASIC
-
-
-//============================================================================
-//============================================================================
-// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
-//============================================================================
-//============================================================================
-
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-//==========================================================================//
-
-//
-// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
-//==================================================
-
-// Program Memory Size
-    
-// Data Memory Size
-    
-// Peripheral Memory Size
-    
-// Data Memory Base Adresses
-
-// Program & Data Memory most significant address bit (for 16 bit words)
-
-//
-// STATES, REGISTER FIELDS, ...
-//======================================
-
-// Instructions type
-
-// Single-operand arithmetic
-
-// Conditional jump
-
-// Two-operand arithmetic
-
-// Addressing modes
-
-// Instruction state machine
-
-// Execution state machine
-// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
-
-// ALU control signals
-
-// Debug interface
-
-// Debug interface CPU_CTL register
-
-// Debug interface CPU_STAT register
-
-// Debug interface BRKx_CTL register
-
-// Basic clock module: BCSCTL1 Control Register
-
-// Basic clock module: BCSCTL2 Control Register
-
-// MCLK Clock gate
-
-// SMCLK Clock gate
-
-//
-// DEBUG INTERFACE EXTRA CONFIGURATION
-//======================================
-
-// Debug interface: CPU version
-
-// Debug interface: Software breakpoint opcode
-
-// Debug UART interface auto data synchronization
-// If the following define is commented out, then
-// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
-// defined.
-
-// Debug UART interface data rate
-//      In order to properly setup the UART debug interface, you
-//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
-//      the chosen BAUD rate from the UART interface.
-//
-//`define DBG_UART_BAUD    9600
-//`define DBG_UART_BAUD   19200
-//`define DBG_UART_BAUD   38400
-//`define DBG_UART_BAUD   57600
-//`define DBG_UART_BAUD  115200
-//`define DBG_UART_BAUD  230400
-//`define DBG_UART_BAUD  460800
-//`define DBG_UART_BAUD  576000
-//`define DBG_UART_BAUD  921600
-
-// Debug interface input synchronizer
-
-// Enable/Disable the hardware breakpoint RANGE mode
- 
-// Counter width for the debug interface UART
-
-// Check configuration
-     
-//
-// MULTIPLIER CONFIGURATION
-//======================================
-
-// If uncommented, the following define selects
-// the 16x16 multiplier (1 cycle) instead of the
-// default 16x8 multplier (2 cycles)
-//`define MPY_16x16
-  
-//======================================
-// CONFIGURATION CHECKS
-//======================================
-        
-module testbench;
-
-// UUT OUTPUTs
-//============
-wire               aclk;              // ASIC ONLY: ACLK
-wire               aclk_en;           // FPGA ONLY: ACLK enable
-wire               dbg_freeze;        // Freeze peripherals
-wire               dbg_i2c_sda_out;   // Debug interface: I2C SDA OUT
-wire               dbg_uart_txd;      // Debug interface: UART TXD
-wire               dco_enable;        // ASIC ONLY: Fast oscillator enable
-wire               dco_wkup;          // ASIC ONLY: Fast oscillator wake-up (asynchronous)
-wire [6-1:0] dmem_addr;         // Data Memory address
-wire               dmem_cen;          // Data Memory chip enable (low active)
-wire        [15:0] dmem_din;          // Data Memory data input
-wire         [1:0] dmem_wen;          // Data Memory write enable (low active)
-wire        [13:0] irq_acc;           // Interrupt request accepted (one-hot signal)
-wire               lfxt_enable;       // ASIC ONLY: Low frequency oscillator enable
-wire               lfxt_wkup;         // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
-wire               mclk;              // Main system clock
-wire        [13:0] per_addr;          // Peripheral address
-wire        [15:0] per_din;           // Peripheral data input
-wire         [1:0] per_we;            // Peripheral write enable (high active)
-wire               per_en;            // Peripheral enable (high active)
-wire [10-1:0] pmem_addr;         // Program Memory address
-wire               pmem_cen;          // Program Memory chip enable (low active)
-wire        [15:0] pmem_din;          // Program Memory data input (optional)
-wire         [1:0] pmem_wen;          // Program Memory write enable (low active) (optional)
-wire               puc_rst;           // Main system reset
-wire               smclk;             // ASIC ONLY: SMCLK
-wire               smclk_en;          // FPGA ONLY: SMCLK enable
-
-
-// UUT INPUTs
-//===========
-wire                cpu_en;            // Enable CPU code execution (asynchronous and non-glitchy)
-wire                dbg_en;            // Debug interface enable (asynchronous and non-glitchy)
-wire          [6:0] dbg_i2c_addr;      // Debug interface: I2C Address
-wire          [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
-wire                dbg_i2c_scl;       // Debug interface: I2C SCL
-wire                dbg_i2c_sda_in;    // Debug interface: I2C SDA IN
-wire                dbg_uart_rxd;      // Debug interface: UART RXD (asynchronous)
-wire                dco_clk;           // Fast oscillator (fast clock)
-reg          [15:0] dmem_dout;         // Data Memory data output
-wire  	     [13:0] irq;               // Maskable interrupts
-wire                lfxt_clk;          // Low frequency oscillator (typ 32kHz)
-wire  	            nmi;               // Non-maskable interrupt (asynchronous and non-glitchy)
-reg          [15:0] per_dout;          // Peripheral data output
-reg          [15:0] pmem_dout;         // Program Memory data output
-wire                reset_n;           // Reset Pin (active low, asynchronous and non-glitchy)
-wire                scan_enable;       // ASIC ONLY: Scan enable (active during scan shifting)
-wire                scan_mode;         // ASIC ONLY: Scan mode
-wire                wkup;              // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
-
-openMSP430 UUT (
-
-// OUTPUTs
-    aclk,                               // ASIC ONLY: ACLK
-    aclk_en,                            // FPGA ONLY: ACLK enable
-    dbg_freeze,                         // Freeze peripherals
-    dbg_i2c_sda_out,                    // Debug interface: I2C SDA OUT
-    dbg_uart_txd,                       // Debug interface: UART TXD
-    dco_enable,                         // ASIC ONLY: Fast oscillator enable
-    dco_wkup,                           // ASIC ONLY: Fast oscillator wake-up (asynchronous)
-    dmem_addr,                          // Data Memory address
-    dmem_cen,                           // Data Memory chip enable (low active)
-    dmem_din,                           // Data Memory data input
-    dmem_wen,                           // Data Memory write enable (low active)
-    irq_acc,                            // Interrupt request accepted (one-hot signal)
-    lfxt_enable,                        // ASIC ONLY: Low frequency oscillator enable
-    lfxt_wkup,                          // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
-    mclk,                               // Main system clock
-    per_addr,                           // Peripheral address
-    per_din,                            // Peripheral data input
-    per_we,                             // Peripheral write enable (high active)
-    per_en,                             // Peripheral enable (high active)
-    pmem_addr,                          // Program Memory address
-    pmem_cen,                           // Program Memory chip enable (low active)
-    pmem_din,                           // Program Memory data input (optional)
-    pmem_wen,                           // Program Memory write enable (low active) (optional)
-    puc_rst,                            // Main system reset
-    smclk,                              // ASIC ONLY: SMCLK
-    smclk_en,                           // FPGA ONLY: SMCLK enable
-
-// INPUTs
-    cpu_en,                             // Enable CPU code execution (asynchronous and non-glitchy)
-    dbg_en,                             // Debug interface enable (asynchronous and non-glitchy)
-    dbg_i2c_addr,                       // Debug interface: I2C Address
-    dbg_i2c_broadcast,                  // Debug interface: I2C Broadcast Address (for multicore systems)
-    dbg_i2c_scl,                        // Debug interface: I2C SCL
-    dbg_i2c_sda_in,                     // Debug interface: I2C SDA IN
-    dbg_uart_rxd,                       // Debug interface: UART RXD (asynchronous)
-    dco_clk,                            // Fast oscillator (fast clock)
-    dmem_dout,                          // Data Memory data output
-    irq,                                // Maskable interrupts
-    lfxt_clk,                           // Low frequency oscillator (typ 32kHz)
-    nmi,                                // Non-maskable interrupt (asynchronous)
-    per_dout,                           // Peripheral data output
-    pmem_dout,                          // Program Memory data output
-    reset_n,                            // Reset Pin (low active, asynchronous and non-glitchy)
-    scan_enable,                        // ASIC ONLY: Scan enable (active during scan shifting)
-    scan_mode,                          // ASIC ONLY: Scan mode
-    wkup                                // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
-);
-
-// -----------------------------------------------------------------------------------
-
-assign cpu_en = 1, dbg_en = 0;
-
-reg clk, rst;
-integer cycles;
-initial begin
-	clk <= 1;
-	rst <= 0;
-	cycles = 0;
-	while (cycles < 8) begin
-		#50; clk <= ~clk;
-		cycles = cycles + 1;
-		#50; clk <= ~clk;
-	end
-	rst <= #20 1;
-	forever begin
-		#50; clk <= ~clk;
-		cycles = cycles + 1;
-		#50; clk <= ~clk;
-		if (cycles == 20000)
-			$finish;
-	end
-end
-
-assign dco_clk = clk;
-assign lfxt_clk = 0;
-assign irq = 0, nmi = 0;
-assign reset_n = rst;
-assign scan_enable = 0;
-assign scan_mode = 0;
-assign wkup = 0;
-
-assign dbg_i2c_addr = 45;
-assign dbg_i2c_broadcast = 67;
-assign dbg_i2c_scl = 0;
-assign dbg_i2c_sda_in = 0;
-assign dbg_uart_rxd = 0;
-
-// -----------------------------------------------------------------------------------
-
-reg [15:0] addr;
-
-reg [15:8] dmem_hi [128/2-1:0];
-reg [ 7:0] dmem_lo [128/2-1:0];
-reg [15:0] pmem    [2048/2-1:0];
-
-integer output_idx;
-reg [15:0] output_buf [1023:0];
-event output_eof;
-
-integer i;
-initial begin
-	for (i = 0; i < 128/2; i=i+1) begin
-		dmem_hi[i] = 0;
-		dmem_lo[i] = 0;
-	end
-	pmem[ 512] = 16'h4031;
-pmem[ 513] = 16'h0280;
-pmem[ 514] = 16'h4215;
-pmem[ 515] = 16'h0120;
-pmem[ 516] = 16'hf375;
-pmem[ 517] = 16'hd035;
-pmem[ 518] = 16'h5a08;
-pmem[ 519] = 16'h403f;
-pmem[ 520] = 16'h0000;
-pmem[ 521] = 16'h930f;
-pmem[ 522] = 16'h2407;
-pmem[ 523] = 16'h4582;
-pmem[ 524] = 16'h0120;
-pmem[ 525] = 16'h832f;
-pmem[ 526] = 16'h4f9f;
-pmem[ 527] = 16'hfccc;
-pmem[ 528] = 16'h0200;
-pmem[ 529] = 16'h23f9;
-pmem[ 530] = 16'h403f;
-pmem[ 531] = 16'h0008;
-pmem[ 532] = 16'h930f;
-pmem[ 533] = 16'h2406;
-pmem[ 534] = 16'h4582;
-pmem[ 535] = 16'h0120;
-pmem[ 536] = 16'h831f;
-pmem[ 537] = 16'h43cf;
-pmem[ 538] = 16'h0200;
-pmem[ 539] = 16'h23fa;
-pmem[ 540] = 16'h43a2;
-pmem[ 541] = 16'h0100;
-pmem[ 542] = 16'h403c;
-pmem[ 543] = 16'h0003;
-pmem[ 544] = 16'h430d;
-pmem[ 545] = 16'h431a;
-pmem[ 546] = 16'h4037;
-pmem[ 547] = 16'h003f;
-pmem[ 548] = 16'h4d0f;
-pmem[ 549] = 16'hf03f;
-pmem[ 550] = 16'h000f;
-pmem[ 551] = 16'h4a0e;
-pmem[ 552] = 16'h930f;
-pmem[ 553] = 16'h2403;
-pmem[ 554] = 16'h5e0e;
-pmem[ 555] = 16'h831f;
-pmem[ 556] = 16'h23fd;
-pmem[ 557] = 16'h4d0f;
-pmem[ 558] = 16'hc312;
-pmem[ 559] = 16'h100f;
-pmem[ 560] = 16'h110f;
-pmem[ 561] = 16'h110f;
-pmem[ 562] = 16'hf03f;
-pmem[ 563] = 16'h7ffe;
-pmem[ 564] = 16'hff1e;
-pmem[ 565] = 16'h0200;
-pmem[ 566] = 16'h2021;
-pmem[ 567] = 16'h4c82;
-pmem[ 568] = 16'h0100;
-pmem[ 569] = 16'h4c0b;
-pmem[ 570] = 16'h5b0b;
-pmem[ 571] = 16'h4319;
-pmem[ 572] = 16'hb31b;
-pmem[ 573] = 16'h2418;
-pmem[ 574] = 16'h4b0e;
-pmem[ 575] = 16'h503e;
-pmem[ 576] = 16'hfffd;
-pmem[ 577] = 16'hc312;
-pmem[ 578] = 16'h100e;
-pmem[ 579] = 16'h9e07;
-pmem[ 580] = 16'h2813;
-pmem[ 581] = 16'h4e0f;
-pmem[ 582] = 16'hc312;
-pmem[ 583] = 16'h100f;
-pmem[ 584] = 16'h110f;
-pmem[ 585] = 16'h110f;
-pmem[ 586] = 16'hf03f;
-pmem[ 587] = 16'h3ffe;
-pmem[ 588] = 16'hf03e;
-pmem[ 589] = 16'h000f;
-pmem[ 590] = 16'h4908;
-pmem[ 591] = 16'h930e;
-pmem[ 592] = 16'h2403;
-pmem[ 593] = 16'h5808;
-pmem[ 594] = 16'h831e;
-pmem[ 595] = 16'h23fd;
-pmem[ 596] = 16'hd88f;
-pmem[ 597] = 16'h0200;
-pmem[ 598] = 16'h5c0b;
-pmem[ 599] = 16'h3fe4;
-pmem[ 600] = 16'h531d;
-pmem[ 601] = 16'h532c;
-pmem[ 602] = 16'h903d;
-pmem[ 603] = 16'h0040;
-pmem[ 604] = 16'h23c7;
-pmem[ 605] = 16'h4382;
-pmem[ 606] = 16'h0100;
-pmem[ 607] = 16'h430f;
-pmem[ 608] = 16'hd032;
-pmem[ 609] = 16'h00f0;
-pmem[ 610] = 16'h3ffd;
-pmem[ 611] = 16'h4030;
-pmem[ 612] = 16'hfcca;
-pmem[ 613] = 16'h1300;
-pmem[1008] = 16'hfcc6;
-pmem[1009] = 16'hfcc6;
-pmem[1010] = 16'hfcc6;
-pmem[1011] = 16'hfcc6;
-pmem[1012] = 16'hfcc6;
-pmem[1013] = 16'hfcc6;
-pmem[1014] = 16'hfcc6;
-pmem[1015] = 16'hfcc6;
-pmem[1016] = 16'hfcc6;
-pmem[1017] = 16'hfcc6;
-pmem[1018] = 16'hfcc6;
-pmem[1019] = 16'hfcc6;
-pmem[1020] = 16'hfcc6;
-pmem[1021] = 16'hfcc6;
-pmem[1022] = 16'hfcc6;
-pmem[1023] = 16'hfc00;
-	output_idx = 0;
-end
-
-always @(posedge mclk) begin
-	dmem_dout <= 'bx;
-	pmem_dout <= 'bx;
-
-	if (~dmem_cen && &dmem_wen) begin
-		addr = 2*dmem_addr + 512;
-		$display("+LOG+ %t -- DR  @%04x %x%x", $time, addr, dmem_hi[dmem_addr], dmem_lo[dmem_addr]);
-		dmem_dout[15:8] <= dmem_hi[dmem_addr];
-		dmem_dout[ 7:0] <= dmem_lo[dmem_addr];
-	end
-
-	if (~pmem_cen) begin
-		addr = 2*pmem_addr - 2048;
-		$display("+LOG+ %t -- PR  @%04x %x", $time, addr, pmem[pmem_addr]);
-		pmem_dout <= pmem[pmem_addr];
-	end
-
-	if (~dmem_cen && ~dmem_wen) begin
-		addr = 2*dmem_addr + 512;
-		$display("+LOG+ %t -- DW  @%04x %x%x", $time, addr, ~dmem_wen[1] ? dmem_din[15:8] : 8'hzz, ~dmem_wen[0] ? dmem_din[ 7:0] : 8'hzz);
-		if (~dmem_wen[1])
-			dmem_hi[dmem_addr] <= dmem_din[15:8];
-		if (~dmem_wen[0])
-			dmem_lo[dmem_addr] <= dmem_din[ 7:0];
-	end
-end
-
-always @(posedge mclk) begin
-	per_dout <= 0;
-
-	if (per_en && per_we) begin
-		addr = 2*per_addr;
-		$display("+LOG+ %t -- PER @%04x %x%x  <---", $time, addr, per_we[1] ? per_din[15:8] : 8'hzz, per_we[0] ? per_din[ 7:0] : 8'hzz);
-
-		if (addr == 16'h0100) begin
-			if (per_din == 0) begin
-				-> output_eof;
-			end else begin
-				output_buf[output_idx] = per_din;
-				output_idx = output_idx + 1;
-			end
-		end
-	end
-end
-
-always @(output_eof) begin
-	#1001;
-	for (i = 0; i < output_idx; i = i + 1) begin
-		$display("+OUT+ %t %d", $time, output_buf[i]);
-	end
-	$finish;
-end
-
-initial begin
-	// $dumpfile("bench.vcd");
-	// $dumpvars(0, testbench);
-end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/sim/sieve.v b/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/sim/sieve.v
deleted file mode 100644
index 8c097cb..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/openmsp430/slpp_unit/work/sim/sieve.v
+++ /dev/null
@@ -1,118 +0,0 @@
-pmem[ 512] = 16'h4031;
-pmem[ 513] = 16'h0280;
-pmem[ 514] = 16'h4215;
-pmem[ 515] = 16'h0120;
-pmem[ 516] = 16'hf375;
-pmem[ 517] = 16'hd035;
-pmem[ 518] = 16'h5a08;
-pmem[ 519] = 16'h403f;
-pmem[ 520] = 16'h0000;
-pmem[ 521] = 16'h930f;
-pmem[ 522] = 16'h2407;
-pmem[ 523] = 16'h4582;
-pmem[ 524] = 16'h0120;
-pmem[ 525] = 16'h832f;
-pmem[ 526] = 16'h4f9f;
-pmem[ 527] = 16'hfccc;
-pmem[ 528] = 16'h0200;
-pmem[ 529] = 16'h23f9;
-pmem[ 530] = 16'h403f;
-pmem[ 531] = 16'h0008;
-pmem[ 532] = 16'h930f;
-pmem[ 533] = 16'h2406;
-pmem[ 534] = 16'h4582;
-pmem[ 535] = 16'h0120;
-pmem[ 536] = 16'h831f;
-pmem[ 537] = 16'h43cf;
-pmem[ 538] = 16'h0200;
-pmem[ 539] = 16'h23fa;
-pmem[ 540] = 16'h43a2;
-pmem[ 541] = 16'h0100;
-pmem[ 542] = 16'h403c;
-pmem[ 543] = 16'h0003;
-pmem[ 544] = 16'h430d;
-pmem[ 545] = 16'h431a;
-pmem[ 546] = 16'h4037;
-pmem[ 547] = 16'h003f;
-pmem[ 548] = 16'h4d0f;
-pmem[ 549] = 16'hf03f;
-pmem[ 550] = 16'h000f;
-pmem[ 551] = 16'h4a0e;
-pmem[ 552] = 16'h930f;
-pmem[ 553] = 16'h2403;
-pmem[ 554] = 16'h5e0e;
-pmem[ 555] = 16'h831f;
-pmem[ 556] = 16'h23fd;
-pmem[ 557] = 16'h4d0f;
-pmem[ 558] = 16'hc312;
-pmem[ 559] = 16'h100f;
-pmem[ 560] = 16'h110f;
-pmem[ 561] = 16'h110f;
-pmem[ 562] = 16'hf03f;
-pmem[ 563] = 16'h7ffe;
-pmem[ 564] = 16'hff1e;
-pmem[ 565] = 16'h0200;
-pmem[ 566] = 16'h2021;
-pmem[ 567] = 16'h4c82;
-pmem[ 568] = 16'h0100;
-pmem[ 569] = 16'h4c0b;
-pmem[ 570] = 16'h5b0b;
-pmem[ 571] = 16'h4319;
-pmem[ 572] = 16'hb31b;
-pmem[ 573] = 16'h2418;
-pmem[ 574] = 16'h4b0e;
-pmem[ 575] = 16'h503e;
-pmem[ 576] = 16'hfffd;
-pmem[ 577] = 16'hc312;
-pmem[ 578] = 16'h100e;
-pmem[ 579] = 16'h9e07;
-pmem[ 580] = 16'h2813;
-pmem[ 581] = 16'h4e0f;
-pmem[ 582] = 16'hc312;
-pmem[ 583] = 16'h100f;
-pmem[ 584] = 16'h110f;
-pmem[ 585] = 16'h110f;
-pmem[ 586] = 16'hf03f;
-pmem[ 587] = 16'h3ffe;
-pmem[ 588] = 16'hf03e;
-pmem[ 589] = 16'h000f;
-pmem[ 590] = 16'h4908;
-pmem[ 591] = 16'h930e;
-pmem[ 592] = 16'h2403;
-pmem[ 593] = 16'h5808;
-pmem[ 594] = 16'h831e;
-pmem[ 595] = 16'h23fd;
-pmem[ 596] = 16'hd88f;
-pmem[ 597] = 16'h0200;
-pmem[ 598] = 16'h5c0b;
-pmem[ 599] = 16'h3fe4;
-pmem[ 600] = 16'h531d;
-pmem[ 601] = 16'h532c;
-pmem[ 602] = 16'h903d;
-pmem[ 603] = 16'h0040;
-pmem[ 604] = 16'h23c7;
-pmem[ 605] = 16'h4382;
-pmem[ 606] = 16'h0100;
-pmem[ 607] = 16'h430f;
-pmem[ 608] = 16'hd032;
-pmem[ 609] = 16'h00f0;
-pmem[ 610] = 16'h3ffd;
-pmem[ 611] = 16'h4030;
-pmem[ 612] = 16'hfcca;
-pmem[ 613] = 16'h1300;
-pmem[1008] = 16'hfcc6;
-pmem[1009] = 16'hfcc6;
-pmem[1010] = 16'hfcc6;
-pmem[1011] = 16'hfcc6;
-pmem[1012] = 16'hfcc6;
-pmem[1013] = 16'hfcc6;
-pmem[1014] = 16'hfcc6;
-pmem[1015] = 16'hfcc6;
-pmem[1016] = 16'hfcc6;
-pmem[1017] = 16'hfcc6;
-pmem[1018] = 16'hfcc6;
-pmem[1019] = 16'hfcc6;
-pmem[1020] = 16'hfcc6;
-pmem[1021] = 16'hfcc6;
-pmem[1022] = 16'hfcc6;
-pmem[1023] = 16'hfc00;
diff --git a/SVIncCompil/Testcases/YosysBigSim/reed_solomon_decoder/slpp_unit/surelog.log b/SVIncCompil/Testcases/YosysBigSim/reed_solomon_decoder/slpp_unit/surelog.log
deleted file mode 100644
index 4120d3e..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/reed_solomon_decoder/slpp_unit/surelog.log
+++ /dev/null
@@ -1,115 +0,0 @@
-********************************************
-*  SURELOG System Verilog Compiler/Linter  *
-********************************************
-
-Copyright (c) 2017-2019 ACE Cloud,
-Authorized used only.
-
-VERSION: 0.05
-BUILT  : Nov  3 2019
-DATE   : 2019-11-03.21:43:09
-COMMAND: -writepp -parse -mt max -nopython -fileunit rtl/BM_lamda.v rtl/DP_RAM.v rtl/GF_matrix_ascending_binary.v rtl/GF_matrix_dec.v rtl/GF_mult_add_syndromes.v rtl/Omega_Phy.v rtl/RS_dec.v rtl/error_correction.v rtl/input_syndromes.v rtl/lamda_roots.v rtl/out_stage.v rtl/transport_in2out.v sim/RS_dec_tb.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
-
-[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
-
-[INFO :CM0024] Executing with 4 threads.
-
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[ERROR:PP0125] Cannot read the file's content "rtl/BM_lamda.v". Only UTF-8 is supported.
-
-[WARNI:PA0205] rtl/GF_matrix_ascending_binary.v:20 No timescale set for "GF_matrix_ascending_binary".
-
-[WARNI:PA0205] rtl/GF_matrix_dec.v:21 No timescale set for "GF_matrix_dec".
-
-[WARNI:PA0205] rtl/DP_RAM.v:18 No timescale set for "DP_RAM".
-
-[WARNI:PA0205] rtl/GF_mult_add_syndromes.v:28 No timescale set for "GF_mult_add_syndromes".
-
-[WARNI:PA0205] rtl/input_syndromes.v:24 No timescale set for "input_syndromes".
-
-[WARNI:PA0205] rtl/RS_dec.v:21 No timescale set for "RS_dec".
-
-[WARNI:PA0205] rtl/Omega_Phy.v:21 No timescale set for "Omega_Phy".
-
-[WARNI:PA0205] rtl/transport_in2out.v:22 No timescale set for "transport_in2out".
-
-[WARNI:PA0205] rtl/error_correction.v:20 No timescale set for "error_correction".
-
-[WARNI:PA0205] rtl/lamda_roots.v:21 No timescale set for "lamda_roots".
-
-[WARNI:PA0205] rtl/out_stage.v:21 No timescale set for "out_stage".
-
-[WARNI:PA0205] sim/RS_dec_tb.v:3 No timescale set for "testbench".
-
-[INFO :CP0300] Compilation...
-
-[INFO :CP0303] rtl/GF_matrix_ascending_binary.v:20 Compile module "work@GF_matrix_ascending_binary".
-
-[INFO :CP0303] rtl/RS_dec.v:21 Compile module "work@RS_dec".
-
-[INFO :CP0303] rtl/GF_mult_add_syndromes.v:28 Compile module "work@GF_mult_add_syndromes".
-
-[INFO :CP0303] rtl/DP_RAM.v:18 Compile module "work@DP_RAM".
-
-[INFO :CP0303] rtl/GF_matrix_dec.v:21 Compile module "work@GF_matrix_dec".
-
-[INFO :CP0303] rtl/input_syndromes.v:24 Compile module "work@input_syndromes".
-
-[INFO :CP0303] rtl/out_stage.v:21 Compile module "work@out_stage".
-
-[INFO :CP0303] rtl/Omega_Phy.v:21 Compile module "work@Omega_Phy".
-
-[INFO :CP0303] rtl/error_correction.v:20 Compile module "work@error_correction".
-
-[INFO :CP0303] rtl/transport_in2out.v:22 Compile module "work@transport_in2out".
-
-[INFO :CP0303] rtl/lamda_roots.v:21 Compile module "work@lamda_roots".
-
-[INFO :CP0303] sim/RS_dec_tb.v:3 Compile module "work@testbench".
-
-[NOTE :CP0309] rtl/Omega_Phy.v:44 Implicit port type (wire) for "add_pow2",
-there are 20 more instances of this message.
-
-[NOTE :CP0309] rtl/lamda_roots.v:30 Implicit port type (wire) for "add_GF_dec1",
-there are 8 more instances of this message.
-
-[NOTE :CP0309] rtl/RS_dec.v:29 Implicit port type (wire) for "Out_byte",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/error_correction.v:44 Implicit port type (wire) for "add_pow2",
-there are 8 more instances of this message.
-
-[NOTE :CP0309] rtl/input_syndromes.v:38 Implicit port type (wire) for "s1",
-there are 15 more instances of this message.
-
-[NOTE :CP0309] rtl/transport_in2out.v:32 Implicit port type (wire) for "WE",
-there are 1 more instances of this message.
-
-[INFO :EL0526] Design Elaboration...
-
-[NOTE :EL0503] sim/RS_dec_tb.v:3 Top level module "work@testbench".
-
-[WARNI:EL0500] rtl/RS_dec.v:106 Cannot find a module definition for "work@RS_dec::BM_lamda".
-
-[NOTE :EL0508] Nb Top level modules: 1.
-
-[NOTE :EL0509] Max instance depth: 5.
-
-[NOTE :EL0510] Nb instances: 26.
-
-[NOTE :EL0511] Nb leaf instances: 1.
-
-[WARNI:EL0512] Nb undefined modules: 1.
-
-[WARNI:EL0513] Nb undefined instances: 1.
-
-[  FATAL] : 0
-[  ERROR] : 1
-[WARNING] : 15
-[   NOTE] : 11
-
-********************************************
-*   End SURELOG SVerilog Compiler/Linter   *
-********************************************
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/surelog.log b/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/surelog.log
deleted file mode 100644
index 1301dc8..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/surelog.log
+++ /dev/null
@@ -1,52 +0,0 @@
-********************************************
-*  SURELOG System Verilog Compiler/Linter  *
-********************************************
-
-Copyright (c) 2017-2019 ACE Cloud,
-Authorized used only.
-
-VERSION: 0.05
-BUILT  : Nov  3 2019
-DATE   : 2019-11-03.21:37:19
-COMMAND: -writepp -parse -mt max -nopython -fileunit rtl/softusb_navre.v sim/bench.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
-
-[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
-
-[INFO :CM0024] Executing with 4 threads.
-
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[WARNI:PA0205] sim/bench.v:2 No timescale set for "testbench".
-
-[WARNI:PA0205] rtl/softusb_navre.v:18 No timescale set for "softusb_navre".
-
-[INFO :CP0300] Compilation...
-
-[INFO :CP0303] rtl/softusb_navre.v:18 Compile module "work@softusb_navre".
-
-[INFO :CP0303] sim/bench.v:2 Compile module "work@testbench".
-
-[NOTE :CP0309] rtl/softusb_navre.v:26 Implicit port type (wire) for "pmem_a",
-there are 2 more instances of this message.
-
-[INFO :EL0526] Design Elaboration...
-
-[NOTE :EL0503] sim/bench.v:2 Top level module "work@testbench".
-
-[NOTE :EL0508] Nb Top level modules: 1.
-
-[NOTE :EL0509] Max instance depth: 2.
-
-[NOTE :EL0510] Nb instances: 2.
-
-[NOTE :EL0511] Nb leaf instances: 0.
-
-[  FATAL] : 0
-[  ERROR] : 0
-[WARNING] : 2
-[   NOTE] : 6
-
-********************************************
-*   End SURELOG SVerilog Compiler/Linter   *
-********************************************
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/work/rtl/softusb_navre.v b/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/work/rtl/softusb_navre.v
deleted file mode 100644
index 1fc9db0..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/work/rtl/softusb_navre.v
+++ /dev/null
@@ -1,974 +0,0 @@
-/*
- * Milkymist SoC
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-module softusb_navre #(
-	parameter pmem_width = 11, /* < in 16-bit instructions */
-	parameter dmem_width = 13 /* < in bytes */
-) (
-	input clk,
-	input rst,
-
-	output reg pmem_ce,
-	output [pmem_width-1:0] pmem_a,
-	input [15:0] pmem_d,
-
-	output reg dmem_we,
-	output reg [dmem_width-1:0] dmem_a,
-	input [7:0] dmem_di,
-	output reg [7:0] dmem_do,
-
-	output reg io_re,
-	output reg io_we,
-	output [5:0] io_a,
-	output [7:0] io_do,
-	input [7:0] io_di,
-
-	input [7:0] irq,
-	output reg [7:0] irq_ack,
-
-	output reg [pmem_width-1:0] dbg_pc
-);
-
-/* Register file */
-reg [pmem_width-1:0] PC;
-reg [7:0] GPR[0:23];
-reg [15:0] U;	/* < R24-R25 */
-reg [15:0] pX;	/* < R26-R27 */
-reg [15:0] pY;	/* < R28-R29 */
-reg [15:0] pZ;	/* < R30-R31 */
-reg I, T, H, S, V, N, Z, C;
-
-/* Stack */
-reg [7:0] io_sp;
-reg [15:0] SP;
-reg push;
-reg pop;
-always @(posedge clk) begin
-	if(rst) begin
-		io_sp <= 8'd0;
-		SP <= 16'd0;
-	end else begin
-		io_sp <= io_a[0] ? SP[7:0] : SP[15:8];
-		if((io_a == 6'b111101) | (io_a == 6'b111110)) begin
-			if(io_we) begin
-				if(io_a[0])
-					SP[7:0] <= io_do;
-				else
-					SP[15:8] <= io_do;
-			end
-		end
-		if(push)
-			SP <= SP - 16'd1;
-		if(pop)
-			SP <= SP + 16'd1;
-	end
-end
-
-/* I/O mapped registers */
-
-localparam IO_SEL_EXT	= 2'd0;
-localparam IO_SEL_STACK	= 2'd1;
-localparam IO_SEL_SREG	= 2'd2;
-
-reg [1:0] io_sel;
-always @(posedge clk) begin
-	if(rst)
-		io_sel <= IO_SEL_EXT;
-	else begin
-		case(io_a)
-			6'b111101,
-			6'b111110: io_sel <= IO_SEL_STACK;
-			6'b111111: io_sel <= IO_SEL_SREG;
-			default: io_sel <= IO_SEL_EXT;
-		endcase
-	end
-end
-
-/* Register operations */
-wire immediate = (pmem_d[14]
-	| (pmem_d[15:12] == 4'b0011))		/* CPI */
-	& (pmem_d[15:10] != 6'b111111)		/* SBRC - SBRS */
-	& (pmem_d[15:10] != 6'b111110);		/* BST - BLD */
-reg lpm_en;
-wire [4:0] Rd = lpm_en ? 5'd0 : {immediate | pmem_d[8], pmem_d[7:4]};
-wire [4:0] Rr = {pmem_d[9], pmem_d[3:0]};
-wire [7:0] K = {pmem_d[11:8], pmem_d[3:0]};
-wire [2:0] b = pmem_d[2:0];
-wire [11:0] Kl = pmem_d[11:0];
-wire [6:0] Ks = pmem_d[9:3];
-wire [1:0] Rd16 = pmem_d[5:4];
-wire [5:0] K16 = {pmem_d[7:6], pmem_d[3:0]};
-wire [5:0] q = {pmem_d[13], pmem_d[11:10], pmem_d[2:0]};
-
-wire [7:0] GPR_Rd8 = GPR[Rd];
-wire [7:0] GPR_Rr8 = GPR[Rr];
-reg [7:0] GPR_Rd;
-always @(*) begin
-	case(Rd)
-		default: GPR_Rd = GPR_Rd8;
-		5'd24: GPR_Rd = U[7:0];
-		5'd25: GPR_Rd = U[15:8];
-		5'd26: GPR_Rd = pX[7:0];
-		5'd27: GPR_Rd = pX[15:8];
-		5'd28: GPR_Rd = pY[7:0];
-		5'd29: GPR_Rd = pY[15:8];
-		5'd30: GPR_Rd = pZ[7:0];
-		5'd31: GPR_Rd = pZ[15:8];
-	endcase
-end
-reg [7:0] GPR_Rr;
-always @(*) begin
-	case(Rr)
-		default: GPR_Rr = GPR_Rr8;
-		5'd24: GPR_Rr = U[7:0];
-		5'd25: GPR_Rr = U[15:8];
-		5'd26: GPR_Rr = pX[7:0];
-		5'd27: GPR_Rr = pX[15:8];
-		5'd28: GPR_Rr = pY[7:0];
-		5'd29: GPR_Rr = pY[15:8];
-		5'd30: GPR_Rr = pZ[7:0];
-		5'd31: GPR_Rr = pZ[15:8];
-	endcase
-end
-wire GPR_Rd_b = GPR_Rd[b];
-
-reg [15:0] GPR_Rd16;
-always @(*) begin
-	case(Rd16)
-		2'd0: GPR_Rd16 = U;
-		2'd1: GPR_Rd16 = pX;
-		2'd2: GPR_Rd16 = pY;
-		2'd3: GPR_Rd16 = pZ;
-	endcase
-end
-
-/* Memorize values to support 16-bit instructions */
-reg regmem_ce;
-
-reg [4:0] Rd_r;
-reg [7:0] GPR_Rd_r;
-always @(posedge clk) begin
-	if(regmem_ce)
-		Rd_r <= Rd; /* < control with regmem_ce */
-	GPR_Rd_r <= GPR_Rd; /* < always loaded */
-end
-
-/* PC */
-
-reg [3:0] pc_sel;
-
-localparam PC_SEL_NOP		= 4'd0;
-localparam PC_SEL_INC		= 4'd1;
-localparam PC_SEL_KL		= 4'd2;
-localparam PC_SEL_KS		= 4'd3;
-localparam PC_SEL_DMEML		= 4'd4;
-localparam PC_SEL_DMEMH		= 4'd6;
-localparam PC_SEL_DEC		= 4'd7;
-localparam PC_SEL_Z		= 4'd8;
-localparam PC_SEL_EX		= 4'd9;
-
-/* Exceptions */
-
-reg [7:0] next_irq_ack;
-always @(*) begin
-	next_irq_ack = 8'b0;
-	casex(irq)
-		8'bxxxx_xxx1: next_irq_ack = 8'b0000_0001;
-		8'bxxxx_xx10: next_irq_ack = 8'b0000_0010;
-		8'bxxxx_x100: next_irq_ack = 8'b0000_0100;
-		8'bxxxx_1000: next_irq_ack = 8'b0000_1000;
-		8'bxxx1_0000: next_irq_ack = 8'b0001_0000;
-		8'bxx10_0000: next_irq_ack = 8'b0010_0000;
-		8'bx100_0000: next_irq_ack = 8'b0100_0000;
-		8'b1000_0000: next_irq_ack = 8'b1000_0000;
-	endcase
-end
-
-reg irq_ack_en;
-always @(posedge clk) begin
-	if(rst)
-		irq_ack <= 8'b0;
-	else begin
-		irq_ack <= 1'b0;
-		if(irq_ack_en)
-			irq_ack <= next_irq_ack;
-	end
-end
-
-/* Priority encoder */
-
-reg [3:0] PC_ex;
-always @(*) begin
-	PC_ex = 4'b0;
-	casex(irq)
-		8'bxxxx_xxx1: PC_ex = 4'h0;
-		8'bxxxx_xx10: PC_ex = 4'h1;
-		8'bxxxx_x100: PC_ex = 4'h2;
-		8'bxxxx_1000: PC_ex = 4'h3;
-		8'bxxx1_0000: PC_ex = 4'h4;
-		8'bxx10_0000: PC_ex = 4'h5;
-		8'bx100_0000: PC_ex = 4'h6;
-		8'b1000_0000: PC_ex = 4'h7;
-	endcase
-end
-
-/* AVR cores always execute at least one instruction after an IRET.
- * Therefore, the I bit is only valid one clock after it has been set. */
-
-reg I_r;
-always @(posedge clk) begin
-	if(rst)
-		I_r <= 1'b0;
-	else
-		I_r <= I;
-end
-wire irq_asserted = |irq;
-wire irq_request = I & I_r & irq_asserted;
-
-always @(posedge clk) begin
-	if(rst) begin
-		PC <= 0;
-	end else begin
-		case(pc_sel)
-			PC_SEL_NOP:;
-			PC_SEL_INC: PC <= PC + 1;
-			// !!! WARNING !!! replace with PC <= PC + {{pmem_width-12{Kl[11]}}, Kl}; if pmem_width>12
-			PC_SEL_KL: PC <= PC + Kl;
-			PC_SEL_KS: PC <= PC + {{pmem_width-7{Ks[6]}}, Ks};
-			PC_SEL_DMEML: PC[7:0] <= dmem_di;
-			PC_SEL_DMEMH: PC[pmem_width-1:8] <= dmem_di;
-			PC_SEL_DEC: PC <= PC - 1;
-			PC_SEL_Z: PC <= pZ - 1;
-			PC_SEL_EX: PC <= {{pmem_width-4{1'b0}}, PC_ex};
-		endcase
-	end
-	dbg_pc <= PC;
-end
-reg pmem_selz;
-assign pmem_a = rst ?
-	0
-	: (pmem_selz ? pZ[15:1] : PC + 1);
-
-/* Load/store operations */
-reg [3:0] dmem_sel;
-
-localparam DMEM_SEL_UNDEFINED	= 3'bxxx;
-localparam DMEM_SEL_X		= 4'd0;
-localparam DMEM_SEL_XPLUS	= 4'd1;
-localparam DMEM_SEL_XMINUS	= 4'd2;
-localparam DMEM_SEL_YPLUS	= 4'd3;
-localparam DMEM_SEL_YMINUS	= 4'd4;
-localparam DMEM_SEL_YQ		= 4'd5;
-localparam DMEM_SEL_ZPLUS	= 4'd6;
-localparam DMEM_SEL_ZMINUS	= 4'd7;
-localparam DMEM_SEL_ZQ		= 4'd8;
-localparam DMEM_SEL_SP_R	= 4'd9;
-localparam DMEM_SEL_SP_PCL	= 4'd10;
-localparam DMEM_SEL_SP_PCH	= 4'd11;
-localparam DMEM_SEL_PMEM	= 4'd12;
-
-/* ALU */
-
-reg normal_en;
-reg lds_writeback;
-
-wire [4:0] write_dest = lds_writeback ? Rd_r : Rd;
-
-integer i_rst_regf;
-reg [7:0] R;
-reg writeback;
-reg update_svnz;
-reg change_z;
-reg [15:0] R16;
-reg mode16;
-reg _N;
-reg _V;
-reg _C;
-reg I_clr;
-reg I_set;
-always @(posedge clk) begin
-	R = 8'hxx;
-	writeback = 1'b0;
-	update_svnz = 1'b0;
-	change_z = 1'b1;
-	R16 = 16'hxxxx;
-	mode16 = 1'b0;
-	if(rst) begin
-		/*
-		 * Not resetting the register file enables the use of more efficient
-		 * distributed block RAM.
-		 */
-		for(i_rst_regf=0;i_rst_regf<24;i_rst_regf=i_rst_regf+1)
-			GPR[i_rst_regf] <= 8'd0;
-		U <= 16'd0;
-		pX <= 16'd0;
-		pY <= 16'd0;
-		pZ <= 16'd0;
-		I <= 1'b0;
-		T <= 1'b0;
-		H <= 1'b0;
-		S <= 1'b0;
-		V <= 1'b0;
-		N <= 1'b0;
-		Z <= 1'b0;
-		C <= 1'b0;
-		_V = 1'b0;
-		_N = 1'b0;
-		_C = 1'b0;
-	end else begin
-		if(I_set)
-			I <= 1'b1;
-		if(normal_en) begin
-			writeback = 1'b1;
-			update_svnz = 1'b1;
-			casex(pmem_d)
-				16'b000x_11xx_xxxx_xxxx: begin
-					/* ADD - ADC */
-					{_C, R} = GPR_Rd + GPR_Rr + (pmem_d[12] & C);
-					C <= _C;
-					H <= (GPR_Rd[3] & GPR_Rr[3])|(GPR_Rr[3] & ~R[3])|(~R[3] & GPR_Rd[3]);
-					_V = (GPR_Rd[7] & GPR_Rr[7] & ~R[7])|(~GPR_Rd[7] & ~GPR_Rr[7] & R[7]);
-				end
-				16'b000x_10xx_xxxx_xxxx, /* subtract */
-				16'b000x_01xx_xxxx_xxxx: /* compare  */ begin
-					/* SUB - SBC / CP - CPC */
-					{_C, R} = GPR_Rd - GPR_Rr - (~pmem_d[12] & C);
-					C <= _C;
-					H <= (~GPR_Rd[3] & GPR_Rr[3])|(GPR_Rr[3] & R[3])|(R[3] & ~GPR_Rd[3]);
-					_V = (GPR_Rd[7] & ~GPR_Rr[7] & ~R[7])|(~GPR_Rd[7] & GPR_Rr[7] & R[7]);
-					if(~pmem_d[12])
-						change_z = 1'b0;
-					writeback = pmem_d[11];
-				end
-				16'b010x_xxxx_xxxx_xxxx, /* subtract */
-				16'b0011_xxxx_xxxx_xxxx: /* compare  */ begin
-					/* SUBI - SBCI / CPI */
-					{_C, R} = GPR_Rd - K - (~pmem_d[12] & C);
-					C <= _C;
-					H <= (~GPR_Rd[3] & K[3])|(K[3] & R[3])|(R[3] & ~GPR_Rd[3]);
-					_V = (GPR_Rd[7] & ~K[7] & ~R[7])|(~GPR_Rd[7] & K[7] & R[7]);
-					if(~pmem_d[12])
-						change_z = 1'b0;
-					writeback = pmem_d[14];
-				end
-				16'b0010_00xx_xxxx_xxxx: begin
-					/* AND */
-					R = GPR_Rd & GPR_Rr;
-					_V = 1'b0;
-				end
-				16'b0111_xxxx_xxxx_xxxx: begin
-					/* ANDI */
-					R = GPR_Rd & K;
-					_V = 1'b0;
-				end
-				16'b0010_10xx_xxxx_xxxx: begin
-					/* OR */
-					R = GPR_Rd | GPR_Rr;
-					_V = 1'b0;
-				end
-				16'b0110_xxxx_xxxx_xxxx: begin
-					/* ORI */
-					R = GPR_Rd | K;
-					_V = 1'b0;
-				end
-				16'b0010_01xx_xxxx_xxxx: begin
-					/* EOR */
-					R = GPR_Rd ^ GPR_Rr;
-					_V = 1'b0;
-				end
-				16'b1001_010x_xxxx_0000: begin
-					/* COM */
-					R = ~GPR_Rd;
-					_V = 1'b0;
-					C <= 1'b1;
-				end
-				16'b1001_010x_xxxx_0001: begin
-					/* NEG */
-					{_C, R} = 8'h00 - GPR_Rd;
-					C <= _C;
-					H <= R[3] | GPR_Rd[3];
-					_V = R == 8'h80;
-				end
-				16'b1001_010x_xxxx_0011: begin
-					/* INC */
-					R = GPR_Rd + 8'd1;
-					_V = R == 8'h80;
-				end
-				16'b1001_010x_xxxx_1010: begin
-					/* DEC */
-					R = GPR_Rd - 8'd1;
-					_V = R == 8'h7f;
-				end
-				16'b1001_010x_xxxx_011x: begin
-					/* LSR - ROR */
-					R = {pmem_d[0] & C, GPR_Rd[7:1]};
-					C <= GPR_Rd[0];
-					_V = R[7] ^ GPR_Rd[0];
-				end
-				16'b1001_010x_xxxx_0101: begin
-					/* ASR */
-					R = {GPR_Rd[7], GPR_Rd[7:1]};
-					C <= GPR_Rd[0];
-					_V = R[7] ^ GPR_Rd[0];
-				end
-				16'b1001_010x_xxxx_0010: begin
-					/* SWAP */
-					R = {GPR_Rd[3:0], GPR_Rd[7:4]};
-					update_svnz = 1'b0;
-				end
-				16'b1001_010x_xxxx_1000: begin
-					/* BSET - BCLR */
-					case(pmem_d[7:4])
-						4'b0000: C <= 1'b1;
-						4'b0001: Z <= 1'b1;
-						4'b0010: N <= 1'b1;
-						4'b0011: V <= 1'b1;
-						4'b0100: S <= 1'b1;
-						4'b0101: H <= 1'b1;
-						4'b0110: T <= 1'b1;
-						4'b0111: I <= 1'b1;
-						4'b1000: C <= 1'b0;
-						4'b1001: Z <= 1'b0;
-						4'b1010: N <= 1'b0;
-						4'b1011: V <= 1'b0;
-						4'b1100: S <= 1'b0;
-						4'b1101: H <= 1'b0;
-						4'b1110: T <= 1'b0;
-						4'b1111: I <= 1'b0;
-					endcase
-					update_svnz = 1'b0;
-					writeback = 1'b0;
-				end
-				16'b1001_011x_xxxx_xxxx: begin
-					mode16 = 1'b1;
-					if(pmem_d[8]) begin
-						/* SBIW */
-						{_C, R16} = GPR_Rd16 - K16;
-						C <= _C;
-						_V = GPR_Rd16[15] & ~R16[15];
-					end else begin
-						/* ADIW */
-						{_C, R16} = GPR_Rd16 + K16;
-						C <= _C;
-						_V = ~GPR_Rd16[15] & R16[15];
-					end
-				end
-				/* SBR and CBR are replaced with ORI and ANDI */
-				/* TST is replaced with AND */
-				/* CLR and SER are replaced with EOR and LDI */
-				16'b0010_11xx_xxxx_xxxx: begin
-					/* MOV */
-					R = GPR_Rr;
-					update_svnz = 1'b0;
-				end
-				16'b1110_xxxx_xxxx_xxxx: begin
-					/* LDI */
-					R = K;
-					update_svnz = 1'b0;
-				end
-				/* LSL is replaced with ADD */
-				/* ROL is replaced with ADC */
-				16'b1111_10xx_xxxx_0xxx: begin
-					if(pmem_d[9]) begin
-						/* BST */
-						T <= GPR_Rd_b;
-						writeback = 1'b0;
-					end else begin
-						/* BLD */
-						case(b)
-							3'd0: R = {GPR_Rd[7:1], T};
-							3'd1: R = {GPR_Rd[7:2], T, GPR_Rd[0]};
-							3'd2: R = {GPR_Rd[7:3], T, GPR_Rd[1:0]};
-							3'd3: R = {GPR_Rd[7:4], T, GPR_Rd[2:0]};
-							3'd4: R = {GPR_Rd[7:5], T, GPR_Rd[3:0]};
-							3'd5: R = {GPR_Rd[7:6], T, GPR_Rd[4:0]};
-							3'd6: R = {GPR_Rd[7], T, GPR_Rd[5:0]};
-							3'd7: R = {T, GPR_Rd[6:0]};
-						endcase
-					end
-					update_svnz = 1'b0;
-				end
-				/* SEC, CLC, SEN, CLN, SEZ, CLZ, SEI, CLI, SES, CLS, SEV, CLV, SET, CLT, SEH, CLH
-				 * are replaced with BSET and BCLR */
-				16'b0000_0000_0000_0000: begin
-					/* NOP */
-					update_svnz = 1'b0;
-					writeback = 1'b0;
-				end
-				/* SLEEP is not implemented */
-				/* WDR is not implemented */
-				16'b1001_00xx_xxxx_1111, /* PUSH/POP */
-				16'b1001_00xx_xxxx_1100, /*  X   */
-				16'b1001_00xx_xxxx_1101, /*  X+  */
-				16'b1001_00xx_xxxx_1110, /* -X   */
-				16'b1001_00xx_xxxx_1001, /*  Y+  */
-				16'b1001_00xx_xxxx_1010, /* -Y   */
-				16'b10x0_xxxx_xxxx_1xxx, /*  Y+q */
-				16'b1001_00xx_xxxx_0001, /*  Z+  */
-				16'b1001_00xx_xxxx_0010, /* -Z   */
-				16'b10x0_xxxx_xxxx_0xxx: /*  Z+q */
-				begin
-					/* LD - POP (run from state WRITEBACK) */
-					R = dmem_di;
-					update_svnz = 1'b0;
-				end
-				16'b1011_0xxx_xxxx_xxxx: begin
-					/* IN (run from state WRITEBACK) */
-					case(io_sel)
-						IO_SEL_EXT: R = io_di;
-						IO_SEL_STACK: R = io_sp;
-						IO_SEL_SREG: R = {I, T, H, S, V, N, Z, C};
-						default: R = 8'hxx;
-					endcase
-					update_svnz = 1'b0;
-				end
-			endcase
-		end /* if(normal_en) */
-		if(lds_writeback) begin
-			R = dmem_di;
-			writeback = 1'b1;
-		end
-		if(lpm_en) begin
-			R = pZ[0] ? pmem_d[15:8] : pmem_d[7:0];
-			writeback = 1'b1;
-		end
-		if(update_svnz) begin
-			_N = mode16 ? R16[15] : R[7];
-			S <= _N ^ _V;
-			V <= _V;
-			N <= _N;
-			Z <= mode16 ? R16 == 16'h0000 : ((R == 8'h00) & (change_z|Z));
-		end
-		if(io_we & (io_a == 6'b111111))
-			{I, T, H, S, V, N, Z, C} <= io_do[7:0];
-		if(I_clr)
-			I <= 1'b0;
-		if(writeback) begin
-			if(mode16) begin
-				// $display("REG WRITE(16): %d < %d", Rd16, R16);
-				case(Rd16)
-					2'd0: U <= R16;
-					2'd1: pX <= R16;
-					2'd2: pY <= R16;
-					2'd3: pZ <= R16;
-				endcase
-			end else begin
-				// $display("REG WRITE: %d < %d", Rd, R);
-				case(write_dest)
-					default: GPR[write_dest] <= R;
-					5'd24: U[7:0] <= R;
-					5'd25: U[15:8] <= R;
-					5'd26: pX[7:0] <= R;
-					5'd27: pX[15:8] <= R;
-					5'd28: pY[7:0] <= R;
-					5'd29: pY[15:8] <= R;
-					5'd30: pZ[7:0] <= R;
-					5'd31: pZ[15:8] <= R;
-				endcase
-			end
-		end else begin /* if(writeback) */
-			case(dmem_sel)
-				DMEM_SEL_XPLUS:		pX <= pX + 16'd1;
-				DMEM_SEL_XMINUS:	pX <= pX - 16'd1;
-				DMEM_SEL_YPLUS:		pY <= pY + 16'd1;
-				DMEM_SEL_YMINUS:	pY <= pY - 16'd1;
-				DMEM_SEL_ZPLUS:		pZ <= pZ + 16'd1;
-				DMEM_SEL_ZMINUS:	pZ <= pZ - 16'd1;
-				default:;
-			endcase
-		end
-	end /* if(rst) ... else */
-end
-
-/* I/O port */
-assign io_a = {pmem_d[10:9], pmem_d[3:0]};
-assign io_do = GPR_Rd;
-
-/* Data memory */
-always @(*) begin
-	case(dmem_sel)
-		DMEM_SEL_X,
-		DMEM_SEL_XPLUS:		dmem_a = pX;
-		DMEM_SEL_XMINUS:	dmem_a = pX - 16'd1;
-		DMEM_SEL_YPLUS:		dmem_a = pY;
-		DMEM_SEL_YMINUS:	dmem_a = pY - 16'd1;
-		DMEM_SEL_YQ:		dmem_a = pY + q;
-		DMEM_SEL_ZPLUS:		dmem_a = pZ;
-		DMEM_SEL_ZMINUS:	dmem_a = pZ - 16'd1;
-		DMEM_SEL_ZQ:		dmem_a = pZ + q;
-		DMEM_SEL_SP_R,
-		DMEM_SEL_SP_PCL,
-		DMEM_SEL_SP_PCH:	dmem_a = SP + pop;
-		DMEM_SEL_PMEM:		dmem_a = pmem_d;
-		default:		dmem_a = {dmem_width{1'bx}};
-	endcase
-end
-
-wire [pmem_width-1:0] PC_inc = PC + 1;
-reg exception;
-always @(*) begin
-	case(dmem_sel)
-		DMEM_SEL_X,
-		DMEM_SEL_XPLUS,
-		DMEM_SEL_XMINUS,
-		DMEM_SEL_YPLUS,
-		DMEM_SEL_YMINUS,
-		DMEM_SEL_YQ,
-		DMEM_SEL_ZPLUS,
-		DMEM_SEL_ZMINUS,
-		DMEM_SEL_ZQ,
-		DMEM_SEL_SP_R:		dmem_do = GPR_Rd;
-		DMEM_SEL_SP_PCL:	dmem_do = exception ? PC[7:0] : PC_inc[7:0];
-		DMEM_SEL_SP_PCH:	dmem_do = exception ? PC[pmem_width-1:8] : PC_inc[pmem_width-1:8];
-		DMEM_SEL_PMEM:		dmem_do = GPR_Rd_r;
-		default:		dmem_do = 8'hxx;
-	endcase
-end
-
-/* Multi-cycle operation sequencer */
-
-wire reg_equal = GPR_Rd == GPR_Rr;
-
-reg sreg_read;
-always @(*) begin
-	case(b)
-		3'd0: sreg_read = C;
-		3'd1: sreg_read = Z;
-		3'd2: sreg_read = N;
-		3'd3: sreg_read = V;
-		3'd4: sreg_read = S;
-		3'd5: sreg_read = H;
-		3'd6: sreg_read = T;
-		3'd7: sreg_read = I;
-	endcase
-end
-
-reg [4:0] state;
-reg [4:0] next_state;
-
-localparam NORMAL	= 5'd0;
-localparam RCALL	= 5'd1;
-localparam ICALL	= 5'd2;
-localparam STALL	= 5'd3;
-localparam RET1		= 5'd4;
-localparam RET2		= 5'd5;
-localparam RET3		= 5'd6;
-localparam LPM		= 5'd7;
-localparam STS		= 5'd8;
-localparam LDS1		= 5'd9;
-localparam LDS2		= 5'd10;
-localparam SKIP		= 5'd11;
-localparam WRITEBACK	= 5'd12;
-localparam EXCEPTION	= 5'd13;
-localparam RETI1	= 5'd14;
-localparam RETI2	= 5'd15;
-localparam RETI3	= 5'd16;
-localparam RETI4	= 5'd17;
-
-always @(posedge clk) begin
-	if(rst)
-		state <= NORMAL;
-	else
-		state <= next_state;
-end
-
-always @(*) begin
-	next_state = state;
-
-	pmem_ce = rst;
-
-	pc_sel = PC_SEL_NOP;
-	normal_en = 1'b0;
-	lpm_en = 1'b0;
-
-	io_re = 1'b0;
-	io_we = 1'b0;
-
-	dmem_we = 1'b0;
-	dmem_sel = DMEM_SEL_UNDEFINED;
-
-	push = 1'b0;
-	pop = 1'b0;
-
-	exception = 1'b0;
-	irq_ack_en = 1'b0;
-	I_set = 1'b0;
-	I_clr = 1'b0;
-
-	pmem_selz = 1'b0;
-
-	regmem_ce = 1'b1;
-	lds_writeback = 1'b0;
-	
-	case(state)
-		NORMAL: begin
-			if(irq_request) begin
-				dmem_sel = DMEM_SEL_SP_PCL;
-				dmem_we = 1'b1;
-				exception = 1'b1;
-				push = 1'b1;
-				irq_ack_en = 1'b1;
-				I_clr = 1'b1;
-				next_state = EXCEPTION;
-			end else begin
-				casex(pmem_d)
-					16'b1100_xxxx_xxxx_xxxx: begin
-						/* RJMP */
-						pc_sel = PC_SEL_KL;
-						next_state = STALL;
-					end
-					16'b1101_xxxx_xxxx_xxxx: begin
-						/* RCALL */
-						dmem_sel = DMEM_SEL_SP_PCL;
-						dmem_we = 1'b1;
-						push = 1'b1;
-						next_state = RCALL;
-					end
-					16'b0001_00xx_xxxx_xxxx: begin
-						/* CPSE */
-						pc_sel = PC_SEL_INC;
-						pmem_ce = 1'b1;
-						if(reg_equal)
-							next_state = SKIP;
-					end
-					16'b1111_11xx_xxxx_0xxx: begin
-						/* SBRC - SBRS */
-						pc_sel = PC_SEL_INC;
-						pmem_ce = 1'b1;
-						if(GPR_Rd_b == pmem_d[9])
-							next_state = SKIP;
-					end
-					/* SBIC, SBIS, SBI, CBI are not implemented */
-					16'b1111_0xxx_xxxx_xxxx: begin
-						/* BRBS - BRBC */
-						pmem_ce = 1'b1;
-						if(sreg_read ^ pmem_d[10]) begin
-							pc_sel = PC_SEL_KS;
-							next_state = STALL;
-						end else
-							pc_sel = PC_SEL_INC;
-					end
-					/* BREQ, BRNE, BRCS, BRCC, BRSH, BRLO, BRMI, BRPL, BRGE, BRLT,
-					 * BRHS, BRHC, BRTS, BRTC, BRVS, BRVC, BRIE, BRID are replaced
-					 * with BRBS/BRBC */
-					16'b1001_00xx_xxxx_1100, /*  X   */
-					16'b1001_00xx_xxxx_1101, /*  X+  */
-					16'b1001_00xx_xxxx_1110, /* -X   */
-					16'b1001_00xx_xxxx_1001, /*  Y+  */
-					16'b1001_00xx_xxxx_1010, /* -Y   */
-					16'b10x0_xxxx_xxxx_1xxx, /*  Y+q */
-					16'b1001_00xx_xxxx_0001, /*  Z+  */
-					16'b1001_00xx_xxxx_0010, /* -Z   */
-					16'b10x0_xxxx_xxxx_0xxx: /*  Z+q */
-					begin
-						casex({pmem_d[12], pmem_d[3:0]})
-							5'b1_1100: dmem_sel = DMEM_SEL_X;
-							5'b1_1101: dmem_sel = DMEM_SEL_XPLUS;
-							5'b1_1110: dmem_sel = DMEM_SEL_XMINUS;
-							5'b1_1001: dmem_sel = DMEM_SEL_YPLUS;
-							5'b1_1010: dmem_sel = DMEM_SEL_YMINUS;
-							5'b0_1xxx: dmem_sel = DMEM_SEL_YQ;
-							5'b1_0001: dmem_sel = DMEM_SEL_ZPLUS;
-							5'b1_0010: dmem_sel = DMEM_SEL_ZMINUS;
-							5'b0_0xxx: dmem_sel = DMEM_SEL_ZQ;
-						endcase
-						if(pmem_d[9]) begin
-							/* ST */
-							pc_sel = PC_SEL_INC;
-							pmem_ce = 1'b1;
-							dmem_we = 1'b1;
-						end else begin
-							/* LD */
-							next_state = WRITEBACK;
-						end
-					end
-					16'b1011_0xxx_xxxx_xxxx: begin
-						/* IN */
-						io_re = 1'b1;
-						next_state = WRITEBACK;
-					end
-					16'b1011_1xxx_xxxx_xxxx: begin
-						/* OUT */
-						io_we = 1'b1;
-						pc_sel = PC_SEL_INC;
-						pmem_ce = 1'b1;
-					end
-					16'b1001_00xx_xxxx_1111: begin
-						if(pmem_d[9]) begin
-							/* PUSH */
-							push = 1'b1;
-							dmem_sel = DMEM_SEL_SP_R;
-							dmem_we = 1'b1;
-							pc_sel = PC_SEL_INC;
-							pmem_ce = 1'b1;
-						end else begin
-							/* POP */
-							pop = 1'b1;
-							dmem_sel = DMEM_SEL_SP_R;
-							next_state = WRITEBACK;
-						end
-					end
-					16'b1001_00xx_xxxx_0000: begin
-						pc_sel = PC_SEL_INC;
-						pmem_ce = 1'b1;
-						if(pmem_d[9])
-							/* STS */
-							next_state = STS;
-						else
-							/* LDS */
-							next_state = LDS1;
-					end
-					16'b1001_0101_000x_1000: begin
-						/* RET / RETI */
-						dmem_sel = DMEM_SEL_SP_PCH;
-						pop = 1'b1;
-						if(pmem_d[4] == 1'b0)
-							next_state = RET1;
-						else
-							next_state = RETI1;
-					end
-					16'b1001_0101_1100_1000: begin
-						/* LPM */
-						pmem_selz = 1'b1;
-						pmem_ce = 1'b1;
-						next_state = LPM;
-					end
-					16'b1001_0100_0000_1001: begin
-						/* IJMP */
-						pc_sel = PC_SEL_Z;
-						next_state = STALL;
-					end
-					16'b1001_0101_0000_1001: begin
-						/* ICALL */
-						dmem_sel = DMEM_SEL_SP_PCL;
-						dmem_we = 1'b1;
-						push = 1'b1;
-						next_state = ICALL;
-					end
-					default: begin
-						pc_sel = PC_SEL_INC;
-						normal_en = 1'b1;
-						pmem_ce = 1'b1;
-					end
-				endcase
-			end
-		end
-		RCALL: begin
-			dmem_sel = DMEM_SEL_SP_PCH;
-			dmem_we = 1'b1;
-			push = 1'b1;
-			pc_sel = PC_SEL_KL;
-			next_state = STALL;
-		end
-		EXCEPTION: begin
-			dmem_sel = DMEM_SEL_SP_PCH;
-			dmem_we = 1'b1;
-			exception = 1'b1;
-			push = 1'b1;
-			pc_sel = PC_SEL_EX;
-			next_state = STALL;
-		end
-		ICALL: begin
-			dmem_sel = DMEM_SEL_SP_PCH;
-			dmem_we = 1'b1;
-			push = 1'b1;
-			pc_sel = PC_SEL_Z;
-			next_state = STALL;
-		end
-		RET1: begin
-			pc_sel = PC_SEL_DMEMH;
-			dmem_sel = DMEM_SEL_SP_PCL;
-			pop = 1'b1;
-			next_state = RET2;
-		end
-		RET2: begin
-			pc_sel = PC_SEL_DMEML;
-			next_state = RET3;
-		end
-		RET3: begin
-			pc_sel = PC_SEL_DEC;
-			next_state = STALL;
-		end
-		RETI1: begin
-			pc_sel = PC_SEL_DMEMH;
-			dmem_sel = DMEM_SEL_SP_PCL;
-			pop = 1'b1;
-			next_state = RETI2;
-		end
-		RETI2: begin
-			pc_sel = PC_SEL_DMEML;
-			next_state = RETI3;
-		end
-		RETI3: begin
-			pc_sel = PC_SEL_DEC;
-			next_state = RETI4;
-		end
-		RETI4: begin
-			pc_sel = PC_SEL_INC;
-			pmem_ce = 1'b1;
-			I_set = 1'b1;
-			next_state = NORMAL;
-		end
-		LPM: begin
-			lpm_en = 1'b1;
-			pc_sel = PC_SEL_INC;
-			pmem_ce = 1'b1;
-			next_state = NORMAL;
-		end
-		STS: begin
-			pc_sel = PC_SEL_INC;
-			pmem_ce = 1'b1;
-			dmem_sel = DMEM_SEL_PMEM;
-			dmem_we = 1'b1;
-			next_state = NORMAL;
-		end
-		LDS1: begin
-			dmem_sel = DMEM_SEL_PMEM;
-			regmem_ce = 1'b0;
-			next_state = LDS2;
-		end
-		LDS2: begin
-			pc_sel = PC_SEL_INC;
-			pmem_ce = 1'b1;
-			lds_writeback = 1'b1;
-			next_state = NORMAL;
-		end
-		SKIP: begin
-			pc_sel = PC_SEL_INC;
-			pmem_ce = 1'b1;
-			/* test for STS and LDS */
-			if((pmem_d[15:10] == 6'b100100) & (pmem_d[3:0] == 4'h0))
-				next_state = STALL; /* 2-word instruction, skip the second word as well */
-			else
-				next_state = NORMAL; /* 1-word instruction */
-		end
-		STALL: begin
-			pc_sel = PC_SEL_INC;
-			pmem_ce = 1'b1;
-			next_state = NORMAL;
-		end
-		WRITEBACK: begin
-			pmem_ce = 1'b1;
-			pc_sel = PC_SEL_INC;
-			normal_en = 1'b1;
-			next_state = NORMAL;
-		end
-	endcase
-end
-
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/work/sim/bench.v b/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/work/sim/bench.v
deleted file mode 100644
index a33a72f..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/softusb_navre/slpp_unit/work/sim/bench.v
+++ /dev/null
@@ -1,258 +0,0 @@
-
-module testbench;
-
-parameter pmem_width = 11;
-parameter dmem_width = 13;
-
-// navre inputs
-reg clk;
-reg rst;
-reg [15:0] pmem_d;
-reg [7:0] dmem_di;
-reg [7:0] io_di;
-reg [7:0] irq;
-
-// navre outputs
-wire pmem_ce;
-wire [pmem_width-1:0] pmem_a;
-wire dmem_we;
-wire [dmem_width-1:0] dmem_a;
-wire [7:0] dmem_do;
-wire io_re;
-wire io_we;
-wire [5:0] io_a;
-wire [7:0] io_do;
-wire [7:0] irq_ack;
-wire [pmem_width-1:0] dbg_pc;
-
-softusb_navre #(
-	pmem_width,
-	dmem_width
-) UUT (
-	clk,
-	rst,
-
-	pmem_ce,
-	pmem_a,
-	pmem_d,
-
-	dmem_we,
-	dmem_a,
-	dmem_di,
-	dmem_do,
-
-	io_re,
-	io_we,
-	io_a,
-	io_do,
-	io_di,
-
-	irq,
-	irq_ack,
-	dbg_pc
-);
-
-integer cycles;
-initial begin
-	clk <= 1;
-	rst <= 1;
-	cycles = 0;
-	while (cycles < 8) begin
-		#50; clk <= ~clk;
-		cycles = cycles + 1;
-		#50; clk <= ~clk;
-	end
-	rst <= #20 0;
-	forever begin
-		#50; clk <= ~clk;
-		cycles = cycles + 1;
-		#50; clk <= ~clk;
-		if (cycles == 10000) begin
-			$display("Reached limit of 10000 cpu cycles.");
-			$finish;
-		end
-	end
-end
-
-reg [15:0] addr;
-reg [15:0] pmem [2**pmem_width-1:0];
-reg [ 7:0] dmem [2**dmem_width-1:0];
-
-integer output_idx;
-reg [7:0] output_buf [1023:0];
-event output_eof;
-
-integer i;
-initial begin
-	for (i=0; i < 2**pmem_width; i = i+1) begin
-		pmem[i] = 0;
-	end
-	for (i=0; i < 2**dmem_width; i = i+1) begin
-		dmem[i] = 0;
-	end
-	pmem[   0] = 16'hc00c;
-pmem[   1] = 16'hc01b;
-pmem[   2] = 16'hc01a;
-pmem[   3] = 16'hc019;
-pmem[   4] = 16'hc018;
-pmem[   5] = 16'hc017;
-pmem[   6] = 16'hc016;
-pmem[   7] = 16'hc015;
-pmem[   8] = 16'hc014;
-pmem[   9] = 16'hc013;
-pmem[  10] = 16'hc012;
-pmem[  11] = 16'hc011;
-pmem[  12] = 16'hc010;
-pmem[  13] = 16'h2411;
-pmem[  14] = 16'hbe1f;
-pmem[  15] = 16'he5cf;
-pmem[  16] = 16'he0d2;
-pmem[  17] = 16'hbfde;
-pmem[  18] = 16'hbfcd;
-pmem[  19] = 16'he010;
-pmem[  20] = 16'he6a0;
-pmem[  21] = 16'he0b0;
-pmem[  22] = 16'hc001;
-pmem[  23] = 16'h921d;
-pmem[  24] = 16'h36a3;
-pmem[  25] = 16'h07b1;
-pmem[  26] = 16'hf7e1;
-pmem[  27] = 16'hd028;
-pmem[  28] = 16'hc059;
-pmem[  29] = 16'hcfe2;
-pmem[  30] = 16'h2fe8;
-pmem[  31] = 16'h95e6;
-pmem[  32] = 16'h95e6;
-pmem[  33] = 16'h95e6;
-pmem[  34] = 16'he0f0;
-pmem[  35] = 16'h5ae0;
-pmem[  36] = 16'h4fff;
-pmem[  37] = 16'h7087;
-pmem[  38] = 16'he021;
-pmem[  39] = 16'he030;
-pmem[  40] = 16'hc001;
-pmem[  41] = 16'h0f22;
-pmem[  42] = 16'h958a;
-pmem[  43] = 16'hf7ea;
-pmem[  44] = 16'h8180;
-pmem[  45] = 16'h2b82;
-pmem[  46] = 16'h8380;
-pmem[  47] = 16'h9508;
-pmem[  48] = 16'h2fe8;
-pmem[  49] = 16'h95e6;
-pmem[  50] = 16'h95e6;
-pmem[  51] = 16'h95e6;
-pmem[  52] = 16'he0f0;
-pmem[  53] = 16'h5ae0;
-pmem[  54] = 16'h4fff;
-pmem[  55] = 16'h8120;
-pmem[  56] = 16'he030;
-pmem[  57] = 16'h7087;
-pmem[  58] = 16'hc002;
-pmem[  59] = 16'h9535;
-pmem[  60] = 16'h9527;
-pmem[  61] = 16'h958a;
-pmem[  62] = 16'hf7e2;
-pmem[  63] = 16'h2f82;
-pmem[  64] = 16'h7081;
-pmem[  65] = 16'h9508;
-pmem[  66] = 16'hbd8a;
-pmem[  67] = 16'h9508;
-pmem[  68] = 16'h931f;
-pmem[  69] = 16'h93cf;
-pmem[  70] = 16'h93df;
-pmem[  71] = 16'he082;
-pmem[  72] = 16'hdff9;
-pmem[  73] = 16'he0c3;
-pmem[  74] = 16'he0d0;
-pmem[  75] = 16'h2f8d;
-pmem[  76] = 16'hdfe3;
-pmem[  77] = 16'h1181;
-pmem[  78] = 16'hc01b;
-pmem[  79] = 16'h2f8c;
-pmem[  80] = 16'hdff1;
-pmem[  81] = 16'h2f1c;
-pmem[  82] = 16'h0f11;
-pmem[  83] = 16'hff10;
-pmem[  84] = 16'hc013;
-pmem[  85] = 16'h2f41;
-pmem[  86] = 16'he050;
-pmem[  87] = 16'h2f24;
-pmem[  88] = 16'h2f35;
-pmem[  89] = 16'h5023;
-pmem[  90] = 16'h0931;
-pmem[  91] = 16'hff37;
-pmem[  92] = 16'hc004;
-pmem[  93] = 16'h2f24;
-pmem[  94] = 16'h2f35;
-pmem[  95] = 16'h5022;
-pmem[  96] = 16'h0931;
-pmem[  97] = 16'h2f82;
-pmem[  98] = 16'h2f93;
-pmem[  99] = 16'h9595;
-pmem[ 100] = 16'h9587;
-pmem[ 101] = 16'h3188;
-pmem[ 102] = 16'hf418;
-pmem[ 103] = 16'hdfb6;
-pmem[ 104] = 16'h0f1c;
-pmem[ 105] = 16'hcfe9;
-pmem[ 106] = 16'h5fdf;
-pmem[ 107] = 16'h5fce;
-pmem[ 108] = 16'h31d8;
-pmem[ 109] = 16'hf6e9;
-pmem[ 110] = 16'he080;
-pmem[ 111] = 16'hdfd2;
-pmem[ 112] = 16'he080;
-pmem[ 113] = 16'he090;
-pmem[ 114] = 16'h91df;
-pmem[ 115] = 16'h91cf;
-pmem[ 116] = 16'h911f;
-pmem[ 117] = 16'h9508;
-pmem[ 118] = 16'h94f8;
-pmem[ 119] = 16'hcfff;
-	output_idx = 0;
-end
-
-always @(posedge clk) begin
-	if (rst) begin
-		pmem_d <= 0;
-		irq <= 0;
-	end else if (pmem_ce) begin
-		addr = pmem_a * 2;
-		$display("+LOG+ %t PR @%x %x", $time, addr, pmem[pmem_a]);
-		pmem_d <= pmem[pmem_a];
-	end
-	if (dmem_we) begin
-		addr = dmem_a;
-		$display("+LOG+ %t DW @%x   %x", $time, addr, dmem_do);
-		dmem[dmem_a] <= dmem_do;
-	end
-	if (io_we && io_a == 42) begin
-		addr = io_a;
-		$display("+LOG+ %t IO @%x   %x  <---", $time, addr, io_do);
-		if (io_do == 0) begin
-			-> output_eof;
-		end else begin
-			output_buf[output_idx] = io_do;
-			output_idx = output_idx + 1;
-		end
-	end
-	dmem_di <= dmem[dmem_a];
-	io_di <= 0;
-end
-
-always @(output_eof) begin
-	#1001;
-	$display("Got EOF marker on IO port.");
-	for (i = 0; i < output_idx; i = i + 1) begin
-		$display("+OUT+ %t %d", $time, output_buf[i]);
-	end
-	$finish;
-end
-
-initial begin
-	// $dumpfile("bench.vcd");
-	// $dumpvars(0, testbench);
-end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/surelog.log b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/surelog.log
deleted file mode 100644
index 8423876..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/surelog.log
+++ /dev/null
@@ -1,76 +0,0 @@
-********************************************
-*  SURELOG System Verilog Compiler/Linter  *
-********************************************
-
-Copyright (c) 2017-2019 ACE Cloud,
-Authorized used only.
-
-VERSION: 0.05
-BUILT  : Nov  3 2019
-DATE   : 2019-11-03.21:44:10
-COMMAND: -writepp -parse -mt max -nopython -fileunit rtl/data.v rtl/debounce.v rtl/front_rom.v rtl/pong_graph.v rtl/text_graph.v rtl/top.v rtl/vga_sync.v sim/bench.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
-
-[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
-
-[INFO :CM0024] Executing with 4 threads.
-
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[WARNI:PP0103] sim/bench.v:5 Undefining an unknown macro "WRITE_FRAMES_PPM".
-
-[WARNI:PA0205] rtl/front_rom.v:1 No timescale set for "font_rom".
-
-[WARNI:PA0205] rtl/text_graph.v:1 No timescale set for "text_graph".
-
-[WARNI:PA0205] rtl/vga_sync.v:1 No timescale set for "vga_sync".
-
-[WARNI:PA0205] sim/bench.v:7 No timescale set for "testbench".
-
-[INFO :CP0300] Compilation...
-
-[INFO :CP0303] rtl/debounce.v:3 Compile module "work@debounce".
-
-[INFO :CP0303] sim/bench.v:7 Compile module "work@testbench".
-
-[INFO :CP0303] rtl/front_rom.v:1 Compile module "work@font_rom".
-
-[INFO :CP0303] rtl/pong_graph.v:3 Compile module "work@pong_graph".
-
-[INFO :CP0303] rtl/text_graph.v:1 Compile module "work@text_graph".
-
-[INFO :CP0303] rtl/vga_sync.v:1 Compile module "work@vga_sync".
-
-[INFO :CP0303] rtl/top.v:3 Compile module "work@top".
-
-[NOTE :CP0309] rtl/top.v:7 Implicit port type (wire) for "vsync".
-
-[NOTE :CP0309] rtl/pong_graph.v:9 Implicit port type (wire) for "hit_left",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/vga_sync.v:4 Implicit port type (wire) for "vsync",
-there are 3 more instances of this message.
-
-[INFO :EL0526] Design Elaboration...
-
-[NOTE :EL0503] sim/bench.v:7 Top level module "work@testbench".
-
-[WARNI:EL0505] rtl/data.v:1 Multiply defined module "work@font_rom",
-               rtl/front_rom.v:1 previous definition.
-
-[NOTE :EL0508] Nb Top level modules: 1.
-
-[NOTE :EL0509] Max instance depth: 4.
-
-[NOTE :EL0510] Nb instances: 10.
-
-[NOTE :EL0511] Nb leaf instances: 1.
-
-[  FATAL] : 0
-[  ERROR] : 0
-[WARNING] : 6
-[   NOTE] : 8
-
-********************************************
-*   End SURELOG SVerilog Compiler/Linter   *
-********************************************
-
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/data.v b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/data.v
deleted file mode 100644
index a3f3af3..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/data.v
+++ /dev/null
@@ -1,2192 +0,0 @@
-module font_rom
-   (
-    input wire clk,
-    input wire [10:0] addr,
-    output reg [7:0] data
-   );
-   reg [10:0] addr_reg; 
-	
-   always @(posedge clk) 
-      addr_reg <= addr;
-      
-   always @*
-      case (addr_reg)
-         //code x00
-         11'h000: data = 8'b00000000; // 
-         11'h001: data = 8'b00000000; // 
-         11'h002: data = 8'b00000000; // 
-         11'h003: data = 8'b00000000; // 
-         11'h004: data = 8'b00000000; // 
-         11'h005: data = 8'b00000000; // 
-         11'h006: data = 8'b00000000; // 
-         11'h007: data = 8'b00000000; // 
-         11'h008: data = 8'b00000000; // 
-         11'h009: data = 8'b00000000; // 
-         11'h00a: data = 8'b00000000; // 
-         11'h00b: data = 8'b00000000; // 
-         11'h00c: data = 8'b00000000; // 
-         11'h00d: data = 8'b00000000; // 
-         11'h00e: data = 8'b00000000; // 
-         11'h00f: data = 8'b00000000; // 
-         //code x01
-         11'h010: data = 8'b00000000; // 
-         11'h011: data = 8'b00000000; // 
-         11'h012: data = 8'b01111110; //  ******
-         11'h013: data = 8'b10000001; // *      *
-         11'h014: data = 8'b10100101; // * *  * *
-         11'h015: data = 8'b10000001; // *      *
-         11'h016: data = 8'b10000001; // *      *
-         11'h017: data = 8'b10111101; // * **** *
-         11'h018: data = 8'b10011001; // *  **  *
-         11'h019: data = 8'b10000001; // *      *
-         11'h01a: data = 8'b10000001; // *      *
-         11'h01b: data = 8'b01111110; //  ******
-         11'h01c: data = 8'b00000000; // 
-         11'h01d: data = 8'b00000000; // 
-         11'h01e: data = 8'b00000000; // 
-         11'h01f: data = 8'b00000000; // 
-         //code x02
-         11'h020: data = 8'b00000000; // 
-         11'h021: data = 8'b00000000; // 
-         11'h022: data = 8'b01111110; //  ******
-         11'h023: data = 8'b11111111; // ********
-         11'h024: data = 8'b11011011; // ** ** **
-         11'h025: data = 8'b11111111; // ********
-         11'h026: data = 8'b11111111; // ********
-         11'h027: data = 8'b11000011; // **    **
-         11'h028: data = 8'b11100111; // ***  ***
-         11'h029: data = 8'b11111111; // ********
-         11'h02a: data = 8'b11111111; // ********
-         11'h02b: data = 8'b01111110; //  ******
-         11'h02c: data = 8'b00000000; // 
-         11'h02d: data = 8'b00000000; // 
-         11'h02e: data = 8'b00000000; // 
-         11'h02f: data = 8'b00000000; // 
-         //code x03
-         11'h030: data = 8'b00000000; // 
-         11'h031: data = 8'b00000000; // 
-         11'h032: data = 8'b00000000; // 
-         11'h033: data = 8'b00000000; // 
-         11'h034: data = 8'b01101100; //  ** **
-         11'h035: data = 8'b11111110; // *******
-         11'h036: data = 8'b11111110; // *******
-         11'h037: data = 8'b11111110; // *******
-         11'h038: data = 8'b11111110; // *******
-         11'h039: data = 8'b01111100; //  *****
-         11'h03a: data = 8'b00111000; //   ***
-         11'h03b: data = 8'b00010000; //    *
-         11'h03c: data = 8'b00000000; // 
-         11'h03d: data = 8'b00000000; // 
-         11'h03e: data = 8'b00000000; // 
-         11'h03f: data = 8'b00000000; // 
-         //code x04
-         11'h040: data = 8'b00000000; // 
-         11'h041: data = 8'b00000000; // 
-         11'h042: data = 8'b00000000; // 
-         11'h043: data = 8'b00000000; // 
-         11'h044: data = 8'b00010000; //    *
-         11'h045: data = 8'b00111000; //   ***
-         11'h046: data = 8'b01111100; //  *****
-         11'h047: data = 8'b11111110; // *******
-         11'h048: data = 8'b01111100; //  *****
-         11'h049: data = 8'b00111000; //   ***
-         11'h04a: data = 8'b00010000; //    *
-         11'h04b: data = 8'b00000000; // 
-         11'h04c: data = 8'b00000000; // 
-         11'h04d: data = 8'b00000000; // 
-         11'h04e: data = 8'b00000000; // 
-         11'h04f: data = 8'b00000000; // 
-         //code x05
-         11'h050: data = 8'b00000000; // 
-         11'h051: data = 8'b00000000; // 
-         11'h052: data = 8'b00000000; // 
-         11'h053: data = 8'b00011000; //    **
-         11'h054: data = 8'b00111100; //   ****
-         11'h055: data = 8'b00111100; //   ****
-         11'h056: data = 8'b11100111; // ***  ***
-         11'h057: data = 8'b11100111; // ***  ***
-         11'h058: data = 8'b11100111; // ***  ***
-         11'h059: data = 8'b00011000; //    **
-         11'h05a: data = 8'b00011000; //    **
-         11'h05b: data = 8'b00111100; //   ****
-         11'h05c: data = 8'b00000000; // 
-         11'h05d: data = 8'b00000000; // 
-         11'h05e: data = 8'b00000000; // 
-         11'h05f: data = 8'b00000000; // 
-         //code x06
-         11'h060: data = 8'b00000000; // 
-         11'h061: data = 8'b00000000; // 
-         11'h062: data = 8'b00000000; // 
-         11'h063: data = 8'b00011000; //    **
-         11'h064: data = 8'b00111100; //   ****
-         11'h065: data = 8'b01111110; //  ******
-         11'h066: data = 8'b11111111; // ********
-         11'h067: data = 8'b11111111; // ********
-         11'h068: data = 8'b01111110; //  ******
-         11'h069: data = 8'b00011000; //    **
-         11'h06a: data = 8'b00011000; //    **
-         11'h06b: data = 8'b00111100; //   ****
-         11'h06c: data = 8'b00000000; // 
-         11'h06d: data = 8'b00000000; // 
-         11'h06e: data = 8'b00000000; // 
-         11'h06f: data = 8'b00000000; // 
-         //code x07
-         11'h070: data = 8'b00000000; // 
-         11'h071: data = 8'b00000000; // 
-         11'h072: data = 8'b00000000; // 
-         11'h073: data = 8'b00000000; // 
-         11'h074: data = 8'b00000000; // 
-         11'h075: data = 8'b00000000; // 
-         11'h076: data = 8'b00011000; //    **
-         11'h077: data = 8'b00111100; //   ****
-         11'h078: data = 8'b00111100; //   ****
-         11'h079: data = 8'b00011000; //    **
-         11'h07a: data = 8'b00000000; // 
-         11'h07b: data = 8'b00000000; // 
-         11'h07c: data = 8'b00000000; // 
-         11'h07d: data = 8'b00000000; // 
-         11'h07e: data = 8'b00000000; // 
-         11'h07f: data = 8'b00000000; // 
-         //code x08
-         11'h080: data = 8'b11111111; // ********
-         11'h081: data = 8'b11111111; // ********
-         11'h082: data = 8'b11111111; // ********
-         11'h083: data = 8'b11111111; // ********
-         11'h084: data = 8'b11111111; // ********
-         11'h085: data = 8'b11111111; // ********
-         11'h086: data = 8'b11100111; // ***  ***
-         11'h087: data = 8'b11000011; // **    **
-         11'h088: data = 8'b11000011; // **    **
-         11'h089: data = 8'b11100111; // ***  ***
-         11'h08a: data = 8'b11111111; // ********
-         11'h08b: data = 8'b11111111; // ********
-         11'h08c: data = 8'b11111111; // ********
-         11'h08d: data = 8'b11111111; // ********
-         11'h08e: data = 8'b11111111; // ********
-         11'h08f: data = 8'b11111111; // ********
-         //code x09
-         11'h090: data = 8'b00000000; // 
-         11'h091: data = 8'b00000000; // 
-         11'h092: data = 8'b00000000; // 
-         11'h093: data = 8'b00000000; // 
-         11'h094: data = 8'b00000000; // 
-         11'h095: data = 8'b00111100; //   ****
-         11'h096: data = 8'b01100110; //  **  **
-         11'h097: data = 8'b01000010; //  *    *
-         11'h098: data = 8'b01000010; //  *    *
-         11'h099: data = 8'b01100110; //  **  **
-         11'h09a: data = 8'b00111100; //   ****
-         11'h09b: data = 8'b00000000; // 
-         11'h09c: data = 8'b00000000; // 
-         11'h09d: data = 8'b00000000; // 
-         11'h09e: data = 8'b00000000; // 
-         11'h09f: data = 8'b00000000; // 
-         //code x0a
-         11'h0a0: data = 8'b11111111; // ********
-         11'h0a1: data = 8'b11111111; // ********
-         11'h0a2: data = 8'b11111111; // ********
-         11'h0a3: data = 8'b11111111; // ********
-         11'h0a4: data = 8'b11111111; // ********
-         11'h0a5: data = 8'b11000011; // **    **
-         11'h0a6: data = 8'b10011001; // *  **  *
-         11'h0a7: data = 8'b10111101; // * **** *
-         11'h0a8: data = 8'b10111101; // * **** *
-         11'h0a9: data = 8'b10011001; // *  **  *
-         11'h0aa: data = 8'b11000011; // **    **
-         11'h0ab: data = 8'b11111111; // ********
-         11'h0ac: data = 8'b11111111; // ********
-         11'h0ad: data = 8'b11111111; // ********
-         11'h0ae: data = 8'b11111111; // ********
-         11'h0af: data = 8'b11111111; // ********
-         //code x0b
-         11'h0b0: data = 8'b00000000; // 
-         11'h0b1: data = 8'b00000000; // 
-         11'h0b2: data = 8'b00011110; //    ****
-         11'h0b3: data = 8'b00001110; //     ***
-         11'h0b4: data = 8'b00011010; //    ** *
-         11'h0b5: data = 8'b00110010; //   **  *
-         11'h0b6: data = 8'b01111000; //  ****
-         11'h0b7: data = 8'b11001100; // **  **
-         11'h0b8: data = 8'b11001100; // **  **
-         11'h0b9: data = 8'b11001100; // **  **
-         11'h0ba: data = 8'b11001100; // **  **
-         11'h0bb: data = 8'b01111000; //  ****
-         11'h0bc: data = 8'b00000000; // 
-         11'h0bd: data = 8'b00000000; // 
-         11'h0be: data = 8'b00000000; // 
-         11'h0bf: data = 8'b00000000; // 
-         //code x0c
-         11'h0c0: data = 8'b00000000; // 
-         11'h0c1: data = 8'b00000000; // 
-         11'h0c2: data = 8'b00111100; //   ****
-         11'h0c3: data = 8'b01100110; //  **  **
-         11'h0c4: data = 8'b01100110; //  **  **
-         11'h0c5: data = 8'b01100110; //  **  **
-         11'h0c6: data = 8'b01100110; //  **  **
-         11'h0c7: data = 8'b00111100; //   ****
-         11'h0c8: data = 8'b00011000; //    **
-         11'h0c9: data = 8'b01111110; //  ******
-         11'h0ca: data = 8'b00011000; //    **
-         11'h0cb: data = 8'b00011000; //    **
-         11'h0cc: data = 8'b00000000; // 
-         11'h0cd: data = 8'b00000000; // 
-         11'h0ce: data = 8'b00000000; // 
-         11'h0cf: data = 8'b00000000; // 
-         //code x0d
-         11'h0d0: data = 8'b00000000; // 
-         11'h0d1: data = 8'b00000000; // 
-         11'h0d2: data = 8'b00111111; //   ******
-         11'h0d3: data = 8'b00110011; //   **  **
-         11'h0d4: data = 8'b00111111; //   ******
-         11'h0d5: data = 8'b00110000; //   **
-         11'h0d6: data = 8'b00110000; //   **
-         11'h0d7: data = 8'b00110000; //   **
-         11'h0d8: data = 8'b00110000; //   **
-         11'h0d9: data = 8'b01110000; //  ***
-         11'h0da: data = 8'b11110000; // ****
-         11'h0db: data = 8'b11100000; // ***
-         11'h0dc: data = 8'b00000000; // 
-         11'h0dd: data = 8'b00000000; // 
-         11'h0de: data = 8'b00000000; // 
-         11'h0df: data = 8'b00000000; // 
-         //code x0e
-         11'h0e0: data = 8'b00000000; // 
-         11'h0e1: data = 8'b00000000; // 
-         11'h0e2: data = 8'b01111111; //  *******
-         11'h0e3: data = 8'b01100011; //  **   **
-         11'h0e4: data = 8'b01111111; //  *******
-         11'h0e5: data = 8'b01100011; //  **   **
-         11'h0e6: data = 8'b01100011; //  **   **
-         11'h0e7: data = 8'b01100011; //  **   **
-         11'h0e8: data = 8'b01100011; //  **   **
-         11'h0e9: data = 8'b01100111; //  **  ***
-         11'h0ea: data = 8'b11100111; // ***  ***
-         11'h0eb: data = 8'b11100110; // ***  **
-         11'h0ec: data = 8'b11000000; // **
-         11'h0ed: data = 8'b00000000; // 
-         11'h0ee: data = 8'b00000000; // 
-         11'h0ef: data = 8'b00000000; // 
-         //code x0f
-         11'h0f0: data = 8'b00000000; // 
-         11'h0f1: data = 8'b00000000; // 
-         11'h0f2: data = 8'b00000000; // 
-         11'h0f3: data = 8'b00011000; //    **
-         11'h0f4: data = 8'b00011000; //    **
-         11'h0f5: data = 8'b11011011; // ** ** **
-         11'h0f6: data = 8'b00111100; //   ****
-         11'h0f7: data = 8'b11100111; // ***  ***
-         11'h0f8: data = 8'b00111100; //   ****
-         11'h0f9: data = 8'b11011011; // ** ** **
-         11'h0fa: data = 8'b00011000; //    **
-         11'h0fb: data = 8'b00011000; //    **
-         11'h0fc: data = 8'b00000000; // 
-         11'h0fd: data = 8'b00000000; // 
-         11'h0fe: data = 8'b00000000; // 
-         11'h0ff: data = 8'b00000000; // 
-         //code x10
-         11'h100: data = 8'b00000000; // 
-         11'h101: data = 8'b10000000; // *
-         11'h102: data = 8'b11000000; // **
-         11'h103: data = 8'b11100000; // ***
-         11'h104: data = 8'b11110000; // ****
-         11'h105: data = 8'b11111000; // *****
-         11'h106: data = 8'b11111110; // *******
-         11'h107: data = 8'b11111000; // *****
-         11'h108: data = 8'b11110000; // ****
-         11'h109: data = 8'b11100000; // ***
-         11'h10a: data = 8'b11000000; // **
-         11'h10b: data = 8'b10000000; // *
-         11'h10c: data = 8'b00000000; // 
-         11'h10d: data = 8'b00000000; // 
-         11'h10e: data = 8'b00000000; // 
-         11'h10f: data = 8'b00000000; // 
-         //code x11
-         11'h110: data = 8'b00000000; // 
-         11'h111: data = 8'b00000010; //       *
-         11'h112: data = 8'b00000110; //      **
-         11'h113: data = 8'b00001110; //     ***
-         11'h114: data = 8'b00011110; //    ****
-         11'h115: data = 8'b00111110; //   *****
-         11'h116: data = 8'b11111110; // *******
-         11'h117: data = 8'b00111110; //   *****
-         11'h118: data = 8'b00011110; //    ****
-         11'h119: data = 8'b00001110; //     ***
-         11'h11a: data = 8'b00000110; //      **
-         11'h11b: data = 8'b00000010; //       *
-         11'h11c: data = 8'b00000000; // 
-         11'h11d: data = 8'b00000000; // 
-         11'h11e: data = 8'b00000000; // 
-         11'h11f: data = 8'b00000000; // 
-         //code x12
-         11'h120: data = 8'b00000000; // 
-         11'h121: data = 8'b00000000; // 
-         11'h122: data = 8'b00011000; //    **
-         11'h123: data = 8'b00111100; //   ****
-         11'h124: data = 8'b01111110; //  ******
-         11'h125: data = 8'b00011000; //    **
-         11'h126: data = 8'b00011000; //    **
-         11'h127: data = 8'b00011000; //    **
-         11'h128: data = 8'b01111110; //  ******
-         11'h129: data = 8'b00111100; //   ****
-         11'h12a: data = 8'b00011000; //    **
-         11'h12b: data = 8'b00000000; // 
-         11'h12c: data = 8'b00000000; // 
-         11'h12d: data = 8'b00000000; // 
-         11'h12e: data = 8'b00000000; // 
-         11'h12f: data = 8'b00000000; // 
-         //code x13
-         11'h130: data = 8'b00000000; // 
-         11'h131: data = 8'b00000000; // 
-         11'h132: data = 8'b01100110; //  **  **
-         11'h133: data = 8'b01100110; //  **  **
-         11'h134: data = 8'b01100110; //  **  **
-         11'h135: data = 8'b01100110; //  **  **
-         11'h136: data = 8'b01100110; //  **  **
-         11'h137: data = 8'b01100110; //  **  **
-         11'h138: data = 8'b01100110; //  **  **
-         11'h139: data = 8'b00000000; // 
-         11'h13a: data = 8'b01100110; //  **  **
-         11'h13b: data = 8'b01100110; //  **  **
-         11'h13c: data = 8'b00000000; // 
-         11'h13d: data = 8'b00000000; // 
-         11'h13e: data = 8'b00000000; // 
-         11'h13f: data = 8'b00000000; // 
-         //code x14
-         11'h140: data = 8'b00000000; // 
-         11'h141: data = 8'b00000000; // 
-         11'h142: data = 8'b01111111; //  *******
-         11'h143: data = 8'b11011011; // ** ** **
-         11'h144: data = 8'b11011011; // ** ** **
-         11'h145: data = 8'b11011011; // ** ** **
-         11'h146: data = 8'b01111011; //  **** **
-         11'h147: data = 8'b00011011; //    ** **
-         11'h148: data = 8'b00011011; //    ** **
-         11'h149: data = 8'b00011011; //    ** **
-         11'h14a: data = 8'b00011011; //    ** **
-         11'h14b: data = 8'b00011011; //    ** **
-         11'h14c: data = 8'b00000000; // 
-         11'h14d: data = 8'b00000000; // 
-         11'h14e: data = 8'b00000000; // 
-         11'h14f: data = 8'b00000000; // 
-         //code x15
-         11'h150: data = 8'b00000000; // 
-         11'h151: data = 8'b01111100; //  *****
-         11'h152: data = 8'b11000110; // **   **
-         11'h153: data = 8'b01100000; //  **
-         11'h154: data = 8'b00111000; //   ***
-         11'h155: data = 8'b01101100; //  ** **
-         11'h156: data = 8'b11000110; // **   **
-         11'h157: data = 8'b11000110; // **   **
-         11'h158: data = 8'b01101100; //  ** **
-         11'h159: data = 8'b00111000; //   ***
-         11'h15a: data = 8'b00001100; //     **
-         11'h15b: data = 8'b11000110; // **   **
-         11'h15c: data = 8'b01111100; //  *****
-         11'h15d: data = 8'b00000000; // 
-         11'h15e: data = 8'b00000000; // 
-         11'h15f: data = 8'b00000000; // 
-         //code x16
-         11'h160: data = 8'b00000000; // 
-         11'h161: data = 8'b00000000; // 
-         11'h162: data = 8'b00000000; // 
-         11'h163: data = 8'b00000000; // 
-         11'h164: data = 8'b00000000; // 
-         11'h165: data = 8'b00000000; // 
-         11'h166: data = 8'b00000000; // 
-         11'h167: data = 8'b00000000; // 
-         11'h168: data = 8'b11111110; // *******
-         11'h169: data = 8'b11111110; // *******
-         11'h16a: data = 8'b11111110; // *******
-         11'h16b: data = 8'b11111110; // *******
-         11'h16c: data = 8'b00000000; // 
-         11'h16d: data = 8'b00000000; // 
-         11'h16e: data = 8'b00000000; // 
-         11'h16f: data = 8'b00000000; // 
-         //code x17
-         11'h170: data = 8'b00000000; // 
-         11'h171: data = 8'b00000000; // 
-         11'h172: data = 8'b00011000; //    **
-         11'h173: data = 8'b00111100; //   ****
-         11'h174: data = 8'b01111110; //  ******
-         11'h175: data = 8'b00011000; //    **
-         11'h176: data = 8'b00011000; //    **
-         11'h177: data = 8'b00011000; //    **
-         11'h178: data = 8'b01111110; //  ******
-         11'h179: data = 8'b00111100; //   ****
-         11'h17a: data = 8'b00011000; //    **
-         11'h17b: data = 8'b01111110; //  ******
-         11'h17c: data = 8'b00110000; // 
-         11'h17d: data = 8'b00000000; // 
-         11'h17e: data = 8'b00000000; // 
-         11'h17f: data = 8'b00000000; // 
-         //code x18
-         11'h180: data = 8'b00000000; // 
-         11'h181: data = 8'b00000000; // 
-         11'h182: data = 8'b00011000; //    **
-         11'h183: data = 8'b00111100; //   ****
-         11'h184: data = 8'b01111110; //  ******
-         11'h185: data = 8'b00011000; //    **
-         11'h186: data = 8'b00011000; //    **
-         11'h187: data = 8'b00011000; //    **
-         11'h188: data = 8'b00011000; //    **
-         11'h189: data = 8'b00011000; //    **
-         11'h18a: data = 8'b00011000; //    **
-         11'h18b: data = 8'b00011000; //    **
-         11'h18c: data = 8'b00000000; // 
-         11'h18d: data = 8'b00000000; // 
-         11'h18e: data = 8'b00000000; // 
-         11'h18f: data = 8'b00000000; // 
-         //code x19
-         11'h190: data = 8'b00000000; // 
-         11'h191: data = 8'b00000000; // 
-         11'h192: data = 8'b00011000; //    **
-         11'h193: data = 8'b00011000; //    **
-         11'h194: data = 8'b00011000; //    **
-         11'h195: data = 8'b00011000; //    **
-         11'h196: data = 8'b00011000; //    **
-         11'h197: data = 8'b00011000; //    **
-         11'h198: data = 8'b00011000; //    **
-         11'h199: data = 8'b01111110; //  ******
-         11'h19a: data = 8'b00111100; //   ****
-         11'h19b: data = 8'b00011000; //    **
-         11'h19c: data = 8'b00000000; // 
-         11'h19d: data = 8'b00000000; // 
-         11'h19e: data = 8'b00000000; // 
-         11'h19f: data = 8'b00000000; // 
-         //code x1a
-         11'h1a0: data = 8'b00000000; // 
-         11'h1a1: data = 8'b00000000; // 
-         11'h1a2: data = 8'b00000000; // 
-         11'h1a3: data = 8'b00000000; // 
-         11'h1a4: data = 8'b00000000; // 
-         11'h1a5: data = 8'b00011000; //    **
-         11'h1a6: data = 8'b00001100; //     **
-         11'h1a7: data = 8'b11111110; // *******
-         11'h1a8: data = 8'b00001100; //     **
-         11'h1a9: data = 8'b00011000; //    **
-         11'h1aa: data = 8'b00000000; // 
-         11'h1ab: data = 8'b00000000; // 
-         11'h1ac: data = 8'b00000000; // 
-         11'h1ad: data = 8'b00000000; // 
-         11'h1ae: data = 8'b00000000; // 
-         11'h1af: data = 8'b00000000; // 
-         //code x1b
-         11'h1b0: data = 8'b00000000; // 
-         11'h1b1: data = 8'b00000000; // 
-         11'h1b2: data = 8'b00000000; // 
-         11'h1b3: data = 8'b00000000; // 
-         11'h1b4: data = 8'b00000000; // 
-         11'h1b5: data = 8'b00110000; //   **
-         11'h1b6: data = 8'b01100000; //  **
-         11'h1b7: data = 8'b11111110; // *******
-         11'h1b8: data = 8'b01100000; //  **
-         11'h1b9: data = 8'b00110000; //   **
-         11'h1ba: data = 8'b00000000; // 
-         11'h1bb: data = 8'b00000000; // 
-         11'h1bc: data = 8'b00000000; // 
-         11'h1bd: data = 8'b00000000; // 
-         11'h1be: data = 8'b00000000; // 
-         11'h1bf: data = 8'b00000000; // 
-         //code x1c
-         11'h1c0: data = 8'b00000000; // 
-         11'h1c1: data = 8'b00000000; // 
-         11'h1c2: data = 8'b00000000; // 
-         11'h1c3: data = 8'b00000000; // 
-         11'h1c4: data = 8'b00000000; // 
-         11'h1c5: data = 8'b00000000; // 
-         11'h1c6: data = 8'b11000000; // **
-         11'h1c7: data = 8'b11000000; // **
-         11'h1c8: data = 8'b11000000; // **
-         11'h1c9: data = 8'b11111110; // *******
-         11'h1ca: data = 8'b00000000; // 
-         11'h1cb: data = 8'b00000000; // 
-         11'h1cc: data = 8'b00000000; // 
-         11'h1cd: data = 8'b00000000; // 
-         11'h1ce: data = 8'b00000000; // 
-         11'h1cf: data = 8'b00000000; // 
-         //code x1d
-         11'h1d0: data = 8'b00000000; // 
-         11'h1d1: data = 8'b00000000; // 
-         11'h1d2: data = 8'b00000000; // 
-         11'h1d3: data = 8'b00000000; // 
-         11'h1d4: data = 8'b00000000; // 
-         11'h1d5: data = 8'b00100100; //   *  *
-         11'h1d6: data = 8'b01100110; //  **  **
-         11'h1d7: data = 8'b11111111; // ********
-         11'h1d8: data = 8'b01100110; //  **  **
-         11'h1d9: data = 8'b00100100; //   *  *
-         11'h1da: data = 8'b00000000; // 
-         11'h1db: data = 8'b00000000; // 
-         11'h1dc: data = 8'b00000000; // 
-         11'h1dd: data = 8'b00000000; // 
-         11'h1de: data = 8'b00000000; // 
-         11'h1df: data = 8'b00000000; // 
-         //code x1e
-         11'h1e0: data = 8'b00000000; // 
-         11'h1e1: data = 8'b00000000; // 
-         11'h1e2: data = 8'b00000000; // 
-         11'h1e3: data = 8'b00000000; // 
-         11'h1e4: data = 8'b00010000; //    *
-         11'h1e5: data = 8'b00111000; //   ***
-         11'h1e6: data = 8'b00111000; //   ***
-         11'h1e7: data = 8'b01111100; //  *****
-         11'h1e8: data = 8'b01111100; //  *****
-         11'h1e9: data = 8'b11111110; // *******
-         11'h1ea: data = 8'b11111110; // *******
-         11'h1eb: data = 8'b00000000; // 
-         11'h1ec: data = 8'b00000000; // 
-         11'h1ed: data = 8'b00000000; // 
-         11'h1ee: data = 8'b00000000; // 
-         11'h1ef: data = 8'b00000000; // 
-         //code x1f
-         11'h1f0: data = 8'b00000000; // 
-         11'h1f1: data = 8'b00000000; // 
-         11'h1f2: data = 8'b00000000; // 
-         11'h1f3: data = 8'b00000000; // 
-         11'h1f4: data = 8'b11111110; // *******
-         11'h1f5: data = 8'b11111110; // *******
-         11'h1f6: data = 8'b01111100; //  *****
-         11'h1f7: data = 8'b01111100; //  *****
-         11'h1f8: data = 8'b00111000; //   ***
-         11'h1f9: data = 8'b00111000; //   ***
-         11'h1fa: data = 8'b00010000; //    *
-         11'h1fb: data = 8'b00000000; // 
-         11'h1fc: data = 8'b00000000; // 
-         11'h1fd: data = 8'b00000000; // 
-         11'h1fe: data = 8'b00000000; // 
-         11'h1ff: data = 8'b00000000; // 
-         //code x20
-         11'h200: data = 8'b00000000; // 
-         11'h201: data = 8'b00000000; // 
-         11'h202: data = 8'b00000000; // 
-         11'h203: data = 8'b00000000; // 
-         11'h204: data = 8'b00000000; // 
-         11'h205: data = 8'b00000000; // 
-         11'h206: data = 8'b00000000; // 
-         11'h207: data = 8'b00000000; // 
-         11'h208: data = 8'b00000000; // 
-         11'h209: data = 8'b00000000; // 
-         11'h20a: data = 8'b00000000; // 
-         11'h20b: data = 8'b00000000; // 
-         11'h20c: data = 8'b00000000; // 
-         11'h20d: data = 8'b00000000; // 
-         11'h20e: data = 8'b00000000; // 
-         11'h20f: data = 8'b00000000; // 
-         //code x21
-         11'h210: data = 8'b00000000; // 
-         11'h211: data = 8'b00000000; // 
-         11'h212: data = 8'b00011000; //    **
-         11'h213: data = 8'b00111100; //   ****
-         11'h214: data = 8'b00111100; //   ****
-         11'h215: data = 8'b00111100; //   ****
-         11'h216: data = 8'b00011000; //    **
-         11'h217: data = 8'b00011000; //    **
-         11'h218: data = 8'b00011000; //    **
-         11'h219: data = 8'b00000000; // 
-         11'h21a: data = 8'b00011000; //    **
-         11'h21b: data = 8'b00011000; //    **
-         11'h21c: data = 8'b00000000; // 
-         11'h21d: data = 8'b00000000; // 
-         11'h21e: data = 8'b00000000; // 
-         11'h21f: data = 8'b00000000; // 
-         //code x22
-         11'h220: data = 8'b00000000; // 
-         11'h221: data = 8'b01100110; //  **  **
-         11'h222: data = 8'b01100110; //  **  **
-         11'h223: data = 8'b01100110; //  **  **
-         11'h224: data = 8'b00100100; //   *  *
-         11'h225: data = 8'b00000000; // 
-         11'h226: data = 8'b00000000; // 
-         11'h227: data = 8'b00000000; // 
-         11'h228: data = 8'b00000000; // 
-         11'h229: data = 8'b00000000; // 
-         11'h22a: data = 8'b00000000; // 
-         11'h22b: data = 8'b00000000; // 
-         11'h22c: data = 8'b00000000; // 
-         11'h22d: data = 8'b00000000; // 
-         11'h22e: data = 8'b00000000; // 
-         11'h22f: data = 8'b00000000; // 
-         //code x23
-         11'h230: data = 8'b00000000; // 
-         11'h231: data = 8'b00000000; // 
-         11'h232: data = 8'b00000000; // 
-         11'h233: data = 8'b01101100; //  ** **
-         11'h234: data = 8'b01101100; //  ** **
-         11'h235: data = 8'b11111110; // *******
-         11'h236: data = 8'b01101100; //  ** **
-         11'h237: data = 8'b01101100; //  ** **
-         11'h238: data = 8'b01101100; //  ** **
-         11'h239: data = 8'b11111110; // *******
-         11'h23a: data = 8'b01101100; //  ** **
-         11'h23b: data = 8'b01101100; //  ** **
-         11'h23c: data = 8'b00000000; // 
-         11'h23d: data = 8'b00000000; // 
-         11'h23e: data = 8'b00000000; // 
-         11'h23f: data = 8'b00000000; // 
-         //code x24
-         11'h240: data = 8'b00011000; //     **
-         11'h241: data = 8'b00011000; //     **
-         11'h242: data = 8'b01111100; //   *****
-         11'h243: data = 8'b11000110; //  **   **
-         11'h244: data = 8'b11000010; //  **    *
-         11'h245: data = 8'b11000000; //  **
-         11'h246: data = 8'b01111100; //   *****
-         11'h247: data = 8'b00000110; //       **
-         11'h248: data = 8'b00000110; //       **
-         11'h249: data = 8'b10000110; //  *    **
-         11'h24a: data = 8'b11000110; //  **   **
-         11'h24b: data = 8'b01111100; //   *****
-         11'h24c: data = 8'b00011000; //     **
-         11'h24d: data = 8'b00011000; //     **
-         11'h24e: data = 8'b00000000; // 
-         11'h24f: data = 8'b00000000; // 
-         //code x25
-         11'h250: data = 8'b00000000; // 
-         11'h251: data = 8'b00000000; // 
-         11'h252: data = 8'b00000000; // 
-         11'h253: data = 8'b00000000; // 
-         11'h254: data = 8'b11000010; // **    *
-         11'h255: data = 8'b11000110; // **   **
-         11'h256: data = 8'b00001100; //     **
-         11'h257: data = 8'b00011000; //    **
-         11'h258: data = 8'b00110000; //   **
-         11'h259: data = 8'b01100000; //  **
-         11'h25a: data = 8'b11000110; // **   **
-         11'h25b: data = 8'b10000110; // *    **
-         11'h25c: data = 8'b00000000; // 
-         11'h25d: data = 8'b00000000; // 
-         11'h25e: data = 8'b00000000; // 
-         11'h25f: data = 8'b00000000; // 
-         //code x26
-         11'h260: data = 8'b00000000; // 
-         11'h261: data = 8'b00000000; // 
-         11'h262: data = 8'b00111000; //   ***
-         11'h263: data = 8'b01101100; //  ** **
-         11'h264: data = 8'b01101100; //  ** **
-         11'h265: data = 8'b00111000; //   ***
-         11'h266: data = 8'b01110110; //  *** **
-         11'h267: data = 8'b11011100; // ** ***
-         11'h268: data = 8'b11001100; // **  **
-         11'h269: data = 8'b11001100; // **  **
-         11'h26a: data = 8'b11001100; // **  **
-         11'h26b: data = 8'b01110110; //  *** **
-         11'h26c: data = 8'b00000000; // 
-         11'h26d: data = 8'b00000000; // 
-         11'h26e: data = 8'b00000000; // 
-         11'h26f: data = 8'b00000000; // 
-         //code x27
-         11'h270: data = 8'b00000000; // 
-         11'h271: data = 8'b00110000; //   **
-         11'h272: data = 8'b00110000; //   **
-         11'h273: data = 8'b00110000; //   **
-         11'h274: data = 8'b01100000; //  **
-         11'h275: data = 8'b00000000; // 
-         11'h276: data = 8'b00000000; // 
-         11'h277: data = 8'b00000000; // 
-         11'h278: data = 8'b00000000; // 
-         11'h279: data = 8'b00000000; // 
-         11'h27a: data = 8'b00000000; // 
-         11'h27b: data = 8'b00000000; // 
-         11'h27c: data = 8'b00000000; // 
-         11'h27d: data = 8'b00000000; // 
-         11'h27e: data = 8'b00000000; // 
-         11'h27f: data = 8'b00000000; // 
-         //code x28
-         11'h280: data = 8'b00000000; // 
-         11'h281: data = 8'b00000000; // 
-         11'h282: data = 8'b00001100; //     **
-         11'h283: data = 8'b00011000; //    **
-         11'h284: data = 8'b00110000; //   **
-         11'h285: data = 8'b00110000; //   **
-         11'h286: data = 8'b00110000; //   **
-         11'h287: data = 8'b00110000; //   **
-         11'h288: data = 8'b00110000; //   **
-         11'h289: data = 8'b00110000; //   **
-         11'h28a: data = 8'b00011000; //    **
-         11'h28b: data = 8'b00001100; //     **
-         11'h28c: data = 8'b00000000; // 
-         11'h28d: data = 8'b00000000; // 
-         11'h28e: data = 8'b00000000; // 
-         11'h28f: data = 8'b00000000; // 
-         //code x29
-         11'h290: data = 8'b00000000; // 
-         11'h291: data = 8'b00000000; // 
-         11'h292: data = 8'b00110000; //   **
-         11'h293: data = 8'b00011000; //    **
-         11'h294: data = 8'b00001100; //     **
-         11'h295: data = 8'b00001100; //     **
-         11'h296: data = 8'b00001100; //     **
-         11'h297: data = 8'b00001100; //     **
-         11'h298: data = 8'b00001100; //     **
-         11'h299: data = 8'b00001100; //     **
-         11'h29a: data = 8'b00011000; //    **
-         11'h29b: data = 8'b00110000; //   **
-         11'h29c: data = 8'b00000000; // 
-         11'h29d: data = 8'b00000000; // 
-         11'h29e: data = 8'b00000000; // 
-         11'h29f: data = 8'b00000000; // 
-         //code x2a
-         11'h2a0: data = 8'b00000000; // 
-         11'h2a1: data = 8'b00000000; // 
-         11'h2a2: data = 8'b00000000; // 
-         11'h2a3: data = 8'b00000000; // 
-         11'h2a4: data = 8'b00000000; // 
-         11'h2a5: data = 8'b01100110; //  **  **
-         11'h2a6: data = 8'b00111100; //   ****
-         11'h2a7: data = 8'b11111111; // ********
-         11'h2a8: data = 8'b00111100; //   ****
-         11'h2a9: data = 8'b01100110; //  **  **
-         11'h2aa: data = 8'b00000000; // 
-         11'h2ab: data = 8'b00000000; // 
-         11'h2ac: data = 8'b00000000; // 
-         11'h2ad: data = 8'b00000000; // 
-         11'h2ae: data = 8'b00000000; // 
-         11'h2af: data = 8'b00000000; // 
-         //code x2b
-         11'h2b0: data = 8'b00000000; // 
-         11'h2b1: data = 8'b00000000; // 
-         11'h2b2: data = 8'b00000000; // 
-         11'h2b3: data = 8'b00000000; // 
-         11'h2b4: data = 8'b00000000; // 
-         11'h2b5: data = 8'b00011000; //    **
-         11'h2b6: data = 8'b00011000; //    **
-         11'h2b7: data = 8'b01111110; //  ******
-         11'h2b8: data = 8'b00011000; //    **
-         11'h2b9: data = 8'b00011000; //    **
-         11'h2ba: data = 8'b00000000; // 
-         11'h2bb: data = 8'b00000000; // 
-         11'h2bc: data = 8'b00000000; // 
-         11'h2bd: data = 8'b00000000; // 
-         11'h2be: data = 8'b00000000; // 
-         11'h2bf: data = 8'b00000000; // 
-         //code x2c
-         11'h2c0: data = 8'b00000000; // 
-         11'h2c1: data = 8'b00000000; // 
-         11'h2c2: data = 8'b00000000; // 
-         11'h2c3: data = 8'b00000000; // 
-         11'h2c4: data = 8'b00000000; // 
-         11'h2c5: data = 8'b00000000; // 
-         11'h2c6: data = 8'b00000000; // 
-         11'h2c7: data = 8'b00000000; // 
-         11'h2c8: data = 8'b00000000; // 
-         11'h2c9: data = 8'b00011000; //    **
-         11'h2ca: data = 8'b00011000; //    **
-         11'h2cb: data = 8'b00011000; //    **
-         11'h2cc: data = 8'b00110000; //   **
-         11'h2cd: data = 8'b00000000; // 
-         11'h2ce: data = 8'b00000000; // 
-         11'h2cf: data = 8'b00000000; // 
-         //code x2d
-         11'h2d0: data = 8'b00000000; // 
-         11'h2d1: data = 8'b00000000; // 
-         11'h2d2: data = 8'b00000000; // 
-         11'h2d3: data = 8'b00000000; // 
-         11'h2d4: data = 8'b00000000; // 
-         11'h2d5: data = 8'b00000000; // 
-         11'h2d6: data = 8'b00000000; // 
-         11'h2d7: data = 8'b01111110; //  ******
-         11'h2d8: data = 8'b00000000; // 
-         11'h2d9: data = 8'b00000000; // 
-         11'h2da: data = 8'b00000000; // 
-         11'h2db: data = 8'b00000000; // 
-         11'h2dc: data = 8'b00000000; // 
-         11'h2dd: data = 8'b00000000; // 
-         11'h2de: data = 8'b00000000; // 
-         11'h2df: data = 8'b00000000; // 
-         //code x2e
-         11'h2e0: data = 8'b00000000; // 
-         11'h2e1: data = 8'b00000000; // 
-         11'h2e2: data = 8'b00000000; // 
-         11'h2e3: data = 8'b00000000; // 
-         11'h2e4: data = 8'b00000000; // 
-         11'h2e5: data = 8'b00000000; // 
-         11'h2e6: data = 8'b00000000; // 
-         11'h2e7: data = 8'b00000000; // 
-         11'h2e8: data = 8'b00000000; // 
-         11'h2e9: data = 8'b00000000; // 
-         11'h2ea: data = 8'b00011000; //    **
-         11'h2eb: data = 8'b00011000; //    **
-         11'h2ec: data = 8'b00000000; // 
-         11'h2ed: data = 8'b00000000; // 
-         11'h2ee: data = 8'b00000000; // 
-         11'h2ef: data = 8'b00000000; // 
-         //code x2f
-         11'h2f0: data = 8'b00000000; // 
-         11'h2f1: data = 8'b00000000; // 
-         11'h2f2: data = 8'b00000000; // 
-         11'h2f3: data = 8'b00000000; // 
-         11'h2f4: data = 8'b00000010; //       *
-         11'h2f5: data = 8'b00000110; //      **
-         11'h2f6: data = 8'b00001100; //     **
-         11'h2f7: data = 8'b00011000; //    **
-         11'h2f8: data = 8'b00110000; //   **
-         11'h2f9: data = 8'b01100000; //  **
-         11'h2fa: data = 8'b11000000; // **
-         11'h2fb: data = 8'b10000000; // *
-         11'h2fc: data = 8'b00000000; // 
-         11'h2fd: data = 8'b00000000; // 
-         11'h2fe: data = 8'b00000000; // 
-         11'h2ff: data = 8'b00000000; // 
-         //code x30
-         11'h300: data = 8'b00000000; // 
-         11'h301: data = 8'b00000000; // 
-         11'h302: data = 8'b01111100; //  *****
-         11'h303: data = 8'b11000110; // **   **
-         11'h304: data = 8'b11000110; // **   **
-         11'h305: data = 8'b11001110; // **  ***
-         11'h306: data = 8'b11011110; // ** ****
-         11'h307: data = 8'b11110110; // **** **
-         11'h308: data = 8'b11100110; // ***  **
-         11'h309: data = 8'b11000110; // **   **
-         11'h30a: data = 8'b11000110; // **   **
-         11'h30b: data = 8'b01111100; //  *****
-         11'h30c: data = 8'b00000000; // 
-         11'h30d: data = 8'b00000000; // 
-         11'h30e: data = 8'b00000000; // 
-         11'h30f: data = 8'b00000000; // 
-         //code x31
-         11'h310: data = 8'b00000000; // 
-         11'h311: data = 8'b00000000; // 
-         11'h312: data = 8'b00011000; // 
-         11'h313: data = 8'b00111000; // 
-         11'h314: data = 8'b01111000; //    **
-         11'h315: data = 8'b00011000; //   ***
-         11'h316: data = 8'b00011000; //  ****
-         11'h317: data = 8'b00011000; //    **
-         11'h318: data = 8'b00011000; //    **
-         11'h319: data = 8'b00011000; //    **
-         11'h31a: data = 8'b00011000; //    **
-         11'h31b: data = 8'b01111110; //    **
-         11'h31c: data = 8'b00000000; //    **
-         11'h31d: data = 8'b00000000; //  ******
-         11'h31e: data = 8'b00000000; // 
-         11'h31f: data = 8'b00000000; // 
-         //code x32
-         11'h320: data = 8'b00000000; // 
-         11'h321: data = 8'b00000000; // 
-         11'h322: data = 8'b01111100; //  *****
-         11'h323: data = 8'b11000110; // **   **
-         11'h324: data = 8'b00000110; //      **
-         11'h325: data = 8'b00001100; //     **
-         11'h326: data = 8'b00011000; //    **
-         11'h327: data = 8'b00110000; //   **
-         11'h328: data = 8'b01100000; //  **
-         11'h329: data = 8'b11000000; // **
-         11'h32a: data = 8'b11000110; // **   **
-         11'h32b: data = 8'b11111110; // *******
-         11'h32c: data = 8'b00000000; // 
-         11'h32d: data = 8'b00000000; // 
-         11'h32e: data = 8'b00000000; // 
-         11'h32f: data = 8'b00000000; // 
-         //code x33
-         11'h330: data = 8'b00000000; // 
-         11'h331: data = 8'b00000000; // 
-         11'h332: data = 8'b01111100; //  *****
-         11'h333: data = 8'b11000110; // **   **
-         11'h334: data = 8'b00000110; //      **
-         11'h335: data = 8'b00000110; //      **
-         11'h336: data = 8'b00111100; //   ****
-         11'h337: data = 8'b00000110; //      **
-         11'h338: data = 8'b00000110; //      **
-         11'h339: data = 8'b00000110; //      **
-         11'h33a: data = 8'b11000110; // **   **
-         11'h33b: data = 8'b01111100; //  *****
-         11'h33c: data = 8'b00000000; // 
-         11'h33d: data = 8'b00000000; // 
-         11'h33e: data = 8'b00000000; // 
-         11'h33f: data = 8'b00000000; // 
-         //code x34
-         11'h340: data = 8'b00000000; // 
-         11'h341: data = 8'b00000000; // 
-         11'h342: data = 8'b00001100; //     **
-         11'h343: data = 8'b00011100; //    ***
-         11'h344: data = 8'b00111100; //   ****
-         11'h345: data = 8'b01101100; //  ** **
-         11'h346: data = 8'b11001100; // **  **
-         11'h347: data = 8'b11111110; // *******
-         11'h348: data = 8'b00001100; //     **
-         11'h349: data = 8'b00001100; //     **
-         11'h34a: data = 8'b00001100; //     **
-         11'h34b: data = 8'b00011110; //    ****
-         11'h34c: data = 8'b00000000; // 
-         11'h34d: data = 8'b00000000; // 
-         11'h34e: data = 8'b00000000; // 
-         11'h34f: data = 8'b00000000; // 
-         //code x35
-         11'h350: data = 8'b00000000; // 
-         11'h351: data = 8'b00000000; // 
-         11'h352: data = 8'b11111110; // *******
-         11'h353: data = 8'b11000000; // **
-         11'h354: data = 8'b11000000; // **
-         11'h355: data = 8'b11000000; // **
-         11'h356: data = 8'b11111100; // ******
-         11'h357: data = 8'b00000110; //      **
-         11'h358: data = 8'b00000110; //      **
-         11'h359: data = 8'b00000110; //      **
-         11'h35a: data = 8'b11000110; // **   **
-         11'h35b: data = 8'b01111100; //  *****
-         11'h35c: data = 8'b00000000; // 
-         11'h35d: data = 8'b00000000; // 
-         11'h35e: data = 8'b00000000; // 
-         11'h35f: data = 8'b00000000; // 
-         //code x36
-         11'h360: data = 8'b00000000; // 
-         11'h361: data = 8'b00000000; // 
-         11'h362: data = 8'b00111000; //   ***
-         11'h363: data = 8'b01100000; //  **
-         11'h364: data = 8'b11000000; // **
-         11'h365: data = 8'b11000000; // **
-         11'h366: data = 8'b11111100; // ******
-         11'h367: data = 8'b11000110; // **   **
-         11'h368: data = 8'b11000110; // **   **
-         11'h369: data = 8'b11000110; // **   **
-         11'h36a: data = 8'b11000110; // **   **
-         11'h36b: data = 8'b01111100; //  *****
-         11'h36c: data = 8'b00000000; // 
-         11'h36d: data = 8'b00000000; // 
-         11'h36e: data = 8'b00000000; // 
-         11'h36f: data = 8'b00000000; // 
-         //code x37
-         11'h370: data = 8'b00000000; // 
-         11'h371: data = 8'b00000000; // 
-         11'h372: data = 8'b11111110; // *******
-         11'h373: data = 8'b11000110; // **   **
-         11'h374: data = 8'b00000110; //      **
-         11'h375: data = 8'b00000110; //      **
-         11'h376: data = 8'b00001100; //     **
-         11'h377: data = 8'b00011000; //    **
-         11'h378: data = 8'b00110000; //   **
-         11'h379: data = 8'b00110000; //   **
-         11'h37a: data = 8'b00110000; //   **
-         11'h37b: data = 8'b00110000; //   **
-         11'h37c: data = 8'b00000000; // 
-         11'h37d: data = 8'b00000000; // 
-         11'h37e: data = 8'b00000000; // 
-         11'h37f: data = 8'b00000000; // 
-         //code x38
-         11'h380: data = 8'b00000000; // 
-         11'h381: data = 8'b00000000; // 
-         11'h382: data = 8'b01111100; //  *****
-         11'h383: data = 8'b11000110; // **   **
-         11'h384: data = 8'b11000110; // **   **
-         11'h385: data = 8'b11000110; // **   **
-         11'h386: data = 8'b01111100; //  *****
-         11'h387: data = 8'b11000110; // **   **
-         11'h388: data = 8'b11000110; // **   **
-         11'h389: data = 8'b11000110; // **   **
-         11'h38a: data = 8'b11000110; // **   **
-         11'h38b: data = 8'b01111100; //  *****
-         11'h38c: data = 8'b00000000; // 
-         11'h38d: data = 8'b00000000; // 
-         11'h38e: data = 8'b00000000; // 
-         11'h38f: data = 8'b00000000; // 
-         //code x39
-         11'h390: data = 8'b00000000; // 
-         11'h391: data = 8'b00000000; // 
-         11'h392: data = 8'b01111100; //  *****
-         11'h393: data = 8'b11000110; // **   **
-         11'h394: data = 8'b11000110; // **   **
-         11'h395: data = 8'b11000110; // **   **
-         11'h396: data = 8'b01111110; //  ******
-         11'h397: data = 8'b00000110; //      **
-         11'h398: data = 8'b00000110; //      **
-         11'h399: data = 8'b00000110; //      **
-         11'h39a: data = 8'b00001100; //     **
-         11'h39b: data = 8'b01111000; //  ****
-         11'h39c: data = 8'b00000000; // 
-         11'h39d: data = 8'b00000000; // 
-         11'h39e: data = 8'b00000000; // 
-         11'h39f: data = 8'b00000000; // 
-         //code x3a 
-         11'h3a0: data = 8'b00000000; // 
-         11'h3a1: data = 8'b00000000; // 
-         11'h3a2: data = 8'b00000000; // 
-         11'h3a3: data = 8'b00000000; // 
-         11'h3a4: data = 8'b00011000; //    **
-         11'h3a5: data = 8'b00011000; //    **
-         11'h3a6: data = 8'b00000000; // 
-         11'h3a7: data = 8'b00000000; // 
-         11'h3a8: data = 8'b00000000; // 
-         11'h3a9: data = 8'b00011000; //    **
-         11'h3aa: data = 8'b00011000; //    **
-         11'h3ab: data = 8'b00000000; // 
-         11'h3ac: data = 8'b00000000; // 
-         11'h3ad: data = 8'b00000000; // 
-         11'h3ae: data = 8'b00000000; // 
-         11'h3af: data = 8'b00000000; // 
-         //code x3b 
-         11'h3b0: data = 8'b00000000; // 
-         11'h3b1: data = 8'b00000000; // 
-         11'h3b2: data = 8'b00000000; // 
-         11'h3b3: data = 8'b00000000; // 
-         11'h3b4: data = 8'b00011000; //    **
-         11'h3b5: data = 8'b00011000; //    **
-         11'h3b6: data = 8'b00000000; // 
-         11'h3b7: data = 8'b00000000; // 
-         11'h3b8: data = 8'b00000000; // 
-         11'h3b9: data = 8'b00011000; //    **
-         11'h3ba: data = 8'b00011000; //    **
-         11'h3bb: data = 8'b00110000; //   **
-         11'h3bc: data = 8'b00000000; // 
-         11'h3bd: data = 8'b00000000; // 
-         11'h3be: data = 8'b00000000; // 
-         11'h3bf: data = 8'b00000000; // 
-         //code x3c 
-         11'h3c0: data = 8'b00000000; // 
-         11'h3c1: data = 8'b00000000; // 
-         11'h3c2: data = 8'b00000000; // 
-         11'h3c3: data = 8'b00000110; //      **
-         11'h3c4: data = 8'b00001100; //     **
-         11'h3c5: data = 8'b00011000; //    **
-         11'h3c6: data = 8'b00110000; //   **
-         11'h3c7: data = 8'b01100000; //  **
-         11'h3c8: data = 8'b00110000; //   **
-         11'h3c9: data = 8'b00011000; //    **
-         11'h3ca: data = 8'b00001100; //     **
-         11'h3cb: data = 8'b00000110; //      **
-         11'h3cc: data = 8'b00000000; // 
-         11'h3cd: data = 8'b00000000; // 
-         11'h3ce: data = 8'b00000000; // 
-         11'h3cf: data = 8'b00000000; // 
-         //code x3d 
-         11'h3d0: data = 8'b00000000; // 
-         11'h3d1: data = 8'b00000000; // 
-         11'h3d2: data = 8'b00000000; // 
-         11'h3d3: data = 8'b00000000; // 
-         11'h3d4: data = 8'b00000000; // 
-         11'h3d5: data = 8'b01111110; //  ******
-         11'h3d6: data = 8'b00000000; // 
-         11'h3d7: data = 8'b00000000; // 
-         11'h3d8: data = 8'b01111110; //  ******
-         11'h3d9: data = 8'b00000000; // 
-         11'h3da: data = 8'b00000000; // 
-         11'h3db: data = 8'b00000000; // 
-         11'h3dc: data = 8'b00000000; // 
-         11'h3dd: data = 8'b00000000; // 
-         11'h3de: data = 8'b00000000; // 
-         11'h3df: data = 8'b00000000; // 
-         //code x3e 
-         11'h3e0: data = 8'b00000000; // 
-         11'h3e1: data = 8'b00000000; // 
-         11'h3e2: data = 8'b00000000; // 
-         11'h3e3: data = 8'b01100000; //  **
-         11'h3e4: data = 8'b00110000; //   **
-         11'h3e5: data = 8'b00011000; //    **
-         11'h3e6: data = 8'b00001100; //     **
-         11'h3e7: data = 8'b00000110; //      **
-         11'h3e8: data = 8'b00001100; //     **
-         11'h3e9: data = 8'b00011000; //    **
-         11'h3ea: data = 8'b00110000; //   **
-         11'h3eb: data = 8'b01100000; //  **
-         11'h3ec: data = 8'b00000000; // 
-         11'h3ed: data = 8'b00000000; // 
-         11'h3ee: data = 8'b00000000; // 
-         11'h3ef: data = 8'b00000000; // 
-         //code x3f 
-         11'h3f0: data = 8'b00000000; // 
-         11'h3f1: data = 8'b00000000; // 
-         11'h3f2: data = 8'b01111100; //  *****
-         11'h3f3: data = 8'b11000110; // **   **
-         11'h3f4: data = 8'b11000110; // **   **
-         11'h3f5: data = 8'b00001100; //     **
-         11'h3f6: data = 8'b00011000; //    **
-         11'h3f7: data = 8'b00011000; //    **
-         11'h3f8: data = 8'b00011000; //    **
-         11'h3f9: data = 8'b00000000; // 
-         11'h3fa: data = 8'b00011000; //    **
-         11'h3fb: data = 8'b00011000; //    **
-         11'h3fc: data = 8'b00000000; // 
-         11'h3fd: data = 8'b00000000; // 
-         11'h3fe: data = 8'b00000000; // 
-         11'h3ff: data = 8'b00000000; // 
-        //code x40 
-         11'h400: data = 8'b00000000; // 
-         11'h401: data = 8'b00000000; // 
-         11'h402: data = 8'b01111100; //  *****
-         11'h403: data = 8'b11000110; // **   **
-         11'h404: data = 8'b11000110; // **   **
-         11'h405: data = 8'b11000110; // **   **
-         11'h406: data = 8'b11011110; // ** ****
-         11'h407: data = 8'b11011110; // ** ****
-         11'h408: data = 8'b11011110; // ** ****
-         11'h409: data = 8'b11011100; // ** ***
-         11'h40a: data = 8'b11000000; // **
-         11'h40b: data = 8'b01111100; //  *****
-         11'h40c: data = 8'b00000000; // 
-         11'h40d: data = 8'b00000000; // 
-         11'h40e: data = 8'b00000000; // 
-         11'h40f: data = 8'b00000000; // 
-         //code x41 
-         11'h410: data = 8'b00000000; // 
-         11'h411: data = 8'b00000000; // 
-         11'h412: data = 8'b00010000; //    *
-         11'h413: data = 8'b00111000; //   ***
-         11'h414: data = 8'b01101100; //  ** **
-         11'h415: data = 8'b11000110; // **   **
-         11'h416: data = 8'b11000110; // **   **
-         11'h417: data = 8'b11111110; // *******
-         11'h418: data = 8'b11000110; // **   **
-         11'h419: data = 8'b11000110; // **   **
-         11'h41a: data = 8'b11000110; // **   **
-         11'h41b: data = 8'b11000110; // **   **
-         11'h41c: data = 8'b00000000; // 
-         11'h41d: data = 8'b00000000; // 
-         11'h41e: data = 8'b00000000; // 
-         11'h41f: data = 8'b00000000; // 
-         //code x42 
-         11'h420: data = 8'b00000000; // 
-         11'h421: data = 8'b00000000; // 
-         11'h422: data = 8'b11111100; // ******
-         11'h423: data = 8'b01100110; //  **  **
-         11'h424: data = 8'b01100110; //  **  **
-         11'h425: data = 8'b01100110; //  **  **
-         11'h426: data = 8'b01111100; //  *****
-         11'h427: data = 8'b01100110; //  **  **
-         11'h428: data = 8'b01100110; //  **  **
-         11'h429: data = 8'b01100110; //  **  **
-         11'h42a: data = 8'b01100110; //  **  **
-         11'h42b: data = 8'b11111100; // ******
-         11'h42c: data = 8'b00000000; // 
-         11'h42d: data = 8'b00000000; // 
-         11'h42e: data = 8'b00000000; // 
-         11'h42f: data = 8'b00000000; // 
-         //code x43 
-         11'h430: data = 8'b00000000; // 
-         11'h431: data = 8'b00000000; // 
-         11'h432: data = 8'b00111100; //   ****
-         11'h433: data = 8'b01100110; //  **  **
-         11'h434: data = 8'b11000010; // **    *
-         11'h435: data = 8'b11000000; // **
-         11'h436: data = 8'b11000000; // **
-         11'h437: data = 8'b11000000; // **
-         11'h438: data = 8'b11000000; // **
-         11'h439: data = 8'b11000010; // **    *
-         11'h43a: data = 8'b01100110; //  **  **
-         11'h43b: data = 8'b00111100; //   ****
-         11'h43c: data = 8'b00000000; // 
-         11'h43d: data = 8'b00000000; // 
-         11'h43e: data = 8'b00000000; // 
-         11'h43f: data = 8'b00000000; // 
-         //code x44 
-         11'h440: data = 8'b00000000; // 
-         11'h441: data = 8'b00000000; // 
-         11'h442: data = 8'b11111000; // *****
-         11'h443: data = 8'b01101100; //  ** **
-         11'h444: data = 8'b01100110; //  **  **
-         11'h445: data = 8'b01100110; //  **  **
-         11'h446: data = 8'b01100110; //  **  **
-         11'h447: data = 8'b01100110; //  **  **
-         11'h448: data = 8'b01100110; //  **  **
-         11'h449: data = 8'b01100110; //  **  **
-         11'h44a: data = 8'b01101100; //  ** **
-         11'h44b: data = 8'b11111000; // *****
-         11'h44c: data = 8'b00000000; // 
-         11'h44d: data = 8'b00000000; // 
-         11'h44e: data = 8'b00000000; // 
-         11'h44f: data = 8'b00000000; // 
-         //code x45 
-         11'h450: data = 8'b00000000; // 
-         11'h451: data = 8'b00000000; // 
-         11'h452: data = 8'b11111110; // *******
-         11'h453: data = 8'b01100110; //  **  **
-         11'h454: data = 8'b01100010; //  **   *
-         11'h455: data = 8'b01101000; //  ** *
-         11'h456: data = 8'b01111000; //  ****
-         11'h457: data = 8'b01101000; //  ** *
-         11'h458: data = 8'b01100000; //  **
-         11'h459: data = 8'b01100010; //  **   *
-         11'h45a: data = 8'b01100110; //  **  **
-         11'h45b: data = 8'b11111110; // *******
-         11'h45c: data = 8'b00000000; // 
-         11'h45d: data = 8'b00000000; // 
-         11'h45e: data = 8'b00000000; // 
-         11'h45f: data = 8'b00000000; // 
-         //code x46 
-         11'h460: data = 8'b00000000; // 
-         11'h461: data = 8'b00000000; // 
-         11'h462: data = 8'b11111110; // *******
-         11'h463: data = 8'b01100110; //  **  **
-         11'h464: data = 8'b01100010; //  **   *
-         11'h465: data = 8'b01101000; //  ** *
-         11'h466: data = 8'b01111000; //  ****
-         11'h467: data = 8'b01101000; //  ** *
-         11'h468: data = 8'b01100000; //  **
-         11'h469: data = 8'b01100000; //  **
-         11'h46a: data = 8'b01100000; //  **
-         11'h46b: data = 8'b11110000; // ****
-         11'h46c: data = 8'b00000000; // 
-         11'h46d: data = 8'b00000000; // 
-         11'h46e: data = 8'b00000000; // 
-         11'h46f: data = 8'b00000000; // 
-         //code x47 
-         11'h470: data = 8'b00000000; // 
-         11'h471: data = 8'b00000000; // 
-         11'h472: data = 8'b00111100; //   ****
-         11'h473: data = 8'b01100110; //  **  **
-         11'h474: data = 8'b11000010; // **    *
-         11'h475: data = 8'b11000000; // **
-         11'h476: data = 8'b11000000; // **
-         11'h477: data = 8'b11011110; // ** ****
-         11'h478: data = 8'b11000110; // **   **
-         11'h479: data = 8'b11000110; // **   **
-         11'h47a: data = 8'b01100110; //  **  **
-         11'h47b: data = 8'b00111010; //   *** *
-         11'h47c: data = 8'b00000000; // 
-         11'h47d: data = 8'b00000000; // 
-         11'h47e: data = 8'b00000000; // 
-         11'h47f: data = 8'b00000000; // 
-         //code x48 
-         11'h480: data = 8'b00000000; // 
-         11'h481: data = 8'b00000000; // 
-         11'h482: data = 8'b11000110; // **   **
-         11'h483: data = 8'b11000110; // **   **
-         11'h484: data = 8'b11000110; // **   **
-         11'h485: data = 8'b11000110; // **   **
-         11'h486: data = 8'b11111110; // *******
-         11'h487: data = 8'b11000110; // **   **
-         11'h488: data = 8'b11000110; // **   **
-         11'h489: data = 8'b11000110; // **   **
-         11'h48a: data = 8'b11000110; // **   **
-         11'h48b: data = 8'b11000110; // **   **
-         11'h48c: data = 8'b00000000; // 
-         11'h48d: data = 8'b00000000; // 
-         11'h48e: data = 8'b00000000; // 
-         11'h48f: data = 8'b00000000; // 
-         //code x49 
-         11'h490: data = 8'b00000000; // 
-         11'h491: data = 8'b00000000; // 
-         11'h492: data = 8'b00111100; //   ****
-         11'h493: data = 8'b00011000; //    **
-         11'h494: data = 8'b00011000; //    **
-         11'h495: data = 8'b00011000; //    **
-         11'h496: data = 8'b00011000; //    **
-         11'h497: data = 8'b00011000; //    **
-         11'h498: data = 8'b00011000; //    **
-         11'h499: data = 8'b00011000; //    **
-         11'h49a: data = 8'b00011000; //    **
-         11'h49b: data = 8'b00111100; //   ****
-         11'h49c: data = 8'b00000000; // 
-         11'h49d: data = 8'b00000000; // 
-         11'h49e: data = 8'b00000000; // 
-         11'h49f: data = 8'b00000000; // 
-         //code x4a   
-         11'h4a0: data = 8'b00000000; // 
-         11'h4a1: data = 8'b00000000; // 
-         11'h4a2: data = 8'b00011110; //    ****
-         11'h4a3: data = 8'b00001100; //     **
-         11'h4a4: data = 8'b00001100; //     **
-         11'h4a5: data = 8'b00001100; //     **
-         11'h4a6: data = 8'b00001100; //     **
-         11'h4a7: data = 8'b00001100; //     **
-         11'h4a8: data = 8'b11001100; // **  **
-         11'h4a9: data = 8'b11001100; // **  **
-         11'h4aa: data = 8'b11001100; // **  **
-         11'h4ab: data = 8'b01111000; //  ****
-         11'h4ac: data = 8'b00000000; // 
-         11'h4ad: data = 8'b00000000; // 
-         11'h4ae: data = 8'b00000000; // 
-         11'h4af: data = 8'b00000000; // 
-         //code x4b   
-         11'h4b0: data = 8'b00000000; // 
-         11'h4b1: data = 8'b00000000; // 
-         11'h4b2: data = 8'b11100110; // ***  **
-         11'h4b3: data = 8'b01100110; //  **  **
-         11'h4b4: data = 8'b01100110; //  **  **
-         11'h4b5: data = 8'b01101100; //  ** **
-         11'h4b6: data = 8'b01111000; //  ****
-         11'h4b7: data = 8'b01111000; //  ****
-         11'h4b8: data = 8'b01101100; //  ** **
-         11'h4b9: data = 8'b01100110; //  **  **
-         11'h4ba: data = 8'b01100110; //  **  **
-         11'h4bb: data = 8'b11100110; // ***  **
-         11'h4bc: data = 8'b00000000; // 
-         11'h4bd: data = 8'b00000000; // 
-         11'h4be: data = 8'b00000000; // 
-         11'h4bf: data = 8'b00000000; // 
-         //code x4c   
-         11'h4c0: data = 8'b00000000; // 
-         11'h4c1: data = 8'b00000000; // 
-         11'h4c2: data = 8'b11110000; // ****
-         11'h4c3: data = 8'b01100000; //  **
-         11'h4c4: data = 8'b01100000; //  **
-         11'h4c5: data = 8'b01100000; //  **
-         11'h4c6: data = 8'b01100000; //  **
-         11'h4c7: data = 8'b01100000; //  **
-         11'h4c8: data = 8'b01100000; //  **
-         11'h4c9: data = 8'b01100010; //  **   *
-         11'h4ca: data = 8'b01100110; //  **  **
-         11'h4cb: data = 8'b11111110; // *******
-         11'h4cc: data = 8'b00000000; // 
-         11'h4cd: data = 8'b00000000; // 
-         11'h4ce: data = 8'b00000000; // 
-         11'h4cf: data = 8'b00000000; // 
-         //code x4d   
-         11'h4d0: data = 8'b00000000; // 
-         11'h4d1: data = 8'b00000000; // 
-         11'h4d2: data = 8'b11000011; // **    **
-         11'h4d3: data = 8'b11100111; // ***  ***
-         11'h4d4: data = 8'b11111111; // ********
-         11'h4d5: data = 8'b11111111; // ********
-         11'h4d6: data = 8'b11011011; // ** ** **
-         11'h4d7: data = 8'b11000011; // **    **
-         11'h4d8: data = 8'b11000011; // **    **
-         11'h4d9: data = 8'b11000011; // **    **
-         11'h4da: data = 8'b11000011; // **    **
-         11'h4db: data = 8'b11000011; // **    **
-         11'h4dc: data = 8'b00000000; // 
-         11'h4dd: data = 8'b00000000; // 
-         11'h4de: data = 8'b00000000; // 
-         11'h4df: data = 8'b00000000; // 
-         //code x4e   
-         11'h4e0: data = 8'b00000000; // 
-         11'h4e1: data = 8'b00000000; // 
-         11'h4e2: data = 8'b11000110; // **   **
-         11'h4e3: data = 8'b11100110; // ***  **
-         11'h4e4: data = 8'b11110110; // **** **
-         11'h4e5: data = 8'b11111110; // *******
-         11'h4e6: data = 8'b11011110; // ** ****
-         11'h4e7: data = 8'b11001110; // **  ***
-         11'h4e8: data = 8'b11000110; // **   **
-         11'h4e9: data = 8'b11000110; // **   **
-         11'h4ea: data = 8'b11000110; // **   **
-         11'h4eb: data = 8'b11000110; // **   **
-         11'h4ec: data = 8'b00000000; // 
-         11'h4ed: data = 8'b00000000; // 
-         11'h4ee: data = 8'b00000000; // 
-         11'h4ef: data = 8'b00000000; // 
-         //code x4f   
-         11'h4f0: data = 8'b00000000; // 
-         11'h4f1: data = 8'b00000000; // 
-         11'h4f2: data = 8'b01111100; //  *****
-         11'h4f3: data = 8'b11000110; // **   **
-         11'h4f4: data = 8'b11000110; // **   **
-         11'h4f5: data = 8'b11000110; // **   **
-         11'h4f6: data = 8'b11000110; // **   **
-         11'h4f7: data = 8'b11000110; // **   **
-         11'h4f8: data = 8'b11000110; // **   **
-         11'h4f9: data = 8'b11000110; // **   **
-         11'h4fa: data = 8'b11000110; // **   **
-         11'h4fb: data = 8'b01111100; //  *****
-         11'h4fc: data = 8'b00000000; // 
-         11'h4fd: data = 8'b00000000; // 
-         11'h4fe: data = 8'b00000000; // 
-         11'h4ff: data = 8'b00000000; // 
-         //code x50   
-         11'h500: data = 8'b00000000; // 
-         11'h501: data = 8'b00000000; // 
-         11'h502: data = 8'b11111100; // ******
-         11'h503: data = 8'b01100110; //  **  **
-         11'h504: data = 8'b01100110; //  **  **
-         11'h505: data = 8'b01100110; //  **  **
-         11'h506: data = 8'b01111100; //  *****
-         11'h507: data = 8'b01100000; //  **
-         11'h508: data = 8'b01100000; //  **
-         11'h509: data = 8'b01100000; //  **
-         11'h50a: data = 8'b01100000; //  **
-         11'h50b: data = 8'b11110000; // ****
-         11'h50c: data = 8'b00000000; // 
-         11'h50d: data = 8'b00000000; // 
-         11'h50e: data = 8'b00000000; // 
-         11'h50f: data = 8'b00000000; // 
-         //code x510f
-         11'h510: data = 8'b00000000; // 
-         11'h511: data = 8'b00000000; // 
-         11'h512: data = 8'b01111100; //  *****
-         11'h513: data = 8'b11000110; // **   **
-         11'h514: data = 8'b11000110; // **   **
-         11'h515: data = 8'b11000110; // **   **
-         11'h516: data = 8'b11000110; // **   **
-         11'h517: data = 8'b11000110; // **   **
-         11'h518: data = 8'b11000110; // **   **
-         11'h519: data = 8'b11010110; // ** * **
-         11'h51a: data = 8'b11011110; // ** ****
-         11'h51b: data = 8'b01111100; //  *****
-         11'h51c: data = 8'b00001100; //     **
-         11'h51d: data = 8'b00001110; //     ***
-         11'h51e: data = 8'b00000000; // 
-         11'h51f: data = 8'b00000000; // 
-         //code x52   
-         11'h520: data = 8'b00000000; // 
-         11'h521: data = 8'b00000000; // 
-         11'h522: data = 8'b11111100; // ******
-         11'h523: data = 8'b01100110; //  **  **
-         11'h524: data = 8'b01100110; //  **  **
-         11'h525: data = 8'b01100110; //  **  **
-         11'h526: data = 8'b01111100; //  *****
-         11'h527: data = 8'b01101100; //  ** **
-         11'h528: data = 8'b01100110; //  **  **
-         11'h529: data = 8'b01100110; //  **  **
-         11'h52a: data = 8'b01100110; //  **  **
-         11'h52b: data = 8'b11100110; // ***  **
-         11'h52c: data = 8'b00000000; // 
-         11'h52d: data = 8'b00000000; // 
-         11'h52e: data = 8'b00000000; // 
-         11'h52f: data = 8'b00000000; // 
-         //code x53   
-         11'h530: data = 8'b00000000; // 
-         11'h531: data = 8'b00000000; // 
-         11'h532: data = 8'b01111100; //  *****
-         11'h533: data = 8'b11000110; // **   **
-         11'h534: data = 8'b11000110; // **   **
-         11'h535: data = 8'b01100000; //  **
-         11'h536: data = 8'b00111000; //   ***
-         11'h537: data = 8'b00001100; //     **
-         11'h538: data = 8'b00000110; //      **
-         11'h539: data = 8'b11000110; // **   **
-         11'h53a: data = 8'b11000110; // **   **
-         11'h53b: data = 8'b01111100; //  *****
-         11'h53c: data = 8'b00000000; // 
-         11'h53d: data = 8'b00000000; // 
-         11'h53e: data = 8'b00000000; // 
-         11'h53f: data = 8'b00000000; // 
-         //code x54   
-         11'h540: data = 8'b00000000; // 
-         11'h541: data = 8'b00000000; // 
-         11'h542: data = 8'b11111111; // ********
-         11'h543: data = 8'b11011011; // ** ** **
-         11'h544: data = 8'b10011001; // *  **  *
-         11'h545: data = 8'b00011000; //    **
-         11'h546: data = 8'b00011000; //    **
-         11'h547: data = 8'b00011000; //    **
-         11'h548: data = 8'b00011000; //    **
-         11'h549: data = 8'b00011000; //    **
-         11'h54a: data = 8'b00011000; //    **
-         11'h54b: data = 8'b00111100; //   ****
-         11'h54c: data = 8'b00000000; // 
-         11'h54d: data = 8'b00000000; // 
-         11'h54e: data = 8'b00000000; // 
-         11'h54f: data = 8'b00000000; // 
-         //code x55   
-         11'h550: data = 8'b00000000; // 
-         11'h551: data = 8'b00000000; // 
-         11'h552: data = 8'b11000110; // **   **
-         11'h553: data = 8'b11000110; // **   **
-         11'h554: data = 8'b11000110; // **   **
-         11'h555: data = 8'b11000110; // **   **
-         11'h556: data = 8'b11000110; // **   **
-         11'h557: data = 8'b11000110; // **   **
-         11'h558: data = 8'b11000110; // **   **
-         11'h559: data = 8'b11000110; // **   **
-         11'h55a: data = 8'b11000110; // **   **
-         11'h55b: data = 8'b01111100; //  *****
-         11'h55c: data = 8'b00000000; // 
-         11'h55d: data = 8'b00000000; // 
-         11'h55e: data = 8'b00000000; // 
-         11'h55f: data = 8'b00000000; // 
-         //code x56   
-         11'h560: data = 8'b00000000; // 
-         11'h561: data = 8'b00000000; // 
-         11'h562: data = 8'b11000011; // **    **
-         11'h563: data = 8'b11000011; // **    **
-         11'h564: data = 8'b11000011; // **    **
-         11'h565: data = 8'b11000011; // **    **
-         11'h566: data = 8'b11000011; // **    **
-         11'h567: data = 8'b11000011; // **    **
-         11'h568: data = 8'b11000011; // **    **
-         11'h569: data = 8'b01100110; //  **  **
-         11'h56a: data = 8'b00111100; //   ****
-         11'h56b: data = 8'b00011000; //    **
-         11'h56c: data = 8'b00000000; // 
-         11'h56d: data = 8'b00000000; // 
-         11'h56e: data = 8'b00000000; // 
-         11'h56f: data = 8'b00000000; // 
-         //code x57   
-         11'h570: data = 8'b00000000; // 
-         11'h571: data = 8'b00000000; // 
-         11'h572: data = 8'b11000011; // **    **
-         11'h573: data = 8'b11000011; // **    **
-         11'h574: data = 8'b11000011; // **    **
-         11'h575: data = 8'b11000011; // **    **
-         11'h576: data = 8'b11000011; // **    **
-         11'h577: data = 8'b11011011; // ** ** **
-         11'h578: data = 8'b11011011; // ** ** **
-         11'h579: data = 8'b11111111; // ********
-         11'h57a: data = 8'b01100110; //  **  **
-         11'h57b: data = 8'b01100110; //  **  **
-         11'h57c: data = 8'b00000000; // 
-         11'h57d: data = 8'b00000000; // 
-         11'h57e: data = 8'b00000000; // 
-         11'h57f: data = 8'b00000000; // 
-         //code x58   
-         11'h580: data = 8'b00000000; // 
-         11'h581: data = 8'b00000000; // 
-         11'h582: data = 8'b11000011; // **    **
-         11'h583: data = 8'b11000011; // **    **
-         11'h584: data = 8'b01100110; //  **  **
-         11'h585: data = 8'b00111100; //   ****
-         11'h586: data = 8'b00011000; //    **
-         11'h587: data = 8'b00011000; //    **
-         11'h588: data = 8'b00111100; //   ****
-         11'h589: data = 8'b01100110; //  **  **
-         11'h58a: data = 8'b11000011; // **    **
-         11'h58b: data = 8'b11000011; // **    **
-         11'h58c: data = 8'b00000000; // 
-         11'h58d: data = 8'b00000000; // 
-         11'h58e: data = 8'b00000000; // 
-         11'h58f: data = 8'b00000000; // 
-         //code x59   
-         11'h590: data = 8'b00000000; // 
-         11'h591: data = 8'b00000000; // 
-         11'h592: data = 8'b11000011; // **    **
-         11'h593: data = 8'b11000011; // **    **
-         11'h594: data = 8'b11000011; // **    **
-         11'h595: data = 8'b01100110; //  **  **
-         11'h596: data = 8'b00111100; //   ****
-         11'h597: data = 8'b00011000; //    **
-         11'h598: data = 8'b00011000; //    **
-         11'h599: data = 8'b00011000; //    **
-         11'h59a: data = 8'b00011000; //    **
-         11'h59b: data = 8'b00111100; //   ****
-         11'h59c: data = 8'b00000000; // 
-         11'h59d: data = 8'b00000000; // 
-         11'h59e: data = 8'b00000000; // 
-         11'h59f: data = 8'b00000000; // 
-         //code x5a   
-         11'h5a0: data = 8'b00000000; // 
-         11'h5a1: data = 8'b00000000; // 
-         11'h5a2: data = 8'b11111111; // ********
-         11'h5a3: data = 8'b11000011; // **    **
-         11'h5a4: data = 8'b10000110; // *    **
-         11'h5a5: data = 8'b00001100; //     **
-         11'h5a6: data = 8'b00011000; //    **
-         11'h5a7: data = 8'b00110000; //   **
-         11'h5a8: data = 8'b01100000; //  **
-         11'h5a9: data = 8'b11000001; // **     *
-         11'h5aa: data = 8'b11000011; // **    **
-         11'h5ab: data = 8'b11111111; // ********
-         11'h5ac: data = 8'b00000000; // 
-         11'h5ad: data = 8'b00000000; // 
-         11'h5ae: data = 8'b00000000; // 
-         11'h5af: data = 8'b00000000; // 
-         //code x5b   
-         11'h5b0: data = 8'b00000000; // 
-         11'h5b1: data = 8'b00000000; // 
-         11'h5b2: data = 8'b00111100; //   ****
-         11'h5b3: data = 8'b00110000; //   **
-         11'h5b4: data = 8'b00110000; //   **
-         11'h5b5: data = 8'b00110000; //   **
-         11'h5b6: data = 8'b00110000; //   **
-         11'h5b7: data = 8'b00110000; //   **
-         11'h5b8: data = 8'b00110000; //   **
-         11'h5b9: data = 8'b00110000; //   **
-         11'h5ba: data = 8'b00110000; //   **
-         11'h5bb: data = 8'b00111100; //   ****
-         11'h5bc: data = 8'b00000000; // 
-         11'h5bd: data = 8'b00000000; // 
-         11'h5be: data = 8'b00000000; // 
-         11'h5bf: data = 8'b00000000; // 
-         //code x5c   
-         11'h5c0: data = 8'b00000000; // 
-         11'h5c1: data = 8'b00000000; // 
-         11'h5c2: data = 8'b00000000; // 
-         11'h5c3: data = 8'b10000000; // *
-         11'h5c4: data = 8'b11000000; // **
-         11'h5c5: data = 8'b11100000; // ***
-         11'h5c6: data = 8'b01110000; //  ***
-         11'h5c7: data = 8'b00111000; //   ***
-         11'h5c8: data = 8'b00011100; //    ***
-         11'h5c9: data = 8'b00001110; //     ***
-         11'h5ca: data = 8'b00000110; //      **
-         11'h5cb: data = 8'b00000010; //       *
-         11'h5cc: data = 8'b00000000; // 
-         11'h5cd: data = 8'b00000000; // 
-         11'h5ce: data = 8'b00000000; // 
-         11'h5cf: data = 8'b00000000; // 
-         //code x5d   
-         11'h5d0: data = 8'b00000000; // 
-         11'h5d1: data = 8'b00000000; // 
-         11'h5d2: data = 8'b00111100; //   ****
-         11'h5d3: data = 8'b00001100; //     **
-         11'h5d4: data = 8'b00001100; //     **
-         11'h5d5: data = 8'b00001100; //     **
-         11'h5d6: data = 8'b00001100; //     **
-         11'h5d7: data = 8'b00001100; //     **
-         11'h5d8: data = 8'b00001100; //     **
-         11'h5d9: data = 8'b00001100; //     **
-         11'h5da: data = 8'b00001100; //     **
-         11'h5db: data = 8'b00111100; //   ****
-         11'h5dc: data = 8'b00000000; // 
-         11'h5dd: data = 8'b00000000; // 
-         11'h5de: data = 8'b00000000; // 
-         11'h5df: data = 8'b00000000; // 
-         //code x5e   
-         11'h5e0: data = 8'b00010000; //    *
-         11'h5e1: data = 8'b00111000; //   ***
-         11'h5e2: data = 8'b01101100; //  ** **
-         11'h5e3: data = 8'b11000110; // **   **
-         11'h5e4: data = 8'b00000000; // 
-         11'h5e5: data = 8'b00000000; // 
-         11'h5e6: data = 8'b00000000; // 
-         11'h5e7: data = 8'b00000000; // 
-         11'h5e8: data = 8'b00000000; // 
-         11'h5e9: data = 8'b00000000; // 
-         11'h5ea: data = 8'b00000000; // 
-         11'h5eb: data = 8'b00000000; // 
-         11'h5ec: data = 8'b00000000; // 
-         11'h5ed: data = 8'b00000000; // 
-         11'h5ee: data = 8'b00000000; // 
-         11'h5ef: data = 8'b00000000; // 
-         //code x5f   
-         11'h5f0: data = 8'b00000000; // 
-         11'h5f1: data = 8'b00000000; // 
-         11'h5f2: data = 8'b00000000; // 
-         11'h5f3: data = 8'b00000000; // 
-         11'h5f4: data = 8'b00000000; // 
-         11'h5f5: data = 8'b00000000; // 
-         11'h5f6: data = 8'b00000000; // 
-         11'h5f7: data = 8'b00000000; // 
-         11'h5f8: data = 8'b00000000; // 
-         11'h5f9: data = 8'b00000000; // 
-         11'h5fa: data = 8'b00000000; // 
-         11'h5fb: data = 8'b00000000; // 
-         11'h5fc: data = 8'b00000000; // 
-         11'h5fd: data = 8'b11111111; // ********
-         11'h5fe: data = 8'b00000000; // 
-         11'h5ff: data = 8'b00000000; // 
-         //code x60   
-         11'h600: data = 8'b00110000; //   **
-         11'h601: data = 8'b00110000; //   **
-         11'h602: data = 8'b00011000; //    **
-         11'h603: data = 8'b00000000; // 
-         11'h604: data = 8'b00000000; // 
-         11'h605: data = 8'b00000000; // 
-         11'h606: data = 8'b00000000; // 
-         11'h607: data = 8'b00000000; // 
-         11'h608: data = 8'b00000000; // 
-         11'h609: data = 8'b00000000; // 
-         11'h60a: data = 8'b00000000; // 
-         11'h60b: data = 8'b00000000; // 
-         11'h60c: data = 8'b00000000; // 
-         11'h60d: data = 8'b00000000; // 
-         11'h60e: data = 8'b00000000; // 
-         11'h60f: data = 8'b00000000; // 
-         //code x61   
-         11'h610: data = 8'b00000000; // 
-         11'h611: data = 8'b00000000; // 
-         11'h612: data = 8'b00000000; // 
-         11'h613: data = 8'b00000000; // 
-         11'h614: data = 8'b00000000; // 
-         11'h615: data = 8'b01111000; //  ****
-         11'h616: data = 8'b00001100; //     **
-         11'h617: data = 8'b01111100; //  *****
-         11'h618: data = 8'b11001100; // **  **
-         11'h619: data = 8'b11001100; // **  **
-         11'h61a: data = 8'b11001100; // **  **
-         11'h61b: data = 8'b01110110; //  *** **
-         11'h61c: data = 8'b00000000; // 
-         11'h61d: data = 8'b00000000; // 
-         11'h61e: data = 8'b00000000; // 
-         11'h61f: data = 8'b00000000; // 
-         //code x62   
-         11'h620: data = 8'b00000000; // 
-         11'h621: data = 8'b00000000; // 
-         11'h622: data = 8'b11100000; //  ***
-         11'h623: data = 8'b01100000; //   **
-         11'h624: data = 8'b01100000; //   **
-         11'h625: data = 8'b01111000; //   ****
-         11'h626: data = 8'b01101100; //   ** **
-         11'h627: data = 8'b01100110; //   **  **
-         11'h628: data = 8'b01100110; //   **  **
-         11'h629: data = 8'b01100110; //   **  **
-         11'h62a: data = 8'b01100110; //   **  **
-         11'h62b: data = 8'b01111100; //   *****
-         11'h62c: data = 8'b00000000; // 
-         11'h62d: data = 8'b00000000; // 
-         11'h62e: data = 8'b00000000; // 
-         11'h62f: data = 8'b00000000; // 
-         //code x63   
-         11'h630: data = 8'b00000000; // 
-         11'h631: data = 8'b00000000; // 
-         11'h632: data = 8'b00000000; // 
-         11'h633: data = 8'b00000000; // 
-         11'h634: data = 8'b00000000; // 
-         11'h635: data = 8'b01111100; //  *****
-         11'h636: data = 8'b11000110; // **   **
-         11'h637: data = 8'b11000000; // **
-         11'h638: data = 8'b11000000; // **
-         11'h639: data = 8'b11000000; // **
-         11'h63a: data = 8'b11000110; // **   **
-         11'h63b: data = 8'b01111100; //  *****
-         11'h63c: data = 8'b00000000; // 
-         11'h63d: data = 8'b00000000; // 
-         11'h63e: data = 8'b00000000; // 
-         11'h63f: data = 8'b00000000; // 
-         //code x64   
-         11'h640: data = 8'b00000000; // 
-         11'h641: data = 8'b00000000; // 
-         11'h642: data = 8'b00011100; //    ***
-         11'h643: data = 8'b00001100; //     **
-         11'h644: data = 8'b00001100; //     **
-         11'h645: data = 8'b00111100; //   ****
-         11'h646: data = 8'b01101100; //  ** **
-         11'h647: data = 8'b11001100; // **  **
-         11'h648: data = 8'b11001100; // **  **
-         11'h649: data = 8'b11001100; // **  **
-         11'h64a: data = 8'b11001100; // **  **
-         11'h64b: data = 8'b01110110; //  *** **
-         11'h64c: data = 8'b00000000; // 
-         11'h64d: data = 8'b00000000; // 
-         11'h64e: data = 8'b00000000; // 
-         11'h64f: data = 8'b00000000; // 
-         //code x65   
-         11'h650: data = 8'b00000000; // 
-         11'h651: data = 8'b00000000; // 
-         11'h652: data = 8'b00000000; // 
-         11'h653: data = 8'b00000000; // 
-         11'h654: data = 8'b00000000; // 
-         11'h655: data = 8'b01111100; //  *****
-         11'h656: data = 8'b11000110; // **   **
-         11'h657: data = 8'b11111110; // *******
-         11'h658: data = 8'b11000000; // **
-         11'h659: data = 8'b11000000; // **
-         11'h65a: data = 8'b11000110; // **   **
-         11'h65b: data = 8'b01111100; //  *****
-         11'h65c: data = 8'b00000000; // 
-         11'h65d: data = 8'b00000000; // 
-         11'h65e: data = 8'b00000000; // 
-         11'h65f: data = 8'b00000000; // 
-         //code x66   
-         11'h660: data = 8'b00000000; // 
-         11'h661: data = 8'b00000000; // 
-         11'h662: data = 8'b00111000; //   ***
-         11'h663: data = 8'b01101100; //  ** **
-         11'h664: data = 8'b01100100; //  **  *
-         11'h665: data = 8'b01100000; //  **
-         11'h666: data = 8'b11110000; // ****
-         11'h667: data = 8'b01100000; //  **
-         11'h668: data = 8'b01100000; //  **
-         11'h669: data = 8'b01100000; //  **
-         11'h66a: data = 8'b01100000; //  **
-         11'h66b: data = 8'b11110000; // ****
-         11'h66c: data = 8'b00000000; // 
-         11'h66d: data = 8'b00000000; // 
-         11'h66e: data = 8'b00000000; // 
-         11'h66f: data = 8'b00000000; // 
-         //code x67   
-         11'h670: data = 8'b00000000; // 
-         11'h671: data = 8'b00000000; // 
-         11'h672: data = 8'b00000000; // 
-         11'h673: data = 8'b00000000; // 
-         11'h674: data = 8'b00000000; // 
-         11'h675: data = 8'b01110110; //  *** **
-         11'h676: data = 8'b11001100; // **  **
-         11'h677: data = 8'b11001100; // **  **
-         11'h678: data = 8'b11001100; // **  **
-         11'h679: data = 8'b11001100; // **  **
-         11'h67a: data = 8'b11001100; // **  **
-         11'h67b: data = 8'b01111100; //  *****
-         11'h67c: data = 8'b00001100; //     **
-         11'h67d: data = 8'b11001100; // **  **
-         11'h67e: data = 8'b01111000; //  ****
-         11'h67f: data = 8'b00000000; // 
-         //code x68   
-         11'h680: data = 8'b00000000; // 
-         11'h681: data = 8'b00000000; // 
-         11'h682: data = 8'b11100000; // ***
-         11'h683: data = 8'b01100000; //  **
-         11'h684: data = 8'b01100000; //  **
-         11'h685: data = 8'b01101100; //  ** **
-         11'h686: data = 8'b01110110; //  *** **
-         11'h687: data = 8'b01100110; //  **  **
-         11'h688: data = 8'b01100110; //  **  **
-         11'h689: data = 8'b01100110; //  **  **
-         11'h68a: data = 8'b01100110; //  **  **
-         11'h68b: data = 8'b11100110; // ***  **
-         11'h68c: data = 8'b00000000; // 
-         11'h68d: data = 8'b00000000; // 
-         11'h68e: data = 8'b00000000; // 
-         11'h68f: data = 8'b00000000; // 
-         //code x69   
-         11'h690: data = 8'b00000000; // 
-         11'h691: data = 8'b00000000; // 
-         11'h692: data = 8'b00011000; //    **
-         11'h693: data = 8'b00011000; //    **
-         11'h694: data = 8'b00000000; // 
-         11'h695: data = 8'b00111000; //   ***
-         11'h696: data = 8'b00011000; //    **
-         11'h697: data = 8'b00011000; //    **
-         11'h698: data = 8'b00011000; //    **
-         11'h699: data = 8'b00011000; //    **
-         11'h69a: data = 8'b00011000; //    **
-         11'h69b: data = 8'b00111100; //   ****
-         11'h69c: data = 8'b00000000; // 
-         11'h69d: data = 8'b00000000; // 
-         11'h69e: data = 8'b00000000; // 
-         11'h69f: data = 8'b00000000; // 
-         //code x6a   
-         11'h6a0: data = 8'b00000000; // 
-         11'h6a1: data = 8'b00000000; // 
-         11'h6a2: data = 8'b00000110; //      **
-         11'h6a3: data = 8'b00000110; //      **
-         11'h6a4: data = 8'b00000000; // 
-         11'h6a5: data = 8'b00001110; //     ***
-         11'h6a6: data = 8'b00000110; //      **
-         11'h6a7: data = 8'b00000110; //      **
-         11'h6a8: data = 8'b00000110; //      **
-         11'h6a9: data = 8'b00000110; //      **
-         11'h6aa: data = 8'b00000110; //      **
-         11'h6ab: data = 8'b00000110; //      **
-         11'h6ac: data = 8'b01100110; //  **  **
-         11'h6ad: data = 8'b01100110; //  **  **
-         11'h6ae: data = 8'b00111100; //   ****
-         11'h6af: data = 8'b00000000; // 
-         //code x6b   
-         11'h6b0: data = 8'b00000000; // 
-         11'h6b1: data = 8'b00000000; // 
-         11'h6b2: data = 8'b11100000; // ***
-         11'h6b3: data = 8'b01100000; //  **
-         11'h6b4: data = 8'b01100000; //  **
-         11'h6b5: data = 8'b01100110; //  **  **
-         11'h6b6: data = 8'b01101100; //  ** **
-         11'h6b7: data = 8'b01111000; //  ****
-         11'h6b8: data = 8'b01111000; //  ****
-         11'h6b9: data = 8'b01101100; //  ** **
-         11'h6ba: data = 8'b01100110; //  **  **
-         11'h6bb: data = 8'b11100110; // ***  **
-         11'h6bc: data = 8'b00000000; // 
-         11'h6bd: data = 8'b00000000; // 
-         11'h6be: data = 8'b00000000; // 
-         11'h6bf: data = 8'b00000000; // 
-         //code x6c   
-         11'h6c0: data = 8'b00000000; // 
-         11'h6c1: data = 8'b00000000; // 
-         11'h6c2: data = 8'b00111000; //   ***
-         11'h6c3: data = 8'b00011000; //    **
-         11'h6c4: data = 8'b00011000; //    **
-         11'h6c5: data = 8'b00011000; //    **
-         11'h6c6: data = 8'b00011000; //    **
-         11'h6c7: data = 8'b00011000; //    **
-         11'h6c8: data = 8'b00011000; //    **
-         11'h6c9: data = 8'b00011000; //    **
-         11'h6ca: data = 8'b00011000; //    **
-         11'h6cb: data = 8'b00111100; //   ****
-         11'h6cc: data = 8'b00000000; // 
-         11'h6cd: data = 8'b00000000; // 
-         11'h6ce: data = 8'b00000000; // 
-         11'h6cf: data = 8'b00000000; // 
-         //code x6d   
-         11'h6d0: data = 8'b00000000; // 
-         11'h6d1: data = 8'b00000000; // 
-         11'h6d2: data = 8'b00000000; // 
-         11'h6d3: data = 8'b00000000; // 
-         11'h6d4: data = 8'b00000000; // 
-         11'h6d5: data = 8'b11100110; // ***  **
-         11'h6d6: data = 8'b11111111; // ********
-         11'h6d7: data = 8'b11011011; // ** ** **
-         11'h6d8: data = 8'b11011011; // ** ** **
-         11'h6d9: data = 8'b11011011; // ** ** **
-         11'h6da: data = 8'b11011011; // ** ** **
-         11'h6db: data = 8'b11011011; // ** ** **
-         11'h6dc: data = 8'b00000000; // 
-         11'h6dd: data = 8'b00000000; // 
-         11'h6de: data = 8'b00000000; // 
-         11'h6df: data = 8'b00000000; // 
-         //code x6e   
-         11'h6e0: data = 8'b00000000; // 
-         11'h6e1: data = 8'b00000000; // 
-         11'h6e2: data = 8'b00000000; // 
-         11'h6e3: data = 8'b00000000; // 
-         11'h6e4: data = 8'b00000000; // 
-         11'h6e5: data = 8'b11011100; // ** ***
-         11'h6e6: data = 8'b01100110; //  **  **
-         11'h6e7: data = 8'b01100110; //  **  **
-         11'h6e8: data = 8'b01100110; //  **  **
-         11'h6e9: data = 8'b01100110; //  **  **
-         11'h6ea: data = 8'b01100110; //  **  **
-         11'h6eb: data = 8'b01100110; //  **  **
-         11'h6ec: data = 8'b00000000; // 
-         11'h6ed: data = 8'b00000000; // 
-         11'h6ee: data = 8'b00000000; // 
-         11'h6ef: data = 8'b00000000; // 
-         //code x6f   
-         11'h6f0: data = 8'b00000000; // 
-         11'h6f1: data = 8'b00000000; // 
-         11'h6f2: data = 8'b00000000; // 
-         11'h6f3: data = 8'b00000000; // 
-         11'h6f4: data = 8'b00000000; // 
-         11'h6f5: data = 8'b01111100; //  *****
-         11'h6f6: data = 8'b11000110; // **   **
-         11'h6f7: data = 8'b11000110; // **   **
-         11'h6f8: data = 8'b11000110; // **   **
-         11'h6f9: data = 8'b11000110; // **   **
-         11'h6fa: data = 8'b11000110; // **   **
-         11'h6fb: data = 8'b01111100; //  *****
-         11'h6fc: data = 8'b00000000; // 
-         11'h6fd: data = 8'b00000000; // 
-         11'h6fe: data = 8'b00000000; // 
-         11'h6ff: data = 8'b00000000; // 
-         //code x70   
-         11'h700: data = 8'b00000000; // 
-         11'h701: data = 8'b00000000; // 
-         11'h702: data = 8'b00000000; // 
-         11'h703: data = 8'b00000000; // 
-         11'h704: data = 8'b00000000; // 
-         11'h705: data = 8'b11011100; // ** ***
-         11'h706: data = 8'b01100110; //  **  **
-         11'h707: data = 8'b01100110; //  **  **
-         11'h708: data = 8'b01100110; //  **  **
-         11'h709: data = 8'b01100110; //  **  **
-         11'h70a: data = 8'b01100110; //  **  **
-         11'h70b: data = 8'b01111100; //  *****
-         11'h70c: data = 8'b01100000; //  **
-         11'h70d: data = 8'b01100000; //  **
-         11'h70e: data = 8'b11110000; // ****
-         11'h70f: data = 8'b00000000; // 
-         //code x71   
-         11'h710: data = 8'b00000000; // 
-         11'h711: data = 8'b00000000; // 
-         11'h712: data = 8'b00000000; // 
-         11'h713: data = 8'b00000000; // 
-         11'h714: data = 8'b00000000; // 
-         11'h715: data = 8'b01110110; //  *** **
-         11'h716: data = 8'b11001100; // **  **
-         11'h717: data = 8'b11001100; // **  **
-         11'h718: data = 8'b11001100; // **  **
-         11'h719: data = 8'b11001100; // **  **
-         11'h71a: data = 8'b11001100; // **  **
-         11'h71b: data = 8'b01111100; //  *****
-         11'h71c: data = 8'b00001100; //     **
-         11'h71d: data = 8'b00001100; //     **
-         11'h71e: data = 8'b00011110; //    ****
-         11'h71f: data = 8'b00000000; // 
-         //code x72   
-         11'h720: data = 8'b00000000; // 
-         11'h721: data = 8'b00000000; // 
-         11'h722: data = 8'b00000000; // 
-         11'h723: data = 8'b00000000; // 
-         11'h724: data = 8'b00000000; // 
-         11'h725: data = 8'b11011100; // ** ***
-         11'h726: data = 8'b01110110; //  *** **
-         11'h727: data = 8'b01100110; //  **  **
-         11'h728: data = 8'b01100000; //  **
-         11'h729: data = 8'b01100000; //  **
-         11'h72a: data = 8'b01100000; //  **
-         11'h72b: data = 8'b11110000; // ****
-         11'h72c: data = 8'b00000000; // 
-         11'h72d: data = 8'b00000000; // 
-         11'h72e: data = 8'b00000000; // 
-         11'h72f: data = 8'b00000000; // 
-         //code x73   
-         11'h730: data = 8'b00000000; // 
-         11'h731: data = 8'b00000000; // 
-         11'h732: data = 8'b00000000; // 
-         11'h733: data = 8'b00000000; // 
-         11'h734: data = 8'b00000000; // 
-         11'h735: data = 8'b01111100; //  *****
-         11'h736: data = 8'b11000110; // **   **
-         11'h737: data = 8'b01100000; //  **
-         11'h738: data = 8'b00111000; //   ***
-         11'h739: data = 8'b00001100; //     **
-         11'h73a: data = 8'b11000110; // **   **
-         11'h73b: data = 8'b01111100; //  *****
-         11'h73c: data = 8'b00000000; // 
-         11'h73d: data = 8'b00000000; // 
-         11'h73e: data = 8'b00000000; // 
-         11'h73f: data = 8'b00000000; // 
-         //code x74   
-         11'h740: data = 8'b00000000; // 
-         11'h741: data = 8'b00000000; // 
-         11'h742: data = 8'b00010000; //    *
-         11'h743: data = 8'b00110000; //   **
-         11'h744: data = 8'b00110000; //   **
-         11'h745: data = 8'b11111100; // ******
-         11'h746: data = 8'b00110000; //   **
-         11'h747: data = 8'b00110000; //   **
-         11'h748: data = 8'b00110000; //   **
-         11'h749: data = 8'b00110000; //   **
-         11'h74a: data = 8'b00110110; //   ** **
-         11'h74b: data = 8'b00011100; //    ***
-         11'h74c: data = 8'b00000000; // 
-         11'h74d: data = 8'b00000000; // 
-         11'h74e: data = 8'b00000000; // 
-         11'h74f: data = 8'b00000000; // 
-         //code x75   
-         11'h750: data = 8'b00000000; // 
-         11'h751: data = 8'b00000000; // 
-         11'h752: data = 8'b00000000; // 
-         11'h753: data = 8'b00000000; // 
-         11'h754: data = 8'b00000000; // 
-         11'h755: data = 8'b11001100; // **  **
-         11'h756: data = 8'b11001100; // **  **
-         11'h757: data = 8'b11001100; // **  **
-         11'h758: data = 8'b11001100; // **  **
-         11'h759: data = 8'b11001100; // **  **
-         11'h75a: data = 8'b11001100; // **  **
-         11'h75b: data = 8'b01110110; //  *** **
-         11'h75c: data = 8'b00000000; // 
-         11'h75d: data = 8'b00000000; // 
-         11'h75e: data = 8'b00000000; // 
-         11'h75f: data = 8'b00000000; // 
-         //code x76   
-         11'h760: data = 8'b00000000; // 
-         11'h761: data = 8'b00000000; // 
-         11'h762: data = 8'b00000000; // 
-         11'h763: data = 8'b00000000; // 
-         11'h764: data = 8'b00000000; // 
-         11'h765: data = 8'b11000011; // **    **
-         11'h766: data = 8'b11000011; // **    **
-         11'h767: data = 8'b11000011; // **    **
-         11'h768: data = 8'b11000011; // **    **
-         11'h769: data = 8'b01100110; //  **  **
-         11'h76a: data = 8'b00111100; //   ****
-         11'h76b: data = 8'b00011000; //    **
-         11'h76c: data = 8'b00000000; // 
-         11'h76d: data = 8'b00000000; // 
-         11'h76e: data = 8'b00000000; // 
-         11'h76f: data = 8'b00000000; // 
-         //code x77   
-         11'h770: data = 8'b00000000; // 
-         11'h771: data = 8'b00000000; // 
-         11'h772: data = 8'b00000000; // 
-         11'h773: data = 8'b00000000; // 
-         11'h774: data = 8'b00000000; // 
-         11'h775: data = 8'b11000011; // **    **
-         11'h776: data = 8'b11000011; // **    **
-         11'h777: data = 8'b11000011; // **    **
-         11'h778: data = 8'b11011011; // ** ** **
-         11'h779: data = 8'b11011011; // ** ** **
-         11'h77a: data = 8'b11111111; // ********
-         11'h77b: data = 8'b01100110; //  **  **
-         11'h77c: data = 8'b00000000; // 
-         11'h77d: data = 8'b00000000; // 
-         11'h77e: data = 8'b00000000; // 
-         11'h77f: data = 8'b00000000; // 
-         //code x78   
-         11'h780: data = 8'b00000000; // 
-         11'h781: data = 8'b00000000; // 
-         11'h782: data = 8'b00000000; // 
-         11'h783: data = 8'b00000000; // 
-         11'h784: data = 8'b00000000; // 
-         11'h785: data = 8'b11000011; // **    **
-         11'h786: data = 8'b01100110; //  **  **
-         11'h787: data = 8'b00111100; //   ****
-         11'h788: data = 8'b00011000; //    **
-         11'h789: data = 8'b00111100; //   ****
-         11'h78a: data = 8'b01100110; //  **  **
-         11'h78b: data = 8'b11000011; // **    **
-         11'h78c: data = 8'b00000000; // 
-         11'h78d: data = 8'b00000000; // 
-         11'h78e: data = 8'b00000000; // 
-         11'h78f: data = 8'b00000000; // 
-         //code x79   
-         11'h790: data = 8'b00000000; // 
-         11'h791: data = 8'b00000000; // 
-         11'h792: data = 8'b00000000; // 
-         11'h793: data = 8'b00000000; // 
-         11'h794: data = 8'b00000000; // 
-         11'h795: data = 8'b11000110; // **   **
-         11'h796: data = 8'b11000110; // **   **
-         11'h797: data = 8'b11000110; // **   **
-         11'h798: data = 8'b11000110; // **   **
-         11'h799: data = 8'b11000110; // **   **
-         11'h79a: data = 8'b11000110; // **   **
-         11'h79b: data = 8'b01111110; //  ******
-         11'h79c: data = 8'b00000110; //      **
-         11'h79d: data = 8'b00001100; //     **
-         11'h79e: data = 8'b11111000; // *****
-         11'h79f: data = 8'b00000000; // 
-         //code x7a   
-         11'h7a0: data = 8'b00000000; // 
-         11'h7a1: data = 8'b00000000; // 
-         11'h7a2: data = 8'b00000000; // 
-         11'h7a3: data = 8'b00000000; // 
-         11'h7a4: data = 8'b00000000; // 
-         11'h7a5: data = 8'b11111110; // *******
-         11'h7a6: data = 8'b11001100; // **  **
-         11'h7a7: data = 8'b00011000; //    **
-         11'h7a8: data = 8'b00110000; //   **
-         11'h7a9: data = 8'b01100000; //  **
-         11'h7aa: data = 8'b11000110; // **   **
-         11'h7ab: data = 8'b11111110; // *******
-         11'h7ac: data = 8'b00000000; // 
-         11'h7ad: data = 8'b00000000; // 
-         11'h7ae: data = 8'b00000000; // 
-         11'h7af: data = 8'b00000000; // 
-         //code x7b   
-         11'h7b0: data = 8'b00000000; // 
-         11'h7b1: data = 8'b00000000; // 
-         11'h7b2: data = 8'b00001110; //     ***
-         11'h7b3: data = 8'b00011000; //    **
-         11'h7b4: data = 8'b00011000; //    **
-         11'h7b5: data = 8'b00011000; //    **
-         11'h7b6: data = 8'b01110000; //  ***
-         11'h7b7: data = 8'b00011000; //    **
-         11'h7b8: data = 8'b00011000; //    **
-         11'h7b9: data = 8'b00011000; //    **
-         11'h7ba: data = 8'b00011000; //    **
-         11'h7bb: data = 8'b00001110; //     ***
-         11'h7bc: data = 8'b00000000; // 
-         11'h7bd: data = 8'b00000000; // 
-         11'h7be: data = 8'b00000000; // 
-         11'h7bf: data = 8'b00000000; // 
-         //code x7c   
-         11'h7c0: data = 8'b00000000; // 
-         11'h7c1: data = 8'b00000000; // 
-         11'h7c2: data = 8'b00011000; //    **
-         11'h7c3: data = 8'b00011000; //    **
-         11'h7c4: data = 8'b00011000; //    **
-         11'h7c5: data = 8'b00011000; //    **
-         11'h7c6: data = 8'b00000000; // 
-         11'h7c7: data = 8'b00011000; //    **
-         11'h7c8: data = 8'b00011000; //    **
-         11'h7c9: data = 8'b00011000; //    **
-         11'h7ca: data = 8'b00011000; //    **
-         11'h7cb: data = 8'b00011000; //    **
-         11'h7cc: data = 8'b00000000; // 
-         11'h7cd: data = 8'b00000000; // 
-         11'h7ce: data = 8'b00000000; // 
-         11'h7cf: data = 8'b00000000; // 
-         //code x7d   
-         11'h7d0: data = 8'b00000000; // 
-         11'h7d1: data = 8'b00000000; // 
-         11'h7d2: data = 8'b01110000; //  ***
-         11'h7d3: data = 8'b00011000; //    **
-         11'h7d4: data = 8'b00011000; //    **
-         11'h7d5: data = 8'b00011000; //    **
-         11'h7d6: data = 8'b00001110; //     ***
-         11'h7d7: data = 8'b00011000; //    **
-         11'h7d8: data = 8'b00011000; //    **
-         11'h7d9: data = 8'b00011000; //    **
-         11'h7da: data = 8'b00011000; //    **
-         11'h7db: data = 8'b01110000; //  ***
-         11'h7dc: data = 8'b00000000; // 
-         11'h7dd: data = 8'b00000000; // 
-         11'h7de: data = 8'b00000000; // 
-         11'h7df: data = 8'b00000000; // 
-         //code x7e   
-         11'h7e0: data = 8'b00000000; // 
-         11'h7e1: data = 8'b00000000; // 
-         11'h7e2: data = 8'b01110110; //  *** **
-         11'h7e3: data = 8'b11011100; // ** ***
-         11'h7e4: data = 8'b00000000; // 
-         11'h7e5: data = 8'b00000000; // 
-         11'h7e6: data = 8'b00000000; // 
-         11'h7e7: data = 8'b00000000; // 
-         11'h7e8: data = 8'b00000000; // 
-         11'h7e9: data = 8'b00000000; // 
-         11'h7ea: data = 8'b00000000; // 
-         11'h7eb: data = 8'b00000000; // 
-         11'h7ec: data = 8'b00000000; // 
-         11'h7ed: data = 8'b00000000; // 
-         11'h7ee: data = 8'b00000000; // 
-         11'h7ef: data = 8'b00000000; // 
-         //code x7f   
-         11'h7f0: data = 8'b00000000; // 
-         11'h7f1: data = 8'b00000000; // 
-         11'h7f2: data = 8'b00000000; // 
-         11'h7f3: data = 8'b00000000; // 
-         11'h7f4: data = 8'b00010000; //    *
-         11'h7f5: data = 8'b00111000; //   ***
-         11'h7f6: data = 8'b01101100; //  ** **
-         11'h7f7: data = 8'b11000110; // **   **
-         11'h7f8: data = 8'b11000110; // **   **
-         11'h7f9: data = 8'b11000110; // **   **
-         11'h7fa: data = 8'b11111110; // *******
-         11'h7fb: data = 8'b00000000; // 
-         11'h7fc: data = 8'b00000000; // 
-         11'h7fd: data = 8'b00000000; // 
-         11'h7fe: data = 8'b00000000; // 
-         11'h7ff: data = 8'b00000000; // 	 
-   endcase  
-   	       
-endmodule
\ No newline at end of file
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/debounce.v b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/debounce.v
deleted file mode 100644
index 0aa3f70..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/debounce.v
+++ /dev/null
@@ -1,33 +0,0 @@
-`timescale 1ns / 1ps
-
-module debounce(
-		input wire clk,
-		input wire button,
-		output reg pbreg
-	);
-
-	reg [2:0] count;
-
-	always @(posedge clk)
-	begin
-		if(button == 0)
-		begin
-			pbreg = 0;
-			count = 0;
-		end
-		else
-		begin
-			if(count < 7)
-			begin
-				count = count + 1;
-				pbreg = 0;
-			end
-			else
-			begin
-				count = 7;
-				pbreg = 1;
-			end
-		end
-	end
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/front_rom.v b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/front_rom.v
deleted file mode 100644
index bd22c8d..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/front_rom.v
+++ /dev/null
@@ -1,2192 +0,0 @@
-module font_rom
-   (
-    input wire clk,
-    input wire [10:0] addr,
-    output reg [7:0] data
-   );
-   reg [10:0] addr_reg; 
-	
-   always @(posedge clk) 
-      addr_reg <= addr;
-      
-   always @*
-      case (addr_reg)
-         //code x00
-         11'h000: data = 8'b00000000; // 
-         11'h001: data = 8'b00000000; // 
-         11'h002: data = 8'b00000000; // 
-         11'h003: data = 8'b00000000; // 
-         11'h004: data = 8'b00000000; // 
-         11'h005: data = 8'b00000000; // 
-         11'h006: data = 8'b00000000; // 
-         11'h007: data = 8'b00000000; // 
-         11'h008: data = 8'b00000000; // 
-         11'h009: data = 8'b00000000; // 
-         11'h00a: data = 8'b00000000; // 
-         11'h00b: data = 8'b00000000; // 
-         11'h00c: data = 8'b00000000; // 
-         11'h00d: data = 8'b00000000; // 
-         11'h00e: data = 8'b00000000; // 
-         11'h00f: data = 8'b00000000; // 
-         //code x01
-         11'h010: data = 8'b00000000; // 
-         11'h011: data = 8'b00000000; // 
-         11'h012: data = 8'b01111110; //  ******
-         11'h013: data = 8'b10000001; // *      *
-         11'h014: data = 8'b10100101; // * *  * *
-         11'h015: data = 8'b10000001; // *      *
-         11'h016: data = 8'b10000001; // *      *
-         11'h017: data = 8'b10111101; // * **** *
-         11'h018: data = 8'b10011001; // *  **  *
-         11'h019: data = 8'b10000001; // *      *
-         11'h01a: data = 8'b10000001; // *      *
-         11'h01b: data = 8'b01111110; //  ******
-         11'h01c: data = 8'b00000000; // 
-         11'h01d: data = 8'b00000000; // 
-         11'h01e: data = 8'b00000000; // 
-         11'h01f: data = 8'b00000000; // 
-         //code x02
-         11'h020: data = 8'b00000000; // 
-         11'h021: data = 8'b00000000; // 
-         11'h022: data = 8'b01111110; //  ******
-         11'h023: data = 8'b11111111; // ********
-         11'h024: data = 8'b11011011; // ** ** **
-         11'h025: data = 8'b11111111; // ********
-         11'h026: data = 8'b11111111; // ********
-         11'h027: data = 8'b11000011; // **    **
-         11'h028: data = 8'b11100111; // ***  ***
-         11'h029: data = 8'b11111111; // ********
-         11'h02a: data = 8'b11111111; // ********
-         11'h02b: data = 8'b01111110; //  ******
-         11'h02c: data = 8'b00000000; // 
-         11'h02d: data = 8'b00000000; // 
-         11'h02e: data = 8'b00000000; // 
-         11'h02f: data = 8'b00000000; // 
-         //code x03
-         11'h030: data = 8'b00000000; // 
-         11'h031: data = 8'b00000000; // 
-         11'h032: data = 8'b00000000; // 
-         11'h033: data = 8'b00000000; // 
-         11'h034: data = 8'b01101100; //  ** **
-         11'h035: data = 8'b11111110; // *******
-         11'h036: data = 8'b11111110; // *******
-         11'h037: data = 8'b11111110; // *******
-         11'h038: data = 8'b11111110; // *******
-         11'h039: data = 8'b01111100; //  *****
-         11'h03a: data = 8'b00111000; //   ***
-         11'h03b: data = 8'b00010000; //    *
-         11'h03c: data = 8'b00000000; // 
-         11'h03d: data = 8'b00000000; // 
-         11'h03e: data = 8'b00000000; // 
-         11'h03f: data = 8'b00000000; // 
-         //code x04
-         11'h040: data = 8'b00000000; // 
-         11'h041: data = 8'b00000000; // 
-         11'h042: data = 8'b00000000; // 
-         11'h043: data = 8'b00000000; // 
-         11'h044: data = 8'b00010000; //    *
-         11'h045: data = 8'b00111000; //   ***
-         11'h046: data = 8'b01111100; //  *****
-         11'h047: data = 8'b11111110; // *******
-         11'h048: data = 8'b01111100; //  *****
-         11'h049: data = 8'b00111000; //   ***
-         11'h04a: data = 8'b00010000; //    *
-         11'h04b: data = 8'b00000000; // 
-         11'h04c: data = 8'b00000000; // 
-         11'h04d: data = 8'b00000000; // 
-         11'h04e: data = 8'b00000000; // 
-         11'h04f: data = 8'b00000000; // 
-         //code x05
-         11'h050: data = 8'b00000000; // 
-         11'h051: data = 8'b00000000; // 
-         11'h052: data = 8'b00000000; // 
-         11'h053: data = 8'b00011000; //    **
-         11'h054: data = 8'b00111100; //   ****
-         11'h055: data = 8'b00111100; //   ****
-         11'h056: data = 8'b11100111; // ***  ***
-         11'h057: data = 8'b11100111; // ***  ***
-         11'h058: data = 8'b11100111; // ***  ***
-         11'h059: data = 8'b00011000; //    **
-         11'h05a: data = 8'b00011000; //    **
-         11'h05b: data = 8'b00111100; //   ****
-         11'h05c: data = 8'b00000000; // 
-         11'h05d: data = 8'b00000000; // 
-         11'h05e: data = 8'b00000000; // 
-         11'h05f: data = 8'b00000000; // 
-         //code x06
-         11'h060: data = 8'b00000000; // 
-         11'h061: data = 8'b00000000; // 
-         11'h062: data = 8'b00000000; // 
-         11'h063: data = 8'b00011000; //    **
-         11'h064: data = 8'b00111100; //   ****
-         11'h065: data = 8'b01111110; //  ******
-         11'h066: data = 8'b11111111; // ********
-         11'h067: data = 8'b11111111; // ********
-         11'h068: data = 8'b01111110; //  ******
-         11'h069: data = 8'b00011000; //    **
-         11'h06a: data = 8'b00011000; //    **
-         11'h06b: data = 8'b00111100; //   ****
-         11'h06c: data = 8'b00000000; // 
-         11'h06d: data = 8'b00000000; // 
-         11'h06e: data = 8'b00000000; // 
-         11'h06f: data = 8'b00000000; // 
-         //code x07
-         11'h070: data = 8'b00000000; // 
-         11'h071: data = 8'b00000000; // 
-         11'h072: data = 8'b00000000; // 
-         11'h073: data = 8'b00000000; // 
-         11'h074: data = 8'b00000000; // 
-         11'h075: data = 8'b00000000; // 
-         11'h076: data = 8'b00011000; //    **
-         11'h077: data = 8'b00111100; //   ****
-         11'h078: data = 8'b00111100; //   ****
-         11'h079: data = 8'b00011000; //    **
-         11'h07a: data = 8'b00000000; // 
-         11'h07b: data = 8'b00000000; // 
-         11'h07c: data = 8'b00000000; // 
-         11'h07d: data = 8'b00000000; // 
-         11'h07e: data = 8'b00000000; // 
-         11'h07f: data = 8'b00000000; // 
-         //code x08
-         11'h080: data = 8'b11111111; // ********
-         11'h081: data = 8'b11111111; // ********
-         11'h082: data = 8'b11111111; // ********
-         11'h083: data = 8'b11111111; // ********
-         11'h084: data = 8'b11111111; // ********
-         11'h085: data = 8'b11111111; // ********
-         11'h086: data = 8'b11100111; // ***  ***
-         11'h087: data = 8'b11000011; // **    **
-         11'h088: data = 8'b11000011; // **    **
-         11'h089: data = 8'b11100111; // ***  ***
-         11'h08a: data = 8'b11111111; // ********
-         11'h08b: data = 8'b11111111; // ********
-         11'h08c: data = 8'b11111111; // ********
-         11'h08d: data = 8'b11111111; // ********
-         11'h08e: data = 8'b11111111; // ********
-         11'h08f: data = 8'b11111111; // ********
-         //code x09
-         11'h090: data = 8'b00000000; // 
-         11'h091: data = 8'b00000000; // 
-         11'h092: data = 8'b00000000; // 
-         11'h093: data = 8'b00000000; // 
-         11'h094: data = 8'b00000000; // 
-         11'h095: data = 8'b00111100; //   ****
-         11'h096: data = 8'b01100110; //  **  **
-         11'h097: data = 8'b01000010; //  *    *
-         11'h098: data = 8'b01000010; //  *    *
-         11'h099: data = 8'b01100110; //  **  **
-         11'h09a: data = 8'b00111100; //   ****
-         11'h09b: data = 8'b00000000; // 
-         11'h09c: data = 8'b00000000; // 
-         11'h09d: data = 8'b00000000; // 
-         11'h09e: data = 8'b00000000; // 
-         11'h09f: data = 8'b00000000; // 
-         //code x0a
-         11'h0a0: data = 8'b11111111; // ********
-         11'h0a1: data = 8'b11111111; // ********
-         11'h0a2: data = 8'b11111111; // ********
-         11'h0a3: data = 8'b11111111; // ********
-         11'h0a4: data = 8'b11111111; // ********
-         11'h0a5: data = 8'b11000011; // **    **
-         11'h0a6: data = 8'b10011001; // *  **  *
-         11'h0a7: data = 8'b10111101; // * **** *
-         11'h0a8: data = 8'b10111101; // * **** *
-         11'h0a9: data = 8'b10011001; // *  **  *
-         11'h0aa: data = 8'b11000011; // **    **
-         11'h0ab: data = 8'b11111111; // ********
-         11'h0ac: data = 8'b11111111; // ********
-         11'h0ad: data = 8'b11111111; // ********
-         11'h0ae: data = 8'b11111111; // ********
-         11'h0af: data = 8'b11111111; // ********
-         //code x0b
-         11'h0b0: data = 8'b00000000; // 
-         11'h0b1: data = 8'b00000000; // 
-         11'h0b2: data = 8'b00011110; //    ****
-         11'h0b3: data = 8'b00001110; //     ***
-         11'h0b4: data = 8'b00011010; //    ** *
-         11'h0b5: data = 8'b00110010; //   **  *
-         11'h0b6: data = 8'b01111000; //  ****
-         11'h0b7: data = 8'b11001100; // **  **
-         11'h0b8: data = 8'b11001100; // **  **
-         11'h0b9: data = 8'b11001100; // **  **
-         11'h0ba: data = 8'b11001100; // **  **
-         11'h0bb: data = 8'b01111000; //  ****
-         11'h0bc: data = 8'b00000000; // 
-         11'h0bd: data = 8'b00000000; // 
-         11'h0be: data = 8'b00000000; // 
-         11'h0bf: data = 8'b00000000; // 
-         //code x0c
-         11'h0c0: data = 8'b00000000; // 
-         11'h0c1: data = 8'b00000000; // 
-         11'h0c2: data = 8'b00111100; //   ****
-         11'h0c3: data = 8'b01100110; //  **  **
-         11'h0c4: data = 8'b01100110; //  **  **
-         11'h0c5: data = 8'b01100110; //  **  **
-         11'h0c6: data = 8'b01100110; //  **  **
-         11'h0c7: data = 8'b00111100; //   ****
-         11'h0c8: data = 8'b00011000; //    **
-         11'h0c9: data = 8'b01111110; //  ******
-         11'h0ca: data = 8'b00011000; //    **
-         11'h0cb: data = 8'b00011000; //    **
-         11'h0cc: data = 8'b00000000; // 
-         11'h0cd: data = 8'b00000000; // 
-         11'h0ce: data = 8'b00000000; // 
-         11'h0cf: data = 8'b00000000; // 
-         //code x0d
-         11'h0d0: data = 8'b00000000; // 
-         11'h0d1: data = 8'b00000000; // 
-         11'h0d2: data = 8'b00111111; //   ******
-         11'h0d3: data = 8'b00110011; //   **  **
-         11'h0d4: data = 8'b00111111; //   ******
-         11'h0d5: data = 8'b00110000; //   **
-         11'h0d6: data = 8'b00110000; //   **
-         11'h0d7: data = 8'b00110000; //   **
-         11'h0d8: data = 8'b00110000; //   **
-         11'h0d9: data = 8'b01110000; //  ***
-         11'h0da: data = 8'b11110000; // ****
-         11'h0db: data = 8'b11100000; // ***
-         11'h0dc: data = 8'b00000000; // 
-         11'h0dd: data = 8'b00000000; // 
-         11'h0de: data = 8'b00000000; // 
-         11'h0df: data = 8'b00000000; // 
-         //code x0e
-         11'h0e0: data = 8'b00000000; // 
-         11'h0e1: data = 8'b00000000; // 
-         11'h0e2: data = 8'b01111111; //  *******
-         11'h0e3: data = 8'b01100011; //  **   **
-         11'h0e4: data = 8'b01111111; //  *******
-         11'h0e5: data = 8'b01100011; //  **   **
-         11'h0e6: data = 8'b01100011; //  **   **
-         11'h0e7: data = 8'b01100011; //  **   **
-         11'h0e8: data = 8'b01100011; //  **   **
-         11'h0e9: data = 8'b01100111; //  **  ***
-         11'h0ea: data = 8'b11100111; // ***  ***
-         11'h0eb: data = 8'b11100110; // ***  **
-         11'h0ec: data = 8'b11000000; // **
-         11'h0ed: data = 8'b00000000; // 
-         11'h0ee: data = 8'b00000000; // 
-         11'h0ef: data = 8'b00000000; // 
-         //code x0f
-         11'h0f0: data = 8'b00000000; // 
-         11'h0f1: data = 8'b00000000; // 
-         11'h0f2: data = 8'b00000000; // 
-         11'h0f3: data = 8'b00011000; //    **
-         11'h0f4: data = 8'b00011000; //    **
-         11'h0f5: data = 8'b11011011; // ** ** **
-         11'h0f6: data = 8'b00111100; //   ****
-         11'h0f7: data = 8'b11100111; // ***  ***
-         11'h0f8: data = 8'b00111100; //   ****
-         11'h0f9: data = 8'b11011011; // ** ** **
-         11'h0fa: data = 8'b00011000; //    **
-         11'h0fb: data = 8'b00011000; //    **
-         11'h0fc: data = 8'b00000000; // 
-         11'h0fd: data = 8'b00000000; // 
-         11'h0fe: data = 8'b00000000; // 
-         11'h0ff: data = 8'b00000000; // 
-         //code x10
-         11'h100: data = 8'b00000000; // 
-         11'h101: data = 8'b10000000; // *
-         11'h102: data = 8'b11000000; // **
-         11'h103: data = 8'b11100000; // ***
-         11'h104: data = 8'b11110000; // ****
-         11'h105: data = 8'b11111000; // *****
-         11'h106: data = 8'b11111110; // *******
-         11'h107: data = 8'b11111000; // *****
-         11'h108: data = 8'b11110000; // ****
-         11'h109: data = 8'b11100000; // ***
-         11'h10a: data = 8'b11000000; // **
-         11'h10b: data = 8'b10000000; // *
-         11'h10c: data = 8'b00000000; // 
-         11'h10d: data = 8'b00000000; // 
-         11'h10e: data = 8'b00000000; // 
-         11'h10f: data = 8'b00000000; // 
-         //code x11
-         11'h110: data = 8'b00000000; // 
-         11'h111: data = 8'b00000010; //       *
-         11'h112: data = 8'b00000110; //      **
-         11'h113: data = 8'b00001110; //     ***
-         11'h114: data = 8'b00011110; //    ****
-         11'h115: data = 8'b00111110; //   *****
-         11'h116: data = 8'b11111110; // *******
-         11'h117: data = 8'b00111110; //   *****
-         11'h118: data = 8'b00011110; //    ****
-         11'h119: data = 8'b00001110; //     ***
-         11'h11a: data = 8'b00000110; //      **
-         11'h11b: data = 8'b00000010; //       *
-         11'h11c: data = 8'b00000000; // 
-         11'h11d: data = 8'b00000000; // 
-         11'h11e: data = 8'b00000000; // 
-         11'h11f: data = 8'b00000000; // 
-         //code x12
-         11'h120: data = 8'b00000000; // 
-         11'h121: data = 8'b00000000; // 
-         11'h122: data = 8'b00011000; //    **
-         11'h123: data = 8'b00111100; //   ****
-         11'h124: data = 8'b01111110; //  ******
-         11'h125: data = 8'b00011000; //    **
-         11'h126: data = 8'b00011000; //    **
-         11'h127: data = 8'b00011000; //    **
-         11'h128: data = 8'b01111110; //  ******
-         11'h129: data = 8'b00111100; //   ****
-         11'h12a: data = 8'b00011000; //    **
-         11'h12b: data = 8'b00000000; // 
-         11'h12c: data = 8'b00000000; // 
-         11'h12d: data = 8'b00000000; // 
-         11'h12e: data = 8'b00000000; // 
-         11'h12f: data = 8'b00000000; // 
-         //code x13
-         11'h130: data = 8'b00000000; // 
-         11'h131: data = 8'b00000000; // 
-         11'h132: data = 8'b01100110; //  **  **
-         11'h133: data = 8'b01100110; //  **  **
-         11'h134: data = 8'b01100110; //  **  **
-         11'h135: data = 8'b01100110; //  **  **
-         11'h136: data = 8'b01100110; //  **  **
-         11'h137: data = 8'b01100110; //  **  **
-         11'h138: data = 8'b01100110; //  **  **
-         11'h139: data = 8'b00000000; // 
-         11'h13a: data = 8'b01100110; //  **  **
-         11'h13b: data = 8'b01100110; //  **  **
-         11'h13c: data = 8'b00000000; // 
-         11'h13d: data = 8'b00000000; // 
-         11'h13e: data = 8'b00000000; // 
-         11'h13f: data = 8'b00000000; // 
-         //code x14
-         11'h140: data = 8'b00000000; // 
-         11'h141: data = 8'b00000000; // 
-         11'h142: data = 8'b01111111; //  *******
-         11'h143: data = 8'b11011011; // ** ** **
-         11'h144: data = 8'b11011011; // ** ** **
-         11'h145: data = 8'b11011011; // ** ** **
-         11'h146: data = 8'b01111011; //  **** **
-         11'h147: data = 8'b00011011; //    ** **
-         11'h148: data = 8'b00011011; //    ** **
-         11'h149: data = 8'b00011011; //    ** **
-         11'h14a: data = 8'b00011011; //    ** **
-         11'h14b: data = 8'b00011011; //    ** **
-         11'h14c: data = 8'b00000000; // 
-         11'h14d: data = 8'b00000000; // 
-         11'h14e: data = 8'b00000000; // 
-         11'h14f: data = 8'b00000000; // 
-         //code x15
-         11'h150: data = 8'b00000000; // 
-         11'h151: data = 8'b01111100; //  *****
-         11'h152: data = 8'b11000110; // **   **
-         11'h153: data = 8'b01100000; //  **
-         11'h154: data = 8'b00111000; //   ***
-         11'h155: data = 8'b01101100; //  ** **
-         11'h156: data = 8'b11000110; // **   **
-         11'h157: data = 8'b11000110; // **   **
-         11'h158: data = 8'b01101100; //  ** **
-         11'h159: data = 8'b00111000; //   ***
-         11'h15a: data = 8'b00001100; //     **
-         11'h15b: data = 8'b11000110; // **   **
-         11'h15c: data = 8'b01111100; //  *****
-         11'h15d: data = 8'b00000000; // 
-         11'h15e: data = 8'b00000000; // 
-         11'h15f: data = 8'b00000000; // 
-         //code x16
-         11'h160: data = 8'b00000000; // 
-         11'h161: data = 8'b00000000; // 
-         11'h162: data = 8'b00000000; // 
-         11'h163: data = 8'b00000000; // 
-         11'h164: data = 8'b00000000; // 
-         11'h165: data = 8'b00000000; // 
-         11'h166: data = 8'b00000000; // 
-         11'h167: data = 8'b00000000; // 
-         11'h168: data = 8'b11111110; // *******
-         11'h169: data = 8'b11111110; // *******
-         11'h16a: data = 8'b11111110; // *******
-         11'h16b: data = 8'b11111110; // *******
-         11'h16c: data = 8'b00000000; // 
-         11'h16d: data = 8'b00000000; // 
-         11'h16e: data = 8'b00000000; // 
-         11'h16f: data = 8'b00000000; // 
-         //code x17
-         11'h170: data = 8'b00000000; // 
-         11'h171: data = 8'b00000000; // 
-         11'h172: data = 8'b00011000; //    **
-         11'h173: data = 8'b00111100; //   ****
-         11'h174: data = 8'b01111110; //  ******
-         11'h175: data = 8'b00011000; //    **
-         11'h176: data = 8'b00011000; //    **
-         11'h177: data = 8'b00011000; //    **
-         11'h178: data = 8'b01111110; //  ******
-         11'h179: data = 8'b00111100; //   ****
-         11'h17a: data = 8'b00011000; //    **
-         11'h17b: data = 8'b01111110; //  ******
-         11'h17c: data = 8'b00110000; // 
-         11'h17d: data = 8'b00000000; // 
-         11'h17e: data = 8'b00000000; // 
-         11'h17f: data = 8'b00000000; // 
-         //code x18
-         11'h180: data = 8'b00000000; // 
-         11'h181: data = 8'b00000000; // 
-         11'h182: data = 8'b00011000; //    **
-         11'h183: data = 8'b00111100; //   ****
-         11'h184: data = 8'b01111110; //  ******
-         11'h185: data = 8'b00011000; //    **
-         11'h186: data = 8'b00011000; //    **
-         11'h187: data = 8'b00011000; //    **
-         11'h188: data = 8'b00011000; //    **
-         11'h189: data = 8'b00011000; //    **
-         11'h18a: data = 8'b00011000; //    **
-         11'h18b: data = 8'b00011000; //    **
-         11'h18c: data = 8'b00000000; // 
-         11'h18d: data = 8'b00000000; // 
-         11'h18e: data = 8'b00000000; // 
-         11'h18f: data = 8'b00000000; // 
-         //code x19
-         11'h190: data = 8'b00000000; // 
-         11'h191: data = 8'b00000000; // 
-         11'h192: data = 8'b00011000; //    **
-         11'h193: data = 8'b00011000; //    **
-         11'h194: data = 8'b00011000; //    **
-         11'h195: data = 8'b00011000; //    **
-         11'h196: data = 8'b00011000; //    **
-         11'h197: data = 8'b00011000; //    **
-         11'h198: data = 8'b00011000; //    **
-         11'h199: data = 8'b01111110; //  ******
-         11'h19a: data = 8'b00111100; //   ****
-         11'h19b: data = 8'b00011000; //    **
-         11'h19c: data = 8'b00000000; // 
-         11'h19d: data = 8'b00000000; // 
-         11'h19e: data = 8'b00000000; // 
-         11'h19f: data = 8'b00000000; // 
-         //code x1a
-         11'h1a0: data = 8'b00000000; // 
-         11'h1a1: data = 8'b00000000; // 
-         11'h1a2: data = 8'b00000000; // 
-         11'h1a3: data = 8'b00000000; // 
-         11'h1a4: data = 8'b00000000; // 
-         11'h1a5: data = 8'b00011000; //    **
-         11'h1a6: data = 8'b00001100; //     **
-         11'h1a7: data = 8'b11111110; // *******
-         11'h1a8: data = 8'b00001100; //     **
-         11'h1a9: data = 8'b00011000; //    **
-         11'h1aa: data = 8'b00000000; // 
-         11'h1ab: data = 8'b00000000; // 
-         11'h1ac: data = 8'b00000000; // 
-         11'h1ad: data = 8'b00000000; // 
-         11'h1ae: data = 8'b00000000; // 
-         11'h1af: data = 8'b00000000; // 
-         //code x1b
-         11'h1b0: data = 8'b00000000; // 
-         11'h1b1: data = 8'b00000000; // 
-         11'h1b2: data = 8'b00000000; // 
-         11'h1b3: data = 8'b00000000; // 
-         11'h1b4: data = 8'b00000000; // 
-         11'h1b5: data = 8'b00110000; //   **
-         11'h1b6: data = 8'b01100000; //  **
-         11'h1b7: data = 8'b11111110; // *******
-         11'h1b8: data = 8'b01100000; //  **
-         11'h1b9: data = 8'b00110000; //   **
-         11'h1ba: data = 8'b00000000; // 
-         11'h1bb: data = 8'b00000000; // 
-         11'h1bc: data = 8'b00000000; // 
-         11'h1bd: data = 8'b00000000; // 
-         11'h1be: data = 8'b00000000; // 
-         11'h1bf: data = 8'b00000000; // 
-         //code x1c
-         11'h1c0: data = 8'b00000000; // 
-         11'h1c1: data = 8'b00000000; // 
-         11'h1c2: data = 8'b00000000; // 
-         11'h1c3: data = 8'b00000000; // 
-         11'h1c4: data = 8'b00000000; // 
-         11'h1c5: data = 8'b00000000; // 
-         11'h1c6: data = 8'b11000000; // **
-         11'h1c7: data = 8'b11000000; // **
-         11'h1c8: data = 8'b11000000; // **
-         11'h1c9: data = 8'b11111110; // *******
-         11'h1ca: data = 8'b00000000; // 
-         11'h1cb: data = 8'b00000000; // 
-         11'h1cc: data = 8'b00000000; // 
-         11'h1cd: data = 8'b00000000; // 
-         11'h1ce: data = 8'b00000000; // 
-         11'h1cf: data = 8'b00000000; // 
-         //code x1d
-         11'h1d0: data = 8'b00000000; // 
-         11'h1d1: data = 8'b00000000; // 
-         11'h1d2: data = 8'b00000000; // 
-         11'h1d3: data = 8'b00000000; // 
-         11'h1d4: data = 8'b00000000; // 
-         11'h1d5: data = 8'b00100100; //   *  *
-         11'h1d6: data = 8'b01100110; //  **  **
-         11'h1d7: data = 8'b11111111; // ********
-         11'h1d8: data = 8'b01100110; //  **  **
-         11'h1d9: data = 8'b00100100; //   *  *
-         11'h1da: data = 8'b00000000; // 
-         11'h1db: data = 8'b00000000; // 
-         11'h1dc: data = 8'b00000000; // 
-         11'h1dd: data = 8'b00000000; // 
-         11'h1de: data = 8'b00000000; // 
-         11'h1df: data = 8'b00000000; // 
-         //code x1e
-         11'h1e0: data = 8'b00000000; // 
-         11'h1e1: data = 8'b00000000; // 
-         11'h1e2: data = 8'b00000000; // 
-         11'h1e3: data = 8'b00000000; // 
-         11'h1e4: data = 8'b00010000; //    *
-         11'h1e5: data = 8'b00111000; //   ***
-         11'h1e6: data = 8'b00111000; //   ***
-         11'h1e7: data = 8'b01111100; //  *****
-         11'h1e8: data = 8'b01111100; //  *****
-         11'h1e9: data = 8'b11111110; // *******
-         11'h1ea: data = 8'b11111110; // *******
-         11'h1eb: data = 8'b00000000; // 
-         11'h1ec: data = 8'b00000000; // 
-         11'h1ed: data = 8'b00000000; // 
-         11'h1ee: data = 8'b00000000; // 
-         11'h1ef: data = 8'b00000000; // 
-         //code x1f
-         11'h1f0: data = 8'b00000000; // 
-         11'h1f1: data = 8'b00000000; // 
-         11'h1f2: data = 8'b00000000; // 
-         11'h1f3: data = 8'b00000000; // 
-         11'h1f4: data = 8'b11111110; // *******
-         11'h1f5: data = 8'b11111110; // *******
-         11'h1f6: data = 8'b01111100; //  *****
-         11'h1f7: data = 8'b01111100; //  *****
-         11'h1f8: data = 8'b00111000; //   ***
-         11'h1f9: data = 8'b00111000; //   ***
-         11'h1fa: data = 8'b00010000; //    *
-         11'h1fb: data = 8'b00000000; // 
-         11'h1fc: data = 8'b00000000; // 
-         11'h1fd: data = 8'b00000000; // 
-         11'h1fe: data = 8'b00000000; // 
-         11'h1ff: data = 8'b00000000; // 
-         //code x20
-         11'h200: data = 8'b00000000; // 
-         11'h201: data = 8'b00000000; // 
-         11'h202: data = 8'b00000000; // 
-         11'h203: data = 8'b00000000; // 
-         11'h204: data = 8'b00000000; // 
-         11'h205: data = 8'b00000000; // 
-         11'h206: data = 8'b00000000; // 
-         11'h207: data = 8'b00000000; // 
-         11'h208: data = 8'b00000000; // 
-         11'h209: data = 8'b00000000; // 
-         11'h20a: data = 8'b00000000; // 
-         11'h20b: data = 8'b00000000; // 
-         11'h20c: data = 8'b00000000; // 
-         11'h20d: data = 8'b00000000; // 
-         11'h20e: data = 8'b00000000; // 
-         11'h20f: data = 8'b00000000; // 
-         //code x21
-         11'h210: data = 8'b00000000; // 
-         11'h211: data = 8'b00000000; // 
-         11'h212: data = 8'b00011000; //    **
-         11'h213: data = 8'b00111100; //   ****
-         11'h214: data = 8'b00111100; //   ****
-         11'h215: data = 8'b00111100; //   ****
-         11'h216: data = 8'b00011000; //    **
-         11'h217: data = 8'b00011000; //    **
-         11'h218: data = 8'b00011000; //    **
-         11'h219: data = 8'b00000000; // 
-         11'h21a: data = 8'b00011000; //    **
-         11'h21b: data = 8'b00011000; //    **
-         11'h21c: data = 8'b00000000; // 
-         11'h21d: data = 8'b00000000; // 
-         11'h21e: data = 8'b00000000; // 
-         11'h21f: data = 8'b00000000; // 
-         //code x22
-         11'h220: data = 8'b00000000; // 
-         11'h221: data = 8'b01100110; //  **  **
-         11'h222: data = 8'b01100110; //  **  **
-         11'h223: data = 8'b01100110; //  **  **
-         11'h224: data = 8'b00100100; //   *  *
-         11'h225: data = 8'b00000000; // 
-         11'h226: data = 8'b00000000; // 
-         11'h227: data = 8'b00000000; // 
-         11'h228: data = 8'b00000000; // 
-         11'h229: data = 8'b00000000; // 
-         11'h22a: data = 8'b00000000; // 
-         11'h22b: data = 8'b00000000; // 
-         11'h22c: data = 8'b00000000; // 
-         11'h22d: data = 8'b00000000; // 
-         11'h22e: data = 8'b00000000; // 
-         11'h22f: data = 8'b00000000; // 
-         //code x23
-         11'h230: data = 8'b00000000; // 
-         11'h231: data = 8'b00000000; // 
-         11'h232: data = 8'b00000000; // 
-         11'h233: data = 8'b01101100; //  ** **
-         11'h234: data = 8'b01101100; //  ** **
-         11'h235: data = 8'b11111110; // *******
-         11'h236: data = 8'b01101100; //  ** **
-         11'h237: data = 8'b01101100; //  ** **
-         11'h238: data = 8'b01101100; //  ** **
-         11'h239: data = 8'b11111110; // *******
-         11'h23a: data = 8'b01101100; //  ** **
-         11'h23b: data = 8'b01101100; //  ** **
-         11'h23c: data = 8'b00000000; // 
-         11'h23d: data = 8'b00000000; // 
-         11'h23e: data = 8'b00000000; // 
-         11'h23f: data = 8'b00000000; // 
-         //code x24
-         11'h240: data = 8'b00011000; //     **
-         11'h241: data = 8'b00011000; //     **
-         11'h242: data = 8'b01111100; //   *****
-         11'h243: data = 8'b11000110; //  **   **
-         11'h244: data = 8'b11000010; //  **    *
-         11'h245: data = 8'b11000000; //  **
-         11'h246: data = 8'b01111100; //   *****
-         11'h247: data = 8'b00000110; //       **
-         11'h248: data = 8'b00000110; //       **
-         11'h249: data = 8'b10000110; //  *    **
-         11'h24a: data = 8'b11000110; //  **   **
-         11'h24b: data = 8'b01111100; //   *****
-         11'h24c: data = 8'b00011000; //     **
-         11'h24d: data = 8'b00011000; //     **
-         11'h24e: data = 8'b00000000; // 
-         11'h24f: data = 8'b00000000; // 
-         //code x25
-         11'h250: data = 8'b00000000; // 
-         11'h251: data = 8'b00000000; // 
-         11'h252: data = 8'b00000000; // 
-         11'h253: data = 8'b00000000; // 
-         11'h254: data = 8'b11000010; // **    *
-         11'h255: data = 8'b11000110; // **   **
-         11'h256: data = 8'b00001100; //     **
-         11'h257: data = 8'b00011000; //    **
-         11'h258: data = 8'b00110000; //   **
-         11'h259: data = 8'b01100000; //  **
-         11'h25a: data = 8'b11000110; // **   **
-         11'h25b: data = 8'b10000110; // *    **
-         11'h25c: data = 8'b00000000; // 
-         11'h25d: data = 8'b00000000; // 
-         11'h25e: data = 8'b00000000; // 
-         11'h25f: data = 8'b00000000; // 
-         //code x26
-         11'h260: data = 8'b00000000; // 
-         11'h261: data = 8'b00000000; // 
-         11'h262: data = 8'b00111000; //   ***
-         11'h263: data = 8'b01101100; //  ** **
-         11'h264: data = 8'b01101100; //  ** **
-         11'h265: data = 8'b00111000; //   ***
-         11'h266: data = 8'b01110110; //  *** **
-         11'h267: data = 8'b11011100; // ** ***
-         11'h268: data = 8'b11001100; // **  **
-         11'h269: data = 8'b11001100; // **  **
-         11'h26a: data = 8'b11001100; // **  **
-         11'h26b: data = 8'b01110110; //  *** **
-         11'h26c: data = 8'b00000000; // 
-         11'h26d: data = 8'b00000000; // 
-         11'h26e: data = 8'b00000000; // 
-         11'h26f: data = 8'b00000000; // 
-         //code x27
-         11'h270: data = 8'b00000000; // 
-         11'h271: data = 8'b00110000; //   **
-         11'h272: data = 8'b00110000; //   **
-         11'h273: data = 8'b00110000; //   **
-         11'h274: data = 8'b01100000; //  **
-         11'h275: data = 8'b00000000; // 
-         11'h276: data = 8'b00000000; // 
-         11'h277: data = 8'b00000000; // 
-         11'h278: data = 8'b00000000; // 
-         11'h279: data = 8'b00000000; // 
-         11'h27a: data = 8'b00000000; // 
-         11'h27b: data = 8'b00000000; // 
-         11'h27c: data = 8'b00000000; // 
-         11'h27d: data = 8'b00000000; // 
-         11'h27e: data = 8'b00000000; // 
-         11'h27f: data = 8'b00000000; // 
-         //code x28
-         11'h280: data = 8'b00000000; // 
-         11'h281: data = 8'b00000000; // 
-         11'h282: data = 8'b00001100; //     **
-         11'h283: data = 8'b00011000; //    **
-         11'h284: data = 8'b00110000; //   **
-         11'h285: data = 8'b00110000; //   **
-         11'h286: data = 8'b00110000; //   **
-         11'h287: data = 8'b00110000; //   **
-         11'h288: data = 8'b00110000; //   **
-         11'h289: data = 8'b00110000; //   **
-         11'h28a: data = 8'b00011000; //    **
-         11'h28b: data = 8'b00001100; //     **
-         11'h28c: data = 8'b00000000; // 
-         11'h28d: data = 8'b00000000; // 
-         11'h28e: data = 8'b00000000; // 
-         11'h28f: data = 8'b00000000; // 
-         //code x29
-         11'h290: data = 8'b00000000; // 
-         11'h291: data = 8'b00000000; // 
-         11'h292: data = 8'b00110000; //   **
-         11'h293: data = 8'b00011000; //    **
-         11'h294: data = 8'b00001100; //     **
-         11'h295: data = 8'b00001100; //     **
-         11'h296: data = 8'b00001100; //     **
-         11'h297: data = 8'b00001100; //     **
-         11'h298: data = 8'b00001100; //     **
-         11'h299: data = 8'b00001100; //     **
-         11'h29a: data = 8'b00011000; //    **
-         11'h29b: data = 8'b00110000; //   **
-         11'h29c: data = 8'b00000000; // 
-         11'h29d: data = 8'b00000000; // 
-         11'h29e: data = 8'b00000000; // 
-         11'h29f: data = 8'b00000000; // 
-         //code x2a
-         11'h2a0: data = 8'b00000000; // 
-         11'h2a1: data = 8'b00000000; // 
-         11'h2a2: data = 8'b00000000; // 
-         11'h2a3: data = 8'b00000000; // 
-         11'h2a4: data = 8'b00000000; // 
-         11'h2a5: data = 8'b01100110; //  **  **
-         11'h2a6: data = 8'b00111100; //   ****
-         11'h2a7: data = 8'b11111111; // ********
-         11'h2a8: data = 8'b00111100; //   ****
-         11'h2a9: data = 8'b01100110; //  **  **
-         11'h2aa: data = 8'b00000000; // 
-         11'h2ab: data = 8'b00000000; // 
-         11'h2ac: data = 8'b00000000; // 
-         11'h2ad: data = 8'b00000000; // 
-         11'h2ae: data = 8'b00000000; // 
-         11'h2af: data = 8'b00000000; // 
-         //code x2b
-         11'h2b0: data = 8'b00000000; // 
-         11'h2b1: data = 8'b00000000; // 
-         11'h2b2: data = 8'b00000000; // 
-         11'h2b3: data = 8'b00000000; // 
-         11'h2b4: data = 8'b00000000; // 
-         11'h2b5: data = 8'b00011000; //    **
-         11'h2b6: data = 8'b00011000; //    **
-         11'h2b7: data = 8'b01111110; //  ******
-         11'h2b8: data = 8'b00011000; //    **
-         11'h2b9: data = 8'b00011000; //    **
-         11'h2ba: data = 8'b00000000; // 
-         11'h2bb: data = 8'b00000000; // 
-         11'h2bc: data = 8'b00000000; // 
-         11'h2bd: data = 8'b00000000; // 
-         11'h2be: data = 8'b00000000; // 
-         11'h2bf: data = 8'b00000000; // 
-         //code x2c
-         11'h2c0: data = 8'b00000000; // 
-         11'h2c1: data = 8'b00000000; // 
-         11'h2c2: data = 8'b00000000; // 
-         11'h2c3: data = 8'b00000000; // 
-         11'h2c4: data = 8'b00000000; // 
-         11'h2c5: data = 8'b00000000; // 
-         11'h2c6: data = 8'b00000000; // 
-         11'h2c7: data = 8'b00000000; // 
-         11'h2c8: data = 8'b00000000; // 
-         11'h2c9: data = 8'b00011000; //    **
-         11'h2ca: data = 8'b00011000; //    **
-         11'h2cb: data = 8'b00011000; //    **
-         11'h2cc: data = 8'b00110000; //   **
-         11'h2cd: data = 8'b00000000; // 
-         11'h2ce: data = 8'b00000000; // 
-         11'h2cf: data = 8'b00000000; // 
-         //code x2d
-         11'h2d0: data = 8'b00000000; // 
-         11'h2d1: data = 8'b00000000; // 
-         11'h2d2: data = 8'b00000000; // 
-         11'h2d3: data = 8'b00000000; // 
-         11'h2d4: data = 8'b00000000; // 
-         11'h2d5: data = 8'b00000000; // 
-         11'h2d6: data = 8'b00000000; // 
-         11'h2d7: data = 8'b01111110; //  ******
-         11'h2d8: data = 8'b00000000; // 
-         11'h2d9: data = 8'b00000000; // 
-         11'h2da: data = 8'b00000000; // 
-         11'h2db: data = 8'b00000000; // 
-         11'h2dc: data = 8'b00000000; // 
-         11'h2dd: data = 8'b00000000; // 
-         11'h2de: data = 8'b00000000; // 
-         11'h2df: data = 8'b00000000; // 
-         //code x2e
-         11'h2e0: data = 8'b00000000; // 
-         11'h2e1: data = 8'b00000000; // 
-         11'h2e2: data = 8'b00000000; // 
-         11'h2e3: data = 8'b00000000; // 
-         11'h2e4: data = 8'b00000000; // 
-         11'h2e5: data = 8'b00000000; // 
-         11'h2e6: data = 8'b00000000; // 
-         11'h2e7: data = 8'b00000000; // 
-         11'h2e8: data = 8'b00000000; // 
-         11'h2e9: data = 8'b00000000; // 
-         11'h2ea: data = 8'b00011000; //    **
-         11'h2eb: data = 8'b00011000; //    **
-         11'h2ec: data = 8'b00000000; // 
-         11'h2ed: data = 8'b00000000; // 
-         11'h2ee: data = 8'b00000000; // 
-         11'h2ef: data = 8'b00000000; // 
-         //code x2f
-         11'h2f0: data = 8'b00000000; // 
-         11'h2f1: data = 8'b00000000; // 
-         11'h2f2: data = 8'b00000000; // 
-         11'h2f3: data = 8'b00000000; // 
-         11'h2f4: data = 8'b00000010; //       *
-         11'h2f5: data = 8'b00000110; //      **
-         11'h2f6: data = 8'b00001100; //     **
-         11'h2f7: data = 8'b00011000; //    **
-         11'h2f8: data = 8'b00110000; //   **
-         11'h2f9: data = 8'b01100000; //  **
-         11'h2fa: data = 8'b11000000; // **
-         11'h2fb: data = 8'b10000000; // *
-         11'h2fc: data = 8'b00000000; // 
-         11'h2fd: data = 8'b00000000; // 
-         11'h2fe: data = 8'b00000000; // 
-         11'h2ff: data = 8'b00000000; // 
-         //code x30
-         11'h300: data = 8'b00000000; // 
-         11'h301: data = 8'b00000000; // 
-         11'h302: data = 8'b01111100; //  *****
-         11'h303: data = 8'b11000110; // **   **
-         11'h304: data = 8'b11000110; // **   **
-         11'h305: data = 8'b11001110; // **  ***
-         11'h306: data = 8'b11011110; // ** ****
-         11'h307: data = 8'b11110110; // **** **
-         11'h308: data = 8'b11100110; // ***  **
-         11'h309: data = 8'b11000110; // **   **
-         11'h30a: data = 8'b11000110; // **   **
-         11'h30b: data = 8'b01111100; //  *****
-         11'h30c: data = 8'b00000000; // 
-         11'h30d: data = 8'b00000000; // 
-         11'h30e: data = 8'b00000000; // 
-         11'h30f: data = 8'b00000000; // 
-         //code x31
-         11'h310: data = 8'b00000000; // 
-         11'h311: data = 8'b00000000; // 
-         11'h312: data = 8'b00011000; // 
-         11'h313: data = 8'b00111000; // 
-         11'h314: data = 8'b01111000; //    **
-         11'h315: data = 8'b00011000; //   ***
-         11'h316: data = 8'b00011000; //  ****
-         11'h317: data = 8'b00011000; //    **
-         11'h318: data = 8'b00011000; //    **
-         11'h319: data = 8'b00011000; //    **
-         11'h31a: data = 8'b00011000; //    **
-         11'h31b: data = 8'b01111110; //    **
-         11'h31c: data = 8'b00000000; //    **
-         11'h31d: data = 8'b00000000; //  ******
-         11'h31e: data = 8'b00000000; // 
-         11'h31f: data = 8'b00000000; // 
-         //code x32
-         11'h320: data = 8'b00000000; // 
-         11'h321: data = 8'b00000000; // 
-         11'h322: data = 8'b01111100; //  *****
-         11'h323: data = 8'b11000110; // **   **
-         11'h324: data = 8'b00000110; //      **
-         11'h325: data = 8'b00001100; //     **
-         11'h326: data = 8'b00011000; //    **
-         11'h327: data = 8'b00110000; //   **
-         11'h328: data = 8'b01100000; //  **
-         11'h329: data = 8'b11000000; // **
-         11'h32a: data = 8'b11000110; // **   **
-         11'h32b: data = 8'b11111110; // *******
-         11'h32c: data = 8'b00000000; // 
-         11'h32d: data = 8'b00000000; // 
-         11'h32e: data = 8'b00000000; // 
-         11'h32f: data = 8'b00000000; // 
-         //code x33
-         11'h330: data = 8'b00000000; // 
-         11'h331: data = 8'b00000000; // 
-         11'h332: data = 8'b01111100; //  *****
-         11'h333: data = 8'b11000110; // **   **
-         11'h334: data = 8'b00000110; //      **
-         11'h335: data = 8'b00000110; //      **
-         11'h336: data = 8'b00111100; //   ****
-         11'h337: data = 8'b00000110; //      **
-         11'h338: data = 8'b00000110; //      **
-         11'h339: data = 8'b00000110; //      **
-         11'h33a: data = 8'b11000110; // **   **
-         11'h33b: data = 8'b01111100; //  *****
-         11'h33c: data = 8'b00000000; // 
-         11'h33d: data = 8'b00000000; // 
-         11'h33e: data = 8'b00000000; // 
-         11'h33f: data = 8'b00000000; // 
-         //code x34
-         11'h340: data = 8'b00000000; // 
-         11'h341: data = 8'b00000000; // 
-         11'h342: data = 8'b00001100; //     **
-         11'h343: data = 8'b00011100; //    ***
-         11'h344: data = 8'b00111100; //   ****
-         11'h345: data = 8'b01101100; //  ** **
-         11'h346: data = 8'b11001100; // **  **
-         11'h347: data = 8'b11111110; // *******
-         11'h348: data = 8'b00001100; //     **
-         11'h349: data = 8'b00001100; //     **
-         11'h34a: data = 8'b00001100; //     **
-         11'h34b: data = 8'b00011110; //    ****
-         11'h34c: data = 8'b00000000; // 
-         11'h34d: data = 8'b00000000; // 
-         11'h34e: data = 8'b00000000; // 
-         11'h34f: data = 8'b00000000; // 
-         //code x35
-         11'h350: data = 8'b00000000; // 
-         11'h351: data = 8'b00000000; // 
-         11'h352: data = 8'b11111110; // *******
-         11'h353: data = 8'b11000000; // **
-         11'h354: data = 8'b11000000; // **
-         11'h355: data = 8'b11000000; // **
-         11'h356: data = 8'b11111100; // ******
-         11'h357: data = 8'b00000110; //      **
-         11'h358: data = 8'b00000110; //      **
-         11'h359: data = 8'b00000110; //      **
-         11'h35a: data = 8'b11000110; // **   **
-         11'h35b: data = 8'b01111100; //  *****
-         11'h35c: data = 8'b00000000; // 
-         11'h35d: data = 8'b00000000; // 
-         11'h35e: data = 8'b00000000; // 
-         11'h35f: data = 8'b00000000; // 
-         //code x36
-         11'h360: data = 8'b00000000; // 
-         11'h361: data = 8'b00000000; // 
-         11'h362: data = 8'b00111000; //   ***
-         11'h363: data = 8'b01100000; //  **
-         11'h364: data = 8'b11000000; // **
-         11'h365: data = 8'b11000000; // **
-         11'h366: data = 8'b11111100; // ******
-         11'h367: data = 8'b11000110; // **   **
-         11'h368: data = 8'b11000110; // **   **
-         11'h369: data = 8'b11000110; // **   **
-         11'h36a: data = 8'b11000110; // **   **
-         11'h36b: data = 8'b01111100; //  *****
-         11'h36c: data = 8'b00000000; // 
-         11'h36d: data = 8'b00000000; // 
-         11'h36e: data = 8'b00000000; // 
-         11'h36f: data = 8'b00000000; // 
-         //code x37
-         11'h370: data = 8'b00000000; // 
-         11'h371: data = 8'b00000000; // 
-         11'h372: data = 8'b11111110; // *******
-         11'h373: data = 8'b11000110; // **   **
-         11'h374: data = 8'b00000110; //      **
-         11'h375: data = 8'b00000110; //      **
-         11'h376: data = 8'b00001100; //     **
-         11'h377: data = 8'b00011000; //    **
-         11'h378: data = 8'b00110000; //   **
-         11'h379: data = 8'b00110000; //   **
-         11'h37a: data = 8'b00110000; //   **
-         11'h37b: data = 8'b00110000; //   **
-         11'h37c: data = 8'b00000000; // 
-         11'h37d: data = 8'b00000000; // 
-         11'h37e: data = 8'b00000000; // 
-         11'h37f: data = 8'b00000000; // 
-         //code x38
-         11'h380: data = 8'b00000000; // 
-         11'h381: data = 8'b00000000; // 
-         11'h382: data = 8'b01111100; //  *****
-         11'h383: data = 8'b11000110; // **   **
-         11'h384: data = 8'b11000110; // **   **
-         11'h385: data = 8'b11000110; // **   **
-         11'h386: data = 8'b01111100; //  *****
-         11'h387: data = 8'b11000110; // **   **
-         11'h388: data = 8'b11000110; // **   **
-         11'h389: data = 8'b11000110; // **   **
-         11'h38a: data = 8'b11000110; // **   **
-         11'h38b: data = 8'b01111100; //  *****
-         11'h38c: data = 8'b00000000; // 
-         11'h38d: data = 8'b00000000; // 
-         11'h38e: data = 8'b00000000; // 
-         11'h38f: data = 8'b00000000; // 
-         //code x39
-         11'h390: data = 8'b00000000; // 
-         11'h391: data = 8'b00000000; // 
-         11'h392: data = 8'b01111100; //  *****
-         11'h393: data = 8'b11000110; // **   **
-         11'h394: data = 8'b11000110; // **   **
-         11'h395: data = 8'b11000110; // **   **
-         11'h396: data = 8'b01111110; //  ******
-         11'h397: data = 8'b00000110; //      **
-         11'h398: data = 8'b00000110; //      **
-         11'h399: data = 8'b00000110; //      **
-         11'h39a: data = 8'b00001100; //     **
-         11'h39b: data = 8'b01111000; //  ****
-         11'h39c: data = 8'b00000000; // 
-         11'h39d: data = 8'b00000000; // 
-         11'h39e: data = 8'b00000000; // 
-         11'h39f: data = 8'b00000000; // 
-         //code x3a 
-         11'h3a0: data = 8'b00000000; // 
-         11'h3a1: data = 8'b00000000; // 
-         11'h3a2: data = 8'b00000000; // 
-         11'h3a3: data = 8'b00000000; // 
-         11'h3a4: data = 8'b00011000; //    **
-         11'h3a5: data = 8'b00011000; //    **
-         11'h3a6: data = 8'b00000000; // 
-         11'h3a7: data = 8'b00000000; // 
-         11'h3a8: data = 8'b00000000; // 
-         11'h3a9: data = 8'b00011000; //    **
-         11'h3aa: data = 8'b00011000; //    **
-         11'h3ab: data = 8'b00000000; // 
-         11'h3ac: data = 8'b00000000; // 
-         11'h3ad: data = 8'b00000000; // 
-         11'h3ae: data = 8'b00000000; // 
-         11'h3af: data = 8'b00000000; // 
-         //code x3b 
-         11'h3b0: data = 8'b00000000; // 
-         11'h3b1: data = 8'b00000000; // 
-         11'h3b2: data = 8'b00000000; // 
-         11'h3b3: data = 8'b00000000; // 
-         11'h3b4: data = 8'b00011000; //    **
-         11'h3b5: data = 8'b00011000; //    **
-         11'h3b6: data = 8'b00000000; // 
-         11'h3b7: data = 8'b00000000; // 
-         11'h3b8: data = 8'b00000000; // 
-         11'h3b9: data = 8'b00011000; //    **
-         11'h3ba: data = 8'b00011000; //    **
-         11'h3bb: data = 8'b00110000; //   **
-         11'h3bc: data = 8'b00000000; // 
-         11'h3bd: data = 8'b00000000; // 
-         11'h3be: data = 8'b00000000; // 
-         11'h3bf: data = 8'b00000000; // 
-         //code x3c 
-         11'h3c0: data = 8'b00000000; // 
-         11'h3c1: data = 8'b00000000; // 
-         11'h3c2: data = 8'b00000000; // 
-         11'h3c3: data = 8'b00000110; //      **
-         11'h3c4: data = 8'b00001100; //     **
-         11'h3c5: data = 8'b00011000; //    **
-         11'h3c6: data = 8'b00110000; //   **
-         11'h3c7: data = 8'b01100000; //  **
-         11'h3c8: data = 8'b00110000; //   **
-         11'h3c9: data = 8'b00011000; //    **
-         11'h3ca: data = 8'b00001100; //     **
-         11'h3cb: data = 8'b00000110; //      **
-         11'h3cc: data = 8'b00000000; // 
-         11'h3cd: data = 8'b00000000; // 
-         11'h3ce: data = 8'b00000000; // 
-         11'h3cf: data = 8'b00000000; // 
-         //code x3d 
-         11'h3d0: data = 8'b00000000; // 
-         11'h3d1: data = 8'b00000000; // 
-         11'h3d2: data = 8'b00000000; // 
-         11'h3d3: data = 8'b00000000; // 
-         11'h3d4: data = 8'b00000000; // 
-         11'h3d5: data = 8'b01111110; //  ******
-         11'h3d6: data = 8'b00000000; // 
-         11'h3d7: data = 8'b00000000; // 
-         11'h3d8: data = 8'b01111110; //  ******
-         11'h3d9: data = 8'b00000000; // 
-         11'h3da: data = 8'b00000000; // 
-         11'h3db: data = 8'b00000000; // 
-         11'h3dc: data = 8'b00000000; // 
-         11'h3dd: data = 8'b00000000; // 
-         11'h3de: data = 8'b00000000; // 
-         11'h3df: data = 8'b00000000; // 
-         //code x3e 
-         11'h3e0: data = 8'b00000000; // 
-         11'h3e1: data = 8'b00000000; // 
-         11'h3e2: data = 8'b00000000; // 
-         11'h3e3: data = 8'b01100000; //  **
-         11'h3e4: data = 8'b00110000; //   **
-         11'h3e5: data = 8'b00011000; //    **
-         11'h3e6: data = 8'b00001100; //     **
-         11'h3e7: data = 8'b00000110; //      **
-         11'h3e8: data = 8'b00001100; //     **
-         11'h3e9: data = 8'b00011000; //    **
-         11'h3ea: data = 8'b00110000; //   **
-         11'h3eb: data = 8'b01100000; //  **
-         11'h3ec: data = 8'b00000000; // 
-         11'h3ed: data = 8'b00000000; // 
-         11'h3ee: data = 8'b00000000; // 
-         11'h3ef: data = 8'b00000000; // 
-         //code x3f 
-         11'h3f0: data = 8'b00000000; // 
-         11'h3f1: data = 8'b00000000; // 
-         11'h3f2: data = 8'b01111100; //  *****
-         11'h3f3: data = 8'b11000110; // **   **
-         11'h3f4: data = 8'b11000110; // **   **
-         11'h3f5: data = 8'b00001100; //     **
-         11'h3f6: data = 8'b00011000; //    **
-         11'h3f7: data = 8'b00011000; //    **
-         11'h3f8: data = 8'b00011000; //    **
-         11'h3f9: data = 8'b00000000; // 
-         11'h3fa: data = 8'b00011000; //    **
-         11'h3fb: data = 8'b00011000; //    **
-         11'h3fc: data = 8'b00000000; // 
-         11'h3fd: data = 8'b00000000; // 
-         11'h3fe: data = 8'b00000000; // 
-         11'h3ff: data = 8'b00000000; // 
-        //code x40 
-         11'h400: data = 8'b00000000; // 
-         11'h401: data = 8'b00000000; // 
-         11'h402: data = 8'b01111100; //  *****
-         11'h403: data = 8'b11000110; // **   **
-         11'h404: data = 8'b11000110; // **   **
-         11'h405: data = 8'b11000110; // **   **
-         11'h406: data = 8'b11011110; // ** ****
-         11'h407: data = 8'b11011110; // ** ****
-         11'h408: data = 8'b11011110; // ** ****
-         11'h409: data = 8'b11011100; // ** ***
-         11'h40a: data = 8'b11000000; // **
-         11'h40b: data = 8'b01111100; //  *****
-         11'h40c: data = 8'b00000000; // 
-         11'h40d: data = 8'b00000000; // 
-         11'h40e: data = 8'b00000000; // 
-         11'h40f: data = 8'b00000000; // 
-         //code x41 
-         11'h410: data = 8'b00000000; // 
-         11'h411: data = 8'b00000000; // 
-         11'h412: data = 8'b00010000; //    *
-         11'h413: data = 8'b00111000; //   ***
-         11'h414: data = 8'b01101100; //  ** **
-         11'h415: data = 8'b11000110; // **   **
-         11'h416: data = 8'b11000110; // **   **
-         11'h417: data = 8'b11111110; // *******
-         11'h418: data = 8'b11000110; // **   **
-         11'h419: data = 8'b11000110; // **   **
-         11'h41a: data = 8'b11000110; // **   **
-         11'h41b: data = 8'b11000110; // **   **
-         11'h41c: data = 8'b00000000; // 
-         11'h41d: data = 8'b00000000; // 
-         11'h41e: data = 8'b00000000; // 
-         11'h41f: data = 8'b00000000; // 
-         //code x42 
-         11'h420: data = 8'b00000000; // 
-         11'h421: data = 8'b00000000; // 
-         11'h422: data = 8'b11111100; // ******
-         11'h423: data = 8'b01100110; //  **  **
-         11'h424: data = 8'b01100110; //  **  **
-         11'h425: data = 8'b01100110; //  **  **
-         11'h426: data = 8'b01111100; //  *****
-         11'h427: data = 8'b01100110; //  **  **
-         11'h428: data = 8'b01100110; //  **  **
-         11'h429: data = 8'b01100110; //  **  **
-         11'h42a: data = 8'b01100110; //  **  **
-         11'h42b: data = 8'b11111100; // ******
-         11'h42c: data = 8'b00000000; // 
-         11'h42d: data = 8'b00000000; // 
-         11'h42e: data = 8'b00000000; // 
-         11'h42f: data = 8'b00000000; // 
-         //code x43 
-         11'h430: data = 8'b00000000; // 
-         11'h431: data = 8'b00000000; // 
-         11'h432: data = 8'b00111100; //   ****
-         11'h433: data = 8'b01100110; //  **  **
-         11'h434: data = 8'b11000010; // **    *
-         11'h435: data = 8'b11000000; // **
-         11'h436: data = 8'b11000000; // **
-         11'h437: data = 8'b11000000; // **
-         11'h438: data = 8'b11000000; // **
-         11'h439: data = 8'b11000010; // **    *
-         11'h43a: data = 8'b01100110; //  **  **
-         11'h43b: data = 8'b00111100; //   ****
-         11'h43c: data = 8'b00000000; // 
-         11'h43d: data = 8'b00000000; // 
-         11'h43e: data = 8'b00000000; // 
-         11'h43f: data = 8'b00000000; // 
-         //code x44 
-         11'h440: data = 8'b00000000; // 
-         11'h441: data = 8'b00000000; // 
-         11'h442: data = 8'b11111000; // *****
-         11'h443: data = 8'b01101100; //  ** **
-         11'h444: data = 8'b01100110; //  **  **
-         11'h445: data = 8'b01100110; //  **  **
-         11'h446: data = 8'b01100110; //  **  **
-         11'h447: data = 8'b01100110; //  **  **
-         11'h448: data = 8'b01100110; //  **  **
-         11'h449: data = 8'b01100110; //  **  **
-         11'h44a: data = 8'b01101100; //  ** **
-         11'h44b: data = 8'b11111000; // *****
-         11'h44c: data = 8'b00000000; // 
-         11'h44d: data = 8'b00000000; // 
-         11'h44e: data = 8'b00000000; // 
-         11'h44f: data = 8'b00000000; // 
-         //code x45 
-         11'h450: data = 8'b00000000; // 
-         11'h451: data = 8'b00000000; // 
-         11'h452: data = 8'b11111110; // *******
-         11'h453: data = 8'b01100110; //  **  **
-         11'h454: data = 8'b01100010; //  **   *
-         11'h455: data = 8'b01101000; //  ** *
-         11'h456: data = 8'b01111000; //  ****
-         11'h457: data = 8'b01101000; //  ** *
-         11'h458: data = 8'b01100000; //  **
-         11'h459: data = 8'b01100010; //  **   *
-         11'h45a: data = 8'b01100110; //  **  **
-         11'h45b: data = 8'b11111110; // *******
-         11'h45c: data = 8'b00000000; // 
-         11'h45d: data = 8'b00000000; // 
-         11'h45e: data = 8'b00000000; // 
-         11'h45f: data = 8'b00000000; // 
-         //code x46 
-         11'h460: data = 8'b00000000; // 
-         11'h461: data = 8'b00000000; // 
-         11'h462: data = 8'b11111110; // *******
-         11'h463: data = 8'b01100110; //  **  **
-         11'h464: data = 8'b01100010; //  **   *
-         11'h465: data = 8'b01101000; //  ** *
-         11'h466: data = 8'b01111000; //  ****
-         11'h467: data = 8'b01101000; //  ** *
-         11'h468: data = 8'b01100000; //  **
-         11'h469: data = 8'b01100000; //  **
-         11'h46a: data = 8'b01100000; //  **
-         11'h46b: data = 8'b11110000; // ****
-         11'h46c: data = 8'b00000000; // 
-         11'h46d: data = 8'b00000000; // 
-         11'h46e: data = 8'b00000000; // 
-         11'h46f: data = 8'b00000000; // 
-         //code x47 
-         11'h470: data = 8'b00000000; // 
-         11'h471: data = 8'b00000000; // 
-         11'h472: data = 8'b00111100; //   ****
-         11'h473: data = 8'b01100110; //  **  **
-         11'h474: data = 8'b11000010; // **    *
-         11'h475: data = 8'b11000000; // **
-         11'h476: data = 8'b11000000; // **
-         11'h477: data = 8'b11011110; // ** ****
-         11'h478: data = 8'b11000110; // **   **
-         11'h479: data = 8'b11000110; // **   **
-         11'h47a: data = 8'b01100110; //  **  **
-         11'h47b: data = 8'b00111010; //   *** *
-         11'h47c: data = 8'b00000000; // 
-         11'h47d: data = 8'b00000000; // 
-         11'h47e: data = 8'b00000000; // 
-         11'h47f: data = 8'b00000000; // 
-         //code x48 
-         11'h480: data = 8'b00000000; // 
-         11'h481: data = 8'b00000000; // 
-         11'h482: data = 8'b11000110; // **   **
-         11'h483: data = 8'b11000110; // **   **
-         11'h484: data = 8'b11000110; // **   **
-         11'h485: data = 8'b11000110; // **   **
-         11'h486: data = 8'b11111110; // *******
-         11'h487: data = 8'b11000110; // **   **
-         11'h488: data = 8'b11000110; // **   **
-         11'h489: data = 8'b11000110; // **   **
-         11'h48a: data = 8'b11000110; // **   **
-         11'h48b: data = 8'b11000110; // **   **
-         11'h48c: data = 8'b00000000; // 
-         11'h48d: data = 8'b00000000; // 
-         11'h48e: data = 8'b00000000; // 
-         11'h48f: data = 8'b00000000; // 
-         //code x49 
-         11'h490: data = 8'b00000000; // 
-         11'h491: data = 8'b00000000; // 
-         11'h492: data = 8'b00111100; //   ****
-         11'h493: data = 8'b00011000; //    **
-         11'h494: data = 8'b00011000; //    **
-         11'h495: data = 8'b00011000; //    **
-         11'h496: data = 8'b00011000; //    **
-         11'h497: data = 8'b00011000; //    **
-         11'h498: data = 8'b00011000; //    **
-         11'h499: data = 8'b00011000; //    **
-         11'h49a: data = 8'b00011000; //    **
-         11'h49b: data = 8'b00111100; //   ****
-         11'h49c: data = 8'b00000000; // 
-         11'h49d: data = 8'b00000000; // 
-         11'h49e: data = 8'b00000000; // 
-         11'h49f: data = 8'b00000000; // 
-         //code x4a   
-         11'h4a0: data = 8'b00000000; // 
-         11'h4a1: data = 8'b00000000; // 
-         11'h4a2: data = 8'b00011110; //    ****
-         11'h4a3: data = 8'b00001100; //     **
-         11'h4a4: data = 8'b00001100; //     **
-         11'h4a5: data = 8'b00001100; //     **
-         11'h4a6: data = 8'b00001100; //     **
-         11'h4a7: data = 8'b00001100; //     **
-         11'h4a8: data = 8'b11001100; // **  **
-         11'h4a9: data = 8'b11001100; // **  **
-         11'h4aa: data = 8'b11001100; // **  **
-         11'h4ab: data = 8'b01111000; //  ****
-         11'h4ac: data = 8'b00000000; // 
-         11'h4ad: data = 8'b00000000; // 
-         11'h4ae: data = 8'b00000000; // 
-         11'h4af: data = 8'b00000000; // 
-         //code x4b   
-         11'h4b0: data = 8'b00000000; // 
-         11'h4b1: data = 8'b00000000; // 
-         11'h4b2: data = 8'b11100110; // ***  **
-         11'h4b3: data = 8'b01100110; //  **  **
-         11'h4b4: data = 8'b01100110; //  **  **
-         11'h4b5: data = 8'b01101100; //  ** **
-         11'h4b6: data = 8'b01111000; //  ****
-         11'h4b7: data = 8'b01111000; //  ****
-         11'h4b8: data = 8'b01101100; //  ** **
-         11'h4b9: data = 8'b01100110; //  **  **
-         11'h4ba: data = 8'b01100110; //  **  **
-         11'h4bb: data = 8'b11100110; // ***  **
-         11'h4bc: data = 8'b00000000; // 
-         11'h4bd: data = 8'b00000000; // 
-         11'h4be: data = 8'b00000000; // 
-         11'h4bf: data = 8'b00000000; // 
-         //code x4c   
-         11'h4c0: data = 8'b00000000; // 
-         11'h4c1: data = 8'b00000000; // 
-         11'h4c2: data = 8'b11110000; // ****
-         11'h4c3: data = 8'b01100000; //  **
-         11'h4c4: data = 8'b01100000; //  **
-         11'h4c5: data = 8'b01100000; //  **
-         11'h4c6: data = 8'b01100000; //  **
-         11'h4c7: data = 8'b01100000; //  **
-         11'h4c8: data = 8'b01100000; //  **
-         11'h4c9: data = 8'b01100010; //  **   *
-         11'h4ca: data = 8'b01100110; //  **  **
-         11'h4cb: data = 8'b11111110; // *******
-         11'h4cc: data = 8'b00000000; // 
-         11'h4cd: data = 8'b00000000; // 
-         11'h4ce: data = 8'b00000000; // 
-         11'h4cf: data = 8'b00000000; // 
-         //code x4d   
-         11'h4d0: data = 8'b00000000; // 
-         11'h4d1: data = 8'b00000000; // 
-         11'h4d2: data = 8'b11000011; // **    **
-         11'h4d3: data = 8'b11100111; // ***  ***
-         11'h4d4: data = 8'b11111111; // ********
-         11'h4d5: data = 8'b11111111; // ********
-         11'h4d6: data = 8'b11011011; // ** ** **
-         11'h4d7: data = 8'b11000011; // **    **
-         11'h4d8: data = 8'b11000011; // **    **
-         11'h4d9: data = 8'b11000011; // **    **
-         11'h4da: data = 8'b11000011; // **    **
-         11'h4db: data = 8'b11000011; // **    **
-         11'h4dc: data = 8'b00000000; // 
-         11'h4dd: data = 8'b00000000; // 
-         11'h4de: data = 8'b00000000; // 
-         11'h4df: data = 8'b00000000; // 
-         //code x4e   
-         11'h4e0: data = 8'b00000000; // 
-         11'h4e1: data = 8'b00000000; // 
-         11'h4e2: data = 8'b11000110; // **   **
-         11'h4e3: data = 8'b11100110; // ***  **
-         11'h4e4: data = 8'b11110110; // **** **
-         11'h4e5: data = 8'b11111110; // *******
-         11'h4e6: data = 8'b11011110; // ** ****
-         11'h4e7: data = 8'b11001110; // **  ***
-         11'h4e8: data = 8'b11000110; // **   **
-         11'h4e9: data = 8'b11000110; // **   **
-         11'h4ea: data = 8'b11000110; // **   **
-         11'h4eb: data = 8'b11000110; // **   **
-         11'h4ec: data = 8'b00000000; // 
-         11'h4ed: data = 8'b00000000; // 
-         11'h4ee: data = 8'b00000000; // 
-         11'h4ef: data = 8'b00000000; // 
-         //code x4f   
-         11'h4f0: data = 8'b00000000; // 
-         11'h4f1: data = 8'b00000000; // 
-         11'h4f2: data = 8'b01111100; //  *****
-         11'h4f3: data = 8'b11000110; // **   **
-         11'h4f4: data = 8'b11000110; // **   **
-         11'h4f5: data = 8'b11000110; // **   **
-         11'h4f6: data = 8'b11000110; // **   **
-         11'h4f7: data = 8'b11000110; // **   **
-         11'h4f8: data = 8'b11000110; // **   **
-         11'h4f9: data = 8'b11000110; // **   **
-         11'h4fa: data = 8'b11000110; // **   **
-         11'h4fb: data = 8'b01111100; //  *****
-         11'h4fc: data = 8'b00000000; // 
-         11'h4fd: data = 8'b00000000; // 
-         11'h4fe: data = 8'b00000000; // 
-         11'h4ff: data = 8'b00000000; // 
-         //code x50   
-         11'h500: data = 8'b00000000; // 
-         11'h501: data = 8'b00000000; // 
-         11'h502: data = 8'b11111100; // ******
-         11'h503: data = 8'b01100110; //  **  **
-         11'h504: data = 8'b01100110; //  **  **
-         11'h505: data = 8'b01100110; //  **  **
-         11'h506: data = 8'b01111100; //  *****
-         11'h507: data = 8'b01100000; //  **
-         11'h508: data = 8'b01100000; //  **
-         11'h509: data = 8'b01100000; //  **
-         11'h50a: data = 8'b01100000; //  **
-         11'h50b: data = 8'b11110000; // ****
-         11'h50c: data = 8'b00000000; // 
-         11'h50d: data = 8'b00000000; // 
-         11'h50e: data = 8'b00000000; // 
-         11'h50f: data = 8'b00000000; // 
-         //code x510f
-         11'h510: data = 8'b00000000; // 
-         11'h511: data = 8'b00000000; // 
-         11'h512: data = 8'b01111100; //  *****
-         11'h513: data = 8'b11000110; // **   **
-         11'h514: data = 8'b11000110; // **   **
-         11'h515: data = 8'b11000110; // **   **
-         11'h516: data = 8'b11000110; // **   **
-         11'h517: data = 8'b11000110; // **   **
-         11'h518: data = 8'b11000110; // **   **
-         11'h519: data = 8'b11010110; // ** * **
-         11'h51a: data = 8'b11011110; // ** ****
-         11'h51b: data = 8'b01111100; //  *****
-         11'h51c: data = 8'b00001100; //     **
-         11'h51d: data = 8'b00001110; //     ***
-         11'h51e: data = 8'b00000000; // 
-         11'h51f: data = 8'b00000000; // 
-         //code x52   
-         11'h520: data = 8'b00000000; // 
-         11'h521: data = 8'b00000000; // 
-         11'h522: data = 8'b11111100; // ******
-         11'h523: data = 8'b01100110; //  **  **
-         11'h524: data = 8'b01100110; //  **  **
-         11'h525: data = 8'b01100110; //  **  **
-         11'h526: data = 8'b01111100; //  *****
-         11'h527: data = 8'b01101100; //  ** **
-         11'h528: data = 8'b01100110; //  **  **
-         11'h529: data = 8'b01100110; //  **  **
-         11'h52a: data = 8'b01100110; //  **  **
-         11'h52b: data = 8'b11100110; // ***  **
-         11'h52c: data = 8'b00000000; // 
-         11'h52d: data = 8'b00000000; // 
-         11'h52e: data = 8'b00000000; // 
-         11'h52f: data = 8'b00000000; // 
-         //code x53   
-         11'h530: data = 8'b00000000; // 
-         11'h531: data = 8'b00000000; // 
-         11'h532: data = 8'b01111100; //  *****
-         11'h533: data = 8'b11000110; // **   **
-         11'h534: data = 8'b11000110; // **   **
-         11'h535: data = 8'b01100000; //  **
-         11'h536: data = 8'b00111000; //   ***
-         11'h537: data = 8'b00001100; //     **
-         11'h538: data = 8'b00000110; //      **
-         11'h539: data = 8'b11000110; // **   **
-         11'h53a: data = 8'b11000110; // **   **
-         11'h53b: data = 8'b01111100; //  *****
-         11'h53c: data = 8'b00000000; // 
-         11'h53d: data = 8'b00000000; // 
-         11'h53e: data = 8'b00000000; // 
-         11'h53f: data = 8'b00000000; // 
-         //code x54   
-         11'h540: data = 8'b00000000; // 
-         11'h541: data = 8'b00000000; // 
-         11'h542: data = 8'b11111111; // ********
-         11'h543: data = 8'b11011011; // ** ** **
-         11'h544: data = 8'b10011001; // *  **  *
-         11'h545: data = 8'b00011000; //    **
-         11'h546: data = 8'b00011000; //    **
-         11'h547: data = 8'b00011000; //    **
-         11'h548: data = 8'b00011000; //    **
-         11'h549: data = 8'b00011000; //    **
-         11'h54a: data = 8'b00011000; //    **
-         11'h54b: data = 8'b00111100; //   ****
-         11'h54c: data = 8'b00000000; // 
-         11'h54d: data = 8'b00000000; // 
-         11'h54e: data = 8'b00000000; // 
-         11'h54f: data = 8'b00000000; // 
-         //code x55   
-         11'h550: data = 8'b00000000; // 
-         11'h551: data = 8'b00000000; // 
-         11'h552: data = 8'b11000110; // **   **
-         11'h553: data = 8'b11000110; // **   **
-         11'h554: data = 8'b11000110; // **   **
-         11'h555: data = 8'b11000110; // **   **
-         11'h556: data = 8'b11000110; // **   **
-         11'h557: data = 8'b11000110; // **   **
-         11'h558: data = 8'b11000110; // **   **
-         11'h559: data = 8'b11000110; // **   **
-         11'h55a: data = 8'b11000110; // **   **
-         11'h55b: data = 8'b01111100; //  *****
-         11'h55c: data = 8'b00000000; // 
-         11'h55d: data = 8'b00000000; // 
-         11'h55e: data = 8'b00000000; // 
-         11'h55f: data = 8'b00000000; // 
-         //code x56   
-         11'h560: data = 8'b00000000; // 
-         11'h561: data = 8'b00000000; // 
-         11'h562: data = 8'b11000011; // **    **
-         11'h563: data = 8'b11000011; // **    **
-         11'h564: data = 8'b11000011; // **    **
-         11'h565: data = 8'b11000011; // **    **
-         11'h566: data = 8'b11000011; // **    **
-         11'h567: data = 8'b11000011; // **    **
-         11'h568: data = 8'b11000011; // **    **
-         11'h569: data = 8'b01100110; //  **  **
-         11'h56a: data = 8'b00111100; //   ****
-         11'h56b: data = 8'b00011000; //    **
-         11'h56c: data = 8'b00000000; // 
-         11'h56d: data = 8'b00000000; // 
-         11'h56e: data = 8'b00000000; // 
-         11'h56f: data = 8'b00000000; // 
-         //code x57   
-         11'h570: data = 8'b00000000; // 
-         11'h571: data = 8'b00000000; // 
-         11'h572: data = 8'b11000011; // **    **
-         11'h573: data = 8'b11000011; // **    **
-         11'h574: data = 8'b11000011; // **    **
-         11'h575: data = 8'b11000011; // **    **
-         11'h576: data = 8'b11000011; // **    **
-         11'h577: data = 8'b11011011; // ** ** **
-         11'h578: data = 8'b11011011; // ** ** **
-         11'h579: data = 8'b11111111; // ********
-         11'h57a: data = 8'b01100110; //  **  **
-         11'h57b: data = 8'b01100110; //  **  **
-         11'h57c: data = 8'b00000000; // 
-         11'h57d: data = 8'b00000000; // 
-         11'h57e: data = 8'b00000000; // 
-         11'h57f: data = 8'b00000000; // 
-         //code x58   
-         11'h580: data = 8'b00000000; // 
-         11'h581: data = 8'b00000000; // 
-         11'h582: data = 8'b11000011; // **    **
-         11'h583: data = 8'b11000011; // **    **
-         11'h584: data = 8'b01100110; //  **  **
-         11'h585: data = 8'b00111100; //   ****
-         11'h586: data = 8'b00011000; //    **
-         11'h587: data = 8'b00011000; //    **
-         11'h588: data = 8'b00111100; //   ****
-         11'h589: data = 8'b01100110; //  **  **
-         11'h58a: data = 8'b11000011; // **    **
-         11'h58b: data = 8'b11000011; // **    **
-         11'h58c: data = 8'b00000000; // 
-         11'h58d: data = 8'b00000000; // 
-         11'h58e: data = 8'b00000000; // 
-         11'h58f: data = 8'b00000000; // 
-         //code x59   
-         11'h590: data = 8'b00000000; // 
-         11'h591: data = 8'b00000000; // 
-         11'h592: data = 8'b11000011; // **    **
-         11'h593: data = 8'b11000011; // **    **
-         11'h594: data = 8'b11000011; // **    **
-         11'h595: data = 8'b01100110; //  **  **
-         11'h596: data = 8'b00111100; //   ****
-         11'h597: data = 8'b00011000; //    **
-         11'h598: data = 8'b00011000; //    **
-         11'h599: data = 8'b00011000; //    **
-         11'h59a: data = 8'b00011000; //    **
-         11'h59b: data = 8'b00111100; //   ****
-         11'h59c: data = 8'b00000000; // 
-         11'h59d: data = 8'b00000000; // 
-         11'h59e: data = 8'b00000000; // 
-         11'h59f: data = 8'b00000000; // 
-         //code x5a   
-         11'h5a0: data = 8'b00000000; // 
-         11'h5a1: data = 8'b00000000; // 
-         11'h5a2: data = 8'b11111111; // ********
-         11'h5a3: data = 8'b11000011; // **    **
-         11'h5a4: data = 8'b10000110; // *    **
-         11'h5a5: data = 8'b00001100; //     **
-         11'h5a6: data = 8'b00011000; //    **
-         11'h5a7: data = 8'b00110000; //   **
-         11'h5a8: data = 8'b01100000; //  **
-         11'h5a9: data = 8'b11000001; // **     *
-         11'h5aa: data = 8'b11000011; // **    **
-         11'h5ab: data = 8'b11111111; // ********
-         11'h5ac: data = 8'b00000000; // 
-         11'h5ad: data = 8'b00000000; // 
-         11'h5ae: data = 8'b00000000; // 
-         11'h5af: data = 8'b00000000; // 
-         //code x5b   
-         11'h5b0: data = 8'b00000000; // 
-         11'h5b1: data = 8'b00000000; // 
-         11'h5b2: data = 8'b00111100; //   ****
-         11'h5b3: data = 8'b00110000; //   **
-         11'h5b4: data = 8'b00110000; //   **
-         11'h5b5: data = 8'b00110000; //   **
-         11'h5b6: data = 8'b00110000; //   **
-         11'h5b7: data = 8'b00110000; //   **
-         11'h5b8: data = 8'b00110000; //   **
-         11'h5b9: data = 8'b00110000; //   **
-         11'h5ba: data = 8'b00110000; //   **
-         11'h5bb: data = 8'b00111100; //   ****
-         11'h5bc: data = 8'b00000000; // 
-         11'h5bd: data = 8'b00000000; // 
-         11'h5be: data = 8'b00000000; // 
-         11'h5bf: data = 8'b00000000; // 
-         //code x5c   
-         11'h5c0: data = 8'b00000000; // 
-         11'h5c1: data = 8'b00000000; // 
-         11'h5c2: data = 8'b00000000; // 
-         11'h5c3: data = 8'b10000000; // *
-         11'h5c4: data = 8'b11000000; // **
-         11'h5c5: data = 8'b11100000; // ***
-         11'h5c6: data = 8'b01110000; //  ***
-         11'h5c7: data = 8'b00111000; //   ***
-         11'h5c8: data = 8'b00011100; //    ***
-         11'h5c9: data = 8'b00001110; //     ***
-         11'h5ca: data = 8'b00000110; //      **
-         11'h5cb: data = 8'b00000010; //       *
-         11'h5cc: data = 8'b00000000; // 
-         11'h5cd: data = 8'b00000000; // 
-         11'h5ce: data = 8'b00000000; // 
-         11'h5cf: data = 8'b00000000; // 
-         //code x5d   
-         11'h5d0: data = 8'b00000000; // 
-         11'h5d1: data = 8'b00000000; // 
-         11'h5d2: data = 8'b00111100; //   ****
-         11'h5d3: data = 8'b00001100; //     **
-         11'h5d4: data = 8'b00001100; //     **
-         11'h5d5: data = 8'b00001100; //     **
-         11'h5d6: data = 8'b00001100; //     **
-         11'h5d7: data = 8'b00001100; //     **
-         11'h5d8: data = 8'b00001100; //     **
-         11'h5d9: data = 8'b00001100; //     **
-         11'h5da: data = 8'b00001100; //     **
-         11'h5db: data = 8'b00111100; //   ****
-         11'h5dc: data = 8'b00000000; // 
-         11'h5dd: data = 8'b00000000; // 
-         11'h5de: data = 8'b00000000; // 
-         11'h5df: data = 8'b00000000; // 
-         //code x5e   
-         11'h5e0: data = 8'b00010000; //    *
-         11'h5e1: data = 8'b00111000; //   ***
-         11'h5e2: data = 8'b01101100; //  ** **
-         11'h5e3: data = 8'b11000110; // **   **
-         11'h5e4: data = 8'b00000000; // 
-         11'h5e5: data = 8'b00000000; // 
-         11'h5e6: data = 8'b00000000; // 
-         11'h5e7: data = 8'b00000000; // 
-         11'h5e8: data = 8'b00000000; // 
-         11'h5e9: data = 8'b00000000; // 
-         11'h5ea: data = 8'b00000000; // 
-         11'h5eb: data = 8'b00000000; // 
-         11'h5ec: data = 8'b00000000; // 
-         11'h5ed: data = 8'b00000000; // 
-         11'h5ee: data = 8'b00000000; // 
-         11'h5ef: data = 8'b00000000; // 
-         //code x5f   
-         11'h5f0: data = 8'b00000000; // 
-         11'h5f1: data = 8'b00000000; // 
-         11'h5f2: data = 8'b00000000; // 
-         11'h5f3: data = 8'b00000000; // 
-         11'h5f4: data = 8'b00000000; // 
-         11'h5f5: data = 8'b00000000; // 
-         11'h5f6: data = 8'b00000000; // 
-         11'h5f7: data = 8'b00000000; // 
-         11'h5f8: data = 8'b00000000; // 
-         11'h5f9: data = 8'b00000000; // 
-         11'h5fa: data = 8'b00000000; // 
-         11'h5fb: data = 8'b00000000; // 
-         11'h5fc: data = 8'b00000000; // 
-         11'h5fd: data = 8'b11111111; // ********
-         11'h5fe: data = 8'b00000000; // 
-         11'h5ff: data = 8'b00000000; // 
-         //code x60   
-         11'h600: data = 8'b00110000; //   **
-         11'h601: data = 8'b00110000; //   **
-         11'h602: data = 8'b00011000; //    **
-         11'h603: data = 8'b00000000; // 
-         11'h604: data = 8'b00000000; // 
-         11'h605: data = 8'b00000000; // 
-         11'h606: data = 8'b00000000; // 
-         11'h607: data = 8'b00000000; // 
-         11'h608: data = 8'b00000000; // 
-         11'h609: data = 8'b00000000; // 
-         11'h60a: data = 8'b00000000; // 
-         11'h60b: data = 8'b00000000; // 
-         11'h60c: data = 8'b00000000; // 
-         11'h60d: data = 8'b00000000; // 
-         11'h60e: data = 8'b00000000; // 
-         11'h60f: data = 8'b00000000; // 
-         //code x61   
-         11'h610: data = 8'b00000000; // 
-         11'h611: data = 8'b00000000; // 
-         11'h612: data = 8'b00000000; // 
-         11'h613: data = 8'b00000000; // 
-         11'h614: data = 8'b00000000; // 
-         11'h615: data = 8'b01111000; //  ****
-         11'h616: data = 8'b00001100; //     **
-         11'h617: data = 8'b01111100; //  *****
-         11'h618: data = 8'b11001100; // **  **
-         11'h619: data = 8'b11001100; // **  **
-         11'h61a: data = 8'b11001100; // **  **
-         11'h61b: data = 8'b01110110; //  *** **
-         11'h61c: data = 8'b00000000; // 
-         11'h61d: data = 8'b00000000; // 
-         11'h61e: data = 8'b00000000; // 
-         11'h61f: data = 8'b00000000; // 
-         //code x62   
-         11'h620: data = 8'b00000000; // 
-         11'h621: data = 8'b00000000; // 
-         11'h622: data = 8'b11100000; //  ***
-         11'h623: data = 8'b01100000; //   **
-         11'h624: data = 8'b01100000; //   **
-         11'h625: data = 8'b01111000; //   ****
-         11'h626: data = 8'b01101100; //   ** **
-         11'h627: data = 8'b01100110; //   **  **
-         11'h628: data = 8'b01100110; //   **  **
-         11'h629: data = 8'b01100110; //   **  **
-         11'h62a: data = 8'b01100110; //   **  **
-         11'h62b: data = 8'b01111100; //   *****
-         11'h62c: data = 8'b00000000; // 
-         11'h62d: data = 8'b00000000; // 
-         11'h62e: data = 8'b00000000; // 
-         11'h62f: data = 8'b00000000; // 
-         //code x63   
-         11'h630: data = 8'b00000000; // 
-         11'h631: data = 8'b00000000; // 
-         11'h632: data = 8'b00000000; // 
-         11'h633: data = 8'b00000000; // 
-         11'h634: data = 8'b00000000; // 
-         11'h635: data = 8'b01111100; //  *****
-         11'h636: data = 8'b11000110; // **   **
-         11'h637: data = 8'b11000000; // **
-         11'h638: data = 8'b11000000; // **
-         11'h639: data = 8'b11000000; // **
-         11'h63a: data = 8'b11000110; // **   **
-         11'h63b: data = 8'b01111100; //  *****
-         11'h63c: data = 8'b00000000; // 
-         11'h63d: data = 8'b00000000; // 
-         11'h63e: data = 8'b00000000; // 
-         11'h63f: data = 8'b00000000; // 
-         //code x64   
-         11'h640: data = 8'b00000000; // 
-         11'h641: data = 8'b00000000; // 
-         11'h642: data = 8'b00011100; //    ***
-         11'h643: data = 8'b00001100; //     **
-         11'h644: data = 8'b00001100; //     **
-         11'h645: data = 8'b00111100; //   ****
-         11'h646: data = 8'b01101100; //  ** **
-         11'h647: data = 8'b11001100; // **  **
-         11'h648: data = 8'b11001100; // **  **
-         11'h649: data = 8'b11001100; // **  **
-         11'h64a: data = 8'b11001100; // **  **
-         11'h64b: data = 8'b01110110; //  *** **
-         11'h64c: data = 8'b00000000; // 
-         11'h64d: data = 8'b00000000; // 
-         11'h64e: data = 8'b00000000; // 
-         11'h64f: data = 8'b00000000; // 
-         //code x65   
-         11'h650: data = 8'b00000000; // 
-         11'h651: data = 8'b00000000; // 
-         11'h652: data = 8'b00000000; // 
-         11'h653: data = 8'b00000000; // 
-         11'h654: data = 8'b00000000; // 
-         11'h655: data = 8'b01111100; //  *****
-         11'h656: data = 8'b11000110; // **   **
-         11'h657: data = 8'b11111110; // *******
-         11'h658: data = 8'b11000000; // **
-         11'h659: data = 8'b11000000; // **
-         11'h65a: data = 8'b11000110; // **   **
-         11'h65b: data = 8'b01111100; //  *****
-         11'h65c: data = 8'b00000000; // 
-         11'h65d: data = 8'b00000000; // 
-         11'h65e: data = 8'b00000000; // 
-         11'h65f: data = 8'b00000000; // 
-         //code x66   
-         11'h660: data = 8'b00000000; // 
-         11'h661: data = 8'b00000000; // 
-         11'h662: data = 8'b00111000; //   ***
-         11'h663: data = 8'b01101100; //  ** **
-         11'h664: data = 8'b01100100; //  **  *
-         11'h665: data = 8'b01100000; //  **
-         11'h666: data = 8'b11110000; // ****
-         11'h667: data = 8'b01100000; //  **
-         11'h668: data = 8'b01100000; //  **
-         11'h669: data = 8'b01100000; //  **
-         11'h66a: data = 8'b01100000; //  **
-         11'h66b: data = 8'b11110000; // ****
-         11'h66c: data = 8'b00000000; // 
-         11'h66d: data = 8'b00000000; // 
-         11'h66e: data = 8'b00000000; // 
-         11'h66f: data = 8'b00000000; // 
-         //code x67   
-         11'h670: data = 8'b00000000; // 
-         11'h671: data = 8'b00000000; // 
-         11'h672: data = 8'b00000000; // 
-         11'h673: data = 8'b00000000; // 
-         11'h674: data = 8'b00000000; // 
-         11'h675: data = 8'b01110110; //  *** **
-         11'h676: data = 8'b11001100; // **  **
-         11'h677: data = 8'b11001100; // **  **
-         11'h678: data = 8'b11001100; // **  **
-         11'h679: data = 8'b11001100; // **  **
-         11'h67a: data = 8'b11001100; // **  **
-         11'h67b: data = 8'b01111100; //  *****
-         11'h67c: data = 8'b00001100; //     **
-         11'h67d: data = 8'b11001100; // **  **
-         11'h67e: data = 8'b01111000; //  ****
-         11'h67f: data = 8'b00000000; // 
-         //code x68   
-         11'h680: data = 8'b00000000; // 
-         11'h681: data = 8'b00000000; // 
-         11'h682: data = 8'b11100000; // ***
-         11'h683: data = 8'b01100000; //  **
-         11'h684: data = 8'b01100000; //  **
-         11'h685: data = 8'b01101100; //  ** **
-         11'h686: data = 8'b01110110; //  *** **
-         11'h687: data = 8'b01100110; //  **  **
-         11'h688: data = 8'b01100110; //  **  **
-         11'h689: data = 8'b01100110; //  **  **
-         11'h68a: data = 8'b01100110; //  **  **
-         11'h68b: data = 8'b11100110; // ***  **
-         11'h68c: data = 8'b00000000; // 
-         11'h68d: data = 8'b00000000; // 
-         11'h68e: data = 8'b00000000; // 
-         11'h68f: data = 8'b00000000; // 
-         //code x69   
-         11'h690: data = 8'b00000000; // 
-         11'h691: data = 8'b00000000; // 
-         11'h692: data = 8'b00011000; //    **
-         11'h693: data = 8'b00011000; //    **
-         11'h694: data = 8'b00000000; // 
-         11'h695: data = 8'b00111000; //   ***
-         11'h696: data = 8'b00011000; //    **
-         11'h697: data = 8'b00011000; //    **
-         11'h698: data = 8'b00011000; //    **
-         11'h699: data = 8'b00011000; //    **
-         11'h69a: data = 8'b00011000; //    **
-         11'h69b: data = 8'b00111100; //   ****
-         11'h69c: data = 8'b00000000; // 
-         11'h69d: data = 8'b00000000; // 
-         11'h69e: data = 8'b00000000; // 
-         11'h69f: data = 8'b00000000; // 
-         //code x6a   
-         11'h6a0: data = 8'b00000000; // 
-         11'h6a1: data = 8'b00000000; // 
-         11'h6a2: data = 8'b00000110; //      **
-         11'h6a3: data = 8'b00000110; //      **
-         11'h6a4: data = 8'b00000000; // 
-         11'h6a5: data = 8'b00001110; //     ***
-         11'h6a6: data = 8'b00000110; //      **
-         11'h6a7: data = 8'b00000110; //      **
-         11'h6a8: data = 8'b00000110; //      **
-         11'h6a9: data = 8'b00000110; //      **
-         11'h6aa: data = 8'b00000110; //      **
-         11'h6ab: data = 8'b00000110; //      **
-         11'h6ac: data = 8'b01100110; //  **  **
-         11'h6ad: data = 8'b01100110; //  **  **
-         11'h6ae: data = 8'b00111100; //   ****
-         11'h6af: data = 8'b00000000; // 
-         //code x6b   
-         11'h6b0: data = 8'b00000000; // 
-         11'h6b1: data = 8'b00000000; // 
-         11'h6b2: data = 8'b11100000; // ***
-         11'h6b3: data = 8'b01100000; //  **
-         11'h6b4: data = 8'b01100000; //  **
-         11'h6b5: data = 8'b01100110; //  **  **
-         11'h6b6: data = 8'b01101100; //  ** **
-         11'h6b7: data = 8'b01111000; //  ****
-         11'h6b8: data = 8'b01111000; //  ****
-         11'h6b9: data = 8'b01101100; //  ** **
-         11'h6ba: data = 8'b01100110; //  **  **
-         11'h6bb: data = 8'b11100110; // ***  **
-         11'h6bc: data = 8'b00000000; // 
-         11'h6bd: data = 8'b00000000; // 
-         11'h6be: data = 8'b00000000; // 
-         11'h6bf: data = 8'b00000000; // 
-         //code x6c   
-         11'h6c0: data = 8'b00000000; // 
-         11'h6c1: data = 8'b00000000; // 
-         11'h6c2: data = 8'b00111000; //   ***
-         11'h6c3: data = 8'b00011000; //    **
-         11'h6c4: data = 8'b00011000; //    **
-         11'h6c5: data = 8'b00011000; //    **
-         11'h6c6: data = 8'b00011000; //    **
-         11'h6c7: data = 8'b00011000; //    **
-         11'h6c8: data = 8'b00011000; //    **
-         11'h6c9: data = 8'b00011000; //    **
-         11'h6ca: data = 8'b00011000; //    **
-         11'h6cb: data = 8'b00111100; //   ****
-         11'h6cc: data = 8'b00000000; // 
-         11'h6cd: data = 8'b00000000; // 
-         11'h6ce: data = 8'b00000000; // 
-         11'h6cf: data = 8'b00000000; // 
-         //code x6d   
-         11'h6d0: data = 8'b00000000; // 
-         11'h6d1: data = 8'b00000000; // 
-         11'h6d2: data = 8'b00000000; // 
-         11'h6d3: data = 8'b00000000; // 
-         11'h6d4: data = 8'b00000000; // 
-         11'h6d5: data = 8'b11100110; // ***  **
-         11'h6d6: data = 8'b11111111; // ********
-         11'h6d7: data = 8'b11011011; // ** ** **
-         11'h6d8: data = 8'b11011011; // ** ** **
-         11'h6d9: data = 8'b11011011; // ** ** **
-         11'h6da: data = 8'b11011011; // ** ** **
-         11'h6db: data = 8'b11011011; // ** ** **
-         11'h6dc: data = 8'b00000000; // 
-         11'h6dd: data = 8'b00000000; // 
-         11'h6de: data = 8'b00000000; // 
-         11'h6df: data = 8'b00000000; // 
-         //code x6e   
-         11'h6e0: data = 8'b00000000; // 
-         11'h6e1: data = 8'b00000000; // 
-         11'h6e2: data = 8'b00000000; // 
-         11'h6e3: data = 8'b00000000; // 
-         11'h6e4: data = 8'b00000000; // 
-         11'h6e5: data = 8'b11011100; // ** ***
-         11'h6e6: data = 8'b01100110; //  **  **
-         11'h6e7: data = 8'b01100110; //  **  **
-         11'h6e8: data = 8'b01100110; //  **  **
-         11'h6e9: data = 8'b01100110; //  **  **
-         11'h6ea: data = 8'b01100110; //  **  **
-         11'h6eb: data = 8'b01100110; //  **  **
-         11'h6ec: data = 8'b00000000; // 
-         11'h6ed: data = 8'b00000000; // 
-         11'h6ee: data = 8'b00000000; // 
-         11'h6ef: data = 8'b00000000; // 
-         //code x6f   
-         11'h6f0: data = 8'b00000000; // 
-         11'h6f1: data = 8'b00000000; // 
-         11'h6f2: data = 8'b00000000; // 
-         11'h6f3: data = 8'b00000000; // 
-         11'h6f4: data = 8'b00000000; // 
-         11'h6f5: data = 8'b01111100; //  *****
-         11'h6f6: data = 8'b11000110; // **   **
-         11'h6f7: data = 8'b11000110; // **   **
-         11'h6f8: data = 8'b11000110; // **   **
-         11'h6f9: data = 8'b11000110; // **   **
-         11'h6fa: data = 8'b11000110; // **   **
-         11'h6fb: data = 8'b01111100; //  *****
-         11'h6fc: data = 8'b00000000; // 
-         11'h6fd: data = 8'b00000000; // 
-         11'h6fe: data = 8'b00000000; // 
-         11'h6ff: data = 8'b00000000; // 
-         //code x70   
-         11'h700: data = 8'b00000000; // 
-         11'h701: data = 8'b00000000; // 
-         11'h702: data = 8'b00000000; // 
-         11'h703: data = 8'b00000000; // 
-         11'h704: data = 8'b00000000; // 
-         11'h705: data = 8'b11011100; // ** ***
-         11'h706: data = 8'b01100110; //  **  **
-         11'h707: data = 8'b01100110; //  **  **
-         11'h708: data = 8'b01100110; //  **  **
-         11'h709: data = 8'b01100110; //  **  **
-         11'h70a: data = 8'b01100110; //  **  **
-         11'h70b: data = 8'b01111100; //  *****
-         11'h70c: data = 8'b01100000; //  **
-         11'h70d: data = 8'b01100000; //  **
-         11'h70e: data = 8'b11110000; // ****
-         11'h70f: data = 8'b00000000; // 
-         //code x71   
-         11'h710: data = 8'b00000000; // 
-         11'h711: data = 8'b00000000; // 
-         11'h712: data = 8'b00000000; // 
-         11'h713: data = 8'b00000000; // 
-         11'h714: data = 8'b00000000; // 
-         11'h715: data = 8'b01110110; //  *** **
-         11'h716: data = 8'b11001100; // **  **
-         11'h717: data = 8'b11001100; // **  **
-         11'h718: data = 8'b11001100; // **  **
-         11'h719: data = 8'b11001100; // **  **
-         11'h71a: data = 8'b11001100; // **  **
-         11'h71b: data = 8'b01111100; //  *****
-         11'h71c: data = 8'b00001100; //     **
-         11'h71d: data = 8'b00001100; //     **
-         11'h71e: data = 8'b00011110; //    ****
-         11'h71f: data = 8'b00000000; // 
-         //code x72   
-         11'h720: data = 8'b00000000; // 
-         11'h721: data = 8'b00000000; // 
-         11'h722: data = 8'b00000000; // 
-         11'h723: data = 8'b00000000; // 
-         11'h724: data = 8'b00000000; // 
-         11'h725: data = 8'b11011100; // ** ***
-         11'h726: data = 8'b01110110; //  *** **
-         11'h727: data = 8'b01100110; //  **  **
-         11'h728: data = 8'b01100000; //  **
-         11'h729: data = 8'b01100000; //  **
-         11'h72a: data = 8'b01100000; //  **
-         11'h72b: data = 8'b11110000; // ****
-         11'h72c: data = 8'b00000000; // 
-         11'h72d: data = 8'b00000000; // 
-         11'h72e: data = 8'b00000000; // 
-         11'h72f: data = 8'b00000000; // 
-         //code x73   
-         11'h730: data = 8'b00000000; // 
-         11'h731: data = 8'b00000000; // 
-         11'h732: data = 8'b00000000; // 
-         11'h733: data = 8'b00000000; // 
-         11'h734: data = 8'b00000000; // 
-         11'h735: data = 8'b01111100; //  *****
-         11'h736: data = 8'b11000110; // **   **
-         11'h737: data = 8'b01100000; //  **
-         11'h738: data = 8'b00111000; //   ***
-         11'h739: data = 8'b00001100; //     **
-         11'h73a: data = 8'b11000110; // **   **
-         11'h73b: data = 8'b01111100; //  *****
-         11'h73c: data = 8'b00000000; // 
-         11'h73d: data = 8'b00000000; // 
-         11'h73e: data = 8'b00000000; // 
-         11'h73f: data = 8'b00000000; // 
-         //code x74   
-         11'h740: data = 8'b00000000; // 
-         11'h741: data = 8'b00000000; // 
-         11'h742: data = 8'b00010000; //    *
-         11'h743: data = 8'b00110000; //   **
-         11'h744: data = 8'b00110000; //   **
-         11'h745: data = 8'b11111100; // ******
-         11'h746: data = 8'b00110000; //   **
-         11'h747: data = 8'b00110000; //   **
-         11'h748: data = 8'b00110000; //   **
-         11'h749: data = 8'b00110000; //   **
-         11'h74a: data = 8'b00110110; //   ** **
-         11'h74b: data = 8'b00011100; //    ***
-         11'h74c: data = 8'b00000000; // 
-         11'h74d: data = 8'b00000000; // 
-         11'h74e: data = 8'b00000000; // 
-         11'h74f: data = 8'b00000000; // 
-         //code x75   
-         11'h750: data = 8'b00000000; // 
-         11'h751: data = 8'b00000000; // 
-         11'h752: data = 8'b00000000; // 
-         11'h753: data = 8'b00000000; // 
-         11'h754: data = 8'b00000000; // 
-         11'h755: data = 8'b11001100; // **  **
-         11'h756: data = 8'b11001100; // **  **
-         11'h757: data = 8'b11001100; // **  **
-         11'h758: data = 8'b11001100; // **  **
-         11'h759: data = 8'b11001100; // **  **
-         11'h75a: data = 8'b11001100; // **  **
-         11'h75b: data = 8'b01110110; //  *** **
-         11'h75c: data = 8'b00000000; // 
-         11'h75d: data = 8'b00000000; // 
-         11'h75e: data = 8'b00000000; // 
-         11'h75f: data = 8'b00000000; // 
-         //code x76   
-         11'h760: data = 8'b00000000; // 
-         11'h761: data = 8'b00000000; // 
-         11'h762: data = 8'b00000000; // 
-         11'h763: data = 8'b00000000; // 
-         11'h764: data = 8'b00000000; // 
-         11'h765: data = 8'b11000011; // **    **
-         11'h766: data = 8'b11000011; // **    **
-         11'h767: data = 8'b11000011; // **    **
-         11'h768: data = 8'b11000011; // **    **
-         11'h769: data = 8'b01100110; //  **  **
-         11'h76a: data = 8'b00111100; //   ****
-         11'h76b: data = 8'b00011000; //    **
-         11'h76c: data = 8'b00000000; // 
-         11'h76d: data = 8'b00000000; // 
-         11'h76e: data = 8'b00000000; // 
-         11'h76f: data = 8'b00000000; // 
-         //code x77   
-         11'h770: data = 8'b00000000; // 
-         11'h771: data = 8'b00000000; // 
-         11'h772: data = 8'b00000000; // 
-         11'h773: data = 8'b00000000; // 
-         11'h774: data = 8'b00000000; // 
-         11'h775: data = 8'b11000011; // **    **
-         11'h776: data = 8'b11000011; // **    **
-         11'h777: data = 8'b11000011; // **    **
-         11'h778: data = 8'b11011011; // ** ** **
-         11'h779: data = 8'b11011011; // ** ** **
-         11'h77a: data = 8'b11111111; // ********
-         11'h77b: data = 8'b01100110; //  **  **
-         11'h77c: data = 8'b00000000; // 
-         11'h77d: data = 8'b00000000; // 
-         11'h77e: data = 8'b00000000; // 
-         11'h77f: data = 8'b00000000; // 
-         //code x78   
-         11'h780: data = 8'b00000000; // 
-         11'h781: data = 8'b00000000; // 
-         11'h782: data = 8'b00000000; // 
-         11'h783: data = 8'b00000000; // 
-         11'h784: data = 8'b00000000; // 
-         11'h785: data = 8'b11000011; // **    **
-         11'h786: data = 8'b01100110; //  **  **
-         11'h787: data = 8'b00111100; //   ****
-         11'h788: data = 8'b00011000; //    **
-         11'h789: data = 8'b00111100; //   ****
-         11'h78a: data = 8'b01100110; //  **  **
-         11'h78b: data = 8'b11000011; // **    **
-         11'h78c: data = 8'b00000000; // 
-         11'h78d: data = 8'b00000000; // 
-         11'h78e: data = 8'b00000000; // 
-         11'h78f: data = 8'b00000000; // 
-         //code x79   
-         11'h790: data = 8'b00000000; // 
-         11'h791: data = 8'b00000000; // 
-         11'h792: data = 8'b00000000; // 
-         11'h793: data = 8'b00000000; // 
-         11'h794: data = 8'b00000000; // 
-         11'h795: data = 8'b11000110; // **   **
-         11'h796: data = 8'b11000110; // **   **
-         11'h797: data = 8'b11000110; // **   **
-         11'h798: data = 8'b11000110; // **   **
-         11'h799: data = 8'b11000110; // **   **
-         11'h79a: data = 8'b11000110; // **   **
-         11'h79b: data = 8'b01111110; //  ******
-         11'h79c: data = 8'b00000110; //      **
-         11'h79d: data = 8'b00001100; //     **
-         11'h79e: data = 8'b11111000; // *****
-         11'h79f: data = 8'b00000000; // 
-         //code x7a   
-         11'h7a0: data = 8'b00000000; // 
-         11'h7a1: data = 8'b00000000; // 
-         11'h7a2: data = 8'b00000000; // 
-         11'h7a3: data = 8'b00000000; // 
-         11'h7a4: data = 8'b00000000; // 
-         11'h7a5: data = 8'b11111110; // *******
-         11'h7a6: data = 8'b11001100; // **  **
-         11'h7a7: data = 8'b00011000; //    **
-         11'h7a8: data = 8'b00110000; //   **
-         11'h7a9: data = 8'b01100000; //  **
-         11'h7aa: data = 8'b11000110; // **   **
-         11'h7ab: data = 8'b11111110; // *******
-         11'h7ac: data = 8'b00000000; // 
-         11'h7ad: data = 8'b00000000; // 
-         11'h7ae: data = 8'b00000000; // 
-         11'h7af: data = 8'b00000000; // 
-         //code x7b   
-         11'h7b0: data = 8'b00000000; // 
-         11'h7b1: data = 8'b00000000; // 
-         11'h7b2: data = 8'b00001110; //     ***
-         11'h7b3: data = 8'b00011000; //    **
-         11'h7b4: data = 8'b00011000; //    **
-         11'h7b5: data = 8'b00011000; //    **
-         11'h7b6: data = 8'b01110000; //  ***
-         11'h7b7: data = 8'b00011000; //    **
-         11'h7b8: data = 8'b00011000; //    **
-         11'h7b9: data = 8'b00011000; //    **
-         11'h7ba: data = 8'b00011000; //    **
-         11'h7bb: data = 8'b00001110; //     ***
-         11'h7bc: data = 8'b00000000; // 
-         11'h7bd: data = 8'b00000000; // 
-         11'h7be: data = 8'b00000000; // 
-         11'h7bf: data = 8'b00000000; // 
-         //code x7c   
-         11'h7c0: data = 8'b00000000; // 
-         11'h7c1: data = 8'b00000000; // 
-         11'h7c2: data = 8'b00011000; //    **
-         11'h7c3: data = 8'b00011000; //    **
-         11'h7c4: data = 8'b00011000; //    **
-         11'h7c5: data = 8'b00011000; //    **
-         11'h7c6: data = 8'b00000000; // 
-         11'h7c7: data = 8'b00011000; //    **
-         11'h7c8: data = 8'b00011000; //    **
-         11'h7c9: data = 8'b00011000; //    **
-         11'h7ca: data = 8'b00011000; //    **
-         11'h7cb: data = 8'b00011000; //    **
-         11'h7cc: data = 8'b00000000; // 
-         11'h7cd: data = 8'b00000000; // 
-         11'h7ce: data = 8'b00000000; // 
-         11'h7cf: data = 8'b00000000; // 
-         //code x7d   
-         11'h7d0: data = 8'b00000000; // 
-         11'h7d1: data = 8'b00000000; // 
-         11'h7d2: data = 8'b01110000; //  ***
-         11'h7d3: data = 8'b00011000; //    **
-         11'h7d4: data = 8'b00011000; //    **
-         11'h7d5: data = 8'b00011000; //    **
-         11'h7d6: data = 8'b00001110; //     ***
-         11'h7d7: data = 8'b00011000; //    **
-         11'h7d8: data = 8'b00011000; //    **
-         11'h7d9: data = 8'b00011000; //    **
-         11'h7da: data = 8'b00011000; //    **
-         11'h7db: data = 8'b01110000; //  ***
-         11'h7dc: data = 8'b00000000; // 
-         11'h7dd: data = 8'b00000000; // 
-         11'h7de: data = 8'b00000000; // 
-         11'h7df: data = 8'b00000000; // 
-         //code x7e   
-         11'h7e0: data = 8'b00000000; // 
-         11'h7e1: data = 8'b00000000; // 
-         11'h7e2: data = 8'b01110110; //  *** **
-         11'h7e3: data = 8'b11011100; // ** ***
-         11'h7e4: data = 8'b00000000; // 
-         11'h7e5: data = 8'b00000000; // 
-         11'h7e6: data = 8'b00000000; // 
-         11'h7e7: data = 8'b00000000; // 
-         11'h7e8: data = 8'b00000000; // 
-         11'h7e9: data = 8'b00000000; // 
-         11'h7ea: data = 8'b00000000; // 
-         11'h7eb: data = 8'b00000000; // 
-         11'h7ec: data = 8'b00000000; // 
-         11'h7ed: data = 8'b00000000; // 
-         11'h7ee: data = 8'b00000000; // 
-         11'h7ef: data = 8'b00000000; // 
-         //code x7f   
-         11'h7f0: data = 8'b00000000; // 
-         11'h7f1: data = 8'b00000000; // 
-         11'h7f2: data = 8'b00000000; // 
-         11'h7f3: data = 8'b00000000; // 
-         11'h7f4: data = 8'b00010000; //    *
-         11'h7f5: data = 8'b00111000; //   ***
-         11'h7f6: data = 8'b01101100; //  ** **
-         11'h7f7: data = 8'b11000110; // **   **
-         11'h7f8: data = 8'b11000110; // **   **
-         11'h7f9: data = 8'b11000110; // **   **
-         11'h7fa: data = 8'b11111110; // *******
-         11'h7fb: data = 8'b00000000; // 
-         11'h7fc: data = 8'b00000000; // 
-         11'h7fd: data = 8'b00000000; // 
-         11'h7fe: data = 8'b00000000; // 
-         11'h7ff: data = 8'b00000000; // 	 
-   endcase  
-   	       
-endmodule
\ No newline at end of file
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/pong_graph.v b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/pong_graph.v
deleted file mode 100644
index 55f27a8..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/pong_graph.v
+++ /dev/null
@@ -1,249 +0,0 @@
-`timescale 1ns / 1ps
-
-module pong_graph(
-		input wire clk, reset,
-		input wire [1:0] btn1,
-		input wire [1:0] btn2,
-		input wire [9:0] pix_x, pix_y,
-		input wire graph_still,
-		output reg miss, hit_left, hit_right,
-		output wire graph_on,
-		output reg [2:0] graph_rgb,
-		output reg [7:0] left_score, right_score
-	);
-
-	// define constant value here
-	localparam MAX_X = 640;
-	localparam MAX_Y = 480;
-	localparam BALL_SIZE = 8;
-	localparam BAR_SIZE = 108;
-	localparam BAR_V = 4;
-	localparam BAR_LEFT_X = 40;
-	localparam BAR_RIGHT_X = 600;
-	localparam BAR_WIDTH = 6;
-	localparam V_X = 3;
-	localparam V_X_N = -3;
-	localparam V_Y = 3;
-	localparam V_Y_N = -3;
-
-	// all about ball
-	reg [9:0] ball_x, ball_y;
-	wire [9:0] ball_x_next, ball_y_next;
-	wire [9:0] ball_right, ball_left, ball_top, ball_bottom;
-	reg [9:0] x_delta, x_delta_next;
-	reg [9:0] y_delta, y_delta_next;
-	
-	wire [2:0] ball_row, ball_col;
-	reg [7:0] ball_data;
-	
-	// all about the output rgb
-	wire bar_on, ball_on;
-	wire [2:0] bar_rgb, ball_rgb;
-	
-	// colors
-	assign bar_rgb = 3'b101;	// purple
-	assign ball_rgb = 3'b100;	// red
-	
-	// bar right & left
-	reg [9:0] bar_right, bar_right_next;
-	reg [9:0] bar_left, bar_left_next;
-	wire [9:0] bar_right_top, bar_right_bottom;
-	wire [9:0] bar_left_top, bar_left_bottom;
-	
-	// to judge wether added
-	reg added;
-
-	// refr_tick: 1-clock tick asserted at start of v-sync
-	//	   i.e., when the screen is refreshed (60 Hz)
-	assign refr_tick = (pix_y == 481) && (pix_x == 0);
-	
-	// keep refreshing all the assistant values
-	assign ball_right = ball_x + 4;
-	assign ball_left = ball_x - 3;
-	assign ball_top = ball_y - 3;
-	assign ball_bottom = ball_y + 4;
-	assign ball_x_next = (graph_still) ? MAX_X / 2 :
-						 (refr_tick) ? ball_x + x_delta : ball_x;
-	assign ball_y_next = (graph_still) ? MAX_Y / 2 :
-						 (refr_tick) ? ball_y + y_delta : ball_y;
-
-	assign ball_row = pix_y[2:0] - ball_top[2:0];
-	assign ball_col = pix_x[2:0] - ball_left[2:0];
-	assign ball_bit = ball_data[ball_col];
-
-	assign ball_on = (ball_left <= pix_x) && (pix_x <= ball_right)
-					 && (ball_top <= pix_y) && (pix_y <= ball_bottom)
-					 && ball_bit;
-
-	assign bar_right_top = bar_right - BAR_SIZE / 2;
-	assign bar_right_bottom = bar_right + BAR_SIZE / 2;
-	assign bar_left_top = bar_left - BAR_SIZE / 2;
-	assign bar_left_bottom = bar_left + BAR_SIZE / 2;
-	
-	assign bar_on = ((BAR_LEFT_X <= pix_x) && (pix_x <= BAR_LEFT_X + BAR_WIDTH)
-					 && (bar_right_top <= pix_y) && (pix_y <= bar_right_bottom))
-					 || ((BAR_RIGHT_X >= pix_x) && (pix_x >= BAR_RIGHT_X - BAR_WIDTH)
-					 && (bar_left_top <= pix_y) && (pix_y <= bar_left_bottom));
-
-	// provide the ball's data
-	always @*
-		case (ball_row)
-			3'h0: ball_data = 8'b00111100;	 //   ****
-			3'h1: ball_data = 8'b01111110;	 //  ******
-			3'h2: ball_data = 8'b11111111;	 // ********
-			3'h3: ball_data = 8'b11111111;	 // ********
-			3'h4: ball_data = 8'b11111111;	 // ********
-			3'h5: ball_data = 8'b11111111;	 // ********
-			3'h6: ball_data = 8'b01111110;	 //  ******
-			3'h7: ball_data = 8'b00111100;	 //   ****
-		endcase
-	
-	// move ball and deal reset
-	always @(posedge clk, posedge reset)
-	begin
-		if (reset)
-			begin
-				bar_right <= 0;
-				bar_left <= 0;
-				ball_x <= 0;
-				ball_y <= 0;
-				x_delta <= V_X;
-				y_delta <= V_Y;
-			end
-		else
-			begin
-				bar_right <= bar_right_next;
-				bar_left <= bar_left_next;
-				ball_x <= ball_x_next;
-				ball_y <= ball_y_next;
-				x_delta <= x_delta_next;
-				y_delta <= y_delta_next;
-			end
-	end
-
-	// calc the position of bar
-	always @*
-	begin
-		bar_right_next = bar_right;
-		if (graph_still)
-			bar_right_next = MAX_Y / 2;
-		else if (refr_tick)
-			if (btn1[1] & (bar_right_bottom < (MAX_Y - 1 - BAR_V)))
-				bar_right_next = bar_right + BAR_V;
-			else if (btn1[0] & (bar_right_top > BAR_V)) 
-				bar_right_next = bar_right - BAR_V;
-
-		bar_left_next = bar_left;
-		if (graph_still)
-			bar_left_next = MAX_Y / 2;
-		else if (refr_tick)
-			if (btn2[1] & (bar_left_bottom < (MAX_Y - 1 - BAR_V)))
-				bar_left_next = bar_left + BAR_V;
-			else if (btn2[0] & (bar_left_top > BAR_V)) 
-				bar_left_next = bar_left - BAR_V;
-	end
-
-	// deal with the ball's movement
-	always @(posedge refr_tick, posedge reset)
-	  if (reset) begin
-		hit_left = 1'b0;
-		hit_right = 1'b0;
-		miss = 1'b0;
-		x_delta_next = V_X;
-		y_delta_next = V_Y;
-		right_score = 8'b0;
-		left_score = 8'b0;
-		added = 0;
-	  end else begin
-		hit_left = 1'b0;
-		hit_right = 1'b0;
-		miss = 1'b0;
-		x_delta_next = x_delta;
-		y_delta_next = y_delta;
-		if (graph_still)
-			begin
-				x_delta_next = V_X;
-				y_delta_next = V_Y;
-				hit_right = 1'b0;
-				hit_left = 1'b0;
-				miss = 1'b0;
-				right_score = 8'b0;
-				left_score = 8'b0;
-				added = 0;
-			end
-		else if (ball_top <= 5)
-			begin
-				y_delta_next = V_Y;
-				hit_right = 1'b0;
-				hit_left = 1'b0;
-				added = 0;
-			end
-		else if (ball_bottom >= MAX_Y - 5)
-			begin
-				y_delta_next = V_Y_N;
-				hit_right = 1'b0;
-				hit_left = 1'b0;
-				added = 0;
-			end
-		else if (BAR_LEFT_X <= ball_left && BAR_LEFT_X + BAR_WIDTH >= ball_left - 1
-				&& ball_top - bar_right + BAR_SIZE / 2 > 0 && bar_right - ball_top + BAR_SIZE / 2 > 0)
-			begin
-				hit_left = 1'b1;
-				hit_right = 1'b0;
-				x_delta_next = V_X;
-				if(added == 0)
-				begin
-					if(left_score[3:0] == 4'b1001)
-					begin
-						left_score[3:0] = 4'b0000;
-						left_score[7:4] = left_score[7:4] + 1;
-					end
-					else
-						left_score[3:0] = left_score[3:0] + 1;
-				end
-				added = 1;
-			end
-		else if (BAR_RIGHT_X >= ball_right && BAR_RIGHT_X - BAR_WIDTH <= ball_right + 1
-				&& ball_top - bar_left + BAR_SIZE / 2 > 0 && bar_left - ball_top + BAR_SIZE / 2 > 0)
-			begin
-				hit_right = 1'b1;
-				hit_left = 1'b0;
-				x_delta_next = V_X_N;
-				if(added == 0)
-				begin
-					if(right_score[3:0] == 4'h9)
-					begin
-						right_score[3:0] = 4'h0;
-						right_score[7:4] = right_score[7:4] + 1;
-					end
-					else
-						right_score[3:0] = right_score[3:0] + 1;
-				end
-				added = 1;
-			end
-		else if (ball_right >= MAX_X - 10 || ball_right <= 10)
-			begin
-				added = 0;
-				miss = 1'b1;
-				hit_right = 1'b0;
-				hit_left = 1'b0;
-				right_score = 8'b0;
-				left_score = 8'b0;
-			end
-	  end
-
-	// assign rgb to the correct color
-	always @* 
-	begin
-		if (bar_on)
-			graph_rgb = bar_rgb;
-		else if (ball_on)
-			graph_rgb = ball_rgb;
-		else
-			graph_rgb = 3'b000;
-	end
-
-	// decide wether need to display
-	assign graph_on =  bar_on | ball_on;
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/text_graph.v b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/text_graph.v
deleted file mode 100644
index e400fec..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/text_graph.v
+++ /dev/null
@@ -1,51 +0,0 @@
-module text_graph(
-		input wire clk,
-		input wire [3:0] left_high, left_low,
-		input wire [3:0] right_high, right_low,
-		input wire [9:0] pix_x, pix_y,
-		output wire text_on,
-		output reg [2:0] text_rgb
-    );
-	wire [10:0] rom_add;
-	wire [3:0] row_add;
-	wire [2:0] bit_add;
-	wire [7:0] temp_data;
-	reg [7:0] char_add;
-	wire bit_color;
-	
-	font_rom rom(.clk(clk),.addr(rom_add),.data(temp_data));
-	
-	assign text_on = (pix_y[9:5]==0) && (pix_x[9:4] >= 9 ) && (pix_x[9:4] < 24);
-	assign row_add = pix_y[4:1];
-	assign bit_add = pix_x[3:1];
-	always @*
-		case(pix_x[9:4])
-			6'b001001: char_add = 7'h53;
-			6'b001010: char_add = 7'h63;
-			6'b001011: char_add = 7'h6f;
-			6'b001100: char_add = 7'h72;
-			6'b001101: char_add = 7'h65;
-			6'b001110: char_add = 7'h3a;
-			6'b001111: char_add = 7'h00;
-			6'b010000: char_add = {3'b011,left_high};
-			6'b010001: char_add = {3'b011,left_low};
-			6'b010010: char_add = 7'h00;
-			6'b010011: char_add = 7'h2d;
-			6'b010100: char_add = 7'h2d;
-			6'b010101: char_add = 7'h00;
-			6'b010110: char_add = {3'b011,right_high};
-			6'b010111: char_add = {3'b011,right_low};
-			6'b011000: char_add = 7'h00;
-		endcase
-
-	always @*
-	begin
-		text_rgb = 3'b110;
-		if(text_on && bit_color)
-			text_rgb = 3'b000;
-	end
-	
-	assign rom_add = {char_add, row_add};
-	assign bit_color = temp_data[~bit_add];
-	
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/top.v b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/top.v
deleted file mode 100644
index 9d37d64..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/top.v
+++ /dev/null
@@ -1,119 +0,0 @@
-`timescale 1ns / 1ps
-
-module top(
-		input wire clk, reset,
-		input wire [1:0] btn1,
-		input wire [1:0] btn2,
-		output wire hsync, vsync,
-		output wire [2:0] rgb
-	);
-
-
-	// define state
-	localparam  [1:0]
-	new	 = 2'b00,	// new game
-	play	= 2'b01,	// playing
-	over	= 2'b10;	// game over
-
-	reg [1:0] state, state_next;
-	wire [9:0] pixel_x, pixel_y;
-	wire video_on, pixel_tick, graph_on, miss;
-	wire [2:0] graph_rgb;
-	reg [2:0] rgb_now, rgb_next;
-	reg graph_still, timer_start;			// graph_still: graph still
-	wire [1:0] btn1_out, btn2_out;
-	wire hit_left, hit_right;
-	wire [7:0] left_s, right_s;
-	wire text_on;
-	wire [2:0] text_rgb;
-	
-	initial begin
-		state = 2'b00;		// state: new
-		rgb_now = 0;
-		graph_still = 1'b1;
-	end
-
-	debounce p0(clk, btn1[0], btn1_out[0]);		// debounce for btns
-	debounce p1(clk, btn1[1], btn1_out[1]);
-	debounce p2(clk, btn2[0], btn2_out[0]);
-	debounce p3(clk, btn2[1], btn2_out[1]);
-
-	text_graph text
-		(.clk(clk), .left_high(left_s[7:4]), .left_low(left_s[3:0]),
-		.right_high(right_s[7:4]), .right_low(right_s[3:0]), .pix_x(pixel_x),
-		.pix_y(pixel_y), .text_on(text_on), .text_rgb(text_rgb));
-	
-	vga_sync vsync_unit
-		(.clk(clk), .reset(reset), .hsync(hsync), .vsync(vsync),
-		.video_on(video_on), .p_tick(pixel_tick),
-		.pixel_x(pixel_x), .pixel_y(pixel_y));
-
-	pong_graph graph_unit
-	  (.clk(clk), .reset(reset), .btn1(btn1_out), .btn2(btn2_out),
-	   .pix_x(pixel_x), .pix_y(pixel_y),
-	   .graph_still(graph_still), .miss(miss),.hit_left(hit_left),.hit_right(hit_right),
-	   .graph_on(graph_on), .graph_rgb(graph_rgb), .left_score(left_s),.right_score(right_s));
-
-
-	always @(posedge clk)
-	begin
-		if (reset)
-			begin
-				state <= new;
-				rgb_now <= 0;
-			end
-		else
-			begin
-				state <= state_next;
-				if (pixel_tick)
-					rgb_now <= rgb_next;
-			end
-	end
-
-	always @*
-	begin
-		graph_still = 1'b1;
-		state_next = state;
-		case (state)
-			new:
-				begin
-					// any button pressed the game start
-					if ((btn1_out != 2'b00) || (btn2_out != 2'b00))
-					begin
-						state_next = play;
-					end
-				end
-			play:
-				begin
-					graph_still = 1'b0;
-					// if any ball is missed, your game is over.
-					if (miss)
-					begin
-						state_next = over;
-					end
-				end
-			over:
-				begin
-					// may add more features here
-					state_next = new;
-				end
-		endcase
-	end
-
-	always @*
-	begin
-		if (~video_on)
-			rgb_next = "000"; // blank the edge/retrace
-		else
-			// the priority is defined here
-			if(graph_on)
-			   rgb_next = graph_rgb;
-			else if (text_on)  // display graph
-				rgb_next = text_rgb;
-			else 
-				rgb_next = 3'b110; // yellow background
-	end
-
-	assign rgb = rgb_now;	// assign rgb register to output
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/vga_sync.v b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/vga_sync.v
deleted file mode 100644
index 9b5cc54..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/rtl/vga_sync.v
+++ /dev/null
@@ -1,84 +0,0 @@
-module vga_sync
-   (
-    input wire clk, reset,
-    output wire hsync, vsync, video_on, p_tick,
-    output wire [9:0] pixel_x, pixel_y
-   );
-
-   localparam HD = 640; // horizontal display area
-   localparam HF = 48 ; // h. front (left) border
-   localparam HB = 16 ; // h. back (right) border
-   localparam HR = 96 ; // h. retrace
-   localparam VD = 480; // vertical display area
-   localparam VF = 10;  // v. front (top) border
-   localparam VB = 33;  // v. back (bottom) border
-   localparam VR = 2;   // v. retrace
-
-   reg point;
-   wire point_next;
-   reg [9:0] h_count, h_count_next;
-   reg [9:0] v_count, v_count_next;
-   reg v_sync_reg, h_sync_reg;
-   wire v_sync_next, h_sync_next;
-   wire h_end, v_end, pixel_tick;
-
-   
-   always @(posedge clk, posedge reset)
-      if (reset)
-         begin
-            point <= 1'b0;
-            v_count <= 0;
-            h_count <= 0;
-            v_sync_reg <= 1'b0;
-            h_sync_reg <= 1'b0;
-         end
-      else
-         begin
-            point <= point_next;
-            v_count <= v_count_next;
-            h_count <= h_count_next;
-            v_sync_reg <= v_sync_next;
-            h_sync_reg <= h_sync_next;
-         end
-
-   assign point_next = ~point;
-   assign pixel_tick = point;
-
-   assign h_end = (h_count==(HD+HF+HB+HR-1));
-   assign v_end = (v_count==(VD+VF+VB+VR-1));
-
-   always @*
-      if (pixel_tick)  // 25 MHz pulse
-         if (h_end)
-			begin
-
-            h_count_next = 0;
-				if(v_end)
-					v_count_next = 0;
-				else
-					v_count_next = v_count + 1;
-			end
-         else begin
-            h_count_next = h_count + 1;
-	    v_count_next = v_count;
-	 end
-      else
-		begin
-         h_count_next = h_count;
-			v_count_next = v_count;
-		end
-
-   assign h_sync_next = (h_count >=(HD+HB) &&
-                         h_count <=(HD+HB+HR-1));
-   assign v_sync_next = (v_count >=(VD+VB) &&
-                         v_count <=(VD+VB+VR-1));
-
-   assign video_on = (h_count<HD) && (v_count<VD);
-
-   assign hsync = h_sync_reg;
-   assign vsync = v_sync_reg;
-   assign pixel_x = h_count;
-   assign pixel_y = v_count;
-   assign p_tick = pixel_tick;
-
-endmodule
diff --git a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/sim/bench.v b/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/sim/bench.v
deleted file mode 100644
index b2da110..0000000
--- a/SVIncCompil/Testcases/YosysBigSim/verilog-pong/slpp_unit/work/sim/bench.v
+++ /dev/null
@@ -1,108 +0,0 @@
-
-// To create a GIF animation from the generated images:
-// convert frame_*.ppm pong.gif
-
-
-
-module testbench;
-
-reg clk, reset;
-reg [1:0] btn1;
-reg [1:0] btn2;
-wire hsync, vsync;
-wire [2:0] rgb;
-
-top UUT (
-	clk,
-	reset,
-	btn1,
-	btn2,
-	hsync,
-	vsync,
-	rgb
-);
-
-initial begin
-	clk <= 0;
-	#100;
-	forever begin
-		clk <= ~clk;
-		#50;
-	end
-end
-
-initial begin
-	btn1 <= 2'b00;
-	btn2 <= 2'b00;
-	reset <= 1;
-	repeat(5) @(posedge clk);
-	btn2 <= 2'b01;
-	repeat(5) @(posedge clk);
-	reset <= 0;
-end
-
-integer x, y, z, idx, fd;
-reg [128*8-1:0] filename;
-reg [2:0] framebuffer [0:700*500-1];
-reg last_hsync, last_vsync;
-reg [63:0] hash;
-
-always @(posedge clk) begin
-	last_hsync <= hsync;
-	last_vsync <= vsync;
-	if (reset) begin
-		x = 96;
-		y = 12;
-		z = 0;
-		for (idx = 0; idx < 700*500; idx=idx+1)
-			framebuffer[idx] = 0;
-	end else
-	if (hsync) begin
-		if (!last_hsync) begin
-			x = 0;
-			y = y + 1;
-			if (z == 0 && y == 13)
-				$write("Frame %3d .", z);
-			if (z != 0 && y == 1)
-				$write("Frame %3d ", z);
-			if (y % 10 == 9) begin
-				$write(".");
-				$fflush;
-			end
-		end
-	end else
-	if (vsync) begin
-		if (!last_vsync)
-		begin
-			hash = 0;
-			for (idx=0; idx < 700*500; idx = idx+1)
-				hash = framebuffer[idx] + (hash << 6) + (hash << 16) - hash;
-			$write(" %016x", hash);
-
-
-			$write("\n");
-
-			x = 0;
-			y = 0;
-			z = z + 1;
-			for (idx = 0; idx < 700*500; idx=idx+1)
-				framebuffer[idx] = 0;
-
-			if (z == 3)
-				$finish;
-		end
-	end else begin
-		x <= x + 1;
-		if (x % 2 == 0 && 5 <= x && x < 1405 && 5 <= y && y < 505) begin
-			idx = (x-5)/2 + 700*(y-5);
-			framebuffer[idx] = rgb;
-		end
-	end
-end
-
-initial begin
-	// $dumpfile("bench.vcd");
-	// $dumpvars(0, testbench);
-end
-
-endmodule