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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_all/surelog.log.

[WARNI:CM0010] Command line argument "-full64" ignored.

[WARNI:CM0010] Command line argument "-PP" ignored.

[WARNI:CM0010] Command line argument "-notice" ignored.

[WARNI:CM0010] Command line argument "-line" ignored.

[NOTE :CM0009] Command line argument "+lint=all,noVCDE,noUI" ignored.

[NOTE :CM0009] Command line argument "+v2k" ignored.

[WARNI:CM0010] Command line argument "-quiet" ignored.

[WARNI:CM0010] Command line argument "-debug_pp" ignored.

[WARNI:CM0010] Command line argument "-Mdirectory=sim/csrc" ignored.

[NOTE :CM0009] Command line argument "+vc+list" ignored.

[WARNI:CM0010] Command line argument "-CC" ignored.

[WARNI:CM0010] Command line argument "-std=c++11" ignored.

[INFO :CM0024] Executing with 4 threads.

[WARNI:CM0005] Include path "/include" does not exist.

[NOTE :PP0105] src/main/verilog/vscale_ctrl_constants.vh:42 Multiply defined macro "MEM_TYPE_WIDTH",
               src/main/verilog/vscale_ctrl_constants.vh:33 previous definition.

[INFO :CM0029] Using global timescale: "1ns/10ps".

[INFO :CP0300] Compilation...

[INFO :CP0303] src/main/verilog/vscale_PC_mux.v:5 Compile module "work@vscale_PC_mux".

[INFO :CP0303] src/main/verilog/vscale_core.v:5 Compile module "work@vscale_core".

[INFO :CP0303] src/main/verilog/vscale_alu.v:5 Compile module "work@vscale_alu".

[INFO :CP0303] src/main/verilog/vscale_csr_file.v:5 Compile module "work@vscale_csr_file".

[INFO :CP0303] src/main/verilog/vscale_ctrl.v:6 Compile module "work@vscale_ctrl".

[INFO :CP0303] src/test/verilog/vscale_dp_hasti_sram.v:2 Compile module "work@vscale_dp_hasti_sram".

[INFO :CP0303] src/main/verilog/vscale_hasti_bridge.v:4 Compile module "work@vscale_hasti_bridge".

[INFO :CP0303] src/test/verilog/vscale_hex_tb.v:3 Compile module "work@vscale_hex_tb".

[INFO :CP0303] src/main/verilog/vscale_pipeline.v:7 Compile module "work@vscale_pipeline".

[INFO :CP0303] src/main/verilog/vscale_mul_div.v:4 Compile module "work@vscale_mul_div".

[INFO :CP0303] src/main/verilog/vscale_regfile.v:2 Compile module "work@vscale_regfile".

[INFO :CP0303] src/main/verilog/vscale_imm_gen.v:5 Compile module "work@vscale_imm_gen".

[INFO :CP0303] src/test/verilog/vscale_sim_top.v:4 Compile module "work@vscale_sim_top".

[INFO :CP0303] src/main/verilog/vscale_src_a_mux.v:5 Compile module "work@vscale_src_a_mux".

[INFO :CP0303] src/main/verilog/vscale_src_b_mux.v:5 Compile module "work@vscale_src_b_mux".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".

[NOTE :CP0309] src/main/verilog/vscale_PC_mux.v:13 Implicit port type (wire) for "PC_PIF".

[NOTE :CP0309] src/main/verilog/vscale_ctrl.v:20 Implicit port type (wire) for "bypass_rs1",
there are 3 more instances of this message.

[NOTE :CP0309] src/test/verilog/vscale_sim_top.v:8 Implicit port type (wire) for "htif_pcr_req_ready",
there are 2 more instances of this message.

[NOTE :CP0309] src/test/verilog/vscale_dp_hasti_sram.v:15 Implicit port type (wire) for "p0_hrdata",
there are 5 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_mul_div.v:8 Implicit port type (wire) for "req_ready",
there are 2 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_core.v:10 Implicit port type (wire) for "imem_haddr",
there are 22 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_hasti_bridge.v:5 Implicit port type (wire) for "haddr",
there are 10 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_pipeline.v:14 Implicit port type (wire) for "imem_addr",
there are 8 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_csr_file.v:15 Implicit port type (wire) for "illegal_access",
there are 6 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_regfile.v:7 Implicit port type (wire) for "rd1",
there are 1 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] src/test/verilog/vscale_hex_tb.v:3 Top level module "work@vscale_hex_tb".

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 5.

[NOTE :EL0510] Nb instances: 16.

[NOTE :EL0511] Nb leaf instances: 2.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 10
[   NOTE] : 19

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*   End SURELOG SVerilog Compiler/Linter   *
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5.22user 0.09system 0:01.79elapsed 296%CPU (0avgtext+0avgdata 114480maxresident)k
0inputs+2848outputs (0major+31046minor)pagefaults 0swaps