********************************************
*  SURELOG System Verilog Compiler/Linter  *
********************************************

[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PP0101] dspmac_16_40_tb.v:4 Cannot open include file "constants.vams".

[WARNI:PA0205] latch.v:7 No timescale set for "latch".

[WARNI:PA0205] crc32.v:8 No timescale set for "crc32".

[WARNI:PA0205] pwm256_tb.v:6 No timescale set for "tb".

[WARNI:PA0205] cic5.v:6 No timescale set for "cic5".

[WARNI:PA0205] pwm256.v:6 No timescale set for "pwm256".

[INFO :CP0300] Compilation...

[INFO :CP0303] cic5.v:6 Compile module "work@cic5".

[INFO :CP0303] latch.v:7 Compile module "work@latch".

[INFO :CP0303] crc32.v:8 Compile module "work@crc32".

[INFO :CP0303] pwm256.v:6 Compile module "work@pwm256".

[INFO :CP0303] pwm256_tb.v:6 Compile module "work@tb".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".

[NOTE :CP0309] crc32.v:8 Implicit port type (wire) for "dout".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] latch.v:7 Top level module "work@latch".

[NOTE :EL0503] crc32.v:8 Top level module "work@crc32".

[NOTE :EL0503] pwm256_tb.v:6 Top level module "work@tb".

[WARNI:EL0505] cic5_tb.v:8 Multiply defined module "work@tb",
               pwm256_tb.v:6 previous definition,
               constants.vams:2 previous definition.

[NOTE :EL0504] Multiple top level modules in design.

[NOTE :EL0508] Nb Top level modules: 3.

[NOTE :EL0509] Max instance depth: 2.

[NOTE :EL0510] Nb instances: 4.

[NOTE :EL0511] Nb leaf instances: 0.

[  FATAL] : 0
[  ERROR] : 1
[WARNING] : 6
[   NOTE] : 9

********************************************
*   End SURELOG SVerilog Compiler/Linter   *
********************************************

3.19user 0.06system 0:01.04elapsed 311%CPU (0avgtext+0avgdata 66208maxresident)k
0inputs+608outputs (0major+14277minor)pagefaults 0swaps