Black Parrot Back End

The Back End (BE) comprises the execution engine for RISC-V instructions in a BlackParrot multicore processor. It contains the true architectural state for the processor and logically controls the FE's speculative execution.

Diagrams for the BE blocks can be found here. (Diagrams are WIP as of 1/30/2019)

Back End (BE)

The file bp_be_top.v defines the top level Back End module. This module is instantiated once per core in a BlackParrot multicore processor. This module consists of three major components: the Calculator and the Checker and the MMU. The Calculator is responsible for performing RISC-V instructions as well as detecting exception conditions. The Checker is reponsible for scheduling instruction execution by interfacing with the FE, preventing hazards from affecting correctness by determining the true next PC, gating incorrect PCs from entering the pipeline, as well as monitoring dependency information from the Calculator. The MMU handles virtual address translation and L1 caching, as well as interface with the ME.

Parameters

  • vaddr_width_p - virtual address width

  • paddr_width_p - physical address width

  • branch_metadata_fwd_width_p - branch prediction metadata from the FE. BE does not modify or inspect this data

  • num_lce_p - number of LCEs in the system

  • num_cce_p - number of CCEs in the system

  • num_mem_p - number of memory units per CCE in the system (deprecated)

  • coh_states_p - number of coherence states in the system (deprecated)

  • lce_assoc_p - associativity of the LCEs

  • lce_sets_p - number of sets in each LCE

  • cce_block_size_in_bytes_p - number of bytes per cache block in the CCEs

Interfaces

The Back End instantiates the L1 Data Cache, which sends messages to and from the LCEs and CCEs in the processor. Outbound messages are routed to the Coherence Network, which then delivers them to either a CCE or another LCE, depending on the type of message. Inbound messages are delivered to the LCEs and may come from either the CCE or another LCE.

  • LCE to CCE - ready->valid (ME is helpful consumer)
  • CCE to LCE - ready->valid (ME is demanding producer)
  • LCE to LCE (inbound) - ready->valid (ME is helpful consumer)
  • LCE to LCE (outbound) - ready->valid (ME is demanding producer)

The BE receives instruction / PC pairs (or FE exceptions) from the FE. The BE also logically controls the FE, sending redirection signals on mispredict or reset, for example.

  • FE to BE - valid->ready (BE is a demanding consumer)
  • BE to FE - ready->valid (BE is a demanding producer)

Note: we use the terminology defined in the BaseJump STL paper.

References

  1. BaseJump STL