| commit | 509d74c8274136d651c20786720d09291a7e6fc0 | [log] [tgz] |
|---|---|---|
| author | Alain <alainmarcel@yahoo.com> | Fri Nov 22 00:09:17 2019 -0800 |
| committer | Alain <alainmarcel@yahoo.com> | Fri Nov 22 00:09:59 2019 -0800 |
| tree | 517c9d241a051acf9aadd83b273dcdc0539d8337 | |
| parent | a2bca728a49ae571d9e4c5859468aaacef5604b7 [diff] |
Remove Antlr dependancy from public API, make Python optional Signed-off-by: Alain <alainmarcel@yahoo.com>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models.
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALLmake make install (/usr/local/bin and /usr/local/lib/surelog by default, use DESTDIR= for alternative locations)
For more build/test options and system requirements for building see src/README file.
The executable is located here (If not installed in:
STANDARD VERILOG COMMAND LINE:
FLOWS OPTIONS:
TRACES OPTIONS:
OUTPUT OPTIONS:
RETURN CODE