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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PA0207] rtl/a23_decode.v:174 Syntax error: mismatched input 'type' expecting {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier},
reg     [3:0]          type;
                       ^-- ./slpp_unit/work/rtl/a23_decode.v:518 col:23.

[WARNI:PA0205] rtl/a23_barrel_shift.v:42 No timescale set for "a23_barrel_shift".

[WARNI:PA0205] rtl/a23_decompile.v:44 No timescale set for "a23_decompile".

[WARNI:PA0205] rtl/a23_fetch.v:45 No timescale set for "a23_fetch".

[WARNI:PA0205] rtl/a23_alu.v:43 No timescale set for "a23_alu".

[WARNI:PA0205] rtl/a23_barrel_shift_fpga.v:46 No timescale set for "a23_barrel_shift_fpga".

[WARNI:PA0205] rtl/a23_coprocessor.v:41 No timescale set for "a23_coprocessor".

[WARNI:PA0205] rtl/a23_core.v:43 No timescale set for "a23_core".

[WARNI:PA0205] rtl/a23_multiply.v:56 No timescale set for "a23_multiply".

[WARNI:PA0205] rtl/a23_register_bank.v:44 No timescale set for "a23_register_bank".

[WARNI:PA0205] rtl/a23_execute.v:45 No timescale set for "a23_execute".

[WARNI:PA0205] rtl/generic_sram_byte_en.v:43 No timescale set for "generic_sram_byte_en".

[WARNI:PA0205] rtl/a23_wishbone.v:58 No timescale set for "a23_wishbone".

[WARNI:PA0205] rtl/generic_sram_line_en.v:42 No timescale set for "generic_sram_line_en".

[WARNI:PA0205] rtl/a23_decode.v:43 No timescale set for "a23_decode".

[WARNI:PA0205] sim/bench.v:2 No timescale set for "testbench".

[WARNI:PA0205] rtl/a23_cache.v:47 No timescale set for "a23_cache".

[WARNI:PA0205] rtl/a23_ram_register_bank.v:44 No timescale set for "a23_ram_register_bank".

[INFO :CP0300] Compilation...

[INFO :CP0303] rtl/a23_alu.v:43 Compile module "work@a23_alu".

[INFO :CP0303] rtl/a23_barrel_shift.v:42 Compile module "work@a23_barrel_shift".

[INFO :CP0303] rtl/a23_barrel_shift_fpga.v:46 Compile module "work@a23_barrel_shift_fpga".

[INFO :CP0303] rtl/a23_cache.v:47 Compile module "work@a23_cache".

[INFO :CP0303] rtl/a23_coprocessor.v:41 Compile module "work@a23_coprocessor".

[INFO :CP0303] rtl/a23_execute.v:45 Compile module "work@a23_execute".

[INFO :CP0303] rtl/a23_decode.v:43 Compile module "work@a23_decode".

[INFO :CP0303] rtl/a23_core.v:43 Compile module "work@a23_core".

[INFO :CP0303] rtl/a23_decompile.v:44 Compile module "work@a23_decompile".

[INFO :CP0303] rtl/a23_ram_register_bank.v:44 Compile module "work@a23_ram_register_bank".

[INFO :CP0303] rtl/a23_fetch.v:45 Compile module "work@a23_fetch".

[INFO :CP0303] rtl/a23_register_bank.v:44 Compile module "work@a23_register_bank".

[INFO :CP0303] rtl/a23_wishbone.v:58 Compile module "work@a23_wishbone".

[INFO :CP0303] rtl/generic_sram_line_en.v:42 Compile module "work@generic_sram_line_en".

[INFO :CP0303] sim/bench.v:2 Compile module "work@testbench".

[INFO :CP0303] rtl/a23_multiply.v:56 Compile module "work@a23_multiply".

[INFO :CP0303] rtl/generic_sram_byte_en.v:43 Compile module "work@generic_sram_byte_en".

[NOTE :CP0309] rtl/a23_alu.v:51 Implicit port type (wire) for "o_out",
there are 1 more instances of this message.

[NOTE :CP0309] rtl/a23_coprocessor.v:58 Implicit port type (wire) for "o_cache_enable",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/a23_execute.v:63 Implicit port type (wire) for "o_address_nxt",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/a23_register_bank.v:71 Implicit port type (wire) for "o_rm",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/a23_barrel_shift.v:50 Implicit port type (wire) for "o_out",
there are 1 more instances of this message.

[NOTE :CP0309] rtl/a23_core.v:53 Implicit port type (wire) for "o_wb_adr",
there are 5 more instances of this message.

[NOTE :CP0309] rtl/a23_fetch.v:54 Implicit port type (wire) for "o_read_data",
there are 7 more instances of this message.

[NOTE :CP0309] rtl/a23_wishbone.v:70 Implicit port type (wire) for "o_stall".

[NOTE :CP0309] rtl/a23_barrel_shift_fpga.v:54 Implicit port type (wire) for "o_out",
there are 1 more instances of this message.

[NOTE :CP0309] rtl/a23_decode.v:81 Implicit port type (wire) for "o_rm_sel_nxt",
there are 8 more instances of this message.

[NOTE :CP0309] rtl/a23_multiply.v:65 Implicit port type (wire) for "o_out",
there are 1 more instances of this message.

[NOTE :CP0309] rtl/a23_cache.v:98 Implicit port type (wire) for "o_read_data",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/a23_ram_register_bank.v:69 Implicit port type (wire) for "o_rm",
there are 4 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] rtl/a23_decompile.v:44 Top level module "work@a23_decompile".

[NOTE :EL0503] rtl/a23_barrel_shift_fpga.v:46 Top level module "work@a23_barrel_shift_fpga".

[NOTE :EL0503] sim/bench.v:2 Top level module "work@testbench".

[NOTE :EL0503] rtl/a23_ram_register_bank.v:44 Top level module "work@a23_ram_register_bank".

[NOTE :EL0504] Multiple top level modules in design.

[ERROR:EL0514] rtl/a23_decode.v:806 Undefined variable: instruction.

[ERROR:EL0514] rtl/a23_decode.v:832 Undefined variable: instruction.

[NOTE :EL0508] Nb Top level modules: 4.

[NOTE :EL0509] Max instance depth: 6.

[NOTE :EL0510] Nb instances: 23.

[NOTE :EL0511] Nb leaf instances: 3.

[  FATAL] : 0
[  ERROR] : 3
[WARNING] : 17
[   NOTE] : 22

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*   End SURELOG SVerilog Compiler/Linter   *
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10.39user 0.25system 0:03.39elapsed 313%CPU (0avgtext+0avgdata 199904maxresident)k
816inputs+1392outputs (0major+47379minor)pagefaults 0swaps