| commit | 6a843e348986deef983b3a6db7761a6eb021a19b | [log] [tgz] |
|---|---|---|
| author | Alain <alainmarcel@yahoo.com> | Thu Nov 28 20:09:43 2019 -0800 |
| committer | Alain <alainmarcel@yahoo.com> | Thu Nov 28 20:10:02 2019 -0800 |
| tree | f6c1b344e82ed11b67865af21fbd96638d45d4cc | |
| parent | d7edc3b49a4ae300828bb1f7e41388e283af74c6 [diff] |
test update Signed-off-by: Alain <alainmarcel@yahoo.com>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models.
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALLmake make install (/usr/local/bin and /usr/local/lib/surelog by default, use DESTDIR= for alternative locations)
For more build/test options and system requirements for building see src/README file.
The executable is located here (If not installed in:
STANDARD VERILOG COMMAND LINE:
FLOWS OPTIONS:
TRACES OPTIONS:
OUTPUT OPTIONS:
RETURN CODE
The file slformatmsg.py illustrates how messages can be reformated.
The file src/API/slSV3_1aPythonListener.py illustrates how a listener can be created to listen to the Parser AST.
A simple example of creating a new error message and generating errors can be found here: python_listener.py
A simple example for design-level data model exploration can be found here: myscriptPerDesign.py
The complete Python API is described in the following files: SLAPI.h vobjecttypes
Waivers can be installed in slwaivers.py files in the execution directory or install directory /usr/local/lib/surelog/python
src/README file.