| commit | 6cb314b221306a9565407d3fcee783d7948873d6 | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Wed Nov 20 10:35:03 2019 -0800 |
| committer | Henner Zeller <h.zeller@acm.org> | Wed Nov 20 10:35:57 2019 -0800 |
| tree | 9e86c68768acd87b0a37ac56ed833cfcd7c6755e | |
| parent | 4ca2f7a6a1ebd89ad40fd1016c8c42ebe1974e29 [diff] |
Work around writable wchar_t* in Py_SetProgramName() pre 3.7 Fixes #94 Signed-off-by: Henner Zeller <h.zeller@acm.org>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALLmake make install (/usr/local/bin and /usr/local/lib/surelog by default, use DESTDIR= for alternative locations)
For more build/test options and system requirements for building see src/README file.
The executable is located here (If not installed in:
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
default_nettype in pre-processor's output
RETURN CODE