| commit | 91fe1f0c7917e5cce5de18f26f90ba0e98f25fb6 | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Mon Nov 18 21:11:13 2019 -0800 |
| committer | Henner Zeller <h.zeller@acm.org> | Mon Nov 18 21:11:13 2019 -0800 |
| tree | f86ecab2e880c555144226e6b83cc8444694bb3a | |
| parent | dc9e31ae8b53ec16b3ecb406d6a9b9103b596931 [diff] |
Include of files that are in the same directory should also be relative to the toplevel directory. That makes reasioning about code less ambiguous, is easier to refactor and thus is also recommended practice in https://google.github.io/styleguide/cppguide.html#Names_and_Order_of_Includes Signed-off-by: Henner Zeller <h.zeller@acm.org>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.
The executable is located here:
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
`default_nettype in pre-processor's output