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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ../../build/tests/SimpleTask/slpp_all/surelog.log.

[NOTE :PP0105] top_1.v:4 Multiply defined macro "append",
               top.v:4 previous definition.

[NOTE :PP0105] top_1.v:6 Multiply defined macro "append",
               top.v:4 previous definition.

[NOTE :PP0105] top_1.v:9 Multiply defined macro "my_macro",
               top.v:6 previous definition.

[NOTE :PP0105] top_2.v:4 Multiply defined macro "append",
               top_1.v:6 previous definition.

[NOTE :PP0105] top_2.v:5 Multiply defined macro "append",
               top_1.v:6 previous definition.

[NOTE :PP0105] top_2.v:6 Multiply defined macro "my_macro",
               top.v:6 previous definition.

[NOTE :PP0105] top_3.v:4 Multiply defined macro "append",
               top_2.v:5 previous definition.

[NOTE :PP0105] top_3.v:5 Multiply defined macro "append",
               top_2.v:5 previous definition.

[NOTE :PP0105] top_3.v:6 Multiply defined macro "my_macro",
               top.v:6 previous definition.

[NOTE :PP0105] top_4.v:4 Multiply defined macro "append",
               top_3.v:5 previous definition.

[NOTE :PP0105] top_4.v:5 Multiply defined macro "append",
               top_3.v:5 previous definition.

[NOTE :PP0105] top_4.v:6 Multiply defined macro "my_macro",
               top.v:6 previous definition.

[NOTE :PP0105] top_5.v:4 Multiply defined macro "append",
               top_4.v:5 previous definition.

[NOTE :PP0105] top_5.v:6 Multiply defined macro "my_macro",
               top.v:6 previous definition.

[NOTE :PP0105] top_5.v:11 Multiply defined macro "append",
               top_4.v:5 previous definition.

[WARNI:PA0205] top.v:2 No timescale set for "bus_wr_rd_task".

[INFO :CP0300] Compilation...

[INFO :CP0303] top.v:2 Compile module "work@bus_wr_rd_task".

[INFO :CP0302] builtin.sv:4 Compile class "work@mailbox".

[INFO :CP0302] builtin.sv:33 Compile class "work@process".

[INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] top.v:2 Top level module "work@bus_wr_rd_task".

[WARNI:EL0505] top_1.v:2 Multiply defined module "work@bus_wr_rd_task",
               top.v:2 previous definition,
               top_2.v:2 previous definition,
               top_3.v:2 previous definition,
               top_4.v:2 previous definition,
               top_5.v:2 previous definition.

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 1.

[NOTE :EL0510] Nb instances: 1.

[NOTE :EL0511] Nb leaf instances: 0.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 2
[   NOTE] : 20

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*   End SURELOG SVerilog Compiler/Linter   *
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1.39user 0.04system 0:01.44elapsed 99%CPU (0avgtext+0avgdata 47020maxresident)k
48inputs+576outputs (0major+15315minor)pagefaults 0swaps