| commit | f29b69094ae895a3554f5825faba07ba868f4fc8 | [log] [tgz] |
|---|---|---|
| author | Alain Dargelas <5085492+alainmarcel@users.noreply.github.com> | Sat Nov 16 09:05:01 2019 -0800 |
| committer | Alain Dargelas <5085492+alainmarcel@users.noreply.github.com> | Sat Nov 16 09:05:01 2019 -0800 |
| tree | 99235b443fea2f6035edf0f7e931b087247350c4 | |
| parent | 51cb18436d4e7e5c955bf0d9582fef9c8625b405 [diff] |
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System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.
The executable is located here
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
`default_nettype in pre-processor's output