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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[WARNI:PA0205] sim/bench.v:2 No timescale set for "testbench".

[WARNI:PA0205] rtl/softusb_navre.v:18 No timescale set for "softusb_navre".

[INFO :CP0300] Compilation...

[INFO :CP0303] rtl/softusb_navre.v:18 Compile module "work@softusb_navre".

[INFO :CP0303] sim/bench.v:2 Compile module "work@testbench".

[NOTE :CP0309] rtl/softusb_navre.v:26 Implicit port type (wire) for "pmem_a",
there are 2 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] sim/bench.v:2 Top level module "work@testbench".

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 2.

[NOTE :EL0510] Nb instances: 2.

[NOTE :EL0511] Nb leaf instances: 0.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 2
[   NOTE] : 6

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*   End SURELOG SVerilog Compiler/Linter   *
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3.22user 0.05system 0:02.41elapsed 135%CPU (0avgtext+0avgdata 98232maxresident)k
64inputs+120outputs (0major+21949minor)pagefaults 0swaps