********************************************
*  SURELOG System Verilog Compiler/Linter  *
********************************************

[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PP0102] asicworld/code_hdl_models_arbiter_tb.v:22 Unknown macro "outfile".

[ERROR:PP0102] asicworld/code_verilog_tutorial_counter_tb.v:34 Unknown macro "outfile".

[ERROR:PP0102] asicworld/code_verilog_tutorial_first_counter_tb.v:9 Unknown macro "outfile".

[ERROR:PP0102] asicworld/code_verilog_tutorial_fsm_full_tb.v:10 Unknown macro "outfile".

[WARNI:PP0113] simple/macros.v:6 Unused macro argument "len".

[WARNI:PP0103] simple/macros.v:26 Undefining an unknown macro "X".

[WARNI:PP0103] simple/macros.v:30 Undefining an unknown macro "A".

[WARNI:PP0103] simple/macros.v:31 Undefining an unknown macro "B".

[WARNI:PP0103] simple/macros.v:39 Undefining an unknown macro "A".

[WARNI:PP0103] simple/macros.v:76 Undefining an unknown macro "A".

[WARNI:PP0103] simple/macros.v:142 Undefining an unknown macro "A".

[WARNI:PP0103] simple/macros.v:179 Undefining an unknown macro "A".

[ERROR:PA0207] asicworld/code_hdl_models_arbiter_tb.v:22 Syntax error: no viable alternative at input 'module testbench ();\n\nreg             clk = 0;\nreg             rst = 1;\nreg             req3 = 0;\nreg             req2 = 0;\nreg             req1 = 0;\nreg             req0 = 0;\nwire            gnt3;   \nwire            gnt2;   \nwire            gnt1;   \nwire            gnt0;  \n\n// Clock generator\nalways #1 clk = ~clk;\ninteger file;\n\nalways @(posedge clk)\n  $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});\n\ninitial begin\n  file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!',
  file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! );
                ^-- ./slpp_unit/work/asicworld/code_hdl_models_arbiter_tb.v:22 col:16.

[ERROR:PA0207] asicworld/code_verilog_tutorial_counter_tb.v:34 Syntax error: mismatched input '(' expecting ';',
 file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! );
              ^-- ./slpp_unit/work/asicworld/code_verilog_tutorial_counter_tb.v:34 col:14.

[ERROR:PA0203] asicworld/code_verilog_tutorial_counter_tb.v:34 Unknown macro "outfile".

[ERROR:PA0207] asicworld/code_verilog_tutorial_first_counter_tb.v:9 Syntax error: no viable alternative at input 'module testbench();\n// Declare inputs as regs and outputs as wires\nreg clock = 1, reset = 0, enable = 0;\nwire [3:0] counter_out;\ninteger file;\n\n// Initialize all variables\ninitial begin        \n  file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!',
  file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! );
                ^-- ./slpp_unit/work/asicworld/code_verilog_tutorial_first_counter_tb.v:9 col:16.

[ERROR:PA0207] asicworld/code_verilog_tutorial_fsm_full_tb.v:10 Syntax error: no viable alternative at input 'module testbench();\nreg clock = 0 , reset ;\nreg req_0 , req_1 ,  req_2 , req_3; \nwire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;\ninteger file;\n\ninitial begin\n  // $dumpfile("testbench.vcd");\n  // $dumpvars(0, testbench);\n  file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!!',
  file = $fopen(SURELOG_MACRO_NOT_DEFINED:outfile!!! );
                ^-- ./slpp_unit/work/asicworld/code_verilog_tutorial_fsm_full_tb.v:10 col:16.

[ERROR:PA0207] errors/syntax_err01.v:2 Syntax error: missing {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier} at '[',
integer [31:0]w;
        ^-- ./slpp_unit/work/errors/syntax_err01.v:2 col:8.

[ERROR:PA0207] errors/syntax_err02.v:3 Syntax error: missing {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier} at '[',
  input integer [3:0]x
                ^-- ./slpp_unit/work/errors/syntax_err02.v:3 col:16.

[ERROR:PA0207] errors/syntax_err03.v:3 Syntax error: mismatched input ']' expecting ':',
  input [3]x
          ^-- ./slpp_unit/work/errors/syntax_err03.v:3 col:10.

[ERROR:PA0207] errors/syntax_err04.v:2 Syntax error: mismatched input ']' expecting ':',
wire [3]x;
       ^-- ./slpp_unit/work/errors/syntax_err04.v:2 col:7.

[ERROR:PA0207] errors/syntax_err05.v:2 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
input x[2:0];
^-- ./slpp_unit/work/errors/syntax_err05.v:2 col:0.

[ERROR:PA0207] errors/syntax_err07.v:4 Syntax error: extraneous input '55' expecting ';',
assign y = (4)55;
              ^-- ./slpp_unit/work/errors/syntax_err07.v:4 col:14.

[ERROR:PA0207] errors/syntax_err08.v:4 Syntax error: no viable alternative at input 'x 55',
assign y = x 55;
             ^-- ./slpp_unit/work/errors/syntax_err08.v:4 col:13.

[ERROR:PA0207] errors/syntax_err10.v:2 Syntax error: missing {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier} at '[',
parameter integer [2:0]x=0;
                  ^-- ./slpp_unit/work/errors/syntax_err10.v:2 col:18.

[ERROR:PA0207] errors/syntax_err11.v:2 Syntax error: extraneous input 'real' expecting {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier},
parameter integer real x=0;
                  ^-- ./slpp_unit/work/errors/syntax_err11.v:2 col:18.

[ERROR:PA0207] lut/map_and.v:1 Syntax error: no viable alternative at input 'module top(..',
module top(...);
            ^-- ./slpp_unit/work/lut/map_and.v:1 col:12.

[ERROR:PA0207] lut/map_cmp.v:1 Syntax error: no viable alternative at input 'module top(..',
module top(...);
            ^-- ./slpp_unit/work/lut/map_cmp.v:1 col:12.

[ERROR:PA0207] lut/map_mux.v:1 Syntax error: no viable alternative at input 'module top(..',
module top(...);
            ^-- ./slpp_unit/work/lut/map_mux.v:1 col:12.

[ERROR:PA0207] lut/map_not.v:1 Syntax error: no viable alternative at input 'module top(..',
module top(...);
            ^-- ./slpp_unit/work/lut/map_not.v:1 col:12.

[ERROR:PA0207] lut/map_or.v:1 Syntax error: no viable alternative at input 'module top(..',
module top(...);
            ^-- ./slpp_unit/work/lut/map_or.v:1 col:12.

[ERROR:PA0207] lut/map_xor.v:1 Syntax error: no viable alternative at input 'module top(..',
module top(...);
            ^-- ./slpp_unit/work/lut/map_xor.v:1 col:12.

[ERROR:PA0207] opt/opt_expr_cmp.v:1 Syntax error: no viable alternative at input 'module top(..',
module top(...);
            ^-- ./slpp_unit/work/opt/opt_expr_cmp.v:1 col:12.

[ERROR:PA0207] opt/opt_share_add_sub.v:6 Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'new', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'expect', 'soft', 'global', 'do', 'this', DOLLAR_ROOT, 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier},
  );
  ^-- ./slpp_unit/work/opt/opt_share_add_sub.v:6 col:2.

[ERROR:PA0207] opt/opt_share_cat.v:8 Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'new', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'expect', 'soft', 'global', 'do', 'this', DOLLAR_ROOT, 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier},
  );
  ^-- ./slpp_unit/work/opt/opt_share_cat.v:8 col:2.

[ERROR:PA0207] opt/opt_share_cat_multiuser.v:8 Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'new', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'expect', 'soft', 'global', 'do', 'this', DOLLAR_ROOT, 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier},
  );
  ^-- ./slpp_unit/work/opt/opt_share_cat_multiuser.v:8 col:2.

[ERROR:PA0207] rpc/design.v:7 Syntax error: no viable alternative at input 'python_inv #(\n\t  .width(4)\n\t) inv (\n\t\t.i(i),\n\t\t.o(o),\n\t)',
	);
 ^-- ./slpp_unit/work/rpc/design.v:7 col:1.

[ERROR:PA0207] svinterfaces/svinterface_at_top_wrapper.v:26 Syntax error: token recognition error at: '\',
    .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting),
     ^-- ./slpp_unit/work/svinterfaces/svinterface_at_top_wrapper.v:26 col:5.

[ERROR:PA0207] various/constmsk_testmap.v:2 Syntax error: no viable alternative at input '(* techmap_celltype = "$reduce_or" *)\nmodule my_opt_reduce_or(..',
module my_opt_reduce_or(...);
                         ^-- ./slpp_unit/work/various/constmsk_testmap.v:2 col:25.

[ERROR:PA0207] various/shregmap.v:15 Syntax error: no viable alternative at input 'module $',
module $__SHREG_DFF_P_(input C, D, output Q);
       ^-- ./slpp_unit/work/various/shregmap.v:15 col:7.

[ERROR:PA0207] arch/common/mul.v:7 Syntax error: mismatched input ')' expecting {'.', 'interface', 'virtual', 'type', 'input', 'output', 'inout', 'ref', 'new', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', DOLLAR_UNIT, '(*', 'expect', 'soft', 'global', 'do', 'this', DOLLAR_ROOT, 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier},
);
^-- ./slpp_unit/work/arch/common/mul.v:7 col:0.

[ERROR:PA0207] arch/xilinx/macc_tb.v:8 Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
	output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
 ^-- ./slpp_unit/work/arch/xilinx/macc_tb.v:8 col:1.

[ERROR:PA0207] arch/xilinx/xilinx_srl.v:29 Syntax error: no viable alternative at input 'module $',
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
       ^-- ./slpp_unit/work/arch/xilinx/xilinx_srl.v:29 col:7.

[WARNI:PA0205] hana/hana_vlib.v:19 No timescale set for "BUF".

[WARNI:PA0205] hana/hana_vlib.v:25 No timescale set for "TRIBUF".

[WARNI:PA0205] hana/hana_vlib.v:31 No timescale set for "INV".

[WARNI:PA0205] hana/hana_vlib.v:37 No timescale set for "AND2".

[WARNI:PA0205] hana/hana_vlib.v:43 No timescale set for "AND3".

[WARNI:PA0205] hana/hana_vlib.v:49 No timescale set for "AND4".

[WARNI:PA0205] hana/hana_vlib.v:55 No timescale set for "OR2".

[WARNI:PA0205] hana/hana_vlib.v:61 No timescale set for "OR3".

[WARNI:PA0205] hana/hana_vlib.v:67 No timescale set for "OR4".

[WARNI:PA0205] hana/hana_vlib.v:74 No timescale set for "NAND2".

[WARNI:PA0205] hana/hana_vlib.v:80 No timescale set for "NAND3".

[WARNI:PA0205] hana/hana_vlib.v:86 No timescale set for "NAND4".

[WARNI:PA0205] hana/hana_vlib.v:92 No timescale set for "NOR2".

[WARNI:PA0205] hana/hana_vlib.v:98 No timescale set for "NOR3".

[WARNI:PA0205] hana/hana_vlib.v:104 No timescale set for "NOR4".

[WARNI:PA0205] hana/hana_vlib.v:111 No timescale set for "XOR2".

[WARNI:PA0205] hana/hana_vlib.v:117 No timescale set for "XOR3".

[WARNI:PA0205] hana/hana_vlib.v:123 No timescale set for "XOR4".

[WARNI:PA0205] hana/hana_vlib.v:130 No timescale set for "XNOR2".

[WARNI:PA0205] hana/hana_vlib.v:136 No timescale set for "XNOR3".

[WARNI:PA0205] hana/hana_vlib.v:142 No timescale set for "XNOR4".

[WARNI:PA0205] hana/hana_vlib.v:148 No timescale set for "DEC1".

[WARNI:PA0205] hana/hana_vlib.v:161 No timescale set for "DEC2".

[WARNI:PA0205] hana/hana_vlib.v:176 No timescale set for "DEC3".

[WARNI:PA0205] hana/hana_vlib.v:195 No timescale set for "DEC4".

[WARNI:PA0205] hana/hana_vlib.v:221 No timescale set for "DEC5".

[WARNI:PA0205] hana/hana_vlib.v:264 No timescale set for "DEC6".

[WARNI:PA0205] hana/hana_vlib.v:341 No timescale set for "MUX2".

[WARNI:PA0205] hana/hana_vlib.v:351 No timescale set for "MUX4".

[WARNI:PA0205] hana/hana_vlib.v:363 No timescale set for "MUX8".

[WARNI:PA0205] hana/hana_vlib.v:378 No timescale set for "MUX16".

[WARNI:PA0205] hana/hana_vlib.v:401 No timescale set for "MUX32".

[WARNI:PA0205] hana/hana_vlib.v:440 No timescale set for "MUX64".

[WARNI:PA0205] hana/hana_vlib.v:511 No timescale set for "ADD1".

[WARNI:PA0205] hana/hana_vlib.v:517 No timescale set for "ADD2".

[WARNI:PA0205] hana/hana_vlib.v:524 No timescale set for "ADD4".

[WARNI:PA0205] hana/hana_vlib.v:531 No timescale set for "ADD8".

[WARNI:PA0205] hana/hana_vlib.v:538 No timescale set for "ADD16".

[WARNI:PA0205] hana/hana_vlib.v:545 No timescale set for "ADD32".

[WARNI:PA0205] hana/hana_vlib.v:551 No timescale set for "ADD64".

[WARNI:PA0205] hana/hana_vlib.v:558 No timescale set for "SUB1".

[WARNI:PA0205] hana/hana_vlib.v:564 No timescale set for "SUB2".

[WARNI:PA0205] hana/hana_vlib.v:571 No timescale set for "SUB4".

[WARNI:PA0205] hana/hana_vlib.v:578 No timescale set for "SUB8".

[WARNI:PA0205] hana/hana_vlib.v:585 No timescale set for "SUB16".

[WARNI:PA0205] hana/hana_vlib.v:592 No timescale set for "SUB32".

[WARNI:PA0205] hana/hana_vlib.v:598 No timescale set for "SUB64".

[WARNI:PA0205] hana/hana_vlib.v:605 No timescale set for "MUL1".

[WARNI:PA0205] hana/hana_vlib.v:611 No timescale set for "MUL2".

[WARNI:PA0205] hana/hana_vlib.v:617 No timescale set for "MUL4".

[WARNI:PA0205] hana/hana_vlib.v:623 No timescale set for "MUL8".

[WARNI:PA0205] hana/hana_vlib.v:629 No timescale set for "MUL16".

[WARNI:PA0205] hana/hana_vlib.v:635 No timescale set for "MUL32".

[WARNI:PA0205] hana/hana_vlib.v:641 No timescale set for "MUL64".

[WARNI:PA0205] hana/hana_vlib.v:647 No timescale set for "DIV1".

[WARNI:PA0205] hana/hana_vlib.v:654 No timescale set for "DIV2".

[WARNI:PA0205] hana/hana_vlib.v:662 No timescale set for "DIV4".

[WARNI:PA0205] hana/hana_vlib.v:670 No timescale set for "DIV8".

[WARNI:PA0205] hana/hana_vlib.v:678 No timescale set for "DIV16".

[WARNI:PA0205] hana/hana_vlib.v:686 No timescale set for "DIV32".

[WARNI:PA0205] hana/hana_vlib.v:694 No timescale set for "DIV64".

[WARNI:PA0205] hana/hana_vlib.v:702 No timescale set for "FF".

[WARNI:PA0205] hana/hana_vlib.v:708 No timescale set for "RFF".

[WARNI:PA0205] hana/hana_vlib.v:716 No timescale set for "SFF".

[WARNI:PA0205] hana/hana_vlib.v:724 No timescale set for "RSFF".

[WARNI:PA0205] hana/hana_vlib.v:734 No timescale set for "SRFF".

[WARNI:PA0205] hana/hana_vlib.v:744 No timescale set for "LATCH".

[WARNI:PA0205] hana/hana_vlib.v:750 No timescale set for "RLATCH".

[WARNI:PA0205] hana/hana_vlib.v:759 No timescale set for "LSHIFT1".

[WARNI:PA0205] hana/hana_vlib.v:771 No timescale set for "LSHIFT2".

[WARNI:PA0205] hana/hana_vlib.v:782 No timescale set for "LSHIFT4".

[WARNI:PA0205] hana/hana_vlib.v:793 No timescale set for "LSHIFT8".

[WARNI:PA0205] hana/hana_vlib.v:803 No timescale set for "LSHIFT16".

[WARNI:PA0205] hana/hana_vlib.v:813 No timescale set for "LSHIFT32".

[WARNI:PA0205] hana/hana_vlib.v:823 No timescale set for "LSHIFT64".

[WARNI:PA0205] hana/hana_vlib.v:833 No timescale set for "RSHIFT1".

[WARNI:PA0205] hana/hana_vlib.v:844 No timescale set for "RSHIFT2".

[WARNI:PA0205] hana/hana_vlib.v:857 No timescale set for "RSHIFT4".

[WARNI:PA0205] hana/hana_vlib.v:868 No timescale set for "RSHIFT8".

[WARNI:PA0205] hana/hana_vlib.v:880 No timescale set for "RSHIFT16".

[WARNI:PA0205] hana/hana_vlib.v:892 No timescale set for "RSHIFT32".

[WARNI:PA0205] hana/hana_vlib.v:903 No timescale set for "RSHIFT64".

[WARNI:PA0205] hana/hana_vlib.v:914 No timescale set for "CMP1".

[WARNI:PA0205] hana/hana_vlib.v:941 No timescale set for "CMP2".

[WARNI:PA0205] hana/hana_vlib.v:967 No timescale set for "CMP4".

[WARNI:PA0205] hana/hana_vlib.v:993 No timescale set for "CMP8".

[WARNI:PA0205] hana/hana_vlib.v:1019 No timescale set for "CMP16".

[WARNI:PA0205] hana/hana_vlib.v:1045 No timescale set for "CMP32".

[WARNI:PA0205] hana/hana_vlib.v:1071 No timescale set for "CMP64".

[WARNI:PA0205] hana/hana_vlib.v:1097 No timescale set for "VCC".

[WARNI:PA0205] hana/hana_vlib.v:1100 No timescale set for "GND".

[WARNI:PA0205] hana/hana_vlib.v:1104 No timescale set for "INC1".

[WARNI:PA0205] hana/hana_vlib.v:1110 No timescale set for "INC2".

[WARNI:PA0205] hana/hana_vlib.v:1116 No timescale set for "INC4".

[WARNI:PA0205] hana/hana_vlib.v:1121 No timescale set for "INC8".

[WARNI:PA0205] hana/hana_vlib.v:1126 No timescale set for "INC16".

[WARNI:PA0205] hana/hana_vlib.v:1131 No timescale set for "INC32".

[WARNI:PA0205] hana/hana_vlib.v:1135 No timescale set for "INC64".

[WARNI:PA0205] asicworld/code_hdl_models_arbiter_tb.v:1 No timescale set for "MODULE NAME UNKNOWN".

[WARNI:PA0205] asicworld/code_hdl_models_clk_div.v:8 No timescale set for "clk_div".

[WARNI:PA0205] asicworld/code_hdl_models_d_latch_gates.v:1 No timescale set for "d_latch_gates".

[WARNI:PA0205] asicworld/code_hdl_models_decoder_using_assign.v:7 No timescale set for "decoder_using_assign".

[WARNI:PA0205] asicworld/code_hdl_models_dff_sync_reset.v:7 No timescale set for "dff_sync_reset".

[WARNI:PA0205] asicworld/code_hdl_models_full_adder_gates.v:7 No timescale set for "full_adder_gates".

[WARNI:PA0205] asicworld/code_hdl_models_cam.v:7 No timescale set for "cam".

[WARNI:PA0205] asicworld/code_hdl_models_d_ff_gates.v:1 No timescale set for "d_ff_gates".

[WARNI:PA0205] asicworld/code_hdl_models_decoder_2to4_gates.v:1 No timescale set for "decoder_2to4_gates".

[WARNI:PA0205] asicworld/code_hdl_models_GrayCounter.v:7 No timescale set for "GrayCounter".

[WARNI:PA0205] asicworld/code_hdl_models_gray_counter.v:7 No timescale set for "gray_counter".

[WARNI:PA0205] asicworld/code_hdl_models_mux_2to1_gates.v:7 No timescale set for "mux_2to1_gates".

[WARNI:PA0205] asicworld/code_hdl_models_decoder_using_case.v:7 No timescale set for "decoder_using_case".

[WARNI:PA0205] asicworld/code_hdl_models_encoder_using_if.v:7 No timescale set for "encoder_using_if".

[WARNI:PA0205] asicworld/code_hdl_models_mux_using_assign.v:7 No timescale set for "mux_using_assign".

[WARNI:PA0205] asicworld/code_hdl_models_mux_using_case.v:7 No timescale set for "mux_using_case".

[WARNI:PA0205] asicworld/code_hdl_models_parity_using_assign.v:7 No timescale set for "parity_using_assign".

[WARNI:PA0205] asicworld/code_hdl_models_rom_using_case.v:7 No timescale set for "rom_using_case".

[WARNI:PA0205] asicworld/code_hdl_models_tff_sync_reset.v:7 No timescale set for "tff_sync_reset".

[WARNI:PA0205] asicworld/code_hdl_models_up_down_counter.v:7 No timescale set for "up_down_counter".

[WARNI:PA0205] asicworld/code_tidbits_asyn_reset.v:1 No timescale set for "asyn_reset".

[WARNI:PA0205] asicworld/code_hdl_models_arbiter.v:5 No timescale set for "arbiter".

[WARNI:PA0205] asicworld/code_hdl_models_full_subtracter_gates.v:7 No timescale set for "full_subtracter_gates".

[WARNI:PA0205] asicworld/code_hdl_models_half_adder_gates.v:7 No timescale set for "half_adder_gates".

[WARNI:PA0205] asicworld/code_hdl_models_parallel_crc.v:7 No timescale set for "parallel_crc_ccitt".

[WARNI:PA0205] asicworld/code_hdl_models_tff_async_reset.v:7 No timescale set for "tff_async_reset".

[WARNI:PA0205] asicworld/code_hdl_models_up_counter.v:7 No timescale set for "up_counter".

[WARNI:PA0205] asicworld/code_hdl_models_clk_div_45.v:7 No timescale set for "clk_div_45".

[WARNI:PA0205] asicworld/code_hdl_models_dff_async_reset.v:7 No timescale set for "dff_async_reset".

[WARNI:PA0205] asicworld/code_specman_switch_fabric.v:1 No timescale set for "switch_fabric".

[WARNI:PA0205] asicworld/code_specman_switch_fabric.v:51 No timescale set for "switch".

[WARNI:PA0205] asicworld/code_hdl_models_encoder_4to2_gates.v:1 No timescale set for "encoder_4to2_gates".

[WARNI:PA0205] asicworld/code_hdl_models_encoder_using_case.v:7 No timescale set for "encoder_using_case".

[WARNI:PA0205] asicworld/code_tidbits_fsm_using_function.v:6 No timescale set for "fsm_using_function".

[WARNI:PA0205] asicworld/code_verilog_tutorial_addbit.v:1 No timescale set for "addbit".

[WARNI:PA0205] asicworld/code_hdl_models_lfsr.v:7 No timescale set for "lfsr".

[WARNI:PA0205] asicworld/code_hdl_models_one_hot_cnt.v:7 No timescale set for "one_hot_cnt".

[WARNI:PA0205] asicworld/code_hdl_models_parity_using_function.v:7 No timescale set for "parity_using_function".

[WARNI:PA0205] asicworld/code_tidbits_fsm_using_single_always.v:7 No timescale set for "fsm_using_single_always".

[WARNI:PA0205] asicworld/code_verilog_tutorial_escape_id.v:3 No timescale set for "1dff".

[WARNI:PA0205] asicworld/code_verilog_tutorial_parity.v:9 No timescale set for "parity".

[WARNI:PA0205] errors/syntax_err04.v:1 No timescale set for "a".

[WARNI:PA0205] asicworld/code_hdl_models_lfsr_updown.v:1 No timescale set for "lfsr_updown".

[WARNI:PA0205] asicworld/code_hdl_models_mux_using_if.v:7 No timescale set for "mux_using_if".

[WARNI:PA0205] asicworld/code_hdl_models_parity_using_bitwise.v:7 No timescale set for "parity_using_bitwise".

[WARNI:PA0205] asicworld/code_hdl_models_serial_crc.v:7 No timescale set for "serial_crc_ccitt".

[WARNI:PA0205] asicworld/code_hdl_models_up_counter_load.v:7 No timescale set for "up_counter_load".

[WARNI:PA0205] asicworld/code_tidbits_blocking.v:1 No timescale set for "blocking".

[WARNI:PA0205] asicworld/code_tidbits_fsm_using_always.v:6 No timescale set for "fsm_using_always".

[WARNI:PA0205] asicworld/code_tidbits_reg_seq_example.v:1 No timescale set for "reg_seq_example".

[WARNI:PA0205] asicworld/code_tidbits_wire_example.v:1 No timescale set for "wire_example".

[WARNI:PA0205] asicworld/code_verilog_tutorial_bus_con.v:1 No timescale set for "bus_con".

[WARNI:PA0205] asicworld/code_verilog_tutorial_d_ff.v:2 No timescale set for "d_ff".

[WARNI:PA0205] asicworld/code_verilog_tutorial_decoder_always.v:1 No timescale set for "decoder_always".

[WARNI:PA0205] asicworld/code_verilog_tutorial_first_counter.v:9 No timescale set for "first_counter".

[WARNI:PA0205] asicworld/code_verilog_tutorial_mux_21.v:1 No timescale set for "mux_21".

[WARNI:PA0205] asicworld/code_verilog_tutorial_n_out_primitive.v:1 No timescale set for "n_out_primitive".

[WARNI:PA0205] asicworld/code_hdl_models_pri_encoder_using_assign.v:7 No timescale set for "pri_encoder_using_assign".

[WARNI:PA0205] asicworld/code_verilog_tutorial_simple_function.v:1 No timescale set for "simple_function".

[WARNI:PA0205] asicworld/code_verilog_tutorial_simple_if.v:1 No timescale set for "simple_if".

[WARNI:PA0205] asicworld/code_verilog_tutorial_tri_buf.v:1 No timescale set for "tri_buf".

[WARNI:PA0205] asicworld/code_verilog_tutorial_which_clock.v:1 No timescale set for "which_clock".

[WARNI:PA0205] asicworld/code_verilog_tutorial_counter_tb.v:16 No timescale set for "testbench".

[WARNI:PA0205] asicworld/code_verilog_tutorial_if_else.v:1 No timescale set for "if_else".

[WARNI:PA0205] asicworld/code_verilog_tutorial_multiply.v:1 No timescale set for "muliply".

[WARNI:PA0205] hana/test_parser.v:3 No timescale set for "f1_test".

[WARNI:PA0205] hana/test_parser.v:7 No timescale set for "f2_test".

[WARNI:PA0205] hana/test_parser.v:19 No timescale set for "f3_test".

[WARNI:PA0205] hana/test_parser.v:34 No timescale set for "f4_ahmad".

[WARNI:PA0205] hana/test_parser.v:41 No timescale set for "f5_test".

[WARNI:PA0205] hana/test_parser.v:53 No timescale set for "f5_ternaryop".

[WARNI:PA0205] hana/test_parser.v:62 No timescale set for "f5_fulladd4".

[WARNI:PA0205] hana/test_parser.v:72 No timescale set for "f6_adder".

[WARNI:PA0205] hana/test_parser.v:80 No timescale set for "f7_test".

[WARNI:PA0205] asicworld/code_verilog_tutorial_parallel_if.v:1 No timescale set for "parallel_if".

[WARNI:PA0205] hana/test_simulation_and.v:18 No timescale set for "f4_test".

[WARNI:PA0205] hana/test_simulation_and.v:28 No timescale set for "f6_test".

[WARNI:PA0205] asicworld/code_verilog_tutorial_task_global.v:1 No timescale set for "task_global".

[WARNI:PA0205] asicworld/code_hdl_models_uart.v:7 No timescale set for "uart".

[WARNI:PA0205] asicworld/code_tidbits_nonblocking.v:1 No timescale set for "nonblocking".

[WARNI:PA0205] asicworld/code_tidbits_reg_combo_example.v:1 No timescale set for "reg_combo_example".

[WARNI:PA0205] asicworld/code_tidbits_syn_reset.v:1 No timescale set for "syn_reset".

[WARNI:PA0205] asicworld/code_verilog_tutorial_always_example.v:1 No timescale set for "always_example".

[WARNI:PA0205] asicworld/code_verilog_tutorial_counter.v:7 No timescale set for "counter".

[WARNI:PA0205] asicworld/code_verilog_tutorial_decoder.v:1 No timescale set for "decoder".

[WARNI:PA0205] hana/test_simulation_shifter.v:45 No timescale set for "f8_test".

[WARNI:PA0205] hana/test_simulation_shifter.v:51 No timescale set for "f9_test".

[WARNI:PA0205] hana/test_simulation_shifter.v:57 No timescale set for "f10_test".

[WARNI:PA0205] asicworld/code_verilog_tutorial_explicit.v:1 No timescale set for "explicit".

[WARNI:PA0205] asicworld/code_verilog_tutorial_explicit.v:19 No timescale set for "dff".

[WARNI:PA0205] asicworld/code_verilog_tutorial_flip_flop.v:1 No timescale set for "flif_flop".

[WARNI:PA0205] hana/test_simulation_always.v:57 No timescale set for "f6_NonBlockingEx".

[WARNI:PA0205] hana/test_simulation_always.v:74 No timescale set for "f7_FlipFlop".

[WARNI:PA0205] hana/test_simulation_always.v:87 No timescale set for "f8_inc".

[WARNI:PA0205] hana/test_simulation_always.v:96 No timescale set for "f9_MyCounter".

[WARNI:PA0205] hana/test_simulation_always.v:112 No timescale set for "f10_FlipFlop".

[WARNI:PA0205] hana/test_simulation_always.v:127 No timescale set for "f11_test".

[WARNI:PA0205] asicworld/code_verilog_tutorial_fsm_full.v:1 No timescale set for "fsm_full".

[WARNI:PA0205] opt/opt_lut.v:1 No timescale set for "top".

[WARNI:PA0205] opt/opt_share_add_sub.v:1 No timescale set for "opt_share_test".

[WARNI:PA0205] memories/amber23_sram_byte_en.v:45 No timescale set for "generic_sram_byte_en".

[WARNI:PA0205] proc/bug_1268.v:1 No timescale set for "gold".

[WARNI:PA0205] proc/bug_1268.v:13 No timescale set for "gate".

[WARNI:PA0205] sat/counters-repeat.v:3 No timescale set for "counter1".

[WARNI:PA0205] sat/counters-repeat.v:18 No timescale set for "counter2".

[WARNI:PA0205] asicworld/code_verilog_tutorial_v2k_reg.v:1 No timescale set for "v2k_reg".

[WARNI:PA0205] hana/test_parse2synthtrans.v:27 No timescale set for "f2_demultiplexer1_to_4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:3 No timescale set for "f1_TECH_AND18".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:7 No timescale set for "f1_TECH_AND4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:12 No timescale set for "f2_TECH_AND5".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:17 No timescale set for "f3_TECH_NAND18".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:21 No timescale set for "f3_TECH_NAND4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:25 No timescale set for "f3_TECH_NAND2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:30 No timescale set for "f4_TECH_NAND18".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:34 No timescale set for "f4_TECH_NAND4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:38 No timescale set for "f4_TECH_NAND2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:43 No timescale set for "f5_TECH_NAND18".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:47 No timescale set for "f5_TECH_NAND4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:51 No timescale set for "f5_TECH_NAND2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:56 No timescale set for "f6_TECH_NOR18".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:60 No timescale set for "f6_TECH_NOR4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:64 No timescale set for "f6_TECH_NOR2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:69 No timescale set for "f7_TECH_NOR18".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:73 No timescale set for "f7_TECH_NOR4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:77 No timescale set for "f7_TECH_NOR2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:82 No timescale set for "f8_TECH_NOR18".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:86 No timescale set for "f8_TECH_NOR4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:90 No timescale set for "f8_TECH_NOR2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:95 No timescale set for "f9_TECH_OR18".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:99 No timescale set for "f9_TECH_OR4".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:104 No timescale set for "f10_TECH_OR5".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:109 No timescale set for "f11_TECH_XOR5".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:112 No timescale set for "f11_TECH_XOR2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:117 No timescale set for "f12_TECH_XOR5".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:120 No timescale set for "f12_TECH_XOR2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:125 No timescale set for "f13_TECH_XOR2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:130 No timescale set for "f14_TECH_XOR5".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:133 No timescale set for "f14_TECH_XOR2".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:138 No timescale set for "f15_TECH_XOR5".

[WARNI:PA0205] hana/test_simulation_techmap_tech.v:141 No timescale set for "f15_TECH_XOR2".

[WARNI:PA0205] errors/syntax_err12.v:1 No timescale set for "iface".

[WARNI:PA0205] sat/expose_dff.v:2 No timescale set for "test1".

[WARNI:PA0205] sat/expose_dff.v:7 No timescale set for "test2".

[WARNI:PA0205] sat/expose_dff.v:17 No timescale set for "test3".

[WARNI:PA0205] sat/expose_dff.v:25 No timescale set for "test4".

[WARNI:PA0205] memories/implicit_en.v:4 No timescale set for "test".

[WARNI:PA0205] hana/test_intermout.v:54 No timescale set for "f5_NonBlockingEx".

[WARNI:PA0205] hana/test_intermout.v:71 No timescale set for "f6_FlipFlop".

[WARNI:PA0205] hana/test_intermout.v:108 No timescale set for "f9_NegEdgeClock".

[WARNI:PA0205] hana/test_intermout.v:121 No timescale set for "f10_MyCounter".

[WARNI:PA0205] hana/test_intermout.v:148 No timescale set for "f12_test".

[WARNI:PA0205] hana/test_intermout.v:154 No timescale set for "f13_test".

[WARNI:PA0205] hana/test_intermout.v:163 No timescale set for "f14_test".

[WARNI:PA0205] hana/test_intermout.v:175 No timescale set for "f14_mybuf".

[WARNI:PA0205] hana/test_intermout.v:187 No timescale set for "f15_test".

[WARNI:PA0205] hana/test_intermout.v:210 No timescale set for "f15_mybuf".

[WARNI:PA0205] hana/test_intermout.v:222 No timescale set for "f16_test".

[WARNI:PA0205] hana/test_intermout.v:234 No timescale set for "f17_test".

[WARNI:PA0205] hana/test_intermout.v:249 No timescale set for "f18_test".

[WARNI:PA0205] hana/test_intermout.v:256 No timescale set for "f19_buffer".

[WARNI:PA0205] hana/test_intermout.v:267 No timescale set for "f20_test".

[WARNI:PA0205] hana/test_intermout.v:280 No timescale set for "f21_test".

[WARNI:PA0205] hana/test_intermout.v:291 No timescale set for "f22_test".

[WARNI:PA0205] hana/test_intermout.v:305 No timescale set for "f23_test".

[WARNI:PA0205] hana/test_intermout.v:314 No timescale set for "f24_test".

[WARNI:PA0205] hana/test_intermout.v:326 No timescale set for "f25_test".

[WARNI:PA0205] hana/test_intermout.v:335 No timescale set for "f26_test".

[WARNI:PA0205] hana/test_intermout.v:347 No timescale set for "f27_test".

[WARNI:PA0205] hana/test_intermout.v:359 No timescale set for "f28_test".

[WARNI:PA0205] hana/test_intermout.v:366 No timescale set for "f29_Reduction".

[WARNI:PA0205] hana/test_intermout.v:384 No timescale set for "f30_test".

[WARNI:PA0205] hana/test_intermout.v:396 No timescale set for "f31_test".

[WARNI:PA0205] hana/test_intermout.v:403 No timescale set for "f32_test".

[WARNI:PA0205] hana/test_intermout.v:409 No timescale set for "f33_test".

[WARNI:PA0205] simple/aes_kexp128.v:4 No timescale set for "aes_key_expand_128".

[WARNI:PA0205] simple/arrays01.v:1 No timescale set for "uut_arrays01".

[WARNI:PA0205] liberty/small.v:3 No timescale set for "small".

[WARNI:PA0205] simple/attrib04_net_var.v:1 No timescale set for "bar".

[WARNI:PA0205] simple/attrib04_net_var.v:24 No timescale set for "foo".

[WARNI:PA0205] memories/issue00335.v:5 No timescale set for "ram2".

[WARNI:PA0205] opt/opt_rmdff.v:1 No timescale set for "opt_rmdff_test".

[WARNI:PA0205] sat/share.v:1 No timescale set for "test_1".

[WARNI:PA0205] sat/share.v:12 No timescale set for "test_2".

[WARNI:PA0205] simple/always01.v:1 No timescale set for "uut_always01".

[WARNI:PA0205] simple/always03.v:1 No timescale set for "uut_always03".

[WARNI:PA0205] sat/asserts_seq.v:1 No timescale set for "test_001".

[WARNI:PA0205] sat/asserts_seq.v:20 No timescale set for "test_002".

[WARNI:PA0205] sat/asserts_seq.v:37 No timescale set for "test_003".

[WARNI:PA0205] sat/asserts_seq.v:54 No timescale set for "test_004".

[WARNI:PA0205] sat/asserts_seq.v:71 No timescale set for "test_005".

[WARNI:PA0205] simple/always02.v:1 No timescale set for "uut_always02".

[WARNI:PA0205] simple/arraycells.v:2 No timescale set for "array_test001".

[WARNI:PA0205] simple/arraycells.v:10 No timescale set for "aoi12".

[WARNI:PA0205] simple/constmuldivmod.v:1 No timescale set for "constmuldivmod".

[WARNI:PA0205] simple/forgen01.v:4 No timescale set for "uut_forgen01".

[WARNI:PA0205] simple/dff_different_styles.v:9 No timescale set for "dffa".

[WARNI:PA0205] simple/dff_different_styles.v:20 No timescale set for "dffa1".

[WARNI:PA0205] simple/dff_different_styles.v:31 No timescale set for "dffa2".

[WARNI:PA0205] simple/dff_different_styles.v:42 No timescale set for "dffa3".

[WARNI:PA0205] simple/dff_different_styles.v:53 No timescale set for "dffa4".

[WARNI:PA0205] simple/dff_different_styles.v:72 No timescale set for "dffsr1".

[WARNI:PA0205] simple/dff_different_styles.v:83 No timescale set for "dffsr2".

[WARNI:PA0205] simple/dff_different_styles.v:91 No timescale set for "dffsr2_sub".

[WARNI:PA0205] simple/hierarchy.v:16 No timescale set for "submod".

[WARNI:PA0205] simple/i2c_master_tests.v:6 No timescale set for "i2c_test01".

[WARNI:PA0205] simple/i2c_master_tests.v:29 No timescale set for "i2c_test02".

[WARNI:PA0205] simple/forgen02.v:1 No timescale set for "uut_forgen02".

[WARNI:PA0205] simple/carryadd.v:1 No timescale set for "carryadd".

[WARNI:PA0205] simple/fiedler-cooley.v:3 No timescale set for "up3down5".

[WARNI:PA0205] simple/fsm.v:4 No timescale set for "fsm_test".

[WARNI:PA0205] simple/constpower.v:1 No timescale set for "constpower".

[WARNI:PA0205] simple/forloops.v:1 No timescale set for "forloops01".

[WARNI:PA0205] simple/forloops.v:15 No timescale set for "forloops02".

[WARNI:PA0205] simple/graphtest.v:1 No timescale set for "graphtest".

[WARNI:PA0205] simple/implicit_ports.v:2 No timescale set for "alu".

[WARNI:PA0205] simple/implicit_ports.v:7 No timescale set for "named_ports".

[WARNI:PA0205] simple/dff_init.v:1 No timescale set for "dff0_test".

[WARNI:PA0205] simple/dff_init.v:11 No timescale set for "dff1_test".

[WARNI:PA0205] simple/dff_init.v:22 No timescale set for "dff0a_test".

[WARNI:PA0205] simple/dff_init.v:33 No timescale set for "dff1a_test".

[WARNI:PA0205] simple/dff_init.v:44 No timescale set for "dff_test_997".

[WARNI:PA0205] simple/hierdefparam.v:3 No timescale set for "hierdefparam_top".

[WARNI:PA0205] simple/hierdefparam.v:11 No timescale set for "hierdefparam_a".

[WARNI:PA0205] simple/hierdefparam.v:22 No timescale set for "hierdefparam_b".

[WARNI:PA0205] simple/localparam_attr.v:1 No timescale set for "uut_localparam_attr".

[WARNI:PA0205] simple/mem2reg.v:2 No timescale set for "mem2reg_test1".

[WARNI:PA0205] simple/mem2reg.v:22 No timescale set for "mem2reg_test2".

[WARNI:PA0205] simple/mem2reg.v:53 No timescale set for "mem2reg_test3".

[WARNI:PA0205] simple/mem2reg.v:64 No timescale set for "mem2reg_test4".

[WARNI:PA0205] simple/mem2reg.v:86 No timescale set for "mem2reg_test5".

[WARNI:PA0205] simple/mem2reg.v:97 No timescale set for "mem2reg_test6".

[WARNI:PA0205] simple/macros.v:2 No timescale set for "test_def".

[WARNI:PA0205] simple/macros.v:19 No timescale set for "test_ifdef".

[WARNI:PA0205] simple/macros.v:241 No timescale set for "test_comment_in_macro".

[WARNI:PA0205] simple/omsp_dbg_uart.v:2 No timescale set for "omsp_dbg_uart".

[WARNI:PA0205] simple/param_attr.v:1 No timescale set for "uut_param_attr".

[WARNI:PA0205] simple/paramods.v:2 No timescale set for "pm_test1".

[WARNI:PA0205] simple/paramods.v:14 No timescale set for "pm_test2".

[WARNI:PA0205] simple/paramods.v:26 No timescale set for "pm_test3".

[WARNI:PA0205] simple/paramods.v:42 No timescale set for "inc".

[WARNI:PA0205] simple/loops.v:6 No timescale set for "aes".

[WARNI:PA0205] simple/process.v:2 No timescale set for "blocking_cond".

[WARNI:PA0205] simple/process.v:21 No timescale set for "uut".

[WARNI:PA0205] simple/mem_arst.v:2 No timescale set for "MyMem".

[WARNI:PA0205] simple/repwhile.v:1 No timescale set for "repwhile_test001".

[WARNI:PA0205] simple/muxtree.v:5 No timescale set for "usb_tx_phy".

[WARNI:PA0205] simple/muxtree.v:56 No timescale set for "default_cases".

[WARNI:PA0205] simple/muxtree.v:76 No timescale set for "select_leaves".

[WARNI:PA0205] simple/signedexpr.v:1 No timescale set for "signed_test01".

[WARNI:PA0205] simple/operators.v:1 No timescale set for "optest".

[WARNI:PA0205] simple/realexpr.v:1 No timescale set for "demo_001".

[WARNI:PA0205] simple/realexpr.v:15 No timescale set for "demo_002".

[WARNI:PA0205] simple/realexpr.v:24 No timescale set for "demo_003".

[WARNI:PA0205] simple/realexpr.v:30 No timescale set for "demo_004".

[WARNI:PA0205] simple/retime.v:1 No timescale set for "retime_test".

[WARNI:PA0205] simple/rotate.v:3 No timescale set for "a23_barrel_shift_fpga_rotate".

[WARNI:PA0205] simple/subbytes.v:4 No timescale set for "subbytes_00".

[WARNI:PA0205] simple/wandwor.v:1 No timescale set for "wandwor_test0".

[WARNI:PA0205] simple/wandwor.v:13 No timescale set for "wandwor_test1".

[WARNI:PA0205] simple/wreduce.v:1 No timescale set for "wreduce_test0".

[WARNI:PA0205] simple/wreduce.v:7 No timescale set for "wreduce_test1".

[WARNI:PA0205] simple/multiplier.v:8 No timescale set for "Multiplier_flat".

[WARNI:PA0205] simple/multiplier.v:66 No timescale set for "Multiplier_2D".

[WARNI:PA0205] simple/multiplier.v:98 No timescale set for "RippleCarryAdder".

[WARNI:PA0205] simple/multiplier.v:119 No timescale set for "FullAdder".

[WARNI:PA0205] simple/sincos.v:6 No timescale set for "d".

[WARNI:PA0205] simple/partsel.v:1 No timescale set for "partsel_test001".

[WARNI:PA0205] simple/partsel.v:7 No timescale set for "partsel_test002".

[WARNI:PA0205] simple/generate.v:2 No timescale set for "gen_test1".

[WARNI:PA0205] simple/generate.v:43 No timescale set for "gen_test2".

[WARNI:PA0205] simple/generate.v:70 No timescale set for "gen_test3".

[WARNI:PA0205] simple/generate.v:97 No timescale set for "gen_test4".

[WARNI:PA0205] simple/generate.v:118 No timescale set for "gen_test5".

[WARNI:PA0205] simple/generate.v:154 No timescale set for "gen_test6".

[WARNI:PA0205] simple_abc9/abc9.v:1 No timescale set for "abc9_test001".

[WARNI:PA0205] simple_abc9/abc9.v:5 No timescale set for "abc9_test002".

[WARNI:PA0205] simple_abc9/abc9.v:9 No timescale set for "abc9_test003".

[WARNI:PA0205] simple_abc9/abc9.v:13 No timescale set for "abc9_test004".

[WARNI:PA0205] simple_abc9/abc9.v:17 No timescale set for "abc9_test005".

[WARNI:PA0205] simple_abc9/abc9.v:22 No timescale set for "abc9_test006".

[WARNI:PA0205] simple_abc9/abc9.v:28 No timescale set for "abc9_test007".

[WARNI:PA0205] simple_abc9/abc9.v:35 No timescale set for "abc9_test007_sub".

[WARNI:PA0205] simple_abc9/abc9.v:39 No timescale set for "abc9_test008".

[WARNI:PA0205] simple_abc9/abc9.v:46 No timescale set for "abc9_test008_sub".

[WARNI:PA0205] simple_abc9/abc9.v:50 No timescale set for "abc9_test009".

[WARNI:PA0205] simple_abc9/abc9.v:58 No timescale set for "abc9_test010".

[WARNI:PA0205] simple_abc9/abc9.v:66 No timescale set for "abc9_test011".

[WARNI:PA0205] simple_abc9/abc9.v:74 No timescale set for "abc9_test012".

[WARNI:PA0205] simple_abc9/abc9.v:82 No timescale set for "abc9_test013".

[WARNI:PA0205] simple_abc9/abc9.v:93 No timescale set for "abc9_test014".

[WARNI:PA0205] simple_abc9/abc9.v:97 No timescale set for "abc9_test012_sub".

[WARNI:PA0205] simple_abc9/abc9.v:108 No timescale set for "abc9_test015".

[WARNI:PA0205] simple_abc9/abc9.v:114 No timescale set for "abc9_test016".

[WARNI:PA0205] simple_abc9/abc9.v:120 No timescale set for "abc9_test017".

[WARNI:PA0205] simple_abc9/abc9.v:126 No timescale set for "abc9_test018".

[WARNI:PA0205] simple_abc9/abc9.v:132 No timescale set for "abc9_test019".

[WARNI:PA0205] simple_abc9/abc9.v:139 No timescale set for "abc9_test020".

[WARNI:PA0205] simple_abc9/abc9.v:147 No timescale set for "abc9_test021".

[WARNI:PA0205] simple_abc9/abc9.v:216 No timescale set for "MUXF8".

[WARNI:PA0205] simple_abc9/abc9.v:227 No timescale set for "abc9_test022".

[WARNI:PA0205] simple_abc9/abc9.v:243 No timescale set for "abc9_test023".

[WARNI:PA0205] simple_abc9/abc9.v:254 No timescale set for "abc9_test024".

[WARNI:PA0205] simple_abc9/abc9.v:258 No timescale set for "abc9_test024_sub".

[WARNI:PA0205] simple_abc9/abc9.v:262 No timescale set for "abc9_test025".

[WARNI:PA0205] simple_abc9/abc9.v:266 No timescale set for "abc9_test026".

[WARNI:PA0205] various/pmux2shiftx.v:1 No timescale set for "pmux2shiftx_test".

[WARNI:PA0205] various/pmux2shiftx.v:36 No timescale set for "issue01135".

[WARNI:PA0205] simple/scopes.v:1 No timescale set for "scopes_test_01".

[WARNI:PA0205] simple/specify.v:1 No timescale set for "test_specify".

[WARNI:PA0205] simple/undef_eqx_nex.v:1 No timescale set for "undef_eqx_nex".

[WARNI:PA0205] various/specify.v:35 No timescale set for "issue01144".

[WARNI:PA0205] arch/common/adffs.v:1 No timescale set for "adff".

[WARNI:PA0205] arch/common/adffs.v:12 No timescale set for "adffn".

[WARNI:PA0205] arch/common/adffs.v:23 No timescale set for "dffs".

[WARNI:PA0205] arch/common/adffs.v:34 No timescale set for "ndffnr".

[WARNI:PA0205] arch/common/tribuf.v:1 No timescale set for "tristate".

[WARNI:PA0205] simple/usb_phy_tests.v:3 No timescale set for "usb_phy_test01".

[WARNI:PA0205] simple/values.v:2 No timescale set for "test_signed".

[WARNI:PA0205] simple/values.v:17 No timescale set for "test_const".

[WARNI:PA0205] techmap/mem_simple_4x1_cells.v:1 No timescale set for "MEM4X1".

[WARNI:PA0205] simple/memory.v:2 No timescale set for "memtest00".

[WARNI:PA0205] simple/memory.v:19 No timescale set for "memtest01".

[WARNI:PA0205] simple/memory.v:39 No timescale set for "memtest02".

[WARNI:PA0205] simple/memory.v:80 No timescale set for "memtest03".

[WARNI:PA0205] simple/memory.v:98 No timescale set for "memtest04".

[WARNI:PA0205] simple/memory.v:119 No timescale set for "memtest05".

[WARNI:PA0205] simple/memory.v:140 No timescale set for "memtest06_sync".

[WARNI:PA0205] simple/memory.v:159 No timescale set for "memtest06_async".

[WARNI:PA0205] simple/memory.v:180 No timescale set for "memtest07".

[WARNI:PA0205] simple/memory.v:200 No timescale set for "memtest08".

[WARNI:PA0205] simple/memory.v:210 No timescale set for "memtest09".

[WARNI:PA0205] simple/memory.v:233 No timescale set for "memtest10".

[WARNI:PA0205] simple/memory.v:249 No timescale set for "memtest11".

[WARNI:PA0205] simple/memory.v:269 No timescale set for "memtest12".

[WARNI:PA0205] simple/memory.v:282 No timescale set for "memtest13".

[WARNI:PA0205] simple/vloghammer.v:5 No timescale set for "test01".

[WARNI:PA0205] simple/vloghammer.v:11 No timescale set for "test02".

[WARNI:PA0205] simple/vloghammer.v:17 No timescale set for "test03".

[WARNI:PA0205] simple/vloghammer.v:24 No timescale set for "test04".

[WARNI:PA0205] simple/vloghammer.v:46 No timescale set for "test07".

[WARNI:PA0205] simple/vloghammer.v:53 No timescale set for "test08".

[WARNI:PA0205] simple/vloghammer.v:60 No timescale set for "test09".

[WARNI:PA0205] simple/vloghammer.v:68 No timescale set for "test10".

[WARNI:PA0205] techmap/mem_simple_4x1_tb.v:1 No timescale set for "tb".

[WARNI:PA0205] techmap/recursive_map.v:1 No timescale set for "sub".

[WARNI:PA0205] simple/task_func.v:2 No timescale set for "task_func_test01".

[WARNI:PA0205] simple/task_func.v:38 No timescale set for "task_func_test02".

[WARNI:PA0205] simple/task_func.v:71 No timescale set for "task_func_test03".

[WARNI:PA0205] simple/task_func.v:86 No timescale set for "task_func_test04".

[WARNI:PA0205] simple/task_func.v:127 No timescale set for "task_func_test05".

[WARNI:PA0205] various/abc9.v:1 No timescale set for "abc9_test027".

[WARNI:PA0205] various/abc9.v:7 No timescale set for "abc9_test028".

[WARNI:PA0205] svinterfaces/svinterface_at_top_ref.v:2 No timescale set for "TopModule".

[WARNI:PA0205] svinterfaces/svinterface_at_top_ref.v:43 No timescale set for "SubModule1".

[WARNI:PA0205] svinterfaces/svinterface_at_top_ref.v:92 No timescale set for "SubModule2".

[WARNI:PA0205] various/shregmap.v:1 No timescale set for "shregmap_static_test".

[WARNI:PA0205] arch/common/fsm.v:1 No timescale set for "fsm".

[WARNI:PA0205] various/muxpack.v:1 No timescale set for "mux_if_unbal_4_1".

[WARNI:PA0205] various/muxpack.v:10 No timescale set for "mux_if_unbal_5_3".

[WARNI:PA0205] various/muxpack.v:21 No timescale set for "mux_if_unbal_5_3_invert".

[WARNI:PA0205] various/muxpack.v:35 No timescale set for "mux_if_unbal_5_3_width_mismatch".

[WARNI:PA0205] various/muxpack.v:46 No timescale set for "mux_if_unbal_4_1_missing".

[WARNI:PA0205] various/muxpack.v:56 No timescale set for "mux_if_unbal_5_3_order".

[WARNI:PA0205] various/muxpack.v:67 No timescale set for "mux_if_unbal_4_1_nonexcl".

[WARNI:PA0205] various/muxpack.v:77 No timescale set for "mux_if_unbal_5_3_nonexcl".

[WARNI:PA0205] various/muxpack.v:89 No timescale set for "mux_case_unbal_8_7".

[WARNI:PA0205] various/muxpack.v:114 No timescale set for "mux_if_bal_8_2".

[WARNI:PA0205] various/muxpack.v:140 No timescale set for "mux_if_bal_5_1".

[WARNI:PA0205] various/muxpack.v:157 No timescale set for "cliffordwolf_nonexclusive_select".

[WARNI:PA0205] various/muxpack.v:170 No timescale set for "cliffordwolf_freduce".

[WARNI:PA0205] various/muxpack.v:183 No timescale set for "case_nonexclusive_select".

[WARNI:PA0205] various/muxpack.v:202 No timescale set for "case_nonoverlap".

[WARNI:PA0205] various/muxpack.v:221 No timescale set for "case_overlap".

[WARNI:PA0205] various/muxpack.v:241 No timescale set for "case_overlap2".

[WARNI:PA0205] techmap/mem_simple_4x1_map.v:2 No timescale set for "$mem".

[WARNI:PA0205] techmap/mem_simple_4x1_map.v:97 No timescale set for "$__mem_4x1_generator".

[WARNI:PA0205] arch/common/dffs.v:6 No timescale set for "dffe".

[WARNI:PA0205] arch/xilinx/macc.v:7 No timescale set for "macc".

[WARNI:PA0205] arch/xilinx/macc.v:44 No timescale set for "macc2".

[WARNI:PA0205] arch/common/latches.v:1 No timescale set for "latchp".

[WARNI:PA0205] arch/common/latches.v:7 No timescale set for "latchn".

[WARNI:PA0205] arch/common/latches.v:13 No timescale set for "latchsr".

[WARNI:PA0205] arch/common/mux.v:1 No timescale set for "mux2".

[WARNI:PA0205] arch/common/mux.v:10 No timescale set for "mux4".

[WARNI:PA0205] arch/common/mux.v:30 No timescale set for "mux8".

[WARNI:PA0205] arch/common/mux.v:54 No timescale set for "mux16".

[WARNI:PA0205] arch/ice40/macc.v:27 No timescale set for "top2".

[WARNI:PA0205] arch/xilinx/mul_unsigned.v:10 No timescale set for "mul_unsigned".

[WARNI:PA0205] arch/xilinx/xilinx_srl.v:1 No timescale set for "xilinx_srl_static_test".

[WARNI:PA0205] arch/xilinx/xilinx_srl.v:15 No timescale set for "xilinx_srl_variable_test".

[INFO :CP0300] Compilation...

[INFO :CP0303] techmap/mem_simple_4x1_map.v:2 Compile module "work@$mem".

[INFO :CP0303] techmap/mem_simple_4x1_map.v:97 Compile module "work@$__mem_4x1_generator".

[INFO :CP0303] hana/hana_vlib.v:511 Compile module "work@ADD1".

[INFO :CP0303] asicworld/code_verilog_tutorial_escape_id.v:3 Compile module "work@1dff".

[INFO :CP0303] hana/hana_vlib.v:517 Compile module "work@ADD2".

[INFO :CP0303] hana/hana_vlib.v:531 Compile module "work@ADD8".

[INFO :CP0303] hana/hana_vlib.v:545 Compile module "work@ADD32".

[INFO :CP0303] hana/hana_vlib.v:524 Compile module "work@ADD4".

[INFO :CP0303] hana/hana_vlib.v:538 Compile module "work@ADD16".

[INFO :CP0303] hana/hana_vlib.v:43 Compile module "work@AND3".

[INFO :CP0303] hana/hana_vlib.v:37 Compile module "work@AND2".

[INFO :CP0303] hana/hana_vlib.v:19 Compile module "work@BUF".

[INFO :CP0303] hana/hana_vlib.v:551 Compile module "work@ADD64".

[INFO :CP0303] hana/hana_vlib.v:1019 Compile module "work@CMP16".

[INFO :CP0303] hana/hana_vlib.v:914 Compile module "work@CMP1".

[INFO :CP0303] hana/hana_vlib.v:1045 Compile module "work@CMP32".

[INFO :CP0303] hana/hana_vlib.v:49 Compile module "work@AND4".

[INFO :CP0303] hana/hana_vlib.v:148 Compile module "work@DEC1".

[INFO :CP0303] hana/hana_vlib.v:941 Compile module "work@CMP2".

[INFO :CP0303] hana/hana_vlib.v:1071 Compile module "work@CMP64".

[INFO :CP0303] hana/hana_vlib.v:993 Compile module "work@CMP8".

[INFO :CP0303] hana/hana_vlib.v:221 Compile module "work@DEC5".

[INFO :CP0303] hana/hana_vlib.v:195 Compile module "work@DEC4".

[INFO :CP0303] hana/hana_vlib.v:654 Compile module "work@DIV2".

[INFO :CP0303] hana/hana_vlib.v:176 Compile module "work@DEC3".

[INFO :CP0303] hana/hana_vlib.v:670 Compile module "work@DIV8".

[INFO :CP0303] hana/hana_vlib.v:678 Compile module "work@DIV16".

[INFO :CP0303] asicworld/code_hdl_models_GrayCounter.v:7 Compile module "work@GrayCounter".

[INFO :CP0303] hana/hana_vlib.v:694 Compile module "work@DIV64".

[INFO :CP0303] hana/hana_vlib.v:647 Compile module "work@DIV1".

[INFO :CP0303] hana/hana_vlib.v:1131 Compile module "work@INC32".

[INFO :CP0303] hana/hana_vlib.v:662 Compile module "work@DIV4".

[INFO :CP0303] hana/hana_vlib.v:1100 Compile module "work@GND".

[INFO :CP0303] hana/hana_vlib.v:967 Compile module "work@CMP4".

[INFO :CP0303] hana/hana_vlib.v:1110 Compile module "work@INC2".

[INFO :CP0303] simple/multiplier.v:119 Compile module "work@FullAdder".

[INFO :CP0303] hana/hana_vlib.v:31 Compile module "work@INV".

[INFO :CP0303] hana/hana_vlib.v:1126 Compile module "work@INC16".

[INFO :CP0303] hana/hana_vlib.v:1121 Compile module "work@INC8".

[INFO :CP0303] hana/hana_vlib.v:161 Compile module "work@DEC2".

[INFO :CP0303] hana/hana_vlib.v:803 Compile module "work@LSHIFT16".

[INFO :CP0303] hana/hana_vlib.v:1135 Compile module "work@INC64".

[INFO :CP0303] hana/hana_vlib.v:771 Compile module "work@LSHIFT2".

[INFO :CP0303] hana/hana_vlib.v:759 Compile module "work@LSHIFT1".

[INFO :CP0303] hana/hana_vlib.v:823 Compile module "work@LSHIFT64".

[INFO :CP0303] hana/hana_vlib.v:264 Compile module "work@DEC6".

[INFO :CP0303] hana/hana_vlib.v:629 Compile module "work@MUL16".

[INFO :CP0303] hana/hana_vlib.v:782 Compile module "work@LSHIFT4".

[INFO :CP0303] hana/hana_vlib.v:793 Compile module "work@LSHIFT8".

[INFO :CP0303] hana/hana_vlib.v:605 Compile module "work@MUL1".

[INFO :CP0303] hana/hana_vlib.v:641 Compile module "work@MUL64".

[INFO :CP0303] hana/hana_vlib.v:686 Compile module "work@DIV32".

[INFO :CP0303] hana/hana_vlib.v:611 Compile module "work@MUL2".

[INFO :CP0303] hana/hana_vlib.v:702 Compile module "work@FF".

[INFO :CP0303] hana/hana_vlib.v:623 Compile module "work@MUL8".

[INFO :CP0303] hana/hana_vlib.v:617 Compile module "work@MUL4".

[INFO :CP0303] hana/hana_vlib.v:401 Compile module "work@MUX32".

[INFO :CP0303] hana/hana_vlib.v:341 Compile module "work@MUX2".

[INFO :CP0303] hana/hana_vlib.v:351 Compile module "work@MUX4".

[INFO :CP0303] hana/hana_vlib.v:1104 Compile module "work@INC1".

[INFO :CP0303] simple_abc9/abc9.v:216 Compile module "work@MUXF8".

[INFO :CP0303] hana/hana_vlib.v:1116 Compile module "work@INC4".

[INFO :CP0303] simple/multiplier.v:66 Compile module "work@Multiplier_2D".

[INFO :CP0303] hana/hana_vlib.v:744 Compile module "work@LATCH".

[INFO :CP0303] hana/hana_vlib.v:74 Compile module "work@NAND2".

[INFO :CP0303] hana/hana_vlib.v:363 Compile module "work@MUX8".

[INFO :CP0303] hana/hana_vlib.v:98 Compile module "work@NOR3".

[INFO :CP0303] hana/hana_vlib.v:813 Compile module "work@LSHIFT32".

[INFO :CP0303] hana/hana_vlib.v:67 Compile module "work@OR4".

[INFO :CP0303] techmap/mem_simple_4x1_cells.v:1 Compile module "work@MEM4X1".

[INFO :CP0303] hana/hana_vlib.v:833 Compile module "work@RSHIFT1".

[INFO :CP0303] simple/mem_arst.v:2 Compile module "work@MyMem".

[INFO :CP0303] hana/hana_vlib.v:80 Compile module "work@NAND3".

[INFO :CP0303] hana/hana_vlib.v:635 Compile module "work@MUL32".

[INFO :CP0303] hana/hana_vlib.v:857 Compile module "work@RSHIFT4".

[INFO :CP0303] hana/hana_vlib.v:92 Compile module "work@NOR2".

[INFO :CP0303] hana/hana_vlib.v:104 Compile module "work@NOR4".

[INFO :CP0303] hana/hana_vlib.v:378 Compile module "work@MUX16".

[INFO :CP0303] hana/hana_vlib.v:708 Compile module "work@RFF".

[INFO :CP0303] hana/hana_vlib.v:61 Compile module "work@OR3".

[INFO :CP0303] hana/hana_vlib.v:716 Compile module "work@SFF".

[INFO :CP0303] hana/hana_vlib.v:440 Compile module "work@MUX64".

[INFO :CP0303] hana/hana_vlib.v:564 Compile module "work@SUB2".

[INFO :CP0303] hana/hana_vlib.v:724 Compile module "work@RSFF".

[INFO :CP0303] hana/hana_vlib.v:578 Compile module "work@SUB8".

[INFO :CP0303] hana/hana_vlib.v:880 Compile module "work@RSHIFT16".

[INFO :CP0303] simple/multiplier.v:8 Compile module "work@Multiplier_flat".

[INFO :CP0303] hana/hana_vlib.v:892 Compile module "work@RSHIFT32".

[INFO :CP0303] svinterfaces/svinterface_at_top_ref.v:2 Compile module "work@TopModule".

[INFO :CP0303] hana/hana_vlib.v:903 Compile module "work@RSHIFT64".

[INFO :CP0303] hana/hana_vlib.v:142 Compile module "work@XNOR4".

[INFO :CP0303] simple/multiplier.v:98 Compile module "work@RippleCarryAdder".

[INFO :CP0303] hana/hana_vlib.v:86 Compile module "work@NAND4".

[INFO :CP0303] hana/hana_vlib.v:585 Compile module "work@SUB16".

[INFO :CP0303] errors/syntax_err04.v:1 Compile module "work@a".

[INFO :CP0303] hana/hana_vlib.v:55 Compile module "work@OR2".

[INFO :CP0303] hana/hana_vlib.v:598 Compile module "work@SUB64".

[INFO :CP0303] simple_abc9/abc9.v:9 Compile module "work@abc9_test003".

[INFO :CP0303] hana/hana_vlib.v:25 Compile module "work@TRIBUF".

[INFO :CP0303] hana/hana_vlib.v:750 Compile module "work@RLATCH".

[INFO :CP0303] hana/hana_vlib.v:136 Compile module "work@XNOR3".

[INFO :CP0303] hana/hana_vlib.v:844 Compile module "work@RSHIFT2".

[INFO :CP0303] simple_abc9/abc9.v:28 Compile module "work@abc9_test007".

[INFO :CP0303] hana/hana_vlib.v:868 Compile module "work@RSHIFT8".

[INFO :CP0303] hana/hana_vlib.v:123 Compile module "work@XOR4".

[INFO :CP0303] hana/hana_vlib.v:558 Compile module "work@SUB1".

[INFO :CP0303] simple_abc9/abc9.v:5 Compile module "work@abc9_test002".

[INFO :CP0303] simple_abc9/abc9.v:50 Compile module "work@abc9_test009".

[INFO :CP0303] simple_abc9/abc9.v:22 Compile module "work@abc9_test006".

[INFO :CP0303] hana/hana_vlib.v:571 Compile module "work@SUB4".

[INFO :CP0303] simple_abc9/abc9.v:46 Compile module "work@abc9_test008_sub".

[INFO :CP0303] simple_abc9/abc9.v:97 Compile module "work@abc9_test012_sub".

[INFO :CP0303] simple_abc9/abc9.v:74 Compile module "work@abc9_test012".

[INFO :CP0303] svinterfaces/svinterface_at_top_ref.v:92 Compile module "work@SubModule2".

[INFO :CP0303] hana/hana_vlib.v:734 Compile module "work@SRFF".

[INFO :CP0303] simple_abc9/abc9.v:108 Compile module "work@abc9_test015".

[INFO :CP0303] hana/hana_vlib.v:592 Compile module "work@SUB32".

[INFO :CP0303] hana/hana_vlib.v:130 Compile module "work@XNOR2".

[INFO :CP0303] svinterfaces/svinterface_at_top_ref.v:43 Compile module "work@SubModule1".

[INFO :CP0303] simple_abc9/abc9.v:132 Compile module "work@abc9_test019".

[INFO :CP0303] simple_abc9/abc9.v:243 Compile module "work@abc9_test023".

[INFO :CP0303] simple_abc9/abc9.v:114 Compile module "work@abc9_test016".

[INFO :CP0303] simple_abc9/abc9.v:266 Compile module "work@abc9_test026".

[INFO :CP0303] hana/hana_vlib.v:1097 Compile module "work@VCC".

[INFO :CP0303] simple_abc9/abc9.v:139 Compile module "work@abc9_test020".

[INFO :CP0303] hana/hana_vlib.v:117 Compile module "work@XOR3".

[INFO :CP0303] arch/common/adffs.v:1 Compile module "work@adff".

[INFO :CP0303] simple_abc9/abc9.v:1 Compile module "work@abc9_test001".

[INFO :CP0303] simple_abc9/abc9.v:254 Compile module "work@abc9_test024".

[INFO :CP0303] hana/hana_vlib.v:111 Compile module "work@XOR2".

[INFO :CP0303] various/abc9.v:1 Compile module "work@abc9_test027".

[INFO :CP0303] simple_abc9/abc9.v:17 Compile module "work@abc9_test005".

[INFO :CP0303] simple/implicit_ports.v:2 Compile module "work@alu".

[INFO :CP0303] simple/rotate.v:3 Compile module "work@a23_barrel_shift_fpga_rotate".

[INFO :CP0303] simple/arraycells.v:2 Compile module "work@array_test001".

[INFO :CP0303] simple_abc9/abc9.v:39 Compile module "work@abc9_test008".

[INFO :CP0303] simple/process.v:2 Compile module "work@blocking_cond".

[INFO :CP0303] simple_abc9/abc9.v:13 Compile module "work@abc9_test004".

[INFO :CP0303] arch/common/adffs.v:12 Compile module "work@adffn".

[INFO :CP0303] simple_abc9/abc9.v:66 Compile module "work@abc9_test011".

[INFO :CP0303] various/muxpack.v:183 Compile module "work@case_nonexclusive_select".

[INFO :CP0303] simple_abc9/abc9.v:35 Compile module "work@abc9_test007_sub".

[INFO :CP0303] various/muxpack.v:170 Compile module "work@cliffordwolf_freduce".

[INFO :CP0303] simple_abc9/abc9.v:93 Compile module "work@abc9_test014".

[INFO :CP0303] simple/constmuldivmod.v:1 Compile module "work@constmuldivmod".

[INFO :CP0303] simple_abc9/abc9.v:126 Compile module "work@abc9_test018".

[INFO :CP0303] simple_abc9/abc9.v:58 Compile module "work@abc9_test010".

[INFO :CP0303] simple_abc9/abc9.v:227 Compile module "work@abc9_test022".

[INFO :CP0303] sat/counters-repeat.v:18 Compile module "work@counter2".

[INFO :CP0303] simple_abc9/abc9.v:82 Compile module "work@abc9_test013".

[INFO :CP0303] simple_abc9/abc9.v:262 Compile module "work@abc9_test025".

[INFO :CP0303] simple_abc9/abc9.v:120 Compile module "work@abc9_test017".

[INFO :CP0303] asicworld/code_hdl_models_d_latch_gates.v:1 Compile module "work@d_latch_gates".

[INFO :CP0303] asicworld/code_verilog_tutorial_always_example.v:1 Compile module "work@always_example".

[INFO :CP0303] asicworld/code_verilog_tutorial_addbit.v:1 Compile module "work@addbit".

[INFO :CP0303] asicworld/code_tidbits_asyn_reset.v:1 Compile module "work@asyn_reset".

[INFO :CP0303] asicworld/code_hdl_models_decoder_using_assign.v:7 Compile module "work@decoder_using_assign".

[INFO :CP0303] asicworld/code_verilog_tutorial_bus_con.v:1 Compile module "work@bus_con".

[INFO :CP0303] simple/aes_kexp128.v:4 Compile module "work@aes_key_expand_128".

[INFO :CP0303] simple_abc9/abc9.v:147 Compile module "work@abc9_test021".

[INFO :CP0303] simple/realexpr.v:15 Compile module "work@demo_002".

[INFO :CP0303] asicworld/code_hdl_models_arbiter.v:5 Compile module "work@arbiter".

[INFO :CP0303] various/muxpack.v:202 Compile module "work@case_nonoverlap".

[INFO :CP0303] simple/dff_init.v:1 Compile module "work@dff0_test".

[INFO :CP0303] various/muxpack.v:157 Compile module "work@cliffordwolf_nonexclusive_select".

[INFO :CP0303] asicworld/code_tidbits_blocking.v:1 Compile module "work@blocking".

[INFO :CP0303] simple_abc9/abc9.v:258 Compile module "work@abc9_test024_sub".

[INFO :CP0303] asicworld/code_hdl_models_dff_async_reset.v:7 Compile module "work@dff_async_reset".

[INFO :CP0303] simple/constpower.v:1 Compile module "work@constpower".

[INFO :CP0303] simple/carryadd.v:1 Compile module "work@carryadd".

[INFO :CP0303] simple/sincos.v:6 Compile module "work@d".

[INFO :CP0303] simple/dff_different_styles.v:20 Compile module "work@dffa1".

[INFO :CP0303] various/abc9.v:7 Compile module "work@abc9_test028".

[INFO :CP0303] arch/common/dffs.v:6 Compile module "work@dffe".

[INFO :CP0303] simple/dff_different_styles.v:91 Compile module "work@dffsr2_sub".

[INFO :CP0303] asicworld/code_verilog_tutorial_decoder.v:1 Compile module "work@decoder".

[INFO :CP0303] simple/loops.v:6 Compile module "work@aes".

[INFO :CP0303] asicworld/code_verilog_tutorial_explicit.v:1 Compile module "work@explicit".

[INFO :CP0303] asicworld/code_hdl_models_decoder_using_case.v:7 Compile module "work@decoder_using_case".

[INFO :CP0303] simple/arraycells.v:10 Compile module "work@aoi12".

[INFO :CP0303] various/muxpack.v:241 Compile module "work@case_overlap2".

[INFO :CP0303] hana/test_simulation_shifter.v:57 Compile module "work@f10_test".

[INFO :CP0303] simple/realexpr.v:24 Compile module "work@demo_003".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:120 Compile module "work@f12_TECH_XOR2".

[INFO :CP0303] asicworld/code_hdl_models_clk_div_45.v:7 Compile module "work@clk_div_45".

[INFO :CP0303] hana/test_intermout.v:154 Compile module "work@f13_test".

[INFO :CP0303] simple/dff_init.v:22 Compile module "work@dff0a_test".

[INFO :CP0303] hana/test_intermout.v:163 Compile module "work@f14_test".

[INFO :CP0303] hana/test_intermout.v:187 Compile module "work@f15_test".

[INFO :CP0303] sat/counters-repeat.v:3 Compile module "work@counter1".

[INFO :CP0303] asicworld/code_hdl_models_dff_sync_reset.v:7 Compile module "work@dff_sync_reset".

[INFO :CP0303] asicworld/code_hdl_models_d_ff_gates.v:1 Compile module "work@d_ff_gates".

[INFO :CP0303] simple/dff_different_styles.v:31 Compile module "work@dffa2".

[INFO :CP0303] hana/test_intermout.v:256 Compile module "work@f19_buffer".

[INFO :CP0303] arch/common/adffs.v:23 Compile module "work@dffs".

[INFO :CP0303] asicworld/code_hdl_models_encoder_4to2_gates.v:1 Compile module "work@encoder_4to2_gates".

[INFO :CP0303] asicworld/code_verilog_tutorial_decoder_always.v:1 Compile module "work@decoder_always".

[INFO :CP0303] hana/test_intermout.v:267 Compile module "work@f20_test".

[INFO :CP0303] hana/test_simulation_always.v:112 Compile module "work@f10_FlipFlop".

[INFO :CP0303] hana/test_intermout.v:314 Compile module "work@f24_test".

[INFO :CP0303] simple/realexpr.v:1 Compile module "work@demo_001".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:112 Compile module "work@f11_TECH_XOR2".

[INFO :CP0303] hana/test_intermout.v:359 Compile module "work@f28_test".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:117 Compile module "work@f12_TECH_XOR5".

[INFO :CP0303] asicworld/code_verilog_tutorial_explicit.v:19 Compile module "work@dff".

[INFO :CP0303] hana/test_parser.v:7 Compile module "work@f2_test".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:133 Compile module "work@f14_TECH_XOR2".

[INFO :CP0303] hana/test_intermout.v:409 Compile module "work@f33_test".

[INFO :CP0303] simple/dff_init.v:33 Compile module "work@dff1a_test".

[INFO :CP0303] simple/attrib04_net_var.v:1 Compile module "work@bar".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:141 Compile module "work@f15_TECH_XOR2".

[INFO :CP0303] hana/test_parser.v:19 Compile module "work@f3_test".

[INFO :CP0303] hana/test_intermout.v:222 Compile module "work@f16_test".

[INFO :CP0303] asicworld/code_hdl_models_cam.v:7 Compile module "work@cam".

[INFO :CP0303] simple/dff_different_styles.v:9 Compile module "work@dffa".

[INFO :CP0303] hana/test_parser.v:34 Compile module "work@f4_ahmad".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:3 Compile module "work@f1_TECH_AND18".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:51 Compile module "work@f5_TECH_NAND2".

[INFO :CP0303] simple/dff_different_styles.v:53 Compile module "work@dffa4".

[INFO :CP0303] hana/test_intermout.v:280 Compile module "work@f21_test".

[INFO :CP0303] hana/test_parser.v:41 Compile module "work@f5_test".

[INFO :CP0303] various/muxpack.v:221 Compile module "work@case_overlap".

[INFO :CP0303] simple/dff_different_styles.v:83 Compile module "work@dffsr2".

[INFO :CP0303] asicworld/code_hdl_models_clk_div.v:8 Compile module "work@clk_div".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:64 Compile module "work@f6_TECH_NOR2".

[INFO :CP0303] hana/test_intermout.v:326 Compile module "work@f25_test".

[INFO :CP0303] asicworld/code_hdl_models_encoder_using_if.v:7 Compile module "work@encoder_using_if".

[INFO :CP0303] asicworld/code_verilog_tutorial_counter.v:7 Compile module "work@counter".

[INFO :CP0303] hana/test_simulation_always.v:74 Compile module "work@f7_FlipFlop".

[INFO :CP0303] hana/test_intermout.v:366 Compile module "work@f29_Reduction".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:104 Compile module "work@f10_TECH_OR5".

[INFO :CP0303] hana/test_intermout.v:384 Compile module "work@f30_test".

[INFO :CP0303] hana/test_parser.v:80 Compile module "work@f7_test".

[INFO :CP0303] asicworld/code_verilog_tutorial_d_ff.v:2 Compile module "work@d_ff".

[INFO :CP0303] hana/test_simulation_always.v:127 Compile module "work@f11_test".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:17 Compile module "work@f3_TECH_NAND18".

[INFO :CP0303] asicworld/code_hdl_models_decoder_2to4_gates.v:1 Compile module "work@decoder_2to4_gates".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:125 Compile module "work@f13_TECH_XOR2".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:30 Compile module "work@f4_TECH_NAND18".

[INFO :CP0303] hana/test_intermout.v:175 Compile module "work@f14_mybuf".

[INFO :CP0303] hana/test_simulation_and.v:18 Compile module "work@f4_test".

[INFO :CP0303] hana/test_intermout.v:210 Compile module "work@f15_mybuf".

[INFO :CP0303] simple/muxtree.v:56 Compile module "work@default_cases".

[INFO :CP0303] hana/test_simulation_always.v:87 Compile module "work@f8_inc".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:47 Compile module "work@f5_TECH_NAND4".

[INFO :CP0303] hana/test_intermout.v:249 Compile module "work@f18_test".

[INFO :CP0303] hana/test_intermout.v:71 Compile module "work@f6_FlipFlop".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:95 Compile module "work@f9_TECH_OR18".

[INFO :CP0303] simple/realexpr.v:30 Compile module "work@demo_004".

[INFO :CP0303] hana/test_parser.v:3 Compile module "work@f1_test".

[INFO :CP0303] simple/dff_init.v:11 Compile module "work@dff1_test".

[INFO :CP0303] asicworld/code_verilog_tutorial_flip_flop.v:1 Compile module "work@flif_flop".

[INFO :CP0303] simple/dff_init.v:44 Compile module "work@dff_test_997".

[INFO :CP0303] arch/common/fsm.v:1 Compile module "work@fsm".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:60 Compile module "work@f6_TECH_NOR4".

[INFO :CP0303] asicworld/code_tidbits_fsm_using_function.v:6 Compile module "work@fsm_using_function".

[INFO :CP0303] simple/dff_different_styles.v:42 Compile module "work@dffa3".

[INFO :CP0303] hana/test_intermout.v:305 Compile module "work@f23_test".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:69 Compile module "work@f7_TECH_NOR18".

[INFO :CP0303] proc/bug_1268.v:13 Compile module "work@gate".

[INFO :CP0303] simple/dff_different_styles.v:72 Compile module "work@dffsr1".

[INFO :CP0303] hana/test_intermout.v:347 Compile module "work@f27_test".

[INFO :CP0303] simple/generate.v:97 Compile module "work@gen_test4".

[INFO :CP0303] asicworld/code_hdl_models_encoder_using_case.v:7 Compile module "work@encoder_using_case".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:82 Compile module "work@f8_TECH_NOR18".

[INFO :CP0303] hana/test_simulation_shifter.v:45 Compile module "work@f8_test".

[INFO :CP0303] hana/test_parse2synthtrans.v:27 Compile module "work@f2_demultiplexer1_to_4".

[INFO :CP0303] hana/test_intermout.v:121 Compile module "work@f10_MyCounter".

[INFO :CP0303] proc/bug_1268.v:1 Compile module "work@gold".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:109 Compile module "work@f11_TECH_XOR5".

[INFO :CP0303] hana/test_intermout.v:403 Compile module "work@f32_test".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:99 Compile module "work@f9_TECH_OR4".

[INFO :CP0303] simple/hierdefparam.v:11 Compile module "work@hierdefparam_a".

[INFO :CP0303] hana/test_intermout.v:148 Compile module "work@f12_test".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:21 Compile module "work@f3_TECH_NAND4".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:130 Compile module "work@f14_TECH_XOR5".

[INFO :CP0303] simple/i2c_master_tests.v:29 Compile module "work@i2c_test02".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:138 Compile module "work@f15_TECH_XOR5".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:34 Compile module "work@f4_TECH_NAND4".

[INFO :CP0303] hana/test_intermout.v:234 Compile module "work@f17_test".

[INFO :CP0303] various/pmux2shiftx.v:36 Compile module "work@issue01135".

[INFO :CP0303] simple/attrib04_net_var.v:24 Compile module "work@foo".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:43 Compile module "work@f5_TECH_NAND18".

[INFO :CP0303] asicworld/code_verilog_tutorial_fsm_full.v:1 Compile module "work@fsm_full".

[INFO :CP0303] arch/common/latches.v:13 Compile module "work@latchsr".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:7 Compile module "work@f1_TECH_AND4".

[INFO :CP0303] hana/test_parser.v:53 Compile module "work@f5_ternaryop".

[INFO :CP0303] asicworld/code_tidbits_fsm_using_single_always.v:7 Compile module "work@fsm_using_single_always".

[INFO :CP0303] arch/xilinx/macc.v:44 Compile module "work@macc2".

[INFO :CP0303] hana/test_intermout.v:291 Compile module "work@f22_test".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:56 Compile module "work@f6_TECH_NOR18".

[INFO :CP0303] simple/generate.v:2 Compile module "work@gen_test1".

[INFO :CP0303] simple/mem2reg.v:64 Compile module "work@mem2reg_test4".

[INFO :CP0303] hana/test_intermout.v:335 Compile module "work@f26_test".

[INFO :CP0303] hana/test_simulation_and.v:28 Compile module "work@f6_test".

[INFO :CP0303] simple/generate.v:118 Compile module "work@gen_test5".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:12 Compile module "work@f2_TECH_AND5".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:73 Compile module "work@f7_TECH_NOR4".

[INFO :CP0303] simple/graphtest.v:1 Compile module "work@graphtest".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:86 Compile module "work@f8_TECH_NOR4".

[INFO :CP0303] simple/hierdefparam.v:22 Compile module "work@hierdefparam_b".

[INFO :CP0303] hana/test_intermout.v:396 Compile module "work@f31_test".

[INFO :CP0303] hana/test_intermout.v:108 Compile module "work@f9_NegEdgeClock".

[INFO :CP0303] asicworld/code_verilog_tutorial_if_else.v:1 Compile module "work@if_else".

[INFO :CP0303] asicworld/code_verilog_tutorial_first_counter.v:9 Compile module "work@first_counter".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:25 Compile module "work@f3_TECH_NAND2".

[INFO :CP0303] simple/memory.v:19 Compile module "work@memtest01".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:38 Compile module "work@f4_TECH_NAND2".

[INFO :CP0303] simple/forloops.v:15 Compile module "work@forloops02".

[INFO :CP0303] simple/memory.v:119 Compile module "work@memtest05".

[INFO :CP0303] hana/test_intermout.v:54 Compile module "work@f5_NonBlockingEx".

[INFO :CP0303] various/specify.v:35 Compile module "work@issue01144".

[INFO :CP0303] hana/test_parser.v:62 Compile module "work@f5_fulladd4".

[INFO :CP0303] asicworld/code_hdl_models_lfsr.v:7 Compile module "work@lfsr".

[INFO :CP0303] simple/mem2reg.v:2 Compile module "work@mem2reg_test1".

[INFO :CP0303] asicworld/code_tidbits_fsm_using_always.v:6 Compile module "work@fsm_using_always".

[INFO :CP0303] simple/mem2reg.v:86 Compile module "work@mem2reg_test5".

[INFO :CP0303] hana/test_simulation_always.v:57 Compile module "work@f6_NonBlockingEx".

[INFO :CP0303] asicworld/code_hdl_models_full_subtracter_gates.v:7 Compile module "work@full_subtracter_gates".

[INFO :CP0303] simple/memory.v:39 Compile module "work@memtest02".

[INFO :CP0303] simple/memory.v:200 Compile module "work@memtest08".

[INFO :CP0303] simple/generate.v:70 Compile module "work@gen_test3".

[INFO :CP0303] simple/memory.v:159 Compile module "work@memtest06_async".

[INFO :CP0303] simple/memory.v:269 Compile module "work@memtest12".

[INFO :CP0303] hana/test_parser.v:72 Compile module "work@f6_adder".

[INFO :CP0303] memories/amber23_sram_byte_en.v:45 Compile module "work@generic_sram_byte_en".

[INFO :CP0303] simple/memory.v:210 Compile module "work@memtest09".

[INFO :CP0303] arch/common/mux.v:54 Compile module "work@mux16".

[INFO :CP0303] simple/memory.v:282 Compile module "work@memtest13".

[INFO :CP0303] asicworld/code_hdl_models_half_adder_gates.v:7 Compile module "work@half_adder_gates".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:77 Compile module "work@f7_TECH_NOR2".

[INFO :CP0303] asicworld/code_verilog_tutorial_mux_21.v:1 Compile module "work@mux_21".

[INFO :CP0303] hana/test_simulation_techmap_tech.v:90 Compile module "work@f8_TECH_NOR2".

[INFO :CP0303] simple/i2c_master_tests.v:6 Compile module "work@i2c_test01".

[INFO :CP0303] arch/common/mux.v:1 Compile module "work@mux2".

[INFO :CP0303] various/muxpack.v:114 Compile module "work@mux_if_bal_8_2".

[INFO :CP0303] hana/test_simulation_always.v:96 Compile module "work@f9_MyCounter".

[INFO :CP0303] simple/paramods.v:42 Compile module "work@inc".

[INFO :CP0303] asicworld/code_hdl_models_mux_2to1_gates.v:7 Compile module "work@mux_2to1_gates".

[INFO :CP0303] various/muxpack.v:10 Compile module "work@mux_if_unbal_5_3".

[INFO :CP0303] arch/common/latches.v:1 Compile module "work@latchp".

[INFO :CP0303] various/muxpack.v:1 Compile module "work@mux_if_unbal_4_1".

[INFO :CP0303] various/muxpack.v:35 Compile module "work@mux_if_unbal_5_3_width_mismatch".

[INFO :CP0303] hana/test_simulation_shifter.v:51 Compile module "work@f9_test".

[INFO :CP0303] arch/xilinx/macc.v:7 Compile module "work@macc".

[INFO :CP0303] various/muxpack.v:21 Compile module "work@mux_if_unbal_5_3_invert".

[INFO :CP0303] simple/mem2reg.v:53 Compile module "work@mem2reg_test3".

[INFO :CP0303] simple/forloops.v:1 Compile module "work@forloops01".

[INFO :CP0303] asicworld/code_hdl_models_mux_using_assign.v:7 Compile module "work@mux_using_assign".

[INFO :CP0303] asicworld/code_verilog_tutorial_n_out_primitive.v:1 Compile module "work@n_out_primitive".

[INFO :CP0303] simple/implicit_ports.v:7 Compile module "work@named_ports".

[INFO :CP0303] simple/fsm.v:4 Compile module "work@fsm_test".

[INFO :CP0303] asicworld/code_hdl_models_one_hot_cnt.v:7 Compile module "work@one_hot_cnt".

[INFO :CP0303] simple/omsp_dbg_uart.v:2 Compile module "work@omsp_dbg_uart".

[INFO :CP0303] simple/memory.v:2 Compile module "work@memtest00".

[INFO :CP0303] asicworld/code_hdl_models_full_adder_gates.v:7 Compile module "work@full_adder_gates".

[INFO :CP0303] asicworld/code_hdl_models_parallel_crc.v:7 Compile module "work@parallel_crc_ccitt".

[INFO :CP0303] simple/operators.v:1 Compile module "work@optest".

[INFO :CP0303] simple/generate.v:43 Compile module "work@gen_test2".

[INFO :CP0303] asicworld/code_hdl_models_parity_using_bitwise.v:7 Compile module "work@parity_using_bitwise".

[INFO :CP0303] asicworld/code_hdl_models_parity_using_assign.v:7 Compile module "work@parity_using_assign".

[INFO :CP0303] simple/memory.v:98 Compile module "work@memtest04".

[INFO :CP0303] simple/partsel.v:7 Compile module "work@partsel_test002".

[INFO :CP0303] simple/paramods.v:2 Compile module "work@pm_test1".

[INFO :CP0303] simple/generate.v:154 Compile module "work@gen_test6".

[INFO :CP0303] asicworld/code_hdl_models_pri_encoder_using_assign.v:7 Compile module "work@pri_encoder_using_assign".

[INFO :CP0303] simple/memory.v:180 Compile module "work@memtest07".

[INFO :CP0303] various/pmux2shiftx.v:1 Compile module "work@pmux2shiftx_test".

[INFO :CP0303] asicworld/code_hdl_models_gray_counter.v:7 Compile module "work@gray_counter".

[INFO :CP0303] simple/memory.v:249 Compile module "work@memtest11".

[INFO :CP0303] simple/repwhile.v:1 Compile module "work@repwhile_test001".

[INFO :CP0303] asicworld/code_tidbits_reg_seq_example.v:1 Compile module "work@reg_seq_example".

[INFO :CP0303] simple/hierdefparam.v:3 Compile module "work@hierdefparam_top".

[INFO :CP0303] asicworld/code_verilog_tutorial_multiply.v:1 Compile module "work@muliply".

[INFO :CP0303] simple/muxtree.v:76 Compile module "work@select_leaves".

[INFO :CP0303] simple/scopes.v:1 Compile module "work@scopes_test_01".

[INFO :CP0304] errors/syntax_err12.v:1 Compile interface "work@iface".

[INFO :CP0303] simple/signedexpr.v:1 Compile module "work@signed_test01".

[INFO :CP0303] asicworld/code_verilog_tutorial_simple_function.v:1 Compile module "work@simple_function".

[INFO :CP0303] arch/common/mux.v:30 Compile module "work@mux8".

[INFO :CP0303] simple/subbytes.v:4 Compile module "work@subbytes_00".

[INFO :CP0303] arch/common/latches.v:7 Compile module "work@latchn".

[INFO :CP0303] techmap/recursive_map.v:1 Compile module "work@sub".

[INFO :CP0303] various/muxpack.v:140 Compile module "work@mux_if_bal_5_1".

[INFO :CP0303] svinterfaces/svinterface_at_top_tb.v:3 Compile module "work@svinterface_at_top_tb".

[INFO :CP0303] asicworld/code_hdl_models_lfsr_updown.v:1 Compile module "work@lfsr_updown".

[INFO :CP0303] asicworld/code_specman_switch_fabric.v:1 Compile module "work@switch_fabric".

[INFO :CP0303] various/muxpack.v:67 Compile module "work@mux_if_unbal_4_1_nonexcl".

[INFO :CP0303] svinterfaces/svinterface_at_top_tb_wrapper.v:3 Compile module "work@svinterface_at_top_tb_wrapper".

[INFO :CP0303] simple/mem2reg.v:22 Compile module "work@mem2reg_test2".

[INFO :CP0303] various/muxpack.v:56 Compile module "work@mux_if_unbal_5_3_order".

[INFO :CP0303] asicworld/code_tidbits_syn_reset.v:1 Compile module "work@syn_reset".

[INFO :CP0303] simple/task_func.v:71 Compile module "work@task_func_test03".

[INFO :CP0303] simple/mem2reg.v:97 Compile module "work@mem2reg_test6".

[INFO :CP0303] simple/task_func.v:86 Compile module "work@task_func_test04".

[INFO :CP0303] asicworld/code_hdl_models_mux_using_if.v:7 Compile module "work@mux_using_if".

[INFO :CP0303] simple/memory.v:80 Compile module "work@memtest03".

[INFO :CP0303] techmap/mem_simple_4x1_tb.v:1 Compile module "work@tb".

[INFO :CP0303] asicworld/code_tidbits_nonblocking.v:1 Compile module "work@nonblocking".

[INFO :CP0303] memories/implicit_en.v:4 Compile module "work@test".

[INFO :CP0303] simple/memory.v:140 Compile module "work@memtest06_sync".

[INFO :CP0303] simple/vloghammer.v:24 Compile module "work@test04".

[INFO :CP0303] opt/opt_share_add_sub.v:1 Compile module "work@opt_share_test".

[INFO :CP0303] asicworld/code_verilog_tutorial_parity.v:9 Compile module "work@parity".

[INFO :CP0303] simple/vloghammer.v:17 Compile module "work@test03".

[INFO :CP0303] simple/partsel.v:1 Compile module "work@partsel_test001".

[INFO :CP0303] sat/expose_dff.v:2 Compile module "work@test1".

[INFO :CP0303] simple/memory.v:233 Compile module "work@memtest10".

[INFO :CP0303] simple/paramods.v:26 Compile module "work@pm_test3".

[INFO :CP0303] sat/expose_dff.v:25 Compile module "work@test4".

[INFO :CP0303] arch/xilinx/mul_unsigned.v:10 Compile module "work@mul_unsigned".

[INFO :CP0303] sat/asserts_seq.v:54 Compile module "work@test_004".

[INFO :CP0303] simple/macros.v:241 Compile module "work@test_comment_in_macro".

[INFO :CP0303] simple/vloghammer.v:60 Compile module "work@test09".

[INFO :CP0303] simple/values.v:2 Compile module "work@test_signed".

[INFO :CP0303] arch/common/mux.v:10 Compile module "work@mux4".

[INFO :CP0303] sat/expose_dff.v:17 Compile module "work@test3".

[INFO :CP0303] asicworld/code_hdl_models_tff_sync_reset.v:7 Compile module "work@tff_sync_reset".

[INFO :CP0303] asicworld/code_tidbits_reg_combo_example.v:1 Compile module "work@reg_combo_example".

[INFO :CP0303] various/muxpack.v:89 Compile module "work@mux_case_unbal_8_7".

[INFO :CP0303] sat/asserts_seq.v:37 Compile module "work@test_003".

[INFO :CP0303] arch/common/tribuf.v:1 Compile module "work@tristate".

[INFO :CP0303] sat/share.v:12 Compile module "work@test_2".

[INFO :CP0303] various/muxpack.v:46 Compile module "work@mux_if_unbal_4_1_missing".

[INFO :CP0303] asicworld/code_hdl_models_rom_using_case.v:7 Compile module "work@rom_using_case".

[INFO :CP0303] various/muxpack.v:77 Compile module "work@mux_if_unbal_5_3_nonexcl".

[INFO :CP0303] simple/macros.v:19 Compile module "work@test_ifdef".

[INFO :CP0303] asicworld/code_hdl_models_mux_using_case.v:7 Compile module "work@mux_using_case".

[INFO :CP0303] various/shregmap.v:1 Compile module "work@shregmap_static_test".

[INFO :CP0303] asicworld/code_hdl_models_up_counter.v:7 Compile module "work@up_counter".

[INFO :CP0303] liberty/small.v:3 Compile module "work@small".

[INFO :CP0303] arch/common/adffs.v:34 Compile module "work@ndffnr".

[INFO :CP0303] asicworld/code_hdl_models_tff_async_reset.v:7 Compile module "work@tff_async_reset".

[INFO :CP0303] simple/muxtree.v:5 Compile module "work@usb_tx_phy".

[INFO :CP0303] svinterfaces/svinterface1_tb.v:3 Compile module "work@svinterface1_tb".

[INFO :CP0303] opt/opt_rmdff.v:1 Compile module "work@opt_rmdff_test".

[INFO :CP0303] asicworld/code_specman_switch_fabric.v:51 Compile module "work@switch".

[INFO :CP0303] simple/always03.v:1 Compile module "work@uut_always03".

[INFO :CP0303] asicworld/code_verilog_tutorial_tri_buf.v:1 Compile module "work@tri_buf".

[INFO :CP0303] simple/fiedler-cooley.v:3 Compile module "work@up3down5".

[INFO :CP0303] simple/localparam_attr.v:1 Compile module "work@uut_localparam_attr".

[INFO :CP0303] simple/usb_phy_tests.v:3 Compile module "work@usb_phy_test01".

[INFO :CP0303] asicworld/code_verilog_tutorial_parallel_if.v:1 Compile module "work@parallel_if".

[INFO :CP0303] simple/task_func.v:38 Compile module "work@task_func_test02".

[INFO :CP0303] simple/wandwor.v:13 Compile module "work@wandwor_test1".

[INFO :CP0303] simple/always02.v:1 Compile module "work@uut_always02".

[INFO :CP0303] asicworld/code_hdl_models_parity_using_function.v:7 Compile module "work@parity_using_function".

[INFO :CP0303] simple/forgen02.v:1 Compile module "work@uut_forgen02".

[INFO :CP0303] simple/paramods.v:14 Compile module "work@pm_test2".

[INFO :CP0303] simple/wandwor.v:1 Compile module "work@wandwor_test0".

[INFO :CP0303] simple/wreduce.v:7 Compile module "work@wreduce_test1".

[INFO :CP0303] asicworld/code_verilog_tutorial_task_global.v:1 Compile module "work@task_global".

[INFO :CP0303] memories/issue00335.v:5 Compile module "work@ram2".

[INFO :CP0303] simple/wreduce.v:1 Compile module "work@wreduce_test0".

[INFO :CP0303] simple/vloghammer.v:11 Compile module "work@test02".

[INFO :CP0303] simple/retime.v:1 Compile module "work@retime_test".

[INFO :CP0303] asicworld/code_hdl_models_serial_crc.v:7 Compile module "work@serial_crc_ccitt".

[INFO :CP0303] simple/vloghammer.v:53 Compile module "work@test08".

[INFO :CP0303] asicworld/code_verilog_tutorial_simple_if.v:1 Compile module "work@simple_if".

[INFO :CP0303] sat/expose_dff.v:7 Compile module "work@test2".

[INFO :CP0303] simple/hierarchy.v:16 Compile module "work@submod".

[INFO :CP0303] sat/asserts_seq.v:20 Compile module "work@test_002".

[INFO :CP0303] svinterfaces/svinterface_at_top_wrapper.v:3 Compile module "work@svinterface_at_top_wrapper".

[INFO :CP0303] simple/task_func.v:2 Compile module "work@task_func_test01".

[INFO :CP0303] sat/share.v:1 Compile module "work@test_1".

[INFO :CP0303] simple/task_func.v:127 Compile module "work@task_func_test05".

[INFO :CP0303] simple/macros.v:2 Compile module "work@test_def".

[INFO :CP0303] simple/vloghammer.v:5 Compile module "work@test01".

[INFO :CP0303] asicworld/code_verilog_tutorial_counter_tb.v:16 Compile module "work@testbench".

[INFO :CP0303] simple/vloghammer.v:46 Compile module "work@test07".

[INFO :CP0303] arch/ice40/macc.v:27 Compile module "work@top2".

[INFO :CP0303] simple/vloghammer.v:68 Compile module "work@test10".

[INFO :CP0303] simple/undef_eqx_nex.v:1 Compile module "work@undef_eqx_nex".

[INFO :CP0303] asicworld/code_hdl_models_up_down_counter.v:7 Compile module "work@up_down_counter".

[INFO :CP0303] sat/asserts_seq.v:1 Compile module "work@test_001".

[INFO :CP0303] simple/always01.v:1 Compile module "work@uut_always01".

[INFO :CP0303] sat/asserts_seq.v:71 Compile module "work@test_005".

[INFO :CP0303] simple/forgen01.v:4 Compile module "work@uut_forgen01".

[INFO :CP0303] simple/values.v:17 Compile module "work@test_const".

[INFO :CP0303] asicworld/code_verilog_tutorial_v2k_reg.v:1 Compile module "work@v2k_reg".

[INFO :CP0303] simple/specify.v:1 Compile module "work@test_specify".

[INFO :CP0303] asicworld/code_tidbits_wire_example.v:1 Compile module "work@wire_example".

[INFO :CP0303] opt/opt_lut.v:1 Compile module "work@top".

[INFO :CP0303] arch/xilinx/xilinx_srl.v:15 Compile module "work@xilinx_srl_variable_test".

[INFO :CP0303] asicworld/code_hdl_models_uart.v:7 Compile module "work@uart".

[INFO :CP0303] asicworld/code_hdl_models_up_counter_load.v:7 Compile module "work@up_counter_load".

[INFO :CP0303] simple/process.v:21 Compile module "work@uut".

[INFO :CP0303] simple/arrays01.v:1 Compile module "work@uut_arrays01".

[INFO :CP0303] simple/param_attr.v:1 Compile module "work@uut_param_attr".

[INFO :CP0303] asicworld/code_verilog_tutorial_which_clock.v:1 Compile module "work@which_clock".

[INFO :CP0303] arch/xilinx/xilinx_srl.v:1 Compile module "work@xilinx_srl_static_test".

[NOTE :CP0309] techmap/mem_simple_4x1_map.v:97 Implicit port type (wire) for "RD_DATA".

[NOTE :CP0309] hana/hana_vlib.v:539 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:552 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:49 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:942 Implicit port type (wire) for "unequal",
there are 2 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:994 Implicit port type (wire) for "unequal",
there are 2 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:679 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:695 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:1100 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:1110 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:1121 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:629 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:641 Implicit port type (wire) for "out".

[NOTE :CP0309] simple_abc9/abc9.v:217 Implicit port type (wire) for "O".

[NOTE :CP0309] hana/hana_vlib.v:74 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:98 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:67 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:565 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:579 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:142 Implicit port type (wire) for "out".

[NOTE :CP0309] simple_abc9/abc9.v:9 Implicit port type (wire) for "o".

[NOTE :CP0309] simple_abc9/abc9.v:28 Implicit port type (wire) for "o".

[NOTE :CP0309] simple_abc9/abc9.v:50 Implicit port type (wire) for "io".

[NOTE :CP0309] simple_abc9/abc9.v:97 Implicit port type (wire) for "io".

[NOTE :CP0309] simple_abc9/abc9.v:114 Implicit port type (wire) for "b".

[NOTE :CP0309] simple_abc9/abc9.v:139 Implicit port type (wire) for "b".

[NOTE :CP0309] simple_abc9/abc9.v:254 Implicit port type (wire) for "o".

[NOTE :CP0309] asicworld/code_verilog_tutorial_bus_con.v:1 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/constpower.v:1 Implicit port type (wire) for "ys",
there are 1 more instances of this message.

[NOTE :CP0309] asicworld/code_verilog_tutorial_decoder.v:1 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/realexpr.v:24 Implicit port type (wire) for "A",
there are 1 more instances of this message.

[NOTE :CP0309] simple/dff_init.v:22 Implicit port type (wire) for "n1_inv".

[NOTE :CP0309] asicworld/code_hdl_models_encoder_4to2_gates.v:1 Implicit port type (wire) for "y".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:112 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:117 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:133 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:141 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:222 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:3 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:280 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_intermout.v:326 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_intermout.v:366 Implicit port type (wire) for "Y1",
there are 5 more instances of this message.

[NOTE :CP0309] hana/test_intermout.v:384 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:17 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:30 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_and.v:18 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:47 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:71 Implicit port type (wire) for "ns".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:60 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:69 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:82 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_shifter.v:45 Implicit port type (wire) for "OUT".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:99 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/generate.v:118 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/graphtest.v:1 Implicit port type (wire) for "Y",
there are 1 more instances of this message.

[NOTE :CP0309] simple/hierdefparam.v:22 Implicit port type (wire) for "Y".

[NOTE :CP0309] various/specify.v:35 Implicit port type (wire) for "q".

[NOTE :CP0309] simple/mem2reg.v:86 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/memory.v:39 Implicit port type (wire) for "y3",
there are 1 more instances of this message.

[NOTE :CP0309] simple/memory.v:159 Implicit port type (wire) for "dout".

[NOTE :CP0309] simple/memory.v:214 Implicit port type (wire) for "b_dout".

[NOTE :CP0309] simple/memory.v:288 Implicit port type (wire) for "dout2".

[NOTE :CP0309] asicworld/code_hdl_models_mux_2to1_gates.v:7 Implicit port type (wire) for "y".

[NOTE :CP0309] asicworld/code_hdl_models_mux_using_assign.v:11 Implicit port type (wire) for "mux_out".

[NOTE :CP0309] simple/implicit_ports.v:7 Implicit port type (wire) for "alu_result",
there are 1 more instances of this message.

[NOTE :CP0309] asicworld/code_hdl_models_parallel_crc.v:13 Implicit port type (wire) for "crc_out".

[NOTE :CP0309] asicworld/code_hdl_models_parity_using_bitwise.v:9 Implicit port type (wire) for "parity_out".

[NOTE :CP0309] simple/paramods.v:2 Implicit port type (wire) for "x",
there are 1 more instances of this message.

[NOTE :CP0309] asicworld/code_hdl_models_pri_encoder_using_assign.v:8 Implicit port type (wire) for "binary_out".

[NOTE :CP0309] simple/repwhile.v:1 Implicit port type (wire) for "y",
there are 1 more instances of this message.

[NOTE :CP0309] simple/task_func.v:86 Implicit port type (wire) for "out1",
there are 3 more instances of this message.

[NOTE :CP0309] simple/vloghammer.v:24 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/macros.v:241 Implicit port type (wire) for "dout_a".

[NOTE :CP0309] simple/wandwor.v:13 Implicit port type (wire) for "X",
there are 2 more instances of this message.

[NOTE :CP0309] simple/wreduce.v:7 Implicit port type (wire) for "x",
there are 3 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:518 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:532 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:19 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:1046 Implicit port type (wire) for "unequal",
there are 2 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:655 Implicit port type (wire) for "out",
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[NOTE :CP0309] hana/hana_vlib.v:671 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:1131 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:31 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:611 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:623 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/multiplier.v:69 Implicit port type (wire) for "P".

[NOTE :CP0309] hana/hana_vlib.v:80 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:104 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:593 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:1097 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:111 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/rotate.v:3 Implicit port type (wire) for "rot_prod".

[NOTE :CP0309] simple_abc9/abc9.v:13 Implicit port type (wire) for "o".

[NOTE :CP0309] simple_abc9/abc9.v:35 Implicit port type (wire) for "b".

[NOTE :CP0309] simple_abc9/abc9.v:58 Implicit port type (wire) for "io".

[NOTE :CP0309] simple_abc9/abc9.v:82 Implicit port type (wire) for "io".

[NOTE :CP0309] simple_abc9/abc9.v:120 Implicit port type (wire) for "b".

[NOTE :CP0309] simple_abc9/abc9.v:147 Implicit port type (wire) for "s_eth_hdr_ready",
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[NOTE :CP0309] simple_abc9/abc9.v:258 Implicit port type (wire) for "o".

[NOTE :CP0309] various/abc9.v:7 Implicit port type (wire) for "o".

[NOTE :CP0309] simple/arraycells.v:10 Implicit port type (wire) for "y".

[NOTE :CP0309] asicworld/code_hdl_models_decoder_2to4_gates.v:1 Implicit port type (wire) for "f0",
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[NOTE :CP0309] simple/realexpr.v:30 Implicit port type (wire) for "A",
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[NOTE :CP0309] simple/dff_init.v:11 Implicit port type (wire) for "n1_inv".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:109 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:148 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:130 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:138 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:234 Implicit port type (wire) for "out",
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[NOTE :CP0309] hana/test_simulation_techmap_tech.v:7 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:291 Implicit port type (wire) for "out",
there are 3 more instances of this message.

[NOTE :CP0309] hana/test_intermout.v:335 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:12 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:396 Implicit port type (wire) for "out",
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[NOTE :CP0309] hana/test_simulation_techmap_tech.v:25 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:38 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_parser.v:62 Implicit port type (wire) for "sum",
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[NOTE :CP0309] hana/test_simulation_techmap_tech.v:77 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:90 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_shifter.v:51 Implicit port type (wire) for "OUT".

[NOTE :CP0309] simple/forloops.v:1 Implicit port type (wire) for "q",
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[NOTE :CP0309] asicworld/code_hdl_models_full_adder_gates.v:7 Implicit port type (wire) for "sum",
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[NOTE :CP0309] simple/generate.v:154 Implicit port type (wire) for "o".

[NOTE :CP0309] asicworld/code_hdl_models_gray_counter.v:8 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/hierdefparam.v:3 Implicit port type (wire) for "Y".

[NOTE :CP0309] asicworld/code_hdl_models_lfsr_updown.v:7 Implicit port type (wire) for "overflow".

[NOTE :CP0309] simple/mem2reg.v:22 Implicit port type (wire) for "data".

[NOTE :CP0309] simple/memory.v:140 Implicit port type (wire) for "dout".

[NOTE :CP0309] simple/memory.v:233 Implicit port type (wire) for "dout".

[NOTE :CP0309] arch/xilinx/mul_unsigned.v:10 Implicit port type (wire) for "RES".

[NOTE :CP0309] opt/opt_rmdff.v:1 Implicit port type (wire) for "Q".

[NOTE :CP0309] asicworld/code_hdl_models_parity_using_function.v:9 Implicit port type (wire) for "parity_out".

[NOTE :CP0309] simple/paramods.v:14 Implicit port type (wire) for "x",
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[NOTE :CP0309] simple/retime.v:1 Implicit port type (wire) for "z".

[NOTE :CP0309] asicworld/code_hdl_models_serial_crc.v:13 Implicit port type (wire) for "crc_out".

[NOTE :CP0309] simple/hierarchy.v:17 Implicit port type (wire) for "y1",
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[NOTE :CP0309] simple/vloghammer.v:5 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/vloghammer.v:46 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/vloghammer.v:68 Implicit port type (wire) for "y".

[NOTE :CP0309] opt/opt_lut.v:4 Implicit port type (wire) for "o1",
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[NOTE :CP0309] arch/xilinx/xilinx_srl.v:1 Implicit port type (wire) for "q".

[NOTE :CP0309] asicworld/code_verilog_tutorial_escape_id.v:4 Implicit port type (wire) for "q",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:546 Implicit port type (wire) for "out",
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[NOTE :CP0309] hana/hana_vlib.v:37 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:915 Implicit port type (wire) for "unequal",
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[NOTE :CP0309] hana/hana_vlib.v:968 Implicit port type (wire) for "unequal",
there are 2 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:687 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:1104 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:1116 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:635 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/multiplier.v:11 Implicit port type (wire) for "P".

[NOTE :CP0309] hana/hana_vlib.v:86 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:55 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:558 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:572 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:130 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:117 Implicit port type (wire) for "out".

[NOTE :CP0309] simple_abc9/abc9.v:1 Implicit port type (wire) for "o".

[NOTE :CP0309] simple_abc9/abc9.v:17 Implicit port type (wire) for "o",
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[NOTE :CP0309] simple_abc9/abc9.v:39 Implicit port type (wire) for "o".

[NOTE :CP0309] simple_abc9/abc9.v:66 Implicit port type (wire) for "io".

[NOTE :CP0309] simple_abc9/abc9.v:93 Implicit port type (wire) for "io".

[NOTE :CP0309] simple_abc9/abc9.v:126 Implicit port type (wire) for "b",
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[NOTE :CP0309] simple_abc9/abc9.v:262 Implicit port type (wire) for "o".

[NOTE :CP0309] asicworld/code_verilog_tutorial_addbit.v:5 Implicit port type (wire) for "sum",
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[NOTE :CP0309] simple/aes_kexp128.v:4 Implicit port type (wire) for "wo_0",
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[NOTE :CP0309] asicworld/code_hdl_models_arbiter.v:12 Implicit port type (wire) for "gnt3",
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[NOTE :CP0309] simple/carryadd.v:1 Implicit port type (wire) for "y".

[NOTE :CP0309] asicworld/code_hdl_models_clk_div_45.v:10 Implicit port type (wire) for "clk_out".

[NOTE :CP0309] sat/counters-repeat.v:3 Implicit port type (wire) for "ping".

[NOTE :CP0309] asicworld/code_hdl_models_d_ff_gates.v:1 Implicit port type (wire) for "q",
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[NOTE :CP0309] simple/realexpr.v:1 Implicit port type (wire) for "y1",
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[NOTE :CP0309] asicworld/code_verilog_tutorial_explicit.v:19 Implicit port type (wire) for "q_bar".

[NOTE :CP0309] simple/dff_init.v:33 Implicit port type (wire) for "n1_inv".

[NOTE :CP0309] simple/dff_different_styles.v:83 Implicit port type (wire) for "q".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:104 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:125 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:175 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:210 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:249 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_intermout.v:305 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_intermout.v:347 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_intermout.v:403 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:21 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:34 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:43 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_parser.v:53 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:56 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_and.v:28 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:73 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:86 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/forloops.v:15 Implicit port type (wire) for "x",
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[NOTE :CP0309] asicworld/code_hdl_models_full_subtracter_gates.v:7 Implicit port type (wire) for "difference",
there are 1 more instances of this message.

[NOTE :CP0309] simple/generate.v:70 Implicit port type (wire) for "y",
there are 1 more instances of this message.

[NOTE :CP0309] asicworld/code_hdl_models_half_adder_gates.v:7 Implicit port type (wire) for "sum",
there are 1 more instances of this message.

[NOTE :CP0309] simple/paramods.v:42 Implicit port type (wire) for "out".

[NOTE :CP0309] arch/xilinx/macc.v:10 Implicit port type (wire) for "accum_out".

[NOTE :CP0309] simple/mem2reg.v:53 Implicit port type (wire) for "dout_b".

[NOTE :CP0309] simple/memory.v:2 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/memory.v:98 Implicit port type (wire) for "rd_data".

[NOTE :CP0309] simple/memory.v:249 Implicit port type (wire) for "rdata".

[NOTE :CP0309] asicworld/code_verilog_tutorial_multiply.v:1 Implicit port type (wire) for "product".

[NOTE :CP0309] opt/opt_share_add_sub.v:5 Implicit port type (wire) for "res".

[NOTE :CP0309] asicworld/code_verilog_tutorial_parity.v:14 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/partsel.v:1 Implicit port type (wire) for "slice_up",
there are 1 more instances of this message.

[NOTE :CP0309] simple/paramods.v:26 Implicit port type (wire) for "x",
there are 1 more instances of this message.

[NOTE :CP0309] various/shregmap.v:1 Implicit port type (wire) for "q".

[NOTE :CP0309] simple/vloghammer.v:11 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/vloghammer.v:53 Implicit port type (wire) for "y".

[NOTE :CP0309] sat/share.v:4 Implicit port type (wire) for "y1",
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[NOTE :CP0309] simple/macros.v:2 Implicit port type (wire) for "y".

[NOTE :CP0309] arch/ice40/macc.v:27 Implicit port type (wire) for "c".

[NOTE :CP0309] simple/undef_eqx_nex.v:1 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/forgen01.v:4 Implicit port type (wire) for "y".

[NOTE :CP0309] asicworld/code_tidbits_wire_example.v:1 Implicit port type (wire) for "y".

[NOTE :CP0309] arch/xilinx/xilinx_srl.v:15 Implicit port type (wire) for "q".

[NOTE :CP0309] hana/hana_vlib.v:511 Implicit port type (wire) for "out",
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[NOTE :CP0309] hana/hana_vlib.v:525 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:43 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:1020 Implicit port type (wire) for "unequal",
there are 2 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:1072 Implicit port type (wire) for "unequal",
there are 2 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:647 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:663 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] simple/multiplier.v:119 Implicit port type (wire) for "Cout".

[NOTE :CP0309] hana/hana_vlib.v:1126 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:1135 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:605 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:617 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:92 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:61 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/multiplier.v:98 Implicit port type (wire) for "S",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:586 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:599 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/hana_vlib.v:25 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:136 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/hana_vlib.v:123 Implicit port type (wire) for "out".

[NOTE :CP0309] simple_abc9/abc9.v:5 Implicit port type (wire) for "o".

[NOTE :CP0309] simple_abc9/abc9.v:22 Implicit port type (wire) for "o".

[NOTE :CP0309] simple_abc9/abc9.v:46 Implicit port type (wire) for "b".

[NOTE :CP0309] simple_abc9/abc9.v:74 Implicit port type (wire) for "io".

[NOTE :CP0309] simple_abc9/abc9.v:108 Implicit port type (wire) for "b".

[NOTE :CP0309] simple_abc9/abc9.v:132 Implicit port type (wire) for "b".

[NOTE :CP0309] simple_abc9/abc9.v:248 Implicit port type (wire) for "dout".

[NOTE :CP0309] simple_abc9/abc9.v:266 Implicit port type (wire) for "o",
there are 1 more instances of this message.

[NOTE :CP0309] simple/implicit_ports.v:2 Implicit port type (wire) for "cout",
there are 1 more instances of this message.

[NOTE :CP0309] simple/arraycells.v:2 Implicit port type (wire) for "y".

[NOTE :CP0309] sat/counters-repeat.v:18 Implicit port type (wire) for "ping".

[NOTE :CP0309] asicworld/code_hdl_models_d_latch_gates.v:1 Implicit port type (wire) for "q",
there are 1 more instances of this message.

[NOTE :CP0309] asicworld/code_hdl_models_decoder_using_assign.v:9 Implicit port type (wire) for "decoder_out".

[NOTE :CP0309] simple/realexpr.v:15 Implicit port type (wire) for "y0",
there are 3 more instances of this message.

[NOTE :CP0309] simple/dff_init.v:1 Implicit port type (wire) for "n1_inv".

[NOTE :CP0309] hana/test_simulation_shifter.v:57 Implicit port type (wire) for "OUT".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:120 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:154 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:163 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:187 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_intermout.v:256 Implicit port type (wire) for "out",
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[NOTE :CP0309] hana/test_intermout.v:267 Implicit port type (wire) for "out",
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[NOTE :CP0309] hana/test_intermout.v:314 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_intermout.v:359 Implicit port type (wire) for "out",
there are 1 more instances of this message.

[NOTE :CP0309] hana/test_parser.v:8 Implicit port type (wire) for "out",
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[NOTE :CP0309] hana/test_parser.v:19 Implicit port type (wire) for "out",
there are 3 more instances of this message.

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:51 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_parser.v:41 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:64 Implicit port type (wire) for "out".

[NOTE :CP0309] hana/test_simulation_always.v:74 Implicit port type (wire) for "ns".

[NOTE :CP0309] hana/test_simulation_techmap_tech.v:95 Implicit port type (wire) for "out".

[NOTE :CP0309] simple/generate.v:97 Implicit port type (wire) for "b".

[NOTE :CP0309] simple/hierdefparam.v:11 Implicit port type (wire) for "Y".

[NOTE :CP0309] various/pmux2shiftx.v:36 Implicit port type (wire) for "o".

[NOTE :CP0309] arch/xilinx/macc.v:49 Implicit port type (wire) for "accum_out",
there are 1 more instances of this message.

[NOTE :CP0309] simple/mem2reg.v:64 Implicit port type (wire) for "result1",
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[NOTE :CP0309] arch/common/mux.v:54 Implicit port type (wire) for "Y".

[NOTE :CP0309] asicworld/code_verilog_tutorial_mux_21.v:1 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/omsp_dbg_uart.v:2 Implicit port type (wire) for "cmd_valid".

[NOTE :CP0309] asicworld/code_hdl_models_parity_using_assign.v:9 Implicit port type (wire) for "parity_out".

[NOTE :CP0309] simple/partsel.v:12 Implicit port type (wire) for "x1",
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[NOTE :CP0309] simple/signedexpr.v:1 Implicit port type (wire) for "xu",
there are 5 more instances of this message.

[NOTE :CP0309] asicworld/code_specman_switch_fabric.v:5 Implicit port type (wire) for "data_out0",
there are 11 more instances of this message.

[NOTE :CP0309] simple/task_func.v:71 Implicit port type (wire) for "dout_a".

[NOTE :CP0309] simple/vloghammer.v:17 Implicit port type (wire) for "y".

[NOTE :CP0309] simple/vloghammer.v:60 Implicit port type (wire) for "y".

[NOTE :CP0309] asicworld/code_verilog_tutorial_tri_buf.v:1 Implicit port type (wire) for "b".

[NOTE :CP0309] simple/forgen02.v:1 Implicit port type (wire) for "y",
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[NOTE :CP0309] simple/wandwor.v:1 Implicit port type (wire) for "X",
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[NOTE :CP0309] simple/wreduce.v:1 Implicit port type (wire) for "x",
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[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] hana/hana_vlib.v:25 Top level module "work@TRIBUF".

[NOTE :EL0503] hana/hana_vlib.v:31 Top level module "work@INV".

[NOTE :EL0503] hana/hana_vlib.v:43 Top level module "work@AND3".

[NOTE :EL0503] hana/hana_vlib.v:49 Top level module "work@AND4".

[NOTE :EL0503] hana/hana_vlib.v:55 Top level module "work@OR2".

[NOTE :EL0503] hana/hana_vlib.v:61 Top level module "work@OR3".

[NOTE :EL0503] hana/hana_vlib.v:67 Top level module "work@OR4".

[NOTE :EL0503] hana/hana_vlib.v:74 Top level module "work@NAND2".

[NOTE :EL0503] hana/hana_vlib.v:80 Top level module "work@NAND3".

[NOTE :EL0503] hana/hana_vlib.v:86 Top level module "work@NAND4".

[NOTE :EL0503] hana/hana_vlib.v:92 Top level module "work@NOR2".

[NOTE :EL0503] hana/hana_vlib.v:98 Top level module "work@NOR3".

[NOTE :EL0503] hana/hana_vlib.v:104 Top level module "work@NOR4".

[NOTE :EL0503] hana/hana_vlib.v:111 Top level module "work@XOR2".

[NOTE :EL0503] hana/hana_vlib.v:117 Top level module "work@XOR3".

[NOTE :EL0503] hana/hana_vlib.v:123 Top level module "work@XOR4".

[NOTE :EL0503] hana/hana_vlib.v:130 Top level module "work@XNOR2".

[NOTE :EL0503] hana/hana_vlib.v:136 Top level module "work@XNOR3".

[NOTE :EL0503] hana/hana_vlib.v:142 Top level module "work@XNOR4".

[NOTE :EL0503] hana/hana_vlib.v:148 Top level module "work@DEC1".

[NOTE :EL0503] hana/hana_vlib.v:161 Top level module "work@DEC2".

[NOTE :EL0503] hana/hana_vlib.v:176 Top level module "work@DEC3".

[NOTE :EL0503] hana/hana_vlib.v:195 Top level module "work@DEC4".

[NOTE :EL0503] hana/hana_vlib.v:221 Top level module "work@DEC5".

[NOTE :EL0503] hana/hana_vlib.v:264 Top level module "work@DEC6".

[NOTE :EL0503] hana/hana_vlib.v:351 Top level module "work@MUX4".

[NOTE :EL0503] hana/hana_vlib.v:363 Top level module "work@MUX8".

[NOTE :EL0503] hana/hana_vlib.v:378 Top level module "work@MUX16".

[NOTE :EL0503] hana/hana_vlib.v:401 Top level module "work@MUX32".

[NOTE :EL0503] hana/hana_vlib.v:440 Top level module "work@MUX64".

[NOTE :EL0503] hana/hana_vlib.v:511 Top level module "work@ADD1".

[NOTE :EL0503] hana/hana_vlib.v:517 Top level module "work@ADD2".

[NOTE :EL0503] hana/hana_vlib.v:524 Top level module "work@ADD4".

[NOTE :EL0503] hana/hana_vlib.v:531 Top level module "work@ADD8".

[NOTE :EL0503] hana/hana_vlib.v:538 Top level module "work@ADD16".

[NOTE :EL0503] hana/hana_vlib.v:545 Top level module "work@ADD32".

[NOTE :EL0503] hana/hana_vlib.v:551 Top level module "work@ADD64".

[NOTE :EL0503] hana/hana_vlib.v:558 Top level module "work@SUB1".

[NOTE :EL0503] hana/hana_vlib.v:564 Top level module "work@SUB2".

[NOTE :EL0503] hana/hana_vlib.v:571 Top level module "work@SUB4".

[NOTE :EL0503] hana/hana_vlib.v:578 Top level module "work@SUB8".

[NOTE :EL0503] hana/hana_vlib.v:585 Top level module "work@SUB16".

[NOTE :EL0503] hana/hana_vlib.v:592 Top level module "work@SUB32".

[NOTE :EL0503] hana/hana_vlib.v:598 Top level module "work@SUB64".

[NOTE :EL0503] hana/hana_vlib.v:605 Top level module "work@MUL1".

[NOTE :EL0503] hana/hana_vlib.v:611 Top level module "work@MUL2".

[NOTE :EL0503] hana/hana_vlib.v:617 Top level module "work@MUL4".

[NOTE :EL0503] hana/hana_vlib.v:623 Top level module "work@MUL8".

[NOTE :EL0503] hana/hana_vlib.v:629 Top level module "work@MUL16".

[NOTE :EL0503] hana/hana_vlib.v:635 Top level module "work@MUL32".

[NOTE :EL0503] hana/hana_vlib.v:641 Top level module "work@MUL64".

[NOTE :EL0503] hana/hana_vlib.v:654 Top level module "work@DIV2".

[NOTE :EL0503] hana/hana_vlib.v:662 Top level module "work@DIV4".

[NOTE :EL0503] hana/hana_vlib.v:670 Top level module "work@DIV8".

[NOTE :EL0503] hana/hana_vlib.v:678 Top level module "work@DIV16".

[NOTE :EL0503] hana/hana_vlib.v:686 Top level module "work@DIV32".

[NOTE :EL0503] hana/hana_vlib.v:694 Top level module "work@DIV64".

[NOTE :EL0503] hana/hana_vlib.v:708 Top level module "work@RFF".

[NOTE :EL0503] hana/hana_vlib.v:716 Top level module "work@SFF".

[NOTE :EL0503] hana/hana_vlib.v:724 Top level module "work@RSFF".

[NOTE :EL0503] hana/hana_vlib.v:734 Top level module "work@SRFF".

[NOTE :EL0503] hana/hana_vlib.v:744 Top level module "work@LATCH".

[NOTE :EL0503] hana/hana_vlib.v:750 Top level module "work@RLATCH".

[NOTE :EL0503] hana/hana_vlib.v:759 Top level module "work@LSHIFT1".

[NOTE :EL0503] hana/hana_vlib.v:771 Top level module "work@LSHIFT2".

[NOTE :EL0503] hana/hana_vlib.v:782 Top level module "work@LSHIFT4".

[NOTE :EL0503] hana/hana_vlib.v:793 Top level module "work@LSHIFT8".

[NOTE :EL0503] hana/hana_vlib.v:803 Top level module "work@LSHIFT16".

[NOTE :EL0503] hana/hana_vlib.v:813 Top level module "work@LSHIFT32".

[NOTE :EL0503] hana/hana_vlib.v:823 Top level module "work@LSHIFT64".

[NOTE :EL0503] hana/hana_vlib.v:833 Top level module "work@RSHIFT1".

[NOTE :EL0503] hana/hana_vlib.v:844 Top level module "work@RSHIFT2".

[NOTE :EL0503] hana/hana_vlib.v:857 Top level module "work@RSHIFT4".

[NOTE :EL0503] hana/hana_vlib.v:868 Top level module "work@RSHIFT8".

[NOTE :EL0503] hana/hana_vlib.v:880 Top level module "work@RSHIFT16".

[NOTE :EL0503] hana/hana_vlib.v:892 Top level module "work@RSHIFT32".

[NOTE :EL0503] hana/hana_vlib.v:903 Top level module "work@RSHIFT64".

[NOTE :EL0503] hana/hana_vlib.v:914 Top level module "work@CMP1".

[NOTE :EL0503] hana/hana_vlib.v:941 Top level module "work@CMP2".

[NOTE :EL0503] hana/hana_vlib.v:967 Top level module "work@CMP4".

[NOTE :EL0503] hana/hana_vlib.v:993 Top level module "work@CMP8".

[NOTE :EL0503] hana/hana_vlib.v:1019 Top level module "work@CMP16".

[NOTE :EL0503] hana/hana_vlib.v:1045 Top level module "work@CMP32".

[NOTE :EL0503] hana/hana_vlib.v:1071 Top level module "work@CMP64".

[NOTE :EL0503] hana/hana_vlib.v:1100 Top level module "work@GND".

[NOTE :EL0503] hana/hana_vlib.v:1104 Top level module "work@INC1".

[NOTE :EL0503] hana/hana_vlib.v:1110 Top level module "work@INC2".

[NOTE :EL0503] hana/hana_vlib.v:1116 Top level module "work@INC4".

[NOTE :EL0503] hana/hana_vlib.v:1121 Top level module "work@INC8".

[NOTE :EL0503] hana/hana_vlib.v:1126 Top level module "work@INC16".

[NOTE :EL0503] hana/hana_vlib.v:1131 Top level module "work@INC32".

[NOTE :EL0503] hana/hana_vlib.v:1135 Top level module "work@INC64".

[NOTE :EL0503] asicworld/code_hdl_models_arbiter_tb.v:1 Top level module "work@MODULE NAME UNKNOWN".

[NOTE :EL0503] asicworld/code_hdl_models_clk_div.v:8 Top level module "work@clk_div".

[NOTE :EL0503] asicworld/code_hdl_models_d_latch_gates.v:1 Top level module "work@d_latch_gates".

[NOTE :EL0503] asicworld/code_hdl_models_decoder_using_assign.v:7 Top level module "work@decoder_using_assign".

[NOTE :EL0503] asicworld/code_hdl_models_dff_sync_reset.v:7 Top level module "work@dff_sync_reset".

[NOTE :EL0503] asicworld/code_hdl_models_full_adder_gates.v:7 Top level module "work@full_adder_gates".

[NOTE :EL0503] asicworld/code_hdl_models_cam.v:7 Top level module "work@cam".

[NOTE :EL0503] asicworld/code_hdl_models_d_ff_gates.v:1 Top level module "work@d_ff_gates".

[NOTE :EL0503] asicworld/code_hdl_models_decoder_2to4_gates.v:1 Top level module "work@decoder_2to4_gates".

[NOTE :EL0503] asicworld/code_hdl_models_GrayCounter.v:7 Top level module "work@GrayCounter".

[NOTE :EL0503] asicworld/code_hdl_models_gray_counter.v:7 Top level module "work@gray_counter".

[NOTE :EL0503] asicworld/code_hdl_models_mux_2to1_gates.v:7 Top level module "work@mux_2to1_gates".

[NOTE :EL0503] asicworld/code_hdl_models_decoder_using_case.v:7 Top level module "work@decoder_using_case".

[NOTE :EL0503] asicworld/code_hdl_models_encoder_using_if.v:7 Top level module "work@encoder_using_if".

[NOTE :EL0503] asicworld/code_hdl_models_mux_using_assign.v:7 Top level module "work@mux_using_assign".

[NOTE :EL0503] asicworld/code_hdl_models_mux_using_case.v:7 Top level module "work@mux_using_case".

[NOTE :EL0503] asicworld/code_hdl_models_parity_using_assign.v:7 Top level module "work@parity_using_assign".

[NOTE :EL0503] asicworld/code_hdl_models_rom_using_case.v:7 Top level module "work@rom_using_case".

[NOTE :EL0503] asicworld/code_hdl_models_tff_sync_reset.v:7 Top level module "work@tff_sync_reset".

[NOTE :EL0503] asicworld/code_hdl_models_up_down_counter.v:7 Top level module "work@up_down_counter".

[NOTE :EL0503] asicworld/code_tidbits_asyn_reset.v:1 Top level module "work@asyn_reset".

[NOTE :EL0503] asicworld/code_hdl_models_full_subtracter_gates.v:7 Top level module "work@full_subtracter_gates".

[NOTE :EL0503] asicworld/code_hdl_models_half_adder_gates.v:7 Top level module "work@half_adder_gates".

[NOTE :EL0503] asicworld/code_hdl_models_parallel_crc.v:7 Top level module "work@parallel_crc_ccitt".

[NOTE :EL0503] asicworld/code_hdl_models_tff_async_reset.v:7 Top level module "work@tff_async_reset".

[NOTE :EL0503] asicworld/code_hdl_models_up_counter.v:7 Top level module "work@up_counter".

[NOTE :EL0503] asicworld/code_hdl_models_clk_div_45.v:7 Top level module "work@clk_div_45".

[NOTE :EL0503] asicworld/code_hdl_models_dff_async_reset.v:7 Top level module "work@dff_async_reset".

[NOTE :EL0503] asicworld/code_specman_switch_fabric.v:1 Top level module "work@switch_fabric".

[NOTE :EL0503] asicworld/code_hdl_models_encoder_4to2_gates.v:1 Top level module "work@encoder_4to2_gates".

[NOTE :EL0503] asicworld/code_hdl_models_encoder_using_case.v:7 Top level module "work@encoder_using_case".

[NOTE :EL0503] asicworld/code_tidbits_fsm_using_function.v:6 Top level module "work@fsm_using_function".

[NOTE :EL0503] asicworld/code_verilog_tutorial_addbit.v:1 Top level module "work@addbit".

[NOTE :EL0503] asicworld/code_hdl_models_lfsr.v:7 Top level module "work@lfsr".

[NOTE :EL0503] asicworld/code_hdl_models_one_hot_cnt.v:7 Top level module "work@one_hot_cnt".

[NOTE :EL0503] asicworld/code_hdl_models_parity_using_function.v:7 Top level module "work@parity_using_function".

[NOTE :EL0503] asicworld/code_tidbits_fsm_using_single_always.v:7 Top level module "work@fsm_using_single_always".

[NOTE :EL0503] asicworld/code_verilog_tutorial_escape_id.v:3 Top level module "work@1dff".

[NOTE :EL0503] asicworld/code_verilog_tutorial_parity.v:9 Top level module "work@parity".

[NOTE :EL0503] errors/syntax_err04.v:1 Top level module "work@a".

[NOTE :EL0503] asicworld/code_hdl_models_lfsr_updown.v:1 Top level module "work@lfsr_updown".

[NOTE :EL0503] asicworld/code_hdl_models_mux_using_if.v:7 Top level module "work@mux_using_if".

[NOTE :EL0503] asicworld/code_hdl_models_parity_using_bitwise.v:7 Top level module "work@parity_using_bitwise".

[NOTE :EL0503] asicworld/code_hdl_models_serial_crc.v:7 Top level module "work@serial_crc_ccitt".

[NOTE :EL0503] asicworld/code_hdl_models_up_counter_load.v:7 Top level module "work@up_counter_load".

[NOTE :EL0503] asicworld/code_tidbits_blocking.v:1 Top level module "work@blocking".

[NOTE :EL0503] asicworld/code_tidbits_fsm_using_always.v:6 Top level module "work@fsm_using_always".

[NOTE :EL0503] asicworld/code_tidbits_reg_seq_example.v:1 Top level module "work@reg_seq_example".

[NOTE :EL0503] asicworld/code_tidbits_wire_example.v:1 Top level module "work@wire_example".

[NOTE :EL0503] asicworld/code_verilog_tutorial_bus_con.v:1 Top level module "work@bus_con".

[NOTE :EL0503] asicworld/code_verilog_tutorial_d_ff.v:2 Top level module "work@d_ff".

[NOTE :EL0503] asicworld/code_verilog_tutorial_decoder_always.v:1 Top level module "work@decoder_always".

[NOTE :EL0503] asicworld/code_verilog_tutorial_first_counter.v:9 Top level module "work@first_counter".

[NOTE :EL0503] asicworld/code_verilog_tutorial_mux_21.v:1 Top level module "work@mux_21".

[NOTE :EL0503] asicworld/code_verilog_tutorial_n_out_primitive.v:1 Top level module "work@n_out_primitive".

[NOTE :EL0503] asicworld/code_hdl_models_pri_encoder_using_assign.v:7 Top level module "work@pri_encoder_using_assign".

[NOTE :EL0503] asicworld/code_verilog_tutorial_simple_function.v:1 Top level module "work@simple_function".

[NOTE :EL0503] asicworld/code_verilog_tutorial_simple_if.v:1 Top level module "work@simple_if".

[NOTE :EL0503] asicworld/code_verilog_tutorial_tri_buf.v:1 Top level module "work@tri_buf".

[NOTE :EL0503] asicworld/code_verilog_tutorial_which_clock.v:1 Top level module "work@which_clock".

[NOTE :EL0503] asicworld/code_verilog_tutorial_counter_tb.v:16 Top level module "work@testbench".

[NOTE :EL0503] asicworld/code_verilog_tutorial_if_else.v:1 Top level module "work@if_else".

[NOTE :EL0503] asicworld/code_verilog_tutorial_multiply.v:1 Top level module "work@muliply".

[NOTE :EL0503] hana/test_parser.v:3 Top level module "work@f1_test".

[NOTE :EL0503] hana/test_parser.v:7 Top level module "work@f2_test".

[NOTE :EL0503] hana/test_parser.v:19 Top level module "work@f3_test".

[NOTE :EL0503] hana/test_parser.v:34 Top level module "work@f4_ahmad".

[NOTE :EL0503] hana/test_parser.v:41 Top level module "work@f5_test".

[NOTE :EL0503] hana/test_parser.v:53 Top level module "work@f5_ternaryop".

[NOTE :EL0503] hana/test_parser.v:62 Top level module "work@f5_fulladd4".

[NOTE :EL0503] hana/test_parser.v:72 Top level module "work@f6_adder".

[NOTE :EL0503] hana/test_parser.v:80 Top level module "work@f7_test".

[NOTE :EL0503] asicworld/code_verilog_tutorial_parallel_if.v:1 Top level module "work@parallel_if".

[NOTE :EL0503] hana/test_simulation_and.v:18 Top level module "work@f4_test".

[NOTE :EL0503] hana/test_simulation_and.v:28 Top level module "work@f6_test".

[NOTE :EL0503] asicworld/code_verilog_tutorial_task_global.v:1 Top level module "work@task_global".

[NOTE :EL0503] asicworld/code_hdl_models_uart.v:7 Top level module "work@uart".

[NOTE :EL0503] asicworld/code_tidbits_nonblocking.v:1 Top level module "work@nonblocking".

[NOTE :EL0503] asicworld/code_tidbits_reg_combo_example.v:1 Top level module "work@reg_combo_example".

[NOTE :EL0503] asicworld/code_tidbits_syn_reset.v:1 Top level module "work@syn_reset".

[NOTE :EL0503] asicworld/code_verilog_tutorial_always_example.v:1 Top level module "work@always_example".

[NOTE :EL0503] asicworld/code_verilog_tutorial_decoder.v:1 Top level module "work@decoder".

[NOTE :EL0503] hana/test_simulation_shifter.v:45 Top level module "work@f8_test".

[NOTE :EL0503] hana/test_simulation_shifter.v:51 Top level module "work@f9_test".

[NOTE :EL0503] hana/test_simulation_shifter.v:57 Top level module "work@f10_test".

[NOTE :EL0503] asicworld/code_verilog_tutorial_explicit.v:1 Top level module "work@explicit".

[NOTE :EL0503] asicworld/code_verilog_tutorial_flip_flop.v:1 Top level module "work@flif_flop".

[NOTE :EL0503] hana/test_simulation_always.v:57 Top level module "work@f6_NonBlockingEx".

[NOTE :EL0503] hana/test_simulation_always.v:74 Top level module "work@f7_FlipFlop".

[NOTE :EL0503] hana/test_simulation_always.v:87 Top level module "work@f8_inc".

[NOTE :EL0503] hana/test_simulation_always.v:96 Top level module "work@f9_MyCounter".

[NOTE :EL0503] hana/test_simulation_always.v:112 Top level module "work@f10_FlipFlop".

[NOTE :EL0503] hana/test_simulation_always.v:127 Top level module "work@f11_test".

[NOTE :EL0503] asicworld/code_verilog_tutorial_fsm_full.v:1 Top level module "work@fsm_full".

[NOTE :EL0503] opt/opt_lut.v:1 Top level module "work@top".

[NOTE :EL0503] opt/opt_share_add_sub.v:1 Top level module "work@opt_share_test".

[NOTE :EL0503] memories/amber23_sram_byte_en.v:45 Top level module "work@generic_sram_byte_en".

[NOTE :EL0503] proc/bug_1268.v:1 Top level module "work@gold".

[NOTE :EL0503] proc/bug_1268.v:13 Top level module "work@gate".

[NOTE :EL0503] sat/counters-repeat.v:3 Top level module "work@counter1".

[NOTE :EL0503] sat/counters-repeat.v:18 Top level module "work@counter2".

[NOTE :EL0503] asicworld/code_verilog_tutorial_v2k_reg.v:1 Top level module "work@v2k_reg".

[NOTE :EL0503] hana/test_parse2synthtrans.v:27 Top level module "work@f2_demultiplexer1_to_4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:3 Top level module "work@f1_TECH_AND18".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:7 Top level module "work@f1_TECH_AND4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:12 Top level module "work@f2_TECH_AND5".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:17 Top level module "work@f3_TECH_NAND18".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:21 Top level module "work@f3_TECH_NAND4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:25 Top level module "work@f3_TECH_NAND2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:30 Top level module "work@f4_TECH_NAND18".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:34 Top level module "work@f4_TECH_NAND4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:38 Top level module "work@f4_TECH_NAND2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:43 Top level module "work@f5_TECH_NAND18".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:47 Top level module "work@f5_TECH_NAND4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:51 Top level module "work@f5_TECH_NAND2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:56 Top level module "work@f6_TECH_NOR18".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:60 Top level module "work@f6_TECH_NOR4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:64 Top level module "work@f6_TECH_NOR2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:69 Top level module "work@f7_TECH_NOR18".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:73 Top level module "work@f7_TECH_NOR4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:77 Top level module "work@f7_TECH_NOR2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:82 Top level module "work@f8_TECH_NOR18".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:86 Top level module "work@f8_TECH_NOR4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:90 Top level module "work@f8_TECH_NOR2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:95 Top level module "work@f9_TECH_OR18".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:99 Top level module "work@f9_TECH_OR4".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:104 Top level module "work@f10_TECH_OR5".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:109 Top level module "work@f11_TECH_XOR5".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:112 Top level module "work@f11_TECH_XOR2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:117 Top level module "work@f12_TECH_XOR5".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:120 Top level module "work@f12_TECH_XOR2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:125 Top level module "work@f13_TECH_XOR2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:130 Top level module "work@f14_TECH_XOR5".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:133 Top level module "work@f14_TECH_XOR2".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:138 Top level module "work@f15_TECH_XOR5".

[NOTE :EL0503] hana/test_simulation_techmap_tech.v:141 Top level module "work@f15_TECH_XOR2".

[NOTE :EL0503] sat/expose_dff.v:2 Top level module "work@test1".

[NOTE :EL0503] sat/expose_dff.v:7 Top level module "work@test2".

[NOTE :EL0503] sat/expose_dff.v:17 Top level module "work@test3".

[NOTE :EL0503] sat/expose_dff.v:25 Top level module "work@test4".

[NOTE :EL0503] memories/implicit_en.v:4 Top level module "work@test".

[NOTE :EL0503] hana/test_intermout.v:54 Top level module "work@f5_NonBlockingEx".

[NOTE :EL0503] hana/test_intermout.v:71 Top level module "work@f6_FlipFlop".

[NOTE :EL0503] hana/test_intermout.v:108 Top level module "work@f9_NegEdgeClock".

[NOTE :EL0503] hana/test_intermout.v:121 Top level module "work@f10_MyCounter".

[NOTE :EL0503] hana/test_intermout.v:148 Top level module "work@f12_test".

[NOTE :EL0503] hana/test_intermout.v:154 Top level module "work@f13_test".

[NOTE :EL0503] hana/test_intermout.v:163 Top level module "work@f14_test".

[NOTE :EL0503] hana/test_intermout.v:187 Top level module "work@f15_test".

[NOTE :EL0503] hana/test_intermout.v:222 Top level module "work@f16_test".

[NOTE :EL0503] hana/test_intermout.v:234 Top level module "work@f17_test".

[NOTE :EL0503] hana/test_intermout.v:249 Top level module "work@f18_test".

[NOTE :EL0503] hana/test_intermout.v:256 Top level module "work@f19_buffer".

[NOTE :EL0503] hana/test_intermout.v:267 Top level module "work@f20_test".

[NOTE :EL0503] hana/test_intermout.v:280 Top level module "work@f21_test".

[NOTE :EL0503] hana/test_intermout.v:291 Top level module "work@f22_test".

[NOTE :EL0503] hana/test_intermout.v:305 Top level module "work@f23_test".

[NOTE :EL0503] hana/test_intermout.v:314 Top level module "work@f24_test".

[NOTE :EL0503] hana/test_intermout.v:326 Top level module "work@f25_test".

[NOTE :EL0503] hana/test_intermout.v:335 Top level module "work@f26_test".

[NOTE :EL0503] hana/test_intermout.v:347 Top level module "work@f27_test".

[NOTE :EL0503] hana/test_intermout.v:359 Top level module "work@f28_test".

[NOTE :EL0503] hana/test_intermout.v:366 Top level module "work@f29_Reduction".

[NOTE :EL0503] hana/test_intermout.v:384 Top level module "work@f30_test".

[NOTE :EL0503] hana/test_intermout.v:396 Top level module "work@f31_test".

[NOTE :EL0503] hana/test_intermout.v:403 Top level module "work@f32_test".

[NOTE :EL0503] hana/test_intermout.v:409 Top level module "work@f33_test".

[NOTE :EL0503] simple/aes_kexp128.v:4 Top level module "work@aes_key_expand_128".

[NOTE :EL0503] simple/arrays01.v:1 Top level module "work@uut_arrays01".

[NOTE :EL0503] liberty/small.v:3 Top level module "work@small".

[NOTE :EL0503] memories/issue00335.v:5 Top level module "work@ram2".

[NOTE :EL0503] opt/opt_rmdff.v:1 Top level module "work@opt_rmdff_test".

[NOTE :EL0503] sat/share.v:1 Top level module "work@test_1".

[NOTE :EL0503] sat/share.v:12 Top level module "work@test_2".

[NOTE :EL0503] simple/always01.v:1 Top level module "work@uut_always01".

[NOTE :EL0503] simple/always03.v:1 Top level module "work@uut_always03".

[NOTE :EL0503] sat/asserts_seq.v:1 Top level module "work@test_001".

[NOTE :EL0503] sat/asserts_seq.v:20 Top level module "work@test_002".

[NOTE :EL0503] sat/asserts_seq.v:37 Top level module "work@test_003".

[NOTE :EL0503] sat/asserts_seq.v:54 Top level module "work@test_004".

[NOTE :EL0503] sat/asserts_seq.v:71 Top level module "work@test_005".

[NOTE :EL0503] simple/always02.v:1 Top level module "work@uut_always02".

[NOTE :EL0503] simple/arraycells.v:2 Top level module "work@array_test001".

[NOTE :EL0503] simple/constmuldivmod.v:1 Top level module "work@constmuldivmod".

[NOTE :EL0503] simple/forgen01.v:4 Top level module "work@uut_forgen01".

[NOTE :EL0503] simple/dff_different_styles.v:9 Top level module "work@dffa".

[NOTE :EL0503] simple/dff_different_styles.v:20 Top level module "work@dffa1".

[NOTE :EL0503] simple/dff_different_styles.v:31 Top level module "work@dffa2".

[NOTE :EL0503] simple/dff_different_styles.v:42 Top level module "work@dffa3".

[NOTE :EL0503] simple/dff_different_styles.v:53 Top level module "work@dffa4".

[NOTE :EL0503] simple/dff_different_styles.v:72 Top level module "work@dffsr1".

[NOTE :EL0503] simple/dff_different_styles.v:83 Top level module "work@dffsr2".

[NOTE :EL0503] simple/i2c_master_tests.v:6 Top level module "work@i2c_test01".

[NOTE :EL0503] simple/i2c_master_tests.v:29 Top level module "work@i2c_test02".

[NOTE :EL0503] simple/forgen02.v:1 Top level module "work@uut_forgen02".

[NOTE :EL0503] simple/carryadd.v:1 Top level module "work@carryadd".

[NOTE :EL0503] simple/fiedler-cooley.v:3 Top level module "work@up3down5".

[NOTE :EL0503] simple/fsm.v:4 Top level module "work@fsm_test".

[NOTE :EL0503] simple/constpower.v:1 Top level module "work@constpower".

[NOTE :EL0503] simple/forloops.v:1 Top level module "work@forloops01".

[NOTE :EL0503] simple/forloops.v:15 Top level module "work@forloops02".

[NOTE :EL0503] simple/graphtest.v:1 Top level module "work@graphtest".

[NOTE :EL0503] simple/implicit_ports.v:7 Top level module "work@named_ports".

[NOTE :EL0503] simple/dff_init.v:1 Top level module "work@dff0_test".

[NOTE :EL0503] simple/dff_init.v:11 Top level module "work@dff1_test".

[NOTE :EL0503] simple/dff_init.v:22 Top level module "work@dff0a_test".

[NOTE :EL0503] simple/dff_init.v:33 Top level module "work@dff1a_test".

[NOTE :EL0503] simple/dff_init.v:44 Top level module "work@dff_test_997".

[NOTE :EL0503] simple/hierdefparam.v:3 Top level module "work@hierdefparam_top".

[NOTE :EL0503] simple/localparam_attr.v:1 Top level module "work@uut_localparam_attr".

[NOTE :EL0503] simple/mem2reg.v:2 Top level module "work@mem2reg_test1".

[NOTE :EL0503] simple/mem2reg.v:22 Top level module "work@mem2reg_test2".

[NOTE :EL0503] simple/mem2reg.v:53 Top level module "work@mem2reg_test3".

[NOTE :EL0503] simple/mem2reg.v:64 Top level module "work@mem2reg_test4".

[NOTE :EL0503] simple/mem2reg.v:86 Top level module "work@mem2reg_test5".

[NOTE :EL0503] simple/mem2reg.v:97 Top level module "work@mem2reg_test6".

[NOTE :EL0503] simple/macros.v:2 Top level module "work@test_def".

[NOTE :EL0503] simple/macros.v:19 Top level module "work@test_ifdef".

[NOTE :EL0503] simple/macros.v:241 Top level module "work@test_comment_in_macro".

[NOTE :EL0503] simple/omsp_dbg_uart.v:2 Top level module "work@omsp_dbg_uart".

[NOTE :EL0503] simple/param_attr.v:1 Top level module "work@uut_param_attr".

[NOTE :EL0503] simple/paramods.v:2 Top level module "work@pm_test1".

[NOTE :EL0503] simple/paramods.v:14 Top level module "work@pm_test2".

[NOTE :EL0503] simple/paramods.v:26 Top level module "work@pm_test3".

[NOTE :EL0503] simple/loops.v:6 Top level module "work@aes".

[NOTE :EL0503] simple/process.v:2 Top level module "work@blocking_cond".

[NOTE :EL0503] simple/mem_arst.v:2 Top level module "work@MyMem".

[NOTE :EL0503] simple/repwhile.v:1 Top level module "work@repwhile_test001".

[NOTE :EL0503] simple/muxtree.v:5 Top level module "work@usb_tx_phy".

[NOTE :EL0503] simple/muxtree.v:56 Top level module "work@default_cases".

[NOTE :EL0503] simple/muxtree.v:76 Top level module "work@select_leaves".

[NOTE :EL0503] simple/signedexpr.v:1 Top level module "work@signed_test01".

[NOTE :EL0503] simple/operators.v:1 Top level module "work@optest".

[NOTE :EL0503] simple/realexpr.v:1 Top level module "work@demo_001".

[NOTE :EL0503] simple/realexpr.v:15 Top level module "work@demo_002".

[NOTE :EL0503] simple/realexpr.v:30 Top level module "work@demo_004".

[NOTE :EL0503] simple/retime.v:1 Top level module "work@retime_test".

[NOTE :EL0503] simple/rotate.v:3 Top level module "work@a23_barrel_shift_fpga_rotate".

[NOTE :EL0503] simple/subbytes.v:4 Top level module "work@subbytes_00".

[NOTE :EL0503] simple/wandwor.v:1 Top level module "work@wandwor_test0".

[NOTE :EL0503] simple/wandwor.v:13 Top level module "work@wandwor_test1".

[NOTE :EL0503] simple/wreduce.v:1 Top level module "work@wreduce_test0".

[NOTE :EL0503] simple/wreduce.v:7 Top level module "work@wreduce_test1".

[NOTE :EL0503] simple/multiplier.v:8 Top level module "work@Multiplier_flat".

[NOTE :EL0503] simple/multiplier.v:66 Top level module "work@Multiplier_2D".

[NOTE :EL0503] simple/sincos.v:6 Top level module "work@d".

[NOTE :EL0503] simple/partsel.v:1 Top level module "work@partsel_test001".

[NOTE :EL0503] simple/partsel.v:7 Top level module "work@partsel_test002".

[NOTE :EL0503] simple/generate.v:2 Top level module "work@gen_test1".

[NOTE :EL0503] simple/generate.v:43 Top level module "work@gen_test2".

[NOTE :EL0503] simple/generate.v:70 Top level module "work@gen_test3".

[NOTE :EL0503] simple/generate.v:97 Top level module "work@gen_test4".

[NOTE :EL0503] simple/generate.v:118 Top level module "work@gen_test5".

[NOTE :EL0503] simple/generate.v:154 Top level module "work@gen_test6".

[NOTE :EL0503] simple_abc9/abc9.v:1 Top level module "work@abc9_test001".

[NOTE :EL0503] simple_abc9/abc9.v:5 Top level module "work@abc9_test002".

[NOTE :EL0503] simple_abc9/abc9.v:9 Top level module "work@abc9_test003".

[NOTE :EL0503] simple_abc9/abc9.v:13 Top level module "work@abc9_test004".

[NOTE :EL0503] simple_abc9/abc9.v:17 Top level module "work@abc9_test005".

[NOTE :EL0503] simple_abc9/abc9.v:22 Top level module "work@abc9_test006".

[NOTE :EL0503] simple_abc9/abc9.v:28 Top level module "work@abc9_test007".

[NOTE :EL0503] simple_abc9/abc9.v:39 Top level module "work@abc9_test008".

[NOTE :EL0503] simple_abc9/abc9.v:50 Top level module "work@abc9_test009".

[NOTE :EL0503] simple_abc9/abc9.v:58 Top level module "work@abc9_test010".

[NOTE :EL0503] simple_abc9/abc9.v:66 Top level module "work@abc9_test011".

[NOTE :EL0503] simple_abc9/abc9.v:74 Top level module "work@abc9_test012".

[NOTE :EL0503] simple_abc9/abc9.v:82 Top level module "work@abc9_test013".

[NOTE :EL0503] simple_abc9/abc9.v:93 Top level module "work@abc9_test014".

[NOTE :EL0503] simple_abc9/abc9.v:108 Top level module "work@abc9_test015".

[NOTE :EL0503] simple_abc9/abc9.v:114 Top level module "work@abc9_test016".

[NOTE :EL0503] simple_abc9/abc9.v:120 Top level module "work@abc9_test017".

[NOTE :EL0503] simple_abc9/abc9.v:126 Top level module "work@abc9_test018".

[NOTE :EL0503] simple_abc9/abc9.v:132 Top level module "work@abc9_test019".

[NOTE :EL0503] simple_abc9/abc9.v:139 Top level module "work@abc9_test020".

[NOTE :EL0503] simple_abc9/abc9.v:147 Top level module "work@abc9_test021".

[NOTE :EL0503] simple_abc9/abc9.v:227 Top level module "work@abc9_test022".

[NOTE :EL0503] simple_abc9/abc9.v:243 Top level module "work@abc9_test023".

[NOTE :EL0503] simple_abc9/abc9.v:254 Top level module "work@abc9_test024".

[NOTE :EL0503] simple_abc9/abc9.v:262 Top level module "work@abc9_test025".

[NOTE :EL0503] simple_abc9/abc9.v:266 Top level module "work@abc9_test026".

[NOTE :EL0503] various/pmux2shiftx.v:1 Top level module "work@pmux2shiftx_test".

[NOTE :EL0503] various/pmux2shiftx.v:36 Top level module "work@issue01135".

[NOTE :EL0503] simple/scopes.v:1 Top level module "work@scopes_test_01".

[NOTE :EL0503] simple/specify.v:1 Top level module "work@test_specify".

[NOTE :EL0503] simple/undef_eqx_nex.v:1 Top level module "work@undef_eqx_nex".

[NOTE :EL0503] various/specify.v:35 Top level module "work@issue01144".

[NOTE :EL0503] arch/common/adffs.v:1 Top level module "work@adff".

[NOTE :EL0503] arch/common/adffs.v:12 Top level module "work@adffn".

[NOTE :EL0503] arch/common/adffs.v:23 Top level module "work@dffs".

[NOTE :EL0503] arch/common/adffs.v:34 Top level module "work@ndffnr".

[NOTE :EL0503] arch/common/tribuf.v:1 Top level module "work@tristate".

[NOTE :EL0503] svinterfaces/svinterface1_tb.v:3 Top level module "work@svinterface1_tb".

[NOTE :EL0503] simple/usb_phy_tests.v:3 Top level module "work@usb_phy_test01".

[NOTE :EL0503] simple/values.v:2 Top level module "work@test_signed".

[NOTE :EL0503] simple/values.v:17 Top level module "work@test_const".

[NOTE :EL0503] svinterfaces/svinterface_at_top_tb.v:3 Top level module "work@svinterface_at_top_tb".

[NOTE :EL0503] svinterfaces/svinterface_at_top_tb_wrapper.v:3 Top level module "work@svinterface_at_top_tb_wrapper".

[NOTE :EL0503] simple/memory.v:2 Top level module "work@memtest00".

[NOTE :EL0503] simple/memory.v:19 Top level module "work@memtest01".

[NOTE :EL0503] simple/memory.v:39 Top level module "work@memtest02".

[NOTE :EL0503] simple/memory.v:80 Top level module "work@memtest03".

[NOTE :EL0503] simple/memory.v:98 Top level module "work@memtest04".

[NOTE :EL0503] simple/memory.v:119 Top level module "work@memtest05".

[NOTE :EL0503] simple/memory.v:140 Top level module "work@memtest06_sync".

[NOTE :EL0503] simple/memory.v:159 Top level module "work@memtest06_async".

[NOTE :EL0503] simple/memory.v:180 Top level module "work@memtest07".

[NOTE :EL0503] simple/memory.v:200 Top level module "work@memtest08".

[NOTE :EL0503] simple/memory.v:210 Top level module "work@memtest09".

[NOTE :EL0503] simple/memory.v:233 Top level module "work@memtest10".

[NOTE :EL0503] simple/memory.v:249 Top level module "work@memtest11".

[NOTE :EL0503] simple/memory.v:269 Top level module "work@memtest12".

[NOTE :EL0503] simple/memory.v:282 Top level module "work@memtest13".

[NOTE :EL0503] simple/vloghammer.v:5 Top level module "work@test01".

[NOTE :EL0503] simple/vloghammer.v:11 Top level module "work@test02".

[NOTE :EL0503] simple/vloghammer.v:17 Top level module "work@test03".

[NOTE :EL0503] simple/vloghammer.v:24 Top level module "work@test04".

[NOTE :EL0503] simple/vloghammer.v:46 Top level module "work@test07".

[NOTE :EL0503] simple/vloghammer.v:53 Top level module "work@test08".

[NOTE :EL0503] simple/vloghammer.v:60 Top level module "work@test09".

[NOTE :EL0503] simple/vloghammer.v:68 Top level module "work@test10".

[NOTE :EL0503] techmap/mem_simple_4x1_tb.v:1 Top level module "work@tb".

[NOTE :EL0503] simple/task_func.v:2 Top level module "work@task_func_test01".

[NOTE :EL0503] simple/task_func.v:38 Top level module "work@task_func_test02".

[NOTE :EL0503] simple/task_func.v:71 Top level module "work@task_func_test03".

[NOTE :EL0503] simple/task_func.v:86 Top level module "work@task_func_test04".

[NOTE :EL0503] simple/task_func.v:127 Top level module "work@task_func_test05".

[NOTE :EL0503] various/abc9.v:1 Top level module "work@abc9_test027".

[NOTE :EL0503] various/abc9.v:7 Top level module "work@abc9_test028".

[NOTE :EL0503] svinterfaces/svinterface_at_top_wrapper.v:3 Top level module "work@svinterface_at_top_wrapper".

[NOTE :EL0503] various/shregmap.v:1 Top level module "work@shregmap_static_test".

[NOTE :EL0503] arch/common/fsm.v:1 Top level module "work@fsm".

[NOTE :EL0503] various/muxpack.v:1 Top level module "work@mux_if_unbal_4_1".

[NOTE :EL0503] various/muxpack.v:10 Top level module "work@mux_if_unbal_5_3".

[NOTE :EL0503] various/muxpack.v:21 Top level module "work@mux_if_unbal_5_3_invert".

[NOTE :EL0503] various/muxpack.v:35 Top level module "work@mux_if_unbal_5_3_width_mismatch".

[NOTE :EL0503] various/muxpack.v:46 Top level module "work@mux_if_unbal_4_1_missing".

[NOTE :EL0503] various/muxpack.v:56 Top level module "work@mux_if_unbal_5_3_order".

[NOTE :EL0503] various/muxpack.v:67 Top level module "work@mux_if_unbal_4_1_nonexcl".

[NOTE :EL0503] various/muxpack.v:77 Top level module "work@mux_if_unbal_5_3_nonexcl".

[NOTE :EL0503] various/muxpack.v:89 Top level module "work@mux_case_unbal_8_7".

[NOTE :EL0503] various/muxpack.v:114 Top level module "work@mux_if_bal_8_2".

[NOTE :EL0503] various/muxpack.v:140 Top level module "work@mux_if_bal_5_1".

[NOTE :EL0503] various/muxpack.v:157 Top level module "work@cliffordwolf_nonexclusive_select".

[NOTE :EL0503] various/muxpack.v:170 Top level module "work@cliffordwolf_freduce".

[NOTE :EL0503] various/muxpack.v:183 Top level module "work@case_nonexclusive_select".

[NOTE :EL0503] various/muxpack.v:202 Top level module "work@case_nonoverlap".

[NOTE :EL0503] various/muxpack.v:221 Top level module "work@case_overlap".

[NOTE :EL0503] various/muxpack.v:241 Top level module "work@case_overlap2".

[NOTE :EL0503] techmap/mem_simple_4x1_map.v:2 Top level module "work@$mem".

[NOTE :EL0503] arch/common/dffs.v:6 Top level module "work@dffe".

[NOTE :EL0503] arch/xilinx/macc.v:7 Top level module "work@macc".

[NOTE :EL0503] arch/xilinx/macc.v:44 Top level module "work@macc2".

[NOTE :EL0503] arch/common/latches.v:1 Top level module "work@latchp".

[NOTE :EL0503] arch/common/latches.v:7 Top level module "work@latchn".

[NOTE :EL0503] arch/common/latches.v:13 Top level module "work@latchsr".

[NOTE :EL0503] arch/common/mux.v:1 Top level module "work@mux2".

[NOTE :EL0503] arch/common/mux.v:10 Top level module "work@mux4".

[NOTE :EL0503] arch/common/mux.v:30 Top level module "work@mux8".

[NOTE :EL0503] arch/common/mux.v:54 Top level module "work@mux16".

[NOTE :EL0503] arch/ice40/macc.v:27 Top level module "work@top2".

[NOTE :EL0503] arch/xilinx/mul_unsigned.v:10 Top level module "work@mul_unsigned".

[NOTE :EL0503] arch/xilinx/xilinx_srl.v:1 Top level module "work@xilinx_srl_static_test".

[NOTE :EL0503] arch/xilinx/xilinx_srl.v:15 Top level module "work@xilinx_srl_variable_test".

[WARNI:EL0505] asicworld/code_verilog_tutorial_first_counter_tb.v:1 Multiply defined module "work@MODULE NAME UNKNOWN",
               asicworld/code_hdl_models_arbiter_tb.v:1 previous definition,
               asicworld/code_verilog_tutorial_fsm_full_tb.v:1 previous definition,
               lut/map_mux.v:1 previous definition,
               lut/map_not.v:1 previous definition,
               lut/map_or.v:1 previous definition,
               lut/map_xor.v:1 previous definition,
               lut/map_and.v:1 previous definition,
               lut/map_cmp.v:1 previous definition,
               opt/opt_expr_cmp.v:1 previous definition,
               various/constmsk_testmap.v:1 previous definition,
               various/shregmap.v:15 previous definition,
               arch/xilinx/xilinx_srl.v:29 previous definition.

[WARNI:EL0505] svinterfaces/svinterface1_ref.v:35 Multiply defined module "work@SubModule1",
               svinterfaces/svinterface_at_top_ref.v:43 previous definition.

[WARNI:EL0505] svinterfaces/svinterface1_ref.v:79 Multiply defined module "work@SubModule2",
               svinterfaces/svinterface_at_top_ref.v:92 previous definition.

[WARNI:EL0505] svinterfaces/svinterface1_ref.v:2 Multiply defined module "work@TopModule",
               svinterfaces/svinterface_at_top_ref.v:2 previous definition.

[WARNI:EL0505] errors/syntax_err06.v:1 Multiply defined module "work@a",
               errors/syntax_err04.v:1 previous definition,
               errors/syntax_err08.v:1 previous definition,
               errors/syntax_err10.v:1 previous definition,
               errors/syntax_err13.v:1 previous definition,
               errors/syntax_err01.v:1 previous definition,
               errors/syntax_err02.v:1 previous definition,
               errors/syntax_err03.v:1 previous definition,
               errors/syntax_err05.v:1 previous definition,
               errors/syntax_err07.v:1 previous definition,
               errors/syntax_err09.v:1 previous definition,
               errors/syntax_err11.v:1 previous definition,
               errors/syntax_err12.v:4 previous definition.

[WARNI:EL0505] asicworld/code_verilog_tutorial_comment.v:4 Multiply defined module "work@addbit",
               asicworld/code_verilog_tutorial_addbit.v:1 previous definition,
               asicworld/code_verilog_tutorial_good_code.v:1 previous definition.

[WARNI:EL0505] simple_abc9/abc9.v:206 Multiply defined module "work@arbiter",
               asicworld/code_hdl_models_arbiter.v:5 previous definition.

[WARNI:EL0505] simple/attrib03_parameter.v:1 Multiply defined module "work@bar",
               simple/attrib04_net_var.v:1 previous definition,
               simple/attrib09_case.v:1 previous definition,
               simple/attrib02_port_decl.v:1 previous definition,
               simple/attrib08_mod_inst.v:1 previous definition,
               simple/attrib01_module.v:1 previous definition,
               simple/attrib06_operator_suffix.v:1 previous definition,
               simple/wandwor.v:34 previous definition,
               various/attrib05_port_conn.v:1 previous definition.

[WARNI:EL0505] sat/counters.v:2 Multiply defined module "work@counter1",
               sat/counters-repeat.v:3 previous definition.

[WARNI:EL0505] sat/counters.v:17 Multiply defined module "work@counter2",
               sat/counters-repeat.v:18 previous definition.

[WARNI:EL0505] simple/dff_different_styles.v:2 Multiply defined module "work@dff",
               asicworld/code_verilog_tutorial_explicit.v:19 previous definition,
               arch/common/dffs.v:1 previous definition.

[WARNI:EL0505] hana/test_intermout.v:137 Multiply defined module "work@f11_test",
               hana/test_simulation_always.v:127 previous definition.

[WARNI:EL0505] hana/test_simulation_and.v:3 Multiply defined module "work@f1_test",
               hana/test_parser.v:3 previous definition,
               hana/test_simulation_inc.v:3 previous definition,
               hana/test_simulation_nand.v:3 previous definition,
               hana/test_simulation_nor.v:3 previous definition,
               hana/test_simulation_or.v:3 previous definition,
               hana/test_simulation_seq.v:3 previous definition,
               hana/test_simulation_shifter.v:3 previous definition,
               hana/test_simulation_techmap.v:3 previous definition,
               hana/test_simulation_always.v:3 previous definition,
               hana/test_simulation_decoder.v:3 previous definition,
               hana/test_parse2synthtrans.v:3 previous definition,
               hana/test_simulation_buffer.v:3 previous definition,
               hana/test_simulation_mux.v:3 previous definition,
               hana/test_simulation_sop.v:3 previous definition,
               hana/test_intermout.v:3 previous definition,
               hana/test_simulation_vlib.v:2 previous definition,
               hana/test_simulation_xnor.v:3 previous definition,
               hana/test_simulation_xor.v:3 previous definition.

[WARNI:EL0505] hana/test_simulation_and.v:8 Multiply defined module "work@f2_test",
               hana/test_parser.v:7 previous definition,
               hana/test_simulation_inc.v:10 previous definition,
               hana/test_simulation_nand.v:8 previous definition,
               hana/test_simulation_nor.v:8 previous definition,
               hana/test_simulation_or.v:8 previous definition,
               hana/test_simulation_seq.v:9 previous definition,
               hana/test_simulation_shifter.v:9 previous definition,
               hana/test_simulation_techmap.v:8 previous definition,
               hana/test_simulation_always.v:10 previous definition,
               hana/test_simulation_decoder.v:19 previous definition,
               hana/test_simulation_buffer.v:8 previous definition,
               hana/test_simulation_mux.v:27 previous definition,
               hana/test_simulation_sop.v:13 previous definition,
               hana/test_intermout.v:18 previous definition,
               hana/test_simulation_vlib.v:16 previous definition,
               hana/test_simulation_xnor.v:8 previous definition,
               hana/test_simulation_xor.v:8 previous definition.

[WARNI:EL0505] hana/test_simulation_and.v:13 Multiply defined module "work@f3_test",
               hana/test_parser.v:19 previous definition,
               hana/test_simulation_inc.v:17 previous definition,
               hana/test_simulation_nand.v:13 previous definition,
               hana/test_simulation_nor.v:13 previous definition,
               hana/test_simulation_or.v:13 previous definition,
               hana/test_simulation_shifter.v:15 previous definition,
               hana/test_simulation_techmap.v:13 previous definition,
               hana/test_simulation_always.v:25 previous definition,
               hana/test_simulation_decoder.v:35 previous definition,
               hana/test_parse2synthtrans.v:55 previous definition,
               hana/test_simulation_buffer.v:14 previous definition,
               hana/test_simulation_mux.v:37 previous definition,
               hana/test_simulation_sop.v:25 previous definition,
               hana/test_intermout.v:30 previous definition,
               hana/test_simulation_xnor.v:13 previous definition,
               hana/test_simulation_xor.v:13 previous definition.

[WARNI:EL0505] hana/test_simulation_inc.v:24 Multiply defined module "work@f4_test",
               hana/test_simulation_and.v:18 previous definition,
               hana/test_simulation_nand.v:18 previous definition,
               hana/test_simulation_nor.v:18 previous definition,
               hana/test_simulation_or.v:18 previous definition,
               hana/test_simulation_shifter.v:21 previous definition,
               hana/test_simulation_techmap.v:23 previous definition,
               hana/test_simulation_always.v:37 previous definition,
               hana/test_simulation_decoder.v:51 previous definition,
               hana/test_parse2synthtrans.v:64 previous definition,
               hana/test_simulation_mux.v:78 previous definition,
               hana/test_simulation_sop.v:41 previous definition,
               hana/test_intermout.v:41 previous definition,
               hana/test_simulation_xnor.v:18 previous definition,
               hana/test_simulation_xor.v:18 previous definition.

[WARNI:EL0505] hana/test_simulation_and.v:23 Multiply defined module "work@f5_test",
               hana/test_parser.v:41 previous definition,
               hana/test_simulation_inc.v:31 previous definition,
               hana/test_simulation_nand.v:23 previous definition,
               hana/test_simulation_or.v:23 previous definition,
               hana/test_simulation_shifter.v:27 previous definition,
               hana/test_simulation_techmap.v:159 previous definition,
               hana/test_simulation_always.v:50 previous definition,
               hana/test_simulation_decoder.v:70 previous definition,
               hana/test_parse2synthtrans.v:68 previous definition,
               hana/test_simulation_mux.v:90 previous definition,
               hana/test_simulation_sop.v:48 previous definition.

[WARNI:EL0505] hana/test_simulation_inc.v:38 Multiply defined module "work@f6_test",
               hana/test_simulation_and.v:28 previous definition,
               hana/test_simulation_or.v:28 previous definition,
               hana/test_simulation_shifter.v:33 previous definition,
               hana/test_simulation_decoder.v:99 previous definition,
               hana/test_parse2synthtrans.v:81 previous definition,
               hana/test_simulation_mux.v:163 previous definition,
               hana/test_simulation_sop.v:53 previous definition.

[WARNI:EL0505] hana/test_intermout.v:84 Multiply defined module "work@f7_FlipFlop",
               hana/test_simulation_always.v:74 previous definition.

[WARNI:EL0505] hana/test_simulation_and.v:33 Multiply defined module "work@f7_test",
               hana/test_parser.v:80 previous definition,
               hana/test_simulation_shifter.v:39 previous definition,
               hana/test_simulation_decoder.v:144 previous definition,
               hana/test_parse2synthtrans.v:90 previous definition,
               hana/test_simulation_sop.v:58 previous definition.

[WARNI:EL0505] hana/test_intermout.v:99 Multiply defined module "work@f8_inc",
               hana/test_simulation_always.v:87 previous definition.

[WARNI:EL0505] hana/test_parse2synthtrans.v:98 Multiply defined module "work@f8_test",
               hana/test_simulation_shifter.v:45 previous definition,
               hana/test_simulation_sop.v:63 previous definition.

[WARNI:EL0505] hana/test_parse2synthtrans.v:109 Multiply defined module "work@f9_test",
               hana/test_simulation_shifter.v:51 previous definition.

[WARNI:EL0505] simple/attrib03_parameter.v:20 Multiply defined module "work@foo",
               simple/attrib04_net_var.v:24 previous definition,
               simple/attrib09_case.v:18 previous definition,
               simple/attrib02_port_decl.v:16 previous definition,
               simple/attrib08_mod_inst.v:13 previous definition,
               simple/attrib01_module.v:13 previous definition,
               simple/attrib06_operator_suffix.v:14 previous definition,
               simple/wandwor.v:30 previous definition,
               techmap/recursive.v:6 previous definition,
               various/attrib05_port_conn.v:13 previous definition,
               various/attrib07_func_call.v:9 previous definition.

[WARNI:EL0505] memories/simple_sram_byte_en.v:4 Multiply defined module "work@generic_sram_byte_en",
               memories/amber23_sram_byte_en.v:45 previous definition.

[WARNI:EL0505] opt/opt_share_large_pmux_part.v:1 Multiply defined module "work@opt_share_test",
               opt/opt_share_add_sub.v:1 previous definition,
               opt/opt_share_cat.v:1 previous definition,
               opt/opt_share_diff_port_widths.v:1 previous definition,
               opt/opt_share_large_pmux_cat.v:1 previous definition,
               opt/opt_share_large_pmux_multipart.v:1 previous definition,
               opt/opt_share_cat_multiuser.v:1 previous definition,
               opt/opt_share_extend.v:1 previous definition,
               opt/opt_share_large_pmux_cat_multipart.v:1 previous definition,
               opt/opt_share_mux_tree.v:1 previous definition.

[WARNI:EL0505] sat/splice.v:1 Multiply defined module "work@test",
               memories/implicit_en.v:4 previous definition,
               sat/asserts.v:2 previous definition,
               memories/no_implicit_en.v:4 previous definition,
               sat/initval.v:1 previous definition,
               memories/shared_ports.v:4 previous definition,
               various/specify.v:1 previous definition,
               various/constmsk_test.v:1 previous definition.

[WARNI:EL0505] various/specify.v:16 Multiply defined module "work@test2",
               sat/expose_dff.v:7 previous definition.

[WARNI:EL0505] arch/xilinx/macc_tb.v:3 Multiply defined module "work@testbench",
               asicworld/code_verilog_tutorial_counter_tb.v:16 previous definition.

[WARNI:EL0505] opt/opt_rmdff_sat.v:1 Multiply defined module "work@top",
               opt/opt_lut.v:1 previous definition,
               memories/firrtl_938.v:1 previous definition,
               rpc/design.v:1 previous definition,
               memories/issue00710.v:5 previous definition,
               memories/read_two_mux.v:5 previous definition,
               simple/hierarchy.v:2 previous definition,
               arch/common/memory.v:1 previous definition,
               arch/common/mul.v:1 previous definition,
               arch/common/shifter.v:1 previous definition,
               arch/ecp5/dpram.v:4 previous definition,
               arch/ice40/dpram.v:4 previous definition,
               techmap/recursive.v:1 previous definition,
               arch/common/counter.v:1 previous definition,
               arch/ecp5/macc.v:4 previous definition,
               arch/ice40/rom.v:4 previous definition,
               arch/common/add_sub.v:1 previous definition,
               arch/common/logic.v:1 previous definition,
               arch/ecp5/rom.v:4 previous definition,
               arch/ice40/macc.v:4 previous definition.

[WARNI:EL0505] simple/process.v:61 Multiply defined module "work@uart",
               asicworld/code_hdl_models_uart.v:7 previous definition.

[WARNI:EL0505] techmap/mem_simple_4x1_uut.v:1 Multiply defined module "work@uut",
               simple/process.v:21 previous definition,
               various/async.v:1 previous definition.

[NOTE :EL0504] Multiple top level modules in design.

[WARNI:EL0500] opt/opt_rmdff.v:2 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:4 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:5 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:6 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:8 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:9 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:10 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:12 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:14 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_PP_".

[WARNI:EL0500] opt/opt_rmdff.v:16 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_PP_".

[WARNI:EL0500] opt/opt_rmdff.v:17 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_PP_".

[WARNI:EL0500] opt/opt_rmdff.v:18 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_PP_".

[WARNI:EL0500] opt/opt_rmdff.v:20 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_PP_".

[WARNI:EL0500] opt/opt_rmdff.v:22 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_NN_".

[WARNI:EL0500] opt/opt_rmdff.v:24 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_NN_".

[WARNI:EL0500] opt/opt_rmdff.v:25 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_NN_".

[WARNI:EL0500] opt/opt_rmdff.v:26 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_NN_".

[WARNI:EL0500] opt/opt_rmdff.v:28 Cannot find a module definition for "work@opt_rmdff_test::$_DFFE_NN_".

[WARNI:EL0500] opt/opt_rmdff.v:30 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:32 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:33 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:35 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:39 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:41 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:43 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:44 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:45 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:46 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[WARNI:EL0500] opt/opt_rmdff.v:48 Cannot find a module definition for "work@opt_rmdff_test::$dffe".

[ERROR:EL0514] simple/generate.v:131 Undefined variable: DIM.

[WARNI:EL0500] various/abc9.v:9 Cannot find a module definition for "work@abc9_test028::unknown".

[WARNI:EL0500] various/abc9.v:10 Cannot find a module definition for "work@abc9_test028::unknown2".

[WARNI:EL0500] svinterfaces/svinterface_at_top_wrapper.v:20 Cannot find a module definition for "work@svinterface_at_top_wrapper::clk".

[WARNI:EL0500] svinterfaces/svinterface_at_top_wrapper.v:26 Cannot find a module definition for "work@svinterface_at_top_wrapper::setting".

[WARNI:EL0500] svinterfaces/svinterface_at_top_wrapper.v:27 Cannot find a module definition for "work@svinterface_at_top_wrapper::other_setting".

[WARNI:EL0500] svinterfaces/svinterface_at_top_wrapper.v:28 Cannot find a module definition for "work@svinterface_at_top_wrapper::mysig_out".

[WARNI:EL0500] svinterfaces/svinterface_at_top_wrapper.v:29 Cannot find a module definition for "work@svinterface_at_top_wrapper::passThrough".

[ERROR:EL0507] techmap/mem_simple_4x1_map.v:111 Instantiation loop for "work@$__mem_4x1_generator",
               techmap/mem_simple_4x1_map.v:82 previous instantiation.

[ERROR:EL0507] techmap/mem_simple_4x1_map.v:125 Instantiation loop for "work@$__mem_4x1_generator",
               techmap/mem_simple_4x1_map.v:82 previous instantiation.

[WARNI:EL0515] simple/hierdefparam.v:7 Defparam does not match any design object: "work@hierdefparam_top.foo.mod_a.bar[0].mod_b.addvalue".

[WARNI:EL0515] simple/hierdefparam.v:8 Defparam does not match any design object: "work@hierdefparam_top.foo.mod_a.bar[1].mod_b.addvalue".

[NOTE :EL0508] Nb Top level modules: 454.

[NOTE :EL0509] Max instance depth: 5.

[NOTE :EL0510] Nb instances: 665.

[NOTE :EL0511] Nb leaf instances: 402.

[WARNI:EL0512] Nb undefined modules: 10.

[WARNI:EL0513] Nb undefined instances: 46.

[  FATAL] : 0
[  ERROR] : 38
[WARNING] : 568
[   NOTE] : 746

********************************************
*   End SURELOG SVerilog Compiler/Linter   *
********************************************

18.51user 0.37system 0:05.45elapsed 346%CPU (0avgtext+0avgdata 354636maxresident)k
16inputs+3328outputs (0major+86081minor)pagefaults 0swaps