commit | 310bd9208f75ca47d3c9c60dd045e07b46ff5848 | [log] [tgz] |
---|---|---|
author | Alain Dargelas <5085492+alainmarcel@users.noreply.github.com> | Fri Nov 29 10:15:45 2019 -1000 |
committer | GitHub <noreply@github.com> | Fri Nov 29 10:15:45 2019 -1000 |
tree | b9a224b019da40bd8538b900e88265595c01d5c7 | |
parent | 0422d6f0f2f9a405c3db72e6416a16bfef511aef [diff] | |
parent | 6ec449e8c2f94e47bb9f3c1b3fe588c16fc5c05d [diff] |
Merge pull request #115 from alainmarcel/alainmarcel-patch-1 test update
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models.
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALL
make make install (/usr/local/bin and /usr/local/lib/surelog by default, use DESTDIR= for alternative locations)
For more build/test options and system requirements for building see src/README
file.
The executable is located here (If not installed in:
STANDARD VERILOG COMMAND LINE:
FLOWS OPTIONS:
TRACES OPTIONS:
OUTPUT OPTIONS:
RETURN CODE
The file slformatmsg.py
illustrates how messages can be reformated.
The file src/API/slSV3_1aPythonListener.py
illustrates how a listener can be created to listen to the Parser AST.
A simple example of creating a new error message and generating errors can be found here: python_listener.py
A simple example for design-level data model exploration can be found here: myscriptPerDesign.py
The complete Python API is described in the following files: SLAPI.h
vobjecttypes
Waivers can be installed in slwaivers.py files in the execution directory or install directory /usr/local/lib/surelog/python
src/README
file.