| commit | a2bca728a49ae571d9e4c5859468aaacef5604b7 | [log] [tgz] |
|---|---|---|
| author | Alain <alainmarcel@yahoo.com> | Thu Nov 21 21:28:17 2019 -0800 |
| committer | Alain <alainmarcel@yahoo.com> | Thu Nov 21 21:28:17 2019 -0800 |
| tree | 8e6c34efeec6801530cc91c2e31ce9d7c7a5b589 | |
| parent | fb8c7d5ebe3bb161a0a30938b86be7898978d405 [diff] | |
| parent | cad7aea7666a37c932253b201d4ca8fdc0cf7e24 [diff] |
Merge branch 'master' into alainmarcel-patch-1
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models.
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALLmake make install (/usr/local/bin and /usr/local/lib/surelog by default, use DESTDIR= for alternative locations)
For more build/test options and system requirements for building see src/README file.
The executable is located here (If not installed in:
STANDARD VERILOG COMMAND LINE:
FLOWS OPTIONS:
TRACES OPTIONS:
OUTPUT OPTIONS:
RETURN CODE