   -full64 -PP -notice -line  +lint=all,noVCDE,noUI +v2k -timescale=1ns/10ps -quiet +define+DEBUG -debug_pp +incdir+src/main/verilog  -Mdirectory=sim/csrc +vc+list -CC "-I/include" -CC "-std=c++11"  src/test/verilog/vscale_hex_tb.v  src/test/verilog/vscale_sim_top.v src/test/verilog/vscale_dp_hasti_sram.v src/main/verilog/vscale_core.v  -writepp -parse -mt max src/main/verilog/vscale_hasti_bridge.v src/main/verilog/vscale_pipeline.v  src/main/verilog/vscale_ctrl.v src/main/verilog/vscale_regfile.v src/main/verilog/vscale_src_a_mux.v  src/main/verilog/vscale_src_b_mux.v src/main/verilog/vscale_imm_gen.v src/main/verilog/vscale_alu.v  src/main/verilog/vscale_mul_div.v src/main/verilog/vscale_csr_file.v src/main/verilog/vscale_PC_mux.v