| commit | b4f31fab7cc43026a264b32348eecb6f94a7b0b5 | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Thu Nov 21 01:36:24 2019 -0800 |
| committer | Henner Zeller <h.zeller@acm.org> | Thu Nov 21 01:54:12 2019 -0800 |
| tree | 329fef36777519534b059da8b932d4ebbb4e3377 | |
| parent | 4ca2f7a6a1ebd89ad40fd1016c8c42ebe1974e29 [diff] |
Code-clean: Modernize class Value and its implementations.
Mostly to improve code robustness and follow style-guides.
General cleanup:
* Add a virtual destructor in the base class (otherwise strange things
might happen)
* Use 'final' overridden virtuals. This allows compiler errors if
signature changes in base-class thus robust ways to refactor. Also,
'final' allows the compiler to optimize away a virtual method look-up
if it can infer the exact type at compile-time.
* Use constructor initializer lists instead of assigning in constructor
body.
* Type enum: use enum class for more type-safe and enforced scoped use.
(this required some small changes outside the Value.{h,cpp} files).
* Use nullptr instead of NULL.
Const cleanness:
* Getter methods that don't change anything: make const. This way they can be
used in a const context.
* operators < and ==: make const member operators and also have their parameters
be const (otherwise all kinds of algorithms will stumble upon this)
* Make setter take a const std::string& instead of std::string by value.
* Copy constructors: take const reference parameter
* Make parameters whose values are guaranteed to not be modifed const
e.g. plus()/minus()/.. etc)
Behavior change:
* Use strtod() instead of atof() to parse double value (avoid
loss of precision)
Signed-off-by: Henner Zeller <h.zeller@acm.org>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALLmake make install (/usr/local/bin and /usr/local/lib/surelog by default, use DESTDIR= for alternative locations)
For more build/test options and system requirements for building see src/README file.
The executable is located here (If not installed in:
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
default_nettype in pre-processor's output
RETURN CODE