Testcases
diff --git "a/SVIncCompil/Testcases/Verilator/\043Verilator_diff.log\043" "b/SVIncCompil/Testcases/Verilator/\043Verilator_diff.log\043" new file mode 100644 index 0000000..cbd96a5 --- /dev/null +++ "b/SVIncCompil/Testcases/Verilator/\043Verilator_diff.log\043"
@@ -0,0 +1,395 @@ +******************************************** +* SURELOG System Verilog Compiler/Linter * +******************************************** + +[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. + +[INFO :CM0020] Separate compilation-unit mode is on. + +[ERROR:PP0102] t_sv_cpu_code/ports.sv, line 44, col 9: Unknown macro "PACKED". + +[ERROR:PP0102] t_sv_cpu_code/ports.sv, line 49, col 11: Unknown macro "PACKED". + +[ERROR:PP0101] t_sv_cpu_code/program_h.sv, line 31: Cannot open include file "rom.sv". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 18, col 6: Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 19, col 6: Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 20, col 6: Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 21, col 6: Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 23, col 6: Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 24, col 6: Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 25, col 6: Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 26, col 6: Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 28, col 6: Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 29, col 6: Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 30, col 6: Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 31, col 6: Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 33, col 6: Unknown macro "JMP". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 35, col 6: Unknown macro "EOP". + +[ERROR:PP0101] t_case_write1.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0102] t_case_write1.v, line 37, col 43: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_case_write1.v, line 38, col 36: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_case_write1_tasks.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0101] t_case_write2.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0102] t_case_write2.v, line 37, col 43: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_case_write2.v, line 38, col 36: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_case_write2_tasks.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0106] t_clk_2in.v, line 26, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif + ^-- line 26, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 87, col 20: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif + ^-- line 87, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 108, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif + ^-- line 108, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 112, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif + ^-- line 112, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 116, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif + ^-- line 116, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 121, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif + ^-- line 121, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 125, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif + ^-- line 125, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 129, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("n`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif + ^-- line 135, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 139, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif + ^-- line 139, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 143, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("or vec"); `endif + ^-- line 143, t_clk_2in.v. + +[ERROR:PP0107] t_clk_2in.v, line 62: Too many arguments (4) for macro "t2", +t_clk_2in.v, line 59: macro definition takes 0. + +[ERROR:PP0106] t_clk_gen.v, line 79, col 17: Syntax error: extraneous input '`else' expecting {One_line_comment, Spaces, CR}, +`ifdef verilator `else // V3.2 races... technically legal + ^-- line 79, t_clk_gen.v. + +[ERROR:PP0118] t_display.v, line 13, col 39: Unknown escaped sequence '\2'. + +[ERROR:PP0118] t_display.v, line 134, col 30: Unknown escaped sequence '\r'. + +[ERROR:PP0118] t_display_esc_bad.v, line 8, col 19: Unknown escaped sequence '\y'. + +[ERROR:PP0118] t_display_esc_bad.v, line 8, col 21: Unknown escaped sequence '\z'. + +[ERROR:PP0101] t_dpi_accessors.v, line 39: Cannot open include file "t_dpi_accessors_macros_inc.vh". + +[ERROR:PP0101] t_dpi_accessors.v, line 40: Cannot open include file "t_dpi_accessors_inc.vh". + +[ERROR:PP0102] t_dpi_display.v, line 11, col 3: Unknown macro "error". + +[ERROR:PP0102] t_dpi_sys.v, line 15, col 3: Unknown macro "error". + +[ERROR:PP0102] t_dpi_threads.v, line 19, col 3: Unknown macro "error". + +[ERROR:PP0102] t_dpi_var.v, line 66: Unknown macro "systemc_imp_header". + +[ERROR:PP0102] t_dpi_var.v, line 69: Unknown macro "verilog". + +[ERROR:PP0102] t_extend_class.v, line 48, col 1: Unknown macro "systemc_header". + +[ERROR:PP0102] t_extend_class.v, line 50, col 1: Unknown macro "systemc_interface". + +[ERROR:PP0102] t_extend_class.v, line 52, col 1: Unknown macro "systemc_ctor". + +[ERROR:PP0102] t_extend_class.v, line 54, col 1: Unknown macro "systemc_dtor". + +[ERROR:PP0102] t_extend_class.v, line 56, col 1: Unknown macro "verilog". + +[ERROR:PP0101] t_flag_f.v, line 3: Cannot open include file "t_flag_f_tsub_inc.v". + +[ERROR:PP0106] t_func_dotted.v, line 104, col 18: Syntax error: extraneous input '#1' expecting {One_line_comment, Spaces, CR}, +`ifndef verilator #1; `endif + ^-- line 104, t_func_dotted.v. + +[ERROR:PP0106] t_func_dotted.v, line 129, col 18: Syntax error: extraneous input '#1' expecting {One_line_comment, Spaces, CR}, +`ifndef verilator #1; `endif + ^-- line 129, t_func_dotted.v. + +[NOTE :PP0105] t_func_flip.v, line 7: Multiply defined macro "INT_RANGE", + t_func_flip.v, line 6: previous definition. + +[ERROR:PP0102] t_gen_missing.v, line 13, col 1: Unknown macro "error". + +[ERROR:PP0101] t_initial.v, line 13: Cannot open include file "t_initial_inc.vh". + +[ERROR:PP0106] t_inst_dtree.v, line 62, col 20: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif + ^-- line 62, t_inst_dtree.v. + +[ERROR:PP0106] t_interface2.v, line 25, col 17: Syntax error: extraneous input 'counter_ansi' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + ^-- line 25, t_interface2.v. + +[ERROR:PP0106] t_interface2.v, line 25, col 36: Syntax error: extraneous input 'counter_nansi' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + ^-- line 25, t_interface2.v. + +[ERROR:PP0102] t_interface_down_gen.v, line 75: Unknown macro "error". + +[ERROR:PP0106] t_interface_modport.v, line 42, col 17: Syntax error: extraneous input 'counter_ansi' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + ^-- line 42, t_interface_modport.v. + +[ERROR:PP0106] t_interface_modport.v, line 42, col 36: Syntax error: extraneous input 'counter_nansi' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + ^-- line 42, t_interface_modport.v. + +[ERROR:PP0106] t_interface_modport.v, line 49, col 17: Syntax error: extraneous input 'counter_ansi_m' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif + ^-- line 49, t_interface_modport.v. + +[ERROR:PP0106] t_interface_modport.v, line 49, col 38: Syntax error: extraneous input 'counter_nansi_m' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif + ^-- line 49, t_interface_modport.v. + +[ERROR:PP0120] t_lint_implicit_def_bad.v, line 21: Illegal directive in design element "`resetall". + +[ERROR:PP0101] t_lint_in_inc_bad.v, line 6: Cannot open include file "t_lint_in_inc_bad_1.vh". + +[ERROR:PP0102] t_lint_unused.v, line 31, col 35: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_lint_unused.v, line 34, col 34: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0107] t_math_clog2.v, line 26: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 27: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 28: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 29: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 46: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 47: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 48: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 49: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 50: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 51: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 52: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 53: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 54: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 55: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 56: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 57: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 58: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[WARNI:PP0113] t_math_signed5.v, line 11, col 9: Unused macro argument "vs". + +[ERROR:PP0101] t_pipe_filter.v, line 13: Cannot open include file "t_pipe_filter_inc.vh". + +[ERROR:PP0101] t_pipe_filter.v, line 15: Cannot open include file "t_pipe_filter_inc.vh". + +[ERROR:PP0115] t_pp_circdef_bad.v, line 9: Recursive macro definition for "SEL_NUM_BITS", + t_pp_circdef_bad.v, line 9: macro used in macro "SEL_NUM_BITS". + +[ERROR:PP0102] t_pp_circdef_bad.v, line 9, col 7: Unknown macro "SEL_NUM_BITS". + +[ERROR:PP0102] t_pp_circdef_bad.v, line 9, col 24: Unknown macro "SEL_NUM_BITS". + +[WARNI:PP0113] t_pp_display.v, line 20, col 8: Unused macro argument "left". + +[ERROR:PP0109] t_pp_display.v, line 34: Macro instantiation omits argument 1 (x) for "thru", +t_pp_display.v, line 17: No default value for argument 1 (x) in macro definition. + +[NOTE :PP0105] t_pp_dupdef.v, line 9: Multiply defined macro "DUP", + t_pp_dupdef.v, line 8: previous definition. + +[NOTE :PP0105] t_pp_dupdef.v, line 12: Multiply defined macro "DUPP", + t_pp_dupdef.v, line 11: previous definition. + +[ERROR:PP0101] t_pp_lib.v, line 6: Cannot open include file "t_pp_lib_inc.vh". + +[ERROR:PP0102] t_pp_lib.v, line 8, col 9: Unknown macro "WIDTH". + +[ERROR:PP0102] t_pp_lib_library.v, line 7, col 10: Unknown macro "WIDTH". + +[ERROR:PP0102] t_pp_misdef_bad.v, line 10, col 3: Unknown macro "NDEFINED". + +[ERROR:PP0102] t_pp_misdef_bad.v, line 13, col 5: Unknown macro "imescale". + +[ERROR:PP0102] t_pp_pragmas.v, line 7: Unknown macro "verilog". + +[ERROR:PP0102] t_pp_pragmas.v, line 40: Unknown macro "remove_gatenames". + +[ERROR:PP0102] t_pp_pragmas.v, line 42: Unknown macro "remove_netnames". + +[ERROR:PP0106] t_preproc.v, line 23, col 19: Syntax error: extraneous input '1'b1 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A3 1'b1 `else 1'b0 `endif , + ^-- line 23, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 23, col 30: Syntax error: extraneous input '1'b0 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A3 1'b1 `else 1'b0 `endif , + ^-- line 23, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 23, col 42: Syntax error: no viable alternative at input '`endif ,', + `ifdef DEF_A3 1'b1 `else 1'b0 `endif , + ^-- line 23, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 24, col 19: Syntax error: extraneous input '1'b1 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A2 1'b1 `else 1'b0 `endif , + ^-- line 24, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 24, col 30: Syntax error: extraneous input '1'b0 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A2 1'b1 `else 1'b0 `endif , + ^-- line 24, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 24, col 42: Syntax error: no viable alternative at input '`endif ,', + `ifdef DEF_A2 1'b1 `else 1'b0 `endif , + ^-- line 24, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 25, col 19: Syntax error: extraneous input '1'b1 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A1 1'b1 `else 1'b0 `endif , + ^-- line 25, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 25, col 30: Syntax error: extraneous input '1'b0 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A1 1'b1 `else 1'b0 `endif , + ^-- line 25, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 25, col 42: Syntax error: no viable alternative at input '`endif ,', + `ifdef DEF_A1 1'b1 `else 1'b0 `endif , + ^-- line 25, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 26, col 19: Syntax error: extraneous input '1'b1 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A0 1'b1 `else 1'b0 `endif + ^-- line 26, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 26, col 30: Syntax error: extraneous input '1'b0 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A0 1'b1 `else 1'b0 `endif + ^-- line 26, t_preproc.v. + +[ERROR:PP0101] t_preproc.v, line 7: Cannot open include file "t_preproc_inc2.vh". + +[ERROR:PP0112] t_preproc.v, line 74, col 16: Illegal space in between macro name "noparam" and open parenthesis. + +[NOTE :PP0105] t_preproc.v, line 99: Multiply defined macro "msg", + t_preproc.v, line 77: previous definition. + +[ERROR:PP0109] t_preproc.v, line 110: Macro instantiation omits argument 1 (x) for "thru", +t_preproc.v, line 97: No default value for argument 1 (x) in macro definition. + +[ERROR:PP0112] t_preproc_def09.v, line 60, col 19: Illegal space in between macro name "MACROPAREN" and open parenthesis. + +[ERROR:PP0106] t_preproc_ifdef.v, line 17, col 9: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef A $display("1A"); num = num + 1; + ^-- line 17, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 18, col 10: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `ifdef C $stop; + ^-- line 18, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 19, col 10: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `elsif A $display("2A"); num = num + 1; + ^-- line 19, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 20, col 11: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `ifdef C $stop; + ^-- line 20, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 21, col 11: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `elsif B $stop; + ^-- line 21, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 22, col 9: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `else $display("3A"); num = num + 1; + ^-- line 22, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 24, col 8: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `else $stop; + ^-- line 24, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 26, col 10: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `elsif B $stop; + ^-- line 26, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 27, col 11: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `ifdef A $stop; + ^-- line 27, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 28, col 11: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `elsif A $stop; + ^-- line 28, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 31, col 9: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`elsif C $stop; + ^-- line 31, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 32, col 7: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`else $stop; + ^-- line 32, t_preproc_ifdef.v. + +[ERROR:PP0101] t_preproc_inc_bad.v, line 8: Cannot open include file "t_preproc_inc_inc_bad.vh". + +[ERROR:PP0101] t_preproc_inc_notfound_bad.v, line 6: Cannot open include file "this_file_is_not_found.vh". + +../../dist/surelog/surelog: line 5: 20627 Segmentation fault (core dumped) ${SCRIPTPATH}/bin/surelog.exe "$@" +Command exited with non-zero status 139 +1.75user 0.12system 0:01.99elapsed 94%CPU (0avgtext+0avgdata 552972maxresident)k +0inputs+80outputs (0major+146048minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/Verilator/Verilator.log b/SVIncCompil/Testcases/Verilator/Verilator.log new file mode 100644 index 0000000..8d3eb5f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/Verilator.log
@@ -0,0 +1,5704 @@ +******************************************** +* SURELOG System Verilog Compiler/Linter * +******************************************** + +[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. + +[INFO :CM0024] Executing with 4 threads. + +[INFO :CM0020] Separate compilation-unit mode is on. + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv". + +[INFO :PP0122] Preprocessing source file "/home/alain/surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac_ana.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/genbus_if.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/adrdec.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac_dig.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/chip.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/cpu.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pads_if.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ports_h.sv". + +[INFO :PP0122] Preprocessing source file "tsub/t_flag_f_tsub_inc.v". + +[INFO :PP0122] Preprocessing source file "t_a_first_cc.v". + +[INFO :PP0122] Preprocessing source file "t_alw_combdly.v". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pad_gnd.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pad_gpio.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pad_vdd.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pads.sv". + +[INFO :PP0122] Preprocessing source file "t_alw_nosplit.v". + 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source file "t_struct_notfound_bad.v". + +[INFO :PP0122] Preprocessing source file "t_struct_packed_sysfunct.v". + +[INFO :PP0122] Preprocessing source file "t_struct_param.v". + +[INFO :PP0122] Preprocessing source file "t_struct_pat_width.v". + +[INFO :PP0122] Preprocessing source file "t_struct_port.v". + +[INFO :PP0122] Preprocessing source file "t_struct_unaligned.v". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux.v". + +[INFO :PP0122] Preprocessing source file "t_sys_plusargs.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_digit.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_notfound.v". + +[INFO :PP0122] Preprocessing source file "t_sys_system.v". + +[INFO :PP0122] Preprocessing source file "t_sys_time.v". + +[INFO :PP0122] Preprocessing source file "t_table_fsm.v". + +[INFO :PP0122] Preprocessing source file "t_trace_packed_struct.v". + +[INFO :PP0122] Preprocessing source file "t_trace_scstruct.v". + +[INFO :PP0122] Preprocessing source file "t_trace_timescale.v". + +[INFO :PP0122] Preprocessing source file "t_tri_array.v". + +[INFO :PP0122] Preprocessing source file "t_tri_gate.v". + +[INFO :PP0122] Preprocessing source file "t_tri_ifbegin.v". + +[INFO :PP0122] Preprocessing source file "t_tri_public.v". + +[INFO :PP0122] Preprocessing source file "t_tri_select.v". + +[INFO :PP0122] Preprocessing source file "t_typedef.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_array.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_circ_bad.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_param.v". + +[INFO :PP0122] Preprocessing source file "t_udp_noname.v". + +[INFO :PP0122] Preprocessing source file "t_uniqueif.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_converge_initial.v". + +[INFO :PP0122] Preprocessing source file "t_unoptflat_simple_3.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_forfor.v". + +[INFO :PP0122] Preprocessing source file "t_var_assign_landr.v". + +[INFO :PP0122] Preprocessing source file "t_var_const_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup3.v". + +[INFO :PP0122] Preprocessing source file "t_var_in_assign.v". + +[INFO :PP0122] Preprocessing source file "t_var_life.v". + +[INFO :PP0122] Preprocessing source file "t_var_overwidth_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_overzero.v". + +[INFO :PP0122] Preprocessing source file "t_var_types_bad.v". + +[INFO :PP0122] Preprocessing source file "t_verilated_debug.v". + +[INFO :PP0122] Preprocessing source file "t_vlt_warn.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_sc.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_unimpl.v". + +[INFO :PP0122] Preprocessing source file "t_wire_types.v". + +[INFO :PP0122] Preprocessing source file "t_interface_top_bad.v". + +[INFO :PP0122] Preprocessing source file "t_interface_typo_bad.v". + +[INFO :PP0122] Preprocessing source file "t_langext_1.v". + +[INFO :PP0122] Preprocessing source file "t_lint_always_comb_iface.v". + +[INFO :PP0122] Preprocessing source file "t_lint_implicit_def_bad.v". + +[INFO :PP0122] Preprocessing source file "t_lint_importstar_bad.v". + +[INFO :PP0122] Preprocessing source file "t_lint_incabspath.v". + +[INFO :PP0122] Preprocessing source file "t_lint_inherit.v". + +[INFO :PP0122] Preprocessing source file "t_lint_only.v". + +[INFO :PP0122] Preprocessing source file "t_lint_pkg_colon_bad.v". + +[INFO :PP0122] Preprocessing source file "t_lint_restore_bad.v". + +[INFO :PP0122] Preprocessing source file "t_lint_unsized_bad.v". + +[INFO :PP0122] Preprocessing source file "t_lint_unsup_deassign.v". + +[INFO :PP0122] Preprocessing source file "t_lint_unused_bad.v". + +[INFO :PP0122] Preprocessing source file "t_lint_unused_iface_bad.v". + +[INFO :PP0122] Preprocessing source file "t_lint_width_genfor.v". + +[INFO :PP0122] Preprocessing source file "t_math_clog2.v". + +[INFO :PP0122] Preprocessing source file "t_math_concat0.v". + +[INFO :PP0122] Preprocessing source file "t_math_cond_huge.v". + +[INFO :PP0122] Preprocessing source file "t_math_shift_sel.v". + +[INFO :PP0122] Preprocessing source file "t_math_signed2.v". + +[INFO :PP0122] Preprocessing source file "t_math_signed4.v". + +[INFO :PP0122] Preprocessing source file "t_math_svl.v". + +[INFO :PP0122] Preprocessing source file "t_math_vliw.v". + +[INFO :PP0122] Preprocessing source file "t_mem_banks.v". + +[INFO :PP0122] Preprocessing source file "t_mem_first.v". + +[INFO :PP0122] Preprocessing source file "t_mem_iforder.v". + +[INFO :PP0122] Preprocessing source file "t_mem_multi_io3.v". + +[INFO :PP0122] Preprocessing source file "t_mem_packed_assign.v". + +[INFO :PP0122] Preprocessing source file "t_mem_shift.v". + +[INFO :PP0122] Preprocessing source file "t_mem_slice_conc_bad.v". + +[INFO :PP0122] Preprocessing source file "t_mod_dup_bad.v". + +[INFO :PP0122] Preprocessing source file "t_mod_interface_array.v". + +[INFO :PP0122] Preprocessing source file "t_mod_longname.v". + +[INFO :PP0122] Preprocessing source file "t_order.v". + +[INFO :PP0122] Preprocessing source file "t_order_doubleloop.v". + +[INFO :PP0122] Preprocessing source file "t_order_quad.v". + +[INFO :PP0122] Preprocessing source file "t_package_abs.v". + +[INFO :PP0122] Preprocessing source file "t_package_dimport.v". + +[INFO :PP0122] Preprocessing source file "t_package_twodeep.v". + +[INFO :PP0122] Preprocessing source file "t_param.v". + +[INFO :PP0122] Preprocessing source file "t_param_bit_sel.v". + +[INFO :PP0122] Preprocessing source file "t_param_circ_bad.v". + +[INFO :PP0122] Preprocessing source file "t_param_const_part.v". + +[INFO :PP0122] Preprocessing source file "t_param_first.v". + +[INFO :PP0122] Preprocessing source file "t_param_no_parentheses.v". + +[INFO :PP0122] Preprocessing source file "t_param_scope_bad.v". + +[INFO :PP0122] Preprocessing source file "t_param_sel.v". + +[INFO :PP0122] Preprocessing source file "t_param_value.v". + +[INFO :PP0122] Preprocessing source file "t_pp_display.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_inc_bad.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_inc_notfound_bad.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_kwd.v". + +[INFO :PP0122] Preprocessing source file "t_reloop_cam.v". + +[INFO :PP0122] Preprocessing source file "t_select_index.v". + +[INFO :PP0122] Preprocessing source file "t_select_index2.v". + +[INFO :PP0122] Preprocessing source file "t_select_lhs_oob.v". + +[INFO :PP0122] Preprocessing source file "t_select_little_pack.v". + +[INFO :PP0122] Preprocessing source file "t_select_negative.v". + +[INFO :PP0122] Preprocessing source file "t_select_runtime_range.v". + +[INFO :PP0122] Preprocessing source file "t_slice_cond.v". + +[INFO :PP0122] Preprocessing source file "t_static_elab.v". + +[INFO :PP0122] Preprocessing source file "t_stream2.v". + +[INFO :PP0122] Preprocessing source file "t_string_type_methods.v". + +[INFO :PP0122] Preprocessing source file "t_struct_packed_value_list.v". + +[INFO :PP0122] Preprocessing source file "t_struct_unpacked.v". + +[INFO :PP0122] Preprocessing source file "t_struct_unpacked_bad.v". + +[INFO :PP0122] Preprocessing source file "t_sv_conditional.v". + +[INFO :PP0122] Preprocessing source file "t_trace_fst.v". + +[INFO :PP0122] Preprocessing source file "t_tri_array_bufif.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inout2.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull2_bad.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull_bad.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pullvec_bad.v". + +[INFO :PP0122] Preprocessing source file "t_tri_select_unsized.v". + +[INFO :PP0122] Preprocessing source file "t_type_param.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_port.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_array.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_converge.v". + +[INFO :PP0122] Preprocessing source file "t_unoptflat_simple.v". + +[INFO :PP0122] Preprocessing source file "t_unpacked_array_order.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_genf.v". + +[INFO :PP0122] Preprocessing source file "t_vams_wreal.v". + +[INFO :PP0122] Preprocessing source file "t_var_dotted.v". + +[INFO :PP0122] Preprocessing source file "t_var_port2_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_port_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref.v". + +[INFO :PP0122] Preprocessing source file "t_var_set_link.v". + +[INFO :PP0122] Preprocessing source file "t_var_types.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_noline.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_persist.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_persist_inc.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_undefineall.v". + +[INFO :PP0122] Preprocessing source file "t_repeat.v". + +[INFO :PP0122] Preprocessing source file "t_runflag.v". + +[INFO :PP0122] Preprocessing source file "t_runflag_seed.v". + +[INFO :PP0122] Preprocessing source file "t_scope_map.v". + +[INFO :PP0122] Preprocessing source file "t_select_bad_msb.v". + +[INFO :PP0122] Preprocessing source file "t_select_bad_range.v". + +[INFO :PP0122] Preprocessing source file "t_select_bad_range2.v". + +[INFO :PP0122] Preprocessing source file "t_select_bound2.v". + +[INFO :PP0122] Preprocessing source file "t_select_little.v". + +[INFO :PP0122] Preprocessing source file "t_select_loop.v". + +[INFO :PP0122] Preprocessing source file "t_select_plus.v". + +[INFO :PP0122] Preprocessing source file "t_slice_struct_array_modport.v". + +[INFO :PP0122] Preprocessing source file "t_stop_bad.v". + +[INFO :PP0122] Preprocessing source file "t_stream.v". + +[INFO :PP0122] Preprocessing source file "t_struct_portsel.v". + +[INFO :PP0122] Preprocessing source file "t_sys_file_basic.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem.v". + +[INFO :PP0122] Preprocessing source file "t_trace_decoration.v". + +[INFO :PP0122] Preprocessing source file "t_trace_ena.v". + +[INFO :PP0122] Preprocessing source file "t_trace_param.v". + +[INFO :PP0122] Preprocessing source file "t_trace_public.v". + +[INFO :PP0122] Preprocessing source file "t_tri_array_pull.v". + +[INFO :PP0122] Preprocessing source file "t_tri_gen.v". + +[INFO :PP0122] Preprocessing source file "t_tri_graph.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inout.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inz.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull01.v". + +[INFO :PP0122] Preprocessing source file "t_tri_various.v". + +[INFO :PP0122] Preprocessing source file "t_udp.v". + +[INFO :PP0122] Preprocessing source file "t_unoptflat_simple_2.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_complexcond.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_signed.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup2.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup2_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_escape.v". + +[INFO :PP0122] Preprocessing source file "t_var_local.v". + +[INFO :PP0122] Preprocessing source file "t_var_notfound_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_overcmp.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref_bad2.v". + +[INFO :PP0122] Preprocessing source file "t_var_rsvd_port.v". + +[INFO :PP0122] Preprocessing source file "t_var_static.v". + +[INFO :PP0122] Preprocessing source file "t_var_xref_gen.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_get.v". + +[INFO :PP0122] Preprocessing source file "t_wire_beh_bad.v". + +[INFO :PP0122] Preprocessing source file "t_xml_first.v". + +[INFO :PP0122] Preprocessing source file "t_xml_tag.v". + +[INFO :PP0122] Preprocessing source file "t_stream3.v". + +[INFO :PP0122] Preprocessing source file "t_struct_anon.v". + +[INFO :PP0122] Preprocessing source file "t_struct_init.v". + +[INFO :PP0122] Preprocessing source file "t_struct_packed_write_read.v". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu.v". + +[INFO :PP0122] Preprocessing source file "t_sys_file_scan.v". + +[INFO :PP0122] Preprocessing source file "t_sys_fread.v". + +[INFO :PP0122] Preprocessing source file "t_sys_plusargs_bad.v". + +[INFO :PP0122] Preprocessing source file "t_sys_rand.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_addr.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_end.v". + +[INFO :PP0122] Preprocessing source file "t_sys_sformat.v". + +[INFO :PP0122] Preprocessing source file "t_threads_counter.v". + +[INFO :PP0122] Preprocessing source file "t_trace_array.v". + +[INFO :PP0122] Preprocessing source file "t_trace_cat.v". + +[INFO :PP0122] Preprocessing source file "t_trace_complex.v". + +[INFO :PP0122] Preprocessing source file "t_trace_primitive.v". + +[INFO :PP0122] Preprocessing source file "t_trace_string.v". + +[INFO :PP0122] Preprocessing source file "t_tri_dangle.v". + +[INFO :PP0122] Preprocessing source file "t_tri_eqcase.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pullup.v". + +[INFO :PP0122] Preprocessing source file "t_tri_unconn.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_signed.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_bound.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_combo.v". + +[INFO :PP0122] Preprocessing source file "t_vams_basic.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_hide.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_hide2.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_sameas.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_sv.v". + +[INFO :PP0122] Preprocessing source file "t_var_const.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_in_assign_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_init.v". + +[INFO :PP0122] Preprocessing source file "t_var_nonamebegin.v". + +[INFO :PP0122] Preprocessing source file "t_var_outoforder.v". + +[INFO :PP0122] Preprocessing source file "t_var_pinsizes.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref_bad1.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref_bad3.v". + +[INFO :PP0122] Preprocessing source file "t_var_rsvd.v". + +[INFO :PP0122] Preprocessing source file "t_var_suggest_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_tieout.v". + +[INFO :PP0122] Preprocessing source file "t_var_vec_sel.v". + +[INFO :PP0122] Preprocessing source file "t_verilated_all.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_memory.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_var.v". + +[ERROR:PP0102] t_sv_cpu_code/ports.sv:44 Unknown macro "PACKED". + +[ERROR:PP0102] t_sv_cpu_code/ports.sv:49 Unknown macro "PACKED". + +[INFO :PP0123] Preprocessing include file "rom.sv". + +[ERROR:PP0101] t_sv_cpu_code/program_h.sv:31 Cannot open include file "rom.sv". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:18 Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:19 Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:20 Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:21 Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:23 Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:24 Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:25 Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:26 Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:28 Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:29 Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:30 Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:31 Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:33 Unknown macro "JMP". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:35 Unknown macro "EOP". + +[INFO :PP0123] Preprocessing include file "verilated.v". + +[ERROR:PP0101] t_case_write1.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_case_write1.v:37 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_case_write1.v:38 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_case_write1_tasks.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0101] t_case_write2.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_case_write2.v:37 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_case_write2.v:38 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_case_write2_tasks.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0118] t_display.v:13 Unknown escaped sequence '\2'. + +[ERROR:PP0118] t_display_esc_bad.v:8 Unknown escaped sequence '\y'. + +[ERROR:PP0118] t_display_esc_bad.v:8 Unknown escaped sequence '\z'. + +[INFO :PP0123] Preprocessing include file "t_dpi_accessors_macros_inc.vh". + +[INFO :PP0123] Preprocessing include file "t_dpi_accessors_inc.vh". + +[ERROR:PP0102] t_dpi_display.v:11 Unknown macro "error". + +[ERROR:PP0102] t_dpi_sys.v:15 Unknown macro "error". + +[ERROR:PP0102] t_dpi_threads.v:19 Unknown macro "error". + +[ERROR:PP0102] t_dpi_var.v:66 Unknown macro "systemc_imp_header". + +[ERROR:PP0102] t_dpi_var.v:69 Unknown macro "verilog". + +[ERROR:PP0102] t_extend_class.v:48 Unknown macro "systemc_header". + +[ERROR:PP0102] t_extend_class.v:50 Unknown macro "systemc_interface". + +[ERROR:PP0102] t_extend_class.v:52 Unknown macro "systemc_ctor". + +[ERROR:PP0102] t_extend_class.v:54 Unknown macro "systemc_dtor". + +[ERROR:PP0102] t_extend_class.v:56 Unknown macro "verilog". + +[INFO :PP0123] Preprocessing include file "t_flag_f_tsub_inc.v". + +[ERROR:PP0101] t_flag_f.v:3 Cannot open include file "t_flag_f_tsub_inc.v". + +[NOTE :PP0105] t_func_flip.v:7 Multiply defined macro "INT_RANGE", + t_func_flip.v:6 previous definition. + +[ERROR:PP0102] t_gen_missing.v:13 Unknown macro "error". + +[INFO :PP0123] Preprocessing include file "t_initial_inc.vh". + +[ERROR:PP0102] t_interface_down_gen.v:75 Unknown macro "error". + +[ERROR:PP0120] t_lint_implicit_def_bad.v:21 Illegal directive in design element "`resetall". + +[INFO :PP0123] Preprocessing include file "t_lint_in_inc_bad_1.vh". + +[INFO :PP0123] Preprocessing include file "t_lint_in_inc_bad_2.vh". + +[INFO :PP0123] Preprocessing include file "/dev/null". + +[ERROR:PP0102] t_lint_unused.v:31 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_lint_unused.v:34 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0107] t_math_clog2.v:26 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:27 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:28 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:29 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:46 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:47 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:48 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:49 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:50 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:51 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:52 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:53 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:54 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:55 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:56 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:57 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:58 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[WARNI:PP0113] t_math_signed5.v:11 Unused macro argument "vs". + +[INFO :PP0123] Preprocessing include file "t_pipe_filter_inc.vh". + +[ERROR:PP0115] t_pp_circdef_bad.v:9 Recursive macro definition for "SEL_NUM_BITS", + t_pp_circdef_bad.v:9 macro used in macro "SEL_NUM_BITS". + +[ERROR:PP0102] t_pp_circdef_bad.v:9 Unknown macro "SEL_NUM_BITS". + +[WARNI:PP0113] t_pp_display.v:20 Unused macro argument "left". + +[ERROR:PP0109] t_pp_display.v:34 Macro instantiation omits argument 1 (x) for "thru", + t_pp_display.v:17 No default value for argument 1 (x) in macro definition. + +[NOTE :PP0105] t_pp_dupdef.v:9 Multiply defined macro "DUP", + t_pp_dupdef.v:8 previous definition. + +[NOTE :PP0105] t_pp_dupdef.v:12 Multiply defined macro "DUPP", + t_pp_dupdef.v:11 previous definition. + +[INFO :PP0123] Preprocessing include file "t_pp_lib_inc.vh". + +[ERROR:PP0102] t_pp_lib_library.v:7 Unknown macro "WIDTH". + +[ERROR:PP0102] t_pp_misdef_bad.v:10 Unknown macro "NDEFINED". + +[ERROR:PP0102] t_pp_misdef_bad.v:13 Unknown macro "imescale". + +[ERROR:PP0102] t_pp_pragmas.v:7 Unknown macro "verilog". + +[ERROR:PP0102] t_pp_pragmas.v:40 Unknown macro "remove_gatenames". + +[ERROR:PP0102] t_pp_pragmas.v:42 Unknown macro "remove_netnames". + +[ERROR:PP0106] t_preproc.v:245 Syntax error: no viable alternative at input '`define\n', +Not a \`define + ^-- t_preproc.v:245 col:14. + +[ERROR:PP0106] t_preproc.v:284 Syntax error: no viable alternative at input '`define /* multi\t\\n\t line1*/', +`define /* multi \ + ^-- t_preproc.v:284 col:8. + +[ERROR:PP0106] t_preproc.v:475 Syntax error: no viable alternative at input '`define ESC(name) \', +`define ESC(name) \`CAT(name,suffix) + ^-- t_preproc.v:475 col:18. + +[INFO :PP0123] Preprocessing include file "t_preproc_inc2.vh". + +[INFO :PP0123] Preprocessing include file "<t_preproc_inc3.vh>". + +[ERROR:PP0101] t_preproc_inc2.vh:6 Cannot open include file "<t_preproc_inc3.vh>". + +[ERROR:PP0112] t_preproc.v:74 Illegal space in between macro name "noparam" and open parenthesis. + +[NOTE :PP0105] t_preproc.v:99 Multiply defined macro "msg", + t_preproc.v:77 previous definition. + +[ERROR:PP0109] t_preproc.v:110 Macro instantiation omits argument 1 (x) for "thru", + t_preproc.v:97 No default value for argument 1 (x) in macro definition. + +[ERROR:PP0116] t_preproc.v:158 Illegal unterminated string. + +[INFO :PP0123] Preprocessing include file "t_preproc_inc4.vh". + +[ERROR:PP0112] t_preproc.v:218 Illegal space in between macro name "ARGPAR" and open parenthesis. + +[WARNI:PP0113] t_preproc.v:251 Unused macro argument "l". + +[ERROR:PP0102] t_preproc.v:263 Unknown macro "error". + +[ERROR:PP0102] t_preproc.v:266 Unknown macro "error". + +[ERROR:PP0102] t_preproc.v:293 Unknown macro "bug202". + +[ERROR:PP0107] t_preproc.v:307 Too many arguments (1) for macro "CMT1", + t_preproc.v:297 macro definition takes 0. + +[ERROR:PP0107] t_preproc.v:308 Too many arguments (1) for macro "CMT2", + t_preproc.v:298 macro definition takes 0. + +[ERROR:PP0107] t_preproc.v:309 Too many arguments (1) for macro "CMT3", + t_preproc.v:299 macro definition takes 0. + +[ERROR:PP0107] t_preproc.v:310 Too many arguments (1) for macro "CMT4", + t_preproc.v:301 macro definition takes 0. + +[ERROR:PP0107] t_preproc.v:311 Too many arguments (1) for macro "CMT5", + t_preproc.v:303 macro definition takes 0. + +[WARNI:PP0113] t_preproc.v:318 Unused macro argument "log". + +[WARNI:PP0113] t_preproc.v:372 Unused macro argument "d". + +[ERROR:PP0102] t_preproc.v:379 Unknown macro "REPEAT_". + +[WARNI:PP0103] t_preproc.v:386 Undefining an unknown macro "T_PREPROC_INC4". + +[WARNI:PP0103] t_preproc.v:396 Undefining an unknown macro "TEMP". + +[ERROR:PP0102] t_preproc.v:400 Unknown macro "error". + +[ERROR:PP0116] t_preproc.v:406 Illegal unterminated string. + +[WARNI:PP0114] t_preproc.v:418 Undefined macro argument "b". + +[ERROR:PP0102] t_preproc.v:442 Unknown macro "QA". + +[WARNI:PP0113] t_preproc.v:462 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:469 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:469 Unused macro argument "name2". + +[ERROR:PP0102] t_preproc.v:478 Unknown macro "ESC". + +[WARNI:PP0103] t_preproc.v:479 Undefining an unknown macro "ESC". + +[WARNI:PP0113] t_preproc.v:482 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:488 Unused macro argument "name". + +[ERROR:PP0102] t_preproc.v:491 Unknown macro "zzz". + +[WARNI:PP0113] t_preproc.v:495 Unused macro argument "name". + +[WARNI:PP0103] t_preproc.v:504 Undefining an unknown macro "UNKNOWN". + +[ERROR:PP0102] t_preproc.v:505 Unknown macro "UNKNOWN". + +[WARNI:PP0113] t_preproc.v:514 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:519 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:543 Unused macro argument "foo". + +[WARNI:PP0114] t_preproc.v:547 Undefined macro argument "XXE_". + +[WARNI:PP0114] t_preproc.v:554 Undefined macro argument "XYE_". + +[WARNI:PP0114] t_preproc.v:561 Undefined macro argument "XXS_". + +[WARNI:PP0114] t_preproc.v:568 Undefined macro argument "XYS_". + +[ERROR:PP0102] t_preproc.v:617 Unknown macro "dbg_hdl". + +[WARNI:PP0113] t_preproc.v:620 Unused macro argument "LVL". + +[ERROR:PP0102] t_preproc.v:637 Unknown macro "SV_COV_START". + +[ERROR:PP0102] t_preproc.v:638 Unknown macro "SV_COV_STOP". + +[ERROR:PP0102] t_preproc.v:639 Unknown macro "SV_COV_RESET". + +[ERROR:PP0102] t_preproc.v:640 Unknown macro "SV_COV_CHECK". + +[ERROR:PP0102] t_preproc.v:641 Unknown macro "SV_COV_MODULE". + +[ERROR:PP0102] t_preproc.v:642 Unknown macro "SV_COV_HIER". + +[ERROR:PP0102] t_preproc.v:643 Unknown macro "SV_COV_ASSERTION". + +[ERROR:PP0102] t_preproc.v:644 Unknown macro "SV_COV_FSM_STATE". + +[ERROR:PP0102] t_preproc.v:645 Unknown macro "SV_COV_STATEMENT". + +[ERROR:PP0102] t_preproc.v:646 Unknown macro "SV_COV_TOGGLE". + +[ERROR:PP0102] t_preproc.v:647 Unknown macro "SV_COV_OVERFLOW". + +[ERROR:PP0102] t_preproc.v:648 Unknown macro "SV_COV_ERROR". + +[ERROR:PP0102] t_preproc.v:649 Unknown macro "SV_COV_NOCOV". + +[ERROR:PP0102] t_preproc.v:650 Unknown macro "SV_COV_OK". + +[ERROR:PP0102] t_preproc.v:651 Unknown macro "SV_COV_PARTIAL". + +[ERROR:PP0112] t_preproc_def09.v:60 Illegal space in between macro name "MACROPAREN" and open parenthesis. + +[INFO :PP0123] Preprocessing include file "t_preproc_inc_inc_bad.vh". + +[INFO :PP0123] Preprocessing include file "this_file_is_not_found.vh". + +[ERROR:PP0101] t_preproc_inc_notfound_bad.v:6 Cannot open include file "this_file_is_not_found.vh". + +[INFO :PP0123] Preprocessing include file "t_preproc_persist_inc.v". + +[ERROR:PP0102] t_preproc_undefineall.v:9 Unknown macro "error". + +[ERROR:PP0102] t_preproc_undefineall.v:14 Unknown macro "error". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv". + +[ERROR:PP0101] t_sys_file_basic.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_sys_file_basic.v:46 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_sys_file_scan.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_sys_file_scan.v:16 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_sys_fread.v:42 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_sys_sformat.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_tri_gate.v:36 Unknown macro "error". + +[WARNI:PP0113] t_var_types.v:182 Unused macro argument "zeroinit". + +[INFO :PA0201] Parsing source file "/home/alain/surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ac.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/genbus_if.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/adrdec.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ac_dig.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/cpu.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ac_ana.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ports_h.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/rom.sv". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/chip.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pad_vdd.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pads_h.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ports.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pad_gnd.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pad_gpio.sv". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pads.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pinout_h.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/program_h.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/timescale.sv". + +[INFO :PA0201] Parsing source file "tsub/t_flag_f_tsub_inc.v". + +[INFO :PA0201] Parsing source file "t_a_first_cc.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pads_if.sv". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "tsub/t_flag_f_tsub.v". + +[INFO :PA0201] Parsing source file "t_EXAMPLE.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_alw_nosplit.v". + +[INFO :PA0201] Parsing source file "t_array_backw_index_bad.v". + +[INFO :PA0201] Parsing source file "t_array_compare.v". + +[INFO :PA0201] Parsing source file "t_array_mda.v". + +[INFO :PA0201] Parsing source file "t_array_query.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_array_rev.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_arraysel_wide.v". + +[INFO :PA0201] Parsing source file "t_assert_basic.v". + +[INFO :PA0201] Parsing source file "t_assert_comp_bad.v". + +[INFO :PA0201] Parsing source file "t_alw_combdly.v". + +[INFO :PA0201] Parsing source file "t_assert_dup_bad.v". + +[INFO :PA0201] Parsing source file "t_assert_elab.v". + +[INFO :PA0201] Parsing source file "t_alw_reorder.v". + +[INFO :PA0201] Parsing source file "t_alw_split_rst.v". + +[INFO :PA0201] Parsing source file "t_assert_property.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_alw_dly.v". + +[INFO :PA0201] Parsing source file "t_alw_split.v". + +[INFO :PA0201] Parsing source file "t_alw_splitord.v". + +[INFO :PA0201] Parsing source file "t_assert_question.v". + +[INFO :PA0201] Parsing source file "t_array_list_bad.v". + +[INFO :PA0201] Parsing source file "t_array_packed_sysfunct.v". + +[INFO :PA0201] Parsing source file "t_assign_inline.v". + +[INFO :PA0201] Parsing source file "t_bench_mux4k.v". + +[INFO :PA0201] Parsing source file "t_array_pattern_bad.v". + +[INFO :PA0201] Parsing source file "t_array_pattern_unpacked.v". + +[INFO :PA0201] Parsing source file "t_array_type_methods.v". + +[INFO :PA0201] Parsing source file "t_assert_casez.v". + +[INFO :PA0201] Parsing source file "t_assert_comp.v". + +[INFO :PA0201] Parsing source file "t_assert_cover.v". + +[INFO :PA0201] Parsing source file "t_bitsel_struct2.v". + +[INFO :PA0201] Parsing source file "t_case_default_bad.v". + +[INFO :PA0201] Parsing source file "t_case_dupitems.v". + +[INFO :PA0201] Parsing source file "t_case_huge_sub.v". + +[INFO :PA0201] Parsing source file "t_case_orig.v". + +[INFO :PA0201] Parsing source file "t_case_write1_tasks.v". + +[INFO :PA0201] Parsing source file "t_attr_parenstar.v". + +[INFO :PA0201] Parsing source file "t_bind.v". + +[INFO :PA0201] Parsing source file "t_bitsel_const_bad.v". + +[INFO :PA0201] Parsing source file "t_bitsel_enum.v". + +[INFO :PA0201] Parsing source file "t_bitsel_slice.v". + +[INFO :PA0201] Parsing source file "t_bitsel_wire_array_bad.v". + +[INFO :PA0201] Parsing source file "t_blocking.v". + +[INFO :PA0201] Parsing source file "t_case_deep.v". + +[INFO :PA0201] Parsing source file "t_case_onehot.v". + +[INFO :PA0201] Parsing source file "t_case_genx_bad.v". + +[INFO :PA0201] Parsing source file "t_case_reducer.v". + +[INFO :PA0201] Parsing source file "t_case_group.v". + +[INFO :PA0201] Parsing source file "t_case_huge_sub2.v". + +[INFO :PA0201] Parsing source file "t_clk_concat4.v". + +[INFO :PA0201] Parsing source file "t_case_huge_sub4.v". + +[INFO :PA0201] Parsing source file "t_case_inside.v". + +[INFO :PA0201] Parsing source file "t_case_itemwidth.v". + +[INFO :PA0201] Parsing source file "t_case_nest.v". + +[INFO :PA0201] Parsing source file "t_case_wild.v". + +[INFO :PA0201] Parsing source file "t_clk_concat6.v". + +[INFO :PA0201] Parsing source file "t_clk_condflop_nord.v". + +[INFO :PA0201] Parsing source file "t_clk_dsp.v". + +[INFO :PA0201] Parsing source file "t_clk_gater.v". + +[INFO :PA0201] Parsing source file "t_clk_latch.v". + +[INFO :PA0201] Parsing source file "t_case_write2_tasks.v". + +[INFO :PA0201] Parsing source file "t_clk_powerdn.v". + +[INFO :PA0201] Parsing source file "t_clk_scope_bad.v". + +[INFO :PA0201] Parsing source file "t_clk_vecgen1.v". + +[INFO :PA0201] Parsing source file "t_concat_large.v". + +[INFO :PA0201] Parsing source file "t_const.v". + +[INFO :PA0201] Parsing source file "t_const_bad.v". + +[INFO :PA0201] Parsing source file "t_const_dec_mixed_bad.v". + +[INFO :PA0201] Parsing source file "t_const_overflow_bad.v". + +[INFO :PA0201] Parsing source file "t_cover_sva_notflat.v". + +[INFO :PA0201] Parsing source file "t_cover_toggle.v". + +[INFO :PA0201] Parsing source file "t_dedupe_seq_logic.v". + +[INFO :PA0201] Parsing source file "t_detectarray_3.v". + +[INFO :PA0201] Parsing source file "t_display_bad.v". + +[INFO :PA0201] Parsing source file "t_display_esc_bad.v". + +[INFO :PA0201] Parsing source file "t_display_l.v". + +[INFO :PA0201] Parsing source file "t_display_mcd.v". + +[INFO :PA0201] Parsing source file "t_display_merge.v". + +[INFO :PA0201] Parsing source file "t_display_real.v". + +[INFO :PA0201] Parsing source file "t_display_realtime.v". + +[INFO :PA0201] Parsing source file "t_display_signed.v". + +[INFO :PA0201] Parsing source file "t_display_string.v". + +[INFO :PA0201] Parsing source file "t_display_wide.v". + +[INFO :PA0201] Parsing source file "t_dpi_context.v". + +[INFO :PA0201] Parsing source file "t_dpi_display.v". + +[INFO :PA0201] Parsing source file "t_dpi_dup_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_exp_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_export.v". + +[INFO :PA0201] Parsing source file "t_dpi_import.v". + +[INFO :PA0201] Parsing source file "t_dpi_shortcircuit.v". + +[INFO :PA0201] Parsing source file "t_enum_large_methods.v". + +[INFO :PA0201] Parsing source file "t_enum_overlap_bad.v". + +[INFO :PA0201] Parsing source file "t_enum_size.v". + +[INFO :PA0201] Parsing source file "t_enum_type_pins.v". + +[INFO :PA0201] Parsing source file "t_extend_class.v". + +[INFO :PA0201] Parsing source file "t_flag_csplit.v". + +[INFO :PA0201] Parsing source file "t_enumeration.v". + +[INFO :PA0201] Parsing source file "t_flag_f__3.v". + +[INFO :PA0201] Parsing source file "t_flag_fi.v". + +[INFO :PA0201] Parsing source file "t_flag_ldflags.v". + +[INFO :PA0201] Parsing source file "t_flag_nomod_bad.v". + +[INFO :PA0201] Parsing source file "t_flag_skipidentical.v". + +[INFO :PA0201] Parsing source file "t_flag_stats.v". + +[INFO :PA0201] Parsing source file "t_flag_topmodule.v". + +[INFO :PA0201] Parsing source file "t_flag_werror.v". + +[INFO :PA0201] Parsing source file "t_flag_woff.v". + +[INFO :PA0201] Parsing source file "t_flag_xinitial_unique.v". + +[INFO :PA0201] Parsing source file "t_for_comma_bad.v". + +[INFO :PA0201] Parsing source file "t_for_count.v". + +[INFO :PA0201] Parsing source file "t_foreach.v". + +[INFO :PA0201] Parsing source file "t_func_const_bad.v". + +[INFO :PA0201] Parsing source file "t_func_crc.v". + +[INFO :PA0201] Parsing source file "t_func_plog.v". + +[INFO :PA0201] Parsing source file "t_for_init_bug.v". + +[INFO :PA0201] Parsing source file "t_func.v". + +[INFO :PA0201] Parsing source file "t_func_const2_bad.v". + +[INFO :PA0201] Parsing source file "t_func_const_packed_struct_bad.v". + +[INFO :PA0201] Parsing source file "t_func_regfirst.v". + +[INFO :PA0201] Parsing source file "t_func_const_struct_bad.v". + +[INFO :PA0201] Parsing source file "t_func_task_bad.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_func_tie_bad.v". + +[INFO :PA0201] Parsing source file "t_func_types.v". + +[INFO :PA0201] Parsing source file "t_func_wide.v". + +[INFO :PA0201] Parsing source file "t_func_dotted.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_gate_elim.v". + +[INFO :PA0201] Parsing source file "t_gen_assign.v". + +[INFO :PA0201] Parsing source file "t_array_interface.v". + +[INFO :PA0201] Parsing source file "t_gen_cond_const.v". + +[INFO :PA0201] Parsing source file "t_func_mlog2.v". + +[INFO :PA0201] Parsing source file "t_array_pattern_2d.v". + +[INFO :PA0201] Parsing source file "t_gen_for.v". + +[INFO :PA0201] Parsing source file "t_func_noinl.v". + +[INFO :PA0201] Parsing source file "t_array_pattern_packed.v". + +[INFO :PA0201] Parsing source file "t_func_paramed.v". + +[INFO :PA0201] Parsing source file "t_func_rand.v". + +[INFO :PA0201] Parsing source file "t_func_real_abs.v". + +[INFO :PA0201] Parsing source file "t_func_return.v". + +[INFO :PA0201] Parsing source file "t_func_twocall.v". + +[INFO :PA0201] Parsing source file "t_func_v.v". + +[INFO :PA0201] Parsing source file "t_func_while.v". + +[INFO :PA0201] Parsing source file "t_gate_basic.v". + +[INFO :PA0201] Parsing source file "t_gen_intdot.v". + +[INFO :PA0201] Parsing source file "t_gate_implicit.v". + +[INFO :PA0201] Parsing source file "t_gen_cond_bitrange.v". + +[INFO :PA0201] Parsing source file "t_gen_lsb.v". + +[INFO :PA0201] Parsing source file "t_gen_upscope.v". + +[INFO :PA0201] Parsing source file "t_embed1.v". + +[INFO :PA0201] Parsing source file "t_emit_constw.v". + +[INFO :PA0201] Parsing source file "t_iff.v". + +[INFO :PA0201] Parsing source file "t_initial_dlyass.v". + +[INFO :PA0201] Parsing source file "t_inside_wild.v". + +[INFO :PA0201] Parsing source file "t_inst_array.v". + +[INFO :PA0201] Parsing source file "t_gen_for1.v". + +[INFO :PA0201] Parsing source file "t_gen_forif.v". + +[INFO :PA0201] Parsing source file "t_inst_ccall.v". + +[INFO :PA0201] Parsing source file "t_inst_darray.v". + +[INFO :PA0201] Parsing source file "t_flag_debugi9.v". + +[INFO :PA0201] Parsing source file "t_flag_errorlimit_bad.v". + +[INFO :PA0201] Parsing source file "t_flag_f.v". + +[INFO :PA0201] Parsing source file "t_flag_language.v". + +[INFO :PA0201] Parsing source file "t_flag_names.v". + +[INFO :PA0201] Parsing source file "t_flag_parameter.v". + +[INFO :PA0201] Parsing source file "t_for_funcbound.v". + +[INFO :PA0201] Parsing source file "t_inst_first_b.v". + +[INFO :PA0201] Parsing source file "t_inst_misarray_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_mism.v". + +[INFO :PA0201] Parsing source file "t_inst_overwide.v". + +[INFO :PA0201] Parsing source file "t_inst_prepost.v". + +[INFO :PA0201] Parsing source file "t_inst_signed.v". + +[INFO :PA0201] Parsing source file "t_inst_v2k.v". + +[INFO :PA0201] Parsing source file "t_for_local.v". + +[INFO :PA0201] Parsing source file "t_interface1.v". + +[INFO :PA0201] Parsing source file "t_interface_array.v". + +[INFO :PA0201] Parsing source file "t_func_bad.v". + +[INFO :PA0201] Parsing source file "t_func_bad2.v". + +[INFO :PA0201] Parsing source file "t_func_bad_width.v". + +[INFO :PA0201] Parsing source file "t_func_check.v". + +[INFO :PA0201] Parsing source file "t_func_const3_bad.v". + +[INFO :PA0201] Parsing source file "t_func_const_packed_array_bad.v". + +[INFO :PA0201] Parsing source file "t_func_const_packed_struct_bad2.v". + +[INFO :PA0201] Parsing source file "t_interface_array_nocolon_bad.v". + +[INFO :PA0201] Parsing source file "t_func_defaults.v". + +[INFO :PA0201] Parsing source file "t_interface_down.v". + +[INFO :PA0201] Parsing source file "t_interface_dups.v". + +[INFO :PA0201] Parsing source file "t_interface_gen8.v". + +[INFO :PA0201] Parsing source file "t_func_first.v". + +[INFO :PA0201] Parsing source file "t_func_flip.v". + +[INFO :PA0201] Parsing source file "t_func_gen.v". + +[INFO :PA0201] Parsing source file "t_interface_missing_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_modport_import.v". + +[INFO :PA0201] Parsing source file "t_gen_intdot2.v". + +[INFO :PA0201] Parsing source file "t_interface_param1.v". + +[INFO :PA0201] Parsing source file "t_interface_param_another_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_size_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_twod.v". + +[INFO :PA0201] Parsing source file "t_langext_2.v". + +[INFO :PA0201] Parsing source file "t_func_grey.v". + +[INFO :PA0201] Parsing source file "t_lint_blksync_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_bsspace_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_colonplus_bad.v". + +[INFO :PA0201] Parsing source file "t_func_named.v". + +[INFO :PA0201] Parsing source file "t_func_outp.v". + +[INFO :PA0201] Parsing source file "t_func_public.v". + +[INFO :PA0201] Parsing source file "t_gen_var_bad.v". + +[INFO :PA0201] Parsing source file "t_genfor_hier.v". + +[INFO :PA0201] Parsing source file "t_func_under2.v". + +[INFO :PA0201] Parsing source file "t_func_void_bad.v". + +[INFO :PA0201] Parsing source file "t_gate_array.v". + +[INFO :PA0201] Parsing source file "t_gate_unsup.v". + +[INFO :PA0201] Parsing source file "t_gen_alw.v". + +[INFO :PA0201] Parsing source file "t_lint_comb_use.v". + +[INFO :PA0201] Parsing source file "t_lint_implicit.v". + +[INFO :PA0201] Parsing source file "t_lint_implicit_port.v". + +[INFO :PA0201] Parsing source file "t_genvar_misuse_bad.v". + +[INFO :PA0201] Parsing source file "t_hierarchy_identifier_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_infinite.v". + +[INFO :PA0201] Parsing source file "t_lint_latch_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_once_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_pkg_colon_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_restore_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unsized_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unsup_deassign.v". + +[INFO :PA0201] Parsing source file "t_lint_unused_bad.v". + +[INFO :PA0201] Parsing source file "t_gen_defparam.v". + +[INFO :PA0201] Parsing source file "t_gen_div0.v". + +[INFO :PA0201] Parsing source file "t_initarray_nonarray.v". + +[INFO :PA0201] Parsing source file "t_lint_unused_iface_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_width_genfor.v". + +[INFO :PA0201] Parsing source file "t_initial.v". + +[INFO :PA0201] Parsing source file "t_initial_edge.v". + +[INFO :PA0201] Parsing source file "t_gen_for0.v". + +[INFO :PA0201] Parsing source file "t_math_clog2.v". + +[INFO :PA0201] Parsing source file "t_gen_for_overlap.v". + +[INFO :PA0201] Parsing source file "t_gen_if.v". + +[INFO :PA0201] Parsing source file "t_inst_array_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_array_partial.v". + +[INFO :PA0201] Parsing source file "t_math_concat0.v". + +[INFO :PA0201] Parsing source file "t_math_concat_sel_bad.v". + +[INFO :PA0201] Parsing source file "t_gen_index.v". + +[INFO :PA0201] Parsing source file "t_math_div.v". + +[INFO :PA0201] Parsing source file "t_gen_local.v". + +[INFO :PA0201] Parsing source file "t_inst_dff.v". + +[INFO :PA0201] Parsing source file "t_gen_mislevel.v". + +[INFO :PA0201] Parsing source file "t_gen_missing.v". + +[INFO :PA0201] Parsing source file "t_inst_missing.v". + +[INFO :PA0201] Parsing source file "t_inst_notunsized.v". + +[INFO :PA0201] Parsing source file "t_math_div0.v". + +[INFO :PA0201] Parsing source file "t_math_divw.v". + +[INFO :PA0201] Parsing source file "t_inst_sv.v". + +[INFO :PA0201] Parsing source file "t_inst_wideconst.v". + +[INFO :PA0201] Parsing source file "t_interface1_modport.v". + +[INFO :PA0201] Parsing source file "t_interface_array_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_array_modport.v". + +[INFO :PA0201] Parsing source file "t_interface_arraymux.v". + +[INFO :PA0201] Parsing source file "t_math_pow.v". + +[INFO :PA0201] Parsing source file "t_math_precedence.v". + +[INFO :PA0201] Parsing source file "t_gen_self_return.v". + +[INFO :PA0201] Parsing source file "t_interface_gen.v". + +[INFO :PA0201] Parsing source file "t_math_real_public.v". + +[INFO :PA0201] Parsing source file "t_math_repl.v". + +[INFO :PA0201] Parsing source file "t_interface_gen3.v". + +[INFO :PA0201] Parsing source file "t_interface_gen7.v". + +[INFO :PA0201] Parsing source file "t_interface_modport_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_modportlist.v". + +[INFO :PA0201] Parsing source file "t_interface_mp_func.v". + +[INFO :PA0201] Parsing source file "t_interface_param2.v". + +[INFO :PA0201] Parsing source file "t_interface_star.v". + +[INFO :PA0201] Parsing source file "t_interface_wrong_bad.v". + +[INFO :PA0201] Parsing source file "t_langext_3.v". + +[INFO :PA0201] Parsing source file "t_leak.v". + +[INFO :PA0201] Parsing source file "t_lint_blksync_loop.v". + +[INFO :PA0201] Parsing source file "t_lint_importstar_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_incabspath.v". + +[INFO :PA0201] Parsing source file "t_lint_inherit.v". + +[INFO :PA0201] Parsing source file "t_lint_only.v". + +[INFO :PA0201] Parsing source file "t_lint_pindup_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_syncasyncnet_bad.v". + +[INFO :PA0201] Parsing source file "t_math_arith.v". + +[INFO :PA0201] Parsing source file "t_assert_synth.v". + +[INFO :PA0201] Parsing source file "t_bind2.v". + +[INFO :PA0201] Parsing source file "t_hierarchy_identifier.v". + +[INFO :PA0201] Parsing source file "t_bitsel_struct.v". + +[INFO :PA0201] Parsing source file "t_bitsel_struct3.v". + +[INFO :PA0201] Parsing source file "t_math_const.v". + +[INFO :PA0201] Parsing source file "t_case_66bits.v". + +[INFO :PA0201] Parsing source file "t_case_auto1.v". + +[INFO :PA0201] Parsing source file "t_case_huge.v". + +[INFO :PA0201] Parsing source file "t_case_huge_sub3.v". + +[INFO :PA0201] Parsing source file "t_init_concat.v". + +[INFO :PA0201] Parsing source file "t_inside.v". + +[INFO :PA0201] Parsing source file "t_case_write1.v". + +[INFO :PA0201] Parsing source file "t_case_write2.v". + +[INFO :PA0201] Parsing source file "t_case_x.v". + +[INFO :PA0201] Parsing source file "t_math_eq.v". + +[INFO :PA0201] Parsing source file "t_inst_dtree.v". + +[INFO :PA0201] Parsing source file "t_inst_first_a.v". + +[INFO :PA0201] Parsing source file "t_inst_implicit.v". + +[INFO :PA0201] Parsing source file "t_case_x_bad.v". + +[INFO :PA0201] Parsing source file "t_case_zx_bad.v". + +[INFO :PA0201] Parsing source file "t_math_imm.v". + +[INFO :PA0201] Parsing source file "t_cast.v". + +[INFO :PA0201] Parsing source file "t_inst_missing_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_mnpipe.v". + +[INFO :PA0201] Parsing source file "t_inst_recurse2_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_recurse_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_slice.v". + +[INFO :PA0201] Parsing source file "t_math_pick.v". + +[INFO :PA0201] Parsing source file "t_interface.v". + +[INFO :PA0201] Parsing source file "t_math_pow3.v". + +[INFO :PA0201] Parsing source file "t_interface_array_nocolon.v". + +[INFO :PA0201] Parsing source file "t_interface_down_gen.v". + +[INFO :PA0201] Parsing source file "t_math_sign_extend.v". + +[INFO :PA0201] Parsing source file "t_math_signed5.v". + +[INFO :PA0201] Parsing source file "t_math_vliw.v". + +[INFO :PA0201] Parsing source file "t_interface_gen10.v". + +[INFO :PA0201] Parsing source file "t_interface_gen12.v". + +[INFO :PA0201] Parsing source file "t_interface_gen4.v". + +[INFO :PA0201] Parsing source file "t_interface_gen5.v". + +[INFO :PA0201] Parsing source file "t_mem_banks.v". + +[INFO :PA0201] Parsing source file "t_interface_mismodport_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_modport_export.v". + +[INFO :PA0201] Parsing source file "t_interface_nest.v". + +[INFO :PA0201] Parsing source file "t_math_shift_over_bad.v". + +[INFO :PA0201] Parsing source file "t_math_shift_sel.v". + +[INFO :PA0201] Parsing source file "t_math_signed2.v". + +[INFO :PA0201] Parsing source file "t_interface_parameter_access.v". + +[INFO :PA0201] Parsing source file "t_math_signed4.v". + +[INFO :PA0201] Parsing source file "t_cdc_async_bad.v". + +[INFO :PA0201] Parsing source file "t_langext_order.v". + +[INFO :PA0201] Parsing source file "t_cellarray.v". + +[INFO :PA0201] Parsing source file "t_math_tri.v". + +[INFO :PA0201] Parsing source file "t_math_vgen.v". + +[INFO :PA0201] Parsing source file "t_mem_first.v". + +[INFO :PA0201] Parsing source file "t_langext_order_sub.v". + +[INFO :PA0201] Parsing source file "t_lint_always_comb_iface.v". + +[INFO :PA0201] Parsing source file "t_lint_ifdepth_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_input_eq_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_mod_paren_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_multidriven_bad.v". + +[INFO :PA0201] Parsing source file "t_chg_first.v". + +[INFO :PA0201] Parsing source file "t_clk_concat.v". + +[INFO :PA0201] Parsing source file "t_lint_repeat_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_setout_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unused.v". + +[INFO :PA0201] Parsing source file "t_lint_width_bad.v". + +[INFO :PA0201] Parsing source file "t_clk_concat2.v". + +[INFO :PA0201] Parsing source file "t_mem_iforder.v". + +[INFO :PA0201] Parsing source file "t_mem_multidim.v". + +[INFO :PA0201] Parsing source file "t_math_cmp.v". + +[INFO :PA0201] Parsing source file "t_clk_concat3.v". + +[INFO :PA0201] Parsing source file "t_math_cond_huge.v". + +[INFO :PA0201] Parsing source file "t_math_reverse.v". + +[INFO :PA0201] Parsing source file "t_clk_concat5.v". + +[INFO :PA0201] Parsing source file "t_math_shift_rep.v". + +[INFO :PA0201] Parsing source file "t_math_signed.v". + +[INFO :PA0201] Parsing source file "t_clk_condflop.v". + +[INFO :PA0201] Parsing source file "t_clk_dpulse.v". + +[INFO :PA0201] Parsing source file "t_clk_first.v". + +[INFO :PA0201] Parsing source file "t_clk_gen.v". + +[INFO :PA0201] Parsing source file "t_clk_inp_init.v". + +[INFO :PA0201] Parsing source file "t_math_signed6.v". + +[INFO :PA0201] Parsing source file "t_clk_latchgate.v". + +[INFO :PA0201] Parsing source file "t_math_signed7.v". + +[INFO :PA0201] Parsing source file "t_math_svl.v". + +[INFO :PA0201] Parsing source file "t_clocker.v". + +[INFO :PA0201] Parsing source file "t_mem_slice_bad.v". + +[INFO :PA0201] Parsing source file "t_concat_large_bad.v". + +[INFO :PA0201] Parsing source file "t_concat_opt.v". + +[INFO :PA0201] Parsing source file "t_math_trig.v". + +[INFO :PA0201] Parsing source file "t_mem_slice_dtype_bad.v". + +[INFO :PA0201] Parsing source file "t_metacmt_onoff.v". + +[INFO :PA0201] Parsing source file "t_mod_interface_array.v". + +[INFO :PA0201] Parsing source file "t_mod_longname.v". + +[INFO :PA0201] Parsing source file "t_order.v". + +[INFO :PA0201] Parsing source file "t_order_doubleloop.v". + +[INFO :PA0201] Parsing source file "t_mem_file.v". + +[INFO :PA0201] Parsing source file "t_cover_line.v". + +[INFO :PA0201] Parsing source file "t_crazy_sel.v". + +[INFO :PA0201] Parsing source file "t_order_wireloop.v". + +[INFO :PA0201] Parsing source file "t_package_abs.v". + +[INFO :PA0201] Parsing source file "t_mem_multi_io2.v". + +[INFO :PA0201] Parsing source file "t_mem_multi_ref_bad.v". + +[INFO :PA0201] Parsing source file "t_mem_packed.v". + +[INFO :PA0201] Parsing source file "t_dedupe_clk_gate.v". + +[INFO :PA0201] Parsing source file "t_delay.v". + +[INFO :PA0201] Parsing source file "t_detectarray_1.v". + +[INFO :PA0201] Parsing source file "t_detectarray_2.v". + +[INFO :PA0201] Parsing source file "t_display.v". + +[INFO :PA0201] Parsing source file "t_package_dimport.v". + +[INFO :PA0201] Parsing source file "t_display_time.v". + +[INFO :PA0201] Parsing source file "t_dos.v". + +[INFO :PA0201] Parsing source file "t_dpi_2exp_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_accessors.v". + +[INFO :PA0201] Parsing source file "t_package_twodeep.v". + +[INFO :PA0201] Parsing source file "t_param_array.v". + +[INFO :PA0201] Parsing source file "t_mem_slot.v". + +[INFO :PA0201] Parsing source file "t_mod_dup_bad.v". + +[INFO :PA0201] Parsing source file "t_mod_interface_array1.v". + +[INFO :PA0201] Parsing source file "t_mod_nomod.v". + +[INFO :PA0201] Parsing source file "t_mod_recurse1.v". + +[INFO :PA0201] Parsing source file "t_multitop_sig.v". + +[INFO :PA0201] Parsing source file "t_optm_redor.v". + +[INFO :PA0201] Parsing source file "t_order_b.v". + +[INFO :PA0201] Parsing source file "t_order_clkinst.v". + +[INFO :PA0201] Parsing source file "t_order_multidriven.v". + +[INFO :PA0201] Parsing source file "t_param_concat.v". + +[INFO :PA0201] Parsing source file "t_param_default_bad.v". + +[INFO :PA0201] Parsing source file "t_param_first_b.v". + +[INFO :PA0201] Parsing source file "t_param_if_blk.v". + +[INFO :PA0201] Parsing source file "t_param_array3.v". + +[INFO :PA0201] Parsing source file "t_param_bit_sel.v". + +[INFO :PA0201] Parsing source file "t_param_circ_bad.v". + +[INFO :PA0201] Parsing source file "t_param_const_part.v". + +[INFO :PA0201] Parsing source file "t_param_first.v". + +[INFO :PA0201] Parsing source file "t_param_package.v". + +[INFO :PA0201] Parsing source file "t_mem_multi_io3.v". + +[INFO :PA0201] Parsing source file "t_param_real.v". + +[INFO :PA0201] Parsing source file "t_param_scope_bad.v". + +[INFO :PA0201] Parsing source file "t_param_sel.v". + +[INFO :PA0201] Parsing source file "t_param_value.v". + +[INFO :PA0201] Parsing source file "t_dpi_imp_gen.v". + +[INFO :PA0201] Parsing source file "t_dpi_lib.v". + +[INFO :PA0201] Parsing source file "t_param_named.v". + +[INFO :PA0201] Parsing source file "t_param_no_parentheses.v". + +[INFO :PA0201] Parsing source file "t_param_repl.v". + +[INFO :PA0201] Parsing source file "t_dpi_logic_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_name_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_open.v". + +[INFO :PA0201] Parsing source file "t_mem_packed_assign.v". + +[INFO :PA0201] Parsing source file "t_mem_packed_bad.v". + +[INFO :PA0201] Parsing source file "t_param_shift.v". + +[INFO :PA0201] Parsing source file "t_mem_slice.v". + +[INFO :PA0201] Parsing source file "t_param_type.v". + +[INFO :PA0201] Parsing source file "t_mod_dup_ign.v". + +[INFO :PA0201] Parsing source file "t_mod_interface_array2.v". + +[INFO :PA0201] Parsing source file "t_mod_recurse.v". + +[INFO :PA0201] Parsing source file "t_order_a.v". + +[INFO :PA0201] Parsing source file "t_param_wide_io.v". + +[INFO :PA0201] Parsing source file "t_order_comboloop.v". + +[INFO :PA0201] Parsing source file "t_parse_delay.v". + +[INFO :PA0201] Parsing source file "t_order_first.v". + +[INFO :PA0201] Parsing source file "t_past_bad.v". + +[INFO :PA0201] Parsing source file "t_order_quad.v". + +[INFO :PA0201] Parsing source file "t_pp_circdef_bad.v". + +[INFO :PA0201] Parsing source file "t_pp_dupdef.v". + +[INFO :PA0201] Parsing source file "t_pp_lib.v". + +[INFO :PA0201] Parsing source file "t_pp_misdef_bad.v". + +[INFO :PA0201] Parsing source file "t_pp_underline_bad.v". + +[INFO :PA0201] Parsing source file "t_preproc_def09.v". + +[INFO :PA0201] Parsing source file "t_preproc_persist2.v". + +[INFO :PA0201] Parsing source file "t_preproc_ttempty.v". + +[INFO :PA0201] Parsing source file "t_program.v". + +[INFO :PA0201] Parsing source file "t_reloop_cam.v". + +[INFO :PA0201] Parsing source file "t_package.v". + +[INFO :PA0201] Parsing source file "t_pipe_filter.v". + +[INFO :PA0201] Parsing source file "t_pp_lib_library.v". + +[INFO :PA0201] Parsing source file "t_pp_pragmas.v". + +[INFO :PA0201] Parsing source file "t_preproc_inc_notfound_bad.v". + +[INFO :PA0201] Parsing source file "t_preproc_kwd.v". + +[INFO :PA0201] Parsing source file "t_package_enum.v". + +[INFO :PA0201] Parsing source file "t_dpi_openfirst.v". + +[INFO :PA0201] Parsing source file "t_select_index.v". + +[INFO :PA0201] Parsing source file "t_real_param.v". + +[INFO :PA0201] Parsing source file "t_select_index2.v". + +[INFO :PA0201] Parsing source file "t_dpi_openreg_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_qw.v". + +[INFO :PA0201] Parsing source file "t_dpi_shortcircuit2.v". + +[INFO :PA0201] Parsing source file "t_dpi_string.v". + +[INFO :PA0201] Parsing source file "t_select_lhs_oob2.v". + +[INFO :PA0201] Parsing source file "t_dpi_sys.v". + +[INFO :PA0201] Parsing source file "t_dpi_threads.v". + +[INFO :PA0201] Parsing source file "t_package_param.v". + +[INFO :PA0201] Parsing source file "t_param.v". + +[INFO :PA0201] Parsing source file "t_param_ceil.v". + +[INFO :PA0201] Parsing source file "t_dpi_vams.v". + +[INFO :PA0201] Parsing source file "t_dpi_var.v". + +[INFO :PA0201] Parsing source file "t_rnd.v". + +[INFO :PA0201] Parsing source file "t_scope_map.v". + +[INFO :PA0201] Parsing source file "t_select_param.v". + +[INFO :PA0201] Parsing source file "t_select_bad_msb.v". + +[INFO :PA0201] Parsing source file "t_select_bad_range.v". + +[INFO :PA0201] Parsing source file "t_select_bad_range2.v". + +[INFO :PA0201] Parsing source file "t_select_bound2.v". + +[INFO :PA0201] Parsing source file "t_select_little.v". + +[INFO :PA0201] Parsing source file "t_param_ddeep_width.v". + +[INFO :PA0201] Parsing source file "t_param_first_a.v". + +[INFO :PA0201] Parsing source file "t_param_local.v". + +[INFO :PA0201] Parsing source file "t_embed1_child.v". + +[INFO :PA0201] Parsing source file "t_embed1_wrap.v". + +[INFO :PA0201] Parsing source file "t_enum.v". + +[INFO :PA0201] Parsing source file "t_param_mem_attr.v". + +[INFO :PA0201] Parsing source file "t_param_module.v". + +[INFO :PA0201] Parsing source file "t_select_loop.v". + +[INFO :PA0201] Parsing source file "t_select_plusloop.v". + +[INFO :PA0201] Parsing source file "t_select_plus.v". + +[INFO :PA0201] Parsing source file "t_stream2.v". + +[INFO :PA0201] Parsing source file "t_enum_bad_hide.v". + +[INFO :PA0201] Parsing source file "t_enum_func.v". + +[INFO :PA0201] Parsing source file "t_param_named_2.v". + +[INFO :PA0201] Parsing source file "t_enum_int.v". + +[INFO :PA0201] Parsing source file "t_param_public.v". + +[INFO :PA0201] Parsing source file "t_param_real2.v". + +[INFO :PA0201] Parsing source file "t_enum_name2.v". + +[INFO :PA0201] Parsing source file "t_param_seg.v". + +[INFO :PA0201] Parsing source file "t_enum_name3.v". + +[INFO :PA0201] Parsing source file "t_enum_public.v". + +[INFO :PA0201] Parsing source file "t_param_sel_range.v". + +[INFO :PA0201] Parsing source file "t_enum_type_methods.v". + +[INFO :PA0201] Parsing source file "t_string_type_methods.v". + +[INFO :PA0201] Parsing source file "t_slice_cond.v". + +[INFO :PA0201] Parsing source file "t_struct_param.v". + +[INFO :PA0201] Parsing source file "t_param_type2.v". + +[INFO :PA0201] Parsing source file "t_param_up_bad.v". + +[INFO :PA0201] Parsing source file "t_param_while.v". + +[INFO :PA0201] Parsing source file "t_past.v". + +[INFO :PA0201] Parsing source file "t_stop_bad.v". + +[INFO :PA0201] Parsing source file "t_stream.v". + +[INFO :PA0201] Parsing source file "t_preproc.v". + +[INFO :PA0201] Parsing source file "t_select_set.v". + +[INFO :PA0201] Parsing source file "t_struct_pat_width.v". + +[INFO :PA0201] Parsing source file "t_struct_portsel.v". + +[INFO :PA0201] Parsing source file "t_struct_port.v". + +[INFO :PA0201] Parsing source file "t_struct_unpacked.v". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux.v". + +[INFO :PA0201] Parsing source file "t_slice_init.v". + +[INFO :PA0201] Parsing source file "t_stream3.v". + +[INFO :PA0201] Parsing source file "t_trace_fst.v". + +[INFO :PA0201] Parsing source file "t_trace_timescale.v". + +[INFO :PA0201] Parsing source file "t_tri_array_pull.v". + +[INFO :PA0201] Parsing source file "t_sv_conditional.v". + +[INFO :PA0201] Parsing source file "t_tri_eqcase.v". + +[INFO :PA0201] Parsing source file "t_tri_pull2_bad.v". + +[INFO :PA0201] Parsing source file "t_tri_pull_bad.v". + +[INFO :PA0201] Parsing source file "t_tri_pullvec_bad.v". + +[INFO :PA0201] Parsing source file "t_tri_select_unsized.v". + +[INFO :PA0201] Parsing source file "t_type_param.v". + +[INFO :PA0201] Parsing source file "t_struct_anon.v". + +[INFO :PA0201] Parsing source file "t_struct_array.v". + +[INFO :PA0201] Parsing source file "t_struct_init.v". + +[INFO :PA0201] Parsing source file "t_trace_cat.v". + +[INFO :PA0201] Parsing source file "t_trace_decoration.v". + +[INFO :PA0201] Parsing source file "t_trace_ena.v". + +[INFO :PA0201] Parsing source file "t_struct_nest.v". + +[INFO :PA0201] Parsing source file "t_trace_packed_struct.v". + +[INFO :PA0201] Parsing source file "t_struct_notfound_bad.v". + +[INFO :PA0201] Parsing source file "t_struct_packed_value_list.v". + +[INFO :PA0201] Parsing source file "t_trace_primitive.v". + +[INFO :PA0201] Parsing source file "t_struct_unaligned.v". + +[INFO :PA0201] Parsing source file "t_trace_string.v". + +[INFO :PA0201] Parsing source file "t_struct_unpacked_bad.v". + +[INFO :PA0201] Parsing source file "t_sv_cpu.v". + +[INFO :PA0201] Parsing source file "t_sys_file_scan.v". + +[INFO :PA0201] Parsing source file "t_sys_fread.v". + +[INFO :PA0201] Parsing source file "t_sys_plusargs_bad.v". + +[INFO :PA0201] Parsing source file "t_sys_rand.v". + +[INFO :PA0201] Parsing source file "t_typedef_port.v". + +[INFO :PA0201] Parsing source file "t_unopt_array.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem_bad_addr.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem_bad_digit.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem_bad_end.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem_bad_notfound.v". + +[INFO :PA0201] Parsing source file "t_sys_sformat.v". + +[INFO :PA0201] Parsing source file "t_table_fsm.v". + +[INFO :PA0201] Parsing source file "t_unoptflat_simple_2.v". + +[INFO :PA0201] Parsing source file "t_unroll_complexcond.v". + +[INFO :PA0201] Parsing source file "t_unroll_signed.v". + +[INFO :PA0201] Parsing source file "t_trace_param.v". + +[INFO :PA0201] Parsing source file "t_trace_scstruct.v". + +[INFO :PA0201] Parsing source file "t_tri_array.v". + +[INFO :PA0201] Parsing source file "t_tri_dangle.v". + +[INFO :PA0201] Parsing source file "t_tri_gen.v". + +[INFO :PA0201] Parsing source file "t_tri_ifbegin.v". + +[INFO :PA0201] Parsing source file "t_tri_gate.v". + +[INFO :PA0201] Parsing source file "t_var_dup2.v". + +[INFO :PA0201] Parsing source file "t_var_dup_bad.v". + +[INFO :PA0201] Parsing source file "t_var_in_assign_bad.v". + +[INFO :PA0201] Parsing source file "t_var_init.v". + +[INFO :PA0201] Parsing source file "t_tri_public.v". + +[INFO :PA0201] Parsing source file "t_tri_select.v". + +[INFO :PA0201] Parsing source file "t_typedef.v". + +[INFO :PA0201] Parsing source file "t_var_nonamebegin.v". + +[INFO :PA0201] Parsing source file "t_tri_graph.v". + +[INFO :PA0201] Parsing source file "t_var_outoforder.v". + +[INFO :PA0201] Parsing source file "t_tri_inout.v". + +[INFO :PA0201] Parsing source file "t_tri_inz.v". + +[INFO :PA0201] Parsing source file "t_tri_pull01.v". + +[INFO :PA0201] Parsing source file "t_var_port2_bad.v". + +[INFO :PA0201] Parsing source file "t_var_port_bad.v". + +[INFO :PA0201] Parsing source file "t_var_ref.v". + +[INFO :PA0201] Parsing source file "t_tri_various.v". + +[INFO :PA0201] Parsing source file "t_udp.v". + +[INFO :PA0201] Parsing source file "t_var_types_bad.v". + +[INFO :PA0201] Parsing source file "t_verilated_debug.v". + +[INFO :PA0201] Parsing source file "t_vpi_memory.v". + +[INFO :PA0201] Parsing source file "t_vpi_var.v". + +[INFO :PA0201] Parsing source file "t_typedef_array.v". + +[INFO :PA0201] Parsing source file "t_typedef_circ_bad.v". + +[INFO :PA0201] Parsing source file "t_typedef_param.v". + +[INFO :PA0201] Parsing source file "t_udp_noname.v". + +[INFO :PA0201] Parsing source file "t_uniqueif.v". + +[INFO :PA0201] Parsing source file "t_unopt_converge.v". + +[INFO :PA0201] Parsing source file "t_unopt_converge_initial.v". + +[INFO :PA0201] Parsing source file "t_unoptflat_simple_3.v". + +[INFO :PA0201] Parsing source file "t_unroll_forfor.v". + +[INFO :PA0201] Parsing source file "t_unoptflat_simple.v". + +[INFO :PA0201] Parsing source file "t_unpacked_array_order.v". + +[INFO :PA0201] Parsing source file "t_var_assign_landr.v". + +[INFO :PA0201] Parsing source file "t_var_dotted.v". + +[INFO :PA0201] Parsing source file "t_extend.v". + +[INFO :PA0201] Parsing source file "t_final.v". + +[INFO :PA0201] Parsing source file "t_flag_bboxsys.v". + +[INFO :PA0201] Parsing source file "t_unroll_genf.v". + +[INFO :PA0201] Parsing source file "t_vams_wreal.v". + +[INFO :PA0201] Parsing source file "t_var_const.v". + +[INFO :PA0201] Parsing source file "t_var_overzero.v". + +[INFO :PA0201] Parsing source file "t_var_suggest_bad.v". + +[INFO :PA0201] Parsing source file "t_var_types.v". + +[INFO :PA0201] Parsing source file "t_flag_debug_noleak.v". + +[INFO :PA0201] Parsing source file "t_flag_define.v". + +[INFO :PA0201] Parsing source file "t_flag_future.v". + +[INFO :PA0201] Parsing source file "t_flag_getenv.v". + +[INFO :PA0201] Parsing source file "t_flag_lib.v". + +[INFO :PA0201] Parsing source file "t_flag_libinc.v". + +[INFO :PA0201] Parsing source file "t_flag_relinc.v". + +[INFO :PA0201] Parsing source file "t_flag_topmod2_bad.v". + +[INFO :PA0201] Parsing source file "t_flag_topmodule_inline.v". + +[INFO :PA0201] Parsing source file "t_flag_wfatal.v". + +[INFO :PA0201] Parsing source file "t_flag_xinitial_0.v". + +[INFO :PA0201] Parsing source file "t_for_break.v". + +[INFO :PA0201] Parsing source file "t_for_loop.v". + +[INFO :PA0201] Parsing source file "t_func_begin2.v". + +[INFO :PA0201] Parsing source file "t_func_const.v". + +[INFO :PA0201] Parsing source file "t_var_dup3.v". + +[INFO :PA0201] Parsing source file "t_var_in_assign.v". + +[INFO :PA0201] Parsing source file "t_var_life.v". + +[INFO :PA0201] Parsing source file "t_var_overwidth_bad.v". + +[INFO :PA0201] Parsing source file "t_var_pinsizes.v". + +[INFO :PA0201] Parsing source file "t_func_default_warn.v". + +[INFO :PA0201] Parsing source file "t_func_endian.v". + +[INFO :PA0201] Parsing source file "t_var_ref_bad1.v". + +[INFO :PA0201] Parsing source file "t_var_ref_bad2.v". + +[INFO :PA0201] Parsing source file "t_var_rsvd_port.v". + +[INFO :PA0201] Parsing source file "t_var_set_link.v". + +[INFO :PA0201] Parsing source file "t_var_tieout.v". + +[INFO :PA0201] Parsing source file "t_var_vec_sel.v". + +[INFO :PA0201] Parsing source file "t_verilated_all.v". + +[INFO :PA0201] Parsing source file "t_vpi_get.v". + +[INFO :PA0201] Parsing source file "t_wire_beh_bad.v". + +[INFO :PA0201] Parsing source file "t_xml_first.v". + +[INFO :PA0201] Parsing source file "t_xml_tag.v". + +[INFO :PA0201] Parsing source file "t_func_graphcirc.v". + +[INFO :PA0201] Parsing source file "t_func_lib.v". + +[INFO :PA0201] Parsing source file "t_func_lib_sub.v". + +[INFO :PA0201] Parsing source file "t_func_numones.v". + +[INFO :PA0201] Parsing source file "t_func_outfirst.v". + +[INFO :PA0201] Parsing source file "t_func_range.v". + +[INFO :PA0201] Parsing source file "t_func_real_param.v". + +[INFO :PA0201] Parsing source file "t_func_sum.v". + +[INFO :PA0201] Parsing source file "t_func_under.v". + +[INFO :PA0201] Parsing source file "t_func_unit.v". + +[INFO :PA0201] Parsing source file "t_func_void.v". + +[INFO :PA0201] Parsing source file "t_func_wide_out_bad.v". + +[INFO :PA0201] Parsing source file "t_gate_delref.v". + +[INFO :PA0201] Parsing source file "t_gate_fdup.v". + +[INFO :PA0201] Parsing source file "t_gated_clk_1.v". + +[INFO :PA0201] Parsing source file "t_gen_cond_bitrange_bad.v". + +[INFO :PA0201] Parsing source file "t_gen_for2.v". + +[INFO :PA0201] Parsing source file "t_gen_for_shuffle.v". + +[INFO :PA0201] Parsing source file "t_gen_inc.v". + +[INFO :PA0201] Parsing source file "t_generate_fatal_bad.v". + +[INFO :PA0201] Parsing source file "t_hierarchy_unnamed.v". + +[INFO :PA0201] Parsing source file "t_if_deep.v". + +[INFO :PA0201] Parsing source file "t_inst_aport.v". + +[INFO :PA0201] Parsing source file "t_inst_comma.v". + +[INFO :PA0201] Parsing source file "t_inst_first.v". + +[INFO :PA0201] Parsing source file "t_inst_port_array.v". + +[INFO :PA0201] Parsing source file "t_inst_signed1.v". + +[INFO :PA0201] Parsing source file "t_inst_tree.v". + +[INFO :PA0201] Parsing source file "t_interface2.v". + +[INFO :PA0201] Parsing source file "t_interface_bind_public.v". + +[INFO :PA0201] Parsing source file "t_interface_gen11.v". + +[INFO :PA0201] Parsing source file "t_interface_gen2.v". + +[INFO :PA0201] Parsing source file "t_interface_gen6.v". + +[INFO :PA0201] Parsing source file "t_interface_gen9.v". + +[INFO :PA0201] Parsing source file "t_interface_modport.v". + +[INFO :PA0201] Parsing source file "t_interface_top_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_typo_bad.v". + +[INFO :PA0201] Parsing source file "t_langext_1.v". + +[INFO :PA0201] Parsing source file "t_lint_always_comb_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_block_redecl_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_comb_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_declfilename.v". + +[INFO :PA0201] Parsing source file "t_lint_defparam.v". + +[INFO :PA0201] Parsing source file "t_lint_implicit_def_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_import_name_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_in_inc_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_literal_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_modport_dir_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_realcvt_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_rsvd_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_subout_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unsup_mixed.v". + +[INFO :PA0201] Parsing source file "t_lint_unused_iface.v". + +[INFO :PA0201] Parsing source file "t_lint_width.v". + +[INFO :PA0201] Parsing source file "t_lint_width_genfor_bad.v". + +[INFO :PA0201] Parsing source file "t_math_concat.v". + +[INFO :PA0201] Parsing source file "t_math_concat64.v". + +[INFO :PA0201] Parsing source file "t_math_equal.v". + +[INFO :PA0201] Parsing source file "t_math_imm2.v". + +[INFO :PA0201] Parsing source file "t_math_msvc_64.v". + +[INFO :PA0201] Parsing source file "t_math_mul.v". + +[INFO :PA0201] Parsing source file "t_math_pow2.v". + +[INFO :PA0201] Parsing source file "t_math_pow4.v". + +[INFO :PA0201] Parsing source file "t_math_pow5.v". + +[INFO :PA0201] Parsing source file "t_math_pow6.v". + +[INFO :PA0201] Parsing source file "t_math_real.v". + +[INFO :PA0201] Parsing source file "t_math_shift.v". + +[INFO :PA0201] Parsing source file "t_math_shiftrs.v". + +[INFO :PA0201] Parsing source file "t_math_signed3.v". + +[INFO :PA0201] Parsing source file "t_math_signed_wire.v". + +[INFO :PA0201] Parsing source file "t_math_strwidth.v". + +[INFO :PA0201] Parsing source file "t_math_svl2.v". + +[INFO :PA0201] Parsing source file "t_math_swap.v". + +[INFO :PA0201] Parsing source file "t_math_width.v". + +[INFO :PA0201] Parsing source file "t_mem.v". + +[INFO :PA0201] Parsing source file "t_mem_cond.v". + +[INFO :PA0201] Parsing source file "t_mem_fifo.v". + +[INFO :PA0201] Parsing source file "t_mem_func.v". + +[INFO :PA0201] Parsing source file "t_mem_multi_io.v". + +[INFO :PA0201] Parsing source file "t_mem_multiwire.v". + +[INFO :PA0201] Parsing source file "t_mem_shift.v". + +[INFO :PA0201] Parsing source file "t_mem_slice_conc_bad.v". + +[INFO :PA0201] Parsing source file "t_mem_twoedge.v". + +[INFO :PA0201] Parsing source file "t_multitop1.v". + +[INFO :PA0201] Parsing source file "t_multitop1s.v". + +[INFO :PA0201] Parsing source file "t_optm_if_array.v". + +[INFO :PA0201] Parsing source file "t_order_2d.v". + +[INFO :PA0201] Parsing source file "t_order_comboclkloop.v". + +[INFO :PA0201] Parsing source file "t_order_loop_bad.v". + +[INFO :PA0201] Parsing source file "t_order_multialways.v". + +[INFO :PA0201] Parsing source file "t_package_ddecl.v". + +[INFO :PA0201] Parsing source file "t_package_dot.v". + +[INFO :PA0201] Parsing source file "t_package_export.v". + +[INFO :PA0201] Parsing source file "t_package_verb.v". + +[INFO :PA0201] Parsing source file "t_param_array2.v". + +[INFO :PA0201] Parsing source file "t_param_avec.v". + +[INFO :PA0201] Parsing source file "t_param_chain.v". + +[INFO :PA0201] Parsing source file "t_param_default.v". + +[INFO :PA0201] Parsing source file "t_param_func.v". + +[INFO :PA0201] Parsing source file "t_param_long.v". + +[INFO :PA0201] Parsing source file "t_past_unsup_bad.v". + +[INFO :PA0201] Parsing source file "t_pp_display.v". + +[INFO :PA0201] Parsing source file "t_preproc_ifdef.v". + +[INFO :PA0201] Parsing source file "t_preproc_inc_bad.v". + +[INFO :PA0201] Parsing source file "t_preproc_noline.v". + +[INFO :PA0201] Parsing source file "t_preproc_persist.v". + +[INFO :PA0201] Parsing source file "t_preproc_persist_inc.v". + +[INFO :PA0201] Parsing source file "t_preproc_undefineall.v". + +[INFO :PA0201] Parsing source file "t_repeat.v". + +[INFO :PA0201] Parsing source file "t_runflag.v". + +[INFO :PA0201] Parsing source file "t_runflag_seed.v". + +[INFO :PA0201] Parsing source file "t_savable.v". + +[INFO :PA0201] Parsing source file "t_select_bad_range3.v". + +[INFO :PA0201] Parsing source file "t_select_bad_tri.v". + +[INFO :PA0201] Parsing source file "t_select_bound1.v". + +[INFO :PA0201] Parsing source file "t_select_lhs_oob.v". + +[INFO :PA0201] Parsing source file "t_select_little_pack.v". + +[INFO :PA0201] Parsing source file "t_select_negative.v". + +[INFO :PA0201] Parsing source file "t_select_runtime_range.v". + +[INFO :PA0201] Parsing source file "t_slice_struct_array_modport.v". + +[INFO :PA0201] Parsing source file "t_static_elab.v". + +[INFO :PA0201] Parsing source file "t_string.v". + +[INFO :PA0201] Parsing source file "t_struct_packed_sysfunct.v". + +[INFO :PA0201] Parsing source file "t_struct_packed_write_read.v". + +[INFO :PA0201] Parsing source file "t_sys_file_basic.v". + +[INFO :PA0201] Parsing source file "t_sys_plusargs.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem.v". + +[INFO :PA0201] Parsing source file "t_sys_system.v". + +[INFO :PA0201] Parsing source file "t_sys_time.v". + +[INFO :PA0201] Parsing source file "t_threads_counter.v". + +[INFO :PA0201] Parsing source file "t_trace_array.v". + +[INFO :PA0201] Parsing source file "t_trace_complex.v". + +[INFO :PA0201] Parsing source file "t_trace_public.v". + +[INFO :PA0201] Parsing source file "t_tri_array_bufif.v". + +[INFO :PA0201] Parsing source file "t_tri_inout2.v". + +[INFO :PA0201] Parsing source file "t_tri_pullup.v". + +[INFO :PA0201] Parsing source file "t_tri_unconn.v". + +[INFO :PA0201] Parsing source file "t_typedef_signed.v". + +[INFO :PA0201] Parsing source file "t_unopt_bound.v". + +[INFO :PA0201] Parsing source file "t_unopt_combo.v". + +[INFO :PA0201] Parsing source file "t_vams_basic.v". + +[INFO :PA0201] Parsing source file "t_var_bad_hide.v". + +[INFO :PA0201] Parsing source file "t_var_bad_hide2.v". + +[INFO :PA0201] Parsing source file "t_var_bad_sameas.v". + +[INFO :PA0201] Parsing source file "t_var_bad_sv.v". + +[INFO :PA0201] Parsing source file "t_var_const_bad.v". + +[INFO :PA0201] Parsing source file "t_var_dup2_bad.v". + +[INFO :PA0201] Parsing source file "t_var_escape.v". + +[INFO :PA0201] Parsing source file "t_var_local.v". + +[INFO :PA0201] Parsing source file "t_var_notfound_bad.v". + +[INFO :PA0201] Parsing source file "t_var_overcmp.v". + +[INFO :PA0201] Parsing source file "t_var_ref_bad3.v". + +[INFO :PA0201] Parsing source file "t_var_rsvd.v". + +[INFO :PA0201] Parsing source file "t_var_static.v". + +[INFO :PA0201] Parsing source file "t_var_xref_gen.v". + +[INFO :PA0201] Parsing source file "t_vlt_warn.v". + +[INFO :PA0201] Parsing source file "t_vpi_sc.v". + +[INFO :PA0201] Parsing source file "t_vpi_unimpl.v". + +[INFO :PA0201] Parsing source file "t_wire_types.v". + +[ERROR:PA0207] t_sv_cpu_code/ports.sv:39 Syntax error: extraneous input 'SURELOG_MACRO_NOT_DEFINED:PACKED!!!' expecting {'{', 'packed'}, + struct SURELOG_MACRO_NOT_DEFINED:PACKED!!! + ^-- ./slpp_unit/work/t_sv_cpu_code/ports.sv:39 col:9. + +[ERROR:PA0207] t_sv_cpu_code/rom.sv:18 Syntax error: no viable alternative at input ''{\n SURELOG_MACRO_NOT_DEFINED:LDI!!!', + SURELOG_MACRO_NOT_DEFINED:LDI!!! + ^-- ./slpp_unit/work/t_sv_cpu_code/rom.sv:18 col:6. + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:18 Unknown macro "LDI". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:19 Unknown macro "LDI". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:20 Unknown macro "LDI". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:21 Unknown macro "LDI". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:23 Unknown macro "STS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:24 Unknown macro "STS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:25 Unknown macro "STS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:26 Unknown macro "STS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:28 Unknown macro "LDS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:29 Unknown macro "LDS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:30 Unknown macro "LDS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:31 Unknown macro "LDS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:33 Unknown macro "JMP". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:35 Unknown macro "EOP". + +[ERROR:PA0207] t_attr_parenstar.v:32 Syntax error: no viable alternative at input '@ (*', + always @ (* + ^-- ./slpp_unit/work/t_attr_parenstar.v:32 col:12. + +[ERROR:PA0207] t_case_wild.v:64 Syntax error: no viable alternative at input 'casez (in[0])\n endcase', + endcase + ^-- ./slpp_unit/work/t_case_wild.v:64 col:6. + +[ERROR:PA0207] t_clk_concat2.v:80 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + input clk; + ^-- ./slpp_unit/work/t_clk_concat2.v:80 col:3. + +[ERROR:PA0207] t_clk_concat5.v:83 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + input clk; + ^-- ./slpp_unit/work/t_clk_concat5.v:83 col:3. + +[ERROR:PA0207] t_clk_concat6.v:96 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + input clk; + ^-- ./slpp_unit/work/t_clk_concat6.v:96 col:3. + +[ERROR:PA0207] t_const_dec_mixed_bad.v:8 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n parameter [200:0] MIXED = 32'dx_1', + parameter [200:0] MIXED = 32'dx_1; + ^-- ./slpp_unit/work/t_const_dec_mixed_bad.v:8 col:35. + +[ERROR:PA0207] t_dpi_display.v:10 Syntax error: no viable alternative at input 'module t ();\n\n SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion."', + SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion." + ^-- ./slpp_unit/work/t_dpi_display.v:10 col:39. + +[ERROR:PA0203] t_dpi_display.v:10 Unknown macro "error". + +[ERROR:PA0207] t_dpi_sys.v:14 Syntax error: no viable alternative at input 'module t ();\n\n SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls."', + SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." + ^-- ./slpp_unit/work/t_dpi_sys.v:14 col:39. + +[ERROR:PA0203] t_dpi_sys.v:14 Unknown macro "error". + +[ERROR:PA0207] t_dpi_threads.v:18 Syntax error: extraneous input '"Only Verilator supports PLI-ish DPI calls."' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." + ^-- ./slpp_unit/work/t_dpi_threads.v:18 col:39. + +[ERROR:PA0203] t_dpi_threads.v:18 Unknown macro "error". + +[ERROR:PA0209] t_dpi_vams.v:7 Unsupported keyword set: "1800+VAMS". + +[ERROR:PA0207] t_dpi_var.v:64 Syntax error: no viable alternative at input 'module sub (/*AUTOARG*/\n // Outputs\n fr_a, fr_b, fr_chk,\n // Inputs\n in\n );\n\nSURELOG_MACRO_NOT_DEFINED:systemc_imp_header!!! \n void', + void mon_class_name(const char* namep); + ^-- ./slpp_unit/work/t_dpi_var.v:64 col:2. + +[ERROR:PA0203] t_dpi_var.v:63 Unknown macro "systemc_imp_header". + +[ERROR:PA0207] t_enum.v:33 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n localparam FIVE = 5;\n\n enum { e0,\n\t e1,\n\t e3=3,\n\t e5=FIVE,\n\t e10_[2] = 10,\n\t e12,\n\t e20_[5:7] = 25,\n\t e20_z,\n\t e30_[7:5] = 30,\n\t e30_z\n\t } EN;\n\n enum {\n\t z5 = e5\n\t } ZN;\n\n typedef enum [', + typedef enum [2:0] { ONES=~0 } three_t; + ^-- ./slpp_unit/work/t_enum.v:33 col:16. + +[ERROR:PA0207] t_enum_type_methods.v:13 Syntax error: no viable alternative at input 'enum [', + typedef enum [3:0] { + ^-- ./slpp_unit/work/t_enum_type_methods.v:13 col:16. + +[ERROR:PA0207] t_extend_class.v:49 Syntax error: extraneous input '#' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, +#include "t_extend_class_c.h" // Header for contained object +^-- ./slpp_unit/work/t_extend_class.v:49 col:0. + +[ERROR:PA0203] t_extend_class.v:48 Unknown macro "systemc_header". + +[ERROR:PA0203] t_extend_class.v:50 Unknown macro "systemc_interface". + +[ERROR:PA0203] t_extend_class.v:52 Unknown macro "systemc_ctor". + +[ERROR:PA0203] t_extend_class.v:54 Unknown macro "systemc_dtor". + +[ERROR:PA0203] t_extend_class.v:56 Unknown macro "verilog". + +[ERROR:PA0207] t_gen_missing.v:8 Syntax error: extraneous input '"Bad Test"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + SURELOG_MACRO_NOT_DEFINED:error!!! "Bad Test" + ^-- ./slpp_unit/work/t_gen_missing.v:8 col:37. + +[ERROR:PA0203] t_gen_missing.v:8 Unknown macro "error". + +[ERROR:PA0207] t_hierarchy_identifier.v:30 Syntax error: token recognition error at: '\', + if (cnt==SIZE) begin : \0escaped___name + ^-- ./slpp_unit/work/t_hierarchy_identifier.v:30 col:26. + +[ERROR:PA0207] t_inst_missing.v:10 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n wire ok = 1'b0;\n // verilator lint_off PINNOCONNECT\n // verilator lint_off PINCONNECTEMPTY\n sub sub (.ok(ok), ,', + sub sub (.ok(ok), , .nc()); + ^-- ./slpp_unit/work/t_inst_missing.v:10 col:21. + +[ERROR:PA0207] t_inst_missing_bad.v:8 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n wire ok = 1'b0;\n sub sub (.ok(ok), ,', + sub sub (.ok(ok), , .nc()); + ^-- ./slpp_unit/work/t_inst_missing_bad.v:8 col:21. + +[ERROR:PA0207] t_interface_down_gen.v:75 Syntax error: no viable alternative at input 'Commercial sims choke', +SURELOG_MACRO_NOT_DEFINED:error!!! Commercial sims choke on cross ref here + ^-- ./slpp_unit/work/t_interface_down_gen.v:75 col:52. + +[ERROR:PA0203] t_interface_down_gen.v:75 Unknown macro "error". + +[ERROR:PA0207] t_interface_modportlist.v:10 Syntax error: no viable alternative at input 'my_module m(.clk(clk), iface', + my_module m(.clk(clk), iface); + ^-- ./slpp_unit/work/t_interface_modportlist.v:10 col:26. + +[ERROR:PA0207] t_lint_bsspace_bad.v:11 Syntax error: no viable alternative at input 'blak\n\nmodule', +module t; +^-- ./slpp_unit/work/t_lint_bsspace_bad.v:11 col:0. + +[ERROR:PA0207] t_lint_implicit_def_bad.v:14 Syntax error: extraneous input '`default_nettype' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, +`default_nettype none +^-- ./slpp_unit/work/t_lint_implicit_def_bad.v:14 col:0. + +[ERROR:PA0207] t_lint_in_inc_bad_2.vh:8 Syntax error: mismatched input 'if' expecting '(', + if if if; + ^-- ./slpp_unit/work/t_lint_in_inc_bad.v:18 col:6. + +[ERROR:PA0207] t_lint_mod_paren_bad.v:12 Syntax error: mismatched input '(' expecting ';', + ) ( + ^-- ./slpp_unit/work/t_lint_mod_paren_bad.v:12 col:5. + +[ERROR:PA0207] t_lint_pindup_bad.v:14 Syntax error: no viable alternative at input 'sub\n #(,', + #(, // Not found + ^-- ./slpp_unit/work/t_lint_pindup_bad.v:14 col:7. + +[ERROR:PA0207] t_lint_pkg_colon_bad.v:7 Syntax error: mismatched input '::' expecting ';', + reg mispkgb::bar_t b; + ^-- ./slpp_unit/work/t_lint_pkg_colon_bad.v:7 col:14. + +[ERROR:PA0207] t_lint_rsvd_bad.v:7 Syntax error: mismatched input 'endconfig' expecting {'design', 'localparam'}, +endconfig +^-- ./slpp_unit/work/t_lint_rsvd_bad.v:7 col:0. + +[ERROR:PA0207] t_mem_multi_ref_bad.v:18 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n reg dimn;\n reg [1:0] dim0;\n reg [1:0] dim1 [1:0];\n reg [1:0] dim2 [1:0][1:0];\n reg dim0nv[1:0];\n\n initial begin\n dimn[1:0] = 0; // Bad: Not ranged\n dim0[1][1] = 0; // Bad: Not arrayed\n dim1[1][1][1] = 0; // Bad: Not arrayed to right depth\n dim2[1][1][1] = 0; // OK\n dim2[0 +: 1][', + dim2[0 +: 1][1] = 0; // Bad: Range on non-bits + ^-- ./slpp_unit/work/t_mem_multi_ref_bad.v:18 col:18. + +[ERROR:PA0207] t_mem_slice_bad.v:38 Syntax error: mismatched input '[' expecting '=', + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^-- ./slpp_unit/work/t_mem_slice_bad.v:38 col:30. + +[ERROR:PA0207] t_pipe_filter.v:10 Syntax error: no viable alternative at input 'example line 10', +example line 10; + ^-- ./slpp_unit/work/t_pipe_filter.v:10 col:13. + +[ERROR:PA0207] t_pp_circdef_bad.v:14 Syntax error: no viable alternative at input 'logic [12-SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!!', +typedef logic [12-SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! +: SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! -1:0] d_t; + ^-- ./slpp_unit/work/t_pp_circdef_bad.v:9 col:18. + +[ERROR:PA0203] t_pp_circdef_bad.v:14 Unknown macro "SEL_NUM_BITS". + +[ERROR:PA0207] t_pp_display.v:22 Syntax error: no viable alternative at input '$display("left side : \"right side \"" // The 'left' as the variable name shouldn't match the "left" in the `" string\n initial', + initial begin + ^-- ./slpp_unit/work/t_pp_display.v:24 col:3. + +[ERROR:PA0207] t_pp_lib_library.v:7 Syntax error: no viable alternative at input 'input [SURELOG_MACRO_NOT_DEFINED:WIDTH!!!', + input [SURELOG_MACRO_NOT_DEFINED:WIDTH!!! -1:0] a; + ^-- ./slpp_unit/work/t_pp_lib_library.v:7 col:10. + +[ERROR:PA0203] t_pp_lib_library.v:7 Unknown macro "WIDTH". + +[ERROR:PA0203] t_pp_misdef_bad.v:9 Unknown macro "NDEFINED". + +[ERROR:PA0203] t_pp_misdef_bad.v:12 Unknown macro "imescale". + +[ERROR:PA0203] t_pp_pragmas.v:7 Unknown macro "verilog". + +[ERROR:PA0203] t_pp_pragmas.v:40 Unknown macro "remove_gatenames". + +[ERROR:PA0203] t_pp_pragmas.v:42 Unknown macro "remove_netnames". + +[ERROR:PA0207] t_preproc.v:100 Syntax error: token recognition error at: '"twoline: \"first \n', +$display("twoline: \"first + ^-- ./slpp_unit/work/t_preproc.v:125 col:9. + +[ERROR:PA0207] t_preproc_def09.v:12 Syntax error: mismatched input ''' expecting <EOF>, +'initial $display("start", "msg1" , "msg2" , "end");' +^-- ./slpp_unit/work/t_preproc_def09.v:10 col:0. + +[ERROR:PA0207] t_preproc_inc_inc_bad.vh:10 Syntax error: no viable alternative at input 'xx // intentional error\n\nendmodule', +endmodule +^-- ./slpp_unit/work/t_preproc_inc_bad.v:17 col:0. + +[ERROR:PA0209] t_preproc_kwd.v:73 Unsupported keyword set: "VAMS-2.3". + +[ERROR:PA0207] t_preproc_noline.v:7 Syntax error: no viable alternative at input 'Hello in t_preproc_psl', +Hello in t_preproc_psl.v + ^-- ./slpp_unit/work/t_preproc_noline.v:7 col:9. + +[ERROR:PA0207] t_preproc_persist.v:6 Syntax error: no viable alternative at input 'Inside "t_preproc_persist.v"', +Inside "t_preproc_persist.v". + ^-- ./slpp_unit/work/t_preproc_persist.v:6 col:7. + +[ERROR:PA0207] t_preproc_persist2.v:6 Syntax error: no viable alternative at input 'Inside "t_preproc_persist2.v"', +Inside "t_preproc_persist2.v". + ^-- ./slpp_unit/work/t_preproc_persist2.v:6 col:7. + +[ERROR:PA0207] t_preproc_persist_inc.v:6 Syntax error: no viable alternative at input 'Inside "t_preproc_persist_inc.v"', + Inside "t_preproc_persist_inc.v". + ^-- ./slpp_unit/work/t_preproc_persist_inc.v:6 col:8. + +[ERROR:PA0207] t_preproc_undefineall.v:8 Syntax error: extraneous input '"Test setup error, PREDEF_COMMAND_LINE pre-missing"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, +SURELOG_MACRO_NOT_DEFINED:error!!! "Test setup error, PREDEF_COMMAND_LINE pre-missing" + ^-- ./slpp_unit/work/t_preproc_undefineall.v:8 col:36. + +[ERROR:PA0203] t_preproc_undefineall.v:8 Unknown macro "error". + +[ERROR:PA0203] t_preproc_undefineall.v:13 Unknown macro "error". + +[ERROR:PA0207] t_trace_primitive.v:34 Syntax error: extraneous input 'assign' expecting {'input', 'output', 'reg', '(*', 'table', 'initial'}, +assign b = ~a; +^-- ./slpp_unit/work/t_trace_primitive.v:34 col:0. + +[ERROR:PA0207] t_tri_gate.v:21 Syntax error: extraneous input '"Unknown test name"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + SURELOG_MACRO_NOT_DEFINED:error!!! "Unknown test name" + ^-- ./slpp_unit/work/t_tri_gate.v:21 col:37. + +[ERROR:PA0203] t_tri_gate.v:21 Unknown macro "error". + +[ERROR:PA0209] t_vams_basic.v:6 Unsupported keyword set: "VAMS-2.3". + +[ERROR:PA0209] t_vams_wreal.v:6 Unsupported keyword set: "VAMS-2.3". + +[ERROR:PA0207] t_var_dup_bad.v:65 Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + output bad_reout_port; + ^-- ./slpp_unit/work/t_var_dup_bad.v:65 col:3. + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:9 No timescale set for "package_bus". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:17 No timescale set for "package_str". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:22 No timescale set for "package_uni". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv:28 No timescale set for "sv_bus_mux_demux_wrap". + +[WARNI:PA0205] t_sv_cpu_code/ac.sv:8 No timescale set for "ac". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv:12 No timescale set for "sv_bus_mux_demux_mux". + +[WARNI:PA0205] t_sv_cpu_code/adrdec.sv:8 No timescale set for "adrdec". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv:11 No timescale set for "sv_bus_mux_demux_demux". + +[WARNI:PA0205] t_sv_cpu_code/genbus_if.sv:14 No timescale set for "genbus_if". + +[WARNI:PA0205] t_sv_cpu_code/ac_ana.sv:8 No timescale set for "ac_ana". + +[WARNI:PA0205] t_sv_cpu_code/chip.sv:12 No timescale set for "chip". + +[WARNI:PA0205] t_sv_cpu_code/pad_vdd.sv:12 No timescale set for "pad_vdd". + +[WARNI:PA0205] t_sv_cpu_code/ac_dig.sv:8 No timescale set for "ac_dig". + +[WARNI:PA0205] t_sv_cpu_code/pad_gnd.sv:12 No timescale set for "pad_gnd". + +[WARNI:PA0205] t_sv_cpu_code/pad_gpio.sv:12 No timescale set for "pad_gpio". + +[WARNI:PA0205] t_sv_cpu_code/cpu.sv:8 No timescale set for "cpu". + +[WARNI:PA0205] t_a_first_cc.v:6 No timescale set for "t". + +[WARNI:PA0205] t_sv_cpu_code/pads.sv:8 No timescale set for "pads". + +[WARNI:PA0205] t_sv_cpu_code/pads_if.sv:9 No timescale set for "pads_if". + +[WARNI:PA0205] t_sv_cpu_code/ports.sv:9 No timescale set for "ports". + +[WARNI:PA0205] t_EXAMPLE.v:78 No timescale set for "Test". + +[WARNI:PA0205] t_array_query.v:29 No timescale set for "array_test". + +[WARNI:PA0205] t_array_rev.v:42 No timescale set for "arr_rev". + +[WARNI:PA0205] t_array_list_bad.v:6 No timescale set for "pkg". + +[WARNI:PA0205] t_bench_mux4k.v:89 No timescale set for "mux4096". + +[WARNI:PA0205] t_bench_mux4k.v:103 No timescale set for "mux4096_1bit". + +[WARNI:PA0205] t_bench_mux4k.v:139 No timescale set for "mux64". + +[WARNI:PA0205] t_bench_mux4k.v:171 No timescale set for "drv". + +[WARNI:PA0205] t_case_huge_sub.v:6 No timescale set for "t_case_huge_sub". + +[WARNI:PA0205] t_bind.v:37 No timescale set for "InstModule". + +[WARNI:PA0205] t_bind.v:44 No timescale set for "Prog". + +[WARNI:PA0205] t_bind.v:48 No timescale set for "ExampInst". + +[WARNI:PA0205] t_bind.v:75 No timescale set for "Prog2". + +[WARNI:PA0205] t_bitsel_enum.v:6 No timescale set for "t_bitsel_enum". + +[WARNI:PA0205] t_case_reducer.v:120 No timescale set for "clz". + +[WARNI:PA0205] t_case_huge_sub2.v:6 No timescale set for "t_case_huge_sub2". + +[WARNI:PA0205] t_case_huge_sub4.v:6 No timescale set for "t_case_huge_sub4". + +[WARNI:PA0205] t_case_inside.v:45 No timescale set for "sub". + +[WARNI:PA0205] t_case_itemwidth.v:91 No timescale set for "test". + +[WARNI:PA0205] t_clk_concat4.v:7 No timescale set for "some_module". + +[WARNI:PA0205] t_clk_concat4.v:30 No timescale set for "t1". + +[WARNI:PA0205] t_clk_concat4.v:48 No timescale set for "t2". + +[WARNI:PA0205] t_clk_concat6.v:49 No timescale set for "ident". + +[WARNI:PA0205] t_clk_condflop_nord.v:69 No timescale set for "condff". + +[WARNI:PA0205] t_clk_condflop_nord.v:82 No timescale set for "condffimp". + +[WARNI:PA0205] t_clk_condflop_nord.v:104 No timescale set for "clockgate". + +[WARNI:PA0205] t_clk_dsp.v:78 No timescale set for "t_dspchip". + +[WARNI:PA0205] t_clk_dsp.v:119 No timescale set for "t_dspcore". + +[WARNI:PA0205] t_clk_dsp.v:145 No timescale set for "t_dsppla". + +[WARNI:PA0205] t_clk_scope_bad.v:26 No timescale set for "flop". + +[WARNI:PA0205] t_const_dec_mixed_bad.v:6 No timescale set for "MODULE NAME UNKNOWN". + +[WARNI:PA0205] t_cover_toggle.v:86 No timescale set for "alpha". + +[WARNI:PA0205] t_cover_toggle.v:125 No timescale set for "beta". + +[WARNI:PA0205] t_cover_toggle.v:142 No timescale set for "off". + +[WARNI:PA0205] t_dedupe_seq_logic.v:35 No timescale set for "l". + +[WARNI:PA0205] t_dedupe_seq_logic.v:44 No timescale set for "ll". + +[WARNI:PA0205] t_dedupe_seq_logic.v:53 No timescale set for "lll". + +[WARNI:PA0205] t_dedupe_seq_logic.v:59 No timescale set for "llr". + +[WARNI:PA0205] t_dedupe_seq_logic.v:65 No timescale set for "lr". + +[WARNI:PA0205] t_dedupe_seq_logic.v:71 No timescale set for "r". + +[WARNI:PA0205] t_dedupe_seq_logic.v:80 No timescale set for "rr". + +[WARNI:PA0205] t_dedupe_seq_logic.v:86 No timescale set for "rl". + +[WARNI:PA0205] t_dedupe_seq_logic.v:95 No timescale set for "rll". + +[WARNI:PA0205] t_dedupe_seq_logic.v:101 No timescale set for "rlr". + +[WARNI:PA0205] t_dedupe_seq_logic.v:107 No timescale set for "add". + +[WARNI:PA0205] t_dedupe_seq_logic.v:116 No timescale set for "add2". + +[WARNI:PA0205] verilated.v:2 No timescale set for "t_case_write2_tasks". + +[WARNI:PA0205] verilated.v:2 No timescale set for "t_case_write1_tasks". + +[WARNI:PA0205] t_extend_class.v:33 No timescale set for "t_extend_class_v". + +[WARNI:PA0205] t_flag_topmodule.v:6 No timescale set for "a". + +[WARNI:PA0205] t_flag_topmodule.v:14 No timescale set for "a2". + +[WARNI:PA0205] t_flag_topmodule.v:21 No timescale set for "b". + +[WARNI:PA0205] t_flag_topmodule.v:25 No timescale set for "c". + +[WARNI:PA0205] t_flag_topmodule.v:32 No timescale set for "d". + +[WARNI:PA0205] t_func_const2_bad.v:17 No timescale set for "c9". + +[WARNI:PA0205] t_func_const2_bad.v:25 No timescale set for "b8". + +[WARNI:PA0205] t_func_regfirst.v:49 No timescale set for "f6". + +[WARNI:PA0205] t_func_wide.v:30 No timescale set for "muxtop". + +[WARNI:PA0205] t_gate_elim.v:66 No timescale set for "ta". + +[WARNI:PA0205] t_gate_elim.v:76 No timescale set for "tb". + +[WARNI:PA0205] t_gate_elim.v:86 No timescale set for "tc". + +[WARNI:PA0205] t_gate_elim.v:96 No timescale set for "td". + +[WARNI:PA0205] t_gate_elim.v:106 No timescale set for "te". + +[WARNI:PA0205] t_func_dotted.v:66 No timescale set for "global_mod". + +[WARNI:PA0205] t_func_dotted.v:76 No timescale set for "ma". + +[WARNI:PA0205] t_func_dotted.v:91 No timescale set for "mb". + +[WARNI:PA0205] t_func_dotted.v:119 No timescale set for "mc". + +[WARNI:PA0205] t_array_interface.v:6 No timescale set for "intf". + +[WARNI:PA0205] t_array_interface.v:12 No timescale set for "modify_interface". + +[WARNI:PA0205] t_gen_cond_const.v:45 No timescale set for "test_gen". + +[WARNI:PA0205] t_func_paramed.v:53 No timescale set for "extractor". + +[WARNI:PA0205] t_func_v.v:13 No timescale set for "level1". + +[WARNI:PA0205] t_func_v.v:23 No timescale set for "level2". + +[WARNI:PA0205] t_gen_for.v:54 No timescale set for "gencase". + +[WARNI:PA0205] t_gen_for.v:74 No timescale set for "paramed". + +[WARNI:PA0205] t_gen_for.v:129 No timescale set for "mbuf". + +[WARNI:PA0205] t_gen_for.v:136 No timescale set for "enflop". + +[WARNI:PA0205] t_gen_for.v:162 No timescale set for "enflop_one". + +[WARNI:PA0205] t_gate_implicit.v:78 No timescale set for "Mxor". + +[WARNI:PA0205] t_gen_intdot.v:45 No timescale set for "Generate". + +[WARNI:PA0205] t_gen_intdot.v:58 No timescale set for "Checker". + +[WARNI:PA0205] t_gen_intdot.v:77 No timescale set for "Genit". + +[WARNI:PA0205] t_gen_upscope.v:78 No timescale set for "tag". + +[WARNI:PA0205] t_gen_for1.v:42 No timescale set for "Testit". + +[WARNI:PA0205] t_gen_for1.v:68 No timescale set for "fnxtclk". + +[WARNI:PA0205] t_inst_darray.v:9 No timescale set for "the_intf". + +[WARNI:PA0205] t_inst_darray.v:26 No timescale set for "Contemplator". + +[WARNI:PA0205] t_inst_darray.v:44 No timescale set for "DeepThought". + +[WARNI:PA0205] t_inst_first_b.v:6 No timescale set for "t_inst_first_b". + +[WARNI:PA0205] t_inst_misarray_bad.v:20 No timescale set for "dut". + +[WARNI:PA0205] t_inst_misarray_bad.v:33 No timescale set for "suba". + +[WARNI:PA0205] t_inst_prepost.v:31 No timescale set for "ip". + +[WARNI:PA0205] t_for_funcbound.v:53 No timescale set for "strings". + +[WARNI:PA0205] t_inst_v2k.v:62 No timescale set for "hello". + +[WARNI:PA0205] t_interface1.v:8 No timescale set for "ifc". + +[WARNI:PA0205] t_func_check.v:33 No timescale set for "chk". + +[WARNI:PA0205] t_func_const3_bad.v:15 No timescale set for "b9". + +[WARNI:PA0205] t_interface_array.v:6 No timescale set for "foo_intf". + +[WARNI:PA0205] t_interface_array_nocolon_bad.v:12 No timescale set for "foo_subm". + +[WARNI:PA0205] t_interface_down.v:44 No timescale set for "wrapper". + +[WARNI:PA0205] t_interface_down.v:55 No timescale set for "lower". + +[WARNI:PA0205] t_interface_dups.v:88 No timescale set for "dti". + +[WARNI:PA0205] t_interface_missing_bad.v:11 No timescale set for "foo_mod". + +[WARNI:PA0205] t_gen_forif.v:67 No timescale set for "Test_wrap1". + +[WARNI:PA0205] t_gen_forif.v:75 No timescale set for "Test_wrap2". + +[WARNI:PA0205] t_interface_modport_import.v:8 No timescale set for "test_if". + +[WARNI:PA0205] t_interface_modport_import.v:42 No timescale set for "testmod". + +[WARNI:PA0205] t_interface_param1.v:21 No timescale set for "sub_test". + +[WARNI:PA0205] t_interface_param_another_bad.v:15 No timescale set for "simple_bus". + +[WARNI:PA0205] t_interface_size_bad.v:20 No timescale set for "baz". + +[WARNI:PA0205] t_func_grey.v:48 No timescale set for "t_func_grey2bin". + +[WARNI:PA0205] t_func_outp.v:48 No timescale set for "inv". + +[WARNI:PA0205] t_func_outp.v:56 No timescale set for "ftest". + +[WARNI:PA0205] t_func_outp.v:84 No timescale set for "mytop". + +[WARNI:PA0205] t_gen_intdot2.v:38 No timescale set for "One". + +[WARNI:PA0205] t_func_public.v:33 No timescale set for "tpub". + +[WARNI:PA0205] t_genfor_hier.v:7 No timescale set for "m1". + +[WARNI:PA0205] t_genvar_misuse_bad.v:7 No timescale set for "top". + +[WARNI:PA0205] t_lint_implicit_port.v:20 No timescale set for "set". + +[WARNI:PA0205] t_lint_implicit_port.v:27 No timescale set for "read". + +[WARNI:PA0205] t_gen_defparam.v:40 No timescale set for "m2". + +[WARNI:PA0205] t_lint_unused_iface_bad.v:6 No timescale set for "dummy_if". + +[WARNI:PA0205] t_gen_for_overlap.v:35 No timescale set for "sub1". + +[WARNI:PA0205] t_gen_for_overlap.v:40 No timescale set for "sub2". + +[WARNI:PA0205] t_gen_index.v:41 No timescale set for "foo". + +[WARNI:PA0205] t_gen_index.v:62 No timescale set for "bar". + +[WARNI:PA0205] t_inst_dff.v:109 No timescale set for "dff". + +[WARNI:PA0205] t_inst_notunsized.v:93 No timescale set for "Muxer". + +[WARNI:PA0205] t_inst_sv.v:61 No timescale set for "t_inst". + +[WARNI:PA0205] t_inst_wideconst.v:59 No timescale set for "wide". + +[WARNI:PA0205] t_gen_missing.v:12 No timescale set for "foobar". + +[WARNI:PA0205] t_gen_missing.v:45 No timescale set for "foo0". + +[WARNI:PA0205] t_interface_arraymux.v:32 No timescale set for "ThingMuxOH". + +[WARNI:PA0205] t_interface_arraymux.v:43 No timescale set for "Thinker". + +[WARNI:PA0205] t_interface_modport_bad.v:20 No timescale set for "counter_ansi". + +[WARNI:PA0205] t_interface_modportlist.v:13 No timescale set for "my_module". + +[WARNI:PA0205] t_interface_modportlist.v:20 No timescale set for "my_interface". + +[WARNI:PA0205] t_interface_param2.v:37 No timescale set for "mem". + +[WARNI:PA0205] t_interface_star.v:30 No timescale set for "counter_io". + +[WARNI:PA0205] t_interface_wrong_bad.v:11 No timescale set for "bar_intf". + +[WARNI:PA0205] t_lint_blksync_loop.v:44 No timescale set for "reg_1r1w". + +[WARNI:PA0205] t_lint_importstar_bad.v:6 No timescale set for "defs". + +[WARNI:PA0205] t_bind2.v:50 No timescale set for "targetmod". + +[WARNI:PA0205] t_bind2.v:66 No timescale set for "mycheck". + +[WARNI:PA0205] t_init_concat.v:59 No timescale set for "regfile". + +[WARNI:PA0205] t_case_huge_sub3.v:6 No timescale set for "t_case_huge_sub3". + +[WARNI:PA0205] t_inst_dtree.v:19 No timescale set for "bmod". + +[WARNI:PA0205] t_inst_dtree.v:28 No timescale set for "cmod". + +[WARNI:PA0205] t_inst_dtree.v:38 No timescale set for "dmod". + +[WARNI:PA0205] t_inst_first_a.v:6 No timescale set for "t_inst_first_a". + +[WARNI:PA0205] t_inst_implicit.v:30 No timescale set for "subimp". + +[WARNI:PA0205] t_inst_mnpipe.v:42 No timescale set for "dffn". + +[WARNI:PA0205] t_inst_mnpipe.v:55 No timescale set for "MxN_pipeline". + +[WARNI:PA0205] t_inst_recurse2_bad.v:17 No timescale set for "looped". + +[WARNI:PA0205] t_inst_recurse_bad.v:21 No timescale set for "looped2". + +[WARNI:PA0205] t_math_imm.v:73 No timescale set for "example". + +[WARNI:PA0205] t_interface.v:70 No timescale set for "handshake". + +[WARNI:PA0205] t_interface.v:109 No timescale set for "source". + +[WARNI:PA0205] t_interface.v:141 No timescale set for "drain". + +[WARNI:PA0205] t_interface_gen12.v:8 No timescale set for "foo_module". + +[WARNI:PA0205] t_interface_gen12.v:16 No timescale set for "bar_module". + +[WARNI:PA0205] t_math_vliw.v:58 No timescale set for "vliw". + +[WARNI:PA0205] t_interface_modport_export.v:45 No timescale set for "testmod_callee". + +[WARNI:PA0205] t_interface_modport_export.v:58 No timescale set for "testmod_caller". + +[WARNI:PA0205] t_interface_nest.v:6 No timescale set for "if1". + +[WARNI:PA0205] t_interface_nest.v:10 No timescale set for "if2". + +[WARNI:PA0205] t_interface_nest.v:15 No timescale set for "mod1". + +[WARNI:PA0205] t_cdc_async_bad.v:66 No timescale set for "Flop". + +[WARNI:PA0205] t_cdc_async_bad.v:78 No timescale set for "Sub". + +[WARNI:PA0205] t_langext_order_sub.v:10 No timescale set for "t_langext_order_sub". + +[WARNI:PA0205] t_lint_always_comb_iface.v:6 No timescale set for "my_if". + +[WARNI:PA0205] t_lint_always_comb_iface.v:54 No timescale set for "my_module1". + +[WARNI:PA0205] t_lint_always_comb_iface.v:68 No timescale set for "my_module2". + +[WARNI:PA0205] t_lint_always_comb_iface.v:84 No timescale set for "my_module3". + +[WARNI:PA0205] t_cellarray.v:66 No timescale set for "drv1". + +[WARNI:PA0205] t_cellarray.v:73 No timescale set for "drv2". + +[WARNI:PA0205] t_cellarray.v:81 No timescale set for "drv3". + +[WARNI:PA0205] t_cellarray.v:91 No timescale set for "drv4". + +[WARNI:PA0205] t_chg_first.v:61 No timescale set for "t_chg_a". + +[WARNI:PA0205] t_lint_unused.v:51 No timescale set for "udp_mux2". + +[WARNI:PA0205] t_mem_iforder.v:58 No timescale set for "fifo". + +[WARNI:PA0205] t_lint_width_bad.v:35 No timescale set for "p". + +[WARNI:PA0205] t_math_cmp.v:71 No timescale set for "prover". + +[WARNI:PA0205] t_clk_first.v:30 No timescale set for "t_clk". + +[WARNI:PA0205] t_clk_first.v:133 No timescale set for "t_clk_flop". + +[WARNI:PA0205] t_clk_first.v:151 No timescale set for "t_clk_two". + +[WARNI:PA0205] t_clk_first.v:175 No timescale set for "t_clk_twob". + +[WARNI:PA0205] t_math_signed.v:164 No timescale set for "by_width". + +[WARNI:PA0205] t_clk_latchgate.v:97 No timescale set for "llq". + +[WARNI:PA0205] t_clk_latchgate.v:116 No timescale set for "ffq". + +[WARNI:PA0205] t_mod_interface_array.v:8 No timescale set for "a_if". + +[WARNI:PA0205] t_mod_interface_array.v:14 No timescale set for "intf_source". + +[WARNI:PA0205] t_mod_interface_array.v:26 No timescale set for "intf_sink". + +[WARNI:PA0205] t_mod_longname.v:28 No timescale set for "modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie". + +[WARNI:PA0205] t_cover_line.v:114 No timescale set for "tsk". + +[WARNI:PA0205] t_mem_file.v:76 No timescale set for "file". + +[WARNI:PA0205] t_dedupe_clk_gate.v:20 No timescale set for "flop_gated_latch". + +[WARNI:PA0205] t_dedupe_clk_gate.v:30 No timescale set for "flop_gated_flop". + +[WARNI:PA0205] t_dedupe_clk_gate.v:40 No timescale set for "clock_gate_latch". + +[WARNI:PA0205] t_dedupe_clk_gate.v:52 No timescale set for "clock_gate_flop". + +[WARNI:PA0205] t_package_abs.v:8 No timescale set for "functions". + +[WARNI:PA0205] t_package_twodeep.v:8 No timescale set for "pkg2". + +[WARNI:PA0205] t_package_twodeep.v:12 No timescale set for "pkg1". + +[WARNI:PA0205] t_mem_slot.v:7 No timescale set for "t_mem_slot". + +[WARNI:PA0205] t_mod_recurse1.v:12 No timescale set for "rec". + +[WARNI:PA0205] t_mod_recurse1.v:28 No timescale set for "bottom". + +[WARNI:PA0205] t_order_b.v:6 No timescale set for "t_order_b". + +[WARNI:PA0205] t_order_clkinst.v:61 No timescale set for "comb_loop". + +[WARNI:PA0205] t_order_clkinst.v:90 No timescale set for "seq_loop". + +[WARNI:PA0205] t_param_array.v:78 No timescale set for "checkstr". + +[WARNI:PA0205] t_param_default_bad.v:6 No timescale set for "m". + +[WARNI:PA0205] t_param_first_b.v:6 No timescale set for "t_param_first_b". + +[WARNI:PA0205] t_order_multidriven.v:61 No timescale set for "FooWr". + +[WARNI:PA0205] t_order_multidriven.v:86 No timescale set for "FooRd". + +[WARNI:PA0205] t_order_multidriven.v:125 No timescale set for "FooMem". + +[WARNI:PA0205] t_order_multidriven.v:151 No timescale set for "FooMemImpl". + +[WARNI:PA0205] t_param_package.v:12 No timescale set for "params". + +[WARNI:PA0205] t_param_package.v:16 No timescale set for "Test0". + +[WARNI:PA0205] t_param_package.v:21 No timescale set for "Test1". + +[WARNI:PA0205] t_param_real.v:6 No timescale set for "mod". + +[WARNI:PA0205] t_dpi_accessors.v:50 No timescale set for "test_sub". + +[WARNI:PA0205] t_param_if_blk.v:71 No timescale set for "Nested". + +[WARNI:PA0205] t_param_named.v:29 No timescale set for "m3". + +[WARNI:PA0205] t_param_no_parentheses.v:66 No timescale set for "mnooverride". + +[WARNI:PA0205] t_mem_multi_io3.v:34 No timescale set for "testio". + +[WARNI:PA0205] t_mod_recurse.v:62 No timescale set for "PriorityChoice". + +[WARNI:PA0205] t_param_type.v:54 No timescale set for "mod_typ". + +[WARNI:PA0205] t_order_a.v:6 No timescale set for "t_order_a". + +[WARNI:PA0205] t_order_first.v:20 No timescale set for "t_netlist". + +[WARNI:PA0205] t_pp_lib_library.v:6 No timescale set for "library_cell". + +[WARNI:PA0205] t_package.v:20 No timescale set for "p2". + +[WARNI:PA0205] t_reloop_cam.v:95 No timescale set for "cam". + +[WARNI:PA0205] t_preproc_kwd.v:28 No timescale set for "v95". + +[WARNI:PA0205] t_preproc_kwd.v:34 No timescale set for "v01". + +[WARNI:PA0205] t_preproc_kwd.v:40 No timescale set for "v05". + +[WARNI:PA0205] t_preproc_kwd.v:46 No timescale set for "s05". + +[WARNI:PA0205] t_preproc_kwd.v:52 No timescale set for "s09". + +[WARNI:PA0205] t_preproc_kwd.v:58 No timescale set for "s12". + +[WARNI:PA0205] t_preproc_kwd.v:66 No timescale set for "s17". + +[WARNI:PA0205] t_preproc_kwd.v:74 No timescale set for "a23". + +[WARNI:PA0205] t_param_ddeep_width.v:13 No timescale set for "paramtest_WRAP". + +[WARNI:PA0205] t_param_ddeep_width.v:20 No timescale set for "paramtest_DFFRE". + +[WARNI:PA0205] t_param_first_a.v:6 No timescale set for "t_param_first_a". + +[WARNI:PA0205] t_embed1_child.v:6 No timescale set for "t_embed1_child". + +[WARNI:PA0205] t_embed1_wrap.v:6 No timescale set for "t_embed1_wrap". + +[WARNI:PA0205] t_param_mem_attr.v:34 No timescale set for "memory". + +[WARNI:PA0205] t_enum_name2.v:6 No timescale set for "our_pkg". + +[WARNI:PA0205] t_enum_name2.v:19 No timescale set for "our". + +[WARNI:PA0205] t_enum_public.v:6 No timescale set for "p3". + +[WARNI:PA0205] t_enum_public.v:12 No timescale set for "p62". + +[WARNI:PA0205] t_param_sel_range.v:15 No timescale set for "submod". + +[WARNI:PA0205] t_param_type2.v:6 No timescale set for "tt_pkg". + +[WARNI:PA0205] t_param_type2.v:31 No timescale set for "tt_buf". + +[WARNI:PA0205] t_param_up_bad.v:12 No timescale set for "child". + +[WARNI:PA0205] t_param_up_bad.v:18 No timescale set for "parent". + +[WARNI:PA0205] t_past.v:84 No timescale set for "Test2". + +[WARNI:PA0205] t_struct_param.v:7 No timescale set for "config_pkg". + +[WARNI:PA0205] t_struct_param.v:40 No timescale set for "struct_submodule". + +[WARNI:PA0205] t_struct_unpacked.v:6 No timescale set for "x". + +[WARNI:PA0205] t_tri_array_pull.v:6 No timescale set for "IOBUF". + +[WARNI:PA0205] t_struct_array.v:6 No timescale set for "TEST_TYPES". + +[WARNI:PA0205] t_sv_conditional.v:62 No timescale set for "st3_testbench". + +[WARNI:PA0205] t_sv_conditional.v:145 No timescale set for "simple_test_3". + +[WARNI:PA0205] t_sv_conditional.v:230 No timescale set for "counterA". + +[WARNI:PA0205] t_sv_conditional.v:277 No timescale set for "counterB". + +[WARNI:PA0205] t_sv_conditional.v:311 No timescale set for "simple_test_3a". + +[WARNI:PA0205] t_sv_conditional.v:331 No timescale set for "simple_test_3b". + +[WARNI:PA0205] t_sv_conditional.v:363 No timescale set for "simple_test_3c". + +[WARNI:PA0205] t_sv_conditional.v:395 No timescale set for "simple_test_3d". + +[WARNI:PA0205] t_sv_conditional.v:425 No timescale set for "simple_test_3e". + +[WARNI:PA0205] t_sv_conditional.v:449 No timescale set for "simple_test_3f". + +[WARNI:PA0205] t_trace_primitive.v:31 No timescale set for "CINV". + +[WARNI:PA0205] t_sv_cpu.v:79 No timescale set for "testbench". + +[WARNI:PA0205] t_type_param.v:15 No timescale set for "foo_wrapper". + +[WARNI:PA0205] t_typedef_port.v:78 No timescale set for "TestNonAnsi". + +[WARNI:PA0205] t_typedef_port.v:95 No timescale set for "TestAnsi". + +[WARNI:PA0205] t_trace_param.v:6 No timescale set for "my_funcs". + +[WARNI:PA0205] t_trace_param.v:14 No timescale set for "my_module_types". + +[WARNI:PA0205] t_tri_gen.v:27 No timescale set for "updown". + +[WARNI:PA0205] t_tri_gen.v:39 No timescale set for "t_up". + +[WARNI:PA0205] t_tri_gen.v:42 No timescale set for "t_down". + +[WARNI:PA0205] t_tri_array.v:65 No timescale set for "Pad". + +[WARNI:PA0205] t_var_dup_bad.v:46 No timescale set for "sub0". + +[WARNI:PA0205] t_var_dup_bad.v:68 No timescale set for "sub3". + +[WARNI:PA0205] t_tri_public.v:47 No timescale set for "sub_mod". + +[WARNI:PA0205] t_tri_select.v:35 No timescale set for "io_ring". + +[WARNI:PA0205] t_tri_select.v:39 No timescale set for "io". + +[WARNI:PA0205] t_tri_gate.v:15 No timescale set for "pass". + +[WARNI:PA0205] t_tri_gate.v:20 No timescale set for "tbuf". + +[WARNI:PA0205] t_tri_gate.v:24 No timescale set for "mux". + +[WARNI:PA0205] t_var_port_bad.v:11 No timescale set for "subok". + +[WARNI:PA0205] t_tri_pull01.v:71 No timescale set for "t_tri2". + +[WARNI:PA0205] t_tri_pull01.v:84 No timescale set for "t_tri3". + +[WARNI:PA0205] t_tri_various.v:146 No timescale set for "Test3". + +[WARNI:PA0205] t_tri_various.v:154 No timescale set for "Test4". + +[WARNI:PA0205] t_tri_various.v:159 No timescale set for "Test5". + +[WARNI:PA0205] t_tri_various.v:167 No timescale set for "Test6". + +[WARNI:PA0205] t_tri_various.v:173 No timescale set for "Test6a". + +[WARNI:PA0205] t_tri_various.v:177 No timescale set for "Test7". + +[WARNI:PA0205] t_vpi_var.v:87 No timescale set for "arr". + +[WARNI:PA0205] t_udp_noname.v:35 No timescale set for "udp". + +[WARNI:PA0205] t_unoptflat_simple_3.v:41 No timescale set for "test1". + +[WARNI:PA0205] t_unoptflat_simple_3.v:60 No timescale set for "test2". + +[WARNI:PA0205] t_udp.v:115 No timescale set for "udp_latch". + +[WARNI:PA0205] t_udp.v:126 No timescale set for "udp_dff". + +[WARNI:PA0205] t_final.v:6 No timescale set for "submodule". + +[WARNI:PA0205] t_vams_wreal.v:87 No timescale set for "through". + +[WARNI:PA0205] t_vams_wreal.v:93 No timescale set for "within_range". + +[WARNI:PA0205] t_vams_wreal.v:106 No timescale set for "wreal_bus". + +[WARNI:PA0205] t_vams_wreal.v:114 No timescale set for "first_level". + +[WARNI:PA0205] t_vams_wreal.v:121 No timescale set for "second_level". + +[WARNI:PA0205] t_var_overzero.v:33 No timescale set for "tsub". + +[WARNI:PA0205] t_flag_libinc.v:6 No timescale set for "liblib_a". + +[WARNI:PA0205] t_flag_libinc.v:10 No timescale set for "liblib_b". + +[WARNI:PA0205] t_flag_libinc.v:17 No timescale set for "liblib_c". + +[WARNI:PA0205] t_flag_libinc.v:23 No timescale set for "liblib_d". + +[WARNI:PA0205] t_flag_topmod2_bad.v:6 No timescale set for "a_top". + +[WARNI:PA0205] t_flag_topmodule_inline.v:22 No timescale set for "l3". + +[WARNI:PA0205] t_func_begin2.v:6 No timescale set for "init". + +[WARNI:PA0205] t_var_in_assign.v:59 No timescale set for "z". + +[WARNI:PA0205] t_func_const.v:6 No timescale set for "testpackage". + +[WARNI:PA0205] t_xml_first.v:44 No timescale set for "mod2". + +[WARNI:PA0205] t_func_lib_sub.v:7 No timescale set for "BreadAddrDP". + +[WARNI:PA0205] t_func_lib_sub.v:56 No timescale set for "DecCountReg4". + +[WARNI:PA0205] t_gate_fdup.v:6 No timescale set for "fnor2". + +[WARNI:PA0205] t_generate_fatal_bad.v:15 No timescale set for "foo2". + +[WARNI:PA0205] t_inst_aport.v:65 No timescale set for "callee". + +[WARNI:PA0205] t_inst_tree.v:63 No timescale set for "ps". + +[WARNI:PA0205] t_inst_tree.v:69 No timescale set for "l1". + +[WARNI:PA0205] t_inst_tree.v:76 No timescale set for "l2". + +[WARNI:PA0205] t_inst_tree.v:92 No timescale set for "l4". + +[WARNI:PA0205] t_inst_tree.v:100 No timescale set for "l5". + +[WARNI:PA0205] t_interface2.v:72 No timescale set for "ifunused". + +[WARNI:PA0205] t_interface2.v:93 No timescale set for "counter_nansi". + +[WARNI:PA0205] t_interface2.v:104 No timescale set for "modunused". + +[WARNI:PA0205] t_interface_bind_public.v:6 No timescale set for "hex2ram_if". + +[WARNI:PA0205] t_interface_bind_public.v:69 No timescale set for "testharness_ext". + +[WARNI:PA0205] t_interface_bind_public.v:100 No timescale set for "SimpleTestHarness". + +[WARNI:PA0205] t_interface_modport.v:6 No timescale set for "counter_if". + +[WARNI:PA0205] t_interface_modport.v:103 No timescale set for "counter_ansi_m". + +[WARNI:PA0205] t_interface_modport.v:116 No timescale set for "counter_nansi_m". + +[WARNI:PA0205] t_lint_declfilename.v:10 No timescale set for "t_lint_declfilename". + +[WARNI:PA0205] t_math_imm2.v:13 No timescale set for "t_math_imm2". + +[WARNI:PA0205] t_math_pow4.v:43 No timescale set for "test004". + +[WARNI:PA0205] t_math_real.v:141 No timescale set for "sub_cast_bug374". + +[WARNI:PA0205] t_mem_multi_io.v:39 No timescale set for "has_array". + +[WARNI:PA0205] t_mem_multiwire.v:53 No timescale set for "inst". + +[WARNI:PA0205] t_mem_multiwire.v:75 No timescale set for "inst2". + +[WARNI:PA0205] t_mem_slice_conc_bad.v:68 No timescale set for "bbb". + +[WARNI:PA0205] t_mem_slice_conc_bad.v:101 No timescale set for "aaa". + +[WARNI:PA0205] t_multitop1s.v:6 No timescale set for "t_multitop1s". + +[WARNI:PA0205] t_multitop1s.v:10 No timescale set for "in_subfile". + +[WARNI:PA0205] t_package_dot.v:13 No timescale set for "csr_pkg". + +[WARNI:PA0205] t_package_export.v:14 No timescale set for "pkg10". + +[WARNI:PA0205] t_package_export.v:19 No timescale set for "pkg11". + +[WARNI:PA0205] t_package_export.v:23 No timescale set for "pkg20". + +[WARNI:PA0205] t_package_export.v:27 No timescale set for "pkg21". + +[WARNI:PA0205] t_package_export.v:31 No timescale set for "pkg30". + +[WARNI:PA0205] t_package_export.v:35 No timescale set for "pkg31". + +[WARNI:PA0205] t_package_verb.v:7 No timescale set for "verb_pkg". + +[WARNI:PA0205] t_param_long.v:94 No timescale set for "i". + +[WARNI:PA0205] t_preproc_inc_inc_bad.vh:6 No timescale set for "xx". + +[WARNI:PA0205] t_trace_public.v:32 No timescale set for "glbl". + +[WARNI:PA0205] t_trace_public.v:36 No timescale set for "neg". + +[WARNI:PA0205] t_trace_public.v:51 No timescale set for "little". + +[WARNI:PA0205] t_tri_inout2.v:59 No timescale set for "ChildA". + +[WARNI:PA0205] t_tri_inout2.v:73 No timescale set for "ChildB". + +[WARNI:PA0205] t_tri_pullup.v:24 No timescale set for "pullup_module". + +[WARNI:PA0205] t_tri_unconn.v:78 No timescale set for "t_tri0". + +[WARNI:PA0205] t_tri_unconn.v:90 No timescale set for "t_tri1". + +[WARNI:PA0205] t_var_notfound_bad.v:32 No timescale set for "subsub". + +[ERROR:PA0206] t_altera_lpm.v:60 Missing timeunit/timeprecision for "LPM_MEMORY_INITIALIZATION". + +[ERROR:PA0206] t_altera_lpm.v:1265 Missing timeunit/timeprecision for "LPM_HINT_EVALUATION". + +[ERROR:PA0206] t_altera_lpm.v:1375 Missing timeunit/timeprecision for "LPM_DEVICE_FAMILIES". + +[ERROR:PA0206] t_altera_lpm.v:1585 Missing timeunit/timeprecision for "lpm_constant". + +[ERROR:PA0206] t_altera_lpm.v:1636 Missing timeunit/timeprecision for "lpm_inv". + +[ERROR:PA0206] t_altera_lpm.v:1689 Missing timeunit/timeprecision for "lpm_and". + +[ERROR:PA0206] t_altera_lpm.v:1769 Missing timeunit/timeprecision for "lpm_or". + +[ERROR:PA0206] t_altera_lpm.v:1850 Missing timeunit/timeprecision for "lpm_xor". + +[ERROR:PA0206] t_altera_lpm.v:1979 Missing timeunit/timeprecision for "lpm_bustri". + +[ERROR:PA0206] t_altera_lpm.v:2065 Missing timeunit/timeprecision for "lpm_mux". + +[ERROR:PA0206] t_altera_lpm.v:2200 Missing timeunit/timeprecision for "lpm_decode". + +[ERROR:PA0206] t_altera_lpm.v:2328 Missing timeunit/timeprecision for "lpm_clshift". + +[ERROR:PA0206] t_altera_lpm.v:2613 Missing timeunit/timeprecision for "lpm_add_sub". + +[ERROR:PA0206] t_altera_lpm.v:2819 Missing timeunit/timeprecision for "lpm_compare". + +[ERROR:PA0206] t_altera_lpm.v:2993 Missing timeunit/timeprecision for "lpm_mult". + +[ERROR:PA0206] t_altera_lpm.v:3279 Missing timeunit/timeprecision for "lpm_divide". + +[ERROR:PA0206] t_altera_lpm.v:3486 Missing timeunit/timeprecision for "lpm_abs". + +[ERROR:PA0206] t_altera_lpm.v:3550 Missing timeunit/timeprecision for "lpm_counter". + +[ERROR:PA0206] t_altera_lpm.v:3836 Missing timeunit/timeprecision for "lpm_latch". + +[ERROR:PA0206] t_altera_lpm.v:3960 Missing timeunit/timeprecision for "lpm_ff". + +[ERROR:PA0206] t_altera_lpm.v:4179 Missing timeunit/timeprecision for "lpm_shiftreg". + +[ERROR:PA0206] t_altera_lpm.v:4383 Missing timeunit/timeprecision for "lpm_ram_dq". + +[ERROR:PA0206] t_altera_lpm.v:4639 Missing timeunit/timeprecision for "lpm_ram_dp". + +[ERROR:PA0206] t_altera_lpm.v:4930 Missing timeunit/timeprecision for "lpm_ram_io". + +[ERROR:PA0206] t_altera_lpm.v:5192 Missing timeunit/timeprecision for "lpm_rom". + +[ERROR:PA0206] t_altera_lpm.v:5407 Missing timeunit/timeprecision for "lpm_fifo". + +[ERROR:PA0206] t_altera_lpm.v:5738 Missing timeunit/timeprecision for "lpm_fifo_dc_dffpipe". + +[ERROR:PA0206] t_altera_lpm.v:5825 Missing timeunit/timeprecision for "lpm_fifo_dc_fefifo". + +[ERROR:PA0206] t_altera_lpm.v:6033 Missing timeunit/timeprecision for "lpm_fifo_dc_async". + +[ERROR:PA0206] t_altera_lpm.v:6470 Missing timeunit/timeprecision for "lpm_fifo_dc". + +[ERROR:PA0206] t_altera_lpm.v:6593 Missing timeunit/timeprecision for "lpm_inpad". + +[ERROR:PA0206] t_altera_lpm.v:6649 Missing timeunit/timeprecision for "lpm_outpad". + +[ERROR:PA0206] t_altera_lpm.v:6705 Missing timeunit/timeprecision for "lpm_bipad". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:9 Missing timeunit/timeprecision for "package_bus". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:17 Missing timeunit/timeprecision for "package_str". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:22 Missing timeunit/timeprecision for "package_uni". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv:28 Missing timeunit/timeprecision for "sv_bus_mux_demux_wrap". + +[ERROR:PA0206] t_sv_cpu_code/ac.sv:8 Missing timeunit/timeprecision for "ac". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv:12 Missing timeunit/timeprecision for "sv_bus_mux_demux_mux". + +[ERROR:PA0206] t_sv_cpu_code/adrdec.sv:8 Missing timeunit/timeprecision for "adrdec". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv:11 Missing timeunit/timeprecision for "sv_bus_mux_demux_demux". + +[ERROR:PA0206] t_sv_cpu_code/genbus_if.sv:14 Missing timeunit/timeprecision for "genbus_if". + +[ERROR:PA0206] t_sv_cpu_code/ac_ana.sv:8 Missing timeunit/timeprecision for "ac_ana". + +[ERROR:PA0206] t_sv_cpu_code/chip.sv:12 Missing timeunit/timeprecision for "chip". + +[ERROR:PA0206] t_sv_cpu_code/pad_vdd.sv:12 Missing timeunit/timeprecision for "pad_vdd". + +[ERROR:PA0206] t_sv_cpu_code/ac_dig.sv:8 Missing timeunit/timeprecision for "ac_dig". + +[ERROR:PA0206] t_sv_cpu_code/pad_gnd.sv:12 Missing timeunit/timeprecision for "pad_gnd". + +[ERROR:PA0206] t_sv_cpu_code/pad_gpio.sv:12 Missing timeunit/timeprecision for "pad_gpio". + +[ERROR:PA0206] t_sv_cpu_code/cpu.sv:8 Missing timeunit/timeprecision for "cpu". + +[ERROR:PA0206] t_a_first_cc.v:6 Missing timeunit/timeprecision for "t". + +[ERROR:PA0206] t_sv_cpu_code/pads.sv:8 Missing timeunit/timeprecision for "pads". + +[ERROR:PA0206] t_sv_cpu_code/pads_if.sv:9 Missing timeunit/timeprecision for "pads_if". + +[ERROR:PA0206] t_sv_cpu_code/ports.sv:9 Missing timeunit/timeprecision for "ports". + +[ERROR:PA0206] t_EXAMPLE.v:78 Missing timeunit/timeprecision for "Test". + +[ERROR:PA0206] t_array_query.v:29 Missing timeunit/timeprecision for "array_test". + +[ERROR:PA0206] t_array_rev.v:42 Missing timeunit/timeprecision for "arr_rev". + +[ERROR:PA0206] t_array_list_bad.v:6 Missing timeunit/timeprecision for "pkg". + +[ERROR:PA0206] t_bench_mux4k.v:89 Missing timeunit/timeprecision for "mux4096". + +[ERROR:PA0206] t_bench_mux4k.v:103 Missing timeunit/timeprecision for "mux4096_1bit". + +[ERROR:PA0206] t_bench_mux4k.v:139 Missing timeunit/timeprecision for "mux64". + +[ERROR:PA0206] t_bench_mux4k.v:171 Missing timeunit/timeprecision for "drv". + +[ERROR:PA0206] t_case_huge_sub.v:6 Missing timeunit/timeprecision for "t_case_huge_sub". + +[ERROR:PA0206] t_bind.v:37 Missing timeunit/timeprecision for "InstModule". + +[ERROR:PA0206] t_bind.v:44 Missing timeunit/timeprecision for "Prog". + +[ERROR:PA0206] t_bind.v:48 Missing timeunit/timeprecision for "ExampInst". + +[ERROR:PA0206] t_bind.v:75 Missing timeunit/timeprecision for "Prog2". + +[ERROR:PA0206] t_bitsel_enum.v:6 Missing timeunit/timeprecision for "t_bitsel_enum". + +[ERROR:PA0206] t_case_reducer.v:120 Missing timeunit/timeprecision for "clz". + +[ERROR:PA0206] t_case_huge_sub2.v:6 Missing timeunit/timeprecision for "t_case_huge_sub2". + +[ERROR:PA0206] t_case_huge_sub4.v:6 Missing timeunit/timeprecision for "t_case_huge_sub4". + +[ERROR:PA0206] t_case_inside.v:45 Missing timeunit/timeprecision for "sub". + +[ERROR:PA0206] t_case_itemwidth.v:91 Missing timeunit/timeprecision for "test". + +[ERROR:PA0206] t_clk_concat4.v:7 Missing timeunit/timeprecision for "some_module". + +[ERROR:PA0206] t_clk_concat4.v:30 Missing timeunit/timeprecision for "t1". + +[ERROR:PA0206] t_clk_concat4.v:48 Missing timeunit/timeprecision for "t2". + +[ERROR:PA0206] t_clk_concat6.v:49 Missing timeunit/timeprecision for "ident". + +[ERROR:PA0206] t_clk_condflop_nord.v:69 Missing timeunit/timeprecision for "condff". + +[ERROR:PA0206] t_clk_condflop_nord.v:82 Missing timeunit/timeprecision for "condffimp". + +[ERROR:PA0206] t_clk_condflop_nord.v:104 Missing timeunit/timeprecision for "clockgate". + +[ERROR:PA0206] t_clk_dsp.v:78 Missing timeunit/timeprecision for "t_dspchip". + +[ERROR:PA0206] t_clk_dsp.v:119 Missing timeunit/timeprecision for "t_dspcore". + +[ERROR:PA0206] t_clk_dsp.v:145 Missing timeunit/timeprecision for "t_dsppla". + +[ERROR:PA0206] t_clk_scope_bad.v:26 Missing timeunit/timeprecision for "flop". + +[ERROR:PA0206] t_const_dec_mixed_bad.v:6 Missing timeunit/timeprecision for "MODULE NAME UNKNOWN". + +[ERROR:PA0206] t_cover_toggle.v:86 Missing timeunit/timeprecision for "alpha". + +[ERROR:PA0206] t_cover_toggle.v:125 Missing timeunit/timeprecision for "beta". + +[ERROR:PA0206] t_cover_toggle.v:142 Missing timeunit/timeprecision for "off". + +[ERROR:PA0206] t_dedupe_seq_logic.v:35 Missing timeunit/timeprecision for "l". + +[ERROR:PA0206] t_dedupe_seq_logic.v:44 Missing timeunit/timeprecision for "ll". + +[ERROR:PA0206] t_dedupe_seq_logic.v:53 Missing timeunit/timeprecision for "lll". + +[ERROR:PA0206] t_dedupe_seq_logic.v:59 Missing timeunit/timeprecision for "llr". + +[ERROR:PA0206] t_dedupe_seq_logic.v:65 Missing timeunit/timeprecision for "lr". + +[ERROR:PA0206] t_dedupe_seq_logic.v:71 Missing timeunit/timeprecision for "r". + +[ERROR:PA0206] t_dedupe_seq_logic.v:80 Missing timeunit/timeprecision for "rr". + +[ERROR:PA0206] t_dedupe_seq_logic.v:86 Missing timeunit/timeprecision for "rl". + +[ERROR:PA0206] t_dedupe_seq_logic.v:95 Missing timeunit/timeprecision for "rll". + +[ERROR:PA0206] t_dedupe_seq_logic.v:101 Missing timeunit/timeprecision for "rlr". + +[ERROR:PA0206] t_dedupe_seq_logic.v:107 Missing timeunit/timeprecision for "add". + +[ERROR:PA0206] t_dedupe_seq_logic.v:116 Missing timeunit/timeprecision for "add2". + +[ERROR:PA0206] verilated.v:2 Missing timeunit/timeprecision for "t_case_write2_tasks". + +[ERROR:PA0206] verilated.v:2 Missing timeunit/timeprecision for "t_case_write1_tasks". + +[ERROR:PA0206] t_extend_class.v:33 Missing timeunit/timeprecision for "t_extend_class_v". + +[ERROR:PA0206] t_flag_topmodule.v:6 Missing timeunit/timeprecision for "a". + +[ERROR:PA0206] t_flag_topmodule.v:14 Missing timeunit/timeprecision for "a2". + +[ERROR:PA0206] t_flag_topmodule.v:21 Missing timeunit/timeprecision for "b". + +[ERROR:PA0206] t_flag_topmodule.v:25 Missing timeunit/timeprecision for "c". + +[ERROR:PA0206] t_flag_topmodule.v:32 Missing timeunit/timeprecision for "d". + +[ERROR:PA0206] t_func_const2_bad.v:17 Missing timeunit/timeprecision for "c9". + +[ERROR:PA0206] t_func_const2_bad.v:25 Missing timeunit/timeprecision for "b8". + +[ERROR:PA0206] t_func_regfirst.v:49 Missing timeunit/timeprecision for "f6". + +[ERROR:PA0206] t_func_wide.v:30 Missing timeunit/timeprecision for "muxtop". + +[ERROR:PA0206] t_gate_elim.v:66 Missing timeunit/timeprecision for "ta". + +[ERROR:PA0206] t_gate_elim.v:76 Missing timeunit/timeprecision for "tb". + +[ERROR:PA0206] t_gate_elim.v:86 Missing timeunit/timeprecision for "tc". + +[ERROR:PA0206] t_gate_elim.v:96 Missing timeunit/timeprecision for "td". + +[ERROR:PA0206] t_gate_elim.v:106 Missing timeunit/timeprecision for "te". + +[ERROR:PA0206] t_gen_assign.v:46 Missing timeunit/timeprecision for "assigns". + +[ERROR:PA0206] t_func_dotted.v:66 Missing timeunit/timeprecision for "global_mod". + +[ERROR:PA0206] t_func_dotted.v:76 Missing timeunit/timeprecision for "ma". + +[ERROR:PA0206] t_func_dotted.v:91 Missing timeunit/timeprecision for "mb". + +[ERROR:PA0206] t_func_dotted.v:119 Missing timeunit/timeprecision for "mc". + +[ERROR:PA0206] t_array_interface.v:6 Missing timeunit/timeprecision for "intf". + +[ERROR:PA0206] t_array_interface.v:12 Missing timeunit/timeprecision for "modify_interface". + +[ERROR:PA0206] t_gen_cond_const.v:45 Missing timeunit/timeprecision for "test_gen". + +[ERROR:PA0206] t_func_paramed.v:53 Missing timeunit/timeprecision for "extractor". + +[ERROR:PA0206] t_func_v.v:13 Missing timeunit/timeprecision for "level1". + +[ERROR:PA0206] t_func_v.v:23 Missing timeunit/timeprecision for "level2". + +[ERROR:PA0206] t_gen_for.v:54 Missing timeunit/timeprecision for "gencase". + +[ERROR:PA0206] t_gen_for.v:74 Missing timeunit/timeprecision for "paramed". + +[ERROR:PA0206] t_gen_for.v:129 Missing timeunit/timeprecision for "mbuf". + +[ERROR:PA0206] t_gen_for.v:136 Missing timeunit/timeprecision for "enflop". + +[ERROR:PA0206] t_gen_for.v:162 Missing timeunit/timeprecision for "enflop_one". + +[ERROR:PA0206] t_gate_implicit.v:78 Missing timeunit/timeprecision for "Mxor". + +[ERROR:PA0206] t_gen_intdot.v:45 Missing timeunit/timeprecision for "Generate". + +[ERROR:PA0206] t_gen_intdot.v:58 Missing timeunit/timeprecision for "Checker". + +[ERROR:PA0206] t_gen_intdot.v:77 Missing timeunit/timeprecision for "Genit". + +[ERROR:PA0206] t_gen_upscope.v:78 Missing timeunit/timeprecision for "tag". + +[ERROR:PA0206] t_gen_for1.v:42 Missing timeunit/timeprecision for "Testit". + +[ERROR:PA0206] t_gen_for1.v:68 Missing timeunit/timeprecision for "fnxtclk". + +[ERROR:PA0206] t_inst_darray.v:9 Missing timeunit/timeprecision for "the_intf". + +[ERROR:PA0206] t_inst_darray.v:26 Missing timeunit/timeprecision for "Contemplator". + +[ERROR:PA0206] t_inst_darray.v:44 Missing timeunit/timeprecision for "DeepThought". + +[ERROR:PA0206] t_inst_first_b.v:6 Missing timeunit/timeprecision for "t_inst_first_b". + +[ERROR:PA0206] t_inst_misarray_bad.v:20 Missing timeunit/timeprecision for "dut". + +[ERROR:PA0206] t_inst_misarray_bad.v:33 Missing timeunit/timeprecision for "suba". + +[ERROR:PA0206] t_inst_prepost.v:31 Missing timeunit/timeprecision for "ip". + +[ERROR:PA0206] t_for_funcbound.v:53 Missing timeunit/timeprecision for "strings". + +[ERROR:PA0206] t_inst_v2k.v:62 Missing timeunit/timeprecision for "hello". + +[ERROR:PA0206] t_interface1.v:8 Missing timeunit/timeprecision for "ifc". + +[ERROR:PA0206] t_func_check.v:33 Missing timeunit/timeprecision for "chk". + +[ERROR:PA0206] t_func_const3_bad.v:15 Missing timeunit/timeprecision for "b9". + +[ERROR:PA0206] t_interface_array.v:6 Missing timeunit/timeprecision for "foo_intf". + +[ERROR:PA0206] t_interface_array_nocolon_bad.v:12 Missing timeunit/timeprecision for "foo_subm". + +[ERROR:PA0206] t_interface_down.v:44 Missing timeunit/timeprecision for "wrapper". + +[ERROR:PA0206] t_interface_down.v:55 Missing timeunit/timeprecision for "lower". + +[ERROR:PA0206] t_interface_dups.v:88 Missing timeunit/timeprecision for "dti". + +[ERROR:PA0206] t_interface_missing_bad.v:11 Missing timeunit/timeprecision for "foo_mod". + +[ERROR:PA0206] t_gen_forif.v:67 Missing timeunit/timeprecision for "Test_wrap1". + +[ERROR:PA0206] t_gen_forif.v:75 Missing timeunit/timeprecision for "Test_wrap2". + +[ERROR:PA0206] t_interface_modport_import.v:8 Missing timeunit/timeprecision for "test_if". + +[ERROR:PA0206] t_interface_modport_import.v:42 Missing timeunit/timeprecision for "testmod". + +[ERROR:PA0206] t_interface_param1.v:21 Missing timeunit/timeprecision for "sub_test". + +[ERROR:PA0206] t_interface_param_another_bad.v:15 Missing timeunit/timeprecision for "simple_bus". + +[ERROR:PA0206] t_interface_size_bad.v:20 Missing timeunit/timeprecision for "baz". + +[ERROR:PA0206] t_func_grey.v:48 Missing timeunit/timeprecision for "t_func_grey2bin". + +[ERROR:PA0206] t_func_outp.v:48 Missing timeunit/timeprecision for "inv". + +[ERROR:PA0206] t_func_outp.v:56 Missing timeunit/timeprecision for "ftest". + +[ERROR:PA0206] t_func_outp.v:84 Missing timeunit/timeprecision for "mytop". + +[ERROR:PA0206] t_gen_intdot2.v:38 Missing timeunit/timeprecision for "One". + +[ERROR:PA0206] t_func_public.v:33 Missing timeunit/timeprecision for "tpub". + +[ERROR:PA0206] t_genfor_hier.v:7 Missing timeunit/timeprecision for "m1". + +[ERROR:PA0206] t_genvar_misuse_bad.v:7 Missing timeunit/timeprecision for "top". + +[ERROR:PA0206] t_lint_implicit_port.v:20 Missing timeunit/timeprecision for "set". + +[ERROR:PA0206] t_lint_implicit_port.v:27 Missing timeunit/timeprecision for "read". + +[ERROR:PA0206] t_gen_defparam.v:40 Missing timeunit/timeprecision for "m2". + +[ERROR:PA0206] t_lint_unused_iface_bad.v:6 Missing timeunit/timeprecision for "dummy_if". + +[ERROR:PA0206] t_gen_for_overlap.v:35 Missing timeunit/timeprecision for "sub1". + +[ERROR:PA0206] t_gen_for_overlap.v:40 Missing timeunit/timeprecision for "sub2". + +[ERROR:PA0206] t_initial_edge.v:69 Missing timeunit/timeprecision for "initial_edge_n". + +[ERROR:PA0206] t_initial_edge.v:85 Missing timeunit/timeprecision for "initial_edge". + +[ERROR:PA0206] t_gen_index.v:41 Missing timeunit/timeprecision for "foo". + +[ERROR:PA0206] t_gen_index.v:62 Missing timeunit/timeprecision for "bar". + +[ERROR:PA0206] t_inst_dff.v:109 Missing timeunit/timeprecision for "dff". + +[ERROR:PA0206] t_inst_notunsized.v:93 Missing timeunit/timeprecision for "Muxer". + +[ERROR:PA0206] t_inst_sv.v:61 Missing timeunit/timeprecision for "t_inst". + +[ERROR:PA0206] t_inst_wideconst.v:59 Missing timeunit/timeprecision for "wide". + +[ERROR:PA0206] t_gen_missing.v:12 Missing timeunit/timeprecision for "foobar". + +[ERROR:PA0206] t_gen_missing.v:45 Missing timeunit/timeprecision for "foo0". + +[ERROR:PA0206] t_interface_arraymux.v:32 Missing timeunit/timeprecision for "ThingMuxOH". + +[ERROR:PA0206] t_interface_arraymux.v:43 Missing timeunit/timeprecision for "Thinker". + +[ERROR:PA0206] t_interface_modport_bad.v:20 Missing timeunit/timeprecision for "counter_ansi". + +[ERROR:PA0206] t_interface_modportlist.v:13 Missing timeunit/timeprecision for "my_module". + +[ERROR:PA0206] t_interface_modportlist.v:20 Missing timeunit/timeprecision for "my_interface". + +[ERROR:PA0206] t_interface_param2.v:37 Missing timeunit/timeprecision for "mem". + +[ERROR:PA0206] t_interface_star.v:30 Missing timeunit/timeprecision for "counter_io". + +[ERROR:PA0206] t_interface_wrong_bad.v:11 Missing timeunit/timeprecision for "bar_intf". + +[ERROR:PA0206] t_lint_blksync_loop.v:44 Missing timeunit/timeprecision for "reg_1r1w". + +[ERROR:PA0206] t_lint_importstar_bad.v:6 Missing timeunit/timeprecision for "defs". + +[ERROR:PA0206] t_bind2.v:50 Missing timeunit/timeprecision for "targetmod". + +[ERROR:PA0206] t_bind2.v:66 Missing timeunit/timeprecision for "mycheck". + +[ERROR:PA0206] t_init_concat.v:59 Missing timeunit/timeprecision for "regfile". + +[ERROR:PA0206] t_case_huge_sub3.v:6 Missing timeunit/timeprecision for "t_case_huge_sub3". + +[ERROR:PA0206] t_inst_dtree.v:19 Missing timeunit/timeprecision for "bmod". + +[ERROR:PA0206] t_inst_dtree.v:28 Missing timeunit/timeprecision for "cmod". + +[ERROR:PA0206] t_inst_dtree.v:38 Missing timeunit/timeprecision for "dmod". + +[ERROR:PA0206] t_inst_first_a.v:6 Missing timeunit/timeprecision for "t_inst_first_a". + +[ERROR:PA0206] t_inst_implicit.v:30 Missing timeunit/timeprecision for "subimp". + +[ERROR:PA0206] t_inst_mnpipe.v:42 Missing timeunit/timeprecision for "dffn". + +[ERROR:PA0206] t_inst_mnpipe.v:55 Missing timeunit/timeprecision for "MxN_pipeline". + +[ERROR:PA0206] t_inst_recurse2_bad.v:17 Missing timeunit/timeprecision for "looped". + +[ERROR:PA0206] t_inst_recurse_bad.v:21 Missing timeunit/timeprecision for "looped2". + +[ERROR:PA0206] t_math_imm.v:73 Missing timeunit/timeprecision for "example". + +[ERROR:PA0206] t_interface.v:70 Missing timeunit/timeprecision for "handshake". + +[ERROR:PA0206] t_interface.v:109 Missing timeunit/timeprecision for "source". + +[ERROR:PA0206] t_interface.v:141 Missing timeunit/timeprecision for "drain". + +[ERROR:PA0206] t_interface_gen12.v:8 Missing timeunit/timeprecision for "foo_module". + +[ERROR:PA0206] t_interface_gen12.v:16 Missing timeunit/timeprecision for "bar_module". + +[ERROR:PA0206] t_math_vliw.v:58 Missing timeunit/timeprecision for "vliw". + +[ERROR:PA0206] t_interface_modport_export.v:45 Missing timeunit/timeprecision for "testmod_callee". + +[ERROR:PA0206] t_interface_modport_export.v:58 Missing timeunit/timeprecision for "testmod_caller". + +[ERROR:PA0206] t_interface_nest.v:6 Missing timeunit/timeprecision for "if1". + +[ERROR:PA0206] t_interface_nest.v:10 Missing timeunit/timeprecision for "if2". + +[ERROR:PA0206] t_interface_nest.v:15 Missing timeunit/timeprecision for "mod1". + +[ERROR:PA0206] t_cdc_async_bad.v:66 Missing timeunit/timeprecision for "Flop". + +[ERROR:PA0206] t_cdc_async_bad.v:78 Missing timeunit/timeprecision for "Sub". + +[ERROR:PA0206] t_langext_order_sub.v:10 Missing timeunit/timeprecision for "t_langext_order_sub". + +[ERROR:PA0206] t_lint_always_comb_iface.v:6 Missing timeunit/timeprecision for "my_if". + +[ERROR:PA0206] t_lint_always_comb_iface.v:54 Missing timeunit/timeprecision for "my_module1". + +[ERROR:PA0206] t_lint_always_comb_iface.v:68 Missing timeunit/timeprecision for "my_module2". + +[ERROR:PA0206] t_lint_always_comb_iface.v:84 Missing timeunit/timeprecision for "my_module3". + +[ERROR:PA0206] t_cellarray.v:66 Missing timeunit/timeprecision for "drv1". + +[ERROR:PA0206] t_cellarray.v:73 Missing timeunit/timeprecision for "drv2". + +[ERROR:PA0206] t_cellarray.v:81 Missing timeunit/timeprecision for "drv3". + +[ERROR:PA0206] t_cellarray.v:91 Missing timeunit/timeprecision for "drv4". + +[ERROR:PA0206] t_chg_first.v:61 Missing timeunit/timeprecision for "t_chg_a". + +[ERROR:PA0206] t_lint_unused.v:51 Missing timeunit/timeprecision for "udp_mux2". + +[ERROR:PA0206] t_mem_iforder.v:58 Missing timeunit/timeprecision for "fifo". + +[ERROR:PA0206] t_lint_width_bad.v:35 Missing timeunit/timeprecision for "p". + +[ERROR:PA0206] t_math_cmp.v:71 Missing timeunit/timeprecision for "prover". + +[ERROR:PA0206] t_clk_first.v:30 Missing timeunit/timeprecision for "t_clk". + +[ERROR:PA0206] t_clk_first.v:133 Missing timeunit/timeprecision for "t_clk_flop". + +[ERROR:PA0206] t_clk_first.v:151 Missing timeunit/timeprecision for "t_clk_two". + +[ERROR:PA0206] t_clk_first.v:175 Missing timeunit/timeprecision for "t_clk_twob". + +[ERROR:PA0206] t_math_signed.v:164 Missing timeunit/timeprecision for "by_width". + +[ERROR:PA0206] t_clk_latchgate.v:97 Missing timeunit/timeprecision for "llq". + +[ERROR:PA0206] t_clk_latchgate.v:116 Missing timeunit/timeprecision for "ffq". + +[ERROR:PA0206] t_mod_interface_array.v:8 Missing timeunit/timeprecision for "a_if". + +[ERROR:PA0206] t_mod_interface_array.v:14 Missing timeunit/timeprecision for "intf_source". + +[ERROR:PA0206] t_mod_interface_array.v:26 Missing timeunit/timeprecision for "intf_sink". + +[ERROR:PA0206] t_mod_longname.v:28 Missing timeunit/timeprecision for "modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie". + +[ERROR:PA0206] t_cover_line.v:114 Missing timeunit/timeprecision for "tsk". + +[ERROR:PA0206] t_mem_file.v:76 Missing timeunit/timeprecision for "file". + +[ERROR:PA0206] t_dedupe_clk_gate.v:20 Missing timeunit/timeprecision for "flop_gated_latch". + +[ERROR:PA0206] t_dedupe_clk_gate.v:30 Missing timeunit/timeprecision for "flop_gated_flop". + +[ERROR:PA0206] t_dedupe_clk_gate.v:40 Missing timeunit/timeprecision for "clock_gate_latch". + +[ERROR:PA0206] t_dedupe_clk_gate.v:52 Missing timeunit/timeprecision for "clock_gate_flop". + +[ERROR:PA0206] t_package_abs.v:8 Missing timeunit/timeprecision for "functions". + +[ERROR:PA0206] t_package_twodeep.v:8 Missing timeunit/timeprecision for "pkg2". + +[ERROR:PA0206] t_package_twodeep.v:12 Missing timeunit/timeprecision for "pkg1". + +[ERROR:PA0206] t_mem_slot.v:7 Missing timeunit/timeprecision for "t_mem_slot". + +[ERROR:PA0206] t_mod_recurse1.v:12 Missing timeunit/timeprecision for "rec". + +[ERROR:PA0206] t_mod_recurse1.v:28 Missing timeunit/timeprecision for "bottom". + +[ERROR:PA0206] t_order_b.v:6 Missing timeunit/timeprecision for "t_order_b". + +[ERROR:PA0206] t_order_clkinst.v:61 Missing timeunit/timeprecision for "comb_loop". + +[ERROR:PA0206] t_order_clkinst.v:90 Missing timeunit/timeprecision for "seq_loop". + +[ERROR:PA0206] t_param_array.v:78 Missing timeunit/timeprecision for "checkstr". + +[ERROR:PA0206] t_param_default_bad.v:6 Missing timeunit/timeprecision for "m". + +[ERROR:PA0206] t_param_first_b.v:6 Missing timeunit/timeprecision for "t_param_first_b". + +[ERROR:PA0206] t_order_multidriven.v:61 Missing timeunit/timeprecision for "FooWr". + +[ERROR:PA0206] t_order_multidriven.v:86 Missing timeunit/timeprecision for "FooRd". + +[ERROR:PA0206] t_order_multidriven.v:125 Missing timeunit/timeprecision for "FooMem". + +[ERROR:PA0206] t_order_multidriven.v:151 Missing timeunit/timeprecision for "FooMemImpl". + +[ERROR:PA0206] t_param_package.v:12 Missing timeunit/timeprecision for "params". + +[ERROR:PA0206] t_param_package.v:16 Missing timeunit/timeprecision for "Test0". + +[ERROR:PA0206] t_param_package.v:21 Missing timeunit/timeprecision for "Test1". + +[ERROR:PA0206] t_param_real.v:6 Missing timeunit/timeprecision for "mod". + +[ERROR:PA0206] t_dpi_accessors.v:50 Missing timeunit/timeprecision for "test_sub". + +[ERROR:PA0206] t_param_if_blk.v:71 Missing timeunit/timeprecision for "Nested". + +[ERROR:PA0206] t_param_named.v:29 Missing timeunit/timeprecision for "m3". + +[ERROR:PA0206] t_param_no_parentheses.v:66 Missing timeunit/timeprecision for "mnooverride". + +[ERROR:PA0206] t_mem_multi_io3.v:34 Missing timeunit/timeprecision for "testio". + +[ERROR:PA0206] t_mod_recurse.v:62 Missing timeunit/timeprecision for "PriorityChoice". + +[ERROR:PA0206] t_param_type.v:54 Missing timeunit/timeprecision for "mod_typ". + +[ERROR:PA0206] t_order_a.v:6 Missing timeunit/timeprecision for "t_order_a". + +[ERROR:PA0206] t_order_first.v:20 Missing timeunit/timeprecision for "t_netlist". + +[ERROR:PA0206] t_pp_lib_library.v:6 Missing timeunit/timeprecision for "library_cell". + +[ERROR:PA0206] t_package.v:20 Missing timeunit/timeprecision for "p2". + +[ERROR:PA0206] t_reloop_cam.v:95 Missing timeunit/timeprecision for "cam". + +[ERROR:PA0206] t_preproc_kwd.v:28 Missing timeunit/timeprecision for "v95". + +[ERROR:PA0206] t_preproc_kwd.v:34 Missing timeunit/timeprecision for "v01". + +[ERROR:PA0206] t_preproc_kwd.v:40 Missing timeunit/timeprecision for "v05". + +[ERROR:PA0206] t_preproc_kwd.v:46 Missing timeunit/timeprecision for "s05". + +[ERROR:PA0206] t_preproc_kwd.v:52 Missing timeunit/timeprecision for "s09". + +[ERROR:PA0206] t_preproc_kwd.v:58 Missing timeunit/timeprecision for "s12". + +[ERROR:PA0206] t_preproc_kwd.v:66 Missing timeunit/timeprecision for "s17". + +[ERROR:PA0206] t_preproc_kwd.v:74 Missing timeunit/timeprecision for "a23". + +[ERROR:PA0206] t_param_ddeep_width.v:13 Missing timeunit/timeprecision for "paramtest_WRAP". + +[ERROR:PA0206] t_param_ddeep_width.v:20 Missing timeunit/timeprecision for "paramtest_DFFRE". + +[ERROR:PA0206] t_param_first_a.v:6 Missing timeunit/timeprecision for "t_param_first_a". + +[ERROR:PA0206] t_embed1_child.v:6 Missing timeunit/timeprecision for "t_embed1_child". + +[ERROR:PA0206] t_embed1_wrap.v:6 Missing timeunit/timeprecision for "t_embed1_wrap". + +[ERROR:PA0206] t_param_mem_attr.v:34 Missing timeunit/timeprecision for "memory". + +[ERROR:PA0206] t_enum_name2.v:6 Missing timeunit/timeprecision for "our_pkg". + +[ERROR:PA0206] t_enum_name2.v:19 Missing timeunit/timeprecision for "our". + +[ERROR:PA0206] t_enum_public.v:6 Missing timeunit/timeprecision for "p3". + +[ERROR:PA0206] t_enum_public.v:12 Missing timeunit/timeprecision for "p62". + +[ERROR:PA0206] t_param_sel_range.v:15 Missing timeunit/timeprecision for "submod". + +[ERROR:PA0206] t_param_type2.v:6 Missing timeunit/timeprecision for "tt_pkg". + +[ERROR:PA0206] t_param_type2.v:31 Missing timeunit/timeprecision for "tt_buf". + +[ERROR:PA0206] t_param_up_bad.v:12 Missing timeunit/timeprecision for "child". + +[ERROR:PA0206] t_param_up_bad.v:18 Missing timeunit/timeprecision for "parent". + +[ERROR:PA0206] t_past.v:84 Missing timeunit/timeprecision for "Test2". + +[ERROR:PA0206] t_struct_param.v:7 Missing timeunit/timeprecision for "config_pkg". + +[ERROR:PA0206] t_struct_param.v:40 Missing timeunit/timeprecision for "struct_submodule". + +[ERROR:PA0206] t_struct_unpacked.v:6 Missing timeunit/timeprecision for "x". + +[ERROR:PA0206] t_tri_array_pull.v:6 Missing timeunit/timeprecision for "IOBUF". + +[ERROR:PA0206] t_struct_array.v:6 Missing timeunit/timeprecision for "TEST_TYPES". + +[ERROR:PA0206] t_sv_conditional.v:62 Missing timeunit/timeprecision for "st3_testbench". + +[ERROR:PA0206] t_sv_conditional.v:145 Missing timeunit/timeprecision for "simple_test_3". + +[ERROR:PA0206] t_sv_conditional.v:230 Missing timeunit/timeprecision for "counterA". + +[ERROR:PA0206] t_sv_conditional.v:277 Missing timeunit/timeprecision for "counterB". + +[ERROR:PA0206] t_sv_conditional.v:311 Missing timeunit/timeprecision for "simple_test_3a". + +[ERROR:PA0206] t_sv_conditional.v:331 Missing timeunit/timeprecision for "simple_test_3b". + +[ERROR:PA0206] t_sv_conditional.v:363 Missing timeunit/timeprecision for "simple_test_3c". + +[ERROR:PA0206] t_sv_conditional.v:395 Missing timeunit/timeprecision for "simple_test_3d". + +[ERROR:PA0206] t_sv_conditional.v:425 Missing timeunit/timeprecision for "simple_test_3e". + +[ERROR:PA0206] t_sv_conditional.v:449 Missing timeunit/timeprecision for "simple_test_3f". + +[ERROR:PA0206] t_trace_primitive.v:31 Missing timeunit/timeprecision for "CINV". + +[ERROR:PA0206] t_sv_cpu.v:79 Missing timeunit/timeprecision for "testbench". + +[ERROR:PA0206] t_type_param.v:15 Missing timeunit/timeprecision for "foo_wrapper". + +[ERROR:PA0206] t_typedef_port.v:78 Missing timeunit/timeprecision for "TestNonAnsi". + +[ERROR:PA0206] t_typedef_port.v:95 Missing timeunit/timeprecision for "TestAnsi". + +[ERROR:PA0206] t_trace_param.v:6 Missing timeunit/timeprecision for "my_funcs". + +[ERROR:PA0206] t_trace_param.v:14 Missing timeunit/timeprecision for "my_module_types". + +[ERROR:PA0206] t_tri_gen.v:27 Missing timeunit/timeprecision for "updown". + +[ERROR:PA0206] t_tri_gen.v:39 Missing timeunit/timeprecision for "t_up". + +[ERROR:PA0206] t_tri_gen.v:42 Missing timeunit/timeprecision for "t_down". + +[ERROR:PA0206] t_tri_array.v:65 Missing timeunit/timeprecision for "Pad". + +[ERROR:PA0206] t_var_dup_bad.v:46 Missing timeunit/timeprecision for "sub0". + +[ERROR:PA0206] t_var_dup_bad.v:68 Missing timeunit/timeprecision for "sub3". + +[ERROR:PA0206] t_tri_public.v:47 Missing timeunit/timeprecision for "sub_mod". + +[ERROR:PA0206] t_tri_select.v:35 Missing timeunit/timeprecision for "io_ring". + +[ERROR:PA0206] t_tri_select.v:39 Missing timeunit/timeprecision for "io". + +[ERROR:PA0206] t_tri_gate.v:15 Missing timeunit/timeprecision for "pass". + +[ERROR:PA0206] t_tri_gate.v:20 Missing timeunit/timeprecision for "tbuf". + +[ERROR:PA0206] t_tri_gate.v:24 Missing timeunit/timeprecision for "mux". + +[ERROR:PA0206] t_var_port_bad.v:11 Missing timeunit/timeprecision for "subok". + +[ERROR:PA0206] t_tri_pull01.v:71 Missing timeunit/timeprecision for "t_tri2". + +[ERROR:PA0206] t_tri_pull01.v:84 Missing timeunit/timeprecision for "t_tri3". + +[ERROR:PA0206] t_tri_various.v:146 Missing timeunit/timeprecision for "Test3". + +[ERROR:PA0206] t_tri_various.v:154 Missing timeunit/timeprecision for "Test4". + +[ERROR:PA0206] t_tri_various.v:159 Missing timeunit/timeprecision for "Test5". + +[ERROR:PA0206] t_tri_various.v:167 Missing timeunit/timeprecision for "Test6". + +[ERROR:PA0206] t_tri_various.v:173 Missing timeunit/timeprecision for "Test6a". + +[ERROR:PA0206] t_tri_various.v:177 Missing timeunit/timeprecision for "Test7". + +[ERROR:PA0206] t_vpi_var.v:87 Missing timeunit/timeprecision for "arr". + +[ERROR:PA0206] t_udp_noname.v:35 Missing timeunit/timeprecision for "udp". + +[ERROR:PA0206] t_unoptflat_simple_3.v:41 Missing timeunit/timeprecision for "test1". + +[ERROR:PA0206] t_unoptflat_simple_3.v:60 Missing timeunit/timeprecision for "test2". + +[ERROR:PA0206] t_udp.v:115 Missing timeunit/timeprecision for "udp_latch". + +[ERROR:PA0206] t_udp.v:126 Missing timeunit/timeprecision for "udp_dff". + +[ERROR:PA0206] t_final.v:6 Missing timeunit/timeprecision for "submodule". + +[ERROR:PA0206] t_vams_wreal.v:87 Missing timeunit/timeprecision for "through". + +[ERROR:PA0206] t_vams_wreal.v:93 Missing timeunit/timeprecision for "within_range". + +[ERROR:PA0206] t_vams_wreal.v:106 Missing timeunit/timeprecision for "wreal_bus". + +[ERROR:PA0206] t_vams_wreal.v:114 Missing timeunit/timeprecision for "first_level". + +[ERROR:PA0206] t_vams_wreal.v:121 Missing timeunit/timeprecision for "second_level". + +[ERROR:PA0206] t_var_overzero.v:33 Missing timeunit/timeprecision for "tsub". + +[ERROR:PA0206] t_flag_libinc.v:6 Missing timeunit/timeprecision for "liblib_a". + +[ERROR:PA0206] t_flag_libinc.v:10 Missing timeunit/timeprecision for "liblib_b". + +[ERROR:PA0206] t_flag_libinc.v:17 Missing timeunit/timeprecision for "liblib_c". + +[ERROR:PA0206] t_flag_libinc.v:23 Missing timeunit/timeprecision for "liblib_d". + +[ERROR:PA0206] t_flag_topmod2_bad.v:6 Missing timeunit/timeprecision for "a_top". + +[ERROR:PA0206] t_flag_topmodule_inline.v:22 Missing timeunit/timeprecision for "l3". + +[ERROR:PA0206] t_func_begin2.v:6 Missing timeunit/timeprecision for "init". + +[ERROR:PA0206] t_var_in_assign.v:59 Missing timeunit/timeprecision for "z". + +[ERROR:PA0206] t_func_const.v:6 Missing timeunit/timeprecision for "testpackage". + +[ERROR:PA0206] t_xml_first.v:44 Missing timeunit/timeprecision for "mod2". + +[ERROR:PA0206] t_func_lib_sub.v:7 Missing timeunit/timeprecision for "BreadAddrDP". + +[ERROR:PA0206] t_func_lib_sub.v:56 Missing timeunit/timeprecision for "DecCountReg4". + +[ERROR:PA0206] t_gate_fdup.v:6 Missing timeunit/timeprecision for "fnor2". + +[ERROR:PA0206] t_generate_fatal_bad.v:15 Missing timeunit/timeprecision for "foo2". + +[ERROR:PA0206] t_inst_aport.v:65 Missing timeunit/timeprecision for "callee". + +[ERROR:PA0206] t_inst_tree.v:63 Missing timeunit/timeprecision for "ps". + +[ERROR:PA0206] t_inst_tree.v:69 Missing timeunit/timeprecision for "l1". + +[ERROR:PA0206] t_inst_tree.v:76 Missing timeunit/timeprecision for "l2". + +[ERROR:PA0206] t_inst_tree.v:92 Missing timeunit/timeprecision for "l4". + +[ERROR:PA0206] t_inst_tree.v:100 Missing timeunit/timeprecision for "l5". + +[ERROR:PA0206] t_interface2.v:72 Missing timeunit/timeprecision for "ifunused". + +[ERROR:PA0206] t_interface2.v:93 Missing timeunit/timeprecision for "counter_nansi". + +[ERROR:PA0206] t_interface2.v:104 Missing timeunit/timeprecision for "modunused". + +[ERROR:PA0206] t_interface_bind_public.v:6 Missing timeunit/timeprecision for "hex2ram_if". + +[ERROR:PA0206] t_interface_bind_public.v:69 Missing timeunit/timeprecision for "testharness_ext". + +[ERROR:PA0206] t_interface_bind_public.v:100 Missing timeunit/timeprecision for "SimpleTestHarness". + +[ERROR:PA0206] t_interface_modport.v:6 Missing timeunit/timeprecision for "counter_if". + +[ERROR:PA0206] t_interface_modport.v:103 Missing timeunit/timeprecision for "counter_ansi_m". + +[ERROR:PA0206] t_interface_modport.v:116 Missing timeunit/timeprecision for "counter_nansi_m". + +[ERROR:PA0206] t_lint_declfilename.v:10 Missing timeunit/timeprecision for "t_lint_declfilename". + +[ERROR:PA0206] t_math_imm2.v:13 Missing timeunit/timeprecision for "t_math_imm2". + +[ERROR:PA0206] t_math_pow4.v:43 Missing timeunit/timeprecision for "test004". + +[ERROR:PA0206] t_math_real.v:141 Missing timeunit/timeprecision for "sub_cast_bug374". + +[ERROR:PA0206] t_mem_multi_io.v:39 Missing timeunit/timeprecision for "has_array". + +[ERROR:PA0206] t_mem_multiwire.v:53 Missing timeunit/timeprecision for "inst". + +[ERROR:PA0206] t_mem_multiwire.v:75 Missing timeunit/timeprecision for "inst2". + +[ERROR:PA0206] t_mem_slice_conc_bad.v:68 Missing timeunit/timeprecision for "bbb". + +[ERROR:PA0206] t_mem_slice_conc_bad.v:101 Missing timeunit/timeprecision for "aaa". + +[ERROR:PA0206] t_multitop1s.v:6 Missing timeunit/timeprecision for "t_multitop1s". + +[ERROR:PA0206] t_multitop1s.v:10 Missing timeunit/timeprecision for "in_subfile". + +[ERROR:PA0206] t_package_dot.v:13 Missing timeunit/timeprecision for "csr_pkg". + +[ERROR:PA0206] t_package_export.v:14 Missing timeunit/timeprecision for "pkg10". + +[ERROR:PA0206] t_package_export.v:19 Missing timeunit/timeprecision for "pkg11". + +[ERROR:PA0206] t_package_export.v:23 Missing timeunit/timeprecision for "pkg20". + +[ERROR:PA0206] t_package_export.v:27 Missing timeunit/timeprecision for "pkg21". + +[ERROR:PA0206] t_package_export.v:31 Missing timeunit/timeprecision for "pkg30". + +[ERROR:PA0206] t_package_export.v:35 Missing timeunit/timeprecision for "pkg31". + +[ERROR:PA0206] t_package_verb.v:7 Missing timeunit/timeprecision for "verb_pkg". + +[ERROR:PA0206] t_param_long.v:94 Missing timeunit/timeprecision for "i". + +[ERROR:PA0206] t_preproc_inc_inc_bad.vh:6 Missing timeunit/timeprecision for "xx". + +[ERROR:PA0206] t_trace_public.v:32 Missing timeunit/timeprecision for "glbl". + +[ERROR:PA0206] t_trace_public.v:36 Missing timeunit/timeprecision for "neg". + +[ERROR:PA0206] t_trace_public.v:51 Missing timeunit/timeprecision for "little". + +[ERROR:PA0206] t_tri_inout2.v:59 Missing timeunit/timeprecision for "ChildA". + +[ERROR:PA0206] t_tri_inout2.v:73 Missing timeunit/timeprecision for "ChildB". + +[ERROR:PA0206] t_tri_pullup.v:24 Missing timeunit/timeprecision for "pullup_module". + +[ERROR:PA0206] t_tri_unconn.v:78 Missing timeunit/timeprecision for "t_tri0". + +[ERROR:PA0206] t_tri_unconn.v:90 Missing timeunit/timeprecision for "t_tri1". + +[ERROR:PA0206] t_var_notfound_bad.v:32 Missing timeunit/timeprecision for "subsub". + +[ FATAL] : 0 +[ ERROR] : 631 +[WARNING] : 416 +[ NOTE] : 4 + +******************************************** +* End SURELOG SVerilog Compiler/Linter * +******************************************** + +181.45user 1.80system 1:41.24elapsed 180%CPU (0avgtext+0avgdata 1924636maxresident)k +8296inputs+9744outputs (0major+478748minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/Verilator/Verilator_diff.log b/SVIncCompil/Testcases/Verilator/Verilator_diff.log new file mode 100644 index 0000000..55dd938 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/Verilator_diff.log
@@ -0,0 +1,5704 @@ +******************************************** +* SURELOG System Verilog Compiler/Linter * +******************************************** + +[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. + +[INFO :CM0024] Executing with 4 threads. + +[INFO :CM0020] Separate compilation-unit mode is on. + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv". + +[INFO :PP0122] Preprocessing source file "/home/alain/surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac_ana.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac_dig.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/genbus_if.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/adrdec.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/chip.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/cpu.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pads_if.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ports_h.sv". + +[INFO :PP0122] Preprocessing source file "tsub/t_flag_f_tsub_inc.v". + +[INFO :PP0122] Preprocessing source file "t_a_first_cc.v". + +[INFO :PP0122] Preprocessing source file "t_alw_combdly.v". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pad_gnd.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pad_gpio.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pad_vdd.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pads.sv". + +[INFO :PP0122] Preprocessing source file "t_alw_nosplit.v". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pinout_h.sv". + +[INFO :PP0122] Preprocessing source file "t_array_backw_index_bad.v". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/program_h.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/pads_h.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/rom.sv". + +[INFO :PP0122] Preprocessing source file "t_array_compare.v". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ports.sv". + +[INFO :PP0122] Preprocessing source file "t_array_interface.v". + +[INFO :PP0122] Preprocessing source file "t_array_pattern_2d.v". + +[INFO :PP0122] Preprocessing source file "t_array_pattern_bad.v". + +[INFO :PP0122] Preprocessing source file "t_array_pattern_unpacked.v". + +[INFO :PP0122] Preprocessing source file "t_array_query.v". + +[INFO :PP0122] Preprocessing source file "t_array_rev.v". + +[INFO :PP0122] Preprocessing source file "t_array_type_methods.v". + +[INFO :PP0122] Preprocessing source file "tsub/t_flag_f_tsub.v". + +[INFO :PP0122] Preprocessing source file "t_EXAMPLE.v". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/timescale.sv". + +[INFO :PP0122] Preprocessing source file "t_altera_lpm.v". + +[INFO :PP0122] Preprocessing source file "t_assert_basic.v". + +[INFO :PP0122] Preprocessing source file "t_alw_reorder.v". + +[INFO :PP0122] Preprocessing source file "t_assert_cover.v". + +[INFO :PP0122] Preprocessing source file "t_alw_dly.v". + +[INFO :PP0122] Preprocessing source file "t_alw_split_rst.v". + +[INFO :PP0122] Preprocessing source file "t_alw_split.v". + +[INFO :PP0122] Preprocessing source file "t_alw_splitord.v". + +[INFO :PP0122] Preprocessing source file "t_array_list_bad.v". + +[INFO :PP0122] Preprocessing source file "t_array_mda.v". + +[INFO :PP0122] Preprocessing source file "t_array_packed_sysfunct.v". + +[INFO :PP0122] Preprocessing source file "t_array_pattern_packed.v". + +[INFO :PP0122] Preprocessing source file "t_assert_dup_bad.v". + +[INFO :PP0122] Preprocessing source file "t_assert_property.v". + +[INFO :PP0122] Preprocessing source file "t_assert_synth.v". + +[INFO :PP0122] Preprocessing source file "t_bench_mux4k.v". + +[INFO :PP0122] Preprocessing source file "t_bind2.v". + +[INFO :PP0122] Preprocessing source file "t_bitsel_wire_array_bad.v". + +[INFO :PP0122] Preprocessing source file "t_case_66bits.v". + +[INFO :PP0122] Preprocessing source file "t_case_auto1.v". + +[INFO :PP0122] Preprocessing source file "t_case_genx_bad.v". + +[INFO :PP0122] Preprocessing source file "t_case_group.v". + +[INFO :PP0122] Preprocessing source file "t_case_huge.v". + +[INFO :PP0122] Preprocessing source file "t_bitsel_slice.v". + +[INFO :PP0122] Preprocessing source file "t_bitsel_struct3.v". + +[INFO :PP0122] Preprocessing source file "t_case_huge_sub2.v". + +[INFO :PP0122] Preprocessing source file "t_case_deep.v". + +[INFO :PP0122] Preprocessing source file "t_case_inside.v". + +[INFO :PP0122] Preprocessing source file "t_case_itemwidth.v". + +[INFO :PP0122] Preprocessing source file "t_case_onehot.v". + +[INFO :PP0122] Preprocessing source file "t_case_reducer.v". + +[INFO :PP0122] Preprocessing source file "t_case_huge_sub3.v". + +[INFO :PP0122] Preprocessing source file "t_case_x.v". + +[INFO :PP0122] Preprocessing source file "t_case_x_bad.v". + +[INFO :PP0122] Preprocessing source file "t_case_zx_bad.v". + +[INFO :PP0122] Preprocessing source file "t_cast.v". + +[INFO :PP0122] Preprocessing source file "t_case_write1.v". + +[INFO :PP0122] Preprocessing source file "t_cdc_async_bad.v". + +[INFO :PP0122] Preprocessing source file "t_cellarray.v". + +[INFO :PP0122] Preprocessing source file "t_chg_first.v". + +[INFO :PP0122] Preprocessing source file "t_clk_concat.v". + +[INFO :PP0122] Preprocessing source file "t_case_write2.v". + +[INFO :PP0122] Preprocessing source file "t_clk_concat2.v". + +[INFO :PP0122] Preprocessing source file "t_case_write2_tasks.v". + +[INFO :PP0122] Preprocessing source file "t_clk_concat3.v". + +[INFO :PP0122] Preprocessing source file "t_clk_concat4.v". + +[INFO :PP0122] Preprocessing source file "t_clk_concat5.v". + +[INFO :PP0122] Preprocessing source file "t_clk_concat6.v". + +[INFO :PP0122] Preprocessing source file "t_clk_condflop.v". + +[INFO :PP0122] Preprocessing source file "t_clk_condflop_nord.v". + +[INFO :PP0122] Preprocessing source file "t_clk_dpulse.v". + +[INFO :PP0122] Preprocessing source file "t_clk_dsp.v". + +[INFO :PP0122] Preprocessing source file "t_clk_first.v". + +[INFO :PP0122] Preprocessing source file "t_clk_gater.v". + +[INFO :PP0122] Preprocessing source file "t_arraysel_wide.v". + +[INFO :PP0122] Preprocessing source file "t_assert_casez.v". + +[INFO :PP0122] Preprocessing source file "t_assert_comp.v". + +[INFO :PP0122] Preprocessing source file "t_assert_comp_bad.v". + +[INFO :PP0122] Preprocessing source file "t_clk_gen.v". + +[INFO :PP0122] Preprocessing source file "t_assert_elab.v". + +[INFO :PP0122] Preprocessing source file "t_assert_question.v". + +[INFO :PP0122] Preprocessing source file "t_assign_inline.v". + +[INFO :PP0122] Preprocessing source file "t_attr_parenstar.v". + +[INFO :PP0122] Preprocessing source file "t_bind.v". + +[INFO :PP0122] Preprocessing source file "t_bitsel_const_bad.v". + +[INFO :PP0122] Preprocessing source file "t_bitsel_enum.v". + +[INFO :PP0122] Preprocessing source file "t_bitsel_struct.v". + +[INFO :PP0122] Preprocessing source file "t_bitsel_struct2.v". + +[INFO :PP0122] Preprocessing source file "t_blocking.v". + +[INFO :PP0122] Preprocessing source file "t_case_default_bad.v". + +[INFO :PP0122] Preprocessing source file "t_case_dupitems.v". + +[INFO :PP0122] Preprocessing source file "t_case_huge_sub.v". + +[INFO :PP0122] Preprocessing source file "t_clk_inp_init.v". + +[INFO :PP0122] Preprocessing source file "t_clk_latch.v". + +[INFO :PP0122] Preprocessing source file "t_case_huge_sub4.v". + +[INFO :PP0122] Preprocessing source file "t_case_nest.v". + +[INFO :PP0122] Preprocessing source file "t_gen_mislevel.v". + +[INFO :PP0122] Preprocessing source file "t_clk_latchgate.v". + +[INFO :PP0122] Preprocessing source file "t_case_orig.v". + +[INFO :PP0122] Preprocessing source file "t_case_wild.v". + +[INFO :PP0122] Preprocessing source file "t_gen_missing.v". + +[INFO :PP0122] Preprocessing source file "t_clk_powerdn.v". + +[INFO :PP0122] Preprocessing source file "t_case_write1_tasks.v". + +[INFO :PP0122] Preprocessing source file "t_clk_scope_bad.v". + +[INFO :PP0122] Preprocessing source file "t_clk_vecgen1.v". + +[INFO :PP0122] Preprocessing source file "t_gen_upscope.v". + +[INFO :PP0122] Preprocessing source file "t_if_deep.v". + +[INFO :PP0122] Preprocessing source file "t_clocker.v". + +[INFO :PP0122] Preprocessing source file "t_concat_large.v". + +[INFO :PP0122] Preprocessing source file "t_concat_large_bad.v". + +[INFO :PP0122] Preprocessing source file "t_concat_opt.v". + +[INFO :PP0122] Preprocessing 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Preprocessing source file "t_preproc_noline.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_persist.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_persist_inc.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_undefineall.v". + +[INFO :PP0122] Preprocessing source file "t_struct_packed_value_list.v". + +[INFO :PP0122] Preprocessing source file "t_struct_unpacked.v". + +[INFO :PP0122] Preprocessing source file "t_struct_unpacked_bad.v". + +[INFO :PP0122] Preprocessing source file "t_sv_conditional.v". + +[INFO :PP0122] Preprocessing source file "t_trace_fst.v". + +[INFO :PP0122] Preprocessing source file "t_tri_array_bufif.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inout2.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull2_bad.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull_bad.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pullvec_bad.v". + +[INFO :PP0122] Preprocessing source file "t_tri_select_unsized.v". + +[INFO :PP0122] Preprocessing source file "t_type_param.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_port.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_array.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_converge.v". + +[INFO :PP0122] Preprocessing source file "t_unoptflat_simple.v". + +[INFO :PP0122] Preprocessing source file "t_unpacked_array_order.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_genf.v". + +[INFO :PP0122] Preprocessing source file "t_vams_wreal.v". + +[INFO :PP0122] Preprocessing source file "t_var_dotted.v". + +[INFO :PP0122] Preprocessing source file "t_var_port2_bad.v". + +[INFO :PP0122] Preprocessing source file "t_repeat.v". + +[INFO :PP0122] Preprocessing source file "t_var_port_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref.v". + +[INFO :PP0122] Preprocessing source file "t_var_set_link.v". + +[INFO :PP0122] Preprocessing source file "t_runflag.v". + +[INFO :PP0122] Preprocessing source file "t_runflag_seed.v". + +[INFO :PP0122] Preprocessing source file "t_scope_map.v". + +[INFO :PP0122] Preprocessing source file "t_select_bad_msb.v". + +[INFO :PP0122] Preprocessing source file "t_select_bad_range.v". + +[INFO :PP0122] Preprocessing source file "t_select_bad_range2.v". + +[INFO :PP0122] Preprocessing source file "t_select_bound2.v". + +[INFO :PP0122] Preprocessing source file "t_select_little.v". + +[INFO :PP0122] Preprocessing source file "t_select_loop.v". + +[INFO :PP0122] Preprocessing source file "t_select_plus.v". + +[INFO :PP0122] Preprocessing source file "t_slice_struct_array_modport.v". + +[INFO :PP0122] Preprocessing source file "t_stop_bad.v". + +[INFO :PP0122] Preprocessing source file "t_stream.v". + +[INFO :PP0122] Preprocessing source file "t_var_types.v". + +[INFO :PP0122] Preprocessing source file "t_struct_portsel.v". + +[INFO :PP0122] Preprocessing source file "t_sys_file_basic.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem.v". + +[INFO :PP0122] Preprocessing source file "t_trace_decoration.v". + +[INFO :PP0122] Preprocessing source file "t_trace_ena.v". + +[INFO :PP0122] Preprocessing source file "t_trace_param.v". + +[INFO :PP0122] Preprocessing source file "t_trace_public.v". + +[INFO :PP0122] Preprocessing source file "t_tri_array_pull.v". + +[INFO :PP0122] Preprocessing source file "t_tri_gen.v". + +[INFO :PP0122] Preprocessing source file "t_tri_graph.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inout.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inz.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull01.v". + +[INFO :PP0122] Preprocessing source file "t_tri_various.v". + +[INFO :PP0122] Preprocessing source file "t_udp.v". + +[INFO :PP0122] Preprocessing source file "t_unoptflat_simple_2.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_complexcond.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_signed.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup2.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup2_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_escape.v". + +[INFO :PP0122] Preprocessing source file "t_var_local.v". + +[INFO :PP0122] Preprocessing source file "t_var_notfound_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_overcmp.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref_bad2.v". + +[INFO :PP0122] Preprocessing source file "t_var_rsvd_port.v". + +[INFO :PP0122] Preprocessing source file "t_var_static.v". + +[INFO :PP0122] Preprocessing source file "t_var_xref_gen.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_get.v". + +[INFO :PP0122] Preprocessing source file "t_wire_beh_bad.v". + +[INFO :PP0122] Preprocessing source file "t_xml_first.v". + +[INFO :PP0122] Preprocessing source file "t_xml_tag.v". + +[INFO :PP0122] Preprocessing source file "t_stream3.v". + +[INFO :PP0122] Preprocessing source file "t_struct_anon.v". + +[INFO :PP0122] Preprocessing source file "t_struct_init.v". + +[INFO :PP0122] Preprocessing source file "t_struct_packed_write_read.v". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu.v". + +[INFO :PP0122] Preprocessing source file "t_sys_file_scan.v". + +[INFO :PP0122] Preprocessing source file "t_sys_fread.v". + +[INFO :PP0122] Preprocessing source file "t_sys_plusargs_bad.v". + +[INFO :PP0122] Preprocessing source file "t_sys_rand.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_addr.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_end.v". + +[INFO :PP0122] Preprocessing source file "t_sys_sformat.v". + +[INFO :PP0122] Preprocessing source file "t_threads_counter.v". + +[INFO :PP0122] Preprocessing source file "t_trace_array.v". + +[INFO :PP0122] Preprocessing source file "t_trace_cat.v". + +[INFO :PP0122] Preprocessing source file "t_trace_complex.v". + +[INFO :PP0122] Preprocessing source file "t_trace_primitive.v". + +[INFO :PP0122] Preprocessing source file "t_trace_string.v". + +[INFO :PP0122] Preprocessing source file "t_tri_dangle.v". + +[INFO :PP0122] Preprocessing source file "t_tri_eqcase.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pullup.v". + +[INFO :PP0122] Preprocessing source file "t_tri_unconn.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_signed.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_bound.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_combo.v". + +[INFO :PP0122] Preprocessing source file "t_vams_basic.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_hide.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_hide2.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_sameas.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_sv.v". + +[INFO :PP0122] Preprocessing source file "t_var_const.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_in_assign_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_init.v". + +[INFO :PP0122] Preprocessing source file "t_var_nonamebegin.v". + +[INFO :PP0122] Preprocessing source file "t_var_outoforder.v". + +[INFO :PP0122] Preprocessing source file "t_var_pinsizes.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref_bad1.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref_bad3.v". + +[INFO :PP0122] Preprocessing source file "t_var_rsvd.v". + +[INFO :PP0122] Preprocessing source file "t_var_suggest_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_tieout.v". + +[INFO :PP0122] Preprocessing source file "t_var_vec_sel.v". + +[INFO :PP0122] Preprocessing source file "t_verilated_all.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_memory.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_var.v". + +[ERROR:PP0102] t_sv_cpu_code/ports.sv:44 Unknown macro "PACKED". + +[ERROR:PP0102] t_sv_cpu_code/ports.sv:49 Unknown macro "PACKED". + +[INFO :PP0123] Preprocessing include file "rom.sv". + +[ERROR:PP0101] t_sv_cpu_code/program_h.sv:31 Cannot open include file "rom.sv". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:18 Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:19 Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:20 Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:21 Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:23 Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:24 Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:25 Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:26 Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:28 Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:29 Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:30 Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:31 Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:33 Unknown macro "JMP". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv:35 Unknown macro "EOP". + +[INFO :PP0123] Preprocessing include file "verilated.v". + +[ERROR:PP0101] t_case_write1.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_case_write1.v:37 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_case_write1.v:38 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_case_write1_tasks.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0101] t_case_write2.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_case_write2.v:37 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_case_write2.v:38 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_case_write2_tasks.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0118] t_display.v:13 Unknown escaped sequence '\2'. + +[ERROR:PP0118] t_display_esc_bad.v:8 Unknown escaped sequence '\y'. + +[ERROR:PP0118] t_display_esc_bad.v:8 Unknown escaped sequence '\z'. + +[INFO :PP0123] Preprocessing include file "t_dpi_accessors_macros_inc.vh". + +[INFO :PP0123] Preprocessing include file "t_dpi_accessors_inc.vh". + +[ERROR:PP0102] t_dpi_display.v:11 Unknown macro "error". + +[ERROR:PP0102] t_dpi_sys.v:15 Unknown macro "error". + +[ERROR:PP0102] t_dpi_threads.v:19 Unknown macro "error". + +[ERROR:PP0102] t_dpi_var.v:66 Unknown macro "systemc_imp_header". + +[ERROR:PP0102] t_dpi_var.v:69 Unknown macro "verilog". + +[ERROR:PP0102] t_extend_class.v:48 Unknown macro "systemc_header". + +[ERROR:PP0102] t_extend_class.v:50 Unknown macro "systemc_interface". + +[ERROR:PP0102] t_extend_class.v:52 Unknown macro "systemc_ctor". + +[ERROR:PP0102] t_extend_class.v:54 Unknown macro "systemc_dtor". + +[ERROR:PP0102] t_extend_class.v:56 Unknown macro "verilog". + +[INFO :PP0123] Preprocessing include file "t_flag_f_tsub_inc.v". + +[ERROR:PP0101] t_flag_f.v:3 Cannot open include file "t_flag_f_tsub_inc.v". + +[NOTE :PP0105] t_func_flip.v:7 Multiply defined macro "INT_RANGE", + t_func_flip.v:6 previous definition. + +[ERROR:PP0102] t_gen_missing.v:13 Unknown macro "error". + +[INFO :PP0123] Preprocessing include file "t_initial_inc.vh". + +[ERROR:PP0102] t_interface_down_gen.v:75 Unknown macro "error". + +[ERROR:PP0120] t_lint_implicit_def_bad.v:21 Illegal directive in design element "`resetall". + +[INFO :PP0123] Preprocessing include file "t_lint_in_inc_bad_1.vh". + +[INFO :PP0123] Preprocessing include file "t_lint_in_inc_bad_2.vh". + +[INFO :PP0123] Preprocessing include file "/dev/null". + +[ERROR:PP0102] t_lint_unused.v:31 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_lint_unused.v:34 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0107] t_math_clog2.v:26 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:27 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:28 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:29 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:46 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:47 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:48 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:49 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:50 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:51 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:52 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:53 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:54 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:55 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:56 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:57 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v:58 Too many arguments (1) for macro "CLOG2", + t_math_clog2.v:9 macro definition takes 0. + +[WARNI:PP0113] t_math_signed5.v:11 Unused macro argument "vs". + +[INFO :PP0123] Preprocessing include file "t_pipe_filter_inc.vh". + +[ERROR:PP0115] t_pp_circdef_bad.v:9 Recursive macro definition for "SEL_NUM_BITS", + t_pp_circdef_bad.v:9 macro used in macro "SEL_NUM_BITS". + +[ERROR:PP0102] t_pp_circdef_bad.v:9 Unknown macro "SEL_NUM_BITS". + +[WARNI:PP0113] t_pp_display.v:20 Unused macro argument "left". + +[ERROR:PP0109] t_pp_display.v:34 Macro instantiation omits argument 1 (x) for "thru", + t_pp_display.v:17 No default value for argument 1 (x) in macro definition. + +[NOTE :PP0105] t_pp_dupdef.v:9 Multiply defined macro "DUP", + t_pp_dupdef.v:8 previous definition. + +[NOTE :PP0105] t_pp_dupdef.v:12 Multiply defined macro "DUPP", + t_pp_dupdef.v:11 previous definition. + +[INFO :PP0123] Preprocessing include file "t_pp_lib_inc.vh". + +[ERROR:PP0102] t_pp_lib_library.v:7 Unknown macro "WIDTH". + +[ERROR:PP0102] t_pp_misdef_bad.v:10 Unknown macro "NDEFINED". + +[ERROR:PP0102] t_pp_misdef_bad.v:13 Unknown macro "imescale". + +[ERROR:PP0102] t_pp_pragmas.v:7 Unknown macro "verilog". + +[ERROR:PP0102] t_pp_pragmas.v:40 Unknown macro "remove_gatenames". + +[ERROR:PP0102] t_pp_pragmas.v:42 Unknown macro "remove_netnames". + +[ERROR:PP0106] t_preproc.v:245 Syntax error: no viable alternative at input '`define\n', +Not a \`define + ^-- t_preproc.v:245 col:14. + +[ERROR:PP0106] t_preproc.v:284 Syntax error: no viable alternative at input '`define /* multi\t\\n\t line1*/', +`define /* multi \ + ^-- t_preproc.v:284 col:8. + +[ERROR:PP0106] t_preproc.v:475 Syntax error: no viable alternative at input '`define ESC(name) \', +`define ESC(name) \`CAT(name,suffix) + ^-- t_preproc.v:475 col:18. + +[INFO :PP0123] Preprocessing include file "t_preproc_inc2.vh". + +[INFO :PP0123] Preprocessing include file "<t_preproc_inc3.vh>". + +[ERROR:PP0101] t_preproc_inc2.vh:6 Cannot open include file "<t_preproc_inc3.vh>". + +[ERROR:PP0112] t_preproc.v:74 Illegal space in between macro name "noparam" and open parenthesis. + +[NOTE :PP0105] t_preproc.v:99 Multiply defined macro "msg", + t_preproc.v:77 previous definition. + +[ERROR:PP0109] t_preproc.v:110 Macro instantiation omits argument 1 (x) for "thru", + t_preproc.v:97 No default value for argument 1 (x) in macro definition. + +[ERROR:PP0116] t_preproc.v:158 Illegal unterminated string. + +[INFO :PP0123] Preprocessing include file "t_preproc_inc4.vh". + +[ERROR:PP0112] t_preproc.v:218 Illegal space in between macro name "ARGPAR" and open parenthesis. + +[WARNI:PP0113] t_preproc.v:251 Unused macro argument "l". + +[ERROR:PP0102] t_preproc.v:263 Unknown macro "error". + +[ERROR:PP0102] t_preproc.v:266 Unknown macro "error". + +[ERROR:PP0102] t_preproc.v:293 Unknown macro "bug202". + +[ERROR:PP0107] t_preproc.v:307 Too many arguments (1) for macro "CMT1", + t_preproc.v:297 macro definition takes 0. + +[ERROR:PP0107] t_preproc.v:308 Too many arguments (1) for macro "CMT2", + t_preproc.v:298 macro definition takes 0. + +[ERROR:PP0107] t_preproc.v:309 Too many arguments (1) for macro "CMT3", + t_preproc.v:299 macro definition takes 0. + +[ERROR:PP0107] t_preproc.v:310 Too many arguments (1) for macro "CMT4", + t_preproc.v:301 macro definition takes 0. + +[ERROR:PP0107] t_preproc.v:311 Too many arguments (1) for macro "CMT5", + t_preproc.v:303 macro definition takes 0. + +[WARNI:PP0113] t_preproc.v:318 Unused macro argument "log". + +[WARNI:PP0113] t_preproc.v:372 Unused macro argument "d". + +[ERROR:PP0102] t_preproc.v:379 Unknown macro "REPEAT_". + +[WARNI:PP0103] t_preproc.v:386 Undefining an unknown macro "T_PREPROC_INC4". + +[WARNI:PP0103] t_preproc.v:396 Undefining an unknown macro "TEMP". + +[ERROR:PP0102] t_preproc.v:400 Unknown macro "error". + +[ERROR:PP0116] t_preproc.v:406 Illegal unterminated string. + +[WARNI:PP0114] t_preproc.v:418 Undefined macro argument "b". + +[ERROR:PP0102] t_preproc.v:442 Unknown macro "QA". + +[WARNI:PP0113] t_preproc.v:462 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:469 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:469 Unused macro argument "name2". + +[ERROR:PP0102] t_preproc.v:478 Unknown macro "ESC". + +[WARNI:PP0103] t_preproc.v:479 Undefining an unknown macro "ESC". + +[WARNI:PP0113] t_preproc.v:482 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:488 Unused macro argument "name". + +[ERROR:PP0102] t_preproc.v:491 Unknown macro "zzz". + +[WARNI:PP0113] t_preproc.v:495 Unused macro argument "name". + +[WARNI:PP0103] t_preproc.v:504 Undefining an unknown macro "UNKNOWN". + +[ERROR:PP0102] t_preproc.v:505 Unknown macro "UNKNOWN". + +[WARNI:PP0113] t_preproc.v:514 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:519 Unused macro argument "name". + +[WARNI:PP0113] t_preproc.v:543 Unused macro argument "foo". + +[WARNI:PP0114] t_preproc.v:547 Undefined macro argument "XXE_". + +[WARNI:PP0114] t_preproc.v:554 Undefined macro argument "XYE_". + +[WARNI:PP0114] t_preproc.v:561 Undefined macro argument "XXS_". + +[WARNI:PP0114] t_preproc.v:568 Undefined macro argument "XYS_". + +[ERROR:PP0102] t_preproc.v:617 Unknown macro "dbg_hdl". + +[WARNI:PP0113] t_preproc.v:620 Unused macro argument "LVL". + +[ERROR:PP0102] t_preproc.v:637 Unknown macro "SV_COV_START". + +[ERROR:PP0102] t_preproc.v:638 Unknown macro "SV_COV_STOP". + +[ERROR:PP0102] t_preproc.v:639 Unknown macro "SV_COV_RESET". + +[ERROR:PP0102] t_preproc.v:640 Unknown macro "SV_COV_CHECK". + +[ERROR:PP0102] t_preproc.v:641 Unknown macro "SV_COV_MODULE". + +[ERROR:PP0102] t_preproc.v:642 Unknown macro "SV_COV_HIER". + +[ERROR:PP0102] t_preproc.v:643 Unknown macro "SV_COV_ASSERTION". + +[ERROR:PP0102] t_preproc.v:644 Unknown macro "SV_COV_FSM_STATE". + +[ERROR:PP0102] t_preproc.v:645 Unknown macro "SV_COV_STATEMENT". + +[ERROR:PP0102] t_preproc.v:646 Unknown macro "SV_COV_TOGGLE". + +[ERROR:PP0102] t_preproc.v:647 Unknown macro "SV_COV_OVERFLOW". + +[ERROR:PP0102] t_preproc.v:648 Unknown macro "SV_COV_ERROR". + +[ERROR:PP0102] t_preproc.v:649 Unknown macro "SV_COV_NOCOV". + +[ERROR:PP0102] t_preproc.v:650 Unknown macro "SV_COV_OK". + +[ERROR:PP0102] t_preproc.v:651 Unknown macro "SV_COV_PARTIAL". + +[ERROR:PP0112] t_preproc_def09.v:60 Illegal space in between macro name "MACROPAREN" and open parenthesis. + +[INFO :PP0123] Preprocessing include file "t_preproc_inc_inc_bad.vh". + +[INFO :PP0123] Preprocessing include file "this_file_is_not_found.vh". + +[ERROR:PP0101] t_preproc_inc_notfound_bad.v:6 Cannot open include file "this_file_is_not_found.vh". + +[INFO :PP0123] Preprocessing include file "t_preproc_persist_inc.v". + +[ERROR:PP0102] t_preproc_undefineall.v:9 Unknown macro "error". + +[ERROR:PP0102] t_preproc_undefineall.v:14 Unknown macro "error". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv". + +[ERROR:PP0101] t_sys_file_basic.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_sys_file_basic.v:46 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_sys_file_scan.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_sys_file_scan.v:16 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_sys_fread.v:42 Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_sys_sformat.v:6 Cannot open include file "verilated.v". + +[ERROR:PP0102] t_tri_gate.v:36 Unknown macro "error". + +[WARNI:PP0113] t_var_types.v:182 Unused macro argument "zeroinit". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv". + +[INFO :PA0201] Parsing source file "/home/alain/surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ac.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/genbus_if.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/adrdec.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ac_dig.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/cpu.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ac_ana.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ports_h.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/rom.sv". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/chip.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pad_vdd.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pads_h.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/ports.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pad_gnd.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pad_gpio.sv". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pads.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pinout_h.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/program_h.sv". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/timescale.sv". + +[INFO :PA0201] Parsing source file "tsub/t_flag_f_tsub_inc.v". + +[INFO :PA0201] Parsing source file "t_a_first_cc.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_sv_cpu_code/pads_if.sv". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "tsub/t_flag_f_tsub.v". + +[INFO :PA0201] Parsing source file "t_EXAMPLE.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_alw_nosplit.v". + +[INFO :PA0201] Parsing source file "t_array_backw_index_bad.v". + +[INFO :PA0201] Parsing source file "t_array_compare.v". + +[INFO :PA0201] Parsing source file "t_array_mda.v". + +[INFO :PA0201] Parsing source file "t_array_query.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_array_rev.v". + +[INFO :PA0201] Parsing source file "t_arraysel_wide.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_assert_basic.v". + +[INFO :PA0201] Parsing source file "t_assert_comp_bad.v". + +[INFO :PA0201] Parsing source file "t_alw_combdly.v". + +[INFO :PA0201] Parsing source file "t_assert_dup_bad.v". + +[INFO :PA0201] Parsing source file "t_assert_elab.v". + +[INFO :PA0201] Parsing source file "t_alw_reorder.v". + +[INFO :PA0201] Parsing source file "t_alw_split_rst.v". + +[INFO :PA0201] Parsing source file "t_array_list_bad.v". + +[INFO :PA0201] Parsing source file "t_assert_property.v". + +[INFO :PA0201] Parsing source file "t_assert_question.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_alw_dly.v". + +[INFO :PA0201] Parsing source file "t_alw_split.v". + +[INFO :PA0201] Parsing source file "t_alw_splitord.v". + +[INFO :PA0201] Parsing source file "t_array_packed_sysfunct.v". + +[INFO :PA0201] Parsing source file "t_assign_inline.v". + +[INFO :PA0201] Parsing source file "t_bench_mux4k.v". + +[INFO :PA0201] Parsing source file "t_array_pattern_bad.v". + +[INFO :PA0201] Parsing source file "t_array_pattern_unpacked.v". + +[INFO :PA0201] Parsing source file "t_bitsel_struct2.v". + +[INFO :PA0201] Parsing source file "t_array_type_methods.v". + +[INFO :PA0201] Parsing source file "t_assert_casez.v". + +[INFO :PA0201] Parsing source file "t_assert_comp.v". + +[INFO :PA0201] Parsing source file "t_assert_cover.v". + +[INFO :PA0201] Parsing source file "t_case_default_bad.v". + +[INFO :PA0201] Parsing source file "t_case_dupitems.v". + +[INFO :PA0201] Parsing source file "t_case_huge_sub.v". + +[INFO :PA0201] Parsing source file "t_case_orig.v". + +[INFO :PA0201] Parsing source file "t_case_write1_tasks.v". + +[INFO :PA0201] Parsing source file "t_attr_parenstar.v". + +[INFO :PA0201] Parsing source file "t_bind.v". + +[INFO :PA0201] Parsing source file "t_bitsel_const_bad.v". + +[INFO :PA0201] Parsing source file "t_bitsel_enum.v". + +[INFO :PA0201] Parsing source file "t_bitsel_slice.v". + +[INFO :PA0201] Parsing source file "t_bitsel_wire_array_bad.v". + +[INFO :PA0201] Parsing source file "t_blocking.v". + +[INFO :PA0201] Parsing source file "t_case_genx_bad.v". + +[INFO :PA0201] Parsing source file "t_case_group.v". + +[INFO :PA0201] Parsing source file "t_case_huge_sub2.v". + +[INFO :PA0201] Parsing source file "t_case_huge_sub4.v". + +[INFO :PA0201] Parsing source file "t_case_inside.v". + +[INFO :PA0201] Parsing source file "t_case_itemwidth.v". + +[INFO :PA0201] Parsing source file "t_case_deep.v". + +[INFO :PA0201] Parsing source file "t_case_nest.v". + +[INFO :PA0201] Parsing source file "t_case_onehot.v". + +[INFO :PA0201] Parsing source file "t_case_wild.v". + +[INFO :PA0201] Parsing source file "t_case_reducer.v". + +[INFO :PA0201] Parsing source file "t_clk_concat4.v". + +[INFO :PA0201] Parsing source file "t_clk_concat6.v". + +[INFO :PA0201] Parsing source file "t_clk_condflop_nord.v". + +[INFO :PA0201] Parsing source file "t_case_write2_tasks.v". + +[INFO :PA0201] Parsing source file "t_clk_dsp.v". + +[INFO :PA0201] Parsing source file "t_clk_gater.v". + +[INFO :PA0201] Parsing source file "t_clk_latch.v". + +[INFO :PA0201] Parsing source file "t_clk_powerdn.v". + +[INFO :PA0201] Parsing source file "t_clk_scope_bad.v". + +[INFO :PA0201] Parsing source file "t_clk_vecgen1.v". + +[INFO :PA0201] Parsing source file "t_concat_large.v". + +[INFO :PA0201] Parsing source file "t_const.v". + +[INFO :PA0201] Parsing source file "t_const_bad.v". + +[INFO :PA0201] Parsing source file "t_const_dec_mixed_bad.v". + +[INFO :PA0201] Parsing source file "t_const_overflow_bad.v". + +[INFO :PA0201] Parsing source file "t_cover_sva_notflat.v". + +[INFO :PA0201] Parsing source file "t_cover_toggle.v". + +[INFO :PA0201] Parsing source file "t_dedupe_seq_logic.v". + +[INFO :PA0201] Parsing source file "t_detectarray_3.v". + +[INFO :PA0201] Parsing source file "t_display_bad.v". + +[INFO :PA0201] Parsing source file "t_display_esc_bad.v". + +[INFO :PA0201] Parsing source file "t_display_l.v". + +[INFO :PA0201] Parsing source file "t_display_mcd.v". + +[INFO :PA0201] Parsing source file "t_display_merge.v". + +[INFO :PA0201] Parsing source file "t_display_real.v". + +[INFO :PA0201] Parsing source file "t_display_realtime.v". + +[INFO :PA0201] Parsing source file "t_display_signed.v". + +[INFO :PA0201] Parsing source file "t_display_string.v". + +[INFO :PA0201] Parsing source file "t_display_wide.v". + +[INFO :PA0201] Parsing source file "t_dpi_context.v". + +[INFO :PA0201] Parsing source file "t_dpi_display.v". + +[INFO :PA0201] Parsing source file "t_dpi_dup_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_exp_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_export.v". + +[INFO :PA0201] Parsing source file "t_dpi_import.v". + +[INFO :PA0201] Parsing source file "t_dpi_shortcircuit.v". + +[INFO :PA0201] Parsing source file "t_enum_large_methods.v". + +[INFO :PA0201] Parsing source file "t_enum_overlap_bad.v". + +[INFO :PA0201] Parsing source file "t_enum_size.v". + +[INFO :PA0201] Parsing source file "t_extend_class.v". + +[INFO :PA0201] Parsing source file "t_enum_type_pins.v". + +[INFO :PA0201] Parsing source file "t_flag_csplit.v". + +[INFO :PA0201] Parsing source file "t_enumeration.v". + +[INFO :PA0201] Parsing source file "t_flag_f__3.v". + +[INFO :PA0201] Parsing source file "t_flag_fi.v". + +[INFO :PA0201] Parsing source file "t_flag_ldflags.v". + +[INFO :PA0201] Parsing source file "t_flag_nomod_bad.v". + +[INFO :PA0201] Parsing source file "t_flag_skipidentical.v". + +[INFO :PA0201] Parsing source file "t_flag_stats.v". + +[INFO :PA0201] Parsing source file "t_flag_topmodule.v". + +[INFO :PA0201] Parsing source file "t_flag_werror.v". + +[INFO :PA0201] Parsing source file "t_flag_woff.v". + +[INFO :PA0201] Parsing source file "t_flag_xinitial_unique.v". + +[INFO :PA0201] Parsing source file "t_for_comma_bad.v". + +[INFO :PA0201] Parsing source file "t_for_count.v". + +[INFO :PA0201] Parsing source file "t_foreach.v". + +[INFO :PA0201] Parsing source file "t_func_const_bad.v". + +[INFO :PA0201] Parsing source file "t_func_crc.v". + +[INFO :PA0201] Parsing source file "t_func_plog.v". + +[INFO :PA0201] Parsing source file "t_for_init_bug.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_func.v". + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[INFO :PA0201] Parsing source file "t_func_const2_bad.v". + +[INFO :PA0201] Parsing source file "t_func_regfirst.v". + +[INFO :PA0201] Parsing source file "t_func_const_packed_struct_bad.v". + +[INFO :PA0201] Parsing source file "t_func_task_bad.v". + +[INFO :PA0201] Parsing source file "t_func_tie_bad.v". + +[INFO :PA0201] Parsing source file "t_func_types.v". + +[INFO :PA0201] Parsing source file "t_func_wide.v". + +[INFO :PA0201] Parsing source file "t_func_const_struct_bad.v". + +[INFO :PA0201] Parsing source file "t_gate_elim.v". + +[INFO :PA0201] Parsing source file "t_gen_assign.v". + +[INFO :PA0201] Parsing source file "t_array_interface.v". + +[INFO :PA0201] Parsing source file "t_func_dotted.v". + +[INFO :PA0201] Parsing source file "t_array_pattern_2d.v". + +[INFO :PA0201] Parsing source file "t_array_pattern_packed.v". + +[INFO :PA0201] Parsing source file "t_gen_cond_const.v". + +[INFO :PA0201] Parsing source file "t_gen_for.v". + +[INFO :PA0201] Parsing source file "t_func_mlog2.v". + +[INFO :PA0201] Parsing source file "t_func_noinl.v". + +[INFO :PA0201] Parsing source file "t_func_paramed.v". + +[INFO :PA0201] Parsing source file "t_func_rand.v". + +[INFO :PA0201] Parsing source file "t_func_real_abs.v". + +[INFO :PA0201] Parsing source file "t_func_return.v". + +[INFO :PA0201] Parsing source file "t_func_twocall.v". + +[INFO :PA0201] Parsing source file "t_func_v.v". + +[INFO :PA0201] Parsing source file "t_func_while.v". + +[INFO :PA0201] Parsing source file "t_gate_basic.v". + +[INFO :PA0201] Parsing source file "t_gen_intdot.v". + +[INFO :PA0201] Parsing source file "t_gate_implicit.v". + +[INFO :PA0201] Parsing source file "t_gen_cond_bitrange.v". + +[INFO :PA0201] Parsing source file "t_gen_lsb.v". + +[INFO :PA0201] Parsing source file "t_gen_upscope.v". + +[INFO :PA0201] Parsing source file "t_iff.v". + +[INFO :PA0201] Parsing source file "t_embed1.v". + +[INFO :PA0201] Parsing source file "t_initial_dlyass.v". + +[INFO :PA0201] Parsing source file "t_inside_wild.v". + +[INFO :PA0201] Parsing source file "t_emit_constw.v". + +[INFO :PA0201] Parsing source file "t_inst_array.v". + +[INFO :PA0201] Parsing source file "t_gen_for1.v". + +[INFO :PA0201] Parsing source file "t_gen_forif.v". + +[INFO :PA0201] Parsing source file "t_inst_ccall.v". + +[INFO :PA0201] Parsing source file "t_inst_darray.v". + +[INFO :PA0201] Parsing source file "t_inst_first_b.v". + +[INFO :PA0201] Parsing source file "t_inst_misarray_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_mism.v". + +[INFO :PA0201] Parsing source file "t_inst_overwide.v". + +[INFO :PA0201] Parsing source file "t_inst_prepost.v". + +[INFO :PA0201] Parsing source file "t_inst_signed.v". + +[INFO :PA0201] Parsing source file "t_flag_debugi9.v". + +[INFO :PA0201] Parsing source file "t_flag_errorlimit_bad.v". + +[INFO :PA0201] Parsing source file "t_flag_f.v". + +[INFO :PA0201] Parsing source file "t_flag_language.v". + +[INFO :PA0201] Parsing source file "t_flag_names.v". + +[INFO :PA0201] Parsing source file "t_inst_v2k.v". + +[INFO :PA0201] Parsing source file "t_flag_parameter.v". + +[INFO :PA0201] Parsing source file "t_interface1.v". + +[INFO :PA0201] Parsing source file "t_interface_array.v". + +[INFO :PA0201] Parsing source file "t_for_funcbound.v". + +[INFO :PA0201] Parsing source file "t_for_local.v". + +[INFO :PA0201] Parsing source file "t_interface_array_nocolon_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_down.v". + +[INFO :PA0201] Parsing source file "t_interface_dups.v". + +[INFO :PA0201] Parsing source file "t_interface_gen8.v". + +[INFO :PA0201] Parsing source file "t_func_bad.v". + +[INFO :PA0201] Parsing source file "t_func_bad2.v". + +[INFO :PA0201] Parsing source file "t_func_bad_width.v". + +[INFO :PA0201] Parsing source file "t_func_check.v". + +[INFO :PA0201] Parsing source file "t_func_const3_bad.v". + +[INFO :PA0201] Parsing source file "t_func_const_packed_array_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_missing_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_modport_import.v". + +[INFO :PA0201] Parsing source file "t_interface_param1.v". + +[INFO :PA0201] Parsing source file "t_func_const_packed_struct_bad2.v". + +[INFO :PA0201] Parsing source file "t_interface_param_another_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_size_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_twod.v". + +[INFO :PA0201] Parsing source file "t_langext_2.v". + +[INFO :PA0201] Parsing source file "t_lint_blksync_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_bsspace_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_colonplus_bad.v". + +[INFO :PA0201] Parsing source file "t_func_defaults.v". + +[INFO :PA0201] Parsing source file "t_gen_intdot2.v". + +[INFO :PA0201] Parsing source file "t_func_first.v". + +[INFO :PA0201] Parsing source file "t_func_flip.v". + +[INFO :PA0201] Parsing source file "t_func_gen.v". + +[INFO :PA0201] Parsing source file "t_lint_comb_use.v". + +[INFO :PA0201] Parsing source file "t_lint_implicit.v". + +[INFO :PA0201] Parsing source file "t_lint_implicit_port.v". + +[INFO :PA0201] Parsing source file "t_lint_infinite.v". + +[INFO :PA0201] Parsing source file "t_lint_latch_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_once_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_pkg_colon_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_restore_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unsized_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unsup_deassign.v". + +[INFO :PA0201] Parsing source file "t_lint_unused_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unused_iface_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_width_genfor.v". + +[INFO :PA0201] Parsing source file "t_math_clog2.v". + +[INFO :PA0201] Parsing source file "t_math_concat0.v". + +[INFO :PA0201] Parsing source file "t_math_concat_sel_bad.v". + +[INFO :PA0201] Parsing source file "t_math_div.v". + +[INFO :PA0201] Parsing source file "t_gen_var_bad.v". + +[INFO :PA0201] Parsing source file "t_genfor_hier.v". + +[INFO :PA0201] Parsing source file "t_func_grey.v". + +[INFO :PA0201] Parsing source file "t_func_named.v". + +[INFO :PA0201] Parsing source file "t_func_outp.v". + +[INFO :PA0201] Parsing source file "t_func_public.v". + +[INFO :PA0201] Parsing source file "t_genvar_misuse_bad.v". + +[INFO :PA0201] Parsing source file "t_hierarchy_identifier_bad.v". + +[INFO :PA0201] Parsing source file "t_func_under2.v". + +[INFO :PA0201] Parsing source file "t_func_void_bad.v". + +[INFO :PA0201] Parsing source file "t_gate_array.v". + +[INFO :PA0201] Parsing source file "t_gate_unsup.v". + +[INFO :PA0201] Parsing source file "t_math_div0.v". + +[INFO :PA0201] Parsing source file "t_math_divw.v". + +[INFO :PA0201] Parsing source file "t_gen_alw.v". + +[INFO :PA0201] Parsing source file "t_initarray_nonarray.v". + +[INFO :PA0201] Parsing source file "t_initial.v". + +[INFO :PA0201] Parsing source file "t_initial_edge.v". + +[INFO :PA0201] Parsing source file "t_gen_defparam.v". + +[INFO :PA0201] Parsing source file "t_inst_array_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_array_partial.v". + +[INFO :PA0201] Parsing source file "t_gen_div0.v". + +[INFO :PA0201] Parsing source file "t_inst_dff.v". + +[INFO :PA0201] Parsing source file "t_gen_for0.v". + +[INFO :PA0201] Parsing source file "t_gen_for_overlap.v". + +[INFO :PA0201] Parsing source file "t_gen_if.v". + +[INFO :PA0201] Parsing source file "t_gen_index.v". + +[INFO :PA0201] Parsing source file "t_inst_missing.v". + +[INFO :PA0201] Parsing source file "t_inst_notunsized.v". + +[INFO :PA0201] Parsing source file "t_math_pow.v". + +[INFO :PA0201] Parsing source file "t_gen_local.v". + +[INFO :PA0201] Parsing source file "t_gen_mislevel.v". + +[INFO :PA0201] Parsing source file "t_gen_missing.v". + +[INFO :PA0201] Parsing source file "t_math_precedence.v". + +[INFO :PA0201] Parsing source file "t_math_real_public.v". + +[INFO :PA0201] Parsing source file "t_inst_sv.v". + +[INFO :PA0201] Parsing source file "t_inst_wideconst.v". + +[INFO :PA0201] Parsing source file "t_interface1_modport.v". + +[INFO :PA0201] Parsing source file "t_interface_array_bad.v". + +[INFO :PA0201] Parsing source file "t_math_repl.v". + +[INFO :PA0201] Parsing source file "t_interface_array_modport.v". + +[INFO :PA0201] Parsing source file "t_interface_arraymux.v". + +[INFO :PA0201] Parsing source file "t_interface_gen.v". + +[INFO :PA0201] Parsing source file "t_interface_gen3.v". + +[INFO :PA0201] Parsing source file "t_gen_self_return.v". + +[INFO :PA0201] Parsing source file "t_interface_gen7.v". + +[INFO :PA0201] Parsing source file "t_interface_modport_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_modportlist.v". + +[INFO :PA0201] Parsing source file "t_interface_mp_func.v". + +[INFO :PA0201] Parsing source file "t_assert_synth.v". + +[INFO :PA0201] Parsing source file "t_bind2.v". + +[INFO :PA0201] Parsing source file "t_interface_param2.v". + +[INFO :PA0201] Parsing source file "t_interface_star.v". + +[INFO :PA0201] Parsing source file "t_interface_wrong_bad.v". + +[INFO :PA0201] Parsing source file "t_langext_3.v". + +[INFO :PA0201] Parsing source file "t_leak.v". + +[INFO :PA0201] Parsing source file "t_lint_blksync_loop.v". + +[INFO :PA0201] Parsing source file "t_lint_importstar_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_incabspath.v". + +[INFO :PA0201] Parsing source file "t_lint_inherit.v". + +[INFO :PA0201] Parsing source file "t_lint_only.v". + +[INFO :PA0201] Parsing source file "t_lint_pindup_bad.v". + +[INFO :PA0201] Parsing source file "t_bitsel_struct.v". + +[INFO :PA0201] Parsing source file "t_bitsel_struct3.v". + +[INFO :PA0201] Parsing source file "t_lint_syncasyncnet_bad.v". + +[INFO :PA0201] Parsing source file "t_case_66bits.v". + +[INFO :PA0201] Parsing source file "t_case_auto1.v". + +[INFO :PA0201] Parsing source file "t_case_huge.v". + +[INFO :PA0201] Parsing source file "t_case_huge_sub3.v". + +[INFO :PA0201] Parsing source file "t_math_arith.v". + +[INFO :PA0201] Parsing source file "t_case_write1.v". + +[INFO :PA0201] Parsing source file "t_case_write2.v". + +[INFO :PA0201] Parsing source file "t_case_x.v". + +[INFO :PA0201] Parsing source file "t_math_const.v". + +[INFO :PA0201] Parsing source file "t_case_x_bad.v". + +[INFO :PA0201] Parsing source file "t_case_zx_bad.v". + +[INFO :PA0201] Parsing source file "t_cast.v". + +[INFO :PA0201] Parsing source file "t_hierarchy_identifier.v". + +[INFO :PA0201] Parsing source file "t_math_eq.v". + +[INFO :PA0201] Parsing source file "t_math_imm.v". + +[INFO :PA0201] Parsing source file "t_init_concat.v". + +[INFO :PA0201] Parsing source file "t_inside.v". + +[INFO :PA0201] Parsing source file "t_math_pick.v". + +[INFO :PA0201] Parsing source file "t_inst_dtree.v". + +[INFO :PA0201] Parsing source file "t_inst_first_a.v". + +[INFO :PA0201] Parsing source file "t_inst_implicit.v". + +[INFO :PA0201] Parsing source file "t_inst_missing_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_mnpipe.v". + +[INFO :PA0201] Parsing source file "t_math_pow3.v". + +[INFO :PA0201] Parsing source file "t_inst_recurse2_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_recurse_bad.v". + +[INFO :PA0201] Parsing source file "t_inst_slice.v". + +[INFO :PA0201] Parsing source file "t_interface.v". + +[INFO :PA0201] Parsing source file "t_math_sign_extend.v". + +[INFO :PA0201] Parsing source file "t_math_signed5.v". + +[INFO :PA0201] Parsing source file "t_math_shift_over_bad.v". + +[INFO :PA0201] Parsing source file "t_math_shift_sel.v". + +[INFO :PA0201] Parsing source file "t_math_signed2.v". + +[INFO :PA0201] Parsing source file "t_interface_array_nocolon.v". + +[INFO :PA0201] Parsing source file "t_interface_down_gen.v". + +[INFO :PA0201] Parsing source file "t_math_signed4.v". + +[INFO :PA0201] Parsing source file "t_math_vliw.v". + +[INFO :PA0201] Parsing source file "t_mem_banks.v". + +[INFO :PA0201] Parsing source file "t_interface_gen10.v". + +[INFO :PA0201] Parsing source file "t_math_tri.v". + +[INFO :PA0201] Parsing source file "t_math_vgen.v". + +[INFO :PA0201] Parsing source file "t_interface_gen12.v". + +[INFO :PA0201] Parsing source file "t_cdc_async_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_gen4.v". + +[INFO :PA0201] Parsing source file "t_interface_gen5.v". + +[INFO :PA0201] Parsing source file "t_cellarray.v". + +[INFO :PA0201] Parsing source file "t_interface_mismodport_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_modport_export.v". + +[INFO :PA0201] Parsing source file "t_interface_nest.v". + +[INFO :PA0201] Parsing source file "t_interface_parameter_access.v". + +[INFO :PA0201] Parsing source file "t_chg_first.v". + +[INFO :PA0201] Parsing source file "t_clk_concat.v". + +[INFO :PA0201] Parsing source file "t_langext_order.v". + +[INFO :PA0201] Parsing source file "t_clk_concat2.v". + +[INFO :PA0201] Parsing source file "t_mem_first.v". + +[INFO :PA0201] Parsing source file "t_mem_iforder.v". + +[INFO :PA0201] Parsing source file "t_clk_concat3.v". + +[INFO :PA0201] Parsing source file "t_clk_concat5.v". + +[INFO :PA0201] Parsing source file "t_mem_multidim.v". + +[INFO :PA0201] Parsing source file "t_langext_order_sub.v". + +[INFO :PA0201] Parsing source file "t_lint_always_comb_iface.v". + +[INFO :PA0201] Parsing source file "t_lint_ifdepth_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_input_eq_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_mod_paren_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_multidriven_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_repeat_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_setout_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unused.v". + +[INFO :PA0201] Parsing source file "t_lint_width_bad.v". + +[INFO :PA0201] Parsing source file "t_clk_condflop.v". + +[INFO :PA0201] Parsing source file "t_clk_dpulse.v". + +[INFO :PA0201] Parsing source file "t_math_cmp.v". + +[INFO :PA0201] Parsing source file "t_math_cond_huge.v". + +[INFO :PA0201] Parsing source file "t_math_reverse.v". + +[INFO :PA0201] Parsing source file "t_clk_first.v". + +[INFO :PA0201] Parsing source file "t_math_shift_rep.v". + +[INFO :PA0201] Parsing source file "t_math_signed.v". + +[INFO :PA0201] Parsing source file "t_clk_gen.v". + +[INFO :PA0201] Parsing source file "t_clk_inp_init.v". + +[INFO :PA0201] Parsing source file "t_clk_latchgate.v". + +[INFO :PA0201] Parsing source file "t_clocker.v". + +[INFO :PA0201] Parsing source file "t_concat_large_bad.v". + +[INFO :PA0201] Parsing source file "t_concat_opt.v". + +[INFO :PA0201] Parsing source file "t_mem_slice_bad.v". + +[INFO :PA0201] Parsing source file "t_math_signed6.v". + +[INFO :PA0201] Parsing source file "t_math_signed7.v". + +[INFO :PA0201] Parsing source file "t_mem_slice_dtype_bad.v". + +[INFO :PA0201] Parsing source file "t_math_svl.v". + +[INFO :PA0201] Parsing source file "t_math_trig.v". + +[INFO :PA0201] Parsing source file "t_metacmt_onoff.v". + +[INFO :PA0201] Parsing source file "t_mod_interface_array.v". + +[INFO :PA0201] Parsing source file "t_cover_line.v". + +[INFO :PA0201] Parsing source file "t_mod_longname.v". + +[INFO :PA0201] Parsing source file "t_order.v". + +[INFO :PA0201] Parsing source file "t_order_doubleloop.v". + +[INFO :PA0201] Parsing source file "t_crazy_sel.v". + +[INFO :PA0201] Parsing source file "t_order_wireloop.v". + +[INFO :PA0201] Parsing source file "t_package_abs.v". + +[INFO :PA0201] Parsing source file "t_dedupe_clk_gate.v". + +[INFO :PA0201] Parsing source file "t_delay.v". + +[INFO :PA0201] Parsing source file "t_detectarray_1.v". + +[INFO :PA0201] Parsing source file "t_mem_file.v". + +[INFO :PA0201] Parsing source file "t_detectarray_2.v". + +[INFO :PA0201] Parsing source file "t_display.v". + +[INFO :PA0201] Parsing source file "t_display_time.v". + +[INFO :PA0201] Parsing source file "t_dos.v". + +[INFO :PA0201] Parsing source file "t_dpi_2exp_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_accessors.v". + +[INFO :PA0201] Parsing source file "t_package_dimport.v". + +[INFO :PA0201] Parsing source file "t_mem_multi_io2.v". + +[INFO :PA0201] Parsing source file "t_mem_multi_ref_bad.v". + +[INFO :PA0201] Parsing source file "t_mem_packed.v". + +[INFO :PA0201] Parsing source file "t_mem_multi_io3.v". + +[INFO :PA0201] Parsing source file "t_package_twodeep.v". + +[INFO :PA0201] Parsing source file "t_param_array.v". + +[INFO :PA0201] Parsing source file "t_param_concat.v". + +[INFO :PA0201] Parsing source file "t_param_default_bad.v". + +[INFO :PA0201] Parsing source file "t_param_first_b.v". + +[INFO :PA0201] Parsing source file "t_param_if_blk.v". + +[INFO :PA0201] Parsing source file "t_mem_packed_assign.v". + +[INFO :PA0201] Parsing source file "t_mem_packed_bad.v". + +[INFO :PA0201] Parsing source file "t_mem_slice.v". + +[INFO :PA0201] Parsing source file "t_mem_slot.v". + +[INFO :PA0201] Parsing source file "t_mod_dup_bad.v". + +[INFO :PA0201] Parsing source file "t_mod_interface_array1.v". + +[INFO :PA0201] Parsing source file "t_mod_nomod.v". + +[INFO :PA0201] Parsing source file "t_mod_recurse1.v". + +[INFO :PA0201] Parsing source file "t_multitop_sig.v". + +[INFO :PA0201] Parsing source file "t_optm_redor.v". + +[INFO :PA0201] Parsing source file "t_order_b.v". + +[INFO :PA0201] Parsing source file "t_order_clkinst.v". + +[INFO :PA0201] Parsing source file "t_order_multidriven.v". + +[INFO :PA0201] Parsing source file "t_mod_dup_ign.v". + +[INFO :PA0201] Parsing source file "t_mod_interface_array2.v". + +[INFO :PA0201] Parsing source file "t_mod_recurse.v". + +[INFO :PA0201] Parsing source file "t_param_array3.v". + +[INFO :PA0201] Parsing source file "t_dpi_imp_gen.v". + +[INFO :PA0201] Parsing source file "t_param_bit_sel.v". + +[INFO :PA0201] Parsing source file "t_param_circ_bad.v". + +[INFO :PA0201] Parsing source file "t_param_const_part.v". + +[INFO :PA0201] Parsing source file "t_param_first.v". + +[INFO :PA0201] Parsing source file "t_dpi_lib.v". + +[INFO :PA0201] Parsing source file "t_dpi_logic_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_name_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_open.v". + +[INFO :PA0201] Parsing source file "t_order_a.v". + +[INFO :PA0201] Parsing source file "t_order_comboloop.v". + +[INFO :PA0201] Parsing source file "t_order_first.v". + +[INFO :PA0201] Parsing source file "t_order_quad.v". + +[INFO :PA0201] Parsing source file "t_param_package.v". + +[INFO :PA0201] Parsing source file "t_package.v". + +[INFO :PA0201] Parsing source file "t_param_named.v". + +[INFO :PA0201] Parsing source file "t_param_no_parentheses.v". + +[INFO :PA0201] Parsing source file "t_param_repl.v". + +[INFO :PA0201] Parsing source file "t_param_real.v". + +[INFO :PA0201] Parsing source file "t_param_shift.v". + +[INFO :PA0201] Parsing source file "t_param_scope_bad.v". + +[INFO :PA0201] Parsing source file "t_param_sel.v". + +[INFO :PA0201] Parsing source file "t_param_type.v". + +[INFO :PA0201] Parsing source file "t_param_value.v". + +[INFO :PA0201] Parsing source file "t_package_enum.v". + +[INFO :PA0201] Parsing source file "t_param_wide_io.v". + +[INFO :PA0201] Parsing source file "t_parse_delay.v". + +[INFO :PA0201] Parsing source file "t_past_bad.v". + +[INFO :PA0201] Parsing source file "t_pp_circdef_bad.v". + +[INFO :PA0201] Parsing source file "t_pp_dupdef.v". + +[INFO :PA0201] Parsing source file "t_pp_lib.v". + +[INFO :PA0201] Parsing source file "t_pp_misdef_bad.v". + +[INFO :PA0201] Parsing source file "t_pp_underline_bad.v". + +[INFO :PA0201] Parsing source file "t_preproc_def09.v". + +[INFO :PA0201] Parsing source file "t_preproc_persist2.v". + +[INFO :PA0201] Parsing source file "t_preproc_ttempty.v". + +[INFO :PA0201] Parsing source file "t_program.v". + +[INFO :PA0201] Parsing source file "t_reloop_cam.v". + +[INFO :PA0201] Parsing source file "t_dpi_openfirst.v". + +[INFO :PA0201] Parsing source file "t_dpi_openreg_bad.v". + +[INFO :PA0201] Parsing source file "t_package_param.v". + +[INFO :PA0201] Parsing source file "t_param.v". + +[INFO :PA0201] Parsing source file "t_param_ceil.v". + +[INFO :PA0201] Parsing source file "t_dpi_qw.v". + +[INFO :PA0201] Parsing source file "t_dpi_shortcircuit2.v". + +[INFO :PA0201] Parsing source file "t_pipe_filter.v". + +[INFO :PA0201] Parsing source file "t_pp_lib_library.v". + +[INFO :PA0201] Parsing source file "t_pp_pragmas.v". + +[INFO :PA0201] Parsing source file "t_preproc_inc_notfound_bad.v". + +[INFO :PA0201] Parsing source file "t_dpi_string.v". + +[INFO :PA0201] Parsing source file "t_preproc_kwd.v". + +[INFO :PA0201] Parsing source file "t_select_index.v". + +[INFO :PA0201] Parsing source file "t_select_index2.v". + +[INFO :PA0201] Parsing source file "t_dpi_sys.v". + +[INFO :PA0201] Parsing source file "t_dpi_threads.v". + +[INFO :PA0201] Parsing source file "t_param_ddeep_width.v". + +[INFO :PA0201] Parsing source file "t_dpi_vams.v". + +[INFO :PA0201] Parsing source file "t_dpi_var.v". + +[INFO :PA0201] Parsing source file "t_param_first_a.v". + +[INFO :PA0201] Parsing source file "t_param_local.v". + +[INFO :PA0201] Parsing source file "t_param_mem_attr.v". + +[INFO :PA0201] Parsing source file "t_param_module.v". + +[INFO :PA0201] Parsing source file "t_select_lhs_oob2.v". + +[INFO :PA0201] Parsing source file "t_real_param.v". + +[INFO :PA0201] Parsing source file "t_param_named_2.v". + +[INFO :PA0201] Parsing source file "t_param_public.v". + +[INFO :PA0201] Parsing source file "t_param_real2.v". + +[INFO :PA0201] Parsing source file "t_select_param.v". + +[INFO :PA0201] Parsing source file "t_embed1_child.v". + +[INFO :PA0201] Parsing source file "t_embed1_wrap.v". + +[INFO :PA0201] Parsing source file "t_enum.v". + +[INFO :PA0201] Parsing source file "t_enum_bad_hide.v". + +[INFO :PA0201] Parsing source file "t_enum_func.v". + +[INFO :PA0201] Parsing source file "t_enum_int.v". + +[INFO :PA0201] Parsing source file "t_enum_name2.v". + +[INFO :PA0201] Parsing source file "t_enum_name3.v". + +[INFO :PA0201] Parsing source file "t_enum_public.v". + +[INFO :PA0201] Parsing source file "t_param_seg.v". + +[INFO :PA0201] Parsing source file "t_rnd.v". + +[INFO :PA0201] Parsing source file "t_enum_type_methods.v". + +[INFO :PA0201] Parsing source file "t_scope_map.v". + +[INFO :PA0201] Parsing source file "t_param_sel_range.v". + +[INFO :PA0201] Parsing source file "t_select_bad_msb.v". + +[INFO :PA0201] Parsing source file "t_select_bad_range.v". + +[INFO :PA0201] Parsing source file "t_select_bad_range2.v". + +[INFO :PA0201] Parsing source file "t_select_bound2.v". + +[INFO :PA0201] Parsing source file "t_select_plusloop.v". + +[INFO :PA0201] Parsing source file "t_select_little.v". + +[INFO :PA0201] Parsing source file "t_param_type2.v". + +[INFO :PA0201] Parsing source file "t_param_up_bad.v". + +[INFO :PA0201] Parsing source file "t_param_while.v". + +[INFO :PA0201] Parsing source file "t_past.v". + +[INFO :PA0201] Parsing source file "t_select_loop.v". + +[INFO :PA0201] Parsing source file "t_select_plus.v". + +[INFO :PA0201] Parsing source file "t_stream2.v". + +[INFO :PA0201] Parsing source file "t_preproc.v". + +[INFO :PA0201] Parsing source file "t_select_set.v". + +[INFO :PA0201] Parsing source file "t_slice_cond.v". + +[INFO :PA0201] Parsing source file "t_string_type_methods.v". + +[INFO :PA0201] Parsing source file "t_stop_bad.v". + +[INFO :PA0201] Parsing source file "t_stream.v". + +[INFO :PA0201] Parsing source file "t_struct_param.v". + +[INFO :PA0201] Parsing source file "t_struct_pat_width.v". + +[INFO :PA0201] Parsing source file "t_slice_init.v". + +[INFO :PA0201] Parsing source file "t_struct_portsel.v". + +[INFO :PA0201] Parsing source file "t_struct_port.v". + +[INFO :PA0201] Parsing source file "t_struct_unpacked.v". + +[INFO :PA0201] Parsing source file "t_sv_bus_mux_demux.v". + +[INFO :PA0201] Parsing source file "t_stream3.v". + +[INFO :PA0201] Parsing source file "t_struct_anon.v". + +[INFO :PA0201] Parsing source file "t_struct_array.v". + +[INFO :PA0201] Parsing source file "t_trace_fst.v". + +[INFO :PA0201] Parsing source file "t_trace_timescale.v". + +[INFO :PA0201] Parsing source file "t_tri_array_pull.v". + +[INFO :PA0201] Parsing source file "t_tri_eqcase.v". + +[INFO :PA0201] Parsing source file "t_struct_init.v". + +[INFO :PA0201] Parsing source file "t_tri_pull2_bad.v". + +[INFO :PA0201] Parsing source file "t_tri_pull_bad.v". + +[INFO :PA0201] Parsing source file "t_tri_pullvec_bad.v". + +[INFO :PA0201] Parsing source file "t_tri_select_unsized.v". + +[INFO :PA0201] Parsing source file "t_type_param.v". + +[INFO :PA0201] Parsing source file "t_sv_conditional.v". + +[INFO :PA0201] Parsing source file "t_struct_nest.v". + +[INFO :PA0201] Parsing source file "t_struct_notfound_bad.v". + +[INFO :PA0201] Parsing source file "t_struct_packed_value_list.v". + +[INFO :PA0201] Parsing source file "t_struct_unaligned.v". + +[INFO :PA0201] Parsing source file "t_struct_unpacked_bad.v". + +[INFO :PA0201] Parsing source file "t_sv_cpu.v". + +[INFO :PA0201] Parsing source file "t_sys_file_scan.v". + +[INFO :PA0201] Parsing source file "t_sys_fread.v". + +[INFO :PA0201] Parsing source file "t_trace_cat.v". + +[INFO :PA0201] Parsing source file "t_trace_decoration.v". + +[INFO :PA0201] Parsing source file "t_trace_ena.v". + +[INFO :PA0201] Parsing source file "t_trace_packed_struct.v". + +[INFO :PA0201] Parsing source file "t_sys_plusargs_bad.v". + +[INFO :PA0201] Parsing source file "t_sys_rand.v". + +[INFO :PA0201] Parsing source file "t_trace_primitive.v". + +[INFO :PA0201] Parsing source file "t_trace_string.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem_bad_addr.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem_bad_digit.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem_bad_end.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem_bad_notfound.v". + +[INFO :PA0201] Parsing source file "t_typedef_port.v". + +[INFO :PA0201] Parsing source file "t_sys_sformat.v". + +[INFO :PA0201] Parsing source file "t_unopt_array.v". + +[INFO :PA0201] Parsing source file "t_table_fsm.v". + +[INFO :PA0201] Parsing source file "t_trace_param.v". + +[INFO :PA0201] Parsing source file "t_trace_scstruct.v". + +[INFO :PA0201] Parsing source file "t_tri_array.v". + +[INFO :PA0201] Parsing source file "t_tri_gate.v". + +[INFO :PA0201] Parsing source file "t_unoptflat_simple_2.v". + +[INFO :PA0201] Parsing source file "t_unroll_complexcond.v". + +[INFO :PA0201] Parsing source file "t_unroll_signed.v". + +[INFO :PA0201] Parsing source file "t_var_dup2.v". + +[INFO :PA0201] Parsing source file "t_var_dup_bad.v". + +[INFO :PA0201] Parsing source file "t_tri_dangle.v". + +[INFO :PA0201] Parsing source file "t_tri_gen.v". + +[INFO :PA0201] Parsing source file "t_tri_ifbegin.v". + +[INFO :PA0201] Parsing source file "t_var_in_assign_bad.v". + +[INFO :PA0201] Parsing source file "t_var_init.v". + +[INFO :PA0201] Parsing source file "t_tri_graph.v". + +[INFO :PA0201] Parsing source file "t_tri_inout.v". + +[INFO :PA0201] Parsing source file "t_tri_inz.v". + +[INFO :PA0201] Parsing source file "t_tri_pull01.v". + +[INFO :PA0201] Parsing source file "t_tri_various.v". + +[INFO :PA0201] Parsing source file "t_udp.v". + +[INFO :PA0201] Parsing source file "t_var_nonamebegin.v". + +[INFO :PA0201] Parsing source file "t_var_outoforder.v". + +[INFO :PA0201] Parsing source file "t_var_port2_bad.v". + +[INFO :PA0201] Parsing source file "t_tri_public.v". + +[INFO :PA0201] Parsing source file "t_var_port_bad.v". + +[INFO :PA0201] Parsing source file "t_var_ref.v". + +[INFO :PA0201] Parsing source file "t_tri_select.v". + +[INFO :PA0201] Parsing source file "t_typedef.v". + +[INFO :PA0201] Parsing source file "t_unoptflat_simple.v". + +[INFO :PA0201] Parsing source file "t_unpacked_array_order.v". + +[INFO :PA0201] Parsing source file "t_var_types_bad.v". + +[INFO :PA0201] Parsing source file "t_verilated_debug.v". + +[INFO :PA0201] Parsing source file "t_vpi_memory.v". + +[INFO :PA0201] Parsing source file "t_vpi_var.v". + +[INFO :PA0201] Parsing source file "t_typedef_array.v". + +[INFO :PA0201] Parsing source file "t_typedef_circ_bad.v". + +[INFO :PA0201] Parsing source file "t_typedef_param.v". + +[INFO :PA0201] Parsing source file "t_udp_noname.v". + +[INFO :PA0201] Parsing source file "t_uniqueif.v". + +[INFO :PA0201] Parsing source file "t_unopt_converge.v". + +[INFO :PA0201] Parsing source file "t_unopt_converge_initial.v". + +[INFO :PA0201] Parsing source file "t_unoptflat_simple_3.v". + +[INFO :PA0201] Parsing source file "t_unroll_forfor.v". + +[INFO :PA0201] Parsing source file "t_extend.v". + +[INFO :PA0201] Parsing source file "t_final.v". + +[INFO :PA0201] Parsing source file "t_flag_bboxsys.v". + +[INFO :PA0201] Parsing source file "t_var_assign_landr.v". + +[INFO :PA0201] Parsing source file "t_unroll_genf.v". + +[INFO :PA0201] Parsing source file "t_var_dotted.v". + +[INFO :PA0201] Parsing source file "t_vams_wreal.v". + +[INFO :PA0201] Parsing source file "t_var_const.v". + +[INFO :PA0201] Parsing source file "t_var_overzero.v". + +[INFO :PA0201] Parsing source file "t_var_suggest_bad.v". + +[INFO :PA0201] Parsing source file "t_var_types.v". + +[INFO :PA0201] Parsing source file "t_var_dup3.v". + +[INFO :PA0201] Parsing source file "t_var_in_assign.v". + +[INFO :PA0201] Parsing source file "t_var_life.v". + +[INFO :PA0201] Parsing source file "t_var_overwidth_bad.v". + +[INFO :PA0201] Parsing source file "t_var_pinsizes.v". + +[INFO :PA0201] Parsing source file "t_var_ref_bad1.v". + +[INFO :PA0201] Parsing source file "t_var_ref_bad2.v". + +[INFO :PA0201] Parsing source file "t_var_rsvd_port.v". + +[INFO :PA0201] Parsing source file "t_var_set_link.v". + +[INFO :PA0201] Parsing source file "t_var_tieout.v". + +[INFO :PA0201] Parsing source file "t_var_vec_sel.v". + +[INFO :PA0201] Parsing source file "t_verilated_all.v". + +[INFO :PA0201] Parsing source file "t_vpi_get.v". + +[INFO :PA0201] Parsing source file "t_wire_beh_bad.v". + +[INFO :PA0201] Parsing source file "t_xml_first.v". + +[INFO :PA0201] Parsing source file "t_xml_tag.v". + +[INFO :PA0201] Parsing source file "t_flag_debug_noleak.v". + +[INFO :PA0201] Parsing source file "t_flag_define.v". + +[INFO :PA0201] Parsing source file "t_flag_future.v". + +[INFO :PA0201] Parsing source file "t_flag_getenv.v". + +[INFO :PA0201] Parsing source file "t_flag_lib.v". + +[INFO :PA0201] Parsing source file "t_flag_libinc.v". + +[INFO :PA0201] Parsing source file "t_flag_relinc.v". + +[INFO :PA0201] Parsing source file "t_flag_topmod2_bad.v". + +[INFO :PA0201] Parsing source file "t_flag_topmodule_inline.v". + +[INFO :PA0201] Parsing source file "t_flag_wfatal.v". + +[INFO :PA0201] Parsing source file "t_flag_xinitial_0.v". + +[INFO :PA0201] Parsing source file "t_for_break.v". + +[INFO :PA0201] Parsing source file "t_for_loop.v". + +[INFO :PA0201] Parsing source file "t_func_begin2.v". + +[INFO :PA0201] Parsing source file "t_func_const.v". + +[INFO :PA0201] Parsing source file "t_func_default_warn.v". + +[INFO :PA0201] Parsing source file "t_func_endian.v". + +[INFO :PA0201] Parsing source file "t_func_graphcirc.v". + +[INFO :PA0201] Parsing source file "t_func_lib.v". + +[INFO :PA0201] Parsing source file "t_func_lib_sub.v". + +[INFO :PA0201] Parsing source file "t_func_numones.v". + +[INFO :PA0201] Parsing source file "t_func_outfirst.v". + +[INFO :PA0201] Parsing source file "t_func_range.v". + +[INFO :PA0201] Parsing source file "t_func_real_param.v". + +[INFO :PA0201] Parsing source file "t_func_sum.v". + +[INFO :PA0201] Parsing source file "t_func_under.v". + +[INFO :PA0201] Parsing source file "t_func_unit.v". + +[INFO :PA0201] Parsing source file "t_func_void.v". + +[INFO :PA0201] Parsing source file "t_func_wide_out_bad.v". + +[INFO :PA0201] Parsing source file "t_gate_delref.v". + +[INFO :PA0201] Parsing source file "t_gate_fdup.v". + +[INFO :PA0201] Parsing source file "t_gated_clk_1.v". + +[INFO :PA0201] Parsing source file "t_gen_cond_bitrange_bad.v". + +[INFO :PA0201] Parsing source file "t_gen_for2.v". + +[INFO :PA0201] Parsing source file "t_gen_for_shuffle.v". + +[INFO :PA0201] Parsing source file "t_gen_inc.v". + +[INFO :PA0201] Parsing source file "t_generate_fatal_bad.v". + +[INFO :PA0201] Parsing source file "t_hierarchy_unnamed.v". + +[INFO :PA0201] Parsing source file "t_if_deep.v". + +[INFO :PA0201] Parsing source file "t_inst_aport.v". + +[INFO :PA0201] Parsing source file "t_inst_comma.v". + +[INFO :PA0201] Parsing source file "t_inst_first.v". + +[INFO :PA0201] Parsing source file "t_inst_port_array.v". + +[INFO :PA0201] Parsing source file "t_inst_signed1.v". + +[INFO :PA0201] Parsing source file "t_inst_tree.v". + +[INFO :PA0201] Parsing source file "t_interface2.v". + +[INFO :PA0201] Parsing source file "t_interface_bind_public.v". + +[INFO :PA0201] Parsing source file "t_interface_gen11.v". + +[INFO :PA0201] Parsing source file "t_interface_gen2.v". + +[INFO :PA0201] Parsing source file "t_interface_gen6.v". + +[INFO :PA0201] Parsing source file "t_interface_gen9.v". + +[INFO :PA0201] Parsing source file "t_interface_modport.v". + +[INFO :PA0201] Parsing source file "t_interface_top_bad.v". + +[INFO :PA0201] Parsing source file "t_interface_typo_bad.v". + +[INFO :PA0201] Parsing source file "t_langext_1.v". + +[INFO :PA0201] Parsing source file "t_lint_always_comb_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_block_redecl_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_comb_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_declfilename.v". + +[INFO :PA0201] Parsing source file "t_lint_defparam.v". + +[INFO :PA0201] Parsing source file "t_lint_implicit_def_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_import_name_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_in_inc_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_literal_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_modport_dir_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_realcvt_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_rsvd_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_subout_bad.v". + +[INFO :PA0201] Parsing source file "t_lint_unsup_mixed.v". + +[INFO :PA0201] Parsing source file "t_lint_unused_iface.v". + +[INFO :PA0201] Parsing source file "t_lint_width.v". + +[INFO :PA0201] Parsing source file "t_lint_width_genfor_bad.v". + +[INFO :PA0201] Parsing source file "t_math_concat.v". + +[INFO :PA0201] Parsing source file "t_math_concat64.v". + +[INFO :PA0201] Parsing source file "t_math_equal.v". + +[INFO :PA0201] Parsing source file "t_math_imm2.v". + +[INFO :PA0201] Parsing source file "t_math_msvc_64.v". + +[INFO :PA0201] Parsing source file "t_math_mul.v". + +[INFO :PA0201] Parsing source file "t_math_pow2.v". + +[INFO :PA0201] Parsing source file "t_math_pow4.v". + +[INFO :PA0201] Parsing source file "t_math_pow5.v". + +[INFO :PA0201] Parsing source file "t_math_pow6.v". + +[INFO :PA0201] Parsing source file "t_math_real.v". + +[INFO :PA0201] Parsing source file "t_math_shift.v". + +[INFO :PA0201] Parsing source file "t_math_shiftrs.v". + +[INFO :PA0201] Parsing source file "t_math_signed3.v". + +[INFO :PA0201] Parsing source file "t_math_signed_wire.v". + +[INFO :PA0201] Parsing source file "t_math_strwidth.v". + +[INFO :PA0201] Parsing source file "t_math_svl2.v". + +[INFO :PA0201] Parsing source file "t_math_swap.v". + +[INFO :PA0201] Parsing source file "t_math_width.v". + +[INFO :PA0201] Parsing source file "t_mem.v". + +[INFO :PA0201] Parsing source file "t_mem_cond.v". + +[INFO :PA0201] Parsing source file "t_mem_fifo.v". + +[INFO :PA0201] Parsing source file "t_mem_func.v". + +[INFO :PA0201] Parsing source file "t_mem_multi_io.v". + +[INFO :PA0201] Parsing source file "t_mem_multiwire.v". + +[INFO :PA0201] Parsing source file "t_mem_shift.v". + +[INFO :PA0201] Parsing source file "t_mem_slice_conc_bad.v". + +[INFO :PA0201] Parsing source file "t_mem_twoedge.v". + +[INFO :PA0201] Parsing source file "t_multitop1.v". + +[INFO :PA0201] Parsing source file "t_multitop1s.v". + +[INFO :PA0201] Parsing source file "t_optm_if_array.v". + +[INFO :PA0201] Parsing source file "t_order_2d.v". + +[INFO :PA0201] Parsing source file "t_order_comboclkloop.v". + +[INFO :PA0201] Parsing source file "t_order_loop_bad.v". + +[INFO :PA0201] Parsing source file "t_order_multialways.v". + +[INFO :PA0201] Parsing source file "t_package_ddecl.v". + +[INFO :PA0201] Parsing source file "t_package_dot.v". + +[INFO :PA0201] Parsing source file "t_package_export.v". + +[INFO :PA0201] Parsing source file "t_package_verb.v". + +[INFO :PA0201] Parsing source file "t_param_array2.v". + +[INFO :PA0201] Parsing source file "t_param_avec.v". + +[INFO :PA0201] Parsing source file "t_param_chain.v". + +[INFO :PA0201] Parsing source file "t_param_default.v". + +[INFO :PA0201] Parsing source file "t_param_func.v". + +[INFO :PA0201] Parsing source file "t_param_long.v". + +[INFO :PA0201] Parsing source file "t_past_unsup_bad.v". + +[INFO :PA0201] Parsing source file "t_pp_display.v". + +[INFO :PA0201] Parsing source file "t_preproc_ifdef.v". + +[INFO :PA0201] Parsing source file "t_preproc_inc_bad.v". + +[INFO :PA0201] Parsing source file "t_preproc_noline.v". + +[INFO :PA0201] Parsing source file "t_preproc_persist.v". + +[INFO :PA0201] Parsing source file "t_preproc_persist_inc.v". + +[INFO :PA0201] Parsing source file "t_preproc_undefineall.v". + +[INFO :PA0201] Parsing source file "t_repeat.v". + +[INFO :PA0201] Parsing source file "t_runflag.v". + +[INFO :PA0201] Parsing source file "t_runflag_seed.v". + +[INFO :PA0201] Parsing source file "t_savable.v". + +[INFO :PA0201] Parsing source file "t_select_bad_range3.v". + +[INFO :PA0201] Parsing source file "t_select_bad_tri.v". + +[INFO :PA0201] Parsing source file "t_select_bound1.v". + +[INFO :PA0201] Parsing source file "t_select_lhs_oob.v". + +[INFO :PA0201] Parsing source file "t_select_little_pack.v". + +[INFO :PA0201] Parsing source file "t_select_negative.v". + +[INFO :PA0201] Parsing source file "t_select_runtime_range.v". + +[INFO :PA0201] Parsing source file "t_slice_struct_array_modport.v". + +[INFO :PA0201] Parsing source file "t_static_elab.v". + +[INFO :PA0201] Parsing source file "t_string.v". + +[INFO :PA0201] Parsing source file "t_struct_packed_sysfunct.v". + +[INFO :PA0201] Parsing source file "t_struct_packed_write_read.v". + +[INFO :PA0201] Parsing source file "t_sys_file_basic.v". + +[INFO :PA0201] Parsing source file "t_sys_plusargs.v". + +[INFO :PA0201] Parsing source file "t_sys_readmem.v". + +[INFO :PA0201] Parsing source file "t_sys_system.v". + +[INFO :PA0201] Parsing source file "t_sys_time.v". + +[INFO :PA0201] Parsing source file "t_threads_counter.v". + +[INFO :PA0201] Parsing source file "t_trace_array.v". + +[INFO :PA0201] Parsing source file "t_trace_complex.v". + +[INFO :PA0201] Parsing source file "t_trace_public.v". + +[INFO :PA0201] Parsing source file "t_tri_array_bufif.v". + +[INFO :PA0201] Parsing source file "t_tri_inout2.v". + +[INFO :PA0201] Parsing source file "t_tri_pullup.v". + +[INFO :PA0201] Parsing source file "t_tri_unconn.v". + +[INFO :PA0201] Parsing source file "t_typedef_signed.v". + +[INFO :PA0201] Parsing source file "t_unopt_bound.v". + +[INFO :PA0201] Parsing source file "t_unopt_combo.v". + +[INFO :PA0201] Parsing source file "t_vams_basic.v". + +[INFO :PA0201] Parsing source file "t_var_bad_hide.v". + +[INFO :PA0201] Parsing source file "t_var_bad_hide2.v". + +[INFO :PA0201] Parsing source file "t_var_bad_sameas.v". + +[INFO :PA0201] Parsing source file "t_var_bad_sv.v". + +[INFO :PA0201] Parsing source file "t_var_const_bad.v". + +[INFO :PA0201] Parsing source file "t_var_dup2_bad.v". + +[INFO :PA0201] Parsing source file "t_var_escape.v". + +[INFO :PA0201] Parsing source file "t_var_local.v". + +[INFO :PA0201] Parsing source file "t_var_notfound_bad.v". + +[INFO :PA0201] Parsing source file "t_var_overcmp.v". + +[INFO :PA0201] Parsing source file "t_var_ref_bad3.v". + +[INFO :PA0201] Parsing source file "t_var_rsvd.v". + +[INFO :PA0201] Parsing source file "t_var_static.v". + +[INFO :PA0201] Parsing source file "t_var_xref_gen.v". + +[INFO :PA0201] Parsing source file "t_vlt_warn.v". + +[INFO :PA0201] Parsing source file "t_vpi_sc.v". + +[INFO :PA0201] Parsing source file "t_vpi_unimpl.v". + +[INFO :PA0201] Parsing source file "t_wire_types.v". + +[ERROR:PA0207] t_sv_cpu_code/ports.sv:39 Syntax error: extraneous input 'SURELOG_MACRO_NOT_DEFINED:PACKED!!!' expecting {'{', 'packed'}, + struct SURELOG_MACRO_NOT_DEFINED:PACKED!!! + ^-- ./slpp_unit/work/t_sv_cpu_code/ports.sv:39 col:9. + +[ERROR:PA0207] t_sv_cpu_code/rom.sv:18 Syntax error: no viable alternative at input ''{\n SURELOG_MACRO_NOT_DEFINED:LDI!!!', + SURELOG_MACRO_NOT_DEFINED:LDI!!! + ^-- ./slpp_unit/work/t_sv_cpu_code/rom.sv:18 col:6. + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:18 Unknown macro "LDI". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:19 Unknown macro "LDI". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:20 Unknown macro "LDI". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:21 Unknown macro "LDI". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:23 Unknown macro "STS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:24 Unknown macro "STS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:25 Unknown macro "STS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:26 Unknown macro "STS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:28 Unknown macro "LDS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:29 Unknown macro "LDS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:30 Unknown macro "LDS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:31 Unknown macro "LDS". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:33 Unknown macro "JMP". + +[ERROR:PA0203] t_sv_cpu_code/rom.sv:35 Unknown macro "EOP". + +[ERROR:PA0207] t_attr_parenstar.v:32 Syntax error: no viable alternative at input '@ (*', + always @ (* + ^-- ./slpp_unit/work/t_attr_parenstar.v:32 col:12. + +[ERROR:PA0207] t_case_wild.v:64 Syntax error: no viable alternative at input 'casez (in[0])\n endcase', + endcase + ^-- ./slpp_unit/work/t_case_wild.v:64 col:6. + +[ERROR:PA0207] t_clk_concat2.v:80 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + input clk; + ^-- ./slpp_unit/work/t_clk_concat2.v:80 col:3. + +[ERROR:PA0207] t_clk_concat5.v:83 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + input clk; + ^-- ./slpp_unit/work/t_clk_concat5.v:83 col:3. + +[ERROR:PA0207] t_clk_concat6.v:96 Syntax error: extraneous input 'input' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + input clk; + ^-- ./slpp_unit/work/t_clk_concat6.v:96 col:3. + +[ERROR:PA0207] t_const_dec_mixed_bad.v:8 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n parameter [200:0] MIXED = 32'dx_1', + parameter [200:0] MIXED = 32'dx_1; + ^-- ./slpp_unit/work/t_const_dec_mixed_bad.v:8 col:35. + +[ERROR:PA0207] t_dpi_display.v:10 Syntax error: no viable alternative at input 'module t ();\n\n SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion."', + SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls and sformat conversion." + ^-- ./slpp_unit/work/t_dpi_display.v:10 col:39. + +[ERROR:PA0203] t_dpi_display.v:10 Unknown macro "error". + +[ERROR:PA0207] t_dpi_sys.v:14 Syntax error: no viable alternative at input 'module t ();\n\n SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls."', + SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." + ^-- ./slpp_unit/work/t_dpi_sys.v:14 col:39. + +[ERROR:PA0203] t_dpi_sys.v:14 Unknown macro "error". + +[ERROR:PA0207] t_dpi_threads.v:18 Syntax error: extraneous input '"Only Verilator supports PLI-ish DPI calls."' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + SURELOG_MACRO_NOT_DEFINED:error!!! "Only Verilator supports PLI-ish DPI calls." + ^-- ./slpp_unit/work/t_dpi_threads.v:18 col:39. + +[ERROR:PA0203] t_dpi_threads.v:18 Unknown macro "error". + +[ERROR:PA0209] t_dpi_vams.v:7 Unsupported keyword set: "1800+VAMS". + +[ERROR:PA0207] t_dpi_var.v:64 Syntax error: no viable alternative at input 'module sub (/*AUTOARG*/\n // Outputs\n fr_a, fr_b, fr_chk,\n // Inputs\n in\n );\n\nSURELOG_MACRO_NOT_DEFINED:systemc_imp_header!!! \n void', + void mon_class_name(const char* namep); + ^-- ./slpp_unit/work/t_dpi_var.v:64 col:2. + +[ERROR:PA0203] t_dpi_var.v:63 Unknown macro "systemc_imp_header". + +[ERROR:PA0207] t_enum.v:33 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n\n localparam FIVE = 5;\n\n enum { e0,\n\t e1,\n\t e3=3,\n\t e5=FIVE,\n\t e10_[2] = 10,\n\t e12,\n\t e20_[5:7] = 25,\n\t e20_z,\n\t e30_[7:5] = 30,\n\t e30_z\n\t } EN;\n\n enum {\n\t z5 = e5\n\t } ZN;\n\n typedef enum [', + typedef enum [2:0] { ONES=~0 } three_t; + ^-- ./slpp_unit/work/t_enum.v:33 col:16. + +[ERROR:PA0207] t_enum_type_methods.v:13 Syntax error: no viable alternative at input 'enum [', + typedef enum [3:0] { + ^-- ./slpp_unit/work/t_enum_type_methods.v:13 col:16. + +[ERROR:PA0207] t_extend_class.v:49 Syntax error: extraneous input '#' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, +#include "t_extend_class_c.h" // Header for contained object +^-- ./slpp_unit/work/t_extend_class.v:49 col:0. + +[ERROR:PA0203] t_extend_class.v:48 Unknown macro "systemc_header". + +[ERROR:PA0203] t_extend_class.v:50 Unknown macro "systemc_interface". + +[ERROR:PA0203] t_extend_class.v:52 Unknown macro "systemc_ctor". + +[ERROR:PA0203] t_extend_class.v:54 Unknown macro "systemc_dtor". + +[ERROR:PA0203] t_extend_class.v:56 Unknown macro "verilog". + +[ERROR:PA0207] t_gen_missing.v:8 Syntax error: extraneous input '"Bad Test"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + SURELOG_MACRO_NOT_DEFINED:error!!! "Bad Test" + ^-- ./slpp_unit/work/t_gen_missing.v:8 col:37. + +[ERROR:PA0203] t_gen_missing.v:8 Unknown macro "error". + +[ERROR:PA0207] t_hierarchy_identifier.v:30 Syntax error: token recognition error at: '\', + if (cnt==SIZE) begin : \0escaped___name + ^-- ./slpp_unit/work/t_hierarchy_identifier.v:30 col:26. + +[ERROR:PA0207] t_inst_missing.v:10 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n wire ok = 1'b0;\n // verilator lint_off PINNOCONNECT\n // verilator lint_off PINCONNECTEMPTY\n sub sub (.ok(ok), ,', + sub sub (.ok(ok), , .nc()); + ^-- ./slpp_unit/work/t_inst_missing.v:10 col:21. + +[ERROR:PA0207] t_inst_missing_bad.v:8 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n wire ok = 1'b0;\n sub sub (.ok(ok), ,', + sub sub (.ok(ok), , .nc()); + ^-- ./slpp_unit/work/t_inst_missing_bad.v:8 col:21. + +[ERROR:PA0207] t_interface_down_gen.v:75 Syntax error: no viable alternative at input 'Commercial sims choke', +SURELOG_MACRO_NOT_DEFINED:error!!! Commercial sims choke on cross ref here + ^-- ./slpp_unit/work/t_interface_down_gen.v:75 col:52. + +[ERROR:PA0203] t_interface_down_gen.v:75 Unknown macro "error". + +[ERROR:PA0207] t_interface_modportlist.v:10 Syntax error: no viable alternative at input 'my_module m(.clk(clk), iface', + my_module m(.clk(clk), iface); + ^-- ./slpp_unit/work/t_interface_modportlist.v:10 col:26. + +[ERROR:PA0207] t_lint_bsspace_bad.v:11 Syntax error: no viable alternative at input 'blak\n\nmodule', +module t; +^-- ./slpp_unit/work/t_lint_bsspace_bad.v:11 col:0. + +[ERROR:PA0207] t_lint_implicit_def_bad.v:14 Syntax error: extraneous input '`default_nettype' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'input', 'output', 'inout', 'ref', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, +`default_nettype none +^-- ./slpp_unit/work/t_lint_implicit_def_bad.v:14 col:0. + +[ERROR:PA0207] t_lint_in_inc_bad_2.vh:8 Syntax error: mismatched input 'if' expecting '(', + if if if; + ^-- ./slpp_unit/work/t_lint_in_inc_bad.v:18 col:6. + +[ERROR:PA0207] t_lint_mod_paren_bad.v:12 Syntax error: mismatched input '(' expecting ';', + ) ( + ^-- ./slpp_unit/work/t_lint_mod_paren_bad.v:12 col:5. + +[ERROR:PA0207] t_lint_pindup_bad.v:14 Syntax error: no viable alternative at input 'sub\n #(,', + #(, // Not found + ^-- ./slpp_unit/work/t_lint_pindup_bad.v:14 col:7. + +[ERROR:PA0207] t_lint_pkg_colon_bad.v:7 Syntax error: mismatched input '::' expecting ';', + reg mispkgb::bar_t b; + ^-- ./slpp_unit/work/t_lint_pkg_colon_bad.v:7 col:14. + +[ERROR:PA0207] t_lint_rsvd_bad.v:7 Syntax error: mismatched input 'endconfig' expecting {'design', 'localparam'}, +endconfig +^-- ./slpp_unit/work/t_lint_rsvd_bad.v:7 col:0. + +[ERROR:PA0207] t_mem_multi_ref_bad.v:18 Syntax error: no viable alternative at input 'module t (/*AUTOARG*/);\n reg dimn;\n reg [1:0] dim0;\n reg [1:0] dim1 [1:0];\n reg [1:0] dim2 [1:0][1:0];\n reg dim0nv[1:0];\n\n initial begin\n dimn[1:0] = 0; // Bad: Not ranged\n dim0[1][1] = 0; // Bad: Not arrayed\n dim1[1][1][1] = 0; // Bad: Not arrayed to right depth\n dim2[1][1][1] = 0; // OK\n dim2[0 +: 1][', + dim2[0 +: 1][1] = 0; // Bad: Range on non-bits + ^-- ./slpp_unit/work/t_mem_multi_ref_bad.v:18 col:18. + +[ERROR:PA0207] t_mem_slice_bad.v:38 Syntax error: mismatched input '[' expecting '=', + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^-- ./slpp_unit/work/t_mem_slice_bad.v:38 col:30. + +[ERROR:PA0207] t_pipe_filter.v:10 Syntax error: no viable alternative at input 'example line 10', +example line 10; + ^-- ./slpp_unit/work/t_pipe_filter.v:10 col:13. + +[ERROR:PA0207] t_pp_circdef_bad.v:14 Syntax error: no viable alternative at input 'logic [12-SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!!', +typedef logic [12-SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! +: SURELOG_MACRO_NOT_DEFINED:SEL_NUM_BITS!!! -1:0] d_t; + ^-- ./slpp_unit/work/t_pp_circdef_bad.v:9 col:18. + +[ERROR:PA0203] t_pp_circdef_bad.v:14 Unknown macro "SEL_NUM_BITS". + +[ERROR:PA0207] t_pp_display.v:22 Syntax error: no viable alternative at input '$display("left side : \"right side \"" // The 'left' as the variable name shouldn't match the "left" in the `" string\n initial', + initial begin + ^-- ./slpp_unit/work/t_pp_display.v:24 col:3. + +[ERROR:PA0207] t_pp_lib_library.v:7 Syntax error: no viable alternative at input 'input [SURELOG_MACRO_NOT_DEFINED:WIDTH!!!', + input [SURELOG_MACRO_NOT_DEFINED:WIDTH!!! -1:0] a; + ^-- ./slpp_unit/work/t_pp_lib_library.v:7 col:10. + +[ERROR:PA0203] t_pp_lib_library.v:7 Unknown macro "WIDTH". + +[ERROR:PA0203] t_pp_misdef_bad.v:9 Unknown macro "NDEFINED". + +[ERROR:PA0203] t_pp_misdef_bad.v:12 Unknown macro "imescale". + +[ERROR:PA0203] t_pp_pragmas.v:7 Unknown macro "verilog". + +[ERROR:PA0203] t_pp_pragmas.v:40 Unknown macro "remove_gatenames". + +[ERROR:PA0203] t_pp_pragmas.v:42 Unknown macro "remove_netnames". + +[ERROR:PA0207] t_preproc.v:100 Syntax error: token recognition error at: '"twoline: \"first \n', +$display("twoline: \"first + ^-- ./slpp_unit/work/t_preproc.v:125 col:9. + +[ERROR:PA0207] t_preproc_def09.v:12 Syntax error: mismatched input ''' expecting <EOF>, +'initial $display("start", "msg1" , "msg2" , "end");' +^-- ./slpp_unit/work/t_preproc_def09.v:10 col:0. + +[ERROR:PA0207] t_preproc_inc_inc_bad.vh:10 Syntax error: no viable alternative at input 'xx // intentional error\n\nendmodule', +endmodule +^-- ./slpp_unit/work/t_preproc_inc_bad.v:17 col:0. + +[ERROR:PA0209] t_preproc_kwd.v:73 Unsupported keyword set: "VAMS-2.3". + +[ERROR:PA0207] t_preproc_noline.v:7 Syntax error: no viable alternative at input 'Hello in t_preproc_psl', +Hello in t_preproc_psl.v + ^-- ./slpp_unit/work/t_preproc_noline.v:7 col:9. + +[ERROR:PA0207] t_preproc_persist.v:6 Syntax error: no viable alternative at input 'Inside "t_preproc_persist.v"', +Inside "t_preproc_persist.v". + ^-- ./slpp_unit/work/t_preproc_persist.v:6 col:7. + +[ERROR:PA0207] t_preproc_persist2.v:6 Syntax error: no viable alternative at input 'Inside "t_preproc_persist2.v"', +Inside "t_preproc_persist2.v". + ^-- ./slpp_unit/work/t_preproc_persist2.v:6 col:7. + +[ERROR:PA0207] t_preproc_persist_inc.v:6 Syntax error: no viable alternative at input 'Inside "t_preproc_persist_inc.v"', + Inside "t_preproc_persist_inc.v". + ^-- ./slpp_unit/work/t_preproc_persist_inc.v:6 col:8. + +[ERROR:PA0207] t_preproc_undefineall.v:8 Syntax error: extraneous input '"Test setup error, PREDEF_COMMAND_LINE pre-missing"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, +SURELOG_MACRO_NOT_DEFINED:error!!! "Test setup error, PREDEF_COMMAND_LINE pre-missing" + ^-- ./slpp_unit/work/t_preproc_undefineall.v:8 col:36. + +[ERROR:PA0203] t_preproc_undefineall.v:8 Unknown macro "error". + +[ERROR:PA0203] t_preproc_undefineall.v:13 Unknown macro "error". + +[ERROR:PA0207] t_trace_primitive.v:34 Syntax error: extraneous input 'assign' expecting {'input', 'output', 'reg', '(*', 'table', 'initial'}, +assign b = ~a; +^-- ./slpp_unit/work/t_trace_primitive.v:34 col:0. + +[ERROR:PA0207] t_tri_gate.v:21 Syntax error: extraneous input '"Unknown test name"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + SURELOG_MACRO_NOT_DEFINED:error!!! "Unknown test name" + ^-- ./slpp_unit/work/t_tri_gate.v:21 col:37. + +[ERROR:PA0203] t_tri_gate.v:21 Unknown macro "error". + +[ERROR:PA0209] t_vams_basic.v:6 Unsupported keyword set: "VAMS-2.3". + +[ERROR:PA0209] t_vams_wreal.v:6 Unsupported keyword set: "VAMS-2.3". + +[ERROR:PA0207] t_var_dup_bad.v:65 Syntax error: extraneous input 'output' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'new', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'expect', 'not', 'or', 'and', 'sequence', 'covergroup', 'soft', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'do', 'restrict', 'let', 'this', DOLLAR_ROOT, 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED}, + output bad_reout_port; + ^-- ./slpp_unit/work/t_var_dup_bad.v:65 col:3. + +[INFO :PA0201] Parsing source file "t_altera_lpm.v". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:9 No timescale set for "package_bus". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:17 No timescale set for "package_str". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:22 No timescale set for "package_uni". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv:28 No timescale set for "sv_bus_mux_demux_wrap". + +[WARNI:PA0205] t_sv_cpu_code/ac.sv:8 No timescale set for "ac". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv:12 No timescale set for "sv_bus_mux_demux_mux". + +[WARNI:PA0205] t_sv_cpu_code/adrdec.sv:8 No timescale set for "adrdec". + +[WARNI:PA0205] t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv:11 No timescale set for "sv_bus_mux_demux_demux". + +[WARNI:PA0205] t_sv_cpu_code/genbus_if.sv:14 No timescale set for "genbus_if". + +[WARNI:PA0205] t_sv_cpu_code/ac_ana.sv:8 No timescale set for "ac_ana". + +[WARNI:PA0205] t_sv_cpu_code/chip.sv:12 No timescale set for "chip". + +[WARNI:PA0205] t_sv_cpu_code/pad_vdd.sv:12 No timescale set for "pad_vdd". + +[WARNI:PA0205] t_sv_cpu_code/ac_dig.sv:8 No timescale set for "ac_dig". + +[WARNI:PA0205] t_sv_cpu_code/pad_gnd.sv:12 No timescale set for "pad_gnd". + +[WARNI:PA0205] t_sv_cpu_code/pad_gpio.sv:12 No timescale set for "pad_gpio". + +[WARNI:PA0205] t_sv_cpu_code/cpu.sv:8 No timescale set for "cpu". + +[WARNI:PA0205] t_a_first_cc.v:6 No timescale set for "t". + +[WARNI:PA0205] t_sv_cpu_code/pads.sv:8 No timescale set for "pads". + +[WARNI:PA0205] t_sv_cpu_code/pads_if.sv:9 No timescale set for "pads_if". + +[WARNI:PA0205] t_sv_cpu_code/ports.sv:9 No timescale set for "ports". + +[WARNI:PA0205] t_EXAMPLE.v:78 No timescale set for "Test". + +[WARNI:PA0205] t_array_query.v:29 No timescale set for "array_test". + +[WARNI:PA0205] t_array_rev.v:42 No timescale set for "arr_rev". + +[WARNI:PA0205] t_array_list_bad.v:6 No timescale set for "pkg". + +[WARNI:PA0205] t_bench_mux4k.v:89 No timescale set for "mux4096". + +[WARNI:PA0205] t_bench_mux4k.v:103 No timescale set for "mux4096_1bit". + +[WARNI:PA0205] t_bench_mux4k.v:139 No timescale set for "mux64". + +[WARNI:PA0205] t_bench_mux4k.v:171 No timescale set for "drv". + +[WARNI:PA0205] t_case_huge_sub.v:6 No timescale set for "t_case_huge_sub". + +[WARNI:PA0205] t_bind.v:37 No timescale set for "InstModule". + +[WARNI:PA0205] t_bind.v:44 No timescale set for "Prog". + +[WARNI:PA0205] t_bind.v:48 No timescale set for "ExampInst". + +[WARNI:PA0205] t_bind.v:75 No timescale set for "Prog2". + +[WARNI:PA0205] t_bitsel_enum.v:6 No timescale set for "t_bitsel_enum". + +[WARNI:PA0205] t_case_huge_sub2.v:6 No timescale set for "t_case_huge_sub2". + +[WARNI:PA0205] t_case_huge_sub4.v:6 No timescale set for "t_case_huge_sub4". + +[WARNI:PA0205] t_case_inside.v:45 No timescale set for "sub". + +[WARNI:PA0205] t_case_itemwidth.v:91 No timescale set for "test". + +[WARNI:PA0205] t_case_reducer.v:120 No timescale set for "clz". + +[WARNI:PA0205] t_clk_concat4.v:7 No timescale set for "some_module". + +[WARNI:PA0205] t_clk_concat4.v:30 No timescale set for "t1". + +[WARNI:PA0205] t_clk_concat4.v:48 No timescale set for "t2". + +[WARNI:PA0205] t_clk_concat6.v:49 No timescale set for "ident". + +[WARNI:PA0205] t_clk_condflop_nord.v:69 No timescale set for "condff". + +[WARNI:PA0205] t_clk_condflop_nord.v:82 No timescale set for "condffimp". + +[WARNI:PA0205] t_clk_condflop_nord.v:104 No timescale set for "clockgate". + +[WARNI:PA0205] t_clk_dsp.v:78 No timescale set for "t_dspchip". + +[WARNI:PA0205] t_clk_dsp.v:119 No timescale set for "t_dspcore". + +[WARNI:PA0205] t_clk_dsp.v:145 No timescale set for "t_dsppla". + +[WARNI:PA0205] t_clk_scope_bad.v:26 No timescale set for "flop". + +[WARNI:PA0205] t_const_dec_mixed_bad.v:6 No timescale set for "MODULE NAME UNKNOWN". + +[WARNI:PA0205] t_cover_toggle.v:86 No timescale set for "alpha". + +[WARNI:PA0205] t_cover_toggle.v:125 No timescale set for "beta". + +[WARNI:PA0205] t_cover_toggle.v:142 No timescale set for "off". + +[WARNI:PA0205] t_dedupe_seq_logic.v:35 No timescale set for "l". + +[WARNI:PA0205] t_dedupe_seq_logic.v:44 No timescale set for "ll". + +[WARNI:PA0205] t_dedupe_seq_logic.v:53 No timescale set for "lll". + +[WARNI:PA0205] t_dedupe_seq_logic.v:59 No timescale set for "llr". + +[WARNI:PA0205] t_dedupe_seq_logic.v:65 No timescale set for "lr". + +[WARNI:PA0205] t_dedupe_seq_logic.v:71 No timescale set for "r". + +[WARNI:PA0205] t_dedupe_seq_logic.v:80 No timescale set for "rr". + +[WARNI:PA0205] t_dedupe_seq_logic.v:86 No timescale set for "rl". + +[WARNI:PA0205] t_dedupe_seq_logic.v:95 No timescale set for "rll". + +[WARNI:PA0205] t_dedupe_seq_logic.v:101 No timescale set for "rlr". + +[WARNI:PA0205] t_dedupe_seq_logic.v:107 No timescale set for "add". + +[WARNI:PA0205] t_dedupe_seq_logic.v:116 No timescale set for "add2". + +[WARNI:PA0205] t_case_write2_tasks.v:7 No timescale set for "t_case_write2_tasks". + +[WARNI:PA0205] verilated.v:2 No timescale set for "t_case_write1_tasks". + +[WARNI:PA0205] t_extend_class.v:33 No timescale set for "t_extend_class_v". + +[WARNI:PA0205] t_flag_topmodule.v:6 No timescale set for "a". + +[WARNI:PA0205] t_flag_topmodule.v:14 No timescale set for "a2". + +[WARNI:PA0205] t_flag_topmodule.v:21 No timescale set for "b". + +[WARNI:PA0205] t_flag_topmodule.v:25 No timescale set for "c". + +[WARNI:PA0205] t_flag_topmodule.v:32 No timescale set for "d". + +[WARNI:PA0205] t_func_const2_bad.v:17 No timescale set for "c9". + +[WARNI:PA0205] t_func_const2_bad.v:25 No timescale set for "b8". + +[WARNI:PA0205] t_func_regfirst.v:49 No timescale set for "f6". + +[WARNI:PA0205] t_func_wide.v:30 No timescale set for "muxtop". + +[WARNI:PA0205] t_gate_elim.v:66 No timescale set for "ta". + +[WARNI:PA0205] t_gate_elim.v:76 No timescale set for "tb". + +[WARNI:PA0205] t_gate_elim.v:86 No timescale set for "tc". + +[WARNI:PA0205] t_gate_elim.v:96 No timescale set for "td". + +[WARNI:PA0205] t_gate_elim.v:106 No timescale set for "te". + +[WARNI:PA0205] t_array_interface.v:6 No timescale set for "intf". + +[WARNI:PA0205] t_array_interface.v:12 No timescale set for "modify_interface". + +[WARNI:PA0205] t_gen_cond_const.v:45 No timescale set for "test_gen". + +[WARNI:PA0205] t_func_dotted.v:66 No timescale set for "global_mod". + +[WARNI:PA0205] t_func_dotted.v:76 No timescale set for "ma". + +[WARNI:PA0205] t_func_dotted.v:91 No timescale set for "mb". + +[WARNI:PA0205] t_func_dotted.v:119 No timescale set for "mc". + +[WARNI:PA0205] t_func_paramed.v:53 No timescale set for "extractor". + +[WARNI:PA0205] t_func_v.v:13 No timescale set for "level1". + +[WARNI:PA0205] t_func_v.v:23 No timescale set for "level2". + +[WARNI:PA0205] t_gen_for.v:54 No timescale set for "gencase". + +[WARNI:PA0205] t_gen_for.v:74 No timescale set for "paramed". + +[WARNI:PA0205] t_gen_for.v:129 No timescale set for "mbuf". + +[WARNI:PA0205] t_gen_for.v:136 No timescale set for "enflop". + +[WARNI:PA0205] t_gen_for.v:162 No timescale set for "enflop_one". + +[WARNI:PA0205] t_gate_implicit.v:78 No timescale set for "Mxor". + +[WARNI:PA0205] t_gen_intdot.v:45 No timescale set for "Generate". + +[WARNI:PA0205] t_gen_intdot.v:58 No timescale set for "Checker". + +[WARNI:PA0205] t_gen_intdot.v:77 No timescale set for "Genit". + +[WARNI:PA0205] t_gen_upscope.v:78 No timescale set for "tag". + +[WARNI:PA0205] t_gen_for1.v:42 No timescale set for "Testit". + +[WARNI:PA0205] t_gen_for1.v:68 No timescale set for "fnxtclk". + +[WARNI:PA0205] t_inst_darray.v:9 No timescale set for "the_intf". + +[WARNI:PA0205] t_inst_darray.v:26 No timescale set for "Contemplator". + +[WARNI:PA0205] t_inst_darray.v:44 No timescale set for "DeepThought". + +[WARNI:PA0205] t_inst_first_b.v:6 No timescale set for "t_inst_first_b". + +[WARNI:PA0205] t_inst_misarray_bad.v:20 No timescale set for "dut". + +[WARNI:PA0205] t_inst_misarray_bad.v:33 No timescale set for "suba". + +[WARNI:PA0205] t_inst_prepost.v:31 No timescale set for "ip". + +[WARNI:PA0205] t_inst_v2k.v:62 No timescale set for "hello". + +[WARNI:PA0205] t_interface1.v:8 No timescale set for "ifc". + +[WARNI:PA0205] t_for_funcbound.v:53 No timescale set for "strings". + +[WARNI:PA0205] t_interface_array.v:6 No timescale set for "foo_intf". + +[WARNI:PA0205] t_interface_array_nocolon_bad.v:12 No timescale set for "foo_subm". + +[WARNI:PA0205] t_interface_down.v:44 No timescale set for "wrapper". + +[WARNI:PA0205] t_interface_down.v:55 No timescale set for "lower". + +[WARNI:PA0205] t_interface_dups.v:88 No timescale set for "dti". + +[WARNI:PA0205] t_func_check.v:33 No timescale set for "chk". + +[WARNI:PA0205] t_func_const3_bad.v:15 No timescale set for "b9". + +[WARNI:PA0205] t_interface_missing_bad.v:11 No timescale set for "foo_mod". + +[WARNI:PA0205] t_interface_modport_import.v:8 No timescale set for "test_if". + +[WARNI:PA0205] t_interface_modport_import.v:42 No timescale set for "testmod". + +[WARNI:PA0205] t_interface_param1.v:21 No timescale set for "sub_test". + +[WARNI:PA0205] t_interface_param_another_bad.v:15 No timescale set for "simple_bus". + +[WARNI:PA0205] t_interface_size_bad.v:20 No timescale set for "baz". + +[WARNI:PA0205] t_gen_forif.v:67 No timescale set for "Test_wrap1". + +[WARNI:PA0205] t_gen_forif.v:75 No timescale set for "Test_wrap2". + +[WARNI:PA0205] t_lint_implicit_port.v:20 No timescale set for "set". + +[WARNI:PA0205] t_lint_implicit_port.v:27 No timescale set for "read". + +[WARNI:PA0205] t_lint_unused_iface_bad.v:6 No timescale set for "dummy_if". + +[WARNI:PA0205] t_gen_intdot2.v:38 No timescale set for "One". + +[WARNI:PA0205] t_func_grey.v:48 No timescale set for "t_func_grey2bin". + +[WARNI:PA0205] t_func_outp.v:48 No timescale set for "inv". + +[WARNI:PA0205] t_func_outp.v:56 No timescale set for "ftest". + +[WARNI:PA0205] t_func_outp.v:84 No timescale set for "mytop". + +[WARNI:PA0205] t_func_public.v:33 No timescale set for "tpub". + +[WARNI:PA0205] t_genfor_hier.v:7 No timescale set for "m1". + +[WARNI:PA0205] t_genvar_misuse_bad.v:7 No timescale set for "top". + +[WARNI:PA0205] t_gen_defparam.v:40 No timescale set for "m2". + +[WARNI:PA0205] t_gen_for_overlap.v:35 No timescale set for "sub1". + +[WARNI:PA0205] t_gen_for_overlap.v:40 No timescale set for "sub2". + +[WARNI:PA0205] t_inst_dff.v:109 No timescale set for "dff". + +[WARNI:PA0205] t_gen_index.v:41 No timescale set for "foo". + +[WARNI:PA0205] t_gen_index.v:62 No timescale set for "bar". + +[WARNI:PA0205] t_inst_notunsized.v:93 No timescale set for "Muxer". + +[WARNI:PA0205] t_inst_sv.v:61 No timescale set for "t_inst". + +[WARNI:PA0205] t_inst_wideconst.v:59 No timescale set for "wide". + +[WARNI:PA0205] t_interface_arraymux.v:32 No timescale set for "ThingMuxOH". + +[WARNI:PA0205] t_interface_arraymux.v:43 No timescale set for "Thinker". + +[WARNI:PA0205] t_gen_missing.v:12 No timescale set for "foobar". + +[WARNI:PA0205] t_gen_missing.v:45 No timescale set for "foo0". + +[WARNI:PA0205] t_interface_modport_bad.v:20 No timescale set for "counter_ansi". + +[WARNI:PA0205] t_interface_modportlist.v:13 No timescale set for "my_module". + +[WARNI:PA0205] t_interface_modportlist.v:20 No timescale set for "my_interface". + +[WARNI:PA0205] t_interface_param2.v:37 No timescale set for "mem". + +[WARNI:PA0205] t_interface_star.v:30 No timescale set for "counter_io". + +[WARNI:PA0205] t_interface_wrong_bad.v:11 No timescale set for "bar_intf". + +[WARNI:PA0205] t_lint_blksync_loop.v:44 No timescale set for "reg_1r1w". + +[WARNI:PA0205] t_lint_importstar_bad.v:6 No timescale set for "defs". + +[WARNI:PA0205] t_bind2.v:50 No timescale set for "targetmod". + +[WARNI:PA0205] t_bind2.v:66 No timescale set for "mycheck". + +[WARNI:PA0205] t_case_huge_sub3.v:6 No timescale set for "t_case_huge_sub3". + +[WARNI:PA0205] t_init_concat.v:59 No timescale set for "regfile". + +[WARNI:PA0205] t_math_imm.v:73 No timescale set for "example". + +[WARNI:PA0205] t_inst_dtree.v:19 No timescale set for "bmod". + +[WARNI:PA0205] t_inst_dtree.v:28 No timescale set for "cmod". + +[WARNI:PA0205] t_inst_dtree.v:38 No timescale set for "dmod". + +[WARNI:PA0205] t_inst_first_a.v:6 No timescale set for "t_inst_first_a". + +[WARNI:PA0205] t_inst_implicit.v:30 No timescale set for "subimp". + +[WARNI:PA0205] t_inst_mnpipe.v:42 No timescale set for "dffn". + +[WARNI:PA0205] t_inst_mnpipe.v:55 No timescale set for "MxN_pipeline". + +[WARNI:PA0205] t_inst_recurse2_bad.v:17 No timescale set for "looped". + +[WARNI:PA0205] t_inst_recurse_bad.v:21 No timescale set for "looped2". + +[WARNI:PA0205] t_interface.v:70 No timescale set for "handshake". + +[WARNI:PA0205] t_interface.v:109 No timescale set for "source". + +[WARNI:PA0205] t_interface.v:141 No timescale set for "drain". + +[WARNI:PA0205] t_math_vliw.v:58 No timescale set for "vliw". + +[WARNI:PA0205] t_interface_gen12.v:8 No timescale set for "foo_module". + +[WARNI:PA0205] t_interface_gen12.v:16 No timescale set for "bar_module". + +[WARNI:PA0205] t_cdc_async_bad.v:66 No timescale set for "Flop". + +[WARNI:PA0205] t_cdc_async_bad.v:78 No timescale set for "Sub". + +[WARNI:PA0205] t_interface_modport_export.v:45 No timescale set for "testmod_callee". + +[WARNI:PA0205] t_interface_modport_export.v:58 No timescale set for "testmod_caller". + +[WARNI:PA0205] t_interface_nest.v:6 No timescale set for "if1". + +[WARNI:PA0205] t_interface_nest.v:10 No timescale set for "if2". + +[WARNI:PA0205] t_interface_nest.v:15 No timescale set for "mod1". + +[WARNI:PA0205] t_cellarray.v:66 No timescale set for "drv1". + +[WARNI:PA0205] t_cellarray.v:73 No timescale set for "drv2". + +[WARNI:PA0205] t_cellarray.v:81 No timescale set for "drv3". + +[WARNI:PA0205] t_cellarray.v:91 No timescale set for "drv4". + +[WARNI:PA0205] t_chg_first.v:61 No timescale set for "t_chg_a". + +[WARNI:PA0205] t_mem_iforder.v:58 No timescale set for "fifo". + +[WARNI:PA0205] t_langext_order_sub.v:10 No timescale set for "t_langext_order_sub". + +[WARNI:PA0205] t_lint_always_comb_iface.v:6 No timescale set for "my_if". + +[WARNI:PA0205] t_lint_always_comb_iface.v:54 No timescale set for "my_module1". + +[WARNI:PA0205] t_lint_always_comb_iface.v:68 No timescale set for "my_module2". + +[WARNI:PA0205] t_lint_always_comb_iface.v:84 No timescale set for "my_module3". + +[WARNI:PA0205] t_lint_unused.v:51 No timescale set for "udp_mux2". + +[WARNI:PA0205] t_lint_width_bad.v:35 No timescale set for "p". + +[WARNI:PA0205] t_math_cmp.v:71 No timescale set for "prover". + +[WARNI:PA0205] t_clk_first.v:30 No timescale set for "t_clk". + +[WARNI:PA0205] t_clk_first.v:133 No timescale set for "t_clk_flop". + +[WARNI:PA0205] t_clk_first.v:151 No timescale set for "t_clk_two". + +[WARNI:PA0205] t_clk_first.v:175 No timescale set for "t_clk_twob". + +[WARNI:PA0205] t_clk_latchgate.v:97 No timescale set for "llq". + +[WARNI:PA0205] t_clk_latchgate.v:116 No timescale set for "ffq". + +[WARNI:PA0205] t_math_signed.v:164 No timescale set for "by_width". + +[WARNI:PA0205] t_mod_interface_array.v:8 No timescale set for "a_if". + +[WARNI:PA0205] t_mod_interface_array.v:14 No timescale set for "intf_source". + +[WARNI:PA0205] t_mod_interface_array.v:26 No timescale set for "intf_sink". + +[WARNI:PA0205] t_mod_longname.v:28 No timescale set for "modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie". + +[WARNI:PA0205] t_cover_line.v:114 No timescale set for "tsk". + +[WARNI:PA0205] t_dedupe_clk_gate.v:20 No timescale set for "flop_gated_latch". + +[WARNI:PA0205] t_dedupe_clk_gate.v:30 No timescale set for "flop_gated_flop". + +[WARNI:PA0205] t_dedupe_clk_gate.v:40 No timescale set for "clock_gate_latch". + +[WARNI:PA0205] t_dedupe_clk_gate.v:52 No timescale set for "clock_gate_flop". + +[WARNI:PA0205] t_package_abs.v:8 No timescale set for "functions". + +[WARNI:PA0205] t_mem_file.v:76 No timescale set for "file". + +[WARNI:PA0205] t_package_twodeep.v:8 No timescale set for "pkg2". + +[WARNI:PA0205] t_package_twodeep.v:12 No timescale set for "pkg1". + +[WARNI:PA0205] t_param_array.v:78 No timescale set for "checkstr". + +[WARNI:PA0205] t_param_default_bad.v:6 No timescale set for "m". + +[WARNI:PA0205] t_param_first_b.v:6 No timescale set for "t_param_first_b". + +[WARNI:PA0205] t_mem_multi_io3.v:34 No timescale set for "testio". + +[WARNI:PA0205] t_mem_slot.v:7 No timescale set for "t_mem_slot". + +[WARNI:PA0205] t_mod_recurse1.v:12 No timescale set for "rec". + +[WARNI:PA0205] t_mod_recurse1.v:28 No timescale set for "bottom". + +[WARNI:PA0205] t_order_b.v:6 No timescale set for "t_order_b". + +[WARNI:PA0205] t_order_clkinst.v:61 No timescale set for "comb_loop". + +[WARNI:PA0205] t_order_clkinst.v:90 No timescale set for "seq_loop". + +[WARNI:PA0205] t_order_multidriven.v:61 No timescale set for "FooWr". + +[WARNI:PA0205] t_order_multidriven.v:86 No timescale set for "FooRd". + +[WARNI:PA0205] t_order_multidriven.v:125 No timescale set for "FooMem". + +[WARNI:PA0205] t_order_multidriven.v:151 No timescale set for "FooMemImpl". + +[WARNI:PA0205] t_dpi_accessors.v:50 No timescale set for "test_sub". + +[WARNI:PA0205] t_mod_recurse.v:62 No timescale set for "PriorityChoice". + +[WARNI:PA0205] t_order_a.v:6 No timescale set for "t_order_a". + +[WARNI:PA0205] t_order_first.v:20 No timescale set for "t_netlist". + +[WARNI:PA0205] t_param_if_blk.v:71 No timescale set for "Nested". + +[WARNI:PA0205] t_param_named.v:29 No timescale set for "m3". + +[WARNI:PA0205] t_param_no_parentheses.v:66 No timescale set for "mnooverride". + +[WARNI:PA0205] t_param_package.v:12 No timescale set for "params". + +[WARNI:PA0205] t_param_package.v:16 No timescale set for "Test0". + +[WARNI:PA0205] t_param_package.v:21 No timescale set for "Test1". + +[WARNI:PA0205] t_param_real.v:6 No timescale set for "mod". + +[WARNI:PA0205] t_package.v:20 No timescale set for "p2". + +[WARNI:PA0205] t_param_type.v:54 No timescale set for "mod_typ". + +[WARNI:PA0205] t_pp_lib_library.v:6 No timescale set for "library_cell". + +[WARNI:PA0205] t_reloop_cam.v:95 No timescale set for "cam". + +[WARNI:PA0205] t_param_ddeep_width.v:13 No timescale set for "paramtest_WRAP". + +[WARNI:PA0205] t_param_ddeep_width.v:20 No timescale set for "paramtest_DFFRE". + +[WARNI:PA0205] t_param_first_a.v:6 No timescale set for "t_param_first_a". + +[WARNI:PA0205] t_param_mem_attr.v:34 No timescale set for "memory". + +[WARNI:PA0205] t_preproc_kwd.v:28 No timescale set for "v95". + +[WARNI:PA0205] t_preproc_kwd.v:34 No timescale set for "v01". + +[WARNI:PA0205] t_preproc_kwd.v:40 No timescale set for "v05". + +[WARNI:PA0205] t_preproc_kwd.v:46 No timescale set for "s05". + +[WARNI:PA0205] t_preproc_kwd.v:52 No timescale set for "s09". + +[WARNI:PA0205] t_preproc_kwd.v:58 No timescale set for "s12". + +[WARNI:PA0205] t_preproc_kwd.v:66 No timescale set for "s17". + +[WARNI:PA0205] t_preproc_kwd.v:74 No timescale set for "a23". + +[WARNI:PA0205] t_embed1_child.v:6 No timescale set for "t_embed1_child". + +[WARNI:PA0205] t_embed1_wrap.v:6 No timescale set for "t_embed1_wrap". + +[WARNI:PA0205] t_enum_name2.v:6 No timescale set for "our_pkg". + +[WARNI:PA0205] t_enum_name2.v:19 No timescale set for "our". + +[WARNI:PA0205] t_enum_public.v:6 No timescale set for "p3". + +[WARNI:PA0205] t_enum_public.v:12 No timescale set for "p62". + +[WARNI:PA0205] t_param_sel_range.v:15 No timescale set for "submod". + +[WARNI:PA0205] t_param_type2.v:6 No timescale set for "tt_pkg". + +[WARNI:PA0205] t_param_type2.v:31 No timescale set for "tt_buf". + +[WARNI:PA0205] t_param_up_bad.v:12 No timescale set for "child". + +[WARNI:PA0205] t_param_up_bad.v:18 No timescale set for "parent". + +[WARNI:PA0205] t_past.v:84 No timescale set for "Test2". + +[WARNI:PA0205] t_struct_param.v:7 No timescale set for "config_pkg". + +[WARNI:PA0205] t_struct_param.v:40 No timescale set for "struct_submodule". + +[WARNI:PA0205] t_struct_unpacked.v:6 No timescale set for "x". + +[WARNI:PA0205] t_tri_array_pull.v:6 No timescale set for "IOBUF". + +[WARNI:PA0205] t_struct_array.v:6 No timescale set for "TEST_TYPES". + +[WARNI:PA0205] t_sv_cpu.v:79 No timescale set for "testbench". + +[WARNI:PA0205] t_sv_conditional.v:62 No timescale set for "st3_testbench". + +[WARNI:PA0205] t_sv_conditional.v:145 No timescale set for "simple_test_3". + +[WARNI:PA0205] t_sv_conditional.v:230 No timescale set for "counterA". + +[WARNI:PA0205] t_sv_conditional.v:277 No timescale set for "counterB". + +[WARNI:PA0205] t_sv_conditional.v:311 No timescale set for "simple_test_3a". + +[WARNI:PA0205] t_sv_conditional.v:331 No timescale set for "simple_test_3b". + +[WARNI:PA0205] t_sv_conditional.v:363 No timescale set for "simple_test_3c". + +[WARNI:PA0205] t_sv_conditional.v:395 No timescale set for "simple_test_3d". + +[WARNI:PA0205] t_sv_conditional.v:425 No timescale set for "simple_test_3e". + +[WARNI:PA0205] t_sv_conditional.v:449 No timescale set for "simple_test_3f". + +[WARNI:PA0205] t_trace_primitive.v:31 No timescale set for "CINV". + +[WARNI:PA0205] t_type_param.v:15 No timescale set for "foo_wrapper". + +[WARNI:PA0205] t_typedef_port.v:78 No timescale set for "TestNonAnsi". + +[WARNI:PA0205] t_typedef_port.v:95 No timescale set for "TestAnsi". + +[WARNI:PA0205] t_trace_param.v:6 No timescale set for "my_funcs". + +[WARNI:PA0205] t_trace_param.v:14 No timescale set for "my_module_types". + +[WARNI:PA0205] t_tri_array.v:65 No timescale set for "Pad". + +[WARNI:PA0205] t_tri_gen.v:27 No timescale set for "updown". + +[WARNI:PA0205] t_tri_gen.v:39 No timescale set for "t_up". + +[WARNI:PA0205] t_tri_gen.v:42 No timescale set for "t_down". + +[WARNI:PA0205] t_var_dup_bad.v:46 No timescale set for "sub0". + +[WARNI:PA0205] t_var_dup_bad.v:68 No timescale set for "sub3". + +[WARNI:PA0205] t_tri_gate.v:15 No timescale set for "pass". + +[WARNI:PA0205] t_tri_gate.v:20 No timescale set for "tbuf". + +[WARNI:PA0205] t_tri_gate.v:24 No timescale set for "mux". + +[WARNI:PA0205] t_tri_inout.v:15 No timescale set for "io". + +[WARNI:PA0205] t_tri_pull01.v:71 No timescale set for "t_tri2". + +[WARNI:PA0205] t_tri_pull01.v:84 No timescale set for "t_tri3". + +[WARNI:PA0205] t_tri_various.v:146 No timescale set for "Test3". + +[WARNI:PA0205] t_tri_various.v:154 No timescale set for "Test4". + +[WARNI:PA0205] t_tri_various.v:159 No timescale set for "Test5". + +[WARNI:PA0205] t_tri_various.v:167 No timescale set for "Test6". + +[WARNI:PA0205] t_tri_various.v:173 No timescale set for "Test6a". + +[WARNI:PA0205] t_tri_various.v:177 No timescale set for "Test7". + +[WARNI:PA0205] t_var_port_bad.v:11 No timescale set for "subok". + +[WARNI:PA0205] t_tri_public.v:47 No timescale set for "sub_mod". + +[WARNI:PA0205] t_tri_select.v:35 No timescale set for "io_ring". + +[WARNI:PA0205] t_udp.v:115 No timescale set for "udp_latch". + +[WARNI:PA0205] t_udp.v:126 No timescale set for "udp_dff". + +[WARNI:PA0205] t_vpi_var.v:87 No timescale set for "arr". + +[WARNI:PA0205] t_udp_noname.v:35 No timescale set for "udp". + +[WARNI:PA0205] t_unoptflat_simple_3.v:41 No timescale set for "test1". + +[WARNI:PA0205] t_unoptflat_simple_3.v:60 No timescale set for "test2". + +[WARNI:PA0205] t_final.v:6 No timescale set for "submodule". + +[WARNI:PA0205] t_vams_wreal.v:87 No timescale set for "through". + +[WARNI:PA0205] t_vams_wreal.v:93 No timescale set for "within_range". + +[WARNI:PA0205] t_vams_wreal.v:106 No timescale set for "wreal_bus". + +[WARNI:PA0205] t_vams_wreal.v:114 No timescale set for "first_level". + +[WARNI:PA0205] t_vams_wreal.v:121 No timescale set for "second_level". + +[WARNI:PA0205] t_var_overzero.v:33 No timescale set for "tsub". + +[WARNI:PA0205] t_var_in_assign.v:59 No timescale set for "z". + +[WARNI:PA0205] t_xml_first.v:44 No timescale set for "mod2". + +[WARNI:PA0205] t_flag_libinc.v:6 No timescale set for "liblib_a". + +[WARNI:PA0205] t_flag_libinc.v:10 No timescale set for "liblib_b". + +[WARNI:PA0205] t_flag_libinc.v:17 No timescale set for "liblib_c". + +[WARNI:PA0205] t_flag_libinc.v:23 No timescale set for "liblib_d". + +[WARNI:PA0205] t_flag_topmod2_bad.v:6 No timescale set for "a_top". + +[WARNI:PA0205] t_flag_topmodule_inline.v:22 No timescale set for "l3". + +[WARNI:PA0205] t_func_begin2.v:6 No timescale set for "init". + +[WARNI:PA0205] t_func_const.v:6 No timescale set for "testpackage". + +[WARNI:PA0205] t_func_lib_sub.v:7 No timescale set for "BreadAddrDP". + +[WARNI:PA0205] t_func_lib_sub.v:56 No timescale set for "DecCountReg4". + +[WARNI:PA0205] t_gate_fdup.v:6 No timescale set for "fnor2". + +[WARNI:PA0205] t_generate_fatal_bad.v:15 No timescale set for "foo2". + +[WARNI:PA0205] t_inst_aport.v:65 No timescale set for "callee". + +[WARNI:PA0205] t_inst_tree.v:63 No timescale set for "ps". + +[WARNI:PA0205] t_inst_tree.v:69 No timescale set for "l1". + +[WARNI:PA0205] t_inst_tree.v:76 No timescale set for "l2". + +[WARNI:PA0205] t_inst_tree.v:92 No timescale set for "l4". + +[WARNI:PA0205] t_inst_tree.v:100 No timescale set for "l5". + +[WARNI:PA0205] t_interface2.v:72 No timescale set for "ifunused". + +[WARNI:PA0205] t_interface2.v:93 No timescale set for "counter_nansi". + +[WARNI:PA0205] t_interface2.v:104 No timescale set for "modunused". + +[WARNI:PA0205] t_interface_bind_public.v:6 No timescale set for "hex2ram_if". + +[WARNI:PA0205] t_interface_bind_public.v:69 No timescale set for "testharness_ext". + +[WARNI:PA0205] t_interface_bind_public.v:100 No timescale set for "SimpleTestHarness". + +[WARNI:PA0205] t_interface_modport.v:6 No timescale set for "counter_if". + +[WARNI:PA0205] t_interface_modport.v:103 No timescale set for "counter_ansi_m". + +[WARNI:PA0205] t_interface_modport.v:116 No timescale set for "counter_nansi_m". + +[WARNI:PA0205] t_lint_declfilename.v:10 No timescale set for "t_lint_declfilename". + +[WARNI:PA0205] t_math_imm2.v:13 No timescale set for "t_math_imm2". + +[WARNI:PA0205] t_math_pow4.v:43 No timescale set for "test004". + +[WARNI:PA0205] t_math_real.v:141 No timescale set for "sub_cast_bug374". + +[WARNI:PA0205] t_mem_multi_io.v:39 No timescale set for "has_array". + +[WARNI:PA0205] t_mem_multiwire.v:53 No timescale set for "inst". + +[WARNI:PA0205] t_mem_multiwire.v:75 No timescale set for "inst2". + +[WARNI:PA0205] t_mem_slice_conc_bad.v:68 No timescale set for "bbb". + +[WARNI:PA0205] t_mem_slice_conc_bad.v:101 No timescale set for "aaa". + +[WARNI:PA0205] t_multitop1s.v:6 No timescale set for "t_multitop1s". + +[WARNI:PA0205] t_multitop1s.v:10 No timescale set for "in_subfile". + +[WARNI:PA0205] t_package_dot.v:13 No timescale set for "csr_pkg". + +[WARNI:PA0205] t_package_export.v:14 No timescale set for "pkg10". + +[WARNI:PA0205] t_package_export.v:19 No timescale set for "pkg11". + +[WARNI:PA0205] t_package_export.v:23 No timescale set for "pkg20". + +[WARNI:PA0205] t_package_export.v:27 No timescale set for "pkg21". + +[WARNI:PA0205] t_package_export.v:31 No timescale set for "pkg30". + +[WARNI:PA0205] t_package_export.v:35 No timescale set for "pkg31". + +[WARNI:PA0205] t_package_verb.v:7 No timescale set for "verb_pkg". + +[WARNI:PA0205] t_param_long.v:94 No timescale set for "i". + +[WARNI:PA0205] t_preproc_inc_inc_bad.vh:6 No timescale set for "xx". + +[WARNI:PA0205] t_trace_public.v:32 No timescale set for "glbl". + +[WARNI:PA0205] t_trace_public.v:36 No timescale set for "neg". + +[WARNI:PA0205] t_trace_public.v:51 No timescale set for "little". + +[WARNI:PA0205] t_tri_inout2.v:59 No timescale set for "ChildA". + +[WARNI:PA0205] t_tri_inout2.v:73 No timescale set for "ChildB". + +[WARNI:PA0205] t_tri_pullup.v:24 No timescale set for "pullup_module". + +[WARNI:PA0205] t_tri_unconn.v:78 No timescale set for "t_tri0". + +[WARNI:PA0205] t_tri_unconn.v:90 No timescale set for "t_tri1". + +[WARNI:PA0205] t_var_notfound_bad.v:32 No timescale set for "subsub". + +[ERROR:PA0206] t_altera_lpm.v:60 Missing timeunit/timeprecision for "LPM_MEMORY_INITIALIZATION". + +[ERROR:PA0206] t_altera_lpm.v:1265 Missing timeunit/timeprecision for "LPM_HINT_EVALUATION". + +[ERROR:PA0206] t_altera_lpm.v:1375 Missing timeunit/timeprecision for "LPM_DEVICE_FAMILIES". + +[ERROR:PA0206] t_altera_lpm.v:1585 Missing timeunit/timeprecision for "lpm_constant". + +[ERROR:PA0206] t_altera_lpm.v:1636 Missing timeunit/timeprecision for "lpm_inv". + +[ERROR:PA0206] t_altera_lpm.v:1689 Missing timeunit/timeprecision for "lpm_and". + +[ERROR:PA0206] t_altera_lpm.v:1769 Missing timeunit/timeprecision for "lpm_or". + +[ERROR:PA0206] t_altera_lpm.v:1850 Missing timeunit/timeprecision for "lpm_xor". + +[ERROR:PA0206] t_altera_lpm.v:1979 Missing timeunit/timeprecision for "lpm_bustri". + +[ERROR:PA0206] t_altera_lpm.v:2065 Missing timeunit/timeprecision for "lpm_mux". + +[ERROR:PA0206] t_altera_lpm.v:2200 Missing timeunit/timeprecision for "lpm_decode". + +[ERROR:PA0206] t_altera_lpm.v:2328 Missing timeunit/timeprecision for "lpm_clshift". + +[ERROR:PA0206] t_altera_lpm.v:2613 Missing timeunit/timeprecision for "lpm_add_sub". + +[ERROR:PA0206] t_altera_lpm.v:2819 Missing timeunit/timeprecision for "lpm_compare". + +[ERROR:PA0206] t_altera_lpm.v:2993 Missing timeunit/timeprecision for "lpm_mult". + +[ERROR:PA0206] t_altera_lpm.v:3279 Missing timeunit/timeprecision for "lpm_divide". + +[ERROR:PA0206] t_altera_lpm.v:3486 Missing timeunit/timeprecision for "lpm_abs". + +[ERROR:PA0206] t_altera_lpm.v:3550 Missing timeunit/timeprecision for "lpm_counter". + +[ERROR:PA0206] t_altera_lpm.v:3836 Missing timeunit/timeprecision for "lpm_latch". + +[ERROR:PA0206] t_altera_lpm.v:3960 Missing timeunit/timeprecision for "lpm_ff". + +[ERROR:PA0206] t_altera_lpm.v:4179 Missing timeunit/timeprecision for "lpm_shiftreg". + +[ERROR:PA0206] t_altera_lpm.v:4383 Missing timeunit/timeprecision for "lpm_ram_dq". + +[ERROR:PA0206] t_altera_lpm.v:4639 Missing timeunit/timeprecision for "lpm_ram_dp". + +[ERROR:PA0206] t_altera_lpm.v:4930 Missing timeunit/timeprecision for "lpm_ram_io". + +[ERROR:PA0206] t_altera_lpm.v:5192 Missing timeunit/timeprecision for "lpm_rom". + +[ERROR:PA0206] t_altera_lpm.v:5407 Missing timeunit/timeprecision for "lpm_fifo". + +[ERROR:PA0206] t_altera_lpm.v:5738 Missing timeunit/timeprecision for "lpm_fifo_dc_dffpipe". + +[ERROR:PA0206] t_altera_lpm.v:5825 Missing timeunit/timeprecision for "lpm_fifo_dc_fefifo". + +[ERROR:PA0206] t_altera_lpm.v:6033 Missing timeunit/timeprecision for "lpm_fifo_dc_async". + +[ERROR:PA0206] t_altera_lpm.v:6470 Missing timeunit/timeprecision for "lpm_fifo_dc". + +[ERROR:PA0206] t_altera_lpm.v:6593 Missing timeunit/timeprecision for "lpm_inpad". + +[ERROR:PA0206] t_altera_lpm.v:6649 Missing timeunit/timeprecision for "lpm_outpad". + +[ERROR:PA0206] t_altera_lpm.v:6705 Missing timeunit/timeprecision for "lpm_bipad". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:9 Missing timeunit/timeprecision for "package_bus". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:17 Missing timeunit/timeprecision for "package_str". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv:22 Missing timeunit/timeprecision for "package_uni". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv:28 Missing timeunit/timeprecision for "sv_bus_mux_demux_wrap". + +[ERROR:PA0206] t_sv_cpu_code/ac.sv:8 Missing timeunit/timeprecision for "ac". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv:12 Missing timeunit/timeprecision for "sv_bus_mux_demux_mux". + +[ERROR:PA0206] t_sv_cpu_code/adrdec.sv:8 Missing timeunit/timeprecision for "adrdec". + +[ERROR:PA0206] t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv:11 Missing timeunit/timeprecision for "sv_bus_mux_demux_demux". + +[ERROR:PA0206] t_sv_cpu_code/genbus_if.sv:14 Missing timeunit/timeprecision for "genbus_if". + +[ERROR:PA0206] t_sv_cpu_code/ac_ana.sv:8 Missing timeunit/timeprecision for "ac_ana". + +[ERROR:PA0206] t_sv_cpu_code/chip.sv:12 Missing timeunit/timeprecision for "chip". + +[ERROR:PA0206] t_sv_cpu_code/pad_vdd.sv:12 Missing timeunit/timeprecision for "pad_vdd". + +[ERROR:PA0206] t_sv_cpu_code/ac_dig.sv:8 Missing timeunit/timeprecision for "ac_dig". + +[ERROR:PA0206] t_sv_cpu_code/pad_gnd.sv:12 Missing timeunit/timeprecision for "pad_gnd". + +[ERROR:PA0206] t_sv_cpu_code/pad_gpio.sv:12 Missing timeunit/timeprecision for "pad_gpio". + +[ERROR:PA0206] t_sv_cpu_code/cpu.sv:8 Missing timeunit/timeprecision for "cpu". + +[ERROR:PA0206] t_a_first_cc.v:6 Missing timeunit/timeprecision for "t". + +[ERROR:PA0206] t_sv_cpu_code/pads.sv:8 Missing timeunit/timeprecision for "pads". + +[ERROR:PA0206] t_sv_cpu_code/pads_if.sv:9 Missing timeunit/timeprecision for "pads_if". + +[ERROR:PA0206] t_sv_cpu_code/ports.sv:9 Missing timeunit/timeprecision for "ports". + +[ERROR:PA0206] t_EXAMPLE.v:78 Missing timeunit/timeprecision for "Test". + +[ERROR:PA0206] t_array_query.v:29 Missing timeunit/timeprecision for "array_test". + +[ERROR:PA0206] t_array_rev.v:42 Missing timeunit/timeprecision for "arr_rev". + +[ERROR:PA0206] t_array_list_bad.v:6 Missing timeunit/timeprecision for "pkg". + +[ERROR:PA0206] t_bench_mux4k.v:89 Missing timeunit/timeprecision for "mux4096". + +[ERROR:PA0206] t_bench_mux4k.v:103 Missing timeunit/timeprecision for "mux4096_1bit". + +[ERROR:PA0206] t_bench_mux4k.v:139 Missing timeunit/timeprecision for "mux64". + +[ERROR:PA0206] t_bench_mux4k.v:171 Missing timeunit/timeprecision for "drv". + +[ERROR:PA0206] t_case_huge_sub.v:6 Missing timeunit/timeprecision for "t_case_huge_sub". + +[ERROR:PA0206] t_bind.v:37 Missing timeunit/timeprecision for "InstModule". + +[ERROR:PA0206] t_bind.v:44 Missing timeunit/timeprecision for "Prog". + +[ERROR:PA0206] t_bind.v:48 Missing timeunit/timeprecision for "ExampInst". + +[ERROR:PA0206] t_bind.v:75 Missing timeunit/timeprecision for "Prog2". + +[ERROR:PA0206] t_bitsel_enum.v:6 Missing timeunit/timeprecision for "t_bitsel_enum". + +[ERROR:PA0206] t_case_huge_sub2.v:6 Missing timeunit/timeprecision for "t_case_huge_sub2". + +[ERROR:PA0206] t_case_huge_sub4.v:6 Missing timeunit/timeprecision for "t_case_huge_sub4". + +[ERROR:PA0206] t_case_inside.v:45 Missing timeunit/timeprecision for "sub". + +[ERROR:PA0206] t_case_itemwidth.v:91 Missing timeunit/timeprecision for "test". + +[ERROR:PA0206] t_case_reducer.v:120 Missing timeunit/timeprecision for "clz". + +[ERROR:PA0206] t_clk_concat4.v:7 Missing timeunit/timeprecision for "some_module". + +[ERROR:PA0206] t_clk_concat4.v:30 Missing timeunit/timeprecision for "t1". + +[ERROR:PA0206] t_clk_concat4.v:48 Missing timeunit/timeprecision for "t2". + +[ERROR:PA0206] t_clk_concat6.v:49 Missing timeunit/timeprecision for "ident". + +[ERROR:PA0206] t_clk_condflop_nord.v:69 Missing timeunit/timeprecision for "condff". + +[ERROR:PA0206] t_clk_condflop_nord.v:82 Missing timeunit/timeprecision for "condffimp". + +[ERROR:PA0206] t_clk_condflop_nord.v:104 Missing timeunit/timeprecision for "clockgate". + +[ERROR:PA0206] t_clk_dsp.v:78 Missing timeunit/timeprecision for "t_dspchip". + +[ERROR:PA0206] t_clk_dsp.v:119 Missing timeunit/timeprecision for "t_dspcore". + +[ERROR:PA0206] t_clk_dsp.v:145 Missing timeunit/timeprecision for "t_dsppla". + +[ERROR:PA0206] t_clk_scope_bad.v:26 Missing timeunit/timeprecision for "flop". + +[ERROR:PA0206] t_const_dec_mixed_bad.v:6 Missing timeunit/timeprecision for "MODULE NAME UNKNOWN". + +[ERROR:PA0206] t_cover_toggle.v:86 Missing timeunit/timeprecision for "alpha". + +[ERROR:PA0206] t_cover_toggle.v:125 Missing timeunit/timeprecision for "beta". + +[ERROR:PA0206] t_cover_toggle.v:142 Missing timeunit/timeprecision for "off". + +[ERROR:PA0206] t_dedupe_seq_logic.v:35 Missing timeunit/timeprecision for "l". + +[ERROR:PA0206] t_dedupe_seq_logic.v:44 Missing timeunit/timeprecision for "ll". + +[ERROR:PA0206] t_dedupe_seq_logic.v:53 Missing timeunit/timeprecision for "lll". + +[ERROR:PA0206] t_dedupe_seq_logic.v:59 Missing timeunit/timeprecision for "llr". + +[ERROR:PA0206] t_dedupe_seq_logic.v:65 Missing timeunit/timeprecision for "lr". + +[ERROR:PA0206] t_dedupe_seq_logic.v:71 Missing timeunit/timeprecision for "r". + +[ERROR:PA0206] t_dedupe_seq_logic.v:80 Missing timeunit/timeprecision for "rr". + +[ERROR:PA0206] t_dedupe_seq_logic.v:86 Missing timeunit/timeprecision for "rl". + +[ERROR:PA0206] t_dedupe_seq_logic.v:95 Missing timeunit/timeprecision for "rll". + +[ERROR:PA0206] t_dedupe_seq_logic.v:101 Missing timeunit/timeprecision for "rlr". + +[ERROR:PA0206] t_dedupe_seq_logic.v:107 Missing timeunit/timeprecision for "add". + +[ERROR:PA0206] t_dedupe_seq_logic.v:116 Missing timeunit/timeprecision for "add2". + +[ERROR:PA0206] t_case_write2_tasks.v:7 Missing timeunit/timeprecision for "t_case_write2_tasks". + +[ERROR:PA0206] verilated.v:2 Missing timeunit/timeprecision for "t_case_write1_tasks". + +[ERROR:PA0206] t_extend_class.v:33 Missing timeunit/timeprecision for "t_extend_class_v". + +[ERROR:PA0206] t_flag_topmodule.v:6 Missing timeunit/timeprecision for "a". + +[ERROR:PA0206] t_flag_topmodule.v:14 Missing timeunit/timeprecision for "a2". + +[ERROR:PA0206] t_flag_topmodule.v:21 Missing timeunit/timeprecision for "b". + +[ERROR:PA0206] t_flag_topmodule.v:25 Missing timeunit/timeprecision for "c". + +[ERROR:PA0206] t_flag_topmodule.v:32 Missing timeunit/timeprecision for "d". + +[ERROR:PA0206] t_func_const2_bad.v:17 Missing timeunit/timeprecision for "c9". + +[ERROR:PA0206] t_func_const2_bad.v:25 Missing timeunit/timeprecision for "b8". + +[ERROR:PA0206] t_func_regfirst.v:49 Missing timeunit/timeprecision for "f6". + +[ERROR:PA0206] t_func_wide.v:30 Missing timeunit/timeprecision for "muxtop". + +[ERROR:PA0206] t_gate_elim.v:66 Missing timeunit/timeprecision for "ta". + +[ERROR:PA0206] t_gate_elim.v:76 Missing timeunit/timeprecision for "tb". + +[ERROR:PA0206] t_gate_elim.v:86 Missing timeunit/timeprecision for "tc". + +[ERROR:PA0206] t_gate_elim.v:96 Missing timeunit/timeprecision for "td". + +[ERROR:PA0206] t_gate_elim.v:106 Missing timeunit/timeprecision for "te". + +[ERROR:PA0206] t_array_interface.v:6 Missing timeunit/timeprecision for "intf". + +[ERROR:PA0206] t_array_interface.v:12 Missing timeunit/timeprecision for "modify_interface". + +[ERROR:PA0206] t_gen_assign.v:46 Missing timeunit/timeprecision for "assigns". + +[ERROR:PA0206] t_gen_cond_const.v:45 Missing timeunit/timeprecision for "test_gen". + +[ERROR:PA0206] t_func_dotted.v:66 Missing timeunit/timeprecision for "global_mod". + +[ERROR:PA0206] t_func_dotted.v:76 Missing timeunit/timeprecision for "ma". + +[ERROR:PA0206] t_func_dotted.v:91 Missing timeunit/timeprecision for "mb". + +[ERROR:PA0206] t_func_dotted.v:119 Missing timeunit/timeprecision for "mc". + +[ERROR:PA0206] t_func_paramed.v:53 Missing timeunit/timeprecision for "extractor". + +[ERROR:PA0206] t_func_v.v:13 Missing timeunit/timeprecision for "level1". + +[ERROR:PA0206] t_func_v.v:23 Missing timeunit/timeprecision for "level2". + +[ERROR:PA0206] t_gen_for.v:54 Missing timeunit/timeprecision for "gencase". + +[ERROR:PA0206] t_gen_for.v:74 Missing timeunit/timeprecision for "paramed". + +[ERROR:PA0206] t_gen_for.v:129 Missing timeunit/timeprecision for "mbuf". + +[ERROR:PA0206] t_gen_for.v:136 Missing timeunit/timeprecision for "enflop". + +[ERROR:PA0206] t_gen_for.v:162 Missing timeunit/timeprecision for "enflop_one". + +[ERROR:PA0206] t_gate_implicit.v:78 Missing timeunit/timeprecision for "Mxor". + +[ERROR:PA0206] t_gen_intdot.v:45 Missing timeunit/timeprecision for "Generate". + +[ERROR:PA0206] t_gen_intdot.v:58 Missing timeunit/timeprecision for "Checker". + +[ERROR:PA0206] t_gen_intdot.v:77 Missing timeunit/timeprecision for "Genit". + +[ERROR:PA0206] t_gen_upscope.v:78 Missing timeunit/timeprecision for "tag". + +[ERROR:PA0206] t_gen_for1.v:42 Missing timeunit/timeprecision for "Testit". + +[ERROR:PA0206] t_gen_for1.v:68 Missing timeunit/timeprecision for "fnxtclk". + +[ERROR:PA0206] t_inst_darray.v:9 Missing timeunit/timeprecision for "the_intf". + +[ERROR:PA0206] t_inst_darray.v:26 Missing timeunit/timeprecision for "Contemplator". + +[ERROR:PA0206] t_inst_darray.v:44 Missing timeunit/timeprecision for "DeepThought". + +[ERROR:PA0206] t_inst_first_b.v:6 Missing timeunit/timeprecision for "t_inst_first_b". + +[ERROR:PA0206] t_inst_misarray_bad.v:20 Missing timeunit/timeprecision for "dut". + +[ERROR:PA0206] t_inst_misarray_bad.v:33 Missing timeunit/timeprecision for "suba". + +[ERROR:PA0206] t_inst_prepost.v:31 Missing timeunit/timeprecision for "ip". + +[ERROR:PA0206] t_inst_v2k.v:62 Missing timeunit/timeprecision for "hello". + +[ERROR:PA0206] t_interface1.v:8 Missing timeunit/timeprecision for "ifc". + +[ERROR:PA0206] t_for_funcbound.v:53 Missing timeunit/timeprecision for "strings". + +[ERROR:PA0206] t_interface_array.v:6 Missing timeunit/timeprecision for "foo_intf". + +[ERROR:PA0206] t_interface_array_nocolon_bad.v:12 Missing timeunit/timeprecision for "foo_subm". + +[ERROR:PA0206] t_interface_down.v:44 Missing timeunit/timeprecision for "wrapper". + +[ERROR:PA0206] t_interface_down.v:55 Missing timeunit/timeprecision for "lower". + +[ERROR:PA0206] t_interface_dups.v:88 Missing timeunit/timeprecision for "dti". + +[ERROR:PA0206] t_func_check.v:33 Missing timeunit/timeprecision for "chk". + +[ERROR:PA0206] t_func_const3_bad.v:15 Missing timeunit/timeprecision for "b9". + +[ERROR:PA0206] t_interface_missing_bad.v:11 Missing timeunit/timeprecision for "foo_mod". + +[ERROR:PA0206] t_interface_modport_import.v:8 Missing timeunit/timeprecision for "test_if". + +[ERROR:PA0206] t_interface_modport_import.v:42 Missing timeunit/timeprecision for "testmod". + +[ERROR:PA0206] t_interface_param1.v:21 Missing timeunit/timeprecision for "sub_test". + +[ERROR:PA0206] t_interface_param_another_bad.v:15 Missing timeunit/timeprecision for "simple_bus". + +[ERROR:PA0206] t_interface_size_bad.v:20 Missing timeunit/timeprecision for "baz". + +[ERROR:PA0206] t_gen_forif.v:67 Missing timeunit/timeprecision for "Test_wrap1". + +[ERROR:PA0206] t_gen_forif.v:75 Missing timeunit/timeprecision for "Test_wrap2". + +[ERROR:PA0206] t_lint_implicit_port.v:20 Missing timeunit/timeprecision for "set". + +[ERROR:PA0206] t_lint_implicit_port.v:27 Missing timeunit/timeprecision for "read". + +[ERROR:PA0206] t_lint_unused_iface_bad.v:6 Missing timeunit/timeprecision for "dummy_if". + +[ERROR:PA0206] t_gen_intdot2.v:38 Missing timeunit/timeprecision for "One". + +[ERROR:PA0206] t_func_grey.v:48 Missing timeunit/timeprecision for "t_func_grey2bin". + +[ERROR:PA0206] t_func_outp.v:48 Missing timeunit/timeprecision for "inv". + +[ERROR:PA0206] t_func_outp.v:56 Missing timeunit/timeprecision for "ftest". + +[ERROR:PA0206] t_func_outp.v:84 Missing timeunit/timeprecision for "mytop". + +[ERROR:PA0206] t_func_public.v:33 Missing timeunit/timeprecision for "tpub". + +[ERROR:PA0206] t_genfor_hier.v:7 Missing timeunit/timeprecision for "m1". + +[ERROR:PA0206] t_genvar_misuse_bad.v:7 Missing timeunit/timeprecision for "top". + +[ERROR:PA0206] t_initial_edge.v:69 Missing timeunit/timeprecision for "initial_edge_n". + +[ERROR:PA0206] t_initial_edge.v:85 Missing timeunit/timeprecision for "initial_edge". + +[ERROR:PA0206] t_gen_defparam.v:40 Missing timeunit/timeprecision for "m2". + +[ERROR:PA0206] t_gen_for_overlap.v:35 Missing timeunit/timeprecision for "sub1". + +[ERROR:PA0206] t_gen_for_overlap.v:40 Missing timeunit/timeprecision for "sub2". + +[ERROR:PA0206] t_inst_dff.v:109 Missing timeunit/timeprecision for "dff". + +[ERROR:PA0206] t_gen_index.v:41 Missing timeunit/timeprecision for "foo". + +[ERROR:PA0206] t_gen_index.v:62 Missing timeunit/timeprecision for "bar". + +[ERROR:PA0206] t_inst_notunsized.v:93 Missing timeunit/timeprecision for "Muxer". + +[ERROR:PA0206] t_inst_sv.v:61 Missing timeunit/timeprecision for "t_inst". + +[ERROR:PA0206] t_inst_wideconst.v:59 Missing timeunit/timeprecision for "wide". + +[ERROR:PA0206] t_interface_arraymux.v:32 Missing timeunit/timeprecision for "ThingMuxOH". + +[ERROR:PA0206] t_interface_arraymux.v:43 Missing timeunit/timeprecision for "Thinker". + +[ERROR:PA0206] t_gen_missing.v:12 Missing timeunit/timeprecision for "foobar". + +[ERROR:PA0206] t_gen_missing.v:45 Missing timeunit/timeprecision for "foo0". + +[ERROR:PA0206] t_interface_modport_bad.v:20 Missing timeunit/timeprecision for "counter_ansi". + +[ERROR:PA0206] t_interface_modportlist.v:13 Missing timeunit/timeprecision for "my_module". + +[ERROR:PA0206] t_interface_modportlist.v:20 Missing timeunit/timeprecision for "my_interface". + +[ERROR:PA0206] t_interface_param2.v:37 Missing timeunit/timeprecision for "mem". + +[ERROR:PA0206] t_interface_star.v:30 Missing timeunit/timeprecision for "counter_io". + +[ERROR:PA0206] t_interface_wrong_bad.v:11 Missing timeunit/timeprecision for "bar_intf". + +[ERROR:PA0206] t_lint_blksync_loop.v:44 Missing timeunit/timeprecision for "reg_1r1w". + +[ERROR:PA0206] t_lint_importstar_bad.v:6 Missing timeunit/timeprecision for "defs". + +[ERROR:PA0206] t_bind2.v:50 Missing timeunit/timeprecision for "targetmod". + +[ERROR:PA0206] t_bind2.v:66 Missing timeunit/timeprecision for "mycheck". + +[ERROR:PA0206] t_case_huge_sub3.v:6 Missing timeunit/timeprecision for "t_case_huge_sub3". + +[ERROR:PA0206] t_init_concat.v:59 Missing timeunit/timeprecision for "regfile". + +[ERROR:PA0206] t_math_imm.v:73 Missing timeunit/timeprecision for "example". + +[ERROR:PA0206] t_inst_dtree.v:19 Missing timeunit/timeprecision for "bmod". + +[ERROR:PA0206] t_inst_dtree.v:28 Missing timeunit/timeprecision for "cmod". + +[ERROR:PA0206] t_inst_dtree.v:38 Missing timeunit/timeprecision for "dmod". + +[ERROR:PA0206] t_inst_first_a.v:6 Missing timeunit/timeprecision for "t_inst_first_a". + +[ERROR:PA0206] t_inst_implicit.v:30 Missing timeunit/timeprecision for "subimp". + +[ERROR:PA0206] t_inst_mnpipe.v:42 Missing timeunit/timeprecision for "dffn". + +[ERROR:PA0206] t_inst_mnpipe.v:55 Missing timeunit/timeprecision for "MxN_pipeline". + +[ERROR:PA0206] t_inst_recurse2_bad.v:17 Missing timeunit/timeprecision for "looped". + +[ERROR:PA0206] t_inst_recurse_bad.v:21 Missing timeunit/timeprecision for "looped2". + +[ERROR:PA0206] t_interface.v:70 Missing timeunit/timeprecision for "handshake". + +[ERROR:PA0206] t_interface.v:109 Missing timeunit/timeprecision for "source". + +[ERROR:PA0206] t_interface.v:141 Missing timeunit/timeprecision for "drain". + +[ERROR:PA0206] t_math_vliw.v:58 Missing timeunit/timeprecision for "vliw". + +[ERROR:PA0206] t_interface_gen12.v:8 Missing timeunit/timeprecision for "foo_module". + +[ERROR:PA0206] t_interface_gen12.v:16 Missing timeunit/timeprecision for "bar_module". + +[ERROR:PA0206] t_cdc_async_bad.v:66 Missing timeunit/timeprecision for "Flop". + +[ERROR:PA0206] t_cdc_async_bad.v:78 Missing timeunit/timeprecision for "Sub". + +[ERROR:PA0206] t_interface_modport_export.v:45 Missing timeunit/timeprecision for "testmod_callee". + +[ERROR:PA0206] t_interface_modport_export.v:58 Missing timeunit/timeprecision for "testmod_caller". + +[ERROR:PA0206] t_interface_nest.v:6 Missing timeunit/timeprecision for "if1". + +[ERROR:PA0206] t_interface_nest.v:10 Missing timeunit/timeprecision for "if2". + +[ERROR:PA0206] t_interface_nest.v:15 Missing timeunit/timeprecision for "mod1". + +[ERROR:PA0206] t_cellarray.v:66 Missing timeunit/timeprecision for "drv1". + +[ERROR:PA0206] t_cellarray.v:73 Missing timeunit/timeprecision for "drv2". + +[ERROR:PA0206] t_cellarray.v:81 Missing timeunit/timeprecision for "drv3". + +[ERROR:PA0206] t_cellarray.v:91 Missing timeunit/timeprecision for "drv4". + +[ERROR:PA0206] t_chg_first.v:61 Missing timeunit/timeprecision for "t_chg_a". + +[ERROR:PA0206] t_mem_iforder.v:58 Missing timeunit/timeprecision for "fifo". + +[ERROR:PA0206] t_langext_order_sub.v:10 Missing timeunit/timeprecision for "t_langext_order_sub". + +[ERROR:PA0206] t_lint_always_comb_iface.v:6 Missing timeunit/timeprecision for "my_if". + +[ERROR:PA0206] t_lint_always_comb_iface.v:54 Missing timeunit/timeprecision for "my_module1". + +[ERROR:PA0206] t_lint_always_comb_iface.v:68 Missing timeunit/timeprecision for "my_module2". + +[ERROR:PA0206] t_lint_always_comb_iface.v:84 Missing timeunit/timeprecision for "my_module3". + +[ERROR:PA0206] t_lint_unused.v:51 Missing timeunit/timeprecision for "udp_mux2". + +[ERROR:PA0206] t_lint_width_bad.v:35 Missing timeunit/timeprecision for "p". + +[ERROR:PA0206] t_math_cmp.v:71 Missing timeunit/timeprecision for "prover". + +[ERROR:PA0206] t_clk_first.v:30 Missing timeunit/timeprecision for "t_clk". + +[ERROR:PA0206] t_clk_first.v:133 Missing timeunit/timeprecision for "t_clk_flop". + +[ERROR:PA0206] t_clk_first.v:151 Missing timeunit/timeprecision for "t_clk_two". + +[ERROR:PA0206] t_clk_first.v:175 Missing timeunit/timeprecision for "t_clk_twob". + +[ERROR:PA0206] t_clk_latchgate.v:97 Missing timeunit/timeprecision for "llq". + +[ERROR:PA0206] t_clk_latchgate.v:116 Missing timeunit/timeprecision for "ffq". + +[ERROR:PA0206] t_math_signed.v:164 Missing timeunit/timeprecision for "by_width". + +[ERROR:PA0206] t_mod_interface_array.v:8 Missing timeunit/timeprecision for "a_if". + +[ERROR:PA0206] t_mod_interface_array.v:14 Missing timeunit/timeprecision for "intf_source". + +[ERROR:PA0206] t_mod_interface_array.v:26 Missing timeunit/timeprecision for "intf_sink". + +[ERROR:PA0206] t_mod_longname.v:28 Missing timeunit/timeprecision for "modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie". + +[ERROR:PA0206] t_cover_line.v:114 Missing timeunit/timeprecision for "tsk". + +[ERROR:PA0206] t_dedupe_clk_gate.v:20 Missing timeunit/timeprecision for "flop_gated_latch". + +[ERROR:PA0206] t_dedupe_clk_gate.v:30 Missing timeunit/timeprecision for "flop_gated_flop". + +[ERROR:PA0206] t_dedupe_clk_gate.v:40 Missing timeunit/timeprecision for "clock_gate_latch". + +[ERROR:PA0206] t_dedupe_clk_gate.v:52 Missing timeunit/timeprecision for "clock_gate_flop". + +[ERROR:PA0206] t_package_abs.v:8 Missing timeunit/timeprecision for "functions". + +[ERROR:PA0206] t_mem_file.v:76 Missing timeunit/timeprecision for "file". + +[ERROR:PA0206] t_package_twodeep.v:8 Missing timeunit/timeprecision for "pkg2". + +[ERROR:PA0206] t_package_twodeep.v:12 Missing timeunit/timeprecision for "pkg1". + +[ERROR:PA0206] t_param_array.v:78 Missing timeunit/timeprecision for "checkstr". + +[ERROR:PA0206] t_param_default_bad.v:6 Missing timeunit/timeprecision for "m". + +[ERROR:PA0206] t_param_first_b.v:6 Missing timeunit/timeprecision for "t_param_first_b". + +[ERROR:PA0206] t_mem_multi_io3.v:34 Missing timeunit/timeprecision for "testio". + +[ERROR:PA0206] t_mem_slot.v:7 Missing timeunit/timeprecision for "t_mem_slot". + +[ERROR:PA0206] t_mod_recurse1.v:12 Missing timeunit/timeprecision for "rec". + +[ERROR:PA0206] t_mod_recurse1.v:28 Missing timeunit/timeprecision for "bottom". + +[ERROR:PA0206] t_order_b.v:6 Missing timeunit/timeprecision for "t_order_b". + +[ERROR:PA0206] t_order_clkinst.v:61 Missing timeunit/timeprecision for "comb_loop". + +[ERROR:PA0206] t_order_clkinst.v:90 Missing timeunit/timeprecision for "seq_loop". + +[ERROR:PA0206] t_order_multidriven.v:61 Missing timeunit/timeprecision for "FooWr". + +[ERROR:PA0206] t_order_multidriven.v:86 Missing timeunit/timeprecision for "FooRd". + +[ERROR:PA0206] t_order_multidriven.v:125 Missing timeunit/timeprecision for "FooMem". + +[ERROR:PA0206] t_order_multidriven.v:151 Missing timeunit/timeprecision for "FooMemImpl". + +[ERROR:PA0206] t_dpi_accessors.v:50 Missing timeunit/timeprecision for "test_sub". + +[ERROR:PA0206] t_mod_recurse.v:62 Missing timeunit/timeprecision for "PriorityChoice". + +[ERROR:PA0206] t_order_a.v:6 Missing timeunit/timeprecision for "t_order_a". + +[ERROR:PA0206] t_order_first.v:20 Missing timeunit/timeprecision for "t_netlist". + +[ERROR:PA0206] t_param_if_blk.v:71 Missing timeunit/timeprecision for "Nested". + +[ERROR:PA0206] t_param_named.v:29 Missing timeunit/timeprecision for "m3". + +[ERROR:PA0206] t_param_no_parentheses.v:66 Missing timeunit/timeprecision for "mnooverride". + +[ERROR:PA0206] t_param_package.v:12 Missing timeunit/timeprecision for "params". + +[ERROR:PA0206] t_param_package.v:16 Missing timeunit/timeprecision for "Test0". + +[ERROR:PA0206] t_param_package.v:21 Missing timeunit/timeprecision for "Test1". + +[ERROR:PA0206] t_param_real.v:6 Missing timeunit/timeprecision for "mod". + +[ERROR:PA0206] t_package.v:20 Missing timeunit/timeprecision for "p2". + +[ERROR:PA0206] t_param_type.v:54 Missing timeunit/timeprecision for "mod_typ". + +[ERROR:PA0206] t_pp_lib_library.v:6 Missing timeunit/timeprecision for "library_cell". + +[ERROR:PA0206] t_reloop_cam.v:95 Missing timeunit/timeprecision for "cam". + +[ERROR:PA0206] t_param_ddeep_width.v:13 Missing timeunit/timeprecision for "paramtest_WRAP". + +[ERROR:PA0206] t_param_ddeep_width.v:20 Missing timeunit/timeprecision for "paramtest_DFFRE". + +[ERROR:PA0206] t_param_first_a.v:6 Missing timeunit/timeprecision for "t_param_first_a". + +[ERROR:PA0206] t_param_mem_attr.v:34 Missing timeunit/timeprecision for "memory". + +[ERROR:PA0206] t_preproc_kwd.v:28 Missing timeunit/timeprecision for "v95". + +[ERROR:PA0206] t_preproc_kwd.v:34 Missing timeunit/timeprecision for "v01". + +[ERROR:PA0206] t_preproc_kwd.v:40 Missing timeunit/timeprecision for "v05". + +[ERROR:PA0206] t_preproc_kwd.v:46 Missing timeunit/timeprecision for "s05". + +[ERROR:PA0206] t_preproc_kwd.v:52 Missing timeunit/timeprecision for "s09". + +[ERROR:PA0206] t_preproc_kwd.v:58 Missing timeunit/timeprecision for "s12". + +[ERROR:PA0206] t_preproc_kwd.v:66 Missing timeunit/timeprecision for "s17". + +[ERROR:PA0206] t_preproc_kwd.v:74 Missing timeunit/timeprecision for "a23". + +[ERROR:PA0206] t_embed1_child.v:6 Missing timeunit/timeprecision for "t_embed1_child". + +[ERROR:PA0206] t_embed1_wrap.v:6 Missing timeunit/timeprecision for "t_embed1_wrap". + +[ERROR:PA0206] t_enum_name2.v:6 Missing timeunit/timeprecision for "our_pkg". + +[ERROR:PA0206] t_enum_name2.v:19 Missing timeunit/timeprecision for "our". + +[ERROR:PA0206] t_enum_public.v:6 Missing timeunit/timeprecision for "p3". + +[ERROR:PA0206] t_enum_public.v:12 Missing timeunit/timeprecision for "p62". + +[ERROR:PA0206] t_param_sel_range.v:15 Missing timeunit/timeprecision for "submod". + +[ERROR:PA0206] t_param_type2.v:6 Missing timeunit/timeprecision for "tt_pkg". + +[ERROR:PA0206] t_param_type2.v:31 Missing timeunit/timeprecision for "tt_buf". + +[ERROR:PA0206] t_param_up_bad.v:12 Missing timeunit/timeprecision for "child". + +[ERROR:PA0206] t_param_up_bad.v:18 Missing timeunit/timeprecision for "parent". + +[ERROR:PA0206] t_past.v:84 Missing timeunit/timeprecision for "Test2". + +[ERROR:PA0206] t_struct_param.v:7 Missing timeunit/timeprecision for "config_pkg". + +[ERROR:PA0206] t_struct_param.v:40 Missing timeunit/timeprecision for "struct_submodule". + +[ERROR:PA0206] t_struct_unpacked.v:6 Missing timeunit/timeprecision for "x". + +[ERROR:PA0206] t_tri_array_pull.v:6 Missing timeunit/timeprecision for "IOBUF". + +[ERROR:PA0206] t_struct_array.v:6 Missing timeunit/timeprecision for "TEST_TYPES". + +[ERROR:PA0206] t_sv_cpu.v:79 Missing timeunit/timeprecision for "testbench". + +[ERROR:PA0206] t_sv_conditional.v:62 Missing timeunit/timeprecision for "st3_testbench". + +[ERROR:PA0206] t_sv_conditional.v:145 Missing timeunit/timeprecision for "simple_test_3". + +[ERROR:PA0206] t_sv_conditional.v:230 Missing timeunit/timeprecision for "counterA". + +[ERROR:PA0206] t_sv_conditional.v:277 Missing timeunit/timeprecision for "counterB". + +[ERROR:PA0206] t_sv_conditional.v:311 Missing timeunit/timeprecision for "simple_test_3a". + +[ERROR:PA0206] t_sv_conditional.v:331 Missing timeunit/timeprecision for "simple_test_3b". + +[ERROR:PA0206] t_sv_conditional.v:363 Missing timeunit/timeprecision for "simple_test_3c". + +[ERROR:PA0206] t_sv_conditional.v:395 Missing timeunit/timeprecision for "simple_test_3d". + +[ERROR:PA0206] t_sv_conditional.v:425 Missing timeunit/timeprecision for "simple_test_3e". + +[ERROR:PA0206] t_sv_conditional.v:449 Missing timeunit/timeprecision for "simple_test_3f". + +[ERROR:PA0206] t_trace_primitive.v:31 Missing timeunit/timeprecision for "CINV". + +[ERROR:PA0206] t_type_param.v:15 Missing timeunit/timeprecision for "foo_wrapper". + +[ERROR:PA0206] t_typedef_port.v:78 Missing timeunit/timeprecision for "TestNonAnsi". + +[ERROR:PA0206] t_typedef_port.v:95 Missing timeunit/timeprecision for "TestAnsi". + +[ERROR:PA0206] t_trace_param.v:6 Missing timeunit/timeprecision for "my_funcs". + +[ERROR:PA0206] t_trace_param.v:14 Missing timeunit/timeprecision for "my_module_types". + +[ERROR:PA0206] t_tri_array.v:65 Missing timeunit/timeprecision for "Pad". + +[ERROR:PA0206] t_tri_gen.v:27 Missing timeunit/timeprecision for "updown". + +[ERROR:PA0206] t_tri_gen.v:39 Missing timeunit/timeprecision for "t_up". + +[ERROR:PA0206] t_tri_gen.v:42 Missing timeunit/timeprecision for "t_down". + +[ERROR:PA0206] t_var_dup_bad.v:46 Missing timeunit/timeprecision for "sub0". + +[ERROR:PA0206] t_var_dup_bad.v:68 Missing timeunit/timeprecision for "sub3". + +[ERROR:PA0206] t_tri_gate.v:15 Missing timeunit/timeprecision for "pass". + +[ERROR:PA0206] t_tri_gate.v:20 Missing timeunit/timeprecision for "tbuf". + +[ERROR:PA0206] t_tri_gate.v:24 Missing timeunit/timeprecision for "mux". + +[ERROR:PA0206] t_tri_inout.v:15 Missing timeunit/timeprecision for "io". + +[ERROR:PA0206] t_tri_pull01.v:71 Missing timeunit/timeprecision for "t_tri2". + +[ERROR:PA0206] t_tri_pull01.v:84 Missing timeunit/timeprecision for "t_tri3". + +[ERROR:PA0206] t_tri_various.v:146 Missing timeunit/timeprecision for "Test3". + +[ERROR:PA0206] t_tri_various.v:154 Missing timeunit/timeprecision for "Test4". + +[ERROR:PA0206] t_tri_various.v:159 Missing timeunit/timeprecision for "Test5". + +[ERROR:PA0206] t_tri_various.v:167 Missing timeunit/timeprecision for "Test6". + +[ERROR:PA0206] t_tri_various.v:173 Missing timeunit/timeprecision for "Test6a". + +[ERROR:PA0206] t_tri_various.v:177 Missing timeunit/timeprecision for "Test7". + +[ERROR:PA0206] t_var_port_bad.v:11 Missing timeunit/timeprecision for "subok". + +[ERROR:PA0206] t_tri_public.v:47 Missing timeunit/timeprecision for "sub_mod". + +[ERROR:PA0206] t_tri_select.v:35 Missing timeunit/timeprecision for "io_ring". + +[ERROR:PA0206] t_udp.v:115 Missing timeunit/timeprecision for "udp_latch". + +[ERROR:PA0206] t_udp.v:126 Missing timeunit/timeprecision for "udp_dff". + +[ERROR:PA0206] t_vpi_var.v:87 Missing timeunit/timeprecision for "arr". + +[ERROR:PA0206] t_udp_noname.v:35 Missing timeunit/timeprecision for "udp". + +[ERROR:PA0206] t_unoptflat_simple_3.v:41 Missing timeunit/timeprecision for "test1". + +[ERROR:PA0206] t_unoptflat_simple_3.v:60 Missing timeunit/timeprecision for "test2". + +[ERROR:PA0206] t_final.v:6 Missing timeunit/timeprecision for "submodule". + +[ERROR:PA0206] t_vams_wreal.v:87 Missing timeunit/timeprecision for "through". + +[ERROR:PA0206] t_vams_wreal.v:93 Missing timeunit/timeprecision for "within_range". + +[ERROR:PA0206] t_vams_wreal.v:106 Missing timeunit/timeprecision for "wreal_bus". + +[ERROR:PA0206] t_vams_wreal.v:114 Missing timeunit/timeprecision for "first_level". + +[ERROR:PA0206] t_vams_wreal.v:121 Missing timeunit/timeprecision for "second_level". + +[ERROR:PA0206] t_var_overzero.v:33 Missing timeunit/timeprecision for "tsub". + +[ERROR:PA0206] t_var_in_assign.v:59 Missing timeunit/timeprecision for "z". + +[ERROR:PA0206] t_xml_first.v:44 Missing timeunit/timeprecision for "mod2". + +[ERROR:PA0206] t_flag_libinc.v:6 Missing timeunit/timeprecision for "liblib_a". + +[ERROR:PA0206] t_flag_libinc.v:10 Missing timeunit/timeprecision for "liblib_b". + +[ERROR:PA0206] t_flag_libinc.v:17 Missing timeunit/timeprecision for "liblib_c". + +[ERROR:PA0206] t_flag_libinc.v:23 Missing timeunit/timeprecision for "liblib_d". + +[ERROR:PA0206] t_flag_topmod2_bad.v:6 Missing timeunit/timeprecision for "a_top". + +[ERROR:PA0206] t_flag_topmodule_inline.v:22 Missing timeunit/timeprecision for "l3". + +[ERROR:PA0206] t_func_begin2.v:6 Missing timeunit/timeprecision for "init". + +[ERROR:PA0206] t_func_const.v:6 Missing timeunit/timeprecision for "testpackage". + +[ERROR:PA0206] t_func_lib_sub.v:7 Missing timeunit/timeprecision for "BreadAddrDP". + +[ERROR:PA0206] t_func_lib_sub.v:56 Missing timeunit/timeprecision for "DecCountReg4". + +[ERROR:PA0206] t_gate_fdup.v:6 Missing timeunit/timeprecision for "fnor2". + +[ERROR:PA0206] t_generate_fatal_bad.v:15 Missing timeunit/timeprecision for "foo2". + +[ERROR:PA0206] t_inst_aport.v:65 Missing timeunit/timeprecision for "callee". + +[ERROR:PA0206] t_inst_tree.v:63 Missing timeunit/timeprecision for "ps". + +[ERROR:PA0206] t_inst_tree.v:69 Missing timeunit/timeprecision for "l1". + +[ERROR:PA0206] t_inst_tree.v:76 Missing timeunit/timeprecision for "l2". + +[ERROR:PA0206] t_inst_tree.v:92 Missing timeunit/timeprecision for "l4". + +[ERROR:PA0206] t_inst_tree.v:100 Missing timeunit/timeprecision for "l5". + +[ERROR:PA0206] t_interface2.v:72 Missing timeunit/timeprecision for "ifunused". + +[ERROR:PA0206] t_interface2.v:93 Missing timeunit/timeprecision for "counter_nansi". + +[ERROR:PA0206] t_interface2.v:104 Missing timeunit/timeprecision for "modunused". + +[ERROR:PA0206] t_interface_bind_public.v:6 Missing timeunit/timeprecision for "hex2ram_if". + +[ERROR:PA0206] t_interface_bind_public.v:69 Missing timeunit/timeprecision for "testharness_ext". + +[ERROR:PA0206] t_interface_bind_public.v:100 Missing timeunit/timeprecision for "SimpleTestHarness". + +[ERROR:PA0206] t_interface_modport.v:6 Missing timeunit/timeprecision for "counter_if". + +[ERROR:PA0206] t_interface_modport.v:103 Missing timeunit/timeprecision for "counter_ansi_m". + +[ERROR:PA0206] t_interface_modport.v:116 Missing timeunit/timeprecision for "counter_nansi_m". + +[ERROR:PA0206] t_lint_declfilename.v:10 Missing timeunit/timeprecision for "t_lint_declfilename". + +[ERROR:PA0206] t_math_imm2.v:13 Missing timeunit/timeprecision for "t_math_imm2". + +[ERROR:PA0206] t_math_pow4.v:43 Missing timeunit/timeprecision for "test004". + +[ERROR:PA0206] t_math_real.v:141 Missing timeunit/timeprecision for "sub_cast_bug374". + +[ERROR:PA0206] t_mem_multi_io.v:39 Missing timeunit/timeprecision for "has_array". + +[ERROR:PA0206] t_mem_multiwire.v:53 Missing timeunit/timeprecision for "inst". + +[ERROR:PA0206] t_mem_multiwire.v:75 Missing timeunit/timeprecision for "inst2". + +[ERROR:PA0206] t_mem_slice_conc_bad.v:68 Missing timeunit/timeprecision for "bbb". + +[ERROR:PA0206] t_mem_slice_conc_bad.v:101 Missing timeunit/timeprecision for "aaa". + +[ERROR:PA0206] t_multitop1s.v:6 Missing timeunit/timeprecision for "t_multitop1s". + +[ERROR:PA0206] t_multitop1s.v:10 Missing timeunit/timeprecision for "in_subfile". + +[ERROR:PA0206] t_package_dot.v:13 Missing timeunit/timeprecision for "csr_pkg". + +[ERROR:PA0206] t_package_export.v:14 Missing timeunit/timeprecision for "pkg10". + +[ERROR:PA0206] t_package_export.v:19 Missing timeunit/timeprecision for "pkg11". + +[ERROR:PA0206] t_package_export.v:23 Missing timeunit/timeprecision for "pkg20". + +[ERROR:PA0206] t_package_export.v:27 Missing timeunit/timeprecision for "pkg21". + +[ERROR:PA0206] t_package_export.v:31 Missing timeunit/timeprecision for "pkg30". + +[ERROR:PA0206] t_package_export.v:35 Missing timeunit/timeprecision for "pkg31". + +[ERROR:PA0206] t_package_verb.v:7 Missing timeunit/timeprecision for "verb_pkg". + +[ERROR:PA0206] t_param_long.v:94 Missing timeunit/timeprecision for "i". + +[ERROR:PA0206] t_preproc_inc_inc_bad.vh:6 Missing timeunit/timeprecision for "xx". + +[ERROR:PA0206] t_trace_public.v:32 Missing timeunit/timeprecision for "glbl". + +[ERROR:PA0206] t_trace_public.v:36 Missing timeunit/timeprecision for "neg". + +[ERROR:PA0206] t_trace_public.v:51 Missing timeunit/timeprecision for "little". + +[ERROR:PA0206] t_tri_inout2.v:59 Missing timeunit/timeprecision for "ChildA". + +[ERROR:PA0206] t_tri_inout2.v:73 Missing timeunit/timeprecision for "ChildB". + +[ERROR:PA0206] t_tri_pullup.v:24 Missing timeunit/timeprecision for "pullup_module". + +[ERROR:PA0206] t_tri_unconn.v:78 Missing timeunit/timeprecision for "t_tri0". + +[ERROR:PA0206] t_tri_unconn.v:90 Missing timeunit/timeprecision for "t_tri1". + +[ERROR:PA0206] t_var_notfound_bad.v:32 Missing timeunit/timeprecision for "subsub". + +[ FATAL] : 0 +[ ERROR] : 631 +[WARNING] : 416 +[ NOTE] : 4 + +******************************************** +* End SURELOG SVerilog Compiler/Linter * +******************************************** + +174.23user 1.63system 1:35.09elapsed 184%CPU (0avgtext+0avgdata 1926828maxresident)k +8296inputs+9744outputs (0major+479385minor)pagefaults 0swaps
diff --git a/SVIncCompil/Testcases/Verilator/t_EXAMPLE.v b/SVIncCompil/Testcases/Verilator/t_EXAMPLE.v new file mode 100644 index 0000000..83fde05 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_EXAMPLE.v
@@ -0,0 +1,96 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Use this file as a template for submitting bugs, etc. +// This module takes a single clock input, and should either +// $write("*-* All Finished *-*\n"); +// $finish; +// on success, or $stop. +// +// The code as shown applies a random vector to the Test +// module, then calculates a CRC on the Test module's outputs. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by ____YOUR_NAME_HERE____. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. + + input clk; + input [31:0] in; + output reg [31:0] out; + + always @(posedge clk) begin + out <= in; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_a_first_cc.v b/SVIncCompil/Testcases/Verilator/t_a_first_cc.v new file mode 100644 index 0000000..d90fb77 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_a_first_cc.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Test loop + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_altera_lpm.v b/SVIncCompil/Testcases/Verilator/t_altera_lpm.v new file mode 100644 index 0000000..16464a0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_altera_lpm.v
@@ -0,0 +1,6781 @@ +//------------------------------------------------------------------------- +// This Verilog file was developed by Altera Corporation. It may be +// freely copied and/or distributed at no cost. Any persons using this +// file for any purpose do so at their own risk, and are responsible for +// the results of such use. Altera Corporation does not guarantee that +// this file is complete, correct, or fit for any particular purpose. +// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must +// accompany any copy of this file. +//------------------------------------------------------------------------ +// +// Quartus Prime 16.1.0 Build 196 10/24/2016 +// +//------------------------------------------------------------------------ +// LPM Synthesizable Models (Support string type generic) +// These models are based on LPM version 220 (EIA-IS103 October 1998). +//------------------------------------------------------------------------ +// +//----------------------------------------------------------------------------- +// Assumptions: +// +// 1. The default value for LPM_SVALUE, LPM_AVALUE, LPM_PVALUE, and +// LPM_STRENGTH is string UNUSED. +// +//----------------------------------------------------------------------------- +// Verilog Language Issues: +// +// Two dimensional ports are not supported. Modules with two dimensional +// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH) +// bits wide. +// +//----------------------------------------------------------------------------- +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : LPM_MEMORY_INITIALIZATION +// +// Description : Common function to read intel-hex format data file with +// extension .hex and creates the equivalent verilog format +// data file with extension .ver. +// +// Limitation : Supports only record type '00'(data record), '01'(end of +// file record) and '02'(extended segment address record). +// +// Results expected: Creates the verilog format data file with extension .ver +// and return the name of the file. +// +//END_MODULE_NAME-------------------------------------------------------------- + +//See also: https://github.com/twosigma/verilator_support +// verilator lint_off COMBDLY +// verilator lint_off INITIALDLY +// verilator lint_off MULTIDRIVEN +// verilator lint_off UNSIGNED +// verilator lint_off WIDTH + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +`define LPM_TRUE 1 +`define LPM_FALSE 0 +`define LPM_NULL 0 +`define LPM_EOF -1 +`define LPM_MAX_NAME_SZ 128 +`define LPM_MAX_WIDTH 256 +`define LPM_COLON ":" +`define LPM_DOT "." +`define LPM_NEWLINE "\n" +`define LPM_CARRIAGE_RETURN 8'h0D +`define LPM_SPACE " " +`define LPM_TAB "\t" +`define LPM_OPEN_BRACKET "[" +`define LPM_CLOSE_BRACKET "]" +`define LPM_OFFSET 9 +`define LPM_H10 8'h10 +`define LPM_H10000 20'h10000 +`define LPM_AWORD 8 +`define LPM_MASK15 32'h000000FF +`define LPM_EXT_STR "ver" +`define LPM_PERCENT "%" +`define LPM_MINUS "-" +`define LPM_SEMICOLON ";" +`define LPM_EQUAL "=" + +// MODULE DECLARATION +module LPM_MEMORY_INITIALIZATION; + +/****************************************************************/ +/* convert uppercase character values to lowercase. */ +/****************************************************************/ +function [8:1] tolower; + input [8:1] given_character; + reg [8:1] conv_char; + +begin + if ((given_character >= 65) && (given_character <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 + begin + conv_char = given_character + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set + tolower = conv_char; + end + else + tolower = given_character; +end +endfunction + +/****************************************************************/ +/* Read in Altera-mif format data to verilog format data. */ +/****************************************************************/ +task convert_mif2ver; + input[`LPM_MAX_NAME_SZ*8 : 1] in_file; + input width; + output [`LPM_MAX_NAME_SZ*8 : 1] out_file; + reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; + reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; + reg [`LPM_MAX_NAME_SZ*8 : 1] buffer; + reg [`LPM_MAX_WIDTH : 0] memory_data1, memory_data2; + reg [8 : 1] c; + reg [3 : 0] hex, tmp_char; + reg [24 : 1] address_radix, data_radix; + reg get_width; + reg get_depth; + reg get_data_radix; + reg get_address_radix; + reg width_found; + reg depth_found; + reg data_radix_found; + reg address_radix_found; + reg get_address_data_pairs; + reg get_address; + reg get_data; + reg display_address; + reg invalid_address; + reg get_start_address; + reg get_end_address; + reg done; + reg error_status; + reg first_rec; + reg last_rec; + + integer width; + integer memory_width, memory_depth; + integer value; + integer ifp, ofp, r, r2; + integer i, j, k, m, n; + + integer off_addr, nn, address, tt, cc, aah, aal, dd, sum ; + integer start_address, end_address; + integer line_no; + integer character_count; + integer comment_with_percent_found; + integer comment_with_double_minus_found; + +begin + done = `LPM_FALSE; + error_status = `LPM_FALSE; + first_rec = `LPM_FALSE; + last_rec = `LPM_FALSE; + comment_with_percent_found = `LPM_FALSE; + comment_with_double_minus_found = `LPM_FALSE; + + off_addr= 0; + nn= 0; + address = 0; + start_address = 0; + end_address = 0; + tt= 0; + cc= 0; + aah= 0; + aal= 0; + dd= 0; + sum = 0; + line_no = 1; + c = 0; + hex = 0; + value = 0; + buffer = ""; + character_count = 0; + memory_width = 0; + memory_depth = 0; + memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; + memory_data2 = {(`LPM_MAX_WIDTH+1) {1'b0}}; + address_radix = "hex"; + data_radix = "hex"; + get_width = `LPM_FALSE; + get_depth = `LPM_FALSE; + get_data_radix = `LPM_FALSE; + get_address_radix = `LPM_FALSE; + width_found = `LPM_FALSE; + depth_found = `LPM_FALSE; + data_radix_found = `LPM_FALSE; + address_radix_found = `LPM_FALSE; + get_address_data_pairs = `LPM_FALSE; + display_address = `LPM_FALSE; + invalid_address = `LPM_FALSE; + get_start_address = `LPM_FALSE; + get_end_address = `LPM_FALSE; + + if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) + out_file = in_file; + else + begin + ifp = $fopen(in_file, "r"); + + if (ifp == `LPM_NULL) + begin + $display("ERROR: cannot read %0s.", in_file); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + end + + out_file = in_file; + + if((out_file[4*8 : 1] == ".mif") || (out_file[4*8 : 1] == ".MIF")) + out_file[3*8 : 1] = `LPM_EXT_STR; + else + begin + $display("ERROR: Invalid input file name %0s. Expecting file with .mif extension and Altera-mif data format.", in_file); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + end + + if (!done) + begin + ofp = $fopen(out_file, "w"); + + if (ofp == `LPM_NULL) + begin + $display("ERROR : cannot write %0s.", out_file); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + end + end + + while((!done) && (!error_status)) + begin : READER + + r = $fgetc(ifp); + + if (r == `LPM_EOF) + begin + // to do : add more checking on whether a particular assigment(width, depth, memory/address) are mising + if(!first_rec) + begin + error_status = `LPM_TRUE; + $display("WARNING: %0s, Intel-hex data file is empty.", in_file); + $display ("Time: %0t Instance: %m", $time); + end + else if (!get_address_data_pairs) + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + else if(!last_rec) + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Missing `end` statement.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + done = `LPM_TRUE; + end + else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) + begin + if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) + begin + get_address_data_pairs = `LPM_TRUE; + get_address = `LPM_TRUE; + buffer = ""; + end + else if (buffer == "content") + begin + // continue to next character + end + else + if (buffer != "") + begin + // found invalid syntax in the particular line. + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + disable READER; + end + line_no = line_no +1; + + end + else if ((r == `LPM_SPACE) || (r == `LPM_TAB)) + begin + // continue to next character; + end + else if (r == `LPM_PERCENT) + begin + // Ignore all the characters which which is part of comment. + r = $fgetc(ifp); + + while ((r != `LPM_PERCENT) && (r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN)) + begin + r = $fgetc(ifp); + end + + if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) + begin + line_no = line_no +1; + + if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) + begin + get_address_data_pairs = `LPM_TRUE; + get_address = `LPM_TRUE; + buffer = ""; + end + end + end + else if (r == `LPM_MINUS) + begin + r = $fgetc(ifp); + if (r == `LPM_MINUS) + begin + // Ignore all the characters which which is part of comment. + r = $fgetc(ifp); + + while ((r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN)) + begin + r = $fgetc(ifp); + + end + + if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) + begin + line_no = line_no +1; + + if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) + begin + get_address_data_pairs = `LPM_TRUE; + get_address = `LPM_TRUE; + buffer = ""; + end + end + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + end + else if (r == `LPM_EQUAL) + begin + if (buffer == "width") + begin + if (width_found == `LPM_FALSE) + begin + get_width = `LPM_TRUE; + buffer = ""; + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Width has already been specified once.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + end + else if (buffer == "depth") + begin + get_depth = `LPM_TRUE; + buffer = ""; + end + else if (buffer == "data_radix") + begin + get_data_radix = `LPM_TRUE; + buffer = ""; + end + else if (buffer == "address_radix") + begin + get_address_radix = `LPM_TRUE; + buffer = ""; + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Unknown setting (%0s).", in_file, line_no, buffer); + $display("Time: %0t Instance: %m", $time); + end + end + else if (r == `LPM_COLON) + begin + if (!get_address_data_pairs) + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + else if (invalid_address == `LPM_TRUE) + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + begin + get_address = `LPM_FALSE; + get_data = `LPM_TRUE; + display_address = `LPM_TRUE; + end + end + else if (r == `LPM_DOT) + begin + r = $fgetc(ifp); + if (r == `LPM_DOT) + begin + if (get_start_address == `LPM_TRUE) + begin + start_address = address; + address = 0; + get_start_address = `LPM_FALSE; + get_end_address = `LPM_TRUE; + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + end + else if (r == `LPM_OPEN_BRACKET) + begin + get_start_address = `LPM_TRUE; + end + else if (r == `LPM_CLOSE_BRACKET) + begin + if (get_end_address == `LPM_TRUE) + begin + end_address = address; + address = 0; + get_end_address = `LPM_FALSE; + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + end + else if (r == `LPM_SEMICOLON) + begin + if (get_width == `LPM_TRUE) + begin + width_found = `LPM_TRUE; + memory_width = value; + value = 0; + get_width = `LPM_FALSE; + end + else if (get_depth == `LPM_TRUE) + begin + depth_found = `LPM_TRUE; + memory_depth = value; + value = 0; + get_depth = `LPM_FALSE; + end + else if (get_data_radix == `LPM_TRUE) + begin + data_radix_found = `LPM_TRUE; + get_data_radix = `LPM_FALSE; + + if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") || + (buffer == "hex")) + begin + data_radix = buffer[24 : 1]; + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid assignment (%0s) to data_radix.", in_file, line_no, buffer); + $display("Time: %0t Instance: %m", $time); + end + buffer = ""; + end + else if (get_address_radix == `LPM_TRUE) + begin + address_radix_found = `LPM_TRUE; + get_address_radix = `LPM_FALSE; + + if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") || + (buffer == "hex")) + begin + address_radix = buffer[24 : 1]; + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid assignment (%0s) to address radix.", in_file, line_no, buffer); + $display("Time: %0t Instance: %m", $time); + end + buffer = ""; + end + else if (buffer == "end") + begin + if (get_address_data_pairs == `LPM_TRUE) + begin + last_rec = `LPM_TRUE; + buffer = ""; + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + end + else if (get_data == `LPM_TRUE) + begin + get_address = `LPM_TRUE; + get_data = `LPM_FALSE; + buffer = ""; + character_count = 0; + + if (start_address != end_address) + begin + for (address = start_address; address <= end_address; address = address+1) + begin + $fdisplay(ofp,"@%0h", address); + + for (i = memory_width -1; i >= 0; i = i-1 ) + begin + hex[(i % 4)] = memory_data1[i]; + + if ((i % 4) == 0) + begin + $fwrite(ofp, "%0h", hex); + hex = 0; + end + end + + $fwrite(ofp, "\n"); + end + start_address = 0; + end_address = 0; + address = 0; + hex = 0; + memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; + end + else + begin + if (display_address == `LPM_TRUE) + begin + $fdisplay(ofp,"@%0h", address); + display_address = `LPM_FALSE; + end + + for (i = memory_width -1; i >= 0; i = i-1 ) + begin + hex[(i % 4)] = memory_data1[i]; + + if ((i % 4) == 0) + begin + $fwrite(ofp, "%0h", hex); + hex = 0; + end + end + + $fwrite(ofp, "\n"); + address = 0; + hex = 0; + memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; + end + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid assigment.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + end + else if ((get_width == `LPM_TRUE) || (get_depth == `LPM_TRUE)) + begin + if ((r >= "0") && (r <= "9")) + value = (value * 10) + (r - 'h30); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid assignment to width/depth.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + end + else if (get_address == `LPM_TRUE) + begin + if (address_radix == "hex") + begin + if ((r >= "0") && (r <= "9")) + value = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + value = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + value = 10 + (r - 'h61); + else + begin + invalid_address = `LPM_TRUE; + end + + address = (address * 16) + value; + end + else if ((address_radix == "dec")) + begin + if ((r >= "0") && (r <= "9")) + value = (r - 'h30); + else + begin + invalid_address = `LPM_TRUE; + end + + address = (address * 10) + value; + end + else if (address_radix == "uns") + begin + if ((r >= "0") && (r <= "9")) + value = (r - 'h30); + else + begin + invalid_address = `LPM_TRUE; + end + + address = (address * 10) + value; + end + else if (address_radix == "bin") + begin + if ((r >= "0") && (r <= "1")) + value = (r - 'h30); + else + begin + invalid_address = `LPM_TRUE; + end + + address = (address * 2) + value; + end + else if (address_radix == "oct") + begin + if ((r >= "0") && (r <= "7")) + value = (r - 'h30); + else + begin + invalid_address = `LPM_TRUE; + end + + address = (address * 8) + value; + end + + if ((r >= 65) && (r <= 90)) + c = tolower(r); + else + c = r; + + {tmp_char,buffer} = {buffer, c}; + end + else if (get_data == `LPM_TRUE) + begin + character_count = character_count +1; + + if (data_radix == "hex") + begin + if ((r >= "0") && (r <= "9")) + value = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + value = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + value = 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + memory_data1 = (memory_data1 * 16) + value; + end + else if ((data_radix == "dec")) + begin + if ((r >= "0") && (r <= "9")) + value = (r - 'h30); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + memory_data1 = (memory_data1 * 10) + value; + end + else if (data_radix == "uns") + begin + if ((r >= "0") && (r <= "9")) + value = (r - 'h30); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + memory_data1 = (memory_data1 * 10) + value; + end + else if (data_radix == "bin") + begin + if ((r >= "0") && (r <= "1")) + value = (r - 'h30); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + memory_data1 = (memory_data1 * 2) + value; + end + else if (data_radix == "oct") + begin + if ((r >= "0") && (r <= "7")) + value = (r - 'h30); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + memory_data1 = (memory_data1 * 8) + value; + end + end + else + begin + first_rec = `LPM_TRUE; + + if ((r >= 65) && (r <= 90)) + c = tolower(r); + else + c = r; + + {tmp_char,buffer} = {buffer, c}; + end + end + $fclose(ifp); + $fclose(ofp); + end +end +endtask // convert_mif2ver + +/****************************************************************/ +/* Read in Intel-hex format data to verilog format data. */ +/* Intel-hex format :nnaaaaattddddcc */ +/****************************************************************/ +task convert_hex2ver; + input[`LPM_MAX_NAME_SZ*8 : 1] in_file; + input width; + output [`LPM_MAX_NAME_SZ*8 : 1] out_file; + reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; + reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; + reg [8:1] c; + reg [3:0] hex, tmp_char; + reg done; + reg error_status; + reg first_rec; + reg last_rec; + + integer width; + integer ifp, ofp, r, r2; + integer i, j, k, m, n; + + integer off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ; + integer line_no; + +begin + done = `LPM_FALSE; + error_status = `LPM_FALSE; + first_rec = `LPM_FALSE; + last_rec = `LPM_FALSE; + + off_addr= 0; + nn= 0; + aaaa= 0; + tt= 0; + cc= 0; + aah= 0; + aal= 0; + dd= 0; + sum = 0; + line_no = 1; + c = 0; + hex = 0; + + if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) + out_file = in_file; + else + begin + ifp = $fopen(in_file, "r"); + if (ifp == `LPM_NULL) + begin + $display("ERROR: cannot read %0s.", in_file); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + end + + out_file = in_file; + + if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX")) + out_file[3*8 : 1] = `LPM_EXT_STR; + else + begin + $display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + end + + if (!done) + begin + ofp = $fopen(out_file, "w"); + if (ofp == `LPM_NULL) + begin + $display("ERROR : cannot write %0s.", out_file); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + end + end + + while((!done) && (!error_status)) + begin : READER + + r = $fgetc(ifp); + + if (r == `LPM_EOF) + begin + if(!first_rec) + begin + error_status = `LPM_TRUE; + $display("WARNING: %0s, Intel-hex data file is empty.", in_file); + $display ("Time: %0t Instance: %m", $time); + end + else if(!last_rec) + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + end + else if (r == `LPM_COLON) + begin + first_rec = `LPM_TRUE; + nn= 0; + aaaa= 0; + tt= 0; + cc= 0; + aah= 0; + aal= 0; + dd= 0; + sum = 0; + + // get record length bytes + for (i = 0; i < 2; i = i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + nn = (nn * 16) + (r - 'h30); + else if ((r >= "A") && (r <= "F")) + nn = (nn * 16) + 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + nn = (nn * 16) + 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + end + + // get address bytes + for (i = 0; i < 4; i = i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + aaaa = (aaaa * 16) + hex; + + if (i < 2) + aal = (aal * 16) + hex; + else + aah = (aah * 16) + hex; + end + + // get record type bytes + for (i = 0; i < 2; i = i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + tt = (tt * 16) + (r - 'h30); + else if ((r >= "A") && (r <= "F")) + tt = (tt * 16) + 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + tt = (tt * 16) + 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + end + + if((tt == 2) && (nn != 2) ) + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + else + begin + + // get the sum of all the bytes for record length, address and record types + sum = nn + aah + aal + tt ; + + // check the record type + case(tt) + // normal_record + 8'h00 : + begin + first_rec = `LPM_TRUE; + i = 0; + k = width / `LPM_AWORD; + if ((width % `LPM_AWORD) != 0) + k = k + 1; + + // k = no. of bytes per entry. + while (i < nn) + begin + $fdisplay(ofp,"@%0h", (aaaa + off_addr)); + for (j = 1; j <= k; j = j +1) + begin + if ((k - j +1) > nn) + begin + for(m = 1; m <= 2; m= m+1) + begin + if((((k-j)*8) + ((3-m)*4) - width) < 4) + $fwrite(ofp, "0"); + end + end + else + begin + // get the data bytes + for(m = 1; m <= 2; m= m+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + if((((k-j)*8) + ((3-m)*4) - width) < 4) + $fwrite(ofp, "%h", hex); + dd = (dd * 16) + hex; + + if(m % 2 == 0) + begin + sum = sum + dd; + dd = 0; + end + end + end + end + $fwrite(ofp, "\n"); + + i = i + k; + aaaa = aaaa + 1; + end // end of while (i < nn) + end + // last record + 8'h01: + begin + last_rec = `LPM_TRUE; + done = `LPM_TRUE; + end + // address base record + 8'h02: + begin + off_addr= 0; + + // get the extended segment address record + for(i = 1; i <= (nn*2); i= i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + off_addr = (off_addr * `LPM_H10) + hex; + dd = (dd * 16) + hex; + + if(i % 2 == 0) + begin + sum = sum + dd; + dd = 0; + end + end + + off_addr = off_addr * `LPM_H10; + end + // address base record + 8'h03: + // get the start segment address record + for(i = 1; i <= (nn*2); i= i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + dd = (dd * 16) + hex; + + if(i % 2 == 0) + begin + sum = sum + dd; + dd = 0; + end + end + // address base record + 8'h04: + begin + off_addr= 0; + + // get the extended linear address record + for(i = 1; i <= (nn*2); i= i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + + off_addr = (off_addr * `LPM_H10) + hex; + dd = (dd * 16) + hex; + + if(i % 2 == 0) + begin + sum = sum + dd; + dd = 0; + end + end + + off_addr = off_addr * `LPM_H10000; + end + // address base record + 8'h05: + // get the start linear address record + for(i = 1; i <= (nn*2); i= i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + dd = (dd * 16) + hex; + + if(i % 2 == 0) + begin + sum = sum + dd; + dd = 0; + end + end + default: + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + endcase + + // get the checksum bytes + for (i = 0; i < 2; i = i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + cc = (cc * 16) + (r - 'h30); + else if ((r >= "A") && (r <= "F")) + cc = 10 + (cc * 16) + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + cc = 10 + (cc * 16) + (r - 'h61); + else + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + disable READER; + end + end + + // Perform check sum. + if(((~sum+1)& `LPM_MASK15) != cc) + begin + error_status = `LPM_TRUE; + $display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + end + end + end + else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) + begin + line_no = line_no +1; + end + else if (r == `LPM_SPACE) + begin + // continue to next character; + end + else + begin + error_status = `LPM_TRUE; + $display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + $display("Time: %0t Instance: %m", $time); + done = `LPM_TRUE; + end + end + $fclose(ifp); + $fclose(ofp); + end +end +endtask // convert_hex2ver + +task convert_to_ver_file; + input[`LPM_MAX_NAME_SZ*8 : 1] in_file; + input width; + output [`LPM_MAX_NAME_SZ*8 : 1] out_file; + reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; + reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; + integer width; +begin + + if((in_file[4*8 : 1] == ".hex") || (in_file[4*8 : 1] == ".HEX") || + (in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) + convert_hex2ver(in_file, width, out_file); + else if((in_file[4*8 : 1] == ".mif") || (in_file[4*8 : 1] == ".MIF")) + convert_mif2ver(in_file, width, out_file); + else + begin + $display("ERROR: Invalid input file name %0s. Expecting file with .hex extension (with Intel-hex data format) or .mif extension (with Altera-mif data format).", in_file); + $display("Time: %0t Instance: %m", $time); + end +end +endtask // convert_to_ver_file + +endmodule // LPM_MEMORY_INITIALIZATION + + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : LPM_HINT_EVALUATION +// +// Description : Common function to grep the value of altera specific parameters +// within the lpm_hint parameter. +// +// Limitation : No error checking to check whether the content of the lpm_hint +// is valid or not. +// +// Results expected: If the target parameter found, return the value of the parameter. +// Otherwise, return empty string. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module LPM_HINT_EVALUATION; + +// FUNCTON DECLARATION + +// This function will search through the string (given string) to look for a match for the +// a given parameter(compare_param_name). It will return the value for the given parameter. +function [8*200:1] GET_PARAMETER_VALUE; + input [8*200:1] given_string; // string to be searched + input [8*50:1] compare_param_name; // parameter name to be looking for in the given_string. + integer param_value_char_count; // to indicate current character count in the param_value + integer param_name_char_count; // to indicate current character count in the param_name + integer white_space_count; + + reg extract_param_value; // if 1 mean extracting parameters value from given string + reg extract_param_name; // if 1 mean extracting parameters name from given string + reg param_found; // to indicate whether compare_param_name have been found in the given_string + reg include_white_space; // if 1, include white space in the parameter value + + reg [8*200:1] reg_string; // to store the value of the given string + reg [8*50:1] param_name; // to store parameter name + reg [8*20:1] param_value; // to store parameter value + reg [8:1] tmp; // to get the value of the current byte +begin + reg_string = given_string; + param_value_char_count = 0; + param_name_char_count =0; + extract_param_value = 1; + extract_param_name = 0; + param_found = 0; + include_white_space = 0; + white_space_count = 0; + + tmp = reg_string[8:1]; + + // checking every bytes of the reg_string from right to left. + while ((tmp != 0 ) && (param_found != 1)) + begin + tmp = reg_string[8:1]; + + //if tmp != ' ' or should include white space (trailing white space are ignored) + if((tmp != 32) || (include_white_space == 1)) + begin + if(tmp == 32) + begin + white_space_count = 1; + end + else if(tmp == 61) // if tmp = '=' + begin + extract_param_value = 0; + extract_param_name = 1; // subsequent bytes should be part of param_name + include_white_space = 0; // ignore the white space (if any) between param_name and '=' + white_space_count = 0; + param_value = param_value >> (8 * (20 - param_value_char_count)); + param_value_char_count = 0; + end + else if (tmp == 44) // if tmp = ',' + begin + extract_param_value = 1; // subsequent bytes should be part of param_value + extract_param_name = 0; + param_name = param_name >> (8 * (50 - param_name_char_count)); + param_name_char_count = 0; + if(param_name == compare_param_name) + param_found = 1; // the compare_param_name have been found in the reg_string + end + else + begin + if(extract_param_value == 1) + begin + param_value_char_count = param_value_char_count + white_space_count + 1; + include_white_space = 1; + if(white_space_count > 0) + begin + param_value = {8'b100000, param_value[20*8:9]}; + white_space_count = 0; + end + param_value = {tmp, param_value[20*8:9]}; + end + else if(extract_param_name == 1) + begin + param_name = {tmp, param_name[50*8:9]}; + param_name_char_count = param_name_char_count + 1; + end + end + end + reg_string = reg_string >> 8; // shift 1 byte to the right + end + + // for the case whether param_name is the left most part of the reg_string + if(extract_param_name == 1) + begin + param_name = param_name >> (8 * (50 - param_name_char_count)); + + if(param_name == compare_param_name) + param_found = 1; + end + + if (param_found == 1) + GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for + else + GET_PARAMETER_VALUE = ""; // return empty string if parameter not found + +end +endfunction + +endmodule // LPM_HINT_EVALUATION + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module LPM_DEVICE_FAMILIES; + +function IS_FAMILY_CYCLONE; + input[8*20:1] device; + reg is_cyclone; +begin + if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) + is_cyclone = 1; + else + is_cyclone = 0; + + IS_FAMILY_CYCLONE = is_cyclone; +end +endfunction //IS_FAMILY_CYCLONE + +function IS_FAMILY_MAX3000A; + input[8*20:1] device; + reg is_max3000a; +begin + if ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a")) + is_max3000a = 1; + else + is_max3000a = 0; + + IS_FAMILY_MAX3000A = is_max3000a; +end +endfunction //IS_FAMILY_MAX3000A + +function IS_FAMILY_MAX7000A; + input[8*20:1] device; + reg is_max7000a; +begin + if ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a")) + is_max7000a = 1; + else + is_max7000a = 0; + + IS_FAMILY_MAX7000A = is_max7000a; +end +endfunction //IS_FAMILY_MAX7000A + +function IS_FAMILY_MAX7000AE; + input[8*20:1] device; + reg is_max7000ae; +begin + if ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae")) + is_max7000ae = 1; + else + is_max7000ae = 0; + + IS_FAMILY_MAX7000AE = is_max7000ae; +end +endfunction //IS_FAMILY_MAX7000AE + +function IS_FAMILY_MAX7000B; + input[8*20:1] device; + reg is_max7000b; +begin + if ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b")) + is_max7000b = 1; + else + is_max7000b = 0; + + IS_FAMILY_MAX7000B = is_max7000b; +end +endfunction //IS_FAMILY_MAX7000B + +function IS_FAMILY_MAX7000S; + input[8*20:1] device; + reg is_max7000s; +begin + if ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s")) + is_max7000s = 1; + else + is_max7000s = 0; + + IS_FAMILY_MAX7000S = is_max7000s; +end +endfunction //IS_FAMILY_MAX7000S + +function IS_FAMILY_STRATIXGX; + input[8*20:1] device; + reg is_stratixgx; +begin + if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) + is_stratixgx = 1; + else + is_stratixgx = 0; + + IS_FAMILY_STRATIXGX = is_stratixgx; +end +endfunction //IS_FAMILY_STRATIXGX + +function IS_FAMILY_STRATIX; + input[8*20:1] device; + reg is_stratix; +begin + if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) + is_stratix = 1; + else + is_stratix = 0; + + IS_FAMILY_STRATIX = is_stratix; +end +endfunction //IS_FAMILY_STRATIX + +function FEATURE_FAMILY_BASE_STRATIX; + input[8*20:1] device; + reg var_family_base_stratix; +begin + if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) ) + var_family_base_stratix = 1; + else + var_family_base_stratix = 0; + + FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix; +end +endfunction //FEATURE_FAMILY_BASE_STRATIX + +function FEATURE_FAMILY_BASE_CYCLONE; + input[8*20:1] device; + reg var_family_base_cyclone; +begin + if (IS_FAMILY_CYCLONE(device) ) + var_family_base_cyclone = 1; + else + var_family_base_cyclone = 0; + + FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone; +end +endfunction //FEATURE_FAMILY_BASE_CYCLONE + +function FEATURE_FAMILY_MAX; + input[8*20:1] device; + reg var_family_max; +begin + if ((device == "MAX5000") || IS_FAMILY_MAX3000A(device) || (device == "MAX7000") || IS_FAMILY_MAX7000A(device) || IS_FAMILY_MAX7000AE(device) || (device == "MAX7000E") || IS_FAMILY_MAX7000S(device) || IS_FAMILY_MAX7000B(device) || (device == "MAX9000") ) + var_family_max = 1; + else + var_family_max = 0; + + FEATURE_FAMILY_MAX = var_family_max; +end +endfunction //FEATURE_FAMILY_MAX + +function IS_VALID_FAMILY; + input[8*20:1] device; + reg is_valid; +begin + if (((device == "Arria 10") || (device == "ARRIA 10") || (device == "arria 10") || (device == "Arria10") || (device == "ARRIA10") || (device == "arria10") || (device == "Arria VI") || (device == "ARRIA VI") || (device == "arria vi") || (device == "ArriaVI") || (device == "ARRIAVI") || (device == "arriavi") || (device == "Night Fury") || (device == "NIGHT FURY") || (device == "night fury") || (device == "nightfury") || (device == "NIGHTFURY") || (device == "Arria 10 (GX/SX/GT)") || (device == "ARRIA 10 (GX/SX/GT)") || (device == "arria 10 (gx/sx/gt)") || (device == "Arria10(GX/SX/GT)") || (device == "ARRIA10(GX/SX/GT)") || (device == "arria10(gx/sx/gt)") || (device == "Arria 10 (GX)") || (device == "ARRIA 10 (GX)") || (device == "arria 10 (gx)") || (device == "Arria10(GX)") || (device == "ARRIA10(GX)") || (device == "arria10(gx)") || (device == "Arria 10 (SX)") || (device == "ARRIA 10 (SX)") || (device == "arria 10 (sx)") || (device == "Arria10(SX)") || (device == "ARRIA10(SX)") || (device == "arria10(sx)") || (device == "Arria 10 (GT)") || (device == "ARRIA 10 (GT)") || (device == "arria 10 (gt)") || (device == "Arria10(GT)") || (device == "ARRIA10(GT)") || (device == "arria10(gt)")) + || ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite")) + || ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha")) + || ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz")) + || ((device == "Arria V GZ") || (device == "ARRIA V GZ") || (device == "arria v gz") || (device == "ArriaVGZ") || (device == "ARRIAVGZ") || (device == "arriavgz")) + || ((device == "Arria V") || (device == "ARRIA V") || (device == "arria v") || (device == "Arria V (GT/GX)") || (device == "ARRIA V (GT/GX)") || (device == "arria v (gt/gx)") || (device == "ArriaV(GT/GX)") || (device == "ARRIAV(GT/GX)") || (device == "arriav(gt/gx)") || (device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V (GT/GX/ST/SX)") || (device == "ARRIA V (GT/GX/ST/SX)") || (device == "arria v (gt/gx/st/sx)") || (device == "ArriaV(GT/GX/ST/SX)") || (device == "ARRIAV(GT/GX/ST/SX)") || (device == "arriav(gt/gx/st/sx)") || (device == "Arria V (GT)") || (device == "ARRIA V (GT)") || (device == "arria v (gt)") || (device == "ArriaV(GT)") || (device == "ARRIAV(GT)") || (device == "arriav(gt)") || (device == "Arria V (GX)") || (device == "ARRIA V (GX)") || (device == "arria v (gx)") || (device == "ArriaV(GX)") || (device == "ARRIAV(GX)") || (device == "arriav(gx)") || (device == "Arria V (ST)") || (device == "ARRIA V (ST)") || (device == "arria v (st)") || (device == "ArriaV(ST)") || (device == "ARRIAV(ST)") || (device == "arriav(st)") || (device == "Arria V (SX)") || (device == "ARRIA V (SX)") || (device == "arria v (sx)") || (device == "ArriaV(SX)") || (device == "ARRIAV(SX)") || (device == "arriav(sx)")) + || ((device == "BS") || (device == "bs")) + || ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan") || (device == "CycloneII") || (device == "CYCLONEII") || (device == "cycloneii")) + || ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie")) + || ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii")) + || ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive")) + || ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray")) + || ((device == "Cyclone V") || (device == "CYCLONE V") || (device == "cyclone v") || (device == "CycloneV") || (device == "CYCLONEV") || (device == "cyclonev") || (device == "Cyclone V (GT/GX/E/SX)") || (device == "CYCLONE V (GT/GX/E/SX)") || (device == "cyclone v (gt/gx/e/sx)") || (device == "CycloneV(GT/GX/E/SX)") || (device == "CYCLONEV(GT/GX/E/SX)") || (device == "cyclonev(gt/gx/e/sx)") || (device == "Cyclone V (E/GX/GT/SX/SE/ST)") || (device == "CYCLONE V (E/GX/GT/SX/SE/ST)") || (device == "cyclone v (e/gx/gt/sx/se/st)") || (device == "CycloneV(E/GX/GT/SX/SE/ST)") || (device == "CYCLONEV(E/GX/GT/SX/SE/ST)") || (device == "cyclonev(e/gx/gt/sx/se/st)") || (device == "Cyclone V (E)") || (device == "CYCLONE V (E)") || (device == "cyclone v (e)") || (device == "CycloneV(E)") || (device == "CYCLONEV(E)") || (device == "cyclonev(e)") || (device == "Cyclone V (GX)") || (device == "CYCLONE V (GX)") || (device == "cyclone v (gx)") || (device == "CycloneV(GX)") || (device == "CYCLONEV(GX)") || (device == "cyclonev(gx)") || (device == "Cyclone V (GT)") || (device == "CYCLONE V (GT)") || (device == "cyclone v (gt)") || (device == "CycloneV(GT)") || (device == "CYCLONEV(GT)") || (device == "cyclonev(gt)") || (device == "Cyclone V (SX)") || (device == "CYCLONE V (SX)") || (device == "cyclone v (sx)") || (device == "CycloneV(SX)") || (device == "CYCLONEV(SX)") || (device == "cyclonev(sx)") || (device == "Cyclone V (SE)") || (device == "CYCLONE V (SE)") || (device == "cyclone v (se)") || (device == "CycloneV(SE)") || (device == "CYCLONEV(SE)") || (device == "cyclonev(se)") || (device == "Cyclone V (ST)") || (device == "CYCLONE V (ST)") || (device == "cyclone v (st)") || (device == "CycloneV(ST)") || (device == "CYCLONEV(ST)") || (device == "cyclonev(st)")) + || ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) + || ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion")) + || ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx")) + || ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)")) + || ((device == "MAX 10") || (device == "max 10") || (device == "MAX 10 FPGA") || (device == "max 10 fpga") || (device == "Zippleback") || (device == "ZIPPLEBACK") || (device == "zippleback") || (device == "MAX10") || (device == "max10") || (device == "MAX 10 (DA/DF/DC/SA/SC)") || (device == "max 10 (da/df/dc/sa/sc)") || (device == "MAX10(DA/DF/DC/SA/SC)") || (device == "max10(da/df/dc/sa/sc)") || (device == "MAX 10 (DA)") || (device == "max 10 (da)") || (device == "MAX10(DA)") || (device == "max10(da)") || (device == "MAX 10 (DF)") || (device == "max 10 (df)") || (device == "MAX10(DF)") || (device == "max10(df)") || (device == "MAX 10 (DC)") || (device == "max 10 (dc)") || (device == "MAX10(DC)") || (device == "max10(dc)") || (device == "MAX 10 (SA)") || (device == "max 10 (sa)") || (device == "MAX10(SA)") || (device == "max10(sa)") || (device == "MAX 10 (SC)") || (device == "max 10 (sc)") || (device == "MAX10(SC)") || (device == "max10(sc)")) + || ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami")) + || ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade")) + || ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a")) + || ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a")) + || ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae")) + || ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b")) + || ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s")) + || ((device == "Stratix 10") || (device == "STRATIX 10") || (device == "stratix 10") || (device == "Stratix10") || (device == "STRATIX10") || (device == "stratix10") || (device == "nadder") || (device == "NADDER") || (device == "Stratix 10 (GX/SX)") || (device == "STRATIX 10 (GX/SX)") || (device == "stratix 10 (gx/sx)") || (device == "Stratix10(GX/SX)") || (device == "STRATIX10(GX/SX)") || (device == "stratix10(gx/sx)") || (device == "Stratix 10 (GX)") || (device == "STRATIX 10 (GX)") || (device == "stratix 10 (gx)") || (device == "Stratix10(GX)") || (device == "STRATIX10(GX)") || (device == "stratix10(gx)") || (device == "Stratix 10 (SX)") || (device == "STRATIX 10 (SX)") || (device == "stratix 10 (sx)") || (device == "Stratix10(SX)") || (device == "STRATIX10(SX)") || (device == "stratix10(sx)")) + || ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) + || ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx")) + || ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong")) + || ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii")) + || ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)")) + || ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GT)") || (device == "STRATIX V (GT)") || (device == "stratix v (gt)") || (device == "StratixV(GT)") || (device == "STRATIXV(GT)") || (device == "stratixv(gt)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GS/GT)") || (device == "STRATIX V (GS/GT)") || (device == "stratix v (gs/gt)") || (device == "StratixV(GS/GT)") || (device == "STRATIXV(GS/GT)") || (device == "stratixv(gs/gt)") || (device == "Stratix V (GT/GX)") || (device == "STRATIX V (GT/GX)") || (device == "stratix v (gt/gx)") || (device == "StratixV(GT/GX)") || (device == "STRATIXV(GT/GX)") || (device == "stratixv(gt/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)") || (device == "Stratix V (GT/GS)") || (device == "STRATIX V (GT/GS)") || (device == "stratix v (gt/gs)") || (device == "StratixV(GT/GS)") || (device == "STRATIXV(GT/GS)") || (device == "stratixv(gt/gs)") || (device == "Stratix V (GX/GT)") || (device == "STRATIX V (GX/GT)") || (device == "stratix v (gx/gt)") || (device == "StratixV(GX/GT)") || (device == "STRATIXV(GX/GT)") || (device == "stratixv(gx/gt)") || (device == "Stratix V (GS/GT/GX)") || (device == "STRATIX V (GS/GT/GX)") || (device == "stratix v (gs/gt/gx)") || (device == "Stratix V (GS/GX/GT)") || (device == "STRATIX V (GS/GX/GT)") || (device == "stratix v (gs/gx/gt)") || (device == "Stratix V (GT/GS/GX)") || (device == "STRATIX V (GT/GS/GX)") || (device == "stratix v (gt/gs/gx)") || (device == "Stratix V (GT/GX/GS)") || (device == "STRATIX V (GT/GX/GS)") || (device == "stratix v (gt/gx/gs)") || (device == "Stratix V (GX/GS/GT)") || (device == "STRATIX V (GX/GS/GT)") || (device == "stratix v (gx/gs/gt)") || (device == "Stratix V (GX/GT/GS)") || (device == "STRATIX V (GX/GT/GS)") || (device == "stratix v (gx/gt/gs)") || (device == "StratixV(GS/GT/GX)") || (device == "STRATIXV(GS/GT/GX)") || (device == "stratixv(gs/gt/gx)") || (device == "StratixV(GS/GX/GT)") || (device == "STRATIXV(GS/GX/GT)") || (device == "stratixv(gs/gx/gt)") || (device == "StratixV(GT/GS/GX)") || (device == "STRATIXV(GT/GS/GX)") || (device == "stratixv(gt/gs/gx)") || (device == "StratixV(GT/GX/GS)") || (device == "STRATIXV(GT/GX/GS)") || (device == "stratixv(gt/gx/gs)") || (device == "StratixV(GX/GS/GT)") || (device == "STRATIXV(GX/GS/GT)") || (device == "stratixv(gx/gs/gt)") || (device == "StratixV(GX/GT/GS)") || (device == "STRATIXV(GX/GT/GS)") || (device == "stratixv(gx/gt/gs)") || (device == "Stratix V (GS/GT/GX/E)") || (device == "STRATIX V (GS/GT/GX/E)") || (device == "stratix v (gs/gt/gx/e)") || (device == "StratixV(GS/GT/GX/E)") || (device == "STRATIXV(GS/GT/GX/E)") || (device == "stratixv(gs/gt/gx/e)") || (device == "Stratix V (E)") || (device == "STRATIX V (E)") || (device == "stratix v (e)") || (device == "StratixV(E)") || (device == "STRATIXV(E)") || (device == "stratixv(e)")) + || ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) + || ((device == "eFPGA 28 HPM") || (device == "EFPGA 28 HPM") || (device == "efpga 28 hpm") || (device == "eFPGA28HPM") || (device == "EFPGA28HPM") || (device == "efpga28hpm") || (device == "Bedrock") || (device == "BEDROCK") || (device == "bedrock"))) + is_valid = 1; + else + is_valid = 0; + + IS_VALID_FAMILY = is_valid; +end +endfunction // IS_VALID_FAMILY + + +endmodule // LPM_DEVICE_FAMILIES +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_constant +// +// Description : Parameterized constant generator megafunction. lpm_constant +// may be useful for convert a parameter into a constant. +// +// Limitation : n/a +// +// Results expected: Value specified by the argument to LPM_CVALUE. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_constant ( + result // Value specified by the argument to LPM_CVALUE. (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the result[] port. (Required) + parameter lpm_cvalue = 0; // Constant value to be driven out on the + // result[] port. (Required) + parameter lpm_strength = "UNUSED"; + parameter lpm_type = "lpm_constant"; + parameter lpm_hint = "UNUSED"; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INTERNAL REGISTERS DECLARATION + reg[32:0] int_value; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + int_value = lpm_cvalue; + end + +// CONTINOUS ASSIGNMENT + assign result = int_value[lpm_width-1:0]; + +endmodule // lpm_constant + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_inv +// +// Description : Parameterized inverter megafunction. +// +// Limitation : n/a +// +// Results expected: Inverted value of input data +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_inv ( + data, // Data input to the lpm_inv. (Required) + result // inverted result. (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[] and result[] ports. (Required) + parameter lpm_type = "lpm_inv"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] result; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(data) + result = ~data; + +endmodule // lpm_inv + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_and +// +// Description : Parameterized AND gate. This megafunction takes in data inputs +// for a number of AND gates. +// +// Limitation : n/a +// +// Results expected: Each result[] bit is the result of each AND gate. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_and ( + data, // Data input to the AND gate. (Required) + result // Result of the AND operators. (Required) +); + +// GLOBAL PARAMETER DECLARATION + // Width of the data[][] and result[] ports. Number of AND gates. (Required) + parameter lpm_width = 1; + // Number of inputs to each AND gate. Number of input buses. (Required) + parameter lpm_size = 1; + parameter lpm_type = "lpm_and"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [(lpm_size * lpm_width)-1:0] data; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] result_tmp; + +// LOCAL INTEGER DECLARATION + integer i; + integer j; + integer k; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_size <= 0) + begin + $display("Value of lpm_size parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(data) + begin + for (i=0; i<lpm_width; i=i+1) + begin + result_tmp[i] = 1'b1; + for (j=0; j<lpm_size; j=j+1) + begin + k = (j * lpm_width) + i; + result_tmp[i] = result_tmp[i] & data[k]; + end + end + end + +// CONTINOUS ASSIGNMENT + assign result = result_tmp; +endmodule // lpm_and + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_or +// +// Description : Parameterized OR gate megafunction. This megafunction takes in +// data inputs for a number of OR gates. +// +// Limitation : n/a +// +// Results expected: Each result[] bit is the result of each OR gate. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_or ( + data, // Data input to the OR gates. (Required) + result // Result of OR operators. (Required) +); + +// GLOBAL PARAMETER DECLARATION + // Width of the data[] and result[] ports. Number of OR gates. (Required) + parameter lpm_width = 1; + // Number of inputs to each OR gate. Number of input buses. (Required) + parameter lpm_size = 1; + parameter lpm_type = "lpm_or"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [(lpm_size * lpm_width)-1:0] data; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] result_tmp; + +// LOCAL INTEGER DECLARATION + integer i; + integer j; + integer k; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_size <= 0) + begin + $display("Value of lpm_size parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(data) + begin + for (i=0; i<lpm_width; i=i+1) + begin + result_tmp[i] = 1'b0; + for (j=0; j<lpm_size; j=j+1) + begin + k = (j * lpm_width) + i; + result_tmp[i] = result_tmp[i] | data[k]; + end + end + end + +// CONTINOUS ASSIGNMENT + assign result = result_tmp; + +endmodule // lpm_or + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_xor +// +// Description : Parameterized XOR gate megafunction. This megafunction takes in +// data inputs for a number of XOR gates. +// +// Limitation : n/a. +// +// Results expected: Each result[] bit is the result of each XOR gates. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_xor ( + data, // Data input to the XOR gates. (Required) + result // Result of XOR operators. (Required) +); + +// GLOBAL PARAMETER DECLARATION + // Width of the data[] and result[] ports. Number of XOR gates. (Required) + parameter lpm_width = 1; + // Number of inputs to each XOR gate. Number of input buses. (Required) + parameter lpm_size = 1; + parameter lpm_type = "lpm_xor"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [(lpm_size * lpm_width)-1:0] data; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] result_tmp; + +// LOCAL INTEGER DECLARATION + integer i; + integer j; + integer k; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_size <= 0) + begin + $display("Value of lpm_size parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(data) + begin + for (i=0; i<lpm_width; i=i+1) + begin + result_tmp[i] = 1'b0; + for (j=0; j<lpm_size; j=j+1) + begin + k = (j * lpm_width) + i; + result_tmp[i] = result_tmp[i] ^ data[k]; + end + end + end + +// CONTINOUS ASSIGNMENT + assign result = result_tmp; + +endmodule // lpm_xor + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_bustri +// +// Description : Parameterized tri-state buffer. lpm_bustri is useful for +// controlling both unidirectional and bidirectional I/O bus +// controllers. +// +// Limitation : n/a +// +// Results expected: Belows are the three configurations which are valid: +// +// 1) Only the input ports data[LPM_WIDTH-1..0] and enabledt are +// present, and only the output ports tridata[LPM_WIDTH-1..0] +// are present. +// +// ---------------------------------------------------- +// | Input | Output | +// |====================================================| +// | enabledt | tridata[LPM_WIDTH-1..0] | +// |----------------------------------------------------| +// | 0 | Z | +// |----------------------------------------------------| +// | 1 | DATA[LPM_WIDTH-1..0] | +// ---------------------------------------------------- +// +// 2) Only the input ports tridata[LPM_WIDTH-1..0] and enabletr +// are present, and only the output ports result[LPM_WIDTH-1..0] +// are present. +// +// ---------------------------------------------------- +// | Input | Output | +// |====================================================| +// | enabletr | result[LPM_WIDTH-1..0] | +// |----------------------------------------------------| +// | 0 | Z | +// |----------------------------------------------------| +// | 1 | tridata[LPM_WIDTH-1..0] | +// ---------------------------------------------------- +// +// 3) All ports are present: input ports data[LPM_WIDTH-1..0], +// enabledt, and enabletr; output ports result[LPM_WIDTH-1..0]; +// and bidirectional ports tridata[LPM_WIDTH-1..0]. +// +// ---------------------------------------------------------------------------- +// | Input | Bidirectional | Output | +// |----------------------------------------------------------------------------| +// | enabledt | enabletr | tridata[LPM_WIDTH-1..0] | result[LPM_WIDTH-1..0] | +// |============================================================================| +// | 0 | 0 | Z (input) | Z | +// |----------------------------------------------------------------------------| +// | 0 | 1 | Z (input) | tridata[LPM_WIDTH-1..0] | +// |----------------------------------------------------------------------------| +// | 1 | 0 | data[LPM_WIDTH-1..0] | Z | +// |----------------------------------------------------------------------------| +// | 1 | 1 | data[LPM_WIDTH-1..0] | data[LPM_WIDTH-1..0] | +// ---------------------------------------------------------------------------- +// +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_bustri ( + tridata, // Bidirectional bus signal. (Required) + data, // Data input to the tridata[] bus. (Required) + enabletr, // If high, enables tridata[] onto the result bus. + enabledt, // If high, enables data onto the tridata[] bus. + result // Output from the tridata[] bus. +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_type = "lpm_bustri"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input enabletr; + input enabledt; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INPUT/OUTPUT PORT DECLARATION + inout [lpm_width-1:0] tridata; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] result; + +// INTERNAL TRI DECLARATION + tri1 enabletr; + tri1 enabledt; + + wire i_enabledt; + wire i_enabletr; + buf (i_enabledt, enabledt); + buf (i_enabletr, enabletr); + + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(data or tridata or i_enabletr or i_enabledt) + begin + if ((i_enabledt == 1'b0) && (i_enabletr == 1'b1)) + begin + result = tridata; + end + else if ((i_enabledt == 1'b1) && (i_enabletr == 1'b1)) + begin + result = data; + end + else + begin + result = {lpm_width{1'bz}}; + end + end + +// CONTINOUS ASSIGNMENT + assign tridata = (i_enabledt == 1) ? data : {lpm_width{1'bz}}; + +endmodule // lpm_bustri + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_mux +// +// Description : Parameterized multiplexer megafunctions. +// +// Limitation : n/a +// +// Results expected: Selected input port. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_mux ( + data, // Data input. (Required) + sel, // Selects one of the input buses. (Required) + clock, // Clock for pipelined usage + aclr, // Asynchronous clear for pipelined usage. + clken, // Clock enable for pipelined usage. + result // Selected input port. (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[][] and result[] ports. (Required) + parameter lpm_size = 2; // Number of input buses to the multiplexer. (Required) + parameter lpm_widths = 1; // Width of the sel[] input port. (Required) + parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency + // associated with the result[] output. + parameter lpm_type = "lpm_mux"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [(lpm_size * lpm_width)-1:0] data; + input [lpm_widths-1:0] sel; + input clock; + input aclr; + input clken; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] result_pipe [lpm_pipeline+1:0]; + reg [lpm_width-1:0] tmp_result; + +// LOCAL INTEGER DECLARATION + integer i; + integer pipe_ptr; + +// INTERNAL TRI DECLARATION + tri0 aclr; + tri0 clock; + tri1 clken; + + wire i_aclr; + wire i_clock; + wire i_clken; + buf (i_aclr, aclr); + buf (i_clock, clock); + buf (i_clken, clken); + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_size <= 1) + begin + $display("Value of lpm_size parameter must be greater than 1 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_widths <= 0) + begin + $display("Value of lpm_widths parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_pipeline < 0) + begin + $display("Value of lpm_pipeline parameter must NOT less than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + pipe_ptr = 0; + end + + +// ALWAYS CONSTRUCT BLOCK + always @(data or sel) + begin + tmp_result = 0; + + if (sel < lpm_size) + begin + for (i = 0; i < lpm_width; i = i + 1) + tmp_result[i] = data[(sel * lpm_width) + i]; + end + else + tmp_result = {lpm_width{1'bx}}; + end + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) + begin + for (i = 0; i <= (lpm_pipeline+1); i = i + 1) + result_pipe[i] <= 1'b0; + pipe_ptr <= 0; + end + else if (i_clken == 1'b1) + begin + result_pipe[pipe_ptr] <= tmp_result; + + if (lpm_pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; + end + end + +// CONTINOUS ASSIGNMENT + assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; + +endmodule // lpm_mux +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_decode +// +// Description : Parameterized decoder megafunction. +// +// Limitation : n/a +// +// Results expected: Decoded output. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_decode ( + data, // Data input. Treated as an unsigned binary encoded number. (Required) + enable, // Enable. All outputs low when not active. + clock, // Clock for pipelined usage. + aclr, // Asynchronous clear for pipelined usage. + clken, // Clock enable for pipelined usage. + eq // Decoded output. (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[] port, or the + // input value to be decoded. (Required) + parameter lpm_decodes = 1 << lpm_width; // Number of explicit decoder outputs. (Required) + parameter lpm_pipeline = 0; // Number of Clock cycles of latency + parameter lpm_type = "lpm_decode"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input enable; + input clock; + input aclr; + input clken; + +// OUTPUT PORT DECLARATION + output [lpm_decodes-1:0] eq; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_decodes-1:0] eq_pipe [(lpm_pipeline+1):0]; + reg [lpm_decodes-1:0] tmp_eq; + +// LOCAL INTEGER DECLARATION + integer i; + integer pipe_ptr; + +// INTERNAL TRI DECLARATION + tri1 enable; + tri0 clock; + tri0 aclr; + tri1 clken; + + wire i_clock; + wire i_clken; + wire i_aclr; + wire i_enable; + buf (i_clock, clock); + buf (i_clken, clken); + buf (i_aclr, aclr); + buf (i_enable, enable); + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if (lpm_decodes <= 0) + begin + $display("Value of lpm_decodes parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if (lpm_decodes > (1 << lpm_width)) + begin + $display("Value of lpm_decodes parameter must be less or equal to 2^lpm_width (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if (lpm_pipeline < 0) + begin + $display("Value of lpm_pipeline parameter must be greater or equal to 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + pipe_ptr = 0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(data or i_enable) + begin + tmp_eq = {lpm_decodes{1'b0}}; + if (i_enable) + tmp_eq[data] = 1'b1; + end + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) + begin + for (i = 0; i <= lpm_pipeline; i = i + 1) + eq_pipe[i] <= {lpm_decodes{1'b0}}; + + pipe_ptr <= 0; + end + else if (clken == 1'b1) + begin + eq_pipe[pipe_ptr] <= tmp_eq; + + if (lpm_pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; + end + end + + assign eq = (lpm_pipeline > 0) ? eq_pipe[pipe_ptr] : tmp_eq; + +endmodule // lpm_decode +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_clshift +// +// Description : Parameterized combinatorial logic shifter or barrel shifter +// megafunction. +// +// Limitation : n/a +// +// Results expected: Return the shifted data and underflow/overflow status bit. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_clshift ( + data, // Data to be shifted. (Required) + distance, // Number of positions to shift data[] in the direction specified + // by the direction port. (Required) + direction, // Direction of shift. Low = left (toward the MSB), + // high = right (toward the LSB). + clock, // Clock for pipelined usage. + aclr, // Asynchronous clear for pipelined usage. + clken, // Clock enable for pipelined usage. + result, // Shifted data. (Required) + underflow, // Logical or arithmetic underflow. + overflow // Logical or arithmetic overflow. +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[] and result[] ports. Must be + // greater than 0 (Required) + parameter lpm_widthdist = 1; // Width of the distance[] input port. (Required) + parameter lpm_shifttype = "LOGICAL"; // Type of shifting operation to be performed. + parameter lpm_pipeline = 0; // Number of Clock cycles of latency + parameter lpm_type = "lpm_clshift"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input [lpm_widthdist-1:0] distance; + input direction; + input clock; + input aclr; + input clken; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + output underflow; + output overflow; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] ONES; + reg [lpm_width-1:0] ZEROS; + reg [lpm_width-1:0] tmp_result; + reg tmp_underflow; + reg tmp_overflow; + reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0]; + reg [(lpm_pipeline+1):0] overflow_pipe; + reg [(lpm_pipeline+1):0] underflow_pipe; + +// LOCAL INTEGER DECLARATION + integer i; + integer i1; + integer pipe_ptr; + +// INTERNAL TRI DECLARATION + tri0 direction; + tri0 clock; + tri0 aclr; + tri1 clken; + + wire i_direction; + wire i_clock; + wire i_clken; + wire i_aclr; + buf (i_direction, direction); + buf (i_clock, clock); + buf (i_clken, clken); + buf (i_aclr, aclr); + + +// FUNCTON DECLARATION + // Perform logival shift operation + function [lpm_width+1:0] LogicShift; + input [lpm_width-1:0] data; + input [lpm_widthdist-1:0] shift_num; + input direction; + reg [lpm_width-1:0] tmp_buf; + reg underflow; + reg overflow; + + begin + tmp_buf = data; + overflow = 1'b0; + underflow = 1'b0; + if ((direction) && (shift_num > 0)) // shift right + begin + tmp_buf = data >> shift_num; + if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS))) + underflow = 1'b1; + end + else if (shift_num > 0) // shift left + begin + tmp_buf = data << shift_num; + if ((data != ZEROS) && ((shift_num >= lpm_width) + || ((data >> (lpm_width-shift_num)) != ZEROS))) + overflow = 1'b1; + end + LogicShift = {overflow,underflow,tmp_buf[lpm_width-1:0]}; + end + endfunction // LogicShift + + // Perform Arithmetic shift operation + function [lpm_width+1:0] ArithShift; + input [lpm_width-1:0] data; + input [lpm_widthdist-1:0] shift_num; + input direction; + reg [lpm_width-1:0] tmp_buf; + reg underflow; + reg overflow; + integer i; + integer i1; + + begin + tmp_buf = data; + overflow = 1'b0; + underflow = 1'b0; + + if (shift_num < lpm_width) + begin + if ((direction) && (shift_num > 0)) // shift right + begin + if (data[lpm_width-1] == 1'b0) // positive number + begin + tmp_buf = data >> shift_num; + if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS))) + underflow = 1'b1; + end + else // negative number + begin + tmp_buf = (data >> shift_num) | (ONES << (lpm_width - shift_num)); + if ((data != ONES) && ((shift_num >= lpm_width-1) || (tmp_buf == ONES))) + underflow = 1'b1; + end + end + else if (shift_num > 0) // shift left + begin + tmp_buf = data << shift_num; + + for (i=lpm_width-1; i >= lpm_width-shift_num; i=i-1) + begin + if(data[i-1] != data[lpm_width-1]) + overflow = 1'b1; + end + end + end + else // shift_num >= lpm_width + begin + if (direction) + begin + for (i=0; i < lpm_width; i=i+1) + tmp_buf[i] = data[lpm_width-1]; + + underflow = 1'b1; + end + else + begin + tmp_buf = {lpm_width{1'b0}}; + + if (data != ZEROS) + begin + overflow = 1'b1; + end + end + end + ArithShift = {overflow,underflow,tmp_buf[lpm_width-1:0]}; + end + endfunction // ArithShift + + // Perform rotate shift operation + function [lpm_width+1:0] RotateShift; + input [lpm_width-1:0] data; + input [lpm_widthdist-1:0] shift_num; + input direction; + reg [lpm_width-1:0] tmp_buf; + + begin + tmp_buf = data; + if ((direction) && (shift_num > 0)) // shift right + tmp_buf = (data >> shift_num) | (data << (lpm_width - shift_num)); + else if (shift_num > 0) // shift left + tmp_buf = (data << shift_num) | (data >> (lpm_width - shift_num)); + RotateShift = {2'bx, tmp_buf[lpm_width-1:0]}; + end + endfunction // RotateShift + +// INITIAL CONSTRUCT BLOCK + initial + begin + if ((lpm_shifttype != "LOGICAL") && + (lpm_shifttype != "ARITHMETIC") && + (lpm_shifttype != "ROTATE") && + (lpm_shifttype != "UNUSED")) // non-LPM 220 standard + begin + $display("Error! LPM_SHIFTTYPE value must be \"LOGICAL\", \"ARITHMETIC\", or \"ROTATE\"."); + $display("Time: %0t Instance: %m", $time); + end + + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_widthdist <= 0) + begin + $display("Value of lpm_widthdist parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + for (i=0; i < lpm_width; i=i+1) + begin + ONES[i] = 1'b1; + ZEROS[i] = 1'b0; + end + + for (i = 0; i <= lpm_pipeline; i = i + 1) + begin + result_pipe[i] = ZEROS; + overflow_pipe[i] = 1'b0; + underflow_pipe[i] = 1'b0; + end + + tmp_result = ZEROS; + tmp_underflow = 1'b0; + tmp_overflow = 1'b0; + pipe_ptr = 0; + + end + +// ALWAYS CONSTRUCT BLOCK + always @(data or i_direction or distance) + begin + if ((lpm_shifttype == "LOGICAL") || (lpm_shifttype == "UNUSED")) + {tmp_overflow, tmp_underflow, tmp_result} = LogicShift(data, distance, i_direction); + else if (lpm_shifttype == "ARITHMETIC") + {tmp_overflow, tmp_underflow, tmp_result} = ArithShift(data, distance, i_direction); + else if (lpm_shifttype == "ROTATE") + {tmp_overflow, tmp_underflow, tmp_result} = RotateShift(data, distance, i_direction); + end + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) + begin + for (i1 = 0; i1 <= lpm_pipeline; i1 = i1 + 1) + begin + result_pipe[i1] <= {lpm_width{1'b0}}; + overflow_pipe[i1] <= 1'b0; + underflow_pipe[i1] <= 1'b0; + end + pipe_ptr <= 0; + end + else if (i_clken == 1'b1) + begin + result_pipe[pipe_ptr] <= tmp_result; + overflow_pipe[pipe_ptr] <= tmp_overflow; + underflow_pipe[pipe_ptr] <= tmp_underflow; + + if (lpm_pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; + end + end + + assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; + assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow; + assign underflow = (lpm_pipeline > 0) ? underflow_pipe[pipe_ptr] : tmp_underflow; + +endmodule // lpm_clshift +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_add_sub +// +// Description : Parameterized adder/subtractor megafunction. +// +// Limitation : n/a +// +// Results expected: If performs as adder, the result will be dataa[]+datab[]+cin. +// If performs as subtractor, the result will be dataa[]-datab[]+cin-1. +// Also returns carry out bit and overflow status bit. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_add_sub ( + dataa, // Augend/Minuend + datab, // Addend/Subtrahend + cin, // Carry-in to the low-order bit. + add_sub, // If the signal is high, the operation = dataa[]+datab[]+cin. + // If the signal is low, the operation = dataa[]-datab[]+cin-1. + + clock, // Clock for pipelined usage. + aclr, // Asynchronous clear for pipelined usage. + clken, // Clock enable for pipelined usage. + result, // dataa[]+datab[]+cin or dataa[]-datab[]+cin-1 + cout, // Carry-out (borrow-in) of the MSB. + overflow // Result exceeds available precision. +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the dataa[],datab[], and result[] ports. + parameter lpm_representation = "SIGNED"; // Type of addition performed + parameter lpm_direction = "UNUSED"; // Specify the operation of the lpm_add_sub function + parameter lpm_pipeline = 0; // Number of Clock cycles of latency + parameter lpm_type = "lpm_add_sub"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] dataa; + input [lpm_width-1:0] datab; + input cin; + input add_sub; + input clock; + input aclr; + input clken; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + output cout; + output overflow; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0]; + reg [(lpm_pipeline+1):0] cout_pipe; + reg [(lpm_pipeline+1):0] overflow_pipe; + reg tmp_cout; + reg tmp_overflow; + reg [lpm_width-1:0] tmp_result; + reg i_cin; + +// LOCAL INTEGER DECLARATION + integer borrow; + integer i; + integer pipe_ptr; + +// INTERNAL TRI DECLARATION + tri1 i_add_sub; + tri0 i_aclr; + tri1 i_clken; + tri0 i_clock; + + +// INITIAL CONSTRUCT BLOCK + initial + begin + // check if lpm_width < 0 + if (lpm_width <= 0) + begin + $display("Error! LPM_WIDTH must be greater than 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if ((lpm_direction != "ADD") && + (lpm_direction != "SUB") && + (lpm_direction != "UNUSED") && // non-LPM 220 standard + (lpm_direction != "DEFAULT")) // non-LPM 220 standard + begin + $display("Error! LPM_DIRECTION value must be \"ADD\" or \"SUB\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if ((lpm_representation != "SIGNED") && + (lpm_representation != "UNSIGNED")) + begin + $display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if (lpm_pipeline < 0) + begin + $display("Error! LPM_PIPELINE must be greater than or equal to 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + for (i = 0; i <= (lpm_pipeline+1); i = i + 1) + begin + result_pipe[i] = 'b0; + cout_pipe[i] = 1'b0; + overflow_pipe[i] = 1'b0; + end + + pipe_ptr = 0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(cin or dataa or datab or i_add_sub) + begin + i_cin = 1'b0; + borrow = 1'b0; + + // cout is the same for both signed and unsign representation. + if ((lpm_direction == "ADD") || ((i_add_sub == 1) && + ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) + begin + i_cin = (cin === 1'bz) ? 0 : cin; + {tmp_cout, tmp_result} = dataa + datab + i_cin; + tmp_overflow = tmp_cout; + end + else if ((lpm_direction == "SUB") || ((i_add_sub == 0) && + ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) + begin + i_cin = (cin === 1'bz) ? 1 : cin; + borrow = (~i_cin) ? 1 : 0; + {tmp_overflow, tmp_result} = dataa - datab - borrow; + tmp_cout = (dataa >= (datab+borrow))?1:0; + end + + if (lpm_representation == "SIGNED") + begin + // perform the addtion or subtraction operation + if ((lpm_direction == "ADD") || ((i_add_sub == 1) && + ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) + begin + tmp_result = dataa + datab + i_cin; + tmp_overflow = ((dataa[lpm_width-1] == datab[lpm_width-1]) && + (dataa[lpm_width-1] != tmp_result[lpm_width-1])) ? + 1 : 0; + end + else if ((lpm_direction == "SUB") || ((i_add_sub == 0) && + ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) + begin + tmp_result = dataa - datab - borrow; + tmp_overflow = ((dataa[lpm_width-1] != datab[lpm_width-1]) && + (dataa[lpm_width-1] != tmp_result[lpm_width-1])) ? + 1 : 0; + end + end + end + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) + begin + for (i = 0; i <= (lpm_pipeline+1); i = i + 1) + begin + result_pipe[i] <= {lpm_width{1'b0}}; + cout_pipe[i] <= 1'b0; + overflow_pipe[i] <= 1'b0; + end + pipe_ptr <= 0; + end + else if (i_clken == 1) + begin + result_pipe[pipe_ptr] <= tmp_result; + cout_pipe[pipe_ptr] <= tmp_cout; + overflow_pipe[pipe_ptr] <= tmp_overflow; + + if (lpm_pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; + end + end + +// CONTINOUS ASSIGNMENT + assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; + assign cout = (lpm_pipeline > 0) ? cout_pipe[pipe_ptr] : tmp_cout; + assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow; + assign i_clock = clock; + assign i_aclr = aclr; + assign i_clken = clken; + assign i_add_sub = add_sub; + +endmodule // lpm_add_sub +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_compare +// +// Description : Parameterized comparator megafunction. The comparator will +// compare between data[] and datab[] and return the status of +// comparation for the following operation. +// 1) dataa[] < datab[]. +// 2) dataa[] == datab[]. +// 3) dataa[] > datab[]. +// 4) dataa[] >= datab[]. +// 5) dataa[] != datab[]. +// 6) dataa[] <= datab[]. +// +// Limitation : n/a +// +// Results expected: Return status bits of the comparision between dataa[] and +// datab[]. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_compare ( + dataa, // Value to be compared to datab[]. (Required) + datab, // Value to be compared to dataa[]. (Required) + clock, // Clock for pipelined usage. + aclr, // Asynchronous clear for pipelined usage. + clken, // Clock enable for pipelined usage. + + // One of the following ports must be present. + alb, // High (1) if dataa[] < datab[]. + aeb, // High (1) if dataa[] == datab[]. + agb, // High (1) if dataa[] > datab[]. + aleb, // High (1) if dataa[] <= datab[]. + aneb, // High (1) if dataa[] != datab[]. + ageb // High (1) if dataa[] >= datab[]. +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the dataa[] and datab[] ports. (Required) + parameter lpm_representation = "UNSIGNED"; // Type of comparison performed: + // "SIGNED", "UNSIGNED" + parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency + // associated with the alb, aeb, agb, ageb, aleb, + // or aneb output. + parameter lpm_type = "lpm_compare"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] dataa; + input [lpm_width-1:0] datab; + input clock; + input aclr; + input clken; + +// OUTPUT PORT DECLARATION + output alb; + output aeb; + output agb; + output aleb; + output aneb; + output ageb; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_pipeline+1:0] alb_pipe; + reg [lpm_pipeline+1:0] aeb_pipe; + reg [lpm_pipeline+1:0] agb_pipe; + reg [lpm_pipeline+1:0] aleb_pipe; + reg [lpm_pipeline+1:0] aneb_pipe; + reg [lpm_pipeline+1:0] ageb_pipe; + reg tmp_alb; + reg tmp_aeb; + reg tmp_agb; + reg tmp_aleb; + reg tmp_aneb; + reg tmp_ageb; + + +// LOCAL INTEGER DECLARATION + integer i; + integer pipe_ptr; + +// INTERNAL TRI DECLARATION + tri0 aclr; + tri0 clock; + tri1 clken; + + wire i_aclr; + wire i_clock; + wire i_clken; + buf (i_aclr, aclr); + buf (i_clock, clock); + buf (i_clken, clken); + +// INITIAL CONSTRUCT BLOCK + initial + begin + if ((lpm_representation != "SIGNED") && + (lpm_representation != "UNSIGNED")) + begin + $display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + pipe_ptr = 0; + end + +// ALWAYS CONSTRUCT BLOCK + // get the status of comparison + always @(dataa or datab) + begin + tmp_aeb = (dataa == datab); + tmp_aneb = (dataa != datab); + + if ((lpm_representation == "SIGNED") && + ((dataa[lpm_width-1] ^ datab[lpm_width-1]) == 1)) + begin + // create latency + tmp_alb = (dataa > datab); + tmp_agb = (dataa < datab); + tmp_aleb = (dataa >= datab); + tmp_ageb = (dataa <= datab); + end + else + begin + // create latency + tmp_alb = (dataa < datab); + tmp_agb = (dataa > datab); + tmp_aleb = (dataa <= datab); + tmp_ageb = (dataa >= datab); + end + end + + // pipelining process + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) // reset all variables + begin + for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) + begin + aeb_pipe[i] <= 1'b0; + agb_pipe[i] <= 1'b0; + alb_pipe[i] <= 1'b0; + aleb_pipe[i] <= 1'b0; + aneb_pipe[i] <= 1'b0; + ageb_pipe[i] <= 1'b0; + end + pipe_ptr <= 0; + end + else if (i_clken == 1) + begin + alb_pipe[pipe_ptr] <= tmp_alb; + aeb_pipe[pipe_ptr] <= tmp_aeb; + agb_pipe[pipe_ptr] <= tmp_agb; + aleb_pipe[pipe_ptr] <= tmp_aleb; + aneb_pipe[pipe_ptr] <= tmp_aneb; + ageb_pipe[pipe_ptr] <= tmp_ageb; + + if (lpm_pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; + end + end + +// CONTINOUS ASSIGNMENT + assign alb = (lpm_pipeline > 0) ? alb_pipe[pipe_ptr] : tmp_alb; + assign aeb = (lpm_pipeline > 0) ? aeb_pipe[pipe_ptr] : tmp_aeb; + assign agb = (lpm_pipeline > 0) ? agb_pipe[pipe_ptr] : tmp_agb; + assign aleb = (lpm_pipeline > 0) ? aleb_pipe[pipe_ptr] : tmp_aleb; + assign aneb = (lpm_pipeline > 0) ? aneb_pipe[pipe_ptr] : tmp_aneb; + assign ageb = (lpm_pipeline > 0) ? ageb_pipe[pipe_ptr] : tmp_ageb; + +endmodule // lpm_compare + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_mult +// +// Description : Parameterized multiplier megafunction. +// +// Limitation : n/a +// +// Results expected: dataa[] * datab[] + sum[]. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_mult ( + dataa, // Multiplicand. (Required) + datab, // Multiplier. (Required) + sum, // Partial sum. + aclr, // Asynchronous clear for pipelined usage. + sclr, // Synchronous clear for pipelined usage. + clock, // Clock for pipelined usage. + clken, // Clock enable for pipelined usage. + result // result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB. +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_widtha = 1; // Width of the dataa[] port. (Required) + parameter lpm_widthb = 1; // Width of the datab[] port. (Required) + parameter lpm_widthp = 1; // Width of the result[] port. (Required) + parameter lpm_widths = 1; // Width of the sum[] port. (Required) + parameter lpm_representation = "UNSIGNED"; // Type of multiplication performed + parameter lpm_pipeline = 0; // Number of clock cycles of latency + parameter lpm_type = "lpm_mult"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_widtha-1:0] dataa; + input [lpm_widthb-1:0] datab; + input [lpm_widths-1:0] sum; + input aclr; + input sclr; + input clock; + input clken; + +// OUTPUT PORT DECLARATION + output [lpm_widthp-1:0] result; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_widthp-1:0] result_pipe [lpm_pipeline+1:0]; + reg [lpm_widthp-1:0] i_prod; + reg [lpm_widthp-1:0] t_p; + reg [lpm_widths-1:0] i_prod_s; + reg [lpm_widths-1:0] t_s; + reg [lpm_widtha+lpm_widthb-1:0] i_prod_ab; + reg [lpm_widtha-1:0] t_a; + reg [lpm_widthb-1:0] t_b; + reg sign_ab; + reg sign_s; + reg [8*5:1] input_a_is_constant; + reg [8*5:1] input_b_is_constant; + reg [8*lpm_widtha:1] input_a_fixed_value; + reg [8*lpm_widthb:1] input_b_fixed_value; + reg [lpm_widtha-1:0] dataa_fixed; + reg [lpm_widthb-1:0] datab_fixed; + + +// LOCAL INTEGER DECLARATION + integer i; + integer pipe_ptr; + +// INTERNAL WIRE DECLARATION + wire [lpm_widtha-1:0] dataa_wire; + wire [lpm_widthb-1:0] datab_wire; + +// INTERNAL TRI DECLARATION + tri0 aclr; + tri0 sclr; + tri0 clock; + tri1 clken; + + wire i_aclr; + wire i_sclr; + wire i_clock; + wire i_clken; + buf (i_aclr, aclr); + buf (i_sclr, sclr); + buf (i_clock, clock); + buf (i_clken, clken); + +// COMPONENT INSTANTIATIONS + LPM_HINT_EVALUATION eva(); + +// FUNCTION DECLARATION + // convert string to binary bits. + function integer str2bin; + input [8*256:1] str; + input str_width; + + reg [8*256:1] reg_str; + reg [255:0] bin; + reg [8:1] tmp; + integer m; + integer str_width; + + begin + reg_str = str; + for (m=0; m < str_width; m=m+1) + begin + tmp = reg_str[8:1]; + reg_str = reg_str >> 8; + + case (tmp) + "0" : bin[m] = 1'b0; + "1" : bin[m] = 1'b1; + default: bin[m] = 1'bx; + endcase + end + str2bin = bin; + end + endfunction + +// INITIAL CONSTRUCT BLOCK + initial + begin + // check if lpm_widtha > 0 + if (lpm_widtha <= 0) + begin + $display("Error! lpm_widtha must be greater than 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check if lpm_widthb > 0 + if (lpm_widthb <= 0) + begin + $display("Error! lpm_widthb must be greater than 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check if lpm_widthp > 0 + if (lpm_widthp <= 0) + begin + $display("Error! lpm_widthp must be greater than 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check if lpm_widthp > 0 + if (lpm_widths <= 0) + begin + $display("Error! lpm_widths must be greater than 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check for valid lpm_rep value + if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED")) + begin + $display("Error! lpm_representation value must be \"SIGNED\" or \"UNSIGNED\".", $time); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + input_a_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_IS_CONSTANT"); + + if (input_a_is_constant == "FIXED") + begin + input_a_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_FIXED_VALUE"); + dataa_fixed = str2bin(input_a_fixed_value, lpm_widtha); + end + + input_b_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_IS_CONSTANT"); + + if (input_b_is_constant == "FIXED") + begin + input_b_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_FIXED_VALUE"); + datab_fixed = str2bin(input_b_fixed_value, lpm_widthb); + end + + pipe_ptr = 0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(dataa_wire or datab_wire or sum) + begin + t_a = dataa_wire; + t_b = datab_wire; + t_s = sum; + sign_ab = 1'b0; + sign_s = 1'b0; + + // if inputs are sign number + if (lpm_representation == "SIGNED") + begin + sign_ab = dataa_wire[lpm_widtha-1] ^ datab_wire[lpm_widthb-1]; + sign_s = sum[lpm_widths-1]; + + // if negative number, represent them as 2 compliment number. + if (dataa_wire[lpm_widtha-1] == 1) + t_a = (~dataa_wire) + 1; + if (datab_wire[lpm_widthb-1] == 1) + t_b = (~datab_wire) + 1; + if (sum[lpm_widths-1] == 1) + t_s = (~sum) + 1; + end + + // if sum port is not used + if (sum === {lpm_widths{1'bz}}) + begin + t_s = {lpm_widths{1'b0}}; + sign_s = 1'b0; + end + + if (sign_ab == sign_s) + begin + i_prod = (t_a * t_b) + t_s; + i_prod_s = (t_a * t_b) + t_s; + i_prod_ab = (t_a * t_b) + t_s; + end + else + begin + i_prod = (t_a * t_b) - t_s; + i_prod_s = (t_a * t_b) - t_s; + i_prod_ab = (t_a * t_b) - t_s; + end + + // if dataa[] * datab[] produces negative number, compliment the result + if (sign_ab) + begin + i_prod = (~i_prod) + 1; + i_prod_s = (~i_prod_s) + 1; + i_prod_ab = (~i_prod_ab) + 1; + end + + if ((lpm_widthp < lpm_widths) || (lpm_widthp < (lpm_widtha+lpm_widthb))) + for (i = 0; i < lpm_widthp; i = i + 1) + i_prod[lpm_widthp-1-i] = (lpm_widths > lpm_widtha+lpm_widthb) + ? i_prod_s[lpm_widths-1-i] + : i_prod_ab[lpm_widtha+lpm_widthb-1-i]; + + end + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) // clear the pipeline for result to 0 + begin + for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) + result_pipe[i] <= {lpm_widthp{1'b0}}; + + pipe_ptr <= 0; + end + else if (i_clken == 1) + begin + if(i_sclr) + begin + for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) + result_pipe[i] <= {lpm_widthp{1'b0}}; + + pipe_ptr <= 0; + end + else + begin + result_pipe[pipe_ptr] <= i_prod; + + if (lpm_pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; + end + end + end + +// CONTINOUS ASSIGNMENT + assign dataa_wire = (input_a_is_constant == "FIXED") ? dataa_fixed : dataa; + assign datab_wire = (input_b_is_constant == "FIXED") ? datab_fixed : datab; + assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : i_prod; + +endmodule // lpm_mult +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_divide +// +// Description : Parameterized divider megafunction. This function performs a +// divide operation such that denom * quotient + remain = numer +// The function allows for all combinations of signed(two's +// complement) and unsigned inputs. If any of the inputs is +// signed, the output is signed. Otherwise the output is unsigned. +// The function also allows the remainder to be specified as +// always positive (in which case remain >= 0); otherwise remain +// is zero or the same sign as the numerator +// (this parameter is ignored in the case of purely unsigned +// division). Finally the function is also pipelinable. +// +// Limitation : n/a +// +// Results expected: Return quotient and remainder. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_divide ( + numer, // The numerator (Required) + denom, // The denominator (Required) + clock, // Clock input for pipelined usage + aclr, // Asynchronous clear signal + clken, // Clock enable for pipelined usage. + quotient, // Quotient (Required) + remain // Remainder (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_widthn = 1; // Width of the numer[] and quotient[] port. (Required) + parameter lpm_widthd = 1; // Width of the denom[] and remain[] port. (Required) + parameter lpm_nrepresentation = "UNSIGNED"; // The representation of numer + parameter lpm_drepresentation = "UNSIGNED"; // The representation of denom + parameter lpm_pipeline = 0; // Number of Clock cycles of latency + parameter lpm_type = "lpm_divide"; + parameter lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE"; + +// INPUT PORT DECLARATION + input [lpm_widthn-1:0] numer; + input [lpm_widthd-1:0] denom; + input clock; + input aclr; + input clken; + +// OUTPUT PORT DECLARATION + output [lpm_widthn-1:0] quotient; + output [lpm_widthd-1:0] remain; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_widthn-1:0] quotient_pipe [lpm_pipeline+1:0]; + reg [lpm_widthd-1:0] remain_pipe [lpm_pipeline+1:0]; + reg [lpm_widthn-1:0] tmp_quotient; + reg [lpm_widthd-1:0] tmp_remain; + reg [lpm_widthn-1:0] not_numer; + reg [lpm_widthn-1:0] int_numer; + reg [lpm_widthd-1:0] not_denom; + reg [lpm_widthd-1:0] int_denom; + reg [lpm_widthn-1:0] t_numer; + reg [lpm_widthn-1:0] t_q; + reg [lpm_widthd-1:0] t_denom; + reg [lpm_widthd-1:0] t_r; + reg sign_q; + reg sign_r; + reg sign_n; + reg sign_d; + reg [8*5:1] lpm_remainderpositive; + + +// LOCAL INTEGER DECLARATION + integer i; + integer rsig; + integer pipe_ptr; + +// INTERNAL TRI DECLARATION + tri0 aclr; + tri0 clock; + tri1 clken; + + wire i_aclr; + wire i_clock; + wire i_clken; + buf (i_aclr, aclr); + buf (i_clock, clock); + buf (i_clken, clken); + +// COMPONENT INSTANTIATIONS + LPM_HINT_EVALUATION eva(); + +// INITIAL CONSTRUCT BLOCK + initial + begin + // check if lpm_widthn > 0 + if (lpm_widthn <= 0) + begin + $display("Error! LPM_WIDTHN must be greater than 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check if lpm_widthd > 0 + if (lpm_widthd <= 0) + begin + $display("Error! LPM_WIDTHD must be greater than 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check for valid lpm_nrepresentation value + if ((lpm_nrepresentation != "SIGNED") && (lpm_nrepresentation != "UNSIGNED")) + begin + $display("Error! LPM_NREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check for valid lpm_drepresentation value + if ((lpm_drepresentation != "SIGNED") && (lpm_drepresentation != "UNSIGNED")) + begin + $display("Error! LPM_DREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check for valid lpm_remainderpositive value + lpm_remainderpositive = eva.GET_PARAMETER_VALUE(lpm_hint, "LPM_REMAINDERPOSITIVE"); + if ((lpm_remainderpositive == "TRUE") && + (lpm_remainderpositive == "FALSE")) + begin + $display("Error! LPM_REMAINDERPOSITIVE value must be \"TRUE\" or \"FALSE\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + for (i = 0; i <= (lpm_pipeline+1); i = i + 1) + begin + quotient_pipe[i] <= {lpm_widthn{1'b0}}; + remain_pipe[i] <= {lpm_widthd{1'b0}}; + end + + pipe_ptr = 0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(numer or denom or lpm_remainderpositive) + begin + sign_q = 1'b0; + sign_r = 1'b0; + sign_n = 1'b0; + sign_d = 1'b0; + t_numer = numer; + t_denom = denom; + + if (lpm_nrepresentation == "SIGNED") + if (numer[lpm_widthn-1] == 1'b1) + begin + t_numer = ~numer + 1; // numer is negative number + sign_n = 1'b1; + end + + if (lpm_drepresentation == "SIGNED") + if (denom[lpm_widthd-1] == 1'b1) + begin + t_denom = ~denom + 1; // denom is negative numbrt + sign_d = 1'b1; + end + + t_q = t_numer / t_denom; // get quotient + t_r = t_numer % t_denom; // get remainder + sign_q = sign_n ^ sign_d; + sign_r = (t_r != {lpm_widthd{1'b0}}) ? sign_n : 1'b0; + + // Pipeline the result + tmp_quotient = (sign_q == 1'b1) ? (~t_q + 1) : t_q; + tmp_remain = (sign_r == 1'b1) ? (~t_r + 1) : t_r; + + // Recalculate the quotient and remainder if remainder is negative number + // and LPM_REMAINDERPOSITIVE=TRUE. + if ((sign_r) && (lpm_remainderpositive == "TRUE")) + begin + tmp_quotient = tmp_quotient + ((sign_d == 1'b1) ? 1 : -1 ); + tmp_remain = tmp_remain + t_denom; + end + end + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) + begin + for (i = 0; i <= (lpm_pipeline+1); i = i + 1) + begin + quotient_pipe[i] <= {lpm_widthn{1'b0}}; + remain_pipe[i] <= {lpm_widthd{1'b0}}; + end + pipe_ptr <= 0; + end + else if (i_clken) + begin + quotient_pipe[pipe_ptr] <= tmp_quotient; + remain_pipe[pipe_ptr] <= tmp_remain; + + if (lpm_pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; + end + end + +// CONTINOUS ASSIGNMENT + assign quotient = (lpm_pipeline > 0) ? quotient_pipe[pipe_ptr] : tmp_quotient; + assign remain = (lpm_pipeline > 0) ? remain_pipe[pipe_ptr] : tmp_remain; + +endmodule // lpm_divide +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_abs +// +// Description : Parameterized absolute value megafunction. This megafunction +// requires the input data to be signed number. +// +// Limitation : n/a +// +// Results expected: Return absolute value of data and the overflow status +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_abs ( + data, // Signed number (Required) + result, // Absolute value of data[]. + overflow // High if data = -2 ^ (LPM_WIDTH-1). +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[] and result[] ports.(Required) + parameter lpm_type = "lpm_abs"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + output overflow; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] result_tmp; + reg overflow; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(data) + begin + result_tmp = (data[lpm_width-1] == 1) ? (~data) + 1 : data; + overflow = (data[lpm_width-1] == 1) ? (result_tmp == (1<<(lpm_width-1))) : 0; + end + +// CONTINOUS ASSIGNMENT + assign result = result_tmp; + +endmodule // lpm_abs + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_counter +// +// Description : Parameterized counter megafunction. The lpm_counter +// megafunction is a binary counter that features an up, +// down, or up/down counter with optional synchronous or +// asynchronous clear, set, and load ports. +// +// Limitation : n/a +// +// Results expected: Data output from the counter and carry-out of the MSB. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_counter ( + clock, // Positive-edge-triggered clock. (Required) + clk_en, // Clock enable input. Enables all synchronous activities. + cnt_en, // Count enable input. Disables the count when low (0) without + // affecting sload, sset, or sclr. + updown, // Controls the direction of the count. High (1) = count up. + // Low (0) = count down. + aclr, // Asynchronous clear input. + aset, // Asynchronous set input. + aload, // Asynchronous load input. Asynchronously loads the counter with + // the value on the data input. + sclr, // Synchronous clear input. Clears the counter on the next active + // clock edge. + sset, // Synchronous set input. Sets the counter on the next active clock edge. + sload, // Synchronous load input. Loads the counter with data[] on the next + // active clock edge. + data, // Parallel data input to the counter. + cin, // Carry-in to the low-order bit. + q, // Data output from the counter. + cout, // Carry-out of the MSB. + eq // Counter decode output. Active high when the counter reaches the specified + // count value. +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; //The number of bits in the count, or the width of the q[] + // and data[] ports, if they are used. (Required) + parameter lpm_direction = "UNUSED"; // Direction of the count. + parameter lpm_modulus = 0; // The maximum count, plus one. + parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. + parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge + // of clock when sset is high. + parameter lpm_pvalue = "UNUSED"; + parameter lpm_port_updown = "PORT_CONNECTIVITY"; + parameter lpm_type = "lpm_counter"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input clock; + input clk_en; + input cnt_en; + input updown; + input aclr; + input aset; + input aload; + input sclr; + input sset; + input sload; + input [lpm_width-1:0] data; + input cin; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + output cout; + output [15:0] eq; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] tmp_count; + reg [lpm_width-1:0] adata; + + reg use_adata; + reg tmp_updown; + reg [lpm_width:0] tmp_modulus; + reg [lpm_width:0] max_modulus; + reg [lpm_width-1:0] svalue; + reg [lpm_width-1:0] avalue; + reg [lpm_width-1:0] pvalue; + +// INTERNAL WIRE DECLARATION + wire w_updown; + wire [lpm_width-1:0] final_count; + +// LOCAL INTEGER DECLARATION + integer i; + +// INTERNAL TRI DECLARATION + + tri1 clk_en; + tri1 cnt_en; + tri0 aclr; + tri0 aset; + tri0 aload; + tri0 sclr; + tri0 sset; + tri0 sload; + tri1 cin; + tri1 updown_z; + + wire i_clk_en; + wire i_cnt_en; + wire i_aclr; + wire i_aset; + wire i_aload; + wire i_sclr; + wire i_sset; + wire i_sload; + wire i_cin; + wire i_updown; + buf (i_clk_en, clk_en); + buf (i_cnt_en, cnt_en); + buf (i_aclr, aclr); + buf (i_aset, aset); + buf (i_aload, aload); + buf (i_sclr, sclr); + buf (i_sset, sset); + buf (i_sload, sload); + buf (i_cin, cin); + buf (i_updown, updown_z); + +// TASK DECLARATION + task string_to_reg; + input [8*40:1] string_value; + output [lpm_width-1:0] value; + + reg [8*40:1] reg_s; + reg [8:1] digit; + reg [8:1] tmp; + reg [lpm_width-1:0] ivalue; + + integer m; + + begin + ivalue = {lpm_width{1'b0}}; + reg_s = string_value; + for (m=1; m<=40; m=m+1) + begin + tmp = reg_s[320:313]; + digit = tmp & 8'b00001111; + reg_s = reg_s << 8; + ivalue = ivalue * 10 + digit; + end + value = ivalue; + end + endtask + +// INITIAL CONSTRUCT BLOCK + initial + begin + max_modulus = 1 << lpm_width; + + // check if lpm_width < 0 + if (lpm_width <= 0) + begin + $display("Error! LPM_WIDTH must be greater than 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + // check if lpm_modulus < 0 + if (lpm_modulus < 0) + begin + $display("Error! LPM_MODULUS must be greater or equal to 0.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + // check if lpm_modulus > 1<<lpm_width + if (lpm_modulus > max_modulus) + begin + $display("Warning! LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input.\n"); + $display ("Time: %0t Instance: %m", $time); + end + // check if lpm_direction valid + if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && + (lpm_direction != "UP") && (lpm_direction != "DOWN")) + begin + $display("Error! LPM_DIRECTION must be \"UP\" or \"DOWN\" if used.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_avalue == "UNUSED") + avalue = {lpm_width{1'b1}}; + else + string_to_reg(lpm_avalue, avalue); + + if (lpm_svalue == "UNUSED") + svalue = {lpm_width{1'b1}}; + else + string_to_reg(lpm_svalue, svalue); + + if (lpm_pvalue == "UNUSED") + pvalue = {lpm_width{1'b0}}; + else + string_to_reg(lpm_pvalue, pvalue); + + tmp_modulus = ((lpm_modulus == 0) || (lpm_modulus > max_modulus)) + ? max_modulus : lpm_modulus; + tmp_count = pvalue; + use_adata = 1'b0; + end + + // NCSIM will only assigns 1'bZ to unconnected port at time 0fs + 1 + // verilator lint_off STMTDLY + initial #0 + // verilator lint_on STMTDLY + begin + // // check if lpm_direction valid + if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && (updown !== 1'bz) && + (lpm_port_updown == "PORT_CONNECTIVITY")) + begin + $display("Error! LPM_DIRECTION and UPDOWN cannot be used at the same time.\n"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock) + begin + if (i_aclr || i_aset || i_aload) + use_adata <= 1'b1; + else if ($time > 0) + begin + if (i_clk_en) + begin + use_adata <= 1'b0; + + if (i_sclr) + tmp_count <= 0; + else if (i_sset) + tmp_count <= svalue; + else if (i_sload) + tmp_count <= data; + else if (i_cnt_en && i_cin) + begin + if (w_updown) + tmp_count <= (final_count == tmp_modulus-1) ? 0 + : final_count+1; + else + tmp_count <= (final_count == 0) ? tmp_modulus-1 + : final_count-1; + end + else + tmp_count <= final_count; + end + end + end + + always @(i_aclr or i_aset or i_aload or data or avalue) + begin + if (i_aclr) + begin + adata <= 0; + end + else if (i_aset) + begin + adata <= avalue; + end + else if (i_aload) + adata <= data; + end + +// CONTINOUS ASSIGNMENT + assign q = final_count; + assign final_count = (use_adata == 1'b1) ? adata : tmp_count; + assign cout = (i_cin && (((w_updown==0) && (final_count==0)) || + ((w_updown==1) && ((final_count==tmp_modulus-1) || + (final_count=={lpm_width{1'b1}}))) )) + ? 1'b1 : 1'b0; + assign updown_z = updown; + assign w_updown = (lpm_port_updown == "PORT_USED") ? i_updown : + (lpm_port_updown == "PORT_UNUSED") ? ((lpm_direction == "DOWN") ? 1'b0 : 1'b1) : + ((((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) && (i_updown == 1)) || + (lpm_direction == "UP")) + ? 1'b1 : 1'b0; + assign eq = {16{1'b0}}; + +endmodule // lpm_counter +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_latch +// +// Description : Parameterized latch megafunction. +// +// Limitation : n/a +// +// Results expected: Data output from the latch. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_latch ( + data, // Data input to the latch. + gate, // Latch enable input. High = flow-through, low = latch. (Required) + aclr, // Asynchronous clear input. + aset, // Asynchronous set input. + aconst, + q // Data output from the latch. +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) + parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. + parameter lpm_pvalue = "UNUSED"; + parameter lpm_type = "lpm_latch"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input gate; + input aclr; + input aset; + input aconst; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] q; + reg [lpm_width-1:0] avalue; + reg [lpm_width-1:0] pvalue; + + +// INTERNAL TRI DECLARATION + tri0 [lpm_width-1:0] data; + tri0 aclr; + tri0 aset; + tri0 aconst; + + wire i_aclr; + wire i_aset; + buf (i_aclr, aclr); + buf (i_aset, aset); + +// TASK DECLARATION + task string_to_reg; + input [8*40:1] string_value; + output [lpm_width-1:0] value; + + reg [8*40:1] reg_s; + reg [8:1] digit; + reg [8:1] tmp; + reg [lpm_width-1:0] ivalue; + + integer m; + + begin + ivalue = {lpm_width{1'b0}}; + reg_s = string_value; + for (m=1; m<=40; m=m+1) + begin + tmp = reg_s[320:313]; + digit = tmp & 8'b00001111; + reg_s = reg_s << 8; + ivalue = ivalue * 10 + digit; + end + value = ivalue; + end + endtask + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_pvalue != "UNUSED") + begin + string_to_reg(lpm_pvalue, pvalue); + q = pvalue; + end + + if (lpm_avalue == "UNUSED") + avalue = {lpm_width{1'b1}}; + else + string_to_reg(lpm_avalue, avalue); + end + +// ALWAYS CONSTRUCT BLOCK + always @(data or gate or i_aclr or i_aset or avalue) + begin + if (i_aclr) + q <= {lpm_width{1'b0}}; + else if (i_aset) + q <= avalue; + else if (gate) + q <= data; + end + +endmodule // lpm_latch + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_ff +// +// Description : Parameterized flipflop megafunction. The lpm_ff function +// contains features that are not available in the DFF, DFFE, +// DFFEA, TFF, and TFFE primitives, such as synchronous or +// asynchronous set, clear, and load inputs. + +// +// Limitation : n/a +// +// Results expected: Data output from D or T flipflops. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_ff ( + data, // T-type flipflop: Toggle enable + // D-type flipflop: Data input + + clock, // Positive-edge-triggered clock. (Required) + enable, // Clock enable input. + aclr, // Asynchronous clear input. + aset, // Asynchronous set input. + + aload, // Asynchronous load input. Asynchronously loads the flipflop with + // the value on the data input. + + sclr, // Synchronous clear input. + sset, // Synchronous set input. + + sload, // Synchronous load input. Loads the flipflop with the value on the + // data input on the next active clock edge. + + q // Data output from D or T flipflops. (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) + parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. + parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge + // of clock when sset is high. + parameter lpm_pvalue = "UNUSED"; + parameter lpm_fftype = "DFF"; // Type of flipflop + parameter lpm_type = "lpm_ff"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input clock; + input enable; + input aclr; + input aset; + input aload; + input sclr; + input sset; + input sload ; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] tmp_q; + reg [lpm_width-1:0] adata; + reg use_adata; + reg [lpm_width-1:0] svalue; + reg [lpm_width-1:0] avalue; + reg [lpm_width-1:0] pvalue; + +// INTERNAL WIRE DECLARATION + wire [lpm_width-1:0] final_q; + +// LOCAL INTEGER DECLARATION + integer i; + +// INTERNAL TRI DECLARATION + tri1 [lpm_width-1:0] data; + tri1 enable; + tri0 sload; + tri0 sclr; + tri0 sset; + tri0 aload; + tri0 aclr; + tri0 aset; + + wire i_enable; + wire i_sload; + wire i_sclr; + wire i_sset; + wire i_aload; + wire i_aclr; + wire i_aset; + buf (i_enable, enable); + buf (i_sload, sload); + buf (i_sclr, sclr); + buf (i_sset, sset); + buf (i_aload, aload); + buf (i_aclr, aclr); + buf (i_aset, aset); + +// TASK DECLARATION + task string_to_reg; + input [8*40:1] string_value; + output [lpm_width-1:0] value; + + reg [8*40:1] reg_s; + reg [8:1] digit; + reg [8:1] tmp; + reg [lpm_width-1:0] ivalue; + + integer m; + + begin + ivalue = {lpm_width{1'b0}}; + reg_s = string_value; + for (m=1; m<=40; m=m+1) + begin + tmp = reg_s[320:313]; + digit = tmp & 8'b00001111; + reg_s = reg_s << 8; + ivalue = ivalue * 10 + digit; + end + value = ivalue; + end + endtask + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_fftype != "DFF") && + (lpm_fftype != "TFF") && + (lpm_fftype != "UNUSED")) // non-LPM 220 standard + begin + $display("Error! LPM_FFTYPE value must be \"DFF\" or \"TFF\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_avalue == "UNUSED") + avalue = {lpm_width{1'b1}}; + else + string_to_reg(lpm_avalue, avalue); + + if (lpm_svalue == "UNUSED") + svalue = {lpm_width{1'b1}}; + else + string_to_reg(lpm_svalue, svalue); + + if (lpm_pvalue == "UNUSED") + pvalue = {lpm_width{1'b0}}; + else + string_to_reg(lpm_pvalue, pvalue); + + tmp_q = pvalue; + use_adata = 1'b0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock) + begin // Asynchronous process + if (i_aclr || i_aset || i_aload) + use_adata <= 1'b1; + else if ($time > 0) + begin // Synchronous process + if (i_enable) + begin + use_adata <= 1'b0; + + if (i_sclr) + tmp_q <= 0; + else if (i_sset) + tmp_q <= svalue; + else if (i_sload) // Load data + tmp_q <= data; + else + begin + if (lpm_fftype == "TFF") // toggle + begin + for (i = 0; i < lpm_width; i=i+1) + if (data[i] == 1'b1) + tmp_q[i] <= ~final_q[i]; + else + tmp_q[i] <= final_q[i]; + end + else // DFF, load data + tmp_q <= data; + end + end + end + end + + always @(i_aclr or i_aset or i_aload or data or avalue or pvalue) + begin + if (i_aclr === 1'b1) + adata <= {lpm_width{1'b0}}; + else if (i_aclr === 1'bx) + adata <= {lpm_width{1'bx}}; + else if (i_aset) + adata <= avalue; + else if (i_aload) + adata <= data; + else if ((i_aclr === 1'b0) && ($time == 0)) + adata <= pvalue; + end + +// CONTINOUS ASSIGNMENT + assign q = final_q; + assign final_q = (use_adata == 1'b1) ? adata : tmp_q; + +endmodule // lpm_ff +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_shiftreg +// +// Description : Parameterized shift register megafunction. +// +// Limitation : n/a +// +// Results expected: Data output from the shift register and the Serial shift data output. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_shiftreg ( + data, // Data input to the shift register. + clock, // Positive-edge-triggered clock. (Required) + enable, // Clock enable input + shiftin, // Serial shift data input. + load, // Synchronous parallel load. High (1): load operation; + // low (0): shift operation. + aclr, // Asynchronous clear input. + aset, // Asynchronous set input. + sclr, // Synchronous clear input. + sset, // Synchronous set input. + q, // Data output from the shift register. + shiftout // Serial shift data output. +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[] and q ports. (Required) + parameter lpm_direction = "LEFT"; // Values are "LEFT", "RIGHT", and "UNUSED". + parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. + parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge + // of clock when sset is high. + parameter lpm_pvalue = "UNUSED"; + parameter lpm_type = "lpm_shiftreg"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input clock; + input enable; + input shiftin; + input load; + input aclr; + input aset; + input sclr; + input sset; + + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + output shiftout; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] tmp_q; + reg abit; + reg [lpm_width-1:0] svalue; + reg [lpm_width-1:0] avalue; + reg [lpm_width-1:0] pvalue; + +// LOCAL INTEGER DECLARATION + integer i; + +// INTERNAL WIRE DECLARATION + wire tmp_shiftout; + +// INTERNAL TRI DECLARATION + tri1 enable; + tri1 shiftin; + tri0 load; + tri0 aclr; + tri0 aset; + tri0 sclr; + tri0 sset; + + wire i_enable; + wire i_shiftin; + wire i_load; + wire i_aclr; + wire i_aset; + wire i_sclr; + wire i_sset; + buf (i_enable, enable); + buf (i_shiftin, shiftin); + buf (i_load, load); + buf (i_aclr, aclr); + buf (i_aset, aset); + buf (i_sclr, sclr); + buf (i_sset, sset); + +// TASK DECLARATION + task string_to_reg; + input [8*40:1] string_value; + output [lpm_width-1:0] value; + + reg [8*40:1] reg_s; + reg [8:1] digit; + reg [8:1] tmp; + reg [lpm_width-1:0] ivalue; + + integer m; + + begin + ivalue = {lpm_width{1'b0}}; + reg_s = string_value; + for (m=1; m<=40; m=m+1) + begin + tmp = reg_s[320:313]; + digit = tmp & 8'b00001111; + reg_s = reg_s << 8; + ivalue = ivalue * 10 + digit; + end + value = ivalue; + end + endtask + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_direction != "LEFT") && + (lpm_direction != "RIGHT") && + (lpm_direction != "UNUSED")) // non-LPM 220 standard + begin + $display("Error! LPM_DIRECTION value must be \"LEFT\" or \"RIGHT\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_avalue == "UNUSED") + avalue = {lpm_width{1'b1}}; + else + string_to_reg(lpm_avalue, avalue); + + if (lpm_svalue == "UNUSED") + svalue = {lpm_width{1'b1}}; + else + string_to_reg(lpm_svalue, svalue); + + if (lpm_pvalue == "UNUSED") + pvalue = {lpm_width{1'b0}}; + else + string_to_reg(lpm_pvalue, pvalue); + + tmp_q = pvalue; + end + +// ALWAYS CONSTRUCT BLOCK + always @(i_aclr or i_aset or avalue) + begin + if (i_aclr) + tmp_q <= {lpm_width{1'b0}}; + else if (i_aset) + tmp_q <= avalue; + end + + always @(posedge clock) + begin + if (i_aclr) + tmp_q <= (i_aset) ? {lpm_width{1'bx}} : {lpm_width{1'b0}}; + else if (i_aset) + tmp_q <= avalue; + else + begin + if (i_enable) + begin + if (i_sclr) + tmp_q <= {lpm_width{1'b0}}; + else if (i_sset) + tmp_q <= svalue; + else if (i_load) + tmp_q <= data; + else if (!i_load) + begin + if ((lpm_direction == "LEFT") || (lpm_direction == "UNUSED")) + {abit,tmp_q} <= {tmp_q,i_shiftin}; + else if (lpm_direction == "RIGHT") + {tmp_q,abit} <= {i_shiftin,tmp_q}; + end + end + end + end + +// CONTINOUS ASSIGNMENT + assign tmp_shiftout = (lpm_direction == "RIGHT") ? tmp_q[0] + : tmp_q[lpm_width-1]; + assign q = tmp_q; + assign shiftout = tmp_shiftout; + +endmodule // lpm_shiftreg +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_ram_dq +// +// Description : Parameterized RAM with separate input and output ports megafunction. +// lpm_ram_dq implement asynchronous memory or memory with synchronous +// inputs and/or outputs. +// +// Limitation : n/a +// +// Results expected: Data output from the memory. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_ram_dq ( + data, // Data input to the memory. (Required) + address, // Address input to the memory. (Required) + inclock, // Synchronizes memory loading. + outclock, // Synchronizes q outputs from memory. + we, // Write enable input. Enables write operations to the memory when high. (Required) + q // Data output from the memory. (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of data[] and q[] ports. (Required) + parameter lpm_widthad = 1; // Width of the address port. (Required) + parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory. + parameter lpm_indata = "REGISTERED"; // Controls whether the data port is registered. + parameter lpm_address_control = "REGISTERED"; // Controls whether the address and we ports are registered. + parameter lpm_outdata = "REGISTERED"; // Controls whether the q ports are registered. + parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data. + parameter use_eab = "ON"; // Specified whether to use the EAB or not. + parameter intended_device_family = "Stratix"; + parameter lpm_type = "lpm_ram_dq"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input [lpm_widthad-1:0] address; + input inclock; + input outclock; + input we; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] mem_data [lpm_numwords-1:0]; + reg [lpm_width-1:0] tmp_q; + reg [lpm_width-1:0] pdata; + reg [lpm_width-1:0] in_data; + reg [lpm_widthad-1:0] paddress; + reg pwe; + reg [lpm_width-1:0] ZEROS, ONES, UNKNOWN; +`ifdef VERILATOR + reg [`LPM_MAX_NAME_SZ*8:1] ram_initf; +`else + reg [8*256:1] ram_initf; +`endif + +// LOCAL INTEGER DECLARATION + integer i; + +// INTERNAL TRI DECLARATION + tri0 inclock; + tri0 outclock; + + wire i_inclock; + wire i_outclock; + buf (i_inclock, inclock); + buf (i_outclock, outclock); + +// COMPONENT INSTANTIATIONS + LPM_DEVICE_FAMILIES dev (); + LPM_MEMORY_INITIALIZATION mem (); + +// FUNCTON DECLARATION + // Check the validity of the address. + function ValidAddress; + input [lpm_widthad-1:0] paddress; + + begin + ValidAddress = 1'b0; + if (^paddress === {lpm_widthad{1'bx}}) + begin + $display("%t:Error! Invalid address.\n", $time); + $display("Time: %0t Instance: %m", $time); + end + else if (paddress >= lpm_numwords) + begin + $display("%t:Error! Address out of bound on RAM.\n", $time); + $display("Time: %0t Instance: %m", $time); + end + else + ValidAddress = 1'b1; + end + endfunction + +// INITIAL CONSTRUCT BLOCK + initial + begin + + // Initialize the internal data register. + pdata = {lpm_width{1'b0}}; + paddress = {lpm_widthad{1'b0}}; + pwe = 1'b0; + + if (lpm_width <= 0) + begin + $display("Error! LPM_WIDTH parameter must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_widthad <= 0) + begin + $display("Error! LPM_WIDTHAD parameter must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + // check for number of words out of bound + if ((lpm_numwords > (1 << lpm_widthad)) || + (lpm_numwords <= (1 << (lpm_widthad-1)))) + begin + $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED")) + begin + $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) + begin + $display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) + begin + $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + for (i=0; i < lpm_width; i=i+1) + begin + ZEROS[i] = 1'b0; + ONES[i] = 1'b1; + UNKNOWN[i] = 1'bX; + end + + for (i = 0; i < lpm_numwords; i=i+1) + mem_data[i] = {lpm_width{1'b0}}; + + // load data to the RAM + if (lpm_file != "UNUSED") + begin + mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf); + $readmemh(ram_initf, mem_data); + end + + tmp_q = ZEROS; + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge i_inclock) + begin + if (lpm_address_control == "REGISTERED") + begin + if ((we) && (use_eab != "ON") && + (lpm_hint != "USE_EAB=ON")) + begin + if (lpm_indata == "REGISTERED") + mem_data[address] <= data; + else + mem_data[address] <= pdata; + end + paddress <= address; + pwe <= we; + end + if (lpm_indata == "REGISTERED") + pdata <= data; + end + + always @(data) + begin + if (lpm_indata == "UNREGISTERED") + pdata <= data; + end + + always @(address) + begin + if (lpm_address_control == "UNREGISTERED") + paddress <= address; + end + + always @(we) + begin + if (lpm_address_control == "UNREGISTERED") + pwe <= we; + end + + always @(pdata or paddress or pwe) + begin :UNREGISTERED_INCLOCK + if (ValidAddress(paddress)) + begin + if ((lpm_address_control == "UNREGISTERED") && (pwe)) + mem_data[paddress] <= pdata; + end + else + begin + if (lpm_outdata == "UNREGISTERED") + tmp_q <= {lpm_width{1'bx}}; + end + end + + always @(posedge i_outclock) + begin + if (lpm_outdata == "REGISTERED") + begin + if (ValidAddress(paddress)) + tmp_q <= mem_data[paddress]; + else + tmp_q <= {lpm_width{1'bx}}; + end + end + + always @(i_inclock or pwe or paddress or pdata) + begin + if ((lpm_address_control == "REGISTERED") && (pwe)) + if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) + begin + if (i_inclock == 1'b0) + mem_data[paddress] = pdata; + end + end + +// CONTINOUS ASSIGNMENT + assign q = (lpm_outdata == "UNREGISTERED") ? mem_data[paddress] : tmp_q; + +endmodule // lpm_ram_dq +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_ram_dp +// +// Description : Parameterized dual-port RAM megafunction. +// +// Limitation : n/a +// +// Results expected: Data output from the memory. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_ram_dp ( + data, // Data input to the memory. (Required) + rdaddress, // Read address input to the memory. (Required) + wraddress, // Write address input to the memory. (Required) + rdclock, // Positive-edge-triggered clock for read operation. + rdclken, // Clock enable for rdclock. + wrclock, // Positive-edge-triggered clock for write operation. + wrclken, // Clock enable for wrclock. + rden, // Read enable input. Disables reading when low (0). + wren, // Write enable input. (Required) + q // Data output from the memory. (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) + parameter lpm_widthad = 1; // Width of the rdaddress[] and wraddress[] ports. (Required) + parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory. + parameter lpm_indata = "REGISTERED"; // Determines the clock used by the data port. + parameter lpm_rdaddress_control = "REGISTERED"; // Determines the clock used by the rdaddress and rden ports. + parameter lpm_wraddress_control = "REGISTERED"; // Determines the clock used by the wraddress and wren ports. + parameter lpm_outdata = "REGISTERED"; // Determines the clock used by the q[] pxort. + parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data. + parameter use_eab = "ON"; // Specified whether to use the EAB or not. + parameter rden_used = "TRUE"; // Specified whether to use the rden port or not. + parameter intended_device_family = "Stratix"; + parameter lpm_type = "lpm_ram_dp"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input [lpm_widthad-1:0] rdaddress; + input [lpm_widthad-1:0] wraddress; + input rdclock; + input rdclken; + input wrclock; + input wrclken; + input rden; + input wren; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] mem_data [(1<<lpm_widthad)-1:0]; + reg [lpm_width-1:0] i_data_reg, i_data_tmp, i_q_reg, i_q_tmp; + reg [lpm_widthad-1:0] i_wraddress_reg, i_wraddress_tmp; + reg [lpm_widthad-1:0] i_rdaddress_reg, i_rdaddress_tmp; + reg i_wren_reg, i_wren_tmp, i_rden_reg, i_rden_tmp; +`ifdef VERILATOR + reg [`LPM_MAX_NAME_SZ*8:1] ram_initf; +`else + reg [8*256:1] ram_initf; +`endif + +// LOCAL INTEGER DECLARATION + integer i, i_numwords; + +// INTERNAL TRI DECLARATION + tri0 wrclock; + tri1 wrclken; + tri0 rdclock; + tri1 rdclken; + tri0 wren; + tri1 rden; + + wire i_inclock; + wire i_inclocken; + wire i_outclock; + wire i_outclocken; + wire i_wren; + wire i_rden; + + buf (i_inclock, wrclock); + buf (i_inclocken, wrclken); + buf (i_outclock, rdclock); + buf (i_outclocken, rdclken); + buf (i_wren, wren); + buf (i_rden, rden); + +// COMPONENT INSTANTIATIONS + LPM_DEVICE_FAMILIES dev (); + LPM_MEMORY_INITIALIZATION mem (); + +// FUNCTON DECLARATION + function ValidAddress; + input [lpm_widthad-1:0] paddress; + + begin + ValidAddress = 1'b0; + if (^paddress === {lpm_widthad{1'bx}}) + begin + $display("%t:Error! Invalid address.\n", $time); + $display("Time: %0t Instance: %m", $time); + end + else if (paddress >= lpm_numwords) + begin + $display("%t:Error! Address out of bound on RAM.\n", $time); + $display("Time: %0t Instance: %m", $time); + end + else + ValidAddress = 1'b1; + end + endfunction + +// INITIAL CONSTRUCT BLOCK + initial + begin + // Check for invalid parameters + if (lpm_width < 1) + begin + $display("Error! lpm_width parameter must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if (lpm_widthad < 1) + begin + $display("Error! lpm_widthad parameter must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) + begin + $display("Error! lpm_indata must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) + begin + $display("Error! lpm_outdata must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if ((lpm_wraddress_control != "REGISTERED") && (lpm_wraddress_control != "UNREGISTERED")) + begin + $display("Error! lpm_wraddress_control must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + end + if ((lpm_rdaddress_control != "REGISTERED") && (lpm_rdaddress_control != "UNREGISTERED")) + begin + $display("Error! lpm_rdaddress_control must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + // Initialize mem_data + i_numwords = (lpm_numwords) ? lpm_numwords : (1<<lpm_widthad); + + if (lpm_file == "UNUSED") + for (i=0; i<i_numwords; i=i+1) + mem_data[i] = {lpm_width{1'b0}}; + else + begin + mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf); + $readmemh(ram_initf, mem_data); + end + + // Initialize registers + i_data_reg = {lpm_width{1'b0}}; + i_wraddress_reg = {lpm_widthad{1'b0}}; + i_rdaddress_reg = {lpm_widthad{1'b0}}; + i_wren_reg = 1'b0; + if (rden_used == "TRUE") + i_rden_reg = 1'b0; + else + i_rden_reg = 1'b1; + + // Initialize output + i_q_reg = {lpm_width{1'b0}}; + if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) + begin + i_q_tmp = {lpm_width{1'b1}}; + end + else + i_q_tmp = {lpm_width{1'b0}}; + end + + +// ALWAYS CONSTRUCT BLOCK + + always @(posedge i_inclock) + begin + if (lpm_indata == "REGISTERED") + if ((i_inclocken == 1'b1) && ($time > 0)) + i_data_reg <= data; + + if (lpm_wraddress_control == "REGISTERED") + if ((i_inclocken == 1'b1) && ($time > 0)) + begin + i_wraddress_reg <= wraddress; + i_wren_reg <= i_wren; + end + + end + + always @(posedge i_outclock) + begin + if (lpm_outdata == "REGISTERED") + if ((i_outclocken == 1'b1) && ($time > 0)) + begin + i_q_reg <= i_q_tmp; + end + + if (lpm_rdaddress_control == "REGISTERED") + if ((i_outclocken == 1'b1) && ($time > 0)) + begin + i_rdaddress_reg <= rdaddress; + i_rden_reg <= i_rden; + end + end + + + //========= + // Memory + //========= + + always @(i_data_tmp or i_wren_tmp or i_wraddress_tmp or negedge i_inclock) + begin + if (i_wren_tmp == 1'b1) + if (ValidAddress(i_wraddress_tmp)) + begin + if (((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) && + (lpm_wraddress_control == "REGISTERED")) + begin + if (i_inclock == 1'b0) + mem_data[i_wraddress_tmp] <= i_data_tmp; + end + else + mem_data[i_wraddress_tmp] <= i_data_tmp; + end + end + + always @(i_rden_tmp or i_rdaddress_tmp or mem_data[i_rdaddress_tmp]) + begin + if (i_rden_tmp == 1'b1) + i_q_tmp = (ValidAddress(i_rdaddress_tmp)) + ? mem_data[i_rdaddress_tmp] + : {lpm_width{1'bx}}; + end + + + //======= + // Sync + //======= + + always @(wraddress or i_wraddress_reg) + i_wraddress_tmp = (lpm_wraddress_control == "REGISTERED") + ? i_wraddress_reg + : wraddress; + always @(rdaddress or i_rdaddress_reg) + i_rdaddress_tmp = (lpm_rdaddress_control == "REGISTERED") + ? i_rdaddress_reg + : rdaddress; + always @(i_wren or i_wren_reg) + i_wren_tmp = (lpm_wraddress_control == "REGISTERED") + ? i_wren_reg + : i_wren; + always @(i_rden or i_rden_reg) + i_rden_tmp = (lpm_rdaddress_control == "REGISTERED") + ? i_rden_reg + : i_rden; + always @(data or i_data_reg) + i_data_tmp = (lpm_indata == "REGISTERED") + ? i_data_reg + : data; + +// CONTINOUS ASSIGNMENT + assign q = (lpm_outdata == "REGISTERED") ? i_q_reg : i_q_tmp; + +endmodule // lpm_ram_dp +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_ram_io +// +// Description : Parameterized RAM with a single I/O port megafunction +// +// Limitation : This megafunction is provided only for backward +// compatibility in Cyclone, Stratix, and Stratix GX designs; +// instead, Altera recommends using the altsyncram +// megafunction +// +// Results expected: Output of RAM content at bi-directional DIO. +// +//END_MODULE_NAME-------------------------------------------------------------- +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_ram_io ( dio, inclock, outclock, we, memenab, outenab, address ); + +// PARAMETER DECLARATION + parameter lpm_type = "lpm_ram_io"; + parameter lpm_width = 1; + parameter lpm_widthad = 1; + parameter lpm_numwords = 1<< lpm_widthad; + parameter lpm_indata = "REGISTERED"; + parameter lpm_address_control = "REGISTERED"; + parameter lpm_outdata = "REGISTERED"; + parameter lpm_file = "UNUSED"; + parameter lpm_hint = "UNUSED"; + parameter use_eab = "ON"; + parameter intended_device_family = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_widthad-1:0] address; + input inclock, outclock, we; + input memenab; + input outenab; + +// INPUT/OUTPUT PORT DECLARATION + inout [lpm_width-1:0] dio; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] mem_data [lpm_numwords-1:0]; + reg [lpm_width-1:0] tmp_io; + reg [lpm_width-1:0] tmp_q; + reg [lpm_width-1:0] pdio; + reg [lpm_widthad-1:0] paddress; + reg [lpm_widthad-1:0] paddress_tmp; + reg pwe; +`ifdef VERILATOR + reg [`LPM_MAX_NAME_SZ*8:1] ram_initf; +`else + reg [8*256:1] ram_initf; +`endif + +// INTERNAL WIRE DECLARATION + wire [lpm_width-1:0] read_data; + wire i_inclock; + wire i_outclock; + wire i_memenab; + wire i_outenab; + +// LOCAL INTEGER DECLARATION + integer i; + +// INTERNAL TRI DECLARATION + tri0 inclock; + tri0 outclock; + tri1 memenab; + tri1 outenab; + +// INTERNAL BUF DECLARATION + buf (i_inclock, inclock); + buf (i_outclock, outclock); + buf (i_memenab, memenab); + buf (i_outenab, outenab); + + +// FUNCTON DECLARATION + function ValidAddress; + input [lpm_widthad-1:0] paddress; + + begin + ValidAddress = 1'b0; + if (^paddress === {lpm_widthad{1'bx}}) + begin + $display("%t:Error: Invalid address.", $time); + $display("Time: %0t Instance: %m", $time); + $finish; + end + else if (paddress >= lpm_numwords) + begin + $display("%t:Error: Address out of bound on RAM.", $time); + $display("Time: %0t Instance: %m", $time); + $finish; + end + else + ValidAddress = 1'b1; + end + endfunction + +// COMPONENT INSTANTIATIONS + LPM_MEMORY_INITIALIZATION mem (); + + +// INITIAL CONSTRUCT BLOCK + initial + begin + + if (lpm_width <= 0) + begin + $display("Error! LPM_WIDTH parameter must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_widthad <= 0) + begin + $display("Error! LPM_WIDTHAD parameter must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + // check for number of words out of bound + if ((lpm_numwords > (1 << lpm_widthad)) + ||(lpm_numwords <= (1 << (lpm_widthad-1)))) + begin + $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) + begin + $display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED")) + begin + $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) + begin + $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + for (i = 0; i < lpm_numwords; i=i+1) + mem_data[i] = {lpm_width{1'b0}}; + + // Initialize input/output + pwe = 1'b0; + pdio = {lpm_width{1'b0}}; + paddress = {lpm_widthad{1'b0}}; + paddress_tmp = {lpm_widthad{1'b0}}; + tmp_io = {lpm_width{1'b0}}; + tmp_q = {lpm_width{1'b0}}; + + // load data to the RAM + if (lpm_file != "UNUSED") + begin + mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf); + $readmemh(ram_initf, mem_data); + end + end + + +// ALWAYS CONSTRUCT BLOCK + always @(dio) + begin + if (lpm_indata == "UNREGISTERED") + pdio <= dio; + end + + always @(address) + begin + if (lpm_address_control == "UNREGISTERED") + paddress <= address; + end + + + always @(we) + begin + if (lpm_address_control == "UNREGISTERED") + pwe <= we; + end + + always @(posedge i_inclock) + begin + if (lpm_indata == "REGISTERED") + pdio <= dio; + + if (lpm_address_control == "REGISTERED") + begin + paddress <= address; + pwe <= we; + end + end + + always @(pdio or paddress or pwe or i_memenab) + begin + if (ValidAddress(paddress)) + begin + paddress_tmp <= paddress; + if (lpm_address_control == "UNREGISTERED") + if (pwe && i_memenab) + mem_data[paddress] <= pdio; + end + else + begin + if (lpm_outdata == "UNREGISTERED") + tmp_q <= {lpm_width{1'bx}}; + end + end + + always @(read_data) + begin + if (lpm_outdata == "UNREGISTERED") + tmp_q <= read_data; + end + + always @(negedge i_inclock or pdio) + begin + if (lpm_address_control == "REGISTERED") + if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) + if (pwe && i_memenab && (i_inclock == 1'b0)) + mem_data[paddress] = pdio; + end + + always @(posedge i_inclock) + begin + if (lpm_address_control == "REGISTERED") + if ((use_eab == "OFF") && pwe && i_memenab) + mem_data[paddress] <= pdio; + end + + always @(posedge i_outclock) + begin + if (lpm_outdata == "REGISTERED") + tmp_q <= mem_data[paddress]; + end + + always @(i_memenab or i_outenab or tmp_q) + begin + if (i_memenab && i_outenab) + tmp_io = tmp_q; + else if ((!i_memenab) || (i_memenab && (!i_outenab))) + tmp_io = {lpm_width{1'bz}}; + end + + +// CONTINOUS ASSIGNMENT + assign dio = tmp_io; + assign read_data = mem_data[paddress_tmp]; + +endmodule // lpm_ram_io + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_rom +// +// Description : Parameterized ROM megafunction. This megafunction is provided +// only for backward compatibility in Cyclone, Stratix, and +// Stratix GX designs; instead, Altera recommends using the +// altsyncram megafunction. +// +// Limitation : This option is available for all Altera devices supported by +// the Quartus II software except MAX 3000 and MAX 7000 devices. +// +// Results expected: Output of memory. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_rom ( + address, // Address input to the memory. (Required) + inclock, // Clock for input registers. + outclock, // Clock for output registers. + memenab, // Memory enable input. + q // Output of memory. (Required) +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; // Width of the q[] port. (Required) + parameter lpm_widthad = 1; // Width of the address[] port. (Required) + parameter lpm_numwords = 0; // Number of words stored in memory. + parameter lpm_address_control = "REGISTERED"; // Indicates whether the address port is registered. + parameter lpm_outdata = "REGISTERED"; // Indicates whether the q and eq ports are registered. + parameter lpm_file = ""; // Name of the memory file containing ROM initialization data + parameter intended_device_family = "Stratix"; + parameter lpm_type = "lpm_rom"; + parameter lpm_hint = "UNUSED"; + +// LOCAL_PARAMETERS_BEGIN + + parameter NUM_WORDS = (lpm_numwords == 0) ? (1 << lpm_widthad) : lpm_numwords; + +// LOCAL_PARAMETERS_END + +// INPUT PORT DECLARATION + input [lpm_widthad-1:0] address; + input inclock; + input outclock; + input memenab; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] mem_data [0:NUM_WORDS-1]; + reg [lpm_widthad-1:0] address_reg; + reg [lpm_width-1:0] tmp_q_reg; +`ifdef VERILATOR + reg [`LPM_MAX_NAME_SZ*8:1] rom_initf; +`else + reg [8*256:1] rom_initf; +`endif + +// INTERNAL WIRE DECLARATION + wire [lpm_widthad-1:0] w_address; + wire [lpm_width-1:0] w_read_data; + wire i_inclock; + wire i_outclock; + wire i_memenab; + +// LOCAL INTEGER DECLARATION + integer i; + +// INTERNAL TRI DECLARATION + tri0 inclock; + tri0 outclock; + tri1 memenab; + + buf (i_inclock, inclock); + buf (i_outclock, outclock); + buf (i_memenab, memenab); + +// COMPONENT INSTANTIATIONS + LPM_DEVICE_FAMILIES dev (); + LPM_MEMORY_INITIALIZATION mem (); + +// FUNCTON DECLARATION + // Check the validity of the address. + function ValidAddress; + input [lpm_widthad-1:0] address; + begin + ValidAddress = 1'b0; + if (^address == {lpm_widthad{1'bx}}) + begin + $display("%d:Error: Invalid address.", $time); + $display("Time: %0t Instance: %m", $time); + $finish; + end + else if (address >= NUM_WORDS) + begin + $display("%d:Error: Address out of bound on ROM.", $time); + $display("Time: %0t Instance: %m", $time); + $finish; + end + else + ValidAddress = 1'b1; + end + endfunction + +// INITIAL CONSTRUCT BLOCK + initial + begin + // Initialize output + tmp_q_reg = {lpm_width{1'b0}}; + address_reg = {lpm_widthad{1'b0}}; + + if (lpm_width <= 0) + begin + $display("Error! LPM_WIDTH parameter must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (lpm_widthad <= 0) + begin + $display("Error! LPM_WIDTHAD parameter must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + // check for number of words out of bound + if ((NUM_WORDS > (1 << lpm_widthad)) || + (NUM_WORDS <= (1 << (lpm_widthad-1)))) + begin + $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_address_control != "REGISTERED") && + (lpm_address_control != "UNREGISTERED")) + begin + $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) + begin + $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $display("Time: %0t Instance: %m", $time); + $finish; + end + if (dev.FEATURE_FAMILY_MAX(intended_device_family) == 1) + begin + $display ("Error! LPM_ROM megafunction does not support %s devices.", intended_device_family); + $display("Time: %0t Instance: %m", $time); + $finish; + end + + for (i = 0; i < NUM_WORDS; i=i+1) + mem_data[i] = {lpm_width{1'b0}}; + + // load data to the ROM + if ((lpm_file == "") || (lpm_file == "UNUSED")) + begin + $display("Warning: LPM_ROM must have data file for initialization.\n"); + $display ("Time: %0t Instance: %m", $time); + end + else + begin + mem.convert_to_ver_file(lpm_file, lpm_width, rom_initf); + $readmemh(rom_initf, mem_data); + end + end + + always @(posedge i_inclock) + begin + if (lpm_address_control == "REGISTERED") + address_reg <= address; // address port is registered + end + + always @(w_address or w_read_data) + begin + if (ValidAddress(w_address)) + begin + if (lpm_outdata == "UNREGISTERED") + // Load the output register with the contents of the memory location + // pointed to by address[]. + tmp_q_reg <= w_read_data; + end + else + begin + if (lpm_outdata == "UNREGISTERED") + tmp_q_reg <= {lpm_width{1'bx}}; + end + end + + always @(posedge i_outclock) + begin + if (lpm_outdata == "REGISTERED") + begin + if (ValidAddress(w_address)) + tmp_q_reg <= w_read_data; + else + tmp_q_reg <= {lpm_width{1'bx}}; + end + end + +// CONTINOUS ASSIGNMENT + assign w_address = (lpm_address_control == "REGISTERED") ? address_reg : address; + assign w_read_data = mem_data[w_address]; + assign q = (i_memenab) ? tmp_q_reg : {lpm_width{1'bz}}; + +endmodule // lpm_rom +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_fifo +// +// Description : +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +module lpm_fifo ( data, + clock, + wrreq, + rdreq, + aclr, + sclr, + q, + usedw, + full, + empty ); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_widthu = 1; + parameter lpm_numwords = 2; + parameter lpm_showahead = "OFF"; + parameter lpm_type = "lpm_fifo"; + parameter lpm_hint = ""; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input clock; + input wrreq; + input rdreq; + input aclr; + input sclr; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + output [lpm_widthu-1:0] usedw; + output full; + output empty; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] mem_data [(1<<lpm_widthu):0]; + reg [lpm_width-1:0] tmp_data; + reg [lpm_widthu-1:0] count_id; + reg [lpm_widthu-1:0] read_id; + reg [lpm_widthu-1:0] write_id; + reg write_flag; + reg full_flag; + reg empty_flag; + reg [lpm_width-1:0] tmp_q; + + reg [8*5:1] overflow_checking; + reg [8*5:1] underflow_checking; + reg [8*20:1] allow_rwcycle_when_full; + reg [8*20:1] intended_device_family; + +// INTERNAL WIRE DECLARATION + wire valid_rreq; + wire valid_wreq; + +// INTERNAL TRI DECLARATION + tri0 aclr; + +// LOCAL INTEGER DECLARATION + integer i; + +// COMPONENT INSTANTIATIONS + LPM_DEVICE_FAMILIES dev (); + LPM_HINT_EVALUATION eva(); + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display ("Error! LPM_WIDTH must be greater than 0."); + $display("Time: %0t Instance: %m", $time); + $stop; + end + if (lpm_numwords <= 1) + begin + $display ("Error! LPM_NUMWORDS must be greater than or equal to 2."); + $display("Time: %0t Instance: %m", $time); + $stop; + end + if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu))) + begin + $display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU)."); + $display("Time: %0t Instance: %m", $time); + $stop; + end + if (lpm_numwords <= (1 << (lpm_widthu - 1))) + begin + $display ("Error! LPM_WIDTHU is too big for the specified LPM_NUMWORDS."); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING"); + if(overflow_checking == "") + overflow_checking = "ON"; + else if ((overflow_checking != "ON") && (overflow_checking != "OFF")) + begin + $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING"); + if(underflow_checking == "") + underflow_checking = "ON"; + else if ((underflow_checking != "ON") && (underflow_checking != "OFF")) + begin + $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + allow_rwcycle_when_full = eva.GET_PARAMETER_VALUE(lpm_hint, "ALLOW_RWCYCLE_WHEN_FULL"); + if (allow_rwcycle_when_full == "") + allow_rwcycle_when_full = "OFF"; + else if ((allow_rwcycle_when_full != "ON") && (allow_rwcycle_when_full != "OFF")) + begin + $display ("Error! ALLOW_RWCYCLE_WHEN_FULL must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY"); + if (intended_device_family == "") + intended_device_family = "Stratix II"; + else if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $display("Time: %0t Instance: %m", $time); + $stop; + end + for (i = 0; i < (1<<lpm_widthu); i = i + 1) + begin + if (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) + mem_data[i] <= {lpm_width{1'bx}}; + else + mem_data[i] <= {lpm_width{1'b0}}; + end + + tmp_data <= 0; + if (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) + tmp_q <= {lpm_width{1'bx}}; + else + tmp_q <= {lpm_width{1'b0}}; + write_flag <= 1'b0; + count_id <= 0; + read_id <= 0; + write_id <= 0; + full_flag <= 1'b0; + empty_flag <= 1'b1; + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge clock or posedge aclr) + begin + if (aclr) + begin + if (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + begin + if (lpm_showahead == "ON") + tmp_q <= mem_data[0]; + else + tmp_q <= {lpm_width{1'b0}}; + end + + read_id <= 0; + count_id <= 0; + full_flag <= 1'b0; + empty_flag <= 1'b1; + + if (valid_wreq && (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + begin + tmp_data <= data; + write_flag <= 1'b1; + end + else + write_id <= 0; + end + else if (sclr) + begin + if ((lpm_showahead == "ON") || (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + tmp_q <= mem_data[0]; + else + tmp_q <= mem_data[read_id]; + read_id <= 0; + count_id <= 0; + full_flag <= 1'b0; + empty_flag <= 1'b1; + + if (valid_wreq) + begin + tmp_data <= data; + write_flag <= 1'b1; + end + else + write_id <= 0; + end + else + begin + // Both WRITE and READ operations + if (valid_wreq && valid_rreq) + begin + tmp_data <= data; + write_flag <= 1'b1; + empty_flag <= 1'b0; + if (allow_rwcycle_when_full == "OFF") + begin + full_flag <= 1'b0; + end + + if (read_id >= ((1 << lpm_widthu) - 1)) + begin + if (lpm_showahead == "ON") + tmp_q <= mem_data[0]; + else + tmp_q <= mem_data[read_id]; + read_id <= 0; + end + else + begin + if (lpm_showahead == "ON") + tmp_q <= mem_data[read_id + 1]; + else + tmp_q <= mem_data[read_id]; + read_id <= read_id + 1; + end + end + // WRITE operation only + else if (valid_wreq) + begin + tmp_data <= data; + empty_flag <= 1'b0; + write_flag <= 1'b1; + + if (count_id >= (1 << lpm_widthu) - 1) + count_id <= 0; + else + count_id <= count_id + 1; + + if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0)) + full_flag <= 1'b1; + + if (lpm_showahead == "ON") + tmp_q <= mem_data[read_id]; + end + // READ operation only + else if (valid_rreq) + begin + full_flag <= 1'b0; + + if (count_id <= 0) + count_id <= {lpm_widthu{1'b1}}; + else + count_id <= count_id - 1; + + if ((count_id == 1) && (full_flag == 1'b0)) + empty_flag <= 1'b1; + + if (read_id >= ((1<<lpm_widthu) - 1)) + begin + if (lpm_showahead == "ON") + tmp_q <= mem_data[0]; + else + tmp_q <= mem_data[read_id]; + read_id <= 0; + end + else + begin + if (lpm_showahead == "ON") + tmp_q <= mem_data[read_id + 1]; + else + tmp_q <= mem_data[read_id]; + read_id <= read_id + 1; + end + end // if Both WRITE and READ operations + + end // if aclr + end // @(posedge clock) + + always @(negedge clock) + begin + if (write_flag) + begin + write_flag <= 1'b0; + mem_data[write_id] <= tmp_data; + + if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1))) + write_id <= 0; + else + write_id <= write_id + 1; + end + + if ((lpm_showahead == "ON") && ($time > 0)) + tmp_q <= ((write_flag == 1'b1) && (write_id == read_id)) ? + tmp_data : mem_data[read_id]; + + end // @(negedge clock) + +// CONTINOUS ASSIGNMENT + assign valid_rreq = (underflow_checking == "OFF") ? rdreq : rdreq && ~empty_flag; + assign valid_wreq = (overflow_checking == "OFF") ? wrreq : + (allow_rwcycle_when_full == "ON") ? wrreq && (!full_flag || rdreq) : + wrreq && !full_flag; + assign q = tmp_q; + assign full = full_flag; + assign empty = empty_flag; + assign usedw = count_id; + +endmodule // lpm_fifo +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_fifo_dc_dffpipe +// +// Description : Dual Clocks FIFO +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_fifo_dc_dffpipe (d, + clock, + aclr, + q); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_delay = 1; + parameter lpm_width = 64; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] d; + input clock; + input aclr; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] dffpipe [lpm_delay:0]; + reg [lpm_width-1:0] q; + +// LOCAL INTEGER DECLARATION + integer delay; + integer i; + +// INITIAL CONSTRUCT BLOCK + initial + begin + delay <= lpm_delay - 1; + + for (i = 0; i <= lpm_delay; i = i + 1) + dffpipe[i] <= 0; + q <= 0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge aclr or posedge clock) + begin + if (aclr) + begin + for (i = 0; i <= lpm_delay; i = i + 1) + dffpipe[i] <= 0; + q <= 0; + end + else if (clock) + begin + if ((lpm_delay > 0) && ($time > 0)) + begin +`ifdef VERILATOR + if (lpm_delay > 0) +`else + if (delay > 0) +`endif + begin +`ifdef VERILATOR + for (i = lpm_delay-1; i > 0; i = i - 1) +`else + for (i = delay; i > 0; i = i - 1) +`endif + dffpipe[i] <= dffpipe[i - 1]; + q <= dffpipe[delay - 1]; + end + else + q <= d; + + dffpipe[0] <= d; + end + end + end // @(posedge aclr or posedge clock) + + always @(d) + begin + if (lpm_delay == 0) + q <= d; + end // @(d) + +endmodule // lpm_fifo_dc_dffpipe +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_fifo_dc_fefifo +// +// Description : Dual Clock FIFO +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_fifo_dc_fefifo ( usedw_in, + wreq, + rreq, + clock, + aclr, + empty, + full); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_widthad = 1; + parameter lpm_numwords = 1; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + parameter lpm_mode = "READ"; + parameter lpm_hint = ""; + +// INPUT PORT DECLARATION + input [lpm_widthad-1:0] usedw_in; + input wreq; + input rreq; + input clock; + input aclr; + +// OUTPUT PORT DECLARATION + output empty; + output full; + +// INTERNAL REGISTERS DECLARATION + reg [1:0] sm_empty; + reg lrreq; + reg i_empty; + reg i_full; + reg [8*5:1] i_overflow_checking; + reg [8*5:1] i_underflow_checking; + +// LOCAL INTEGER DECLARATION + integer almostfull; + +// COMPONENT INSTANTIATIONS + LPM_HINT_EVALUATION eva(); + +// INITIAL CONSTRUCT BLOCK + initial + begin + if ((lpm_mode != "READ") && (lpm_mode != "WRITE")) + begin + $display ("Error! LPM_MODE must be READ or WRITE."); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING"); + if (i_overflow_checking == "") + begin + if ((overflow_checking != "ON") && (overflow_checking != "OFF")) + begin + $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + else + i_overflow_checking = overflow_checking; + end + else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF")) + begin + $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING"); + if(i_underflow_checking == "") + begin + if ((underflow_checking != "ON") && (underflow_checking != "OFF")) + begin + $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + else + i_underflow_checking = underflow_checking; + end + else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF")) + begin + $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + sm_empty <= 2'b00; + i_empty <= 1'b1; + i_full <= 1'b0; + lrreq <= 1'b0; + + if (lpm_numwords >= 3) + almostfull <= lpm_numwords - 3; + else + almostfull <= 0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge aclr) + begin + sm_empty <= 2'b00; + i_empty <= 1'b1; + i_full <= 1'b0; + lrreq <= 1'b0; + end // @(posedge aclr) + + always @(posedge clock) + begin + if (i_underflow_checking == "OFF") + lrreq <= rreq; + else + lrreq <= rreq && ~i_empty; + + if (~aclr && ($time > 0)) + begin + if (lpm_mode == "READ") + begin + // verilator lint_off CASEX + casex (sm_empty) + // verilator lint_on CASEX + // state_empty + 2'b00: + if (usedw_in != 0) + sm_empty <= 2'b01; + // state_non_empty + // verilator lint_off CMPCONST + 2'b01: + if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq))) + sm_empty <= 2'b10; + // state_emptywait + 2'b10: + if (usedw_in > 1) + sm_empty <= 2'b01; + else + sm_empty <= 2'b00; + // verilator lint_on CMPCONST + default: + begin + $display ("Error! Invalid sm_empty state in read mode."); + $display("Time: %0t Instance: %m", $time); + end + endcase + end // if (lpm_mode == "READ") + else if (lpm_mode == "WRITE") + begin + // verilator lint_off CASEX + casex (sm_empty) + // verilator lint_on CASEX + // state_empty + 2'b00: + if (wreq) + sm_empty <= 2'b01; + // state_one + 2'b01: + if (!wreq) + sm_empty <= 2'b11; + // state_non_empty + 2'b11: + if (wreq) + sm_empty <= 2'b01; + else if (usedw_in == 0) + sm_empty <= 2'b00; + default: + begin + $display ("Error! Invalid sm_empty state in write mode."); + $display("Time: %0t Instance: %m", $time); + end + endcase + end // if (lpm_mode == "WRITE") + + if (~aclr && (usedw_in >= almostfull) && ($time > 0)) + i_full <= 1'b1; + else + i_full <= 1'b0; + end // if (~aclr && $time > 0) + end // @(posedge clock) + + always @(sm_empty) + begin + i_empty <= !sm_empty[0]; + end + // @(sm_empty) + +// CONTINOUS ASSIGNMENT + assign empty = i_empty; + assign full = i_full; +endmodule // lpm_fifo_dc_fefifo +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_fifo_dc_async +// +// Description : Asynchronous Dual Clocks FIFO +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_fifo_dc_async ( data, + rdclk, + wrclk, + aclr, + rdreq, + wrreq, + rdfull, + wrfull, + rdempty, + wrempty, + rdusedw, + wrusedw, + q); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_widthu = 1; + parameter lpm_numwords = 2; + parameter delay_rdusedw = 1; + parameter delay_wrusedw = 1; + parameter rdsync_delaypipe = 3; + parameter wrsync_delaypipe = 3; + parameter lpm_showahead = "OFF"; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + parameter lpm_hint = "INTENDED_DEVICE_FAMILY=Stratix"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input rdclk; + input wrclk; + input aclr; + input wrreq; + input rdreq; + +// OUTPUT PORT DECLARATION + output rdfull; + output wrfull; + output rdempty; + output wrempty; + output [lpm_widthu-1:0] rdusedw; + output [lpm_widthu-1:0] wrusedw; + output [lpm_width-1:0] q; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0]; + reg [lpm_width-1:0] i_data_tmp; + reg [lpm_widthu-1:0] i_rdptr; + reg [lpm_widthu-1:0] i_wrptr; + reg [lpm_widthu-1:0] i_wrptr_tmp; + reg i_rdenclock; + reg i_wren_tmp; + reg [lpm_widthu-1:0] i_wr_udwn; + reg [lpm_widthu-1:0] i_rd_udwn; + reg i_showahead_flag; + reg i_showahead_flag1; + reg [lpm_widthu:0] i_rdusedw; + reg [lpm_widthu-1:0] i_wrusedw; + reg [lpm_width-1:0] i_q_tmp; + + reg [8*5:1] i_overflow_checking; + reg [8*5:1] i_underflow_checking; + reg [8*10:1] use_eab; + reg [8*20:1] intended_device_family; + +// INTERNAL WIRE DECLARATION + wire w_rden; + wire w_wren; + wire w_rdempty; + wire w_wrempty; + wire w_rdfull; + wire w_wrfull; + wire [lpm_widthu-1:0] w_rdptrrg; + wire [lpm_widthu-1:0] w_wrdelaycycle; + wire [lpm_widthu-1:0] w_ws_nbrp; + wire [lpm_widthu-1:0] w_rs_nbwp; + wire [lpm_widthu-1:0] w_ws_dbrp; + wire [lpm_widthu-1:0] w_rs_dbwp; + wire [lpm_widthu-1:0] w_rd_dbuw; + wire [lpm_widthu-1:0] w_wr_dbuw; + wire [lpm_widthu-1:0] w_rdusedw; + wire [lpm_widthu-1:0] w_wrusedw; + +// INTERNAL TRI DECLARATION + tri0 aclr; + +// LOCAL INTEGER DECLARATION + integer i; + +// COMPONENT INSTANTIATIONS + LPM_DEVICE_FAMILIES dev (); + LPM_HINT_EVALUATION eva(); + +// INITIAL CONSTRUCT BLOCK + initial + begin + if((lpm_showahead != "ON") && (lpm_showahead != "OFF")) + begin + $display ("Error! lpm_showahead must be ON or OFF."); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING"); + if (i_overflow_checking == "") + begin + if ((overflow_checking != "ON") && (overflow_checking != "OFF")) + begin + $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + else + i_overflow_checking = overflow_checking; + end + else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF")) + begin + $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING"); + if(i_underflow_checking == "") + begin + if ((underflow_checking != "ON") && (underflow_checking != "OFF")) + begin + $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + else + i_underflow_checking = underflow_checking; + end + else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF")) + begin + $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + use_eab = eva.GET_PARAMETER_VALUE(lpm_hint, "USE_EAB"); + if(use_eab == "") + use_eab = "ON"; + else if ((use_eab != "ON") && (use_eab != "OFF")) + begin + $display ("Error! USE_EAB must equal to either 'ON' or 'OFF'"); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY"); + if (intended_device_family == "") + intended_device_family = "Stratix II"; + else if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $display("Time: %0t Instance: %m", $time); + $stop; + end + + for (i = 0; i < (1 << lpm_widthu); i = i + 1) + mem_data[i] <= 0; + i_data_tmp <= 0; + i_rdptr <= 0; + i_wrptr <= 0; + i_wrptr_tmp <= 0; + i_wren_tmp <= 0; + i_wr_udwn <= 0; + i_rd_udwn <= 0; + + i_rdusedw <= 0; + i_wrusedw <= 0; + i_q_tmp <= 0; + end + +// COMPONENT INSTANTIATIONS + // Delays & DFF Pipes + lpm_fifo_dc_dffpipe DP_RDPTR_D ( + .d (i_rdptr), + .clock (i_rdenclock), + .aclr (aclr), + .q (w_rdptrrg)); + lpm_fifo_dc_dffpipe DP_WRPTR_D ( + .d (i_wrptr), + .clock (wrclk), + .aclr (aclr), + .q (w_wrdelaycycle)); + defparam + DP_RDPTR_D.lpm_delay = 0, + DP_RDPTR_D.lpm_width = lpm_widthu, + DP_WRPTR_D.lpm_delay = 1, + DP_WRPTR_D.lpm_width = lpm_widthu; + + lpm_fifo_dc_dffpipe DP_WS_NBRP ( + .d (w_rdptrrg), + .clock (wrclk), + .aclr (aclr), + .q (w_ws_nbrp)); + lpm_fifo_dc_dffpipe DP_RS_NBWP ( + .d (w_wrdelaycycle), + .clock (rdclk), + .aclr (aclr), + .q (w_rs_nbwp)); + lpm_fifo_dc_dffpipe DP_WS_DBRP ( + .d (w_ws_nbrp), + .clock (wrclk), + .aclr (aclr), + .q (w_ws_dbrp)); + lpm_fifo_dc_dffpipe DP_RS_DBWP ( + .d (w_rs_nbwp), + .clock (rdclk), + .aclr (aclr), + .q (w_rs_dbwp)); + defparam + DP_WS_NBRP.lpm_delay = wrsync_delaypipe, + DP_WS_NBRP.lpm_width = lpm_widthu, + DP_RS_NBWP.lpm_delay = rdsync_delaypipe, + DP_RS_NBWP.lpm_width = lpm_widthu, + DP_WS_DBRP.lpm_delay = 1, // gray_delaypipe + DP_WS_DBRP.lpm_width = lpm_widthu, + DP_RS_DBWP.lpm_delay = 1, // gray_delaypipe + DP_RS_DBWP.lpm_width = lpm_widthu; + + lpm_fifo_dc_dffpipe DP_WRUSEDW ( + .d (i_wr_udwn), + .clock (wrclk), + .aclr (aclr), + .q (w_wrusedw)); + lpm_fifo_dc_dffpipe DP_RDUSEDW ( + .d (i_rd_udwn), + .clock (rdclk), + .aclr (aclr), + .q (w_rdusedw)); + lpm_fifo_dc_dffpipe DP_WR_DBUW ( + .d (i_wr_udwn), + .clock (wrclk), + .aclr (aclr), + .q (w_wr_dbuw)); + lpm_fifo_dc_dffpipe DP_RD_DBUW ( + .d (i_rd_udwn), + .clock (rdclk), + .aclr (aclr), + .q (w_rd_dbuw)); + defparam + DP_WRUSEDW.lpm_delay = delay_wrusedw, + DP_WRUSEDW.lpm_width = lpm_widthu, + DP_RDUSEDW.lpm_delay = delay_rdusedw, + DP_RDUSEDW.lpm_width = lpm_widthu, + DP_WR_DBUW.lpm_delay = 1, // wrusedw_delaypipe + DP_WR_DBUW.lpm_width = lpm_widthu, + DP_RD_DBUW.lpm_delay = 1, // rdusedw_delaypipe + DP_RD_DBUW.lpm_width = lpm_widthu; + + // Empty/Full + lpm_fifo_dc_fefifo WR_FE ( + .usedw_in (w_wr_dbuw), + .wreq (wrreq), + .rreq (rdreq), + .clock (wrclk), + .aclr (aclr), + .empty (w_wrempty), + .full (w_wrfull)); + lpm_fifo_dc_fefifo RD_FE ( + .usedw_in (w_rd_dbuw), + .rreq (rdreq), + .wreq(wrreq), + .clock (rdclk), + .aclr (aclr), + .empty (w_rdempty), + .full (w_rdfull)); + defparam + WR_FE.lpm_widthad = lpm_widthu, + WR_FE.lpm_numwords = lpm_numwords, + WR_FE.underflow_checking = underflow_checking, + WR_FE.overflow_checking = overflow_checking, + WR_FE.lpm_mode = "WRITE", + WR_FE.lpm_hint = lpm_hint, + RD_FE.lpm_widthad = lpm_widthu, + RD_FE.lpm_numwords = lpm_numwords, + RD_FE.underflow_checking = underflow_checking, + RD_FE.overflow_checking = overflow_checking, + RD_FE.lpm_mode = "READ", + RD_FE.lpm_hint = lpm_hint; + +// ALWAYS CONSTRUCT BLOCK + always @(posedge aclr) + begin + i_rdptr <= 0; + i_wrptr <= 0; + if (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) || + (use_eab == "OFF")) + if (lpm_showahead == "ON") + i_q_tmp <= mem_data[0]; + else + i_q_tmp <= 0; + end // @(posedge aclr) + + // FIFOram + always @(posedge wrclk) + begin + if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) || + (use_eab == "OFF"))) + begin + i_data_tmp <= 0; + i_wrptr_tmp <= 0; + i_wren_tmp <= 0; + end + else if (wrclk && ($time > 0)) + begin + i_data_tmp <= data; + i_wrptr_tmp <= i_wrptr; + i_wren_tmp <= w_wren; + + if (w_wren) + begin + if (~aclr && ((i_wrptr < (1<<lpm_widthu)-1) || (i_overflow_checking == "OFF"))) + i_wrptr <= i_wrptr + 1; + else + i_wrptr <= 0; + + if (use_eab == "OFF") + begin + mem_data[i_wrptr] <= data; + + if (lpm_showahead == "ON") + i_showahead_flag1 <= 1'b1; + end + end + end + end // @(posedge wrclk) + + always @(negedge wrclk) + begin + if ((~wrclk && (use_eab == "ON")) && ($time > 0)) + begin + if (i_wren_tmp) + begin + mem_data[i_wrptr_tmp] <= i_data_tmp; + end + + if (lpm_showahead == "ON") + i_showahead_flag1 <= 1'b1; + end + end // @(negedge wrclk) + + always @(posedge rdclk) + begin + if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) || + (use_eab == "OFF"))) + begin + if (lpm_showahead == "ON") + i_q_tmp <= mem_data[0]; + else + i_q_tmp <= 0; + end + else if (rdclk && w_rden && ($time > 0)) + begin + if (~aclr && ((i_rdptr < (1<<lpm_widthu)-1) || (i_underflow_checking == "OFF"))) + i_rdptr <= i_rdptr + 1; + else + i_rdptr <= 0; + + if (lpm_showahead == "ON") + i_showahead_flag1 <= 1'b1; + else + i_q_tmp <= mem_data[i_rdptr]; + end + end // @(rdclk) + + always @(posedge i_showahead_flag) + begin + i_q_tmp <= mem_data[i_rdptr]; + i_showahead_flag1 <= 1'b0; + end // @(posedge i_showahead_flag) + + always @(i_showahead_flag1) + begin + i_showahead_flag <= i_showahead_flag1; + end // @(i_showahead_flag1) + + // Delays & DFF Pipes + always @(negedge rdclk) + begin + i_rdenclock <= 0; + end // @(negedge rdclk) + + always @(posedge rdclk) + begin + if (w_rden) + i_rdenclock <= 1; + end // @(posedge rdclk) + + always @(i_wrptr or w_ws_dbrp) + begin + i_wr_udwn <= i_wrptr - w_ws_dbrp; + end // @(i_wrptr or w_ws_dbrp) + + always @(i_rdptr or w_rs_dbwp) + begin + i_rd_udwn <= w_rs_dbwp - i_rdptr; + end // @(i_rdptr or w_rs_dbwp) + +// CONTINOUS ASSIGNMENT + assign w_rden = (i_underflow_checking == "OFF") ? rdreq : rdreq && !w_rdempty; + assign w_wren = (i_overflow_checking == "OFF") ? wrreq : wrreq && !w_wrfull; + assign q = i_q_tmp; + assign wrfull = w_wrfull; + assign rdfull = w_rdfull; + assign wrempty = w_wrempty; + assign rdempty = w_rdempty; + assign wrusedw = w_wrusedw; + assign rdusedw = w_rdusedw; + +endmodule // lpm_fifo_dc_async +// END OF MODULE + + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_fifo_dc +// +// Description : +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_fifo_dc (data, + rdclock, + wrclock, + aclr, + rdreq, + wrreq, + rdfull, + wrfull, + rdempty, + wrempty, + rdusedw, + wrusedw, + q); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_widthu = 1; + parameter lpm_numwords = 2; + parameter lpm_showahead = "OFF"; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + parameter lpm_hint = ""; + parameter lpm_type = "lpm_fifo_dc"; + +// LOCAL PARAMETER DECLARATION + parameter delay_rdusedw = 1; + parameter delay_wrusedw = 1; + parameter rdsync_delaypipe = 3; + parameter wrsync_delaypipe = 3; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input rdclock; + input wrclock; + input aclr; + input rdreq; + input wrreq; + +// OUTPUT PORT DECLARATION + output rdfull; + output wrfull; + output rdempty; + output wrempty; + output [lpm_widthu-1:0] rdusedw; + output [lpm_widthu-1:0] wrusedw; + output [lpm_width-1:0] q; + +// internal reg + wire w_rdfull_s; + wire w_wrfull_s; + wire w_rdempty_s; + wire w_wrempty_s; + wire w_rdfull_a; + wire w_wrfull_a; + wire w_rdempty_a; + wire w_wrempty_a; + wire [lpm_widthu-1:0] w_rdusedw_s; + wire [lpm_widthu-1:0] w_wrusedw_s; + wire [lpm_widthu-1:0] w_rdusedw_a; + wire [lpm_widthu-1:0] w_wrusedw_a; + wire [lpm_width-1:0] w_q_s; + wire [lpm_width-1:0] w_q_a; + wire i_aclr; + +// INTERNAL TRI DECLARATION + tri0 aclr; + buf (i_aclr, aclr); + +// COMPONENT INSTANTIATIONS + lpm_fifo_dc_async ASYNC ( + .data (data), + .rdclk (rdclock), + .wrclk (wrclock), + .aclr (i_aclr), + .rdreq (rdreq), + .wrreq (wrreq), + .rdfull (w_rdfull_a), + .wrfull (w_wrfull_a), + .rdempty (w_rdempty_a), + .wrempty (w_wrempty_a), + .rdusedw (w_rdusedw_a), + .wrusedw (w_wrusedw_a), + .q (w_q_a) ); + defparam + ASYNC.lpm_width = lpm_width, + ASYNC.lpm_widthu = lpm_widthu, + ASYNC.lpm_numwords = lpm_numwords, + ASYNC.delay_rdusedw = delay_rdusedw, + ASYNC.delay_wrusedw = delay_wrusedw, + ASYNC.rdsync_delaypipe = rdsync_delaypipe, + ASYNC.wrsync_delaypipe = wrsync_delaypipe, + ASYNC.lpm_showahead = lpm_showahead, + ASYNC.underflow_checking = underflow_checking, + ASYNC.overflow_checking = overflow_checking, + ASYNC.lpm_hint = lpm_hint; + +// CONTINOUS ASSIGNMENT + assign rdfull = w_rdfull_a; + assign wrfull = w_wrfull_a; + assign rdempty = w_rdempty_a; + assign wrempty = w_wrempty_a; + assign rdusedw = w_rdusedw_a; + assign wrusedw = w_wrusedw_a; + assign q = w_q_a; +endmodule // lpm_fifo_dc +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_inpad +// +// Description : +// +// Limitation : n/a +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_inpad ( + pad, + result +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_type = "lpm_inpad"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] pad; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] result; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(pad) + begin + result = pad; + end + +endmodule // lpm_inpad +// END OF MODULE + + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_outpad +// +// Description : +// +// Limitation : n/a +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_outpad ( + data, + pad +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_type = "lpm_outpad"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] pad; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] pad; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(data) + begin + pad = data; + end + +endmodule // lpm_outpad +// END OF MODULE + + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : lpm_bipad +// +// Description : +// +// Limitation : n/a +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module lpm_bipad ( + data, + enable, + result, + pad +); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_type = "lpm_bipad"; + parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input enable; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] result; + +// INPUT/OUTPUT PORT DECLARATION + inout [lpm_width-1:0] pad; + +// INTERNAL REGISTER/SIGNAL DECLARATION + reg [lpm_width-1:0] result; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (lpm_width <= 0) + begin + $display("Value of lpm_width parameter must be greater than 0(ERROR)"); + $display("Time: %0t Instance: %m", $time); + $finish; + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(data or pad or enable) + begin + if (enable == 1) + begin + result = {lpm_width{1'bz}}; + end + else if (enable == 0) + begin + result = pad; + end + end + +// CONTINOUS ASSIGNMENT + assign pad = (enable == 1) ? data : {lpm_width{1'bz}}; + +endmodule // lpm_bipad +// END OF MODULE
diff --git a/SVIncCompil/Testcases/Verilator/t_alw_combdly.v b/SVIncCompil/Testcases/Verilator/t_alw_combdly.v new file mode 100644 index 0000000..b17127d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_alw_combdly.v
@@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [31:0] a, b, c, d, e, f, g, h; + + always @ (*) begin // Test Verilog 2001 (*) + // verilator lint_off COMBDLY + c <= a | b; + // verilator lint_on COMBDLY + end + + always @ (posedge (clk)) begin // always bug 2008/4/18 + d <= a | b; + end + always @ ((d)) begin // always bug 2008/4/18 + e = d; + end + + parameter CONSTANT = 1; + always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412 + f = e; + end + always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412 + g = f; + end + always @ ({CONSTANT, g}) begin // bug745 + h = g; + end + //always @ ((posedge b) or (a or b)) begin // note both illegal + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + if (cyc==1) begin + a <= 32'hfeed0000; + b <= 32'h0000face; + end + if (cyc==2) begin + if (c != 32'hfeedface) $stop; + end + if (cyc==3) begin + if (h != 32'hfeedface) $stop; + end + if (cyc==7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_alw_dly.v b/SVIncCompil/Testcases/Verilator/t_alw_dly.v new file mode 100644 index 0000000..781a670 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_alw_dly.v
@@ -0,0 +1,63 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg posedge_wr_clocks; + reg prev_wr_clocks; + reg [31:0] m_din; + reg [31:0] m_dout; + + always @(negedge clk) begin + prev_wr_clocks = 0; + end + + reg comb_pos_1; + reg comb_prev_1; + always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin + comb_pos_1 = (clk &~ prev_wr_clocks); + comb_prev_1 = comb_pos_1 | posedge_wr_clocks; + comb_pos_1 = 1'b1; + end + + always @ (posedge clk) begin + posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS + prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS + if (posedge_wr_clocks) begin + //$write("[%0t] Wrclk\n", $time); + m_dout <= m_din; + end + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + if (cyc==1) begin + $write(" %x\n",comb_pos_1); + m_din <= 32'hfeed; + end + if (cyc==2) begin + $write(" %x\n",comb_pos_1); + m_din <= 32'he11e; + end + if (cyc==3) begin + m_din <= 32'he22e; + $write(" %x\n",comb_pos_1); + if (m_dout!=32'hfeed) $stop; + end + if (cyc==4) begin + if (m_dout!=32'he11e) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_alw_nosplit.v b/SVIncCompil/Testcases/Verilator/t_alw_nosplit.v new file mode 100644 index 0000000..4d1db19 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_alw_nosplit.v
@@ -0,0 +1,131 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [15:0] m_din; + + // We expect none of these blocks to split. + // Blocks that can split should go in t_alw_split.v instead. + + reg [15:0] b_split_1, b_split_2; + always @ (/*AS*/m_din) begin + b_split_1 = m_din; + b_split_2 = b_split_1; + end + + reg [15:0] c_split_1, c_split_2; + always @ (/*AS*/m_din) begin + c_split_1 = m_din; + c_split_2 = c_split_1; + c_split_1 = ~m_din; + end + + always @ (posedge clk) begin + $write(" foo %x", m_din); + $write(" bar %x\n", m_din); + end + + reg [15:0] e_split_1, e_split_2; + always @ (posedge clk) begin + e_split_1 = m_din; + e_split_2 = e_split_1; + end + + reg [15:0] f_split_1, f_split_2; + always @ (posedge clk) begin + f_split_2 = f_split_1; + f_split_1 = m_din; + end + + reg [15:0] l_split_1, l_split_2; + always @ (posedge clk) begin + l_split_2 <= l_split_1; + l_split_1 <= l_split_2 | m_din; + end + + reg [15:0] z_split_1, z_split_2; + always @ (posedge clk) begin + z_split_1 <= 0; + z_split_1 <= ~m_din; + end + always @ (posedge clk) begin + z_split_2 <= 0; + z_split_2 <= z_split_1; + end + + reg [15:0] h_split_1; + reg [15:0] h_split_2; + reg [15:0] h_foo; + always @ (posedge clk) begin +// $write(" cyc = %x m_din = %x\n", cyc, m_din); + h_foo = m_din; + if (cyc > 2) begin + // This conditional depends on non-primary-input foo. + // Its dependency on foo should not be pruned. As a result, + // the dependencies of h_split_1 and h_split_2 on this + // conditional will also not be pruned, making them all + // weakly connected such that they'll end up in the same graph + // and we can't split. + if (h_foo == 16'h0) begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + else begin + h_split_1 <= m_din; + h_split_2 <= ~m_din; + end + end + else begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + end // always @ (posedge clk) + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + end + if (cyc==1) begin + m_din <= 16'hfeed; + end + if (cyc==4) begin + m_din <= 16'he11e; + if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop; + if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop; + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; + if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; + end + if (cyc==5) begin + m_din <= 16'he22e; + if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop; + if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; + if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; + end + if (cyc==6) begin + m_din <= 16'he33e; + if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop; + if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; + if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; + if (!(z_split_1==16'h1ee1 && z_split_2==16'h0112)) $stop; + end + if (cyc==7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_alw_reorder.v b/SVIncCompil/Testcases/Verilator/t_alw_reorder.v new file mode 100644 index 0000000..7433bfb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_alw_reorder.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [15:0] m_din; + + reg [15:0] v1; + reg [15:0] v2; + reg [15:0] v3; + integer nosplit; + + always @ (posedge clk) begin + // write needed so that V3Dead doesn't kill v0..v3 + $write(" values %x %x %x\n", v1, v2, v3); + + // Locally-set 'nosplit' will prevent the if from splitting + // in splitAlwaysAll(). This whole always block should still be + // intact when we call splitReorderAll() which is the subject + // of this test. + nosplit = cyc; + if (nosplit > 2) begin + /* S1 */ v1 <= 16'h0; + /* S2 */ v1 <= m_din; + /* S3 */ if (m_din == 16'h0) begin + /* X1 */ v2 <= v1; + /* X2 */ v3 <= v2; + end + end + + // We expect to swap S2 and S3, and to swap X1 and X2. + // We can check that this worked by the absense of dly vars + // in the generated output; if the reorder fails (or is disabled) + // we should see dly vars for v1 and v2. + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + if (cyc==7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_alw_split.v b/SVIncCompil/Testcases/Verilator/t_alw_split.v new file mode 100644 index 0000000..f852753 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_alw_split.v
@@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [15:0] m_din; + + // We expect all these blocks should split; + // blocks that don't split should go in t_alw_nosplit.v + + reg [15:0] a_split_1, a_split_2; + always @ (/*AS*/m_din) begin + a_split_1 = m_din; + a_split_2 = m_din; + end + + reg [15:0] d_split_1, d_split_2; + always @ (posedge clk) begin + d_split_1 <= m_din; + d_split_2 <= d_split_1; + d_split_1 <= ~m_din; + end + + reg [15:0] h_split_1; + reg [15:0] h_split_2; + always @ (posedge clk) begin +// $write(" cyc = %x m_din = %x\n", cyc, m_din); + if (cyc > 2) begin + if (m_din == 16'h0) begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + else begin + h_split_1 <= m_din; + h_split_2 <= ~m_din; + end + end + else begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + end + + // (The checker block is an exception, it won't split.) + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + if (cyc==1) begin + m_din <= 16'hfeed; + end + if (cyc==3) begin + end + if (cyc==4) begin + m_din <= 16'he11e; + //$write(" A %x %x\n", a_split_1, a_split_2); + if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop; + if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; + if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; + end + if (cyc==5) begin + m_din <= 16'he22e; + if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop; + if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; + if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; + end + if (cyc==6) begin + m_din <= 16'he33e; + if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop; + if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; + if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop; + end + if (cyc==7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end // always @ (posedge clk) + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_alw_split_rst.v b/SVIncCompil/Testcases/Verilator/t_alw_split_rst.v new file mode 100644 index 0000000..9d2c3fb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_alw_split_rst.v
@@ -0,0 +1,158 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [3:0] in = crc[3:0]; + wire clken = crc[4]; + wire rstn = !(cyc < 20 || (crc[11:8]==0)); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] ff_out; // From test of Test.v + wire [3:0] fg_out; // From test of Test.v + wire [3:0] fh_out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .ff_out (ff_out[3:0]), + .fg_out (fg_out[3:0]), + .fh_out (fh_out[3:0]), + // Inputs + .clk (clk), + .clken (clken), + .rstn (rstn), + .in (in[3:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {52'h0, ff_out, fg_out, fh_out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h77979747fd1b3a5a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test + (/*AUTOARG*/ + // Outputs + ff_out, fg_out, fh_out, + // Inputs + clk, clken, rstn, in + ); + + input clk; + input clken; + input rstn; + + input [3:0] in; + + output reg [3:0] ff_out; + reg [3:0] ff_10; + reg [3:0] ff_11; + reg [3:0] ff_12; + reg [3:0] ff_13; + always @(posedge clk) begin + if ((rstn == 0)) begin + ff_10 <= 0; + ff_11 <= 0; + ff_12 <= 0; + ff_13 <= 0; + end + else begin + ff_10 <= in; + ff_11 <= ff_10; + ff_12 <= ff_11; + ff_13 <= ff_12; + ff_out <= ff_13; + end + end + + output reg [3:0] fg_out; + reg [3:0] fg_10; + reg [3:0] fg_11; + reg [3:0] fg_12; + reg [3:0] fg_13; + always @(posedge clk) begin + if (clken) begin + if ((rstn == 0)) begin + fg_10 <= 0; + fg_11 <= 0; + fg_12 <= 0; + fg_13 <= 0; + end + else begin + fg_10 <= in; + fg_11 <= fg_10; + fg_12 <= fg_11; + fg_13 <= fg_12; + fg_out <= fg_13; + end + end + end + + output reg [3:0] fh_out; + reg [3:0] fh_10; + reg [3:0] fh_11; + reg [3:0] fh_12; + reg [3:0] fh_13; + always @(posedge clk) begin + if ((rstn == 0)) begin + fh_10 <= 0; + fh_11 <= 0; + fh_12 <= 0; + fh_13 <= 0; + end + else begin + if (clken) begin + fh_10 <= in; + fh_11 <= fh_10; + fh_12 <= fh_11; + fh_13[3:1] <= fh_12[3:1]; + fh_13[0] <= fh_12[0]; + fh_out <= fh_13; + end + end + end + + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_alw_splitord.v b/SVIncCompil/Testcases/Verilator/t_alw_splitord.v new file mode 100644 index 0000000..f313689 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_alw_splitord.v
@@ -0,0 +1,151 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [15:0] m_din; + + // OK + reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; + always @ (posedge clk) begin + if (cyc==0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + c_split_1 <= 16'h0; + c_split_2 <= 16'h0; + c_split_3 <= 16'h0; + c_split_4 <= 0; + c_split_5 <= 0; + // End of automatics + end + else begin + c_split_1 <= m_din; + c_split_2 <= c_split_1; + c_split_3 <= c_split_2 & {16{(cyc!=0)}}; + if (cyc==1) begin + c_split_4 <= 16'h4; + c_split_5 <= 16'h5; + end + else begin + c_split_4 <= c_split_3; + c_split_5 <= c_split_4; + end + end + end + + // OK + reg [15:0] d_split_1, d_split_2; + always @ (posedge clk) begin + if (cyc==0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + d_split_1 <= 16'h0; + d_split_2 <= 16'h0; + // End of automatics + end + else begin + d_split_1 <= m_din; + d_split_2 <= d_split_1; + d_split_1 <= ~m_din; + end + end + + // Not OK + always @ (posedge clk) begin + if (cyc==0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + // End of automatics + end + else begin + $write(" foo %x", m_din); + $write(" bar %x\n", m_din); + end + end + + // Not OK + reg [15:0] e_split_1, e_split_2; + always @ (posedge clk) begin + if (cyc==0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + e_split_1 = 16'h0; + e_split_2 = 16'h0; + // End of automatics + end + else begin + e_split_1 = m_din; + e_split_2 = e_split_1; + end + end + + // Not OK + reg [15:0] f_split_1, f_split_2; + always @ (posedge clk) begin + if (cyc==0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + f_split_1 = 16'h0; + f_split_2 = 16'h0; + // End of automatics + end + else begin + f_split_2 = f_split_1; + f_split_1 = m_din; + end + end + + always @ (posedge clk) begin + if (cyc!=0) begin + //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); + cyc<=cyc+1; + if (cyc==1) begin + m_din <= 16'hfeed; + end + if (cyc==3) begin + end + if (cyc==4) begin + m_din <= 16'he11e; + if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; + end + if (cyc==5) begin + m_din <= 16'he22e; + if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; + end + if (cyc==6) begin + m_din <= 16'he33e; + if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop; + if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; + if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; + end + if (cyc==7) begin + m_din <= 16'he44e; + if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop; + end + if (cyc==8) begin + m_din <= 16'he55e; + if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e + && c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_backw_index_bad.v b/SVIncCompil/Testcases/Verilator/t_array_backw_index_bad.v new file mode 100644 index 0000000..8b6f9dd --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_backw_index_bad.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/); + + logic [31:0] array_assign [3:0]; + + logic [31:0] larray_assign [0:3]; + + initial begin + array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + + array_assign[4:3] = '{32'd4, 32'd3}; + array_assign[1:-1] = '{32'd4, 32'd3}; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_compare.v b/SVIncCompil/Testcases/Verilator/t_array_compare.v new file mode 100644 index 0000000..d944648 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_compare.v
@@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Andrew Bardsley. + +// bug1071 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [3:0] array_1 [2:0]; + reg [3:0] array_2 [2:0]; + reg [3:0] array_3 [3:1]; + + reg [3:0] elem; + + reg array_1_ne_array_2; + reg array_1_eq_array_2; + reg array_1_ne_array_3; + reg array_1_eq_array_3; + + initial begin + array_1[0] = 4'b1000; + array_1[1] = 4'b1000; + array_1[2] = 4'b1000; + + array_2[0] = 4'b1000; + array_2[1] = 4'b1000; + array_2[2] = 4'b1000; + + array_3[1] = 4'b1000; + array_3[2] = 4'b0100; + array_3[3] = 4'b0100; + + array_1_ne_array_2 = array_1 != array_2; // 0 + array_1_eq_array_2 = array_1 == array_2; // 0 + array_1_ne_array_3 = array_1 != array_3; // 1 + array_1_eq_array_3 = array_1 == array_3; // 1 + + //Not legal: array_rxor = ^ array_1; + //Not legal: array_rxnor = ^~ array_1; + //Not legal: array_ror = | array_1; + //Not legal: array_rand = & array_1; + +`ifdef TEST_VERBOSE + $write("array_1_ne_array2==%0d\n", array_1_ne_array_2); + $write("array_1_ne_array3==%0d\n", array_1_ne_array_3); +`endif + + if (array_1_ne_array_2 !== 0) $stop; + if (array_1_eq_array_2 !== 1) $stop; + if (array_1_ne_array_3 !== 1) $stop; + if (array_1_eq_array_3 !== 0) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_interface.v b/SVIncCompil/Testcases/Verilator/t_array_interface.v new file mode 100644 index 0000000..3d8eaa7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_interface.v
@@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. + +interface intf; + logic logic_in_intf; + modport source(output logic_in_intf); + modport sink(input logic_in_intf); +endinterface + +module modify_interface +( +input logic value, +intf.source intf_inst +); +assign intf_inst.logic_in_intf = value; +endmodule + +function integer return_3(); + return 3; +endfunction + +module t +#( + parameter N = 6 +)(); + intf ifs[N-1:0] (); + logic [N-1:0] data; + assign data = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}; + + generate + genvar i; + for (i = 0;i < 3; i++) begin + assign ifs[i].logic_in_intf = data[i]; + end + endgenerate + modify_interface m3 ( + .value(data[return_3()]), + .intf_inst(ifs[return_3()])); + + modify_interface m4 ( + .value(data[4]), + .intf_inst(ifs[4])); + + modify_interface m5 ( + .value(~ifs[4].logic_in_intf), + .intf_inst(ifs[5])); + + generate + genvar j; + for (j = 0;j < N-1; j++) begin + initial begin + if (ifs[j].logic_in_intf != data[j]) $stop; + end + end + endgenerate + + initial begin + if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_list_bad.v b/SVIncCompil/Testcases/Verilator/t_array_list_bad.v new file mode 100644 index 0000000..50f2f00 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_list_bad.v
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +package pkg; + typedef struct packed { + logic t1; + logic t2; + logic t3; + } type_t; +endpackage : pkg + +module t + ( + input logic sys_clk, + input logic sys_rst_n, + input logic sys_ena, + + input pkg::type_t test_in, + output pkg::type_t test_out + ); + + import pkg::*; + + always_ff @(posedge sys_clk or negedge sys_rst_n) begin + if (~sys_rst_n) begin + test_out <= '{'0, '0, '0}; + end + else begin + if(sys_ena) begin + test_out.t1 <= ~test_in.t1; + test_out.t2 <= ~test_in.t2; + test_out.t3 <= ~test_in.t3; + end + else begin + test_out <= '{'0, '0}; /* Inconsistent array list; */ + end + end + end +endmodule: t
diff --git a/SVIncCompil/Testcases/Verilator/t_array_mda.v b/SVIncCompil/Testcases/Verilator/t_array_mda.v new file mode 100644 index 0000000..648c9b3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_mda.v
@@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // msg2946 + int A [7][1], B [8][1]; + int a [1], b [1]; + always_ff @(posedge clk) begin + a <= A[crc[2:0]]; + b <= B[crc[2:0]]; + end + wire [63:0] result = {a[0], b[0]}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + A[0][0] <= 32'h1_0; + A[1][0] <= 32'h1_1; + A[2][0] <= 32'h1_2; + A[3][0] <= 32'h1_3; + A[4][0] <= 32'h1_4; + A[5][0] <= 32'h1_5; + A[6][0] <= 32'h1_6; + B[0][0] <= 32'h2_0; + B[1][0] <= 32'h2_1; + B[2][0] <= 32'h2_2; + B[3][0] <= 32'h2_3; + B[4][0] <= 32'h2_4; + B[5][0] <= 32'h2_5; + B[6][0] <= 32'h2_6; + B[7][0] <= 32'h2_7; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h619f75c3a6d948bd + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_packed_sysfunct.v b/SVIncCompil/Testcases/Verilator/t_array_packed_sysfunct.v new file mode 100644 index 0000000..0393458 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_packed_sysfunct.v
@@ -0,0 +1,169 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + + // parameters for array sizes + localparam WA = 4; + localparam WB = 6; + localparam WC = 8; + + // 2D packed arrays + logic [WA+1:2] [WB+1:2] [WC+1:2] array_bg; // big endian array + /* verilator lint_off LITENDIAN */ + logic [2:WA+1] [2:WB+1] [2:WC+1] array_lt; // little endian array + /* verilator lint_on LITENDIAN */ + + logic [1:0] array_unpk [3:2][1:0]; + + integer cnt = 0; + integer slc = 0; // slice type + integer dim = 0; // dimension + integer wdt = 0; // width + + initial begin + `checkh($dimensions (array_unpk), 3); +`ifndef VCS + `checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009 +`endif + `checkh($bits (array_unpk), 2*2*2); + `checkh($low (array_unpk), 2); + `checkh($high (array_unpk), 3); + `checkh($left (array_unpk), 3); + `checkh($right(array_unpk), 2); + `checkh($increment(array_unpk), 1); + `checkh($size (array_unpk), 2); + end + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + integer slc_next; + + // calculation of dimention sizes + always @ (posedge clk) begin + // slicing type counter + case (cnt[3:2]) + 2'd0 : begin slc_next = 0; end // full array + 2'd1 : begin slc_next = 1; end // single array element + 2'd2 : begin slc_next = 2; end // half array + default: begin slc_next = 0; end + endcase + slc <= slc_next; + // dimension counter + case (cnt[1:0]) + 2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end + 2'd1 : begin dim <= 2; wdt <= WB; end + 2'd2 : begin dim <= 3; wdt <= WC; end + default: begin dim <= 0; wdt <= 0; end + endcase + end + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); +`endif + if (cnt[30:4]==1) begin + // big endian + if (slc==0) begin + // full array + `checkh($dimensions (array_bg), 3); + `checkh($bits (array_bg), WA*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_bg, dim), wdt+1); + `checkh($right (array_bg, dim), 2 ); + `checkh($low (array_bg, dim), 2 ); + `checkh($high (array_bg, dim), wdt+1); + `checkh($increment (array_bg, dim), 1 ); + `checkh($size (array_bg, dim), wdt ); + end + end else if (slc==1) begin + // single array element + `checkh($dimensions (array_bg[2]), 2); + `checkh($bits (array_bg[2]), WB*WC); + if ((dim>=2)&&(dim<=3)) begin + `checkh($left (array_bg[2], dim-1), wdt+1); + `checkh($right (array_bg[2], dim-1), 2 ); + `checkh($low (array_bg[2], dim-1), 2 ); + `checkh($high (array_bg[2], dim-1), wdt+1); + `checkh($increment (array_bg[2], dim-1), 1 ); + `checkh($size (array_bg[2], dim-1), wdt ); + end +`ifndef VERILATOR // Unsupported slices don't maintain size correctly + end else if (slc==2) begin + // half array + `checkh($dimensions (array_bg[WA/2+1:2]), 3); + `checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_bg[WA/2+1:2], dim), wdt+1); + `checkh($right (array_bg[WA/2+1:2], dim), 2 ); + `checkh($low (array_bg[WA/2+1:2], dim), 2 ); + `checkh($high (array_bg[WA/2+1:2], dim), wdt+1); + `checkh($increment (array_bg[WA/2+1:2], dim), 1 ); + `checkh($size (array_bg[WA/2+1:2], dim), wdt); + end +`endif + end + end else if (cnt[30:4]==2) begin + // little endian + if (slc==0) begin + // full array + `checkh($dimensions (array_lt), 3); + `checkh($bits (array_lt), WA*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_lt, dim), 2 ); + `checkh($right (array_lt, dim), wdt+1); + `checkh($low (array_lt, dim), 2 ); + `checkh($high (array_lt, dim), wdt+1); + `checkh($increment (array_lt, dim), -1 ); + `checkh($size (array_lt, dim), wdt ); + end + end else if (slc==1) begin + // single array element + `checkh($dimensions (array_lt[2]), 2); + `checkh($bits (array_lt[2]), WB*WC); + if ((dim>=2)&&(dim<=3)) begin + `checkh($left (array_lt[2], dim-1), 2 ); + `checkh($right (array_lt[2], dim-1), wdt+1); + `checkh($low (array_lt[2], dim-1), 2 ); + `checkh($high (array_lt[2], dim-1), wdt+1); + `checkh($increment (array_lt[2], dim-1), -1 ); + `checkh($size (array_lt[2], dim-1), wdt ); + end +`ifndef VERILATOR // Unsupported slices don't maintain size correctly + end else if (slc==2) begin + // half array + `checkh($dimensions (array_lt[2:WA/2+1]), 3); + `checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_lt[2:WA/2+1], dim), 2 ); + `checkh($right (array_lt[2:WA/2+1], dim), wdt+1); + `checkh($low (array_lt[2:WA/2+1], dim), 2 ); + `checkh($high (array_lt[2:WA/2+1], dim), wdt+1); + `checkh($increment (array_lt[2:WA/2+1], dim), -1 ); + `checkh($size (array_lt[2:WA/2+1], dim), wdt ); + end +`endif + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_packed_write_read.v.bad b/SVIncCompil/Testcases/Verilator/t_array_packed_write_read.v.bad new file mode 100644 index 0000000..5d69078 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_packed_write_read.v.bad
@@ -0,0 +1,147 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // parameters for array sizes + localparam WA = 8; // address dimension size + localparam WB = 8; // bit dimension size + + localparam NO = 10; // number of access events + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] array_bg; // big endian array + /* verilator lint_off LITENDIAN */ + logic [0:WA-1] [0:WB-1] array_lt; // little endian array + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + + // msg926 + logic [3:0][31:0] packedArray; + initial packedArray <= '0; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to 0) + if (cnt[30:2]==0) array_bg <= '0; + else if (cnt[30:2]==1) array_bg <= '0; + else if (cnt[30:2]==2) array_bg <= '0; + else if (cnt[30:2]==3) array_bg <= '0; + else if (cnt[30:2]==4) array_bg <= '0; + else if (cnt[30:2]==5) array_bg <= '0; + else if (cnt[30:2]==6) array_bg <= '0; + else if (cnt[30:2]==7) array_bg <= '0; + else if (cnt[30:2]==8) array_bg <= '0; + else if (cnt[30:2]==9) array_bg <= '0; + end else if (cnt[1:0]==2'd1) begin + // write value to array + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) array_bg <= {WA *WB +0{1'b1}}; + else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==3) array_bg [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==4) array_bg [ 0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==5) array_bg [WA -1 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; + end else if (cnt[1:0]==2'd2) begin + // check array value + if (cnt[30:2]==0) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==2) begin if (array_bg !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==3) begin if (array_bg !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==4) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==5) begin if (array_bg !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==6) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==8) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]==9) begin if (array_bg !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end + end else if (cnt[1:0]==2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'b0}}) $stop(); end + else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to 0) + if (cnt[30:2]==0) array_lt <= '0; + else if (cnt[30:2]==1) array_lt <= '0; + else if (cnt[30:2]==2) array_lt <= '0; + else if (cnt[30:2]==3) array_lt <= '0; + else if (cnt[30:2]==4) array_lt <= '0; + else if (cnt[30:2]==5) array_lt <= '0; + else if (cnt[30:2]==6) array_lt <= '0; + else if (cnt[30:2]==7) array_lt <= '0; + else if (cnt[30:2]==8) array_lt <= '0; + else if (cnt[30:2]==9) array_lt <= '0; + end else if (cnt[1:0]==2'd1) begin + // write value to array + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) array_lt <= {WA *WB +0{1'b1}}; + else if (cnt[30:2]==2) array_lt [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==3) array_lt [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2]==4) array_lt [0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==5) array_lt [ WA -1] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2]==8) array_lt [0 ][0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; + end else if (cnt[1:0]==2'd2) begin + // check array value + if (cnt[30:2]==0) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==2) begin if (array_lt !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==3) begin if (array_lt !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==4) begin if (array_lt !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==5) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==7) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==8) begin if (array_lt !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==9) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_lt); $stop(); end end + end else if (cnt[1:0]==2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'b0}}) $stop(); end + else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_pattern_2d.v b/SVIncCompil/Testcases/Verilator/t_array_pattern_2d.v new file mode 100644 index 0000000..797c9d4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_pattern_2d.v
@@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +//bug991 +module t (/*AUTOARG*/); + + logic [31:0] array_assign [3:0]; + logic [31:0] array_other [3:0]; + + logic [31:0] larray_assign [0:3]; + logic [31:0] larray_other [0:3]; + + initial begin + array_assign[0] = 32'd1; + array_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + + array_other[0] = array_assign[0]+10; + array_other[3:1] = array_assign[3:1]; + if (array_other[0] != 11) $stop; + if (array_other[1] != 2) $stop; + if (array_other[2] != 3) $stop; + if (array_other[3] != 4) $stop; + + larray_assign[0] = 32'd1; + larray_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + + larray_other[0] = larray_assign[0]+10; + larray_other[1:3] = larray_assign[1:3]; + if (larray_other[0] != 11) $stop; + if (larray_other[1] != 4) $stop; + if (larray_other[2] != 3) $stop; + if (larray_other[3] != 2) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_pattern_bad.v b/SVIncCompil/Testcases/Verilator/t_array_pattern_bad.v new file mode 100644 index 0000000..563de8c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_pattern_bad.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +// bug1364 + +module t (/*AUTOARG*/ + // Inputs + clk, res + ); + input clk; + input res; + + typedef struct packed { + logic [3:0] port_num; + } info_t; + + info_t myinfo; + + always_comb + myinfo = '{default: '0, + valids: '1}; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_pattern_packed.v b/SVIncCompil/Testcases/Verilator/t_array_pattern_packed.v new file mode 100644 index 0000000..768f64d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_pattern_packed.v
@@ -0,0 +1,152 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic [1:0] [3:0] [3:0] array_simp; // big endian array + + logic [3:0] array_oned; + + initial begin + array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; + if (array_oned != 4'b0101) $stop; + + array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; + if (array_simp[0] !== 16'h3210) $stop; + + // verilator lint_off WIDTH + array_simp[0] = '{ 3 ,2 ,1, 0 }; + // verilator lint_on WIDTH + if (array_simp[0] !== 16'h3210) $stop; + + // Doesn't seem to work for unpacked arrays in other simulators + //if (array_simp[0] !== 16'h3210) $stop; + //array_simp[0] = '{ 1:4'd3, default:13}; + //if (array_simp[0] !== 16'hDD3D) $stop; + + array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; + if (array_simp !== 32'h3210_1234) $stop; + + // IEEE says '{} allowed only on assignments, not !=, ==. + + // Doesn't seem to work for unpacked arrays in other simulators + array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; + if (array_simp !== 32'h3210_3210) $stop; + + array_simp = '{2{ '{4{ 4'd3 }} }}; + if (array_simp !== 32'h3333_3333) $stop; + + // Not legal in other simulators - replication doesn't match + // However IEEE suggests this is legal. + //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} + + $write("*-* All Finished *-*\n"); + $finish; + end + + //==================== + + // parameters for array sizes + localparam WA = 4; // address dimension size + localparam WB = 4; // bit dimension size + + localparam NO = 11; // number of access events + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] array_bg; // big endian array + /* verilator lint_off LITENDIAN */ + logic [0:WA-1] [0:WB-1] array_lt; // little endian array + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'b0) + if (cnt[30:2]== 0) array_bg <= '0; + else if (cnt[30:2]== 1) array_bg <= '0; + else if (cnt[30:2]== 2) array_bg <= '0; + else if (cnt[30:2]== 3) array_bg <= '0; + else if (cnt[30:2]== 4) array_bg <= '0; + else if (cnt[30:2]== 5) array_bg <= '0; + else if (cnt[30:2]== 6) array_bg <= '0; + else if (cnt[30:2]== 7) array_bg <= '0; + else if (cnt[30:2]== 8) array_bg <= '0; + else if (cnt[30:2]== 9) array_bg <= '0; + else if (cnt[30:2]==10) array_bg <= '0; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]== 0) begin end + else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_bg <= '{default:13}; + else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7}; + else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13}; + else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end + else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'b0) + if (cnt[30:2]== 0) array_lt <= '0; + else if (cnt[30:2]== 1) array_lt <= '0; + else if (cnt[30:2]== 2) array_lt <= '0; + else if (cnt[30:2]== 3) array_lt <= '0; + else if (cnt[30:2]== 4) array_lt <= '0; + else if (cnt[30:2]== 5) array_lt <= '0; + else if (cnt[30:2]== 6) array_lt <= '0; + else if (cnt[30:2]== 7) array_lt <= '0; + else if (cnt[30:2]== 8) array_lt <= '0; + else if (cnt[30:2]== 9) array_lt <= '0; + else if (cnt[30:2]==10) array_lt <= '0; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]== 0) begin end + else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_lt <= '{default:13}; + else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7}; + else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13}; + else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end + else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_pattern_unpacked.v b/SVIncCompil/Testcases/Verilator/t_array_pattern_unpacked.v new file mode 100644 index 0000000..9aea2cb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_pattern_unpacked.v
@@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/); + + logic [3:0] array_simp [1:0] [3:0]; // big endian array + + initial begin + array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; + if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop; + + // verilator lint_off WIDTH + array_simp[0] = '{ 3 ,2 ,1, 0 }; + // verilator lint_on WIDTH + if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop; + + // Doesn't seem to work for unpacked arrays in other simulators + //array_simp[0] = '{ 1:4'd3, default:13 }; + //if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop; + + array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_1234) $stop; + + // Doesn't seem to work for unpacked arrays in other simulators + array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_3210) $stop; + + array_simp = '{2{ '{4{ 4'd3 }} }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3333_3333) $stop; + + // Not legal in other simulators - replication doesn't match + // However IEEE suggests this is legal. + //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_query.v b/SVIncCompil/Testcases/Verilator/t_array_query.v new file mode 100644 index 0000000..741787c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_query.v
@@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: System Verilog test of array querying functions. +// +// This code instantiates a module that calls the various array querying +// functions. +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty. + +// Contributed 2012 by Jeremy Bennett, Embecosm. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire a = clk; + wire b = 1'b0; + reg c; + + array_test array_test_i (/*AUTOINST*/ + // Inputs + .clk (clk)); + +endmodule + + +// Check the array sizing functions work correctly. +module array_test + + #( parameter + LEFT = 5, + RIGHT = 55) + + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off LITENDIAN + reg [7:0] a [LEFT:RIGHT]; + // verilator lint_on LITENDIAN + + typedef reg [7:0] r_t; + + integer l; + integer r; + integer s; + + always @(posedge clk) begin + l = $left (a); + r = $right (a); + s = $size (a); + +`ifdef TEST_VERBOSE + $write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); +`endif + + if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; + if ($left(r_t)!=7 || $right(r_t)!=0 || $size(r_t)!=8 || $bits(r_t) !=8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_rev.v b/SVIncCompil/Testcases/Verilator/t_array_rev.v new file mode 100644 index 0000000..f9b4a94 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_rev.v
@@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Geoff Barrett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc=0; + // verilator lint_off LITENDIAN + logic arrd [0:1] = '{ 1'b1, 1'b0 }; + // verilator lint_on LITENDIAN + logic y0, y1; + logic localbkw [1:0]; + + arr_rev arr_rev_u ( + .arrbkw (arrd), + .y0(y0), + .y1(y1) + ); + + always @ (posedge clk) begin + if (arrd[0] != 1'b1) $stop; + if (arrd[1] != 1'b0) $stop; + + localbkw = arrd; +`ifdef TEST_VERBOSE + $write("localbkw[0]=%b\n", localbkw[0]); + $write("localbkw[1]=%b\n", localbkw[1]); +`endif + if (localbkw[0] != 1'b0) $stop; + if (localbkw[1] != 1'b1) $stop; + +`ifdef TEST_VERBOSE + $write("y0=%b\n", y0); + $write("y1=%b\n", y1); +`endif + if (y0 != 1'b0) $stop; + if (y1 != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module arr_rev + ( + input var logic arrbkw [1:0], + output var logic y0, + output var logic y1 + ); + + always_comb y0 = arrbkw[0]; + always_comb y1 = arrbkw[1]; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_array_type_methods.v b/SVIncCompil/Testcases/Verilator/t_array_type_methods.v new file mode 100644 index 0000000..0af06c8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_array_type_methods.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + logic [2:0] foo [1:0]; + initial begin + foo[0] = 3'b101; + foo[1] = 3'b011; + + `checkh(foo.or, 3'b111); + `checkh(foo.and, 3'b001); + `checkh(foo.xor, 3'b110); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_arraysel_wide.v b/SVIncCompil/Testcases/Verilator/t_arraysel_wide.v new file mode 100644 index 0000000..f00f68a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_arraysel_wide.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + nnext, + // Inputs + inibble, onibble + ); + + input [3:0] inibble; + input [106:0] onibble; + + output reg [3:0] nnext [0:7]; + + // verilator lint_off WIDTH + wire [2:0] selline = (onibble >>> 102) & 7; + // verilator lint_on WIDTH + + always_comb begin + for (integer i=0; i<8; i=i+1) begin + nnext[i] = '0; + end + nnext[selline] = inibble; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_basic.v b/SVIncCompil/Testcases/Verilator/t_assert_basic.v new file mode 100644 index 0000000..3de5037 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_basic.v
@@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg toggle; + + integer cyc; initial cyc=1; + wire [7:0] cyc_copy = cyc[7:0]; + + always @ (negedge clk) begin + AssertionFalse1: assert (cyc<100); + assert (!(cyc==5) || toggle); + // FIX cover {cyc==3 || cyc==4}; + // FIX cover {cyc==9} report "DefaultClock,expect=1"; + // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 + if (cyc==9) begin +`ifdef FAILING_ASSERTIONS + assert (0) else $info; + assert (0) else $info("Info message"); + assume (0) else $info("Info message from failing assumption"); + assert (0) else $info("Info message, cyc=%d", cyc); + InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); + InErrorBlock: assert (0) else $error("Error...."); + assert (0) else $fatal(1,"Fatal...."); +`endif + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_casez.v b/SVIncCompil/Testcases/Verilator/t_assert_casez.v new file mode 100644 index 0000000..760b628 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_casez.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder + +module t; + + reg [1:0] value; + + initial begin + value = 2'b00; + unique casez (value) + 2'b00 : ; + 2'b01 : ; + 2'b1? : ; + endcase + value = 2'b11; + unique casez (value) + 2'b00 : ; + 2'b01 : ; + 2'b1? : ; + endcase + unique casez (1'b1) + default: ; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_comp.v b/SVIncCompil/Testcases/Verilator/t_assert_comp.v new file mode 100644 index 0000000..d51f679 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_comp.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + if (0) begin + $info("User compile-time info"); + $warning("User compile-time warning"); + $error("User compile-time error"); + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_comp_bad.v b/SVIncCompil/Testcases/Verilator/t_assert_comp_bad.v new file mode 100644 index 0000000..028175b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_comp_bad.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + if (1) begin + $info("User compile-time info"); + $warning("User compile-time warning"); + $warning(1); // Check can convert arguments to format + $error("User compile-time error"); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_cover.v b/SVIncCompil/Testcases/Verilator/t_assert_cover.v new file mode 100644 index 0000000..587dc0b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_cover.v
@@ -0,0 +1,135 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg toggle; + integer cyc; initial cyc=1; + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==9) begin + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module Test + ( + input clk, + input toggle, + input [31:0] cyc + ); + + // Simple cover + cover property (@(posedge clk) cyc==3); + + // With statement, in generate + generate if (1) begin + cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4"); + end + endgenerate + + // Labeled cover + cyc_eq_5: + cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); + + // Using default clock + default clocking @(posedge clk); endclocking + cover property (cyc==6) $display("*COVER: Cyc==6"); + + // Disable statement + // Note () after disable are required + cover property (@(posedge clk) disable iff (toggle) cyc==8) + $display("*COVER: Cyc==8"); + cover property (@(posedge clk) disable iff (!toggle) cyc==8) + $stop; + + // Innediate assert + labeled_imas: assert #0 (1); + assert final (1); + + //============================================================ + // Using a macro and generate + wire reset = (cyc < 2); + +`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn)) + + genvar i; + generate + for (i=0; i<32; i=i+1) + begin: cycval + CycCover_i: `covclk( cyc[i] ); + end + endgenerate + +`ifndef verilator // Unsupported + //============================================================ + // Using a more complicated property + property C1; + @(posedge clk) + disable iff (!toggle) + cyc==5; + endproperty + cover property (C1) $display("*COVER: Cyc==5"); + + // Using covergroup + // Note a covergroup is really inheritance of a special system "covergroup" class. + covergroup counter1 @ (posedge cyc); + // Automatic methods: stop(), start(), sample(), set_inst_name() + + // Each bin value must be <= 32 bits. Strange. + cyc_value : coverpoint cyc { + } + + cyc_bined : coverpoint cyc { + bins zero = {0}; + bins low = {1,5}; + // Note 5 is also in the bin above. Only the first bin matching is counted. + bins mid = {[5:$]}; + // illegal_bins // Has precidence over "first matching bin", creates assertion + // ignore_bins // Not counted, and not part of total + } + toggle : coverpoint (toggle) { + bins off = {0}; + bins on = {1}; + } + cyc5 : coverpoint (cyc==5) { + bins five = {1}; + } + + // option.at_least = {number}; // Default 1 - Hits to be considered covered + // option.auto_bin_max = {number}; // Default 64 + // option.comment = {string} + // option.goal = {number}; // Default 90% + // option.name = {string} + // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) + // option.weight = {number}; // Default 1 + + // CROSS + value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n> + cross cyc_value, toggle; + endgroup + counter1 c1 = new(); +`endif + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_dup_bad.v b/SVIncCompil/Testcases/Verilator/t_assert_dup_bad.v new file mode 100644 index 0000000..6edaa22 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_dup_bad.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc = 0; + + covlabel: + cover property (@(posedge clk) cyc==5); + covlabel: // Error: Duplicate block_identifier + cover property (@(posedge clk) cyc==5); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_elab.v b/SVIncCompil/Testcases/Verilator/t_assert_elab.v new file mode 100644 index 0000000..98283bb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_elab.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. + +module t; + localparam str = "string"; + function logic checkParameter(input logic [8:0] N); + $display("x is %d.", N); + if (N == 1) + return 0; + $fatal(1, "Parameter %d is invalid...%s and %s", N, str, "constant both work"); + endfunction + +`ifdef FAILING_ASSERTIONS + localparam x = checkParameter(5); +`else + localparam x = checkParameter(1); +`endif + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_property.v b/SVIncCompil/Testcases/Verilator/t_assert_property.v new file mode 100644 index 0000000..32f225a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_property.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .cyc (cyc[31:0])); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module Test + ( + input clk, + input [31:0] cyc + ); + +`ifdef FAIL_ASSERT_1 + assert property (@(posedge clk) cyc==3) + else $display("cyc != 3, cyc == %0d", cyc); +`endif + +`ifdef FAIL_ASSERT_2 + assert property (@(posedge clk) cyc!=3); +`endif + + assert property (@(posedge clk) cyc < 100); + + restrict property (@(posedge clk) cyc==1); // Ignored in simulators + +// Unclocked is not supported: +// assert property (cyc != 6); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_question.v b/SVIncCompil/Testcases/Verilator/t_assert_question.v new file mode 100644 index 0000000..c725845 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_question.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder + +module t (/*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, sel, a, c + ); + + input clk; + input bit [3:0] sel; + input bit [3:0] a; + input bit c; + output bit dout; + + localparam logic DC = 1'b?; + + always_ff @(posedge clk) begin + unique casez(sel) + 4'b0000: dout <= a[0]; + 4'b001?: dout <= a[1]; + {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; + {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; + default: dout <= '0; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assert_synth.v b/SVIncCompil/Testcases/Verilator/t_assert_synth.v new file mode 100644 index 0000000..8506ca1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assert_synth.v
@@ -0,0 +1,101 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg a; initial a = 1'b1; + reg b_fc; initial b_fc = 1'b0; + reg b_pc; initial b_pc = 1'b0; + reg b_oh; initial b_oh = 1'b0; + reg b_oc; initial b_oc = 1'b0; + wire a_l = ~a; + wire b_oc_l = ~b_oc; + + // Note we must insure that full, parallel, etc, only fire during + // edges (not mid-cycle), and must provide a way to turn them off. + // SystemVerilog provides: $asserton and $assertoff. + + // verilator lint_off CASEINCOMPLETE + + always @* begin + // Note not all tools support directives on casez's + case ({a,b_fc}) // synopsys full_case + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default + endcase + priority case ({a,b_fc}) + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default + endcase + end + + always @* begin + case (1'b1) // synopsys full_case parallel_case + a: ; + b_pc: ; + endcase + end + +`ifdef NOT_YET_VERILATOR // Unsupported + // ambit synthesis one_hot "a, b_oh" + // cadence one_cold "a_l, b_oc_l" +`endif + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==2) begin + a <= 1'b0; + b_fc <= 1'b1; + b_pc <= 1'b1; + b_oh <= 1'b1; + b_oc <= 1'b1; + end + if (cyc==3) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==4) begin +`ifdef FAILING_FULL + b_fc <= 1'b1; +`endif +`ifdef FAILING_PARALLEL + b_pc <= 1'b1; +`endif +`ifdef FAILING_OH + b_oh <= 1'b1; +`endif +`ifdef FAILING_OC + b_oc <= 1'b1; +`endif + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_assign_inline.v b/SVIncCompil/Testcases/Verilator/t_assign_inline.v new file mode 100644 index 0000000..5d29871 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_assign_inline.v
@@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Mike Thyer. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + int cycle=0; + + // verilator lint_off UNOPTFLAT + reg [7:0] a_r; + wire [7:0] a_w; + reg [7:0] b_r; + reg [7:0] c_d_r, c_q_r; + + assign a_w = a_r; + + always @(*) begin + a_r = 0; + b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete" + a_r = c_q_r; + c_d_r = c_q_r; + end + + // stimulus + checks + always @(posedge clk) begin + cycle <= cycle+1; + if (cycle==0) begin + c_q_r <= 8'b0; + end + else begin + c_q_r <= c_d_r+1; +`ifdef TEST_VERBOSE + $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same +`endif + end + if (cycle >= 10) begin + if (b_r==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_attr_parenstar.v b/SVIncCompil/Testcases/Verilator/t_attr_parenstar.v new file mode 100644 index 0000000..9b68ff4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_attr_parenstar.v
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + always @(*) begin + if (clk) begin end + end + + always @(* ) begin + if (clk) begin end + end + + // Not legal in some simulators, legal in others +// always @(* /*cmt*/ ) begin +// if (clk) begin end +// end + + // Not legal in some simulators, legal in others +// always @(* // cmt +// ) begin +// if (clk) begin end +// end + + always @ (* + ) begin + if (clk) begin end + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bench_mux4k.v b/SVIncCompil/Testcases/Verilator/t_bench_mux4k.v new file mode 100644 index 0000000..2280e13 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bench_mux4k.v
@@ -0,0 +1,179 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks. +// +// This implements a 4096:1 mux via two stages of 64:1 muxing. + +// change these two parameters to see the speed differences +//`define DATA_WIDTH 12 +//`define MUX2_SIZE 32 +`define DATA_WIDTH 2 +`define MUX2_SIZE 8 + +// if you change these, then the testbench will break +`define ADDR_WIDTH 12 +`define MUX1_SIZE 64 + +// Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v + // End of automatics + + reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai; + reg [`ADDR_WIDTH-1:0] addr; + + // Mux: takes in addr and datai and outputs datao + mux4096 mux4096 (/*AUTOINST*/ + // Outputs + .datao (datao[`DATA_WIDTH-1:0]), + // Inputs + .datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), + .addr (addr[`ADDR_WIDTH-1:0])); + + + // calculate what the answer should be from datai. This is bit + // tricky given the way datai gets sliced. datai is in bit + // planes where all the LSBs are contiguous and then the next bit. + reg [`DATA_WIDTH-1:0] datao_check; + integer j; + always @(datai or addr) begin + for(j=0;j<`DATA_WIDTH;j=j+1) begin + /* verilator lint_off WIDTH */ + datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); + /* verilator lint_on WIDTH */ + end + end + + // Run the test loop. This just increments the address + integer i, result; + always @ (posedge clk) begin + // initial the input data with random values + if (addr == 0) begin + result = 1; + datai = 0; + for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin + /* verilator lint_off WIDTH */ + datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); + /* verilator lint_on WIDTH */ + end + end + + addr <= addr + 1; + if (datao_check != datao) begin + result = 0; + $stop; + end + +`ifdef TEST_VERBOSE + $write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao); +`endif + // only run the first 10 addresses for now + if (addr > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module mux4096 + (input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, + input [`ADDR_WIDTH-1:0] addr, + output [`DATA_WIDTH-1:0] datao + ); + + // DATA_WIDTH instantiations of mux4096_1bit + mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] + (.addr(addr), + .datai(datai), + .datao(datao) + ); +endmodule + +module mux4096_1bit + (input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, + input [`ADDR_WIDTH-1:0] addr, + output datao + ); + + // address decoding + wire [3:0] A = (4'b1) << addr[1:0]; + wire [3:0] B = (4'b1) << addr[3:2]; + wire [3:0] C = (4'b1) << addr[5:4]; + wire [3:0] D = (4'b1) << addr[7:6]; + wire [3:0] E = (4'b1) << addr[9:8]; + wire [3:0] F = (4'b1) << addr[11:10]; + + wire [`MUX2_SIZE-1:0] data0; + + // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 + // first stage of 64:1 muxing + mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0] + (.A(A), + .B(B), + .C(C), + .datai(datai), + .datao(data0)); + + // DATA_WIDTH*MUX2_SIZE instantiations of mux64 + // second stage of 64:1 muxing + mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2 + (.A(D), + .B(E), + .C(F), + .datai(data0), + .datao(datao)); + +endmodule + +module mux64 + #(parameter MUX_SIZE=64) + (input [3:0] A, + input [3:0] B, + input [3:0] C, + input [MUX_SIZE-1:0] datai, + output datao + ); + + wire [63:0] colSelA = { 16{ A[3:0] }}; + wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; + wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; + + wire [MUX_SIZE-1:0] data_bus; + + // Note each of these becomes a separate wire. + //.colSelA(colSelA[MUX_SIZE-1:0]), + //.colSelB(colSelB[MUX_SIZE-1:0]), + //.colSelC(colSelC[MUX_SIZE-1:0]), + + drv drv[MUX_SIZE-1:0] + (.colSelA(colSelA[MUX_SIZE-1:0]), + .colSelB(colSelB[MUX_SIZE-1:0]), + .colSelC(colSelC[MUX_SIZE-1:0]), + .datai(datai), + .datao(data_bus) + ); + + assign datao = |data_bus; + +endmodule + +module drv + (input colSelA, + input colSelB, + input colSelC, + input datai, + output datao + ); + assign datao = colSelC & colSelB & colSelA & datai; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bind.v b/SVIncCompil/Testcases/Verilator/t_bind.v new file mode 100644 index 0000000..5576b3d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bind.v
@@ -0,0 +1,77 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +bit a_finished; +bit b_finished; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + wire [31:0] o; + wire si = 1'b0; + + ExampInst i + (// Outputs + .o (o[31:0]), + // Inputs + .i (1'b0) + /*AUTOINST*/); + + Prog p (/*AUTOINST*/ + // Inputs + .si (si)); + + always @ (posedge clk) begin + if (!a_finished) $stop; + if (!b_finished) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module InstModule ( + output logic [31:0] so, + input si + ); + assign so = {32{si}}; +endmodule + +program Prog (input si); + initial a_finished = 1'b1; +endprogram + +module ExampInst (o,i); + output logic [31:0] o; + input i; + + InstModule instName + (// Outputs + .so (o[31:0]), + // Inputs + .si (i) + /*AUTOINST*/); + + //bind InstModule Prog instProg + // (.si(si)); + + // Note is based on context of caller + bind InstModule Prog instProg + (/*AUTOBIND*/ + .si (si)); + +endmodule + +// Check bind at top level +bind InstModule Prog2 instProg2 + (/*AUTOBIND*/ + .si (si)); + +// Check program declared after bind +program Prog2 (input si); + initial b_finished = 1'b1; +endprogram
diff --git a/SVIncCompil/Testcases/Verilator/t_bind2.v b/SVIncCompil/Testcases/Verilator/t_bind2.v new file mode 100644 index 0000000..b9cc732 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bind2.v
@@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Ed Lander. + +// verilator lint_off WIDTH + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + reg [7:0] p1; + reg [7:0] p2; + reg [7:0] p3; + + initial begin + p1 = 8'h01; + p2 = 8'h02; + p3 = 8'h03; + end + + parameter int param1 = 8'h11; + parameter int param2 = 8'h12; + parameter int param3 = 8'h13; + + targetmod i_targetmod (/*AUTOINST*/ + // Inputs + .clk (clk)); + + //Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod + //param1 not over-riden (as mycheck) (=> 0x31) + //param2 explicitly bound to targetmod value (=> 0x22) + //param3 explicitly bound to top value (=> 0x13) + //p1 implictly bound (.*), takes value from targetmod (=> 0x04) + //p2 explictly bound to targetmod (=> 0x05) + //p3 explictly bound to top (=> 0x03) + + // Alternative unsupported form is i_targetmod + bind targetmod mycheck + #( + .param2(param2), + .param3(param3) + ) + i_mycheck (.p2(p2), .p3(p3), .*); + +endmodule + +module targetmod (input clk); + reg [7:0] p1; + reg [7:0] p2; + reg [7:0] p3; + + parameter int param1 = 8'h21; + parameter int param2 = 8'h22; + parameter int param3 = 8'h23; + + initial begin + p1 = 8'h04; + p2 = 8'h05; + p3 = 8'h06; + end +endmodule + +module mycheck (/*AUTOARG*/ + // Inputs + clk, p1, p2, p3 + ); + + input clk; + input [7:0] p1; + input [7:0] p2; + input [7:0] p3; + + parameter int param1 = 8'h31; + parameter int param2 = 8'h32; + parameter int param3 = 8'h33; + + always @ (posedge clk) begin + `checkh(param1,8'h31); + `checkh(param2,8'h22); + `checkh(param3,8'h23); + `checkh(p1,8'h04); + `checkh(p2,8'h05); + `checkh(p3,8'h06); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bitsel_const_bad.v b/SVIncCompil/Testcases/Verilator/t_bitsel_const_bad.v new file mode 100644 index 0000000..918ba6f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bitsel_const_bad.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Test of select from constant +// +// This tests issue 508, bit select of constant fails +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Note that if we declare "wire [0:0] b", this works just fine. + wire a; + wire b; + + assign b = 1'b0; + assign a = b[0]; // IEEE illegal can't extract scalar + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bitsel_enum.v b/SVIncCompil/Testcases/Verilator/t_bitsel_enum.v new file mode 100644 index 0000000..4e316df --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bitsel_enum.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Jonathon Donaldson. + +module t_bitsel_enum + ( + output out0, + output out1 + ); + + localparam [6:0] CNST_VAL = 7'h22; + + enum logic [6:0] { + ENUM_VAL = 7'h33 + } MyEnum; + + assign out0 = CNST_VAL[0]; + // Not supported by NC-verilog nor VCS, but other simulators do + assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bitsel_slice.v b/SVIncCompil/Testcases/Verilator/t_bitsel_slice.v new file mode 100644 index 0000000..304ec4a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bitsel_slice.v
@@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + logic [2:0] [1:0] in; + always @* in = crc[5:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [1:0] [1:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out/*[1:0][1:0]*/), + // Inputs + .clk (clk), + .in (in/*[2:0][1:0]*/)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out[1],out[0]}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hdc21e42d85441511 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + //bug717 + + input clk; + input logic [2:0][1:0] in; + + output logic [1:0][1:0] out; + + always @(posedge clk) begin + out <= in[2 -: 2]; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bitsel_struct.v b/SVIncCompil/Testcases/Verilator/t_bitsel_struct.v new file mode 100644 index 0000000..f8920d9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bitsel_struct.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test case for struct signal bit selection. +// +// This test is to check that bit selection of multi-dimensional signal inside +// of a struct works. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jie Xu. + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + typedef struct packed { + logic [1:0][15:0] channel; + logic others; + } buss_t; + + buss_t b; + reg [7:0] a; + + initial begin + b = {16'h8765,16'h4321,1'b1}; + a = b.channel[0][8+:8]; + if (a != 8'h43) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bitsel_struct2.v b/SVIncCompil/Testcases/Verilator/t_bitsel_struct2.v new file mode 100644 index 0000000..f399711 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bitsel_struct2.v
@@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/); + + typedef struct packed { + logic [3:2] a; + logic [5:4][3:2] b; + } ab_t; + typedef ab_t [7:6] c_t; // array of structs + typedef struct packed { + c_t [17:16] d; + } e_t; + +`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + + initial begin + e_t e; + `checkh($bits(ab_t),6); + `checkh($bits(c_t),12); + `checkh($bits(e_t),24); + `checkh($bits(e), 24); + `checkh($bits(e.d[17]),12); + `checkh($bits(e.d[16][6]),6); + `checkh($bits(e.d[16][6].b[5]),2); + `checkh($bits(e.d[16][6].b[5][2]), 1); + // + e = 24'b101101010111010110101010; + `checkb(e, 24'b101101010111010110101010); + e.d[17] = 12'b111110011011; + `checkb(e, 24'b111110011011010110101010); + e.d[16][6] = 6'b010101; + `checkb(e, 24'b111110011011010110010101); + e.d[16][6].b[5] = 2'b10; + `checkb(e, 24'b111110011011010110011001); + e.d[16][6].b[5][2] = 1'b1; + // + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bitsel_struct3.v b/SVIncCompil/Testcases/Verilator/t_bitsel_struct3.v new file mode 100644 index 0000000..444b29d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bitsel_struct3.v
@@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test case for struct signal bit selection. +// +// This test is to check that bit selection of multi-dimensional signal inside +// of a packed struct works. Currently +: and -: blow up with packed structs. +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2013 by Jie Xu. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + typedef struct packed { + logic [15:0] channel; + logic [15:0] others; + } buss_t; + + buss_t b; + + reg [7:0] a; + reg [7:0] c; + reg [7:0] d; + + union packed { + logic [31:0] [7:0] idx; + struct packed { + logic [15:0] z, y, x; + logic [25:0] [7:0] r; + } nam; + } gpr; + + reg [14:0] gpr_a; + + initial begin + b = {16'h8765,16'h4321}; + a = b[19:12]; // This works + c = b[8+:8]; // This fails + d = b[11-:8]; // This fails + `checkh(a, 8'h54); + `checkh(c, 8'h43); + `checkh(d, 8'h32); + + gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345; + `checkh (gpr[255:255-14], 15'h091a); + gpr_a = gpr.nam.z[15:1]; + `checkh (gpr_a, 15'h091a); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_bitsel_wire_array_bad.v b/SVIncCompil/Testcases/Verilator/t_bitsel_wire_array_bad.v new file mode 100644 index 0000000..90c0501 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_bitsel_wire_array_bad.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Test of select from constant +// +// This tests issue 509, bit select of constant fails +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // a and b are arrays of length 1. + wire a[0:0]; // Array of nets + wire b[0:0]; + + assign a = 1'b0; // Only net assignment allowed + assign b = a[0]; // Only net assignment allowed + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_blocking.v b/SVIncCompil/Testcases/Verilator/t_blocking.v new file mode 100644 index 0000000..f2df6a6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_blocking.v
@@ -0,0 +1,95 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer _mode; initial _mode=0; + reg [7:0] a; + reg [7:0] b; + reg [7:0] c; + + reg [7:0] mode_d1r; + reg [7:0] mode_d2r; + reg [7:0] mode_d3r; + + // surefire lint_off ITENST + // surefire lint_off STMINI + // surefire lint_off NBAJAM + + always @ (posedge clk) begin // filp-flops with asynchronous reset + if (0) begin + _mode <= 0; + end + else begin + _mode <= _mode + 1; + if (_mode==0) begin + $write("[%0t] t_blocking: Running\n", $time); + a <= 8'd0; + b <= 8'd0; + c <= 8'd0; + end + else if (_mode==1) begin + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd1; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; + end + else if (_mode==2) begin + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd2; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + end + else if (_mode==3) begin + if (a !== 8'd1) $stop; + if (b !== 8'd2) $stop; + if (c !== 8'd1) $stop; + end + else if (_mode==4) begin + if (mode_d3r != 8'd1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + always @ (posedge clk) begin + mode_d3r <= mode_d2r; + mode_d2r <= mode_d1r; + mode_d1r <= _mode[7:0]; + end + + reg [14:10] bits; + // surefire lint_off SEQASS + always @ (posedge clk) begin + if (_mode==1) begin + bits[14:13] <= 2'b11; + bits[12] <= 1'b1; + end + if (_mode==2) begin + bits[11:10] <= 2'b10; + bits[13] <= 0; + end + if (_mode==3) begin + if (bits !== 5'b10110) $stop; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_66bits.v b/SVIncCompil/Testcases/Verilator/t_case_66bits.v new file mode 100644 index 0000000..e138e31 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_66bits.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [65:0] idx /*verilator public*/; initial idx = 1; + + always @(posedge clk) begin + case(idx) + 1: idx = 100; + 100: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: $stop; + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_auto1.v b/SVIncCompil/Testcases/Verilator/t_case_auto1.v new file mode 100644 index 0000000..32ea1d4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_auto1.v
@@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam // synopsys enum En_State + EP_State_IDLE = {3'b000,5'd00}, + EP_State_CMDSHIFT0 = {3'b001,5'd00}, + EP_State_CMDSHIFT13 = {3'b001,5'd13}, + EP_State_CMDSHIFT14 = {3'b001,5'd14}, + EP_State_CMDSHIFT15 = {3'b001,5'd15}, + EP_State_CMDSHIFT16 = {3'b001,5'd16}, + EP_State_DWAIT = {3'b010,5'd00}, + EP_State_DSHIFT0 = {3'b100,5'd00}, + EP_State_DSHIFT1 = {3'b100,5'd01}, + EP_State_DSHIFT15 = {3'b100,5'd15}; + + reg [7:0] /* synopsys enum En_State */ + m_state_xr; // Last command, for debugging + /*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/ + // Beginning of automatic ASCII enum decoding + reg [79:0] m_stateAscii_xr; // Decode of m_state_xr + always @(m_state_xr) begin + case ({m_state_xr}) + EP_State_IDLE: m_stateAscii_xr = "idle "; + EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; + EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; + EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; + EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; + EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; + EP_State_DWAIT: m_stateAscii_xr = "dwait "; + EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; + EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; + EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; + default: m_stateAscii_xr = "%Error "; + endcase + end + // End of automatics + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc==1) begin + m_state_xr <= EP_State_IDLE; + end + if (cyc==2) begin + if (m_stateAscii_xr != "idle ") $stop; + m_state_xr <= EP_State_CMDSHIFT13; + end + if (cyc==3) begin + if (m_stateAscii_xr != "cmdshift13") $stop; + m_state_xr <= EP_State_CMDSHIFT16; + end + if (cyc==4) begin + if (m_stateAscii_xr != "cmdshift16") $stop; + m_state_xr <= EP_State_DWAIT; + end + if (cyc==9) begin + if (m_stateAscii_xr != "dwait ") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_deep.v b/SVIncCompil/Testcases/Verilator/t_case_deep.v new file mode 100644 index 0000000..3e4f9d5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_deep.v
@@ -0,0 +1,341 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [33:0] in = crc[33:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] code; // From test of Test.v + wire [4:0] len; // From test of Test.v + wire next; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .next (next), + .code (code[31:0]), + .len (len[4:0]), + // Inputs + .clk (clk), + .in (in[33:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {26'h0, next, len, code}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h5537fa30d49bf865 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + next, code, len, + // Inputs + clk, in + ); + + input clk; + input [33:0] in; + output next; + output [31:0] code; + output [4:0] len; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [31:0] code; + reg [4:0] len; + reg next; + // End of automatics + +/* +#!/usr/bin/perl -w +srand(5); +my @used; +pat: + for (my $pat=0; 1; ) { + last if $pat > 196; + my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20; + my ($try, $val, $mask); + try: + for ($try=0; ; $try++) { + next pat if $try>50; + $val = 0; + for (my $bit=23; $bit>(23-$len); $bit--) { + my $b = int(rand()*2); + $val |= (1<<$bit) if $b; + } + $mask = (1<<(23-$len+1))-1; + for (my $testval = $val; $testval <= ($val + $mask); $testval ++) { + next try if $used[$testval]; + } + last; + } + my $bits = ""; + my $val2 = 0; + for (my $bit=23; $bit>(23-$len); $bit--) { + my $b = ($val & (1<<$bit)); + $bits .= $b?'1':'0'; + } + for (my $testval = $val; $testval <= ($val + $mask); $testval++) { + $used[$testval]= 1; #printf "U%08x\n", $testval; + } + if ($try<90) { + printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n" + ,$bits.("?"x(24-$len)), 31-$len, $len, $pat); + $pat++; + } +} +*/ + + always @* begin + next = 1'b0; + code = 32'd0; + len = 5'b11111; + casez (in[31:8]) + 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; + 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; + 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; + 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; + 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; + 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; + 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; + 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; + 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; + 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; + 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; + 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; + 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; + 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; + 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; + 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; + 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; + 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; + 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; + 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; + 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; + 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; + 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; + 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; + 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; + 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; + 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; + 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; + 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; + 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; + 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; + 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; + 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; + 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; + 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; + 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; + 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; + 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; + 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; + 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; + 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; + 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; + 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; + 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; + 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; + 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; + 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; + 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; + 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; + 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; + 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; + 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; + 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; + 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; + 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; + 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; + 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; + 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; + 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; + 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; + 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; + 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; + 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; + 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; + 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; + 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; + 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; + 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; + 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; + 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; + 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; + 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; + 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; + 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; + 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; + 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; + 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; + 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; + 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; + 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; + 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; + 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; + 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; + 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; + 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; + 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; + 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; + 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; + 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; + 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; + 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; + 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; + 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; + 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; + 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; + 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; + 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; + 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; + 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; + 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; + 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; + 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; + 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; + 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; + 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; + 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; + 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; + 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; + 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; + 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; + 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; + 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; + 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; + 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; + 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; + 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; + 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; + 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; + 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; + 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; + 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; + 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; + 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; + 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; + 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; + 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; + 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; + 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; + 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; + 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; + 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; + 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; + 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; + 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; + 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; + 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; + 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; + 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; + 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; + 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; + 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; + 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; + 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; + 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; + 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; + 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; + 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; + 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; + 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; + 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; + 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; + 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; + 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; + 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; + 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; + 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; + 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; + 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; + 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; + 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; + 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; + 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; + 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; + 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; + 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; + 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; + 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; + 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; + 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; + 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; + 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; + 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; + 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; + 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; + 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; + 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; + 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; + 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; + 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; + 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; + 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; + 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; + 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; + 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; + 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; + 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; + 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; + 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; + 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; + 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; + 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; + 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; + 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; + 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; + 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; + 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; + 24'b000000??????????????????: begin + casez (in[33:32]) + 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; + 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; + 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; + default: ; + endcase + end + default: ; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_default_bad.v b/SVIncCompil/Testcases/Verilator/t_case_default_bad.v new file mode 100644 index 0000000..882d24c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_default_bad.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + value + ); + input [3:0] value; + always @ (/*AS*/value) begin + case (value) + default: $stop; + 4'd0000: $stop; + default: $stop; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_dupitems.v b/SVIncCompil/Testcases/Verilator/t_case_dupitems.v new file mode 100644 index 0000000..c389a7e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_dupitems.v
@@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [1:0] in = crc[1:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[1:0]), + // Inputs + .in (in[1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {62'h0, out}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'hbb2d9709592f64bd + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + input [1:0] in; + output reg [1:0] out; + always @* begin + // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? + case (in[1:0]) + 2'd0, 2'd1, 2'd2, 2'd3: begin + out = in; + end + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_genx_bad.v b/SVIncCompil/Testcases/Verilator/t_case_genx_bad.v new file mode 100644 index 0000000..b09bea3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_genx_bad.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005-2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + parameter P = 32'b1000; + + generate + case (P) + 32'b0: initial begin end + 32'b1xxx: initial begin end + default: initial begin end + endcase + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_group.v b/SVIncCompil/Testcases/Verilator/t_case_group.v new file mode 100644 index 0000000..32cb99e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_group.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jonathon Donaldson. + +module t + ( + input i_clk, + input [6:0] i_input, + output logic o_output + ); + + always_ff @(posedge i_clk) + // verilator lint_off CASEINCOMPLETE + case (i_input) + 7'(92+2), + 7'(92+3): o_output <= 1'b1; + endcase + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_huge.v b/SVIncCompil/Testcases/Verilator/t_case_huge.v new file mode 100644 index 0000000..4eeaee8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_huge.v
@@ -0,0 +1,209 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [9:0] index; + wire [7:0] index0 = index[7:0] + 8'h0; + wire [7:0] index1 = index[7:0] + 8'h1; + wire [7:0] index2 = index[7:0] + 8'h2; + wire [7:0] index3 = index[7:0] + 8'h3; + wire [7:0] index4 = index[7:0] + 8'h4; + wire [7:0] index5 = index[7:0] + 8'h5; + wire [7:0] index6 = index[7:0] + 8'h6; + wire [7:0] index7 = index[7:0] + 8'h7; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [9:0] outa0; // From s0 of t_case_huge_sub.v + wire [9:0] outa1; // From s1 of t_case_huge_sub.v + wire [9:0] outa2; // From s2 of t_case_huge_sub.v + wire [9:0] outa3; // From s3 of t_case_huge_sub.v + wire [9:0] outa4; // From s4 of t_case_huge_sub.v + wire [9:0] outa5; // From s5 of t_case_huge_sub.v + wire [9:0] outa6; // From s6 of t_case_huge_sub.v + wire [9:0] outa7; // From s7 of t_case_huge_sub.v + wire [1:0] outb0; // From s0 of t_case_huge_sub.v + wire [1:0] outb1; // From s1 of t_case_huge_sub.v + wire [1:0] outb2; // From s2 of t_case_huge_sub.v + wire [1:0] outb3; // From s3 of t_case_huge_sub.v + wire [1:0] outb4; // From s4 of t_case_huge_sub.v + wire [1:0] outb5; // From s5 of t_case_huge_sub.v + wire [1:0] outb6; // From s6 of t_case_huge_sub.v + wire [1:0] outb7; // From s7 of t_case_huge_sub.v + wire outc0; // From s0 of t_case_huge_sub.v + wire outc1; // From s1 of t_case_huge_sub.v + wire outc2; // From s2 of t_case_huge_sub.v + wire outc3; // From s3 of t_case_huge_sub.v + wire outc4; // From s4 of t_case_huge_sub.v + wire outc5; // From s5 of t_case_huge_sub.v + wire outc6; // From s6 of t_case_huge_sub.v + wire outc7; // From s7 of t_case_huge_sub.v + wire [9:0] outq; // From q of t_case_huge_sub4.v + wire [3:0] outr; // From sub3 of t_case_huge_sub3.v + wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v + // End of automatics + + t_case_huge_sub2 sub2 ( + // Outputs + .outa (outsmall[9:0]), + /*AUTOINST*/ + // Inputs + .index (index[9:0])); + + t_case_huge_sub3 sub3 (/*AUTOINST*/ + // Outputs + .outr (outr[3:0]), + // Inputs + .clk (clk), + .index (index[9:0])); + + /* t_case_huge_sub AUTO_TEMPLATE ( + .outa (outa@[]), + .outb (outb@[]), + .outc (outc@[]), + .index (index@[])); + */ + + t_case_huge_sub s0 (/*AUTOINST*/ + // Outputs + .outa (outa0[9:0]), // Templated + .outb (outb0[1:0]), // Templated + .outc (outc0), // Templated + // Inputs + .index (index0[7:0])); // Templated + t_case_huge_sub s1 (/*AUTOINST*/ + // Outputs + .outa (outa1[9:0]), // Templated + .outb (outb1[1:0]), // Templated + .outc (outc1), // Templated + // Inputs + .index (index1[7:0])); // Templated + t_case_huge_sub s2 (/*AUTOINST*/ + // Outputs + .outa (outa2[9:0]), // Templated + .outb (outb2[1:0]), // Templated + .outc (outc2), // Templated + // Inputs + .index (index2[7:0])); // Templated + t_case_huge_sub s3 (/*AUTOINST*/ + // Outputs + .outa (outa3[9:0]), // Templated + .outb (outb3[1:0]), // Templated + .outc (outc3), // Templated + // Inputs + .index (index3[7:0])); // Templated + t_case_huge_sub s4 (/*AUTOINST*/ + // Outputs + .outa (outa4[9:0]), // Templated + .outb (outb4[1:0]), // Templated + .outc (outc4), // Templated + // Inputs + .index (index4[7:0])); // Templated + t_case_huge_sub s5 (/*AUTOINST*/ + // Outputs + .outa (outa5[9:0]), // Templated + .outb (outb5[1:0]), // Templated + .outc (outc5), // Templated + // Inputs + .index (index5[7:0])); // Templated + t_case_huge_sub s6 (/*AUTOINST*/ + // Outputs + .outa (outa6[9:0]), // Templated + .outb (outb6[1:0]), // Templated + .outc (outc6), // Templated + // Inputs + .index (index6[7:0])); // Templated + t_case_huge_sub s7 (/*AUTOINST*/ + // Outputs + .outa (outa7[9:0]), // Templated + .outb (outb7[1:0]), // Templated + .outc (outc7), // Templated + // Inputs + .index (index7[7:0])); // Templated + + t_case_huge_sub4 q (/*AUTOINST*/ + // Outputs + .outq (outq[9:0]), + // Inputs + .index (index[7:0])); + + + integer cyc; initial cyc=1; + initial index = 10'h0; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%x: %x\n",cyc,outr); + //$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1); + if (cyc==1) begin + index <= 10'h236; + end + if (cyc==2) begin + index <= 10'h022; + if (outsmall != 10'h282) $stop; + if (outr != 4'b0) $stop; + if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop; + if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop; + if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop; + if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop; + if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop; + if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop; + if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop; + if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc==3) begin + index <= 10'h165; + if (outsmall != 10'h191) $stop; + if (outr != 4'h5) $stop; + if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop; + if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop; + if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop; + if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop; + if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop; + if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop; + if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc==4) begin + index <= 10'h201; + if (outsmall != 10'h268) $stop; + if (outr != 4'h2) $stop; + if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop; + if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop; + if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop; + if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop; + if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop; + if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop; + if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc==5) begin + index <= 10'h3ff; + if (outr != 4'hd) $stop; + if (outq != 10'h001) $stop; + end + if (cyc==6) begin + index <= 10'h0; + if (outr != 4'hd) $stop; + if (outq != 10'h114) $stop; + end + if (cyc==7) begin + if (outr != 4'h4) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_huge_sub.v b/SVIncCompil/Testcases/Verilator/t_case_huge_sub.v new file mode 100644 index 0000000..c0118f1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_huge_sub.v
@@ -0,0 +1,290 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t_case_huge_sub (/*AUTOARG*/ + // Outputs + outa, outb, outc, + // Inputs + index + ); + + input [7:0] index; + output [9:0] outa; + output [1:0] outb; + output outc; + + // ============================= + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [9:0] outa; + reg [1:0] outb; + reg outc; + // End of automatics + + // ============================= + // Created from perl + // for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); }; + + always @(/*AS*/index) begin + case (index) + 8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end + 8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end + 8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end + 8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end + 8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end + 8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end + 8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end + 8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end + 8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end + 8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end + 8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end + 8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end + 8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end + 8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end + 8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end + 8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end + 8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end + 8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end + 8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end + 8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end + 8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end + 8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end + 8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end + 8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end + 8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end + 8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end + 8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end + 8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end + 8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end + 8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end + 8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end + 8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end + 8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end + 8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end + 8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end + 8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end + 8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end + 8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end + 8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end + 8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end + 8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end + 8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end + 8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end + 8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end + 8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end + 8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end + 8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end + 8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end + 8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end + 8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end + 8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end + 8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end + 8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end + 8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end + 8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end + 8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end + 8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end + 8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end + 8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end + 8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end + 8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end + 8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end + 8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end + 8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end + 8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end + 8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end + 8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end + 8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end + 8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end + 8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end + 8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end + 8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end + 8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end + 8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end + 8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end + 8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end + 8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end + 8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end + 8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end + 8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end + 8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end + 8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end + 8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end + 8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end + 8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end + 8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end + 8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end + 8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end + 8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end + 8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end + 8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end + 8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end + 8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end + 8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end + 8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end + 8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end + 8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end + 8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end + 8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end + 8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end + 8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end + 8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end + 8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end + 8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end + 8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end + 8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end + 8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end + 8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end + 8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end + 8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end + 8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end + 8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end + 8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end + 8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end + 8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end + 8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end + 8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end + 8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end + 8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end + 8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end + 8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end + 8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end + 8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end + 8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end + 8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end + 8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end + 8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end + 8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end + 8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end + 8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end + 8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end + 8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end + 8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end + 8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end + 8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end + 8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end + 8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end + 8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end + 8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end + 8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end + 8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end + 8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end + 8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end + 8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end + 8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end + 8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end + 8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end + 8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end + 8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end + 8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end + 8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end + 8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end + 8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end + 8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end + 8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end + 8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end + 8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end + 8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end + 8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end + 8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end + 8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end + 8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end + 8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end + 8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end + 8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end + 8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end + 8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end + 8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end + 8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end + 8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end + 8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end + 8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end + 8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end + 8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end + 8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end + 8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end + 8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end + 8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end + 8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end + 8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end + 8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end + 8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end + 8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end + 8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end + 8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end + 8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end + 8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end + 8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end + 8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end + 8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end + 8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end + 8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end + 8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end + 8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end + 8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end + 8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end + 8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end + 8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end + 8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end + 8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end + 8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end + 8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end + 8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end + 8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end + 8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end + 8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end + 8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end + 8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end + 8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end + 8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end + 8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end + 8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end + 8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end + 8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end + 8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end + 8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end + 8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end + 8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end + 8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end + 8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end + 8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end + 8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end + 8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end + 8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end + 8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end + 8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end + 8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end + 8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end + 8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end + 8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end + 8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end + 8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end + 8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end + 8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end + 8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end + 8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end + 8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end + 8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end + 8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end + 8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end + 8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end + 8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end + 8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end + 8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end + 8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end + 8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end + 8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end + 8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end + 8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end + 8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end + 8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end + 8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end + 8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end + 8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end + 8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end + 8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_huge_sub2.v b/SVIncCompil/Testcases/Verilator/t_case_huge_sub2.v new file mode 100644 index 0000000..53e2ab1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_huge_sub2.v
@@ -0,0 +1,290 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t_case_huge_sub2 (/*AUTOARG*/ + // Outputs + outa, + // Inputs + index + ); + + input [9:0] index; + output [9:0] outa; + + // ============================= + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [9:0] outa; + // End of automatics + + // ============================= + // Created from perl + // for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); }; + + always @(/*AS*/index) begin + case (index[7:0]) +`ifdef VERILATOR // Harder test + 8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable +`else + 8'h00: begin outa = 10'h0; end +`endif + 8'h01: begin outa = 10'h318; end + 8'h02: begin outa = 10'h29f; end + 8'h03: begin outa = 10'h392; end + 8'h04: begin outa = 10'h1ef; end + 8'h05: begin outa = 10'h06c; end + 8'h06: begin outa = 10'h29f; end + 8'h07: begin outa = 10'h29a; end + 8'h08: begin outa = 10'h3ce; end + 8'h09: begin outa = 10'h37c; end + 8'h0a: begin outa = 10'h058; end + 8'h0b: begin outa = 10'h3b2; end + 8'h0c: begin outa = 10'h36f; end + 8'h0d: begin outa = 10'h2c5; end + 8'h0e: begin outa = 10'h23a; end + 8'h0f: begin outa = 10'h222; end + 8'h10: begin outa = 10'h328; end + 8'h11: begin outa = 10'h3c3; end + 8'h12: begin outa = 10'h12c; end + 8'h13: begin outa = 10'h1d0; end + 8'h14: begin outa = 10'h3ff; end + 8'h15: begin outa = 10'h115; end + 8'h16: begin outa = 10'h3ba; end + 8'h17: begin outa = 10'h3ba; end + 8'h18: begin outa = 10'h10d; end + 8'h19: begin outa = 10'h13b; end + 8'h1a: begin outa = 10'h0a0; end + 8'h1b: begin outa = 10'h264; end + 8'h1c: begin outa = 10'h3a2; end + 8'h1d: begin outa = 10'h07c; end + 8'h1e: begin outa = 10'h291; end + 8'h1f: begin outa = 10'h1d1; end + 8'h20: begin outa = 10'h354; end + 8'h21: begin outa = 10'h0c0; end + 8'h22: begin outa = 10'h191; end + 8'h23: begin outa = 10'h379; end + 8'h24: begin outa = 10'h073; end + 8'h25: begin outa = 10'h2fd; end + 8'h26: begin outa = 10'h2e0; end + 8'h27: begin outa = 10'h337; end + 8'h28: begin outa = 10'h2c7; end + 8'h29: begin outa = 10'h19e; end + 8'h2a: begin outa = 10'h107; end + 8'h2b: begin outa = 10'h06a; end + 8'h2c: begin outa = 10'h1c7; end + 8'h2d: begin outa = 10'h107; end + 8'h2e: begin outa = 10'h0cf; end + 8'h2f: begin outa = 10'h009; end + 8'h30: begin outa = 10'h09d; end + 8'h31: begin outa = 10'h28e; end + 8'h32: begin outa = 10'h010; end + 8'h33: begin outa = 10'h1e0; end + 8'h34: begin outa = 10'h079; end + 8'h35: begin outa = 10'h13e; end + 8'h36: begin outa = 10'h282; end + 8'h37: begin outa = 10'h21c; end + 8'h38: begin outa = 10'h148; end + 8'h39: begin outa = 10'h3c0; end + 8'h3a: begin outa = 10'h176; end + 8'h3b: begin outa = 10'h3fc; end + 8'h3c: begin outa = 10'h295; end + 8'h3d: begin outa = 10'h113; end + 8'h3e: begin outa = 10'h354; end + 8'h3f: begin outa = 10'h0db; end + 8'h40: begin outa = 10'h238; end + 8'h41: begin outa = 10'h12b; end + 8'h42: begin outa = 10'h1dc; end + 8'h43: begin outa = 10'h137; end + 8'h44: begin outa = 10'h1e2; end + 8'h45: begin outa = 10'h3d5; end + 8'h46: begin outa = 10'h30c; end + 8'h47: begin outa = 10'h298; end + 8'h48: begin outa = 10'h080; end + 8'h49: begin outa = 10'h35a; end + 8'h4a: begin outa = 10'h01b; end + 8'h4b: begin outa = 10'h0a3; end + 8'h4c: begin outa = 10'h0b3; end + 8'h4d: begin outa = 10'h17a; end + 8'h4e: begin outa = 10'h3ae; end + 8'h4f: begin outa = 10'h078; end + 8'h50: begin outa = 10'h322; end + 8'h51: begin outa = 10'h213; end + 8'h52: begin outa = 10'h11a; end + 8'h53: begin outa = 10'h1a7; end + 8'h54: begin outa = 10'h35a; end + 8'h55: begin outa = 10'h233; end + 8'h56: begin outa = 10'h01d; end + 8'h57: begin outa = 10'h2d5; end + 8'h58: begin outa = 10'h1a0; end + 8'h59: begin outa = 10'h3d0; end + 8'h5a: begin outa = 10'h181; end + 8'h5b: begin outa = 10'h219; end + 8'h5c: begin outa = 10'h26a; end + 8'h5d: begin outa = 10'h050; end + 8'h5e: begin outa = 10'h189; end + 8'h5f: begin outa = 10'h1eb; end + 8'h60: begin outa = 10'h224; end + 8'h61: begin outa = 10'h2fe; end + 8'h62: begin outa = 10'h0ae; end + 8'h63: begin outa = 10'h1cd; end + 8'h64: begin outa = 10'h273; end + 8'h65: begin outa = 10'h268; end + 8'h66: begin outa = 10'h111; end + 8'h67: begin outa = 10'h1f9; end + 8'h68: begin outa = 10'h232; end + 8'h69: begin outa = 10'h255; end + 8'h6a: begin outa = 10'h34c; end + 8'h6b: begin outa = 10'h049; end + 8'h6c: begin outa = 10'h197; end + 8'h6d: begin outa = 10'h0fe; end + 8'h6e: begin outa = 10'h253; end + 8'h6f: begin outa = 10'h2de; end + 8'h70: begin outa = 10'h13b; end + 8'h71: begin outa = 10'h040; end + 8'h72: begin outa = 10'h0b4; end + 8'h73: begin outa = 10'h233; end + 8'h74: begin outa = 10'h198; end + 8'h75: begin outa = 10'h018; end + 8'h76: begin outa = 10'h2f7; end + 8'h77: begin outa = 10'h134; end + 8'h78: begin outa = 10'h1ca; end + 8'h79: begin outa = 10'h286; end + 8'h7a: begin outa = 10'h0e6; end + 8'h7b: begin outa = 10'h064; end + 8'h7c: begin outa = 10'h257; end + 8'h7d: begin outa = 10'h31a; end + 8'h7e: begin outa = 10'h247; end + 8'h7f: begin outa = 10'h299; end + 8'h80: begin outa = 10'h02c; end + 8'h81: begin outa = 10'h2bb; end + 8'h82: begin outa = 10'h180; end + 8'h83: begin outa = 10'h245; end + 8'h84: begin outa = 10'h0da; end + 8'h85: begin outa = 10'h367; end + 8'h86: begin outa = 10'h304; end + 8'h87: begin outa = 10'h38b; end + 8'h88: begin outa = 10'h09f; end + 8'h89: begin outa = 10'h1f0; end + 8'h8a: begin outa = 10'h281; end + 8'h8b: begin outa = 10'h019; end + 8'h8c: begin outa = 10'h1f2; end + 8'h8d: begin outa = 10'h0b1; end + 8'h8e: begin outa = 10'h058; end + 8'h8f: begin outa = 10'h39b; end + 8'h90: begin outa = 10'h2ec; end + 8'h91: begin outa = 10'h250; end + 8'h92: begin outa = 10'h3f4; end + 8'h93: begin outa = 10'h057; end + 8'h94: begin outa = 10'h18f; end + 8'h95: begin outa = 10'h105; end + 8'h96: begin outa = 10'h1ae; end + 8'h97: begin outa = 10'h04e; end + 8'h98: begin outa = 10'h240; end + 8'h99: begin outa = 10'h3e4; end + 8'h9a: begin outa = 10'h3c6; end + 8'h9b: begin outa = 10'h109; end + 8'h9c: begin outa = 10'h073; end + 8'h9d: begin outa = 10'h19f; end + 8'h9e: begin outa = 10'h3b8; end + 8'h9f: begin outa = 10'h00e; end + 8'ha0: begin outa = 10'h1b3; end + 8'ha1: begin outa = 10'h2bd; end + 8'ha2: begin outa = 10'h324; end + 8'ha3: begin outa = 10'h343; end + 8'ha4: begin outa = 10'h1c9; end + 8'ha5: begin outa = 10'h185; end + 8'ha6: begin outa = 10'h37a; end + 8'ha7: begin outa = 10'h0e0; end + 8'ha8: begin outa = 10'h0a3; end + 8'ha9: begin outa = 10'h019; end + 8'haa: begin outa = 10'h099; end + 8'hab: begin outa = 10'h376; end + 8'hac: begin outa = 10'h077; end + 8'had: begin outa = 10'h2b1; end + 8'hae: begin outa = 10'h27f; end + 8'haf: begin outa = 10'h265; end + 8'hb0: begin outa = 10'h156; end + 8'hb1: begin outa = 10'h1ce; end + 8'hb2: begin outa = 10'h008; end + 8'hb3: begin outa = 10'h12e; end + 8'hb4: begin outa = 10'h199; end + 8'hb5: begin outa = 10'h330; end + 8'hb6: begin outa = 10'h1ab; end + 8'hb7: begin outa = 10'h3bd; end + 8'hb8: begin outa = 10'h0ca; end + 8'hb9: begin outa = 10'h367; end + 8'hba: begin outa = 10'h334; end + 8'hbb: begin outa = 10'h040; end + 8'hbc: begin outa = 10'h1a7; end + 8'hbd: begin outa = 10'h036; end + 8'hbe: begin outa = 10'h223; end + 8'hbf: begin outa = 10'h075; end + 8'hc0: begin outa = 10'h3c4; end + 8'hc1: begin outa = 10'h2cc; end + 8'hc2: begin outa = 10'h123; end + 8'hc3: begin outa = 10'h3fd; end + 8'hc4: begin outa = 10'h11e; end + 8'hc5: begin outa = 10'h27c; end + 8'hc6: begin outa = 10'h1e2; end + 8'hc7: begin outa = 10'h377; end + 8'hc8: begin outa = 10'h33a; end + 8'hc9: begin outa = 10'h32d; end + 8'hca: begin outa = 10'h014; end + 8'hcb: begin outa = 10'h332; end + 8'hcc: begin outa = 10'h359; end + 8'hcd: begin outa = 10'h0a4; end + 8'hce: begin outa = 10'h348; end + 8'hcf: begin outa = 10'h04b; end + 8'hd0: begin outa = 10'h147; end + 8'hd1: begin outa = 10'h026; end + 8'hd2: begin outa = 10'h103; end + 8'hd3: begin outa = 10'h106; end + 8'hd4: begin outa = 10'h35a; end + 8'hd5: begin outa = 10'h254; end + 8'hd6: begin outa = 10'h0cd; end + 8'hd7: begin outa = 10'h17c; end + 8'hd8: begin outa = 10'h37e; end + 8'hd9: begin outa = 10'h0a9; end + 8'hda: begin outa = 10'h0fe; end + 8'hdb: begin outa = 10'h3c0; end + 8'hdc: begin outa = 10'h1d9; end + 8'hdd: begin outa = 10'h10e; end + 8'hde: begin outa = 10'h394; end + 8'hdf: begin outa = 10'h316; end + 8'he0: begin outa = 10'h05b; end + 8'he1: begin outa = 10'h126; end + 8'he2: begin outa = 10'h369; end + 8'he3: begin outa = 10'h291; end + 8'he4: begin outa = 10'h2ca; end + 8'he5: begin outa = 10'h25b; end + 8'he6: begin outa = 10'h106; end + 8'he7: begin outa = 10'h172; end + 8'he8: begin outa = 10'h2f7; end + 8'he9: begin outa = 10'h2d3; end + 8'hea: begin outa = 10'h182; end + 8'heb: begin outa = 10'h327; end + 8'hec: begin outa = 10'h1d0; end + 8'hed: begin outa = 10'h204; end + 8'hee: begin outa = 10'h11f; end + 8'hef: begin outa = 10'h365; end + 8'hf0: begin outa = 10'h2c2; end + 8'hf1: begin outa = 10'h2b5; end + 8'hf2: begin outa = 10'h1f8; end + 8'hf3: begin outa = 10'h2a7; end + 8'hf4: begin outa = 10'h1be; end + 8'hf5: begin outa = 10'h25e; end + 8'hf6: begin outa = 10'h032; end + 8'hf7: begin outa = 10'h2ef; end + 8'hf8: begin outa = 10'h02f; end + 8'hf9: begin outa = 10'h201; end + 8'hfa: begin outa = 10'h054; end + 8'hfb: begin outa = 10'h013; end + 8'hfc: begin outa = 10'h249; end + 8'hfd: begin outa = 10'h09a; end + 8'hfe: begin outa = 10'h012; end + 8'hff: begin outa = 10'h114; end + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_huge_sub3.v b/SVIncCompil/Testcases/Verilator/t_case_huge_sub3.v new file mode 100644 index 0000000..746344f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_huge_sub3.v
@@ -0,0 +1,291 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t_case_huge_sub3 (/*AUTOARG*/ + // Outputs + outr, + // Inputs + clk, index + ); + + input clk; + input [9:0] index; + output [3:0] outr; + + // ============================= + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [3:0] outr; + // End of automatics + + // ============================= + // Created from perl + //for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i, + //rand(256); }; + + // Reset cheating + initial outr = 4'b0; + + always @(posedge clk) begin + case (index[7:0]) + 8'h00: begin outr <= 4'h0; end + 8'h01: begin /*No Change*/ end + 8'h02: begin outr <= outr^index[8:5]^4'ha; end + 8'h03: begin outr <= outr^index[8:5]^4'h4; end + 8'h04: begin outr <= outr^index[8:5]^4'hd; end + 8'h05: begin outr <= outr^index[8:5]^4'h1; end + 8'h06: begin outr <= outr^index[8:5]^4'hf; end + 8'h07: begin outr <= outr^index[8:5]^4'he; end + 8'h08: begin outr <= outr^index[8:5]^4'h0; end + 8'h09: begin outr <= outr^index[8:5]^4'h4; end + 8'h0a: begin outr <= outr^index[8:5]^4'h5; end + 8'h0b: begin outr <= outr^index[8:5]^4'ha; end + 8'h0c: begin outr <= outr^index[8:5]^4'h2; end + 8'h0d: begin outr <= outr^index[8:5]^4'hf; end + 8'h0e: begin outr <= outr^index[8:5]^4'h5; end + 8'h0f: begin outr <= outr^index[8:5]^4'h0; end + 8'h10: begin outr <= outr^index[8:5]^4'h3; end + 8'h11: begin outr <= outr^index[8:5]^4'hb; end + 8'h12: begin outr <= outr^index[8:5]^4'h0; end + 8'h13: begin outr <= outr^index[8:5]^4'hf; end + 8'h14: begin outr <= outr^index[8:5]^4'h3; end + 8'h15: begin outr <= outr^index[8:5]^4'h5; end + 8'h16: begin outr <= outr^index[8:5]^4'h7; end + 8'h17: begin outr <= outr^index[8:5]^4'h2; end + 8'h18: begin outr <= outr^index[8:5]^4'h3; end + 8'h19: begin outr <= outr^index[8:5]^4'hb; end + 8'h1a: begin outr <= outr^index[8:5]^4'h5; end + 8'h1b: begin outr <= outr^index[8:5]^4'h4; end + 8'h1c: begin outr <= outr^index[8:5]^4'h2; end + 8'h1d: begin outr <= outr^index[8:5]^4'hf; end + 8'h1e: begin outr <= outr^index[8:5]^4'h0; end + 8'h1f: begin outr <= outr^index[8:5]^4'h4; end + 8'h20: begin outr <= outr^index[8:5]^4'h6; end + 8'h21: begin outr <= outr^index[8:5]^4'ha; end + 8'h22: begin outr <= outr^index[8:5]^4'h6; end + 8'h23: begin outr <= outr^index[8:5]^4'hb; end + 8'h24: begin outr <= outr^index[8:5]^4'ha; end + 8'h25: begin outr <= outr^index[8:5]^4'he; end + 8'h26: begin outr <= outr^index[8:5]^4'h7; end + 8'h27: begin outr <= outr^index[8:5]^4'ha; end + 8'h28: begin outr <= outr^index[8:5]^4'h3; end + 8'h29: begin outr <= outr^index[8:5]^4'h8; end + 8'h2a: begin outr <= outr^index[8:5]^4'h1; end + 8'h2b: begin outr <= outr^index[8:5]^4'h8; end + 8'h2c: begin outr <= outr^index[8:5]^4'h4; end + 8'h2d: begin outr <= outr^index[8:5]^4'h4; end + 8'h2e: begin outr <= outr^index[8:5]^4'he; end + 8'h2f: begin outr <= outr^index[8:5]^4'h8; end + 8'h30: begin outr <= outr^index[8:5]^4'ha; end + 8'h31: begin outr <= outr^index[8:5]^4'h7; end + 8'h32: begin outr <= outr^index[8:5]^4'h0; end + 8'h33: begin outr <= outr^index[8:5]^4'h3; end + 8'h34: begin outr <= outr^index[8:5]^4'h1; end + 8'h35: begin outr <= outr^index[8:5]^4'h3; end + 8'h36: begin outr <= outr^index[8:5]^4'h4; end + 8'h37: begin outr <= outr^index[8:5]^4'h6; end + 8'h38: begin outr <= outr^index[8:5]^4'h4; end + 8'h39: begin outr <= outr^index[8:5]^4'hb; end + 8'h3a: begin outr <= outr^index[8:5]^4'h7; end + 8'h3b: begin outr <= outr^index[8:5]^4'h1; end + 8'h3c: begin outr <= outr^index[8:5]^4'h2; end + 8'h3d: begin outr <= outr^index[8:5]^4'h0; end + 8'h3e: begin outr <= outr^index[8:5]^4'h2; end + 8'h3f: begin outr <= outr^index[8:5]^4'ha; end + 8'h40: begin outr <= outr^index[8:5]^4'h7; end + 8'h41: begin outr <= outr^index[8:5]^4'h5; end + 8'h42: begin outr <= outr^index[8:5]^4'h5; end + 8'h43: begin outr <= outr^index[8:5]^4'h4; end + 8'h44: begin outr <= outr^index[8:5]^4'h8; end + 8'h45: begin outr <= outr^index[8:5]^4'h5; end + 8'h46: begin outr <= outr^index[8:5]^4'hf; end + 8'h47: begin outr <= outr^index[8:5]^4'h6; end + 8'h48: begin outr <= outr^index[8:5]^4'h7; end + 8'h49: begin outr <= outr^index[8:5]^4'h4; end + 8'h4a: begin outr <= outr^index[8:5]^4'ha; end + 8'h4b: begin outr <= outr^index[8:5]^4'hd; end + 8'h4c: begin outr <= outr^index[8:5]^4'hb; end + 8'h4d: begin outr <= outr^index[8:5]^4'hf; end + 8'h4e: begin outr <= outr^index[8:5]^4'hd; end + 8'h4f: begin outr <= outr^index[8:5]^4'h7; end + 8'h50: begin outr <= outr^index[8:5]^4'h9; end + 8'h51: begin outr <= outr^index[8:5]^4'ha; end + 8'h52: begin outr <= outr^index[8:5]^4'hf; end + 8'h53: begin outr <= outr^index[8:5]^4'h3; end + 8'h54: begin outr <= outr^index[8:5]^4'h1; end + 8'h55: begin outr <= outr^index[8:5]^4'h0; end + 8'h56: begin outr <= outr^index[8:5]^4'h2; end + 8'h57: begin outr <= outr^index[8:5]^4'h9; end + 8'h58: begin outr <= outr^index[8:5]^4'h2; end + 8'h59: begin outr <= outr^index[8:5]^4'h4; end + 8'h5a: begin outr <= outr^index[8:5]^4'hc; end + 8'h5b: begin outr <= outr^index[8:5]^4'hd; end + 8'h5c: begin outr <= outr^index[8:5]^4'h3; end + 8'h5d: begin outr <= outr^index[8:5]^4'hb; end + 8'h5e: begin outr <= outr^index[8:5]^4'hd; end + 8'h5f: begin outr <= outr^index[8:5]^4'h7; end + 8'h60: begin outr <= outr^index[8:5]^4'h7; end + 8'h61: begin outr <= outr^index[8:5]^4'h3; end + 8'h62: begin outr <= outr^index[8:5]^4'h3; end + 8'h63: begin outr <= outr^index[8:5]^4'hb; end + 8'h64: begin outr <= outr^index[8:5]^4'h9; end + 8'h65: begin outr <= outr^index[8:5]^4'h4; end + 8'h66: begin outr <= outr^index[8:5]^4'h3; end + 8'h67: begin outr <= outr^index[8:5]^4'h6; end + 8'h68: begin outr <= outr^index[8:5]^4'h7; end + 8'h69: begin outr <= outr^index[8:5]^4'h7; end + 8'h6a: begin outr <= outr^index[8:5]^4'hf; end + 8'h6b: begin outr <= outr^index[8:5]^4'h6; end + 8'h6c: begin outr <= outr^index[8:5]^4'h8; end + 8'h6d: begin outr <= outr^index[8:5]^4'he; end + 8'h6e: begin outr <= outr^index[8:5]^4'h4; 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diff --git a/SVIncCompil/Testcases/Verilator/t_case_huge_sub4.v b/SVIncCompil/Testcases/Verilator/t_case_huge_sub4.v new file mode 100644 index 0000000..8319955 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_huge_sub4.v
@@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t_case_huge_sub4 (/*AUTOARG*/ + // Outputs + outq, + // Inputs + index + ); + + input [7:0] index; + output [9:0] outq; + + // ============================= + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [9:0] outq; + // End of automatics + + // ============================= + always @(/*AS*/index) begin + case (index) + // default below: no change + 8'h00: begin outq = 10'h001; end + 8'he0: begin outq = 10'h05b; end + 8'he1: begin outq = 10'h126; end + 8'he2: begin outq = 10'h369; end + 8'he3: begin outq = 10'h291; end + 8'he4: begin outq = 10'h2ca; end + 8'he5: begin outq = 10'h25b; end + 8'he6: begin outq = 10'h106; end + 8'he7: begin outq = 10'h172; end + 8'he8: begin outq = 10'h2f7; end + 8'he9: begin outq = 10'h2d3; end + 8'hea: begin outq = 10'h182; end + 8'heb: begin outq = 10'h327; end + 8'hec: begin outq = 10'h1d0; end + 8'hed: begin outq = 10'h204; end + 8'hee: begin outq = 10'h11f; end + 8'hef: begin outq = 10'h365; end + 8'hf0: begin outq = 10'h2c2; end + 8'hf1: begin outq = 10'h2b5; end + 8'hf2: begin outq = 10'h1f8; end + 8'hf3: begin outq = 10'h2a7; end + 8'hf4: begin outq = 10'h1be; end + 8'hf5: begin outq = 10'h25e; end + 8'hf6: begin outq = 10'h032; end + 8'hf7: begin outq = 10'h2ef; end + 8'hf8: begin outq = 10'h02f; end + 8'hf9: begin outq = 10'h201; end + 8'hfa: begin outq = 10'h054; end + 8'hfb: begin outq = 10'h013; end + 8'hfc: begin outq = 10'h249; end + 8'hfd: begin outq = 10'h09a; end + 8'hfe: begin outq = 10'h012; end + 8'hff: begin outq = 10'h114; end + default: ; // No change + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_inside.v b/SVIncCompil/Testcases/Verilator/t_case_inside.v new file mode 100644 index 0000000..20aac26 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_inside.v
@@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + reg out1; + reg [4:0] out2; + sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n",$time, cyc, crc, sum, crc[3:0], out1,out2); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; + if (cyc==0) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); +`define EXPECTED_SUM 64'h10204fa5567c8a4b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + out1, out2, + // Inputs + in + ); + + input [23:0] in; + output reg out1; + output reg [4:0] out2; + + always @* begin + case (in[3:0]) inside + default: {out1,out2} = {1'b0,5'h0F}; // Note not last item + 4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01}; + 4'h4: {out1,out2} = {1'b1,5'h04}; + [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match + 4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08}; + [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_itemwidth.v b/SVIncCompil/Testcases/Verilator/t_case_itemwidth.v new file mode 100644 index 0000000..4828f23 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_itemwidth.v
@@ -0,0 +1,123 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Some inputs we'll set to random values + reg [6:0] addr; + reg [6:0] e0; + reg [5:0] e1; + reg [5:0] e2; + + wire [7:0] data; + reg [2:0] wrapcheck_a; + reg [2:0] wrapcheck_b; + + test test (/*AUTOINST*/ + // Outputs + .data (data[7:0]), + // Inputs + .addr (addr[6:0]), + .e0 (e0[6:0]), + .e1 (e1[5:0]), + .e2 (e2[5:0])); + + always @(/*AS*/addr) begin + case(addr[2:0]) + 3'd0+3'd0: wrapcheck_a = 3'h0; + 3'd0+3'd1: wrapcheck_a = 3'h1; + 3'd0+3'd2: wrapcheck_a = 3'h2; + 3'd0+3'd3: wrapcheck_a = 3'h3; + default: wrapcheck_a = 3'h4; + endcase + + case(addr[2:0]) + 3'd0+0: wrapcheck_b = 3'h0; + 3'd1+1: wrapcheck_b = 3'h1; + 3'd2+2: wrapcheck_b = 3'h2; + 3'd3+3: wrapcheck_b = 3'h3; + default: wrapcheck_b = 3'h4; + endcase + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc==1) begin + addr <= 7'h28; + e0 <= 7'h11; + e1 <= 6'h02; + e2 <= 6'h03; + end + if (cyc==2) begin + addr <= 7'h2b; + if (data != 8'h11) $stop; + end + if (cyc==3) begin + addr <= 7'h2c; + if (data != 8'h03) $stop; + if (wrapcheck_a != 3'h3) $stop; + if (wrapcheck_b != 3'h4) $stop; + end + if (cyc==4) begin + addr <= 7'h0; + if (data != 8'h00) $stop; + if (wrapcheck_a != 3'h4) $stop; + if (wrapcheck_b != 3'h2) $stop; + end + if (cyc==5) begin + if (data != 8'h00) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +/* verilator lint_off WIDTH */ +`define AI 7'h28 + +module test (/*AUTOARG*/ + // Outputs + data, + // Inputs + addr, e0, e1, e2 + ); + + output [7:0] data; + + input [6:0] addr; + input [6:0] e0; + input [5:0] e1, e2; + + reg [7:0] data; + + always @(/*AS*/addr or e0 or e1 or e2) + begin + case (addr) + `AI: data = {e0[6], 1'b0, e0[5:0]}; + `AI+1: data = e1; + `AI+2, + `AI+3: data = e2; + default: data = 0; + endcase + end + +endmodule + +// Local Variables: +// eval:(verilog-read-defines) +// verilog-auto-sense-defines-constant: t +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_case_nest.v b/SVIncCompil/Testcases/Verilator/t_case_nest.v new file mode 100644 index 0000000..cb51c33 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_nest.v
@@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + reg out1; + sub sub (.in(crc[23:0]), .out1(out1)); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1}; + if (cyc==1) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc==90) begin + if (sum !== 64'h2e5cb972eb02b8a0) $stop; + end + else if (cyc==91) begin + end + else if (cyc==92) begin + end + else if (cyc==93) begin + end + else if (cyc==94) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + out1, + // Inputs + in + ); + + input [23:0] in; + output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal + + parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; + + always @* begin + casez (in[17:16]) + 2'b00: casez (in[2:0]) + 3'h0: out1[0] = in[0]^RANDOM[0]; + 3'h1: out1[0] = in[0]^RANDOM[1]; + 3'h2: out1[0] = in[0]^RANDOM[2]; + 3'h3: out1[0] = in[0]^RANDOM[3]; + 3'h4: out1[0] = in[0]^RANDOM[4]; + 3'h5: out1[0] = in[0]^RANDOM[5]; + 3'h6: out1[0] = in[0]^RANDOM[6]; + 3'h7: out1[0] = in[0]^RANDOM[7]; + endcase + 2'b01: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[10]; + 3'h1: out1[0] = RANDOM[11]; + 3'h2: out1[0] = RANDOM[12]; + 3'h3: out1[0] = RANDOM[13]; + 3'h4: out1[0] = RANDOM[14]; + 3'h5: out1[0] = RANDOM[15]; + 3'h6: out1[0] = RANDOM[16]; + 3'h7: out1[0] = RANDOM[17]; + endcase + 2'b1?: casez (in[4]) + 1'b1: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[20]; + 3'h1: out1[0] = RANDOM[21]; + 3'h2: out1[0] = RANDOM[22]; + 3'h3: out1[0] = RANDOM[23]; + 3'h4: out1[0] = RANDOM[24]; + 3'h5: out1[0] = RANDOM[25]; + 3'h6: out1[0] = RANDOM[26]; + 3'h7: out1[0] = RANDOM[27]; + endcase + 1'b0: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[30]; + 3'h1: out1[0] = RANDOM[31]; + 3'h2: out1[0] = RANDOM[32]; + 3'h3: out1[0] = RANDOM[33]; + 3'h4: out1[0] = RANDOM[34]; + 3'h5: out1[0] = RANDOM[35]; + 3'h6: out1[0] = RANDOM[36]; + 3'h7: out1[0] = RANDOM[37]; + endcase + endcase + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_onehot.v b/SVIncCompil/Testcases/Verilator/t_case_onehot.v new file mode 100644 index 0000000..ca3dfff --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_onehot.v
@@ -0,0 +1,95 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [2:0] in = (crc[1:0]==0 ? 3'd0 + : crc[1:0]==0 ? 3'd1 + : crc[1:0]==0 ? 3'd2 : 3'd4); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[2:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h704ca23e2a83e1c5 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. + + input clk; + input [2:0] in; + output reg [31:0] out; + + localparam ST_0 = 0; + localparam ST_1 = 1; + localparam ST_2 = 2; + + always @(posedge clk) begin + case (1'b1) // synopsys parallel_case + in[ST_0]: out <= 32'h1234; + in[ST_1]: out <= 32'h4356; + in[ST_2]: out <= 32'h9874; + default: out <= 32'h1; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_orig.v b/SVIncCompil/Testcases/Verilator/t_case_orig.v new file mode 100644 index 0000000..4acd309 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_orig.v
@@ -0,0 +1,186 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg _ranit; + + reg rnd; + reg [2:0] a; + reg [2:0] b; + reg [31:0] wide; + + // surefire lint_off STMINI + initial _ranit = 0; + + wire sigone1 = 1'b1; + wire sigone2 = 1'b1; + reg ok; + + parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b?? + + // Large case statements should be well optimizable. + reg [2:0] anot; + always @ (/*AS*/a) begin + casez (a) + default: anot = 3'b001; + 3'd0: anot = 3'b111; + 3'd1: anot = 3'b110; + 3'd2: anot = 3'b101; + 3'd3: anot = 3'b101; + 3'd4: anot = 3'b011; + 3'd5: anot = 3'b010; + 3'd6: anot = 3'b001; // Same so folds with 7 + endcase + end + + always @ (posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + rnd <= 1; + $write("[%0t] t_case: Running\n", $time); + // + a = 3'b101; + b = 3'b111; + // verilator lint_off CASEX + casex (a) + default: $stop; + 3'bx1x: $stop; + 3'b100: $stop; + 3'bx01: ; + endcase + casez (a) + default: $stop; + 3'b?1?: $stop; + 3'b100: $stop; + 3'b?01: ; + endcase + casez (a) + default: $stop; + {1'b0, twounkn}: $stop; + {1'b1, twounkn}: ; + endcase + casez (b) + default: $stop; + {1'b0, twounkn}: $stop; + {1'b1, twounkn}: ; +// {1'b0, 2'b??}: $stop; +// {1'b1, 2'b??}: ; + endcase + case(a[0]) + default: ; + endcase + casex(a) + default: ; + 3'b?0?: ; + endcase + // verilator lint_off CASEX + //This is illegal, the default occurs before the statements. + //case(a[0]) + // default: $stop; + // 1'b1: ; + //endcase + // + wide = 32'h12345678; + casez (wide) + default: $stop; + 32'h12345677, + 32'h12345678, + 32'h12345679: ; + endcase + // + ok = 0; + casez ({sigone1,sigone2}) + //2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true... + 2'b10, 2'b01: ; + 2'b00: ; + default: ok=1'b1; + endcase + if (ok !== 1'b1) $stop; + // + + if (rnd) begin + $write(""); + end + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // Check parameters in case statements + parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr. + parameter DSP_REGISTER_V = 6'h03; + + reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl + reg [5:0] reg_addr_2s; // Delayed version of reg_addr + reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases + reg [15:10] f_tmp_2s; // Delayed copy of F + reg p00_2s; + + initial begin + alu_ctl_2s = 3'h1; + reg_addr_2s = 6'h3; + ir_slave_2s= 0; + f_tmp_2s= 0; + casex ({alu_ctl_2s,reg_addr_2s, + ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0], + f_tmp_2s[11:10]}) + default: p00_2s = 1'b0; + {ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1; + endcase + if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused + // + case ({1'b1, 1'b1}) + default: $stop; + {1'b1, p00_2s}: ; + endcase + end + + // Check wide overlapping cases + // surefire lint_off CSEOVR + parameter ANY_STATE = 7'h??; + reg [19:0] foo; + initial begin + foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0}; + casez (foo) + default: $stop; + {1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop; + {1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop; + endcase + end + initial begin + foo = 20'b1010; + casex (foo[3:0]) + default: $stop; + 4'b0xxx, + 4'b100x, + 4'b11xx: $stop; + 4'b1010: ; + endcase + end + initial begin + foo = 20'b1010; + ok = 1'b0; + // Test of RANGE(CONCAT reductions... + casex ({foo[3:2],foo[1:0],foo[3]}) + 5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions + 5'bxx00x: $stop; + 5'bxx01x: $stop; + 5'bxx11x: $stop; + endcase + if (!ok) $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_reducer.v b/SVIncCompil/Testcases/Verilator/t_case_reducer.v new file mode 100644 index 0000000..3067861 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_reducer.v
@@ -0,0 +1,278 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [7:0] operand_a = crc[7:0]; + wire [7:0] operand_b = crc[15:8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [6:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[6:0]), + // Inputs + .clk (clk), + .operand_a (operand_a[7:0]), + .operand_b (operand_b[7:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h8a78c2ec4946ac38 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( + // Inputs + input wire clk, + input wire [7:0] operand_a, // operand a + input wire [7:0] operand_b, // operand b + // Outputs + output wire [6:0] out + ); + + wire [6:0] clz_a; + wire [6:0] clz_b; + + clz u_clz_a + ( + // Inputs + .data_i (operand_a), + .out (clz_a)); + + clz u_clz_b + ( + // Inputs + .data_i (operand_b), + .out (clz_b)); + + assign out = clz_a - clz_b; +`ifdef TEST_VERBOSE + always @(posedge clk) + $display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b); +`endif + +endmodule + +`define def_0000_001x 8'b0000_0010, 8'b0000_0011 + +`define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111 + +`define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011 +`define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111 +`define def_0000_1xxx `def_0000_10xx, `def_0000_11xx + +`define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011 +`define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111 +`define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011 +`define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111 + +`define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011 +`define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111 +`define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011 +`define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111 + +`define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011 +`define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111 +`define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011 +`define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111 + +`define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011 +`define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111 +`define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011 +`define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111 + +`define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011 +`define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111 +`define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011 +`define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111 + +`define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011 +`define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111 +`define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011 +`define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111 + +`define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011 +`define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111 +`define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011 +`define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111 + +`define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011 +`define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111 +`define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011 +`define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111 + +`define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011 +`define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111 +`define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011 +`define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111 + +`define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011 +`define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111 +`define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011 +`define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111 + +`define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011 +`define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111 +`define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011 +`define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111 + +`define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011 +`define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111 +`define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011 +`define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111 + +`define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011 +`define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111 +`define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011 +`define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111 + +`define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011 +`define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111 +`define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011 +`define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111 + +`define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011 +`define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111 +`define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011 +`define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111 + +`define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx +`define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx +`define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx +`define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx +`define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx +`define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx +`define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx + +`define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx +`define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx +`define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx +`define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx +`define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx +`define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx +`define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx +`define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx + +`define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \ + `def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx +`define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx +`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx + + + +module clz( + input wire [7:0] data_i, + output wire [6:0] out +); + + // ----------------------------- + // Reg declarations + // ----------------------------- + + reg [2:0] clz_byte0; + reg [2:0] clz_byte1; + reg [2:0] clz_byte2; + reg [2:0] clz_byte3; + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte0 = 3'b000; + `def_01xx_xxxx : clz_byte0 = 3'b001; + `def_001x_xxxx : clz_byte0 = 3'b010; + `def_0001_xxxx : clz_byte0 = 3'b011; + `def_0000_1xxx : clz_byte0 = 3'b100; + `def_0000_01xx : clz_byte0 = 3'b101; + `def_0000_001x : clz_byte0 = 3'b110; + 8'b0000_0001 : clz_byte0 = 3'b111; + 8'b0000_0000 : clz_byte0 = 3'b111; + default : clz_byte0 = 3'bxxx; + endcase + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte1 = 3'b000; + `def_01xx_xxxx : clz_byte1 = 3'b001; + `def_001x_xxxx : clz_byte1 = 3'b010; + `def_0001_xxxx : clz_byte1 = 3'b011; + `def_0000_1xxx : clz_byte1 = 3'b100; + `def_0000_01xx : clz_byte1 = 3'b101; + `def_0000_001x : clz_byte1 = 3'b110; + 8'b0000_0001 : clz_byte1 = 3'b111; + 8'b0000_0000 : clz_byte1 = 3'b111; + default : clz_byte1 = 3'bxxx; + endcase + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte2 = 3'b000; + `def_01xx_xxxx : clz_byte2 = 3'b001; + `def_001x_xxxx : clz_byte2 = 3'b010; + `def_0001_xxxx : clz_byte2 = 3'b011; + `def_0000_1xxx : clz_byte2 = 3'b100; + `def_0000_01xx : clz_byte2 = 3'b101; + `def_0000_001x : clz_byte2 = 3'b110; + 8'b0000_0001 : clz_byte2 = 3'b111; + 8'b0000_0000 : clz_byte2 = 3'b111; + default : clz_byte2 = 3'bxxx; + endcase + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte3 = 3'b000; + `def_01xx_xxxx : clz_byte3 = 3'b001; + `def_001x_xxxx : clz_byte3 = 3'b010; + `def_0001_xxxx : clz_byte3 = 3'b011; + `def_0000_1xxx : clz_byte3 = 3'b100; + `def_0000_01xx : clz_byte3 = 3'b101; + `def_0000_001x : clz_byte3 = 3'b110; + 8'b0000_0001 : clz_byte3 = 3'b111; + 8'b0000_0000 : clz_byte3 = 3'b111; + default : clz_byte3 = 3'bxxx; + endcase + + assign out = {4'b0000, clz_byte1}; + +endmodule // clz
diff --git a/SVIncCompil/Testcases/Verilator/t_case_wild.v b/SVIncCompil/Testcases/Verilator/t_case_wild.v new file mode 100644 index 0000000..5264c38 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_wild.v
@@ -0,0 +1,95 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + reg out1; + reg [4:0] out2; + sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; + if (cyc==0) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc==90) begin + if (sum !== 64'hf0afc2bfa78277c5) $stop; + end + else if (cyc==91) begin + end + else if (cyc==92) begin + end + else if (cyc==93) begin + end + else if (cyc==94) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + out1, out2, + // Inputs + in + ); + + input [23:0] in; + output reg out1; + output reg [4:0] out2; + + always @* begin + // Test empty cases + casez (in[0]) + endcase + casez (in) + 24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00}; + 24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00}; + 24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01}; + 24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02}; + 24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03}; + 24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04}; + 24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05}; + 24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06}; + 24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07}; + // Same pattern, but reversed to test we work OK. + 24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17}; + 24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16}; + 24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15}; + 24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14}; + 24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13}; + 24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12}; + 24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11}; + 24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10}; + 24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f}; + 24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e}; + 24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d}; + 24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c}; + 24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b}; + 24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a}; + 24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09}; + 24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08}; + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_write1.v b/SVIncCompil/Testcases/Verilator/t_case_write1.v new file mode 100644 index 0000000..c0d1123 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_write1.v
@@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +`include "verilated.v" + +`define STRINGIFY(x) `"x`" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [63:0] crc; + integer fd; + integer fdtmp; + + t_case_write1_tasks tasks (); + + integer cyc; initial cyc=0; + + always @ (posedge clk) begin + $fwrite(fd, "[%0d] crc=%x ", cyc, crc); + tasks.big_case(fd, crc[31:0]); + $fwrite(fd, "\n"); + end + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==1) begin + crc <= 64'h00000000_00000097; + $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"}); + fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w"); + fd <= fdtmp; + end + if (cyc==90) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_write1_tasks.v b/SVIncCompil/Testcases/Verilator/t_case_write1_tasks.v new file mode 100644 index 0000000..0c48442 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_write1_tasks.v
@@ -0,0 +1,3794 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +`include "verilated.v" + +module t_case_write1_tasks (); + + // verilator lint_off WIDTH + // verilator lint_off CASEINCOMPLETE + + parameter STRLEN = 78; + task ozonerab; + input [6:0] rab; + inout [STRLEN*8:1] foobar; + // verilator no_inline_task + begin + case (rab[6:0]) + 7'h00 : foobar = {foobar, " 0"}; + 7'h01 : foobar = {foobar, " 1"}; + 7'h02 : foobar = {foobar, " 2"}; + 7'h03 : foobar = {foobar, " 3"}; + 7'h04 : foobar = {foobar, " 4"}; + 7'h05 : foobar = {foobar, " 5"}; + 7'h06 : foobar = {foobar, " 6"}; + 7'h07 : foobar = {foobar, " 7"}; + 7'h08 : foobar = {foobar, " 8"}; + 7'h09 : foobar = {foobar, " 9"}; + 7'h0a : foobar = {foobar, " 10"}; + 7'h0b : foobar = {foobar, " 11"}; + 7'h0c : foobar = {foobar, " 12"}; + 7'h0d : foobar = {foobar, " 13"}; + 7'h0e : foobar = {foobar, " 14"}; + 7'h0f : foobar = {foobar, " 15"}; + 7'h10 : foobar = {foobar, " 16"}; + 7'h11 : foobar = {foobar, " 17"}; + 7'h12 : foobar = {foobar, " 18"}; + 7'h13 : foobar = {foobar, " 19"}; + 7'h14 : foobar = {foobar, " 20"}; + 7'h15 : foobar = {foobar, " 21"}; + 7'h16 : foobar = {foobar, " 22"}; + 7'h17 : foobar = {foobar, " 23"}; + 7'h18 : foobar = {foobar, " 24"}; + 7'h19 : foobar = {foobar, " 25"}; + 7'h1a : foobar = {foobar, " 26"}; + 7'h1b : foobar = {foobar, " 27"}; + 7'h1c : foobar = {foobar, " 28"}; + 7'h1d : foobar = {foobar, " 29"}; + 7'h1e : foobar = {foobar, " 30"}; + 7'h1f : foobar = {foobar, " 31"}; + 7'h20 : foobar = {foobar, " 32"}; + 7'h21 : foobar = {foobar, " 33"}; + 7'h22 : foobar = {foobar, " 34"}; + 7'h23 : foobar = {foobar, " 35"}; + 7'h24 : foobar = {foobar, " 36"}; + 7'h25 : foobar = {foobar, " 37"}; + 7'h26 : foobar = {foobar, " 38"}; + 7'h27 : foobar = {foobar, " 39"}; + 7'h28 : foobar = {foobar, " 40"}; + 7'h29 : foobar = {foobar, " 41"}; + 7'h2a : foobar = {foobar, " 42"}; + 7'h2b : foobar = {foobar, " 43"}; + 7'h2c : foobar = {foobar, " 44"}; + 7'h2d : foobar = {foobar, " 45"}; + 7'h2e : foobar = {foobar, " 46"}; + 7'h2f : foobar = {foobar, " 47"}; + 7'h30 : foobar = {foobar, " 48"}; + 7'h31 : foobar = {foobar, " 49"}; + 7'h32 : foobar = {foobar, " 50"}; + 7'h33 : foobar = {foobar, " 51"}; + 7'h34 : foobar = {foobar, " 52"}; + 7'h35 : foobar = {foobar, " 53"}; + 7'h36 : foobar = {foobar, " 54"}; + 7'h37 : foobar = {foobar, " 55"}; + 7'h38 : foobar = {foobar, " 56"}; + 7'h39 : foobar = {foobar, " 57"}; + 7'h3a : foobar = {foobar, " 58"}; + 7'h3b : foobar = {foobar, " 59"}; + 7'h3c : foobar = {foobar, " 60"}; + 7'h3d : foobar = {foobar, " 61"}; + 7'h3e : foobar = {foobar, " 62"}; + 7'h3f : foobar = {foobar, " 63"}; + 7'h40 : foobar = {foobar, " 64"}; + 7'h41 : foobar = {foobar, " 65"}; + 7'h42 : foobar = {foobar, " 66"}; + 7'h43 : foobar = {foobar, " 67"}; + 7'h44 : foobar = {foobar, " 68"}; + 7'h45 : foobar = {foobar, " 69"}; + 7'h46 : foobar = {foobar, " 70"}; + 7'h47 : foobar = {foobar, " 71"}; + 7'h48 : foobar = {foobar, " 72"}; + 7'h49 : foobar = {foobar, " 73"}; + 7'h4a : foobar = {foobar, " 74"}; + 7'h4b : foobar = {foobar, " 75"}; + 7'h4c : foobar = {foobar, " 76"}; + 7'h4d : foobar = {foobar, " 77"}; + 7'h4e : foobar = {foobar, " 78"}; + 7'h4f : foobar = {foobar, " 79"}; + 7'h50 : foobar = {foobar, " 80"}; + 7'h51 : foobar = {foobar, " 81"}; + 7'h52 : foobar = {foobar, " 82"}; + 7'h53 : foobar = {foobar, " 83"}; + 7'h54 : foobar = {foobar, " 84"}; + 7'h55 : foobar = {foobar, " 85"}; + 7'h56 : foobar = {foobar, " 86"}; + 7'h57 : foobar = {foobar, " 87"}; + 7'h58 : foobar = {foobar, " 88"}; + 7'h59 : foobar = {foobar, " 89"}; + 7'h5a : foobar = {foobar, " 90"}; + 7'h5b : foobar = {foobar, " 91"}; + 7'h5c : foobar = {foobar, " 92"}; + 7'h5d : foobar = {foobar, " 93"}; + 7'h5e : foobar = {foobar, " 94"}; + 7'h5f : foobar = {foobar, " 95"}; + 7'h60 : foobar = {foobar, " 96"}; + 7'h61 : foobar = {foobar, " 97"}; + 7'h62 : foobar = {foobar, " 98"}; + 7'h63 : foobar = {foobar, " 99"}; + 7'h64 : foobar = {foobar, " 100"}; + 7'h65 : foobar = {foobar, " 101"}; + 7'h66 : foobar = {foobar, " 102"}; + 7'h67 : foobar = {foobar, " 103"}; + 7'h68 : foobar = {foobar, " 104"}; + 7'h69 : foobar = {foobar, " 105"}; + 7'h6a : foobar = {foobar, " 106"}; + 7'h6b : foobar = {foobar, " 107"}; + 7'h6c : foobar = {foobar, " 108"}; + 7'h6d : foobar = {foobar, " 109"}; + 7'h6e : foobar = {foobar, " 110"}; + 7'h6f : foobar = {foobar, " 111"}; + 7'h70 : foobar = {foobar, " 112"}; + 7'h71 : foobar = {foobar, " 113"}; + 7'h72 : foobar = {foobar, " 114"}; + 7'h73 : foobar = {foobar, " 115"}; + 7'h74 : foobar = {foobar, " 116"}; + 7'h75 : foobar = {foobar, " 117"}; + 7'h76 : foobar = {foobar, " 118"}; + 7'h77 : foobar = {foobar, " 119"}; + 7'h78 : foobar = {foobar, " 120"}; + 7'h79 : foobar = {foobar, " 121"}; + 7'h7a : foobar = {foobar, " 122"}; + 7'h7b : foobar = {foobar, " 123"}; + 7'h7c : foobar = {foobar, " 124"}; + 7'h7d : foobar = {foobar, " 125"}; + 7'h7e : foobar = {foobar, " 126"}; + 7'h7f : foobar = {foobar, " 127"}; + default:foobar = {foobar, " 128"}; + endcase + end + + endtask + + task ozonerb; + input [5:0] rb; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (rb[5:0]) + 6'h10, + 6'h17, + 6'h1e, + 6'h1f: foobar = {foobar, " 129"}; + default: ozonerab({1'b1, rb}, foobar); + endcase + end + endtask + + task ozonef3f4_iext; + input [1:0] foo; + input [15:0] im16; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo) + 2'h0 : + begin + skyway({4{im16[15]}}, foobar); + skyway({4{im16[15]}}, foobar); + skyway(im16[15:12], foobar); + skyway(im16[11: 8], foobar); + skyway(im16[ 7: 4], foobar); + skyway(im16[ 3:0], foobar); + foobar = {foobar, " 130"}; + end + 2'h1 : + begin + foobar = {foobar, " 131"}; + skyway(im16[15:12], foobar); + skyway(im16[11: 8], foobar); + skyway(im16[ 7: 4], foobar); + skyway(im16[ 3:0], foobar); + end + 2'h2 : + begin + skyway({4{im16[15]}}, foobar); + skyway({4{im16[15]}}, foobar); + skyway(im16[15:12], foobar); + skyway(im16[11: 8], foobar); + skyway(im16[ 7: 4], foobar); + skyway(im16[ 3:0], foobar); + foobar = {foobar, " 132"}; + end + 2'h3 : + begin + foobar = {foobar, " 133"}; + skyway(im16[15:12], foobar); + skyway(im16[11: 8], foobar); + skyway(im16[ 7: 4], foobar); + skyway(im16[ 3:0], foobar); + end + endcase + end + endtask + + task skyway; + input [ 3:0] hex; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (hex) + 4'h0 : foobar = {foobar, " 134"}; + 4'h1 : foobar = {foobar, " 135"}; + 4'h2 : foobar = {foobar, " 136"}; + 4'h3 : foobar = {foobar, " 137"}; + 4'h4 : foobar = {foobar, " 138"}; + 4'h5 : foobar = {foobar, " 139"}; + 4'h6 : foobar = {foobar, " 140"}; + 4'h7 : foobar = {foobar, " 141"}; + 4'h8 : foobar = {foobar, " 142"}; + 4'h9 : foobar = {foobar, " 143"}; + 4'ha : foobar = {foobar, " 144"}; + 4'hb : foobar = {foobar, " 145"}; + 4'hc : foobar = {foobar, " 146"}; + 4'hd : foobar = {foobar, " 147"}; + 4'he : foobar = {foobar, " 148"}; + 4'hf : foobar = {foobar, " 149"}; + endcase + end + endtask + + task ozonesr; + input [ 15:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[11: 9]) + 3'h0 : foobar = {foobar, " 158"}; + 3'h1 : foobar = {foobar, " 159"}; + 3'h2 : foobar = {foobar, " 160"}; + 3'h3 : foobar = {foobar, " 161"}; + 3'h4 : foobar = {foobar, " 162"}; + 3'h5 : foobar = {foobar, " 163"}; + 3'h6 : foobar = {foobar, " 164"}; + 3'h7 : foobar = {foobar, " 165"}; + endcase + end + endtask + + task ozonejk; + input k; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + if (k) + foobar = {foobar, " 166"}; + else + foobar = {foobar, " 167"}; + end + endtask + + task ozoneae; + input [ 2:0] ae; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (ae) + 3'b000 : foobar = {foobar, " 168"}; + 3'b001 : foobar = {foobar, " 169"}; + 3'b010 : foobar = {foobar, " 170"}; + 3'b011 : foobar = {foobar, " 171"}; + 3'b100 : foobar = {foobar, " 172"}; + 3'b101 : foobar = {foobar, " 173"}; + 3'b110 : foobar = {foobar, " 174"}; + 3'b111 : foobar = {foobar, " 175"}; + endcase + end + endtask + + task ozoneaee; + input [ 2:0] aee; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (aee) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : foobar = {foobar, " 176"}; + 3'b000 : foobar = {foobar, " 177"}; + 3'b010 : foobar = {foobar, " 178"}; + 3'b100 : foobar = {foobar, " 179"}; + 3'b110 : foobar = {foobar, " 180"}; + endcase + end + endtask + + task ozoneape; + input [ 2:0] ape; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (ape) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : foobar = {foobar, " 181"}; + 3'b000 : foobar = {foobar, " 182"}; + 3'b010 : foobar = {foobar, " 183"}; + 3'b100 : foobar = {foobar, " 184"}; + 3'b110 : foobar = {foobar, " 185"}; + endcase + end + endtask + + task ozonef1; + input [ 31:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[24:21]) + 4'h0 : + if (foo[26]) + foobar = {foobar, " 186"}; + else + foobar = {foobar, " 187"}; + 4'h1 : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 188"}; + 2'b01 : foobar = {foobar, " 189"}; + 2'b10 : foobar = {foobar, " 190"}; + 2'b11 : foobar = {foobar, " 191"}; + endcase + 4'h2 : foobar = {foobar, " 192"}; + 4'h3 : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 193"}; + 2'b01 : foobar = {foobar, " 194"}; + 2'b10 : foobar = {foobar, " 195"}; + 2'b11 : foobar = {foobar, " 196"}; + endcase + 4'h4 : + if (foo[26]) + foobar = {foobar, " 197"}; + else + foobar = {foobar, " 198"}; + 4'h5 : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 199"}; + 2'b01 : foobar = {foobar, " 200"}; + 2'b10 : foobar = {foobar, " 201"}; + 2'b11 : foobar = {foobar, " 202"}; + endcase + 4'h6 : foobar = {foobar, " 203"}; + 4'h7 : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 204"}; + 2'b01 : foobar = {foobar, " 205"}; + 2'b10 : foobar = {foobar, " 206"}; + 2'b11 : foobar = {foobar, " 207"}; + endcase + 4'h8 : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 208"}; + 2'b01 : foobar = {foobar, " 209"}; + 2'b10 : foobar = {foobar, " 210"}; + 2'b11 : foobar = {foobar, " 211"}; + endcase + 4'h9 : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 212"}; + 2'b01 : foobar = {foobar, " 213"}; + 2'b10 : foobar = {foobar, " 214"}; + 2'b11 : foobar = {foobar, " 215"}; + endcase + 4'ha : + if (foo[25]) + foobar = {foobar, " 216"}; + else + foobar = {foobar, " 217"}; + 4'hb : + if (foo[25]) + foobar = {foobar, " 218"}; + else + foobar = {foobar, " 219"}; + 4'hc : + if (foo[26]) + foobar = {foobar, " 220"}; + else + foobar = {foobar, " 221"}; + 4'hd : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 222"}; + 2'b01 : foobar = {foobar, " 223"}; + 2'b10 : foobar = {foobar, " 224"}; + 2'b11 : foobar = {foobar, " 225"}; + endcase + 4'he : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 226"}; + 2'b01 : foobar = {foobar, " 227"}; + 2'b10 : foobar = {foobar, " 228"}; + 2'b11 : foobar = {foobar, " 229"}; + endcase + 4'hf : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 230"}; + 2'b01 : foobar = {foobar, " 231"}; + 2'b10 : foobar = {foobar, " 232"}; + 2'b11 : foobar = {foobar, " 233"}; + endcase + endcase + end + endtask + + task ozonef1e; + input [ 31:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[27:21]) + 7'h00: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 234"}; + foobar = {foobar, " 235"}; + end + 7'h01: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 236"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 237"}; + foobar = {foobar, " 238"}; + end + 7'h02: + foobar = {foobar, " 239"}; + 7'h03: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 240"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 241"}; + foobar = {foobar, " 242"}; + end + 7'h04: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 243"}; + foobar = {foobar," 244"}; + end + 7'h05: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 245"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 246"}; + end + 7'h06: + foobar = {foobar, " 247"}; + 7'h07: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 248"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 249"}; + end + 7'h08: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 250"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 251"}; + end + 7'h09: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 252"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 253"}; + end + 7'h0a: + begin + ozoneae(foo[17:15], foobar); + foobar = {foobar," 254"}; + end + 7'h0b: + begin + ozoneae(foo[17:15], foobar); + foobar = {foobar," 255"}; + end + 7'h0c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 256"}; + end + 7'h0d: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 257"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 258"}; + end + 7'h0e: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 259"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 260"}; + end + 7'h0f: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 261"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 262"}; + end + 7'h10: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 263"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 264"}; + foobar = {foobar, " 265"}; + foobar = {foobar, " 266"}; + end + 7'h11: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 267"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 268"}; + foobar = {foobar, " 269"}; + foobar = {foobar, " 270"}; + end + 7'h12: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 271"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 272"}; + foobar = {foobar, " 273"}; + foobar = {foobar, " 274"}; + end + 7'h13: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 275"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 276"}; + foobar = {foobar, " 277"}; + foobar = {foobar, " 278"}; + end + 7'h14: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 279"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 280"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 281"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 282"}; + foobar = {foobar, " 283"}; + foobar = {foobar, " 284"}; + end + 7'h15: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 285"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 286"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 287"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 288"}; + foobar = {foobar, " 289"}; + foobar = {foobar, " 290"}; + end + 7'h16: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 291"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 292"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 293"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 294"}; + foobar = {foobar, " 295"}; + foobar = {foobar, " 296"}; + end + 7'h17: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 297"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 298"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 299"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 300"}; + foobar = {foobar, " 301"}; + foobar = {foobar, " 302"}; + end + 7'h18: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 303"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 304"}; + foobar = {foobar, " 305"}; + foobar = {foobar, " 306"}; + end + 7'h19: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 307"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 308"}; + foobar = {foobar, " 309"}; + foobar = {foobar, " 310"}; + end + 7'h1a: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 311"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 312"}; + foobar = {foobar, " 313"}; + foobar = {foobar, " 314"}; + end + 7'h1b: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 315"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 316"}; + foobar = {foobar, " 317"}; + foobar = {foobar, " 318"}; + end + 7'h1c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 319"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 320"}; + foobar = {foobar, " 321"}; + foobar = {foobar, " 322"}; + end + 7'h1d: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 323"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 324"}; + foobar = {foobar, " 325"}; + foobar = {foobar, " 326"}; + end + 7'h1e: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 327"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 328"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 329"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 330"}; + foobar = {foobar, " 331"}; + foobar = {foobar, " 332"}; + end + 7'h1f: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 333"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 334"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 335"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 336"}; + foobar = {foobar, " 337"}; + foobar = {foobar, " 338"}; + end + 7'h20: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 339"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 340"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 341"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 342"}; + foobar = {foobar, " 343"}; + foobar = {foobar, " 344"}; + end + 7'h21: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 345"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 346"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 347"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 348"}; + foobar = {foobar, " 349"}; + foobar = {foobar, " 350"}; + end + 7'h22: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 351"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 352"}; + foobar = {foobar, " 353"}; + foobar = {foobar, " 354"}; + end + 7'h23: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 355"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 356"}; + foobar = {foobar, " 357"}; + foobar = {foobar, " 358"}; + end + 7'h24: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 359"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 360"}; + foobar = {foobar, " 361"}; + foobar = {foobar, " 362"}; + end + 7'h25: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 363"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 364"}; + foobar = {foobar, " 365"}; + foobar = {foobar, " 366"}; + end + 7'h26: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 367"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 368"}; + foobar = {foobar, " 369"}; + foobar = {foobar, " 370"}; + end + 7'h27: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 371"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 372"}; + foobar = {foobar, " 373"}; + foobar = {foobar, " 374"}; + end + 7'h28: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 375"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 376"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 377"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 378"}; + foobar = {foobar, " 379"}; + foobar = {foobar, " 380"}; + end + 7'h29: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 381"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 382"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 383"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 384"}; + foobar = {foobar, " 385"}; + foobar = {foobar, " 386"}; + end + 7'h2a: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 387"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 388"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 389"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 390"}; + foobar = {foobar, " 391"}; + foobar = {foobar, " 392"}; + end + 7'h2b: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 393"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 394"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 395"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 396"}; + foobar = {foobar, " 397"}; + foobar = {foobar, " 398"}; + end + 7'h2c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 399"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 400"}; + foobar = {foobar, " 401"}; + foobar = {foobar, " 402"}; + end + 7'h2d: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 403"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 404"}; + foobar = {foobar, " 405"}; + foobar = {foobar, " 406"}; + end + 7'h2e: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 407"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 408"}; + foobar = {foobar, " 409"}; + foobar = {foobar, " 410"}; + end + 7'h2f: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 411"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 412"}; + foobar = {foobar, " 413"}; + foobar = {foobar, " 414"}; + end + 7'h30: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 415"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 416"}; + foobar = {foobar, " 417"}; + foobar = {foobar, " 418"}; + end + 7'h31: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 419"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 420"}; + foobar = {foobar, " 421"}; + foobar = {foobar, " 422"}; + end + 7'h32: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 423"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 424"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 425"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 426"}; + foobar = {foobar, " 427"}; + foobar = {foobar, " 428"}; + end + 7'h33: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 429"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 430"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 431"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 432"}; + foobar = {foobar, " 433"}; + foobar = {foobar, " 434"}; + end + 7'h34: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 435"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 436"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 437"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 438"}; + foobar = {foobar, " 439"}; + foobar = {foobar, " 440"}; + end + 7'h35: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 441"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 442"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 443"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 444"}; + foobar = {foobar, " 445"}; + foobar = {foobar, " 446"}; + end + 7'h36: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 447"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 448"}; + foobar = {foobar, " 449"}; + foobar = {foobar, " 450"}; + end + 7'h37: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 451"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 452"}; + foobar = {foobar, " 453"}; + foobar = {foobar, " 454"}; + end + 7'h38: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 455"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 456"}; + foobar = {foobar, " 457"}; + end + 7'h39: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 458"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 459"}; + foobar = {foobar, " 460"}; + end + 7'h3a: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 461"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 462"}; + foobar = {foobar, " 463"}; + end + 7'h3b: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 464"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 465"}; + foobar = {foobar, " 466"}; + end + 7'h3c: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 467"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 468"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 469"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 470"}; + foobar = {foobar, " 471"}; + end + 7'h3d: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 472"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 473"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 474"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 475"}; + foobar = {foobar, " 476"}; + end + 7'h3e: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 477"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 478"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 479"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 480"}; + foobar = {foobar, " 481"}; + end + 7'h3f: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 482"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 483"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 484"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 485"}; + foobar = {foobar, " 486"}; + end + 7'h40: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 487"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 488"}; + foobar = {foobar, " 489"}; + foobar = {foobar, " 490"}; + end + 7'h41: + begin + foobar = {foobar, " 491"}; + foobar = {foobar, " 492"}; + end + 7'h42: + begin + foobar = {foobar, " 493"}; + foobar = {foobar, " 494"}; + end + 7'h43: + begin + foobar = {foobar, " 495"}; + foobar = {foobar, " 496"}; + end + 7'h44: + begin + foobar = {foobar, " 497"}; + foobar = {foobar, " 498"}; + end + 7'h45: + foobar = {foobar, " 499"}; + 7'h46: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 500"}; + foobar = {foobar, " 501"}; + foobar = {foobar, " 502"}; + end + 7'h47: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 503"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 504"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 505"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 506"}; + foobar = {foobar, " 507"}; + foobar = {foobar, " 508"}; + end + 7'h48: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 509"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 510"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 511"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 512"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 513"}; + end + 7'h49: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 514"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 515"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 516"}; + end + 7'h4a: + foobar = {foobar," 517"}; + 7'h4b: + foobar = {foobar, " 518"}; + 7'h4c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 519"}; + foobar = {foobar, " 520"}; + foobar = {foobar, " 521"}; + end + 7'h4d: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 522"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 523"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 524"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 525"}; + foobar = {foobar, " 526"}; + foobar = {foobar, " 527"}; + end + 7'h4e: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 528"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 529"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 530"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 531"}; + end + 7'h4f: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 532"}; + end + 7'h50: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 533"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 534"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 535"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 536"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 537"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 538"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 539"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 540"}; + end + 7'h51: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 541"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 542"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 543"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 544"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 545"}; + end + 7'h52: + foobar = {foobar, " 546"}; + 7'h53: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 547"}; + end + 7'h54: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 548"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 549"}; + end + 7'h55: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 550"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 551"}; + end + 7'h56: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 552"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 553"}; + foobar = {foobar, " 554"}; + end + 7'h57: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 555"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 556"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 557"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 558"}; + end + 7'h58: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 559"}; + end + 7'h59: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 560"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 561"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 562"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 563"}; + end + 7'h5a: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 564"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 565"}; + end + 7'h5b: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 566"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 567"}; + end + 7'h5c: + begin + foobar = {foobar," 568"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 569"}; + foobar = {foobar," 570"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 571"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 572"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 573"}; + end + 7'h5d: + begin + foobar = {foobar," 574"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 575"}; + foobar = {foobar," 576"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 577"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 578"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 579"}; + end + 7'h5e: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 580"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 581"}; + end + 7'h5f: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 582"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 583"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 584"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 585"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 586"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 587"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 588"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 589"}; + end + 7'h60: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 590"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 591"}; + end + 7'h61: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 592"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 593"}; + end + 7'h62: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 594"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 595"}; + end + 7'h63: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 596"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 597"}; + end + 7'h64: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 598"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 599"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 600"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 601"}; + end + 7'h65: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 602"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 603"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 604"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 605"}; + end + 7'h66: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 606"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 607"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 608"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 609"}; + end + 7'h67: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 610"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 611"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 612"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 613"}; + end + 7'h68: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 614"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 615"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 616"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 617"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 618"}; + ozoneape(foo[17:15], foobar); + end + 7'h69: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 619"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 620"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 621"}; + end + 7'h6a: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 622"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 623"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 624"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 625"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 626"}; + ozoneae(foo[17:15], foobar); + end + 7'h6b: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 627"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 628"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 629"}; + end + 7'h6c: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 630"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 631"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 632"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 633"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 634"}; + ozoneae(foo[17:15], foobar); + end + 7'h6d: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 635"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 636"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 637"}; + end + 7'h6e: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 638"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 639"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 640"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 641"}; + end + 7'h6f: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 642"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 643"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 644"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 645"}; + end + 7'h70: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 646"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 647"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 648"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 649"}; + end + 7'h71: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 650"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 651"}; + end + 7'h72: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 652"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 653"}; + end + 7'h73: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 654"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 655"}; + ozoneae(foo[17:15], foobar); + end + 7'h74: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 656"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 657"}; + ozoneae(foo[17:15], foobar); + end + 7'h75: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 658"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 659"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 660"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 661"}; + foobar = {foobar, " 662"}; + foobar = {foobar, " 663"}; + end + 7'h76: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 664"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 665"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 666"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 667"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 668"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 669"}; + end + 7'h77: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 670"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 671"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 672"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 673"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 674"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 675"}; + end + 7'h78, + 7'h79, + 7'h7a, + 7'h7b, + 7'h7c, + 7'h7d, + 7'h7e, + 7'h7f: + foobar = {foobar," 676"}; + endcase + end + endtask + + task ozonef2; + input [ 31:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[24:21]) + 4'h0 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 677"}; + 2'b01 : foobar = {foobar," 678"}; + 2'b10 : foobar = {foobar," 679"}; + 2'b11 : foobar = {foobar," 680"}; + endcase + 4'h1 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 681"}; + 2'b01 : foobar = {foobar," 682"}; + 2'b10 : foobar = {foobar," 683"}; + 2'b11 : foobar = {foobar," 684"}; + endcase + 4'h2 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 685"}; + 2'b01 : foobar = {foobar," 686"}; + 2'b10 : foobar = {foobar," 687"}; + 2'b11 : foobar = {foobar," 688"}; + endcase + 4'h3 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 689"}; + 2'b01 : foobar = {foobar," 690"}; + 2'b10 : foobar = {foobar," 691"}; + 2'b11 : foobar = {foobar," 692"}; + endcase + 4'h4 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 693"}; + 2'b01 : foobar = {foobar," 694"}; + 2'b10 : foobar = {foobar," 695"}; + 2'b11 : foobar = {foobar," 696"}; + endcase + 4'h5 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 697"}; + 2'b01 : foobar = {foobar," 698"}; + 2'b10 : foobar = {foobar," 699"}; + 2'b11 : foobar = {foobar," 700"}; + endcase + 4'h6 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 701"}; + 2'b01 : foobar = {foobar," 702"}; + 2'b10 : foobar = {foobar," 703"}; + 2'b11 : foobar = {foobar," 704"}; + endcase + 4'h7 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 705"}; + 2'b01 : foobar = {foobar," 706"}; + 2'b10 : foobar = {foobar," 707"}; + 2'b11 : foobar = {foobar," 708"}; + endcase + 4'h8 : + if (foo[26]) + foobar = {foobar," 709"}; + else + foobar = {foobar," 710"}; + 4'h9 : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 711"}; + 2'b01 : foobar = {foobar," 712"}; + 2'b10 : foobar = {foobar," 713"}; + 2'b11 : foobar = {foobar," 714"}; + endcase + 4'ha : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 715"}; + 2'b01 : foobar = {foobar," 716"}; + 2'b10 : foobar = {foobar," 717"}; + 2'b11 : foobar = {foobar," 718"}; + endcase + 4'hb : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 719"}; + 2'b01 : foobar = {foobar," 720"}; + 2'b10 : foobar = {foobar," 721"}; + 2'b11 : foobar = {foobar," 722"}; + endcase + 4'hc : + if (foo[26]) + foobar = {foobar," 723"}; + else + foobar = {foobar," 724"}; + 4'hd : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 725"}; + 2'b01 : foobar = {foobar," 726"}; + 2'b10 : foobar = {foobar," 727"}; + 2'b11 : foobar = {foobar," 728"}; + endcase + 4'he : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 729"}; + 2'b01 : foobar = {foobar," 730"}; + 2'b10 : foobar = {foobar," 731"}; + 2'b11 : foobar = {foobar," 732"}; + endcase + 4'hf : + case (foo[26:25]) + 2'b00 : foobar = {foobar," 733"}; + 2'b01 : foobar = {foobar," 734"}; + 2'b10 : foobar = {foobar," 735"}; + 2'b11 : foobar = {foobar," 736"}; + endcase + endcase + end + endtask + + task ozonef2e; + input [ 31:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + casez (foo[25:21]) + 5'h00 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 737"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 738"}; + end + 5'h01 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 739"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 740"}; + end + 5'h02 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 741"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 742"}; + end + 5'h03 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 743"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 744"}; + end + 5'h04 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 745"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 746"}; + end + 5'h05 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 747"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 748"}; + end + 5'h06 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 749"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 750"}; + end + 5'h07 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 751"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 752"}; + end + 5'h08 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 753"}; + if (foo[ 6]) + foobar = {foobar," 754"}; + else + foobar = {foobar," 755"}; + end + 5'h09 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 756"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 757"}; + end + 5'h0a : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 758"}; + ozoneae(foo[17:15], foobar); + end + 5'h0b : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 759"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 760"}; + end + 5'h0c : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 761"}; + end + 5'h0d : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 762"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 763"}; + end + 5'h0e : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 764"}; + ozoneae(foo[17:15], foobar); + end + 5'h0f : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 765"}; + ozoneae(foo[17:15], foobar); + end + 5'h10 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 766"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 767"}; + end + 5'h11 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 768"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 769"}; + end + 5'h18 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 770"}; + if (foo[ 6]) + foobar = {foobar," 771"}; + else + foobar = {foobar," 772"}; + end + 5'h1a : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 773"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 774"}; + end + 5'h1b : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 775"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 776"}; + if (foo[ 6]) + foobar = {foobar," 777"}; + else + foobar = {foobar," 778"}; + foobar = {foobar," 779"}; + end + 5'h1c : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 780"}; + end + 5'h1d : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 781"}; + if (foo[ 6]) + foobar = {foobar," 782"}; + else + foobar = {foobar," 783"}; + foobar = {foobar," 784"}; + end + 5'h1e : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 785"}; + if (foo[ 6]) + foobar = {foobar," 786"}; + else + foobar = {foobar," 787"}; + foobar = {foobar," 788"}; + end + 5'h1f : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 789"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 790"}; + if (foo[ 6]) + foobar = {foobar," 791"}; + else + foobar = {foobar," 792"}; + foobar = {foobar," 793"}; + end + default : + foobar = {foobar," 794"}; + endcase + end + endtask + + task ozonef3e; + input [ 31:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[25:21]) + 5'h00, + 5'h01, + 5'h02: + begin + ozoneae(foo[20:18], foobar); + case (foo[22:21]) + 2'h0: foobar = {foobar," 795"}; + 2'h1: foobar = {foobar," 796"}; + 2'h2: foobar = {foobar," 797"}; + endcase + ozoneae(foo[17:15], foobar); + foobar = {foobar," 798"}; + if (foo[ 9]) + ozoneae(foo[ 8: 6], foobar); + else + ozonef3e_te(foo[ 8: 6], foobar); + foobar = {foobar," 799"}; + end + 5'h08, + 5'h09, + 5'h0d, + 5'h0e, + 5'h0f: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 800"}; + ozoneae(foo[17:15], foobar); + case (foo[23:21]) + 3'h0: foobar = {foobar," 801"}; + 3'h1: foobar = {foobar," 802"}; + 3'h5: foobar = {foobar," 803"}; + 3'h6: foobar = {foobar," 804"}; + 3'h7: foobar = {foobar," 805"}; + endcase + if (foo[ 9]) + ozoneae(foo[ 8: 6], foobar); + else + ozonef3e_te(foo[ 8: 6], foobar); + end + 5'h0a, + 5'h0b: + begin + ozoneae(foo[17:15], foobar); + if (foo[21]) + foobar = {foobar," 806"}; + else + foobar = {foobar," 807"}; + if (foo[ 9]) + ozoneae(foo[ 8: 6], foobar); + else + ozonef3e_te(foo[ 8: 6], foobar); + end + 5'h0c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 808"}; + if (foo[ 9]) + ozoneae(foo[ 8: 6], foobar); + else + ozonef3e_te(foo[ 8: 6], foobar); + foobar = {foobar," 809"}; + ozoneae(foo[17:15], foobar); + end + 5'h10, + 5'h11, + 5'h12, + 5'h13: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 810"}; + ozoneae(foo[17:15], foobar); + case (foo[22:21]) + 2'h0, + 2'h2: + foobar = {foobar," 811"}; + 2'h1, + 2'h3: + foobar = {foobar," 812"}; + endcase + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar," 813"}; + ozoneae((foo[20:18]+1), foobar); + foobar = {foobar," 814"}; + ozoneae((foo[17:15]+1), foobar); + case (foo[22:21]) + 2'h0, + 2'h3: + foobar = {foobar," 815"}; + 2'h1, + 2'h2: + foobar = {foobar," 816"}; + endcase + ozoneae((foo[ 8: 6]+1), foobar); + end + 5'h18: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 817"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 818"}; + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar," 819"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 820"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 821"}; + ozoneae(foo[ 8: 6], foobar); + end + default : + foobar = {foobar," 822"}; + endcase + end + endtask + task ozonef3e_te; + input [ 2:0] te; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (te) + 3'b100 : foobar = {foobar, " 823"}; + 3'b101 : foobar = {foobar, " 824"}; + 3'b110 : foobar = {foobar, " 825"}; + default: foobar = {foobar, " 826"}; + endcase + end + endtask + task ozonearm; + input [ 2:0] ate; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (ate) + 3'b000 : foobar = {foobar, " 827"}; + 3'b001 : foobar = {foobar, " 828"}; + 3'b010 : foobar = {foobar, " 829"}; + 3'b011 : foobar = {foobar, " 830"}; + 3'b100 : foobar = {foobar, " 831"}; + 3'b101 : foobar = {foobar, " 832"}; + 3'b110 : foobar = {foobar, " 833"}; + 3'b111 : foobar = {foobar, " 834"}; + endcase + end + endtask + task ozonebmuop; + input [ 4:0] f4; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (f4[ 4:0]) + 5'h00, + 5'h04 : + foobar = {foobar, " 835"}; + 5'h01, + 5'h05 : + foobar = {foobar, " 836"}; + 5'h02, + 5'h06 : + foobar = {foobar, " 837"}; + 5'h03, + 5'h07 : + foobar = {foobar, " 838"}; + 5'h08, + 5'h18 : + foobar = {foobar, " 839"}; + 5'h09, + 5'h19 : + foobar = {foobar, " 840"}; + 5'h0a, + 5'h1a : + foobar = {foobar, " 841"}; + 5'h0b : + foobar = {foobar, " 842"}; + 5'h1b : + foobar = {foobar, " 843"}; + 5'h0c, + 5'h1c : + foobar = {foobar, " 844"}; + 5'h0d, + 5'h1d : + foobar = {foobar, " 845"}; + 5'h1e : + foobar = {foobar, " 846"}; + endcase + end + endtask + task ozonef3; + input [ 31:0] foo; + inout [STRLEN*8: 1] foobar; + reg nacho; + // verilator no_inline_task + begin : f3_body + nacho = 1'b0; + case (foo[24:21]) + 4'h0: + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 847"}; + 2'b01 : foobar = {foobar, " 848"}; + 2'b10 : foobar = {foobar, " 849"}; + 2'b11 : foobar = {foobar, " 850"}; + endcase + 4'h1: + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 851"}; + 2'b01 : foobar = {foobar, " 852"}; + 2'b10 : foobar = {foobar, " 853"}; + 2'b11 : foobar = {foobar, " 854"}; + endcase + 4'h2: + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 855"}; + 2'b01 : foobar = {foobar, " 856"}; + 2'b10 : foobar = {foobar, " 857"}; + 2'b11 : foobar = {foobar, " 858"}; + endcase + 4'h8, + 4'h9, + 4'hd, + 4'he, + 4'hf : + case (foo[26:25]) + 2'b00 : foobar = {foobar, " 859"}; + 2'b01 : foobar = {foobar, " 860"}; + 2'b10 : foobar = {foobar, " 861"}; + 2'b11 : foobar = {foobar, " 862"}; + endcase + 4'ha, + 4'hb : + if (foo[25]) + foobar = {foobar, " 863"}; + else + foobar = {foobar, " 864"}; + 4'hc : + if (foo[26]) + foobar = {foobar, " 865"}; + else + foobar = {foobar, " 866"}; + default : + begin + foobar = {foobar, " 867"}; + nacho = 1'b1; + end + endcase + if (~nacho) + begin + case (foo[24:21]) + 4'h8 : + foobar = {foobar, " 868"}; + 4'h9 : + foobar = {foobar, " 869"}; + 4'ha, + 4'he : + foobar = {foobar, " 870"}; + 4'hb, + 4'hf : + foobar = {foobar, " 871"}; + 4'hd : + foobar = {foobar, " 872"}; + endcase + if (foo[20]) + case (foo[18:16]) + 3'b000 : foobar = {foobar, " 873"}; + 3'b100 : foobar = {foobar, " 874"}; + default: foobar = {foobar, " 875"}; + endcase + else + ozoneae(foo[18:16], foobar); + if (foo[24:21] === 4'hc) + if (foo[25]) + foobar = {foobar, " 876"}; + else + foobar = {foobar, " 877"}; + case (foo[24:21]) + 4'h0, + 4'h1, + 4'h2: + foobar = {foobar, " 878"}; + endcase + end + end + endtask + task ozonerx; + input [ 31:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[19:18]) + 2'h0 : foobar = {foobar, " 879"}; + 2'h1 : foobar = {foobar, " 880"}; + 2'h2 : foobar = {foobar, " 881"}; + 2'h3 : foobar = {foobar, " 882"}; + endcase + case (foo[17:16]) + 2'h1 : foobar = {foobar, " 883"}; + 2'h2 : foobar = {foobar, " 884"}; + 2'h3 : foobar = {foobar, " 885"}; + endcase + end + endtask + task ozonerme; + input [ 2:0] rme; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (rme) + 3'h0 : foobar = {foobar, " 886"}; + 3'h1 : foobar = {foobar, " 887"}; + 3'h2 : foobar = {foobar, " 888"}; + 3'h3 : foobar = {foobar, " 889"}; + 3'h4 : foobar = {foobar, " 890"}; + 3'h5 : foobar = {foobar, " 891"}; + 3'h6 : foobar = {foobar, " 892"}; + 3'h7 : foobar = {foobar, " 893"}; + endcase + end + endtask + task ozoneye; + input [5:0] ye; + input l; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + foobar = {foobar, " 894"}; + ozonerme(ye[5:3],foobar); + case ({ye[ 2:0], l}) + 4'h2, + 4'ha: foobar = {foobar, " 895"}; + 4'h4, + 4'hb: foobar = {foobar, " 896"}; + 4'h6, + 4'he: foobar = {foobar, " 897"}; + 4'h8, + 4'hc: foobar = {foobar, " 898"}; + endcase + end + endtask + task ozonef1e_ye; + input [5:0] ye; + input l; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + foobar = {foobar, " 899"}; + ozonerme(ye[5:3],foobar); + ozonef1e_inc_dec(ye[5:0], l ,foobar); + end + endtask + task ozonef1e_h; + input [ 2:0] e; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + if (e[ 2:0] <= 3'h4) + foobar = {foobar, " 900"}; + end + endtask + task ozonef1e_inc_dec; + input [5:0] ye; + input l; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case ({ye[ 2:0], l}) + 4'h2, + 4'h3, + 4'ha: foobar = {foobar, " 901"}; + 4'h4, + 4'h5, + 4'hb: foobar = {foobar, " 902"}; + 4'h6, + 4'h7, + 4'he: foobar = {foobar, " 903"}; + 4'h8, + 4'h9, + 4'hc: foobar = {foobar, " 904"}; + 4'hf: foobar = {foobar, " 905"}; + endcase + end + endtask + task ozonef1e_hl; + input [ 2:0] e; + input l; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case ({e[ 2:0], l}) + 4'h0, + 4'h2, + 4'h4, + 4'h6, + 4'h8: foobar = {foobar, " 906"}; + 4'h1, + 4'h3, + 4'h5, + 4'h7, + 4'h9: foobar = {foobar, " 907"}; + endcase + end + endtask + task ozonexe; + input [ 3:0] xe; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (xe[3]) + 1'b0 : foobar = {foobar, " 908"}; + 1'b1 : foobar = {foobar, " 909"}; + endcase + case (xe[ 2:0]) + 3'h1, + 3'h5: foobar = {foobar, " 910"}; + 3'h2, + 3'h6: foobar = {foobar, " 911"}; + 3'h3, + 3'h7: foobar = {foobar, " 912"}; + 3'h4: foobar = {foobar, " 913"}; + endcase + end + endtask + task ozonerp; + input [ 2:0] rp; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (rp) + 3'h0 : foobar = {foobar, " 914"}; + 3'h1 : foobar = {foobar, " 915"}; + 3'h2 : foobar = {foobar, " 916"}; + 3'h3 : foobar = {foobar, " 917"}; + 3'h4 : foobar = {foobar, " 918"}; + 3'h5 : foobar = {foobar, " 919"}; + 3'h6 : foobar = {foobar, " 920"}; + 3'h7 : foobar = {foobar, " 921"}; + endcase + end + endtask + task ozonery; + input [ 3:0] ry; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (ry) + 4'h0 : foobar = {foobar, " 922"}; + 4'h1 : foobar = {foobar, " 923"}; + 4'h2 : foobar = {foobar, " 924"}; + 4'h3 : foobar = {foobar, " 925"}; + 4'h4 : foobar = {foobar, " 926"}; + 4'h5 : foobar = {foobar, " 927"}; + 4'h6 : foobar = {foobar, " 928"}; + 4'h7 : foobar = {foobar, " 929"}; + 4'h8 : foobar = {foobar, " 930"}; + 4'h9 : foobar = {foobar, " 931"}; + 4'ha : foobar = {foobar, " 932"}; + 4'hb : foobar = {foobar, " 933"}; + 4'hc : foobar = {foobar, " 934"}; + 4'hd : foobar = {foobar, " 935"}; + 4'he : foobar = {foobar, " 936"}; + 4'hf : foobar = {foobar, " 937"}; + endcase + end + endtask + task ozonearx; + input [ 15:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[1:0]) + 2'h0 : foobar = {foobar, " 938"}; + 2'h1 : foobar = {foobar, " 939"}; + 2'h2 : foobar = {foobar, " 940"}; + 2'h3 : foobar = {foobar, " 941"}; + endcase + end + endtask + task ozonef3f4imop; + input [ 4:0] f3f4iml; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + casez (f3f4iml) + 5'b000??: foobar = {foobar, " 942"}; + 5'b001??: foobar = {foobar, " 943"}; + 5'b?10??: foobar = {foobar, " 944"}; + 5'b0110?: foobar = {foobar, " 945"}; + 5'b01110: foobar = {foobar, " 946"}; + 5'b01111: foobar = {foobar, " 947"}; + 5'b10???: foobar = {foobar, " 948"}; + 5'b11100: foobar = {foobar, " 949"}; + 5'b11101: foobar = {foobar, " 950"}; + 5'b11110: foobar = {foobar, " 951"}; + 5'b11111: foobar = {foobar, " 952"}; + endcase + end + endtask + task ozonecon; + input [ 4:0] con; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (con) + 5'h00 : foobar = {foobar, " 953"}; + 5'h01 : foobar = {foobar, " 954"}; + 5'h02 : foobar = {foobar, " 955"}; + 5'h03 : foobar = {foobar, " 956"}; + 5'h04 : foobar = {foobar, " 957"}; + 5'h05 : foobar = {foobar, " 958"}; + 5'h06 : foobar = {foobar, " 959"}; + 5'h07 : foobar = {foobar, " 960"}; + 5'h08 : foobar = {foobar, " 961"}; + 5'h09 : foobar = {foobar, " 962"}; + 5'h0a : foobar = {foobar, " 963"}; + 5'h0b : foobar = {foobar, " 964"}; + 5'h0c : foobar = {foobar, " 965"}; + 5'h0d : foobar = {foobar, " 966"}; + 5'h0e : foobar = {foobar, " 967"}; + 5'h0f : foobar = {foobar, " 968"}; + 5'h10 : foobar = {foobar, " 969"}; + 5'h11 : foobar = {foobar, " 970"}; + 5'h12 : foobar = {foobar, " 971"}; + 5'h13 : foobar = {foobar, " 972"}; + 5'h14 : foobar = {foobar, " 973"}; + 5'h15 : foobar = {foobar, " 974"}; + 5'h16 : foobar = {foobar, " 975"}; + 5'h17 : foobar = {foobar, " 976"}; + 5'h18 : foobar = {foobar, " 977"}; + 5'h19 : foobar = {foobar, " 978"}; + 5'h1a : foobar = {foobar, " 979"}; + 5'h1b : foobar = {foobar, " 980"}; + 5'h1c : foobar = {foobar, " 981"}; + 5'h1d : foobar = {foobar, " 982"}; + 5'h1e : foobar = {foobar, " 983"}; + 5'h1f : foobar = {foobar, " 984"}; + endcase + end + endtask + task ozonedr; + input [ 15:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[ 9: 6]) + 4'h0 : foobar = {foobar, " 985"}; + 4'h1 : foobar = {foobar, " 986"}; + 4'h2 : foobar = {foobar, " 987"}; + 4'h3 : foobar = {foobar, " 988"}; + 4'h4 : foobar = {foobar, " 989"}; + 4'h5 : foobar = {foobar, " 990"}; + 4'h6 : foobar = {foobar, " 991"}; + 4'h7 : foobar = {foobar, " 992"}; + 4'h8 : foobar = {foobar, " 993"}; + 4'h9 : foobar = {foobar, " 994"}; + 4'ha : foobar = {foobar, " 995"}; + 4'hb : foobar = {foobar, " 996"}; + 4'hc : foobar = {foobar, " 997"}; + 4'hd : foobar = {foobar, " 998"}; + 4'he : foobar = {foobar, " 999"}; + 4'hf : foobar = {foobar, " 1000"}; + endcase + end + endtask + task ozoneshift; + input [ 15:0] foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo[ 4: 3]) + 2'h0 : foobar = {foobar, " 1001"}; + 2'h1 : foobar = {foobar, " 1002"}; + 2'h2 : foobar = {foobar, " 1003"}; + 2'h3 : foobar = {foobar, " 1004"}; + endcase + end + endtask + task ozoneacc; + input foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo) + 2'h0 : foobar = {foobar, " 1005"}; + 2'h1 : foobar = {foobar, " 1006"}; + endcase + end + endtask + task ozonehl; + input foo; + inout [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + case (foo) + 2'h0 : foobar = {foobar, " 1007"}; + 2'h1 : foobar = {foobar, " 1008"}; + endcase + end + endtask + task dude; + inout [STRLEN*8: 1] foobar; + reg [ 7:0] temp; + integer i; + reg nacho; + // verilator no_inline_task + begin : justify_block + nacho = 1'b0; + for (i=STRLEN-1; i>1; i=i-1) + begin + temp = foobar>>((STRLEN-1)*8); + if (temp || nacho) + nacho = 1'b1; + else + begin + foobar = foobar<<8; + foobar[8:1] = 32; + end + end + end + endtask + + task big_case; + input [ 31:0] fd; + input [ 31:0] foo; + reg [STRLEN*8: 1] foobar; + // verilator no_inline_task + begin + foobar = " 1009"; + if (&foo === 1'bx) + $fwrite(fd, " 1010"); + else + casez ( {foo[31:26], foo[19:15], foo[5:0]} ) + 17'b00_111?_?_????_??_???? : + begin + ozonef1(foo, foobar); + foobar = {foobar, " 1011"}; + ozoneacc(~foo[26], foobar); + ozonehl(foo[20], foobar); + foobar = {foobar, " 1012"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite (fd, " 1013:%s", foobar); + end + 17'b01_001?_?_????_??_???? : + begin + ozonef1(foo, foobar); + foobar = {foobar, " 1014"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1015"}; + foobar = {foobar, " 1016"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite (fd, " 1017:%s", foobar); + end + 17'b10_100?_?_????_??_???? : + begin + ozonef1(foo, foobar); + foobar = {foobar, " 1018"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1019"}; + foobar = {foobar, " 1020"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite (fd, " 1021:%s", foobar); + end + 17'b10_101?_?_????_??_???? : + begin + ozonef1(foo, foobar); + foobar = {foobar, " 1022"}; + if (foo[20]) + begin + foobar = {foobar, " 1023"}; + ozoneacc(foo[18], foobar); + foobar = {foobar, " 1024"}; + foobar = {foobar, " 1025"}; + if (foo[19]) + foobar = {foobar, " 1026"}; + else + foobar = {foobar, " 1027"}; + end + else + ozonerx(foo, foobar); + dude(foobar); + $fwrite (fd, " 1028:%s", foobar); + end + 17'b10_110?_?_????_??_???? : + begin + ozonef1(foo, foobar); + foobar = {foobar, " 1029"}; + foobar = {foobar, " 1030"}; + ozonehl(foo[20], foobar); + foobar = {foobar, " 1031"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite (fd, " 1032:%s", foobar); + end + 17'b10_111?_?_????_??_???? : + begin + ozonef1(foo, foobar); + foobar = {foobar, " 1033"}; + foobar = {foobar, " 1034"}; + ozonehl(foo[20], foobar); + foobar = {foobar, " 1035"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite (fd, " 1036:%s", foobar); + end + 17'b11_001?_?_????_??_???? : + begin + ozonef1(foo, foobar); + foobar = {foobar, " 1037"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1038"}; + foobar = {foobar, " 1039"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite (fd, " 1040:%s", foobar); + end + 17'b11_111?_?_????_??_???? : + begin + ozonef1(foo, foobar); + foobar = {foobar, " 1041"}; + foobar = {foobar, " 1042"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1043"}; + if (foo[20]) + foobar = {foobar, " 1044"}; + else + foobar = {foobar, " 1045"}; + dude(foobar); + $fwrite (fd, " 1046:%s", foobar); + end + 17'b00_10??_?_????_?1_1111 : + casez (foo[11: 5]) + 7'b??_0_010_0: + begin + foobar = " 1047"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1048"}; + ozonef1e(foo, foobar); + dude(foobar); + $fwrite (fd, " 1049:%s", foobar); + end + 7'b00_?_110_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1050"}; + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + foobar = {foobar, " 1051"}; + ozoneae(foo[14:12], foobar); + ozonehl(foo[ 5], foobar); + end + 2'b01: + begin + foobar = {foobar, " 1052"}; + ozoneae(foo[14:12], foobar); + ozonehl(foo[ 5], foobar); + end + 2'b10: + begin + foobar = {foobar, " 1053"}; + ozoneae(foo[14:12], foobar); + end + 2'b11: foobar = {foobar, " 1054"}; + endcase + dude(foobar); + $fwrite (fd, " 1055:%s", foobar); + end + 7'b01_?_110_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1056"}; + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + ozoneae(foo[14:12], foobar); + ozonehl(foo[ 5], foobar); + foobar = {foobar, " 1057"}; + end + 2'b01: + begin + ozoneae(foo[14:12], foobar); + ozonehl(foo[ 5], foobar); + foobar = {foobar, " 1058"}; + end + 2'b10: + begin + ozoneae(foo[14:12], foobar); + foobar = {foobar, " 1059"}; + end + 2'b11: foobar = {foobar, " 1060"}; + endcase + dude(foobar); + $fwrite (fd, " 1061:%s", foobar); + end + 7'b10_0_110_0: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1062"}; + foobar = {foobar, " 1063"}; + if (foo[12]) + foobar = {foobar, " 1064"}; + else + ozonerab({4'b1001, foo[14:12]}, foobar); + dude(foobar); + $fwrite (fd, " 1065:%s", foobar); + end + 7'b10_0_110_1: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1066"}; + if (foo[12]) + foobar = {foobar, " 1067"}; + else + ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1068"}; + dude(foobar); + $fwrite (fd, " 1069:%s", foobar); + end + 7'b??_?_000_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1070"}; + foobar = {foobar, " 1071"}; + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + foobar = {foobar, " 1072"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1073:%s", foobar); + end + 7'b??_?_100_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1074"}; + foobar = {foobar, " 1075"}; + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + foobar = {foobar, " 1076"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1077:%s", foobar); + end + 7'b??_?_001_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1078"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + foobar = {foobar, " 1079"}; + foobar = {foobar, " 1080"}; + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1081:%s", foobar); + end + 7'b??_?_011_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1082"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + foobar = {foobar, " 1083"}; + foobar = {foobar, " 1084"}; + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1085:%s", foobar); + end + 7'b??_?_101_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1086"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1087:%s", foobar); + end + endcase + 17'b00_10??_?_????_?0_0110 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1088"}; + ozoneae(foo[ 8: 6], foobar); + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + foobar = {foobar, " 1089"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1090:%s", foobar); + end + 17'b00_10??_?_????_00_0111 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1091"}; + if (foo[ 6]) + foobar = {foobar, " 1092"}; + else + ozonerab({4'b1001, foo[ 8: 6]}, foobar); + foobar = {foobar, " 1093"}; + foobar = {foobar, " 1094"}; + ozonerme(foo[14:12],foobar); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0,foobar); + 3'h1, + 3'h3, + 3'h4: + foobar = {foobar, " 1095"}; + endcase + dude(foobar); + $fwrite (fd, " 1096:%s", foobar); + end + 17'b00_10??_?_????_?0_0100 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1097"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + foobar = {foobar, " 1098"}; + ozoneae(foo[ 8: 6], foobar); + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1099:%s", foobar); + end + 17'b00_10??_?_????_10_0111 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1100"}; + foobar = {foobar, " 1101"}; + ozonerme(foo[14:12],foobar); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0,foobar); + 3'h1, + 3'h3, + 3'h4: + foobar = {foobar, " 1102"}; + endcase + foobar = {foobar, " 1103"}; + if (foo[ 6]) + foobar = {foobar, " 1104"}; + else + ozonerab({4'b1001, foo[ 8: 6]}, foobar); + dude(foobar); + $fwrite (fd, " 1105:%s", foobar); + end + 17'b00_10??_?_????_?0_1110 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1106"}; + case (foo[11:9]) + 3'h2: + begin + foobar = {foobar, " 1107"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1108"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1109"}; + end + 3'h6: + begin + foobar = {foobar, " 1110"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1111"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1112"}; + end + 3'h0: + begin + foobar = {foobar, " 1113"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1114"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1115"}; + if (foo[ 7: 5] >= 3'h5) + foobar = {foobar, " 1116"}; + else + ozonexe(foo[ 8: 5], foobar); + end + 3'h1: + begin + foobar = {foobar, " 1117"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1118"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1119"}; + if (foo[ 7: 5] >= 3'h5) + foobar = {foobar, " 1120"}; + else + ozonexe(foo[ 8: 5], foobar); + end + 3'h4: + begin + foobar = {foobar, " 1121"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1122"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1123"}; + if (foo[ 7: 5] >= 3'h5) + foobar = {foobar, " 1124"}; + else + ozonexe(foo[ 8: 5], foobar); + end + 3'h5: + begin + foobar = {foobar, " 1125"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1126"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1127"}; + if (foo[ 7: 5] >= 3'h5) + foobar = {foobar, " 1128"}; + else + ozonexe(foo[ 8: 5], foobar); + end + endcase + dude(foobar); + $fwrite (fd, " 1129:%s", foobar); + end + 17'b00_10??_?_????_?0_1111 : + casez (foo[14: 9]) + 6'b001_10_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1130"}; + foobar = {foobar, " 1131"}; + ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); + foobar = {foobar, " 1132"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1133:%s", foobar); + end + 6'b???_11_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1134"}; + ozoneae(foo[14:12], foobar); + ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); + foobar = {foobar, " 1135"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1136:%s", foobar); + end + 6'b000_10_1, + 6'b010_10_1, + 6'b100_10_1, + 6'b110_10_1: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1137"}; + ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1138"}; + if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) + foobar = {foobar, " 1139"}; + else + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1140:%s", foobar); + end + 6'b000_10_0, + 6'b010_10_0, + 6'b100_10_0, + 6'b110_10_0: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1141"}; + foobar = {foobar, " 1142"}; + ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1143"}; + foobar = {foobar, " 1144"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1145"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1146:%s", foobar); + end + 6'b???_00_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1147"}; + if (foo[ 9]) + begin + foobar = {foobar, " 1148"}; + ozoneae(foo[14:12], foobar); + end + else + begin + foobar = {foobar, " 1149"}; + ozoneae(foo[14:12], foobar); + foobar = {foobar, " 1150"}; + end + foobar = {foobar, " 1151"}; + foobar = {foobar, " 1152"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1153"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1154:%s", foobar); + end + 6'b???_01_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1155"}; + ozoneae(foo[14:12], foobar); + if (foo[ 9]) + foobar = {foobar, " 1156"}; + else + foobar = {foobar, " 1157"}; + foobar = {foobar, " 1158"}; + foobar = {foobar, " 1159"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1160"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1161:%s", foobar); + end + 6'b011_10_0: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1162"}; + case (foo[ 8: 5]) + 4'h0: foobar = {foobar, " 1163"}; + 4'h1: foobar = {foobar, " 1164"}; + 4'h2: foobar = {foobar, " 1165"}; + 4'h3: foobar = {foobar, " 1166"}; + 4'h4: foobar = {foobar, " 1167"}; + 4'h5: foobar = {foobar, " 1168"}; + 4'h8: foobar = {foobar, " 1169"}; + 4'h9: foobar = {foobar, " 1170"}; + 4'ha: foobar = {foobar, " 1171"}; + 4'hb: foobar = {foobar, " 1172"}; + 4'hc: foobar = {foobar, " 1173"}; + 4'hd: foobar = {foobar, " 1174"}; + default: foobar = {foobar, " 1175"}; + endcase + dude(foobar); + $fwrite (fd, " 1176:%s", foobar); + end + default: foobar = {foobar, " 1177"}; + endcase + 17'b00_10??_?_????_?0_110? : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1178"}; + foobar = {foobar, " 1179"}; + ozonef1e_hl(foo[11:9], foo[0], foobar); + foobar = {foobar, " 1180"}; + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1181"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1182"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1183:%s", foobar); + end + 17'b00_10??_?_????_?1_110? : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1184"}; + foobar = {foobar, " 1185"}; + ozonef1e_hl(foo[11:9],foo[0],foobar); + foobar = {foobar, " 1186"}; + ozonef1e_ye(foo[14:9],foo[ 0],foobar); + foobar = {foobar, " 1187"}; + foobar = {foobar, " 1188"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1189"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1190:%s", foobar); + end + 17'b00_10??_?_????_?0_101? : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1191"}; + ozonef1e_ye(foo[14:9],foo[ 0],foobar); + foobar = {foobar, " 1192"}; + foobar = {foobar, " 1193"}; + ozonef1e_hl(foo[11:9],foo[0],foobar); + foobar = {foobar, " 1194"}; + foobar = {foobar, " 1195"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1196"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1197:%s", foobar); + end + 17'b00_10??_?_????_?0_1001 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1198"}; + foobar = {foobar, " 1199"}; + ozonef1e_h(foo[11:9],foobar); + foobar = {foobar, " 1200"}; + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1201"}; + case (foo[ 7: 5]) + 3'h1, + 3'h2, + 3'h3: + foobar = {foobar, " 1202"}; + default: + begin + foobar = {foobar, " 1203"}; + foobar = {foobar, " 1204"}; + ozonexe(foo[ 8: 5], foobar); + end + endcase + dude(foobar); + $fwrite (fd, " 1205:%s", foobar); + end + 17'b00_10??_?_????_?0_0101 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1206"}; + case (foo[11: 9]) + 3'h1, + 3'h3, + 3'h4: + foobar = {foobar, " 1207"}; + default: + begin + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1208"}; + foobar = {foobar, " 1209"}; + end + endcase + foobar = {foobar, " 1210"}; + foobar = {foobar, " 1211"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1212"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1213:%s", foobar); + end + 17'b00_10??_?_????_?1_1110 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1214"}; + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1215"}; + foobar = {foobar, " 1216"}; + ozonef1e_h(foo[11: 9],foobar); + foobar = {foobar, " 1217"}; + foobar = {foobar, " 1218"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1219"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1220:%s", foobar); + end + 17'b00_10??_?_????_?0_1000 : + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1221"}; + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1222"}; + foobar = {foobar, " 1223"}; + ozonef1e_h(foo[11: 9],foobar); + foobar = {foobar, " 1224"}; + foobar = {foobar, " 1225"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1226"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1227:%s", foobar); + end + 17'b10_01??_?_????_??_???? : + begin + if (foo[27]) + foobar = " 1228"; + else + foobar = " 1229"; + ozonecon(foo[20:16], foobar); + foobar = {foobar, " 1230"}; + ozonef2(foo[31:0], foobar); + dude(foobar); + $fwrite (fd, " 1231:%s", foobar); + end + 17'b00_1000_?_????_01_0011 : + if (~|foo[ 9: 8]) + begin + if (foo[ 7]) + foobar = " 1232"; + else + foobar = " 1233"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1234"}; + ozonef2e(foo[31:0], foobar); + dude(foobar); + $fwrite (fd, " 1235:%s", foobar); + end + else + begin + foobar = " 1236"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1237"}; + ozonef3e(foo[31:0], foobar); + dude(foobar); + $fwrite (fd, " 1238:%s", foobar); + end + 17'b11_110?_1_????_??_???? : + begin + ozonef3(foo[31:0], foobar); + dude(foobar); + $fwrite(fd, " 1239:%s", foobar); + end + 17'b11_110?_0_????_??_???? : + begin : f4_body + casez (foo[24:20]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite (fd, " 1240"); + end + 5'b0_00??: + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1241"}; + ozoneacc(foo[25], foobar); + ozonebmuop(foo[24:20], foobar); + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1242"}; + dude(foobar); + $fwrite(fd, " 1243:%s", foobar); + end + 5'b0_01??: + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1244"}; + ozoneacc(foo[25], foobar); + ozonebmuop(foo[24:20], foobar); + ozonearm(foo[18:16], foobar); + dude(foobar); + $fwrite(fd, " 1245:%s", foobar); + end + 5'b0_1011: + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1246"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1247"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1248"}; + dude(foobar); + $fwrite(fd, " 1249:%s", foobar); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1250"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1251"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1252"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1253"}; + dude(foobar); + $fwrite(fd, " 1254:%s", foobar); + end + 5'b0_1111 : + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1255"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1256"}; + ozoneae(foo[18:16], foobar); + dude(foobar); + $fwrite(fd, " 1257:%s", foobar); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1258"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1259"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1260"}; + ozonearm(foo[18:16], foobar); + foobar = {foobar, " 1261"}; + dude(foobar); + $fwrite(fd, " 1262:%s", foobar); + end + endcase + end + 17'b11_100?_?_????_??_???? : + casez (foo[23:19]) + 5'b111??, + 5'b0111?: + begin + ozoneae(foo[26:24], foobar); + foobar = {foobar, " 1263"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1264"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1265"}; + skyway(foo[15:12], foobar); + skyway(foo[11: 8], foobar); + skyway(foo[ 7: 4], foobar); + skyway(foo[ 3:0], foobar); + foobar = {foobar, " 1266"}; + dude(foobar); + $fwrite(fd, " 1267:%s", foobar); + end + 5'b?0???, + 5'b110??: + begin + ozoneae(foo[26:24], foobar); + foobar = {foobar, " 1268"}; + if (foo[23:21] == 3'b100) + foobar = {foobar, " 1269"}; + ozoneae(foo[18:16], foobar); + if (foo[19]) + foobar = {foobar, " 1270"}; + else + foobar = {foobar, " 1271"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1272"}; + ozonef3f4_iext(foo[20:19], foo[15:0], foobar); + dude(foobar); + $fwrite(fd, " 1273:%s", foobar); + end + 5'b010??, + 5'b0110?: + begin + ozoneae(foo[18:16], foobar); + if (foo[19]) + foobar = {foobar, " 1274"}; + else + foobar = {foobar, " 1275"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1276"}; + ozonef3f4_iext(foo[20:19], foo[15:0], foobar); + dude(foobar); + $fwrite(fd, " 1277:%s", foobar); + end + endcase + 17'b00_1000_?_????_11_0011 : + begin + foobar = " 1278"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1279"}; + casez (foo[25:21]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite(fd, " 1280"); + end + 5'b0_00??: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1281"}; + ozoneae(foo[17:15], foobar); + ozonebmuop(foo[25:21], foobar); + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar, " 1282"}; + dude(foobar); + $fwrite(fd, " 1283:%s", foobar); + end + 5'b0_01??: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1284"}; + ozoneae(foo[17:15], foobar); + ozonebmuop(foo[25:21], foobar); + ozonearm(foo[ 8: 6], foobar); + dude(foobar); + $fwrite(fd, " 1285:%s", foobar); + end + 5'b0_1011: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1286"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1287"}; + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar, " 1288"}; + dude(foobar); + $fwrite(fd, " 1289:%s", foobar); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1290"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1291"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1292"}; + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar, " 1293"}; + dude(foobar); + $fwrite(fd, " 1294:%s", foobar); + end + 5'b0_1111 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1295"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1296"}; + ozoneae(foo[ 8: 6], foobar); + dude(foobar); + $fwrite(fd, " 1297:%s", foobar); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1298"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1299"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1300"}; + ozonearm(foo[ 8: 6], foobar); + foobar = {foobar, " 1301"}; + dude(foobar); + $fwrite(fd, " 1302:%s", foobar); + end + endcase + end + 17'b00_0010_?_????_??_???? : + begin + $fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]); + ozonerab({1'b0, foo[25:20]}, foobar); + $fwrite(fd, " 1304b:%x", foobar); + foobar = {foobar, " 1303"}; + $fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]); + skyway(foo[19:16], foobar); + $fwrite(fd, " 1304d:%x", foobar); + dude(foobar); + $fwrite(fd, " 1304e:%x", foobar); + $fwrite(fd, " 1304:%s", foobar); + end + 17'b00_01??_?_????_??_???? : + begin + if (foo[27]) + begin + foobar = {foobar, " 1305"}; + if (foo[26]) + foobar = {foobar, " 1306"}; + else + foobar = {foobar, " 1307"}; + skyway(foo[19:16], foobar); + foobar = {foobar, " 1308"}; + ozonerab({1'b0, foo[25:20]}, foobar); + end + else + begin + ozonerab({1'b0, foo[25:20]}, foobar); + foobar = {foobar, " 1309"}; + if (foo[26]) + foobar = {foobar, " 1310"}; + else + foobar = {foobar, " 1311"}; + skyway(foo[19:16], foobar); + foobar = {foobar, " 1312"}; + end + dude(foobar); + $fwrite(fd, " 1313:%s", foobar); + end + 17'b01_000?_?_????_??_???? : + begin + if (foo[26]) + begin + ozonerb(foo[25:20], foobar); + foobar = {foobar, " 1314"}; + ozoneae(foo[18:16], foobar); + ozonehl(foo[19], foobar); + end + else + begin + ozoneae(foo[18:16], foobar); + ozonehl(foo[19], foobar); + foobar = {foobar, " 1315"}; + ozonerb(foo[25:20], foobar); + end + dude(foobar); + $fwrite(fd, " 1316:%s", foobar); + end + 17'b01_10??_?_????_??_???? : + begin + if (foo[27]) + begin + ozonerab({1'b0, foo[25:20]}, foobar); + foobar = {foobar, " 1317"}; + ozonerx(foo, foobar); + end + else + begin + ozonerx(foo, foobar); + foobar = {foobar, " 1318"}; + ozonerab({1'b0, foo[25:20]}, foobar); + end + dude(foobar); + $fwrite(fd, " 1319:%s", foobar); + end + 17'b11_101?_?_????_??_???? : + begin + ozonerab (foo[26:20], foobar); + foobar = {foobar, " 1320"}; + skyway(foo[19:16], foobar); + skyway(foo[15:12], foobar); + skyway(foo[11: 8], foobar); + skyway(foo[ 7: 4], foobar); + skyway(foo[ 3: 0], foobar); + dude(foobar); + $fwrite(fd, " 1321:%s", foobar); + end + 17'b11_0000_?_????_??_???? : + begin + casez (foo[25:23]) + 3'b00?: + begin + ozonerab(foo[22:16], foobar); + foobar = {foobar, " 1322"}; + end + 3'b01?: + begin + foobar = {foobar, " 1323"}; + if (foo[22:16]>=7'h60) + foobar = {foobar, " 1324"}; + else + ozonerab(foo[22:16], foobar); + end + 3'b110: + foobar = {foobar, " 1325"}; + 3'b10?: + begin + foobar = {foobar, " 1326"}; + if (foo[22:16]>=7'h60) + foobar = {foobar, " 1327"}; + else + ozonerab(foo[22:16], foobar); + end + 3'b111: + begin + foobar = {foobar, " 1328"}; + ozonerab(foo[22:16], foobar); + foobar = {foobar, " 1329"}; + end + endcase + dude(foobar); + $fwrite(fd, " 1330:%s", foobar); + end + 17'b00_10??_?_????_?1_0000 : + begin + if (foo[27]) + begin + foobar = {foobar, " 1331"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1332"}; + skyway(foo[19:16], foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + foobar = {foobar, " 1333"}; + if (foo[26:20]>=7'h60) + foobar = {foobar, " 1334"}; + else + ozonerab(foo[26:20], foobar); + end + else + begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1335"}; + foobar = {foobar, " 1336"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1337"}; + skyway(foo[19:16], foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + foobar = {foobar, " 1338"}; + end + dude(foobar); + $fwrite(fd, " 1339:%s", foobar); + end + 17'b00_101?_1_0000_?1_0010 : + if (~|foo[11: 7]) + begin + if (foo[ 6]) + begin + foobar = {foobar, " 1340"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1341"}; + ozonejk(foo[ 5], foobar); + foobar = {foobar, " 1342"}; + if (foo[26:20]>=7'h60) + foobar = {foobar, " 1343"}; + else + ozonerab(foo[26:20], foobar); + end + else + begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1344"}; + foobar = {foobar, " 1345"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1346"}; + ozonejk(foo[ 5], foobar); + foobar = {foobar, " 1347"}; + end + dude(foobar); + $fwrite(fd, " 1348:%s", foobar); + end + else + $fwrite(fd, " 1349"); + 17'b00_100?_0_0011_?1_0101 : + if (~|foo[ 8: 7]) + begin + if (foo[6]) + begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1350"}; + ozoneye(foo[14: 9],foo[ 5], foobar); + end + else + begin + ozoneye(foo[14: 9],foo[ 5], foobar); + foobar = {foobar, " 1351"}; + if (foo[26:20]>=7'h60) + foobar = {foobar, " 1352"}; + else + ozonerab(foo[26:20], foobar); + end + dude(foobar); + $fwrite(fd, " 1353:%s", foobar); + end + else + $fwrite(fd, " 1354"); + 17'b00_1001_0_0000_?1_0010 : + if (~|foo[25:20]) + begin + ozoneye(foo[14: 9],1'b0, foobar); + foobar = {foobar, " 1355"}; + ozonef1e_h(foo[11: 9],foobar); + foobar = {foobar, " 1356"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1357"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite(fd, " 1358:%s", foobar); + end + else + $fwrite(fd, " 1359"); + 17'b00_101?_0_????_?1_0010 : + if (~foo[13]) + begin + if (foo[12]) + begin + foobar = {foobar, " 1360"}; + if (foo[26:20]>=7'h60) + foobar = {foobar, " 1361"}; + else + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1362"}; + foobar = {foobar, " 1363"}; + skyway({1'b0,foo[18:16]}, foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + dude(foobar); + $fwrite(fd, " 1364:%s", foobar); + end + else + begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1365"}; + foobar = {foobar, " 1366"}; + skyway({1'b0,foo[18:16]}, foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + dude(foobar); + $fwrite(fd, " 1367:%s", foobar); + end + end + else + $fwrite(fd, " 1368"); + 17'b01_01??_?_????_??_???? : + begin + ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar); + foobar = {foobar, " 1369"}; + ozonerab({1'b0,foo[25:20]}, foobar); + dude(foobar); + $fwrite(fd, " 1370:%s", foobar); + end + 17'b00_100?_?_???0_11_0101 : + if (~foo[6]) + begin + foobar = " 1371"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1372"}; + ozonerab({foo[ 9: 7],foo[19:16]}, foobar); + foobar = {foobar, " 1373"}; + ozonerab({foo[26:20]}, foobar); + dude(foobar); + $fwrite(fd, " 1374:%s", foobar); + end + else + $fwrite(fd, " 1375"); + 17'b00_1000_?_????_?1_0010 : + if (~|foo[25:24]) + begin + ozonery(foo[23:20], foobar); + foobar = {foobar, " 1376"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1377"}; + skyway(foo[19:16], foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + dude(foobar); + $fwrite(fd, " 1378:%s", foobar); + end + else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) + begin + ozonery(foo[23:20], foobar); + foobar = {foobar, " 1379"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1380"}; + ozonejk(foo[ 5], foobar); + dude(foobar); + $fwrite(fd, " 1381:%s", foobar); + end + else + $fwrite(fd, " 1382"); + 17'b11_01??_?_????_??_????, + 17'b10_00??_?_????_??_???? : + if (foo[30]) + $fwrite(fd, " 1383:%s", foo[27:16]); + else + $fwrite(fd, " 1384:%s", foo[27:16]); + 17'b00_10??_?_????_01_1000 : + if (~foo[6]) + begin + if (foo[7]) + $fwrite(fd, " 1385:%s", foo[27: 8]); + else + $fwrite(fd, " 1386:%s", foo[27: 8]); + end + else + $fwrite(fd, " 1387"); + 17'b00_10??_?_????_11_1000 : + begin + foobar = " 1388"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1389"}; + if (foo[15]) + foobar = {foobar, " 1390"}; + else + foobar = {foobar, " 1391"}; + skyway(foo[27:24], foobar); + skyway(foo[23:20], foobar); + skyway(foo[19:16], foobar); + skyway(foo[ 9: 6], foobar); + dude(foobar); + $fwrite(fd, " 1392:%s", foobar); + end + 17'b11_0001_?_????_??_???? : + casez (foo[25:22]) + 4'b01?? : + begin + foobar = " 1393"; + ozonecon(foo[20:16], foobar); + case (foo[23:21]) + 3'h0 : foobar = {foobar, " 1394"}; + 3'h1 : foobar = {foobar, " 1395"}; + 3'h2 : foobar = {foobar, " 1396"}; + 3'h3 : foobar = {foobar, " 1397"}; + 3'h4 : foobar = {foobar, " 1398"}; + 3'h5 : foobar = {foobar, " 1399"}; + 3'h6 : foobar = {foobar, " 1400"}; + 3'h7 : foobar = {foobar, " 1401"}; + endcase + dude(foobar); + $fwrite(fd, " 1402:%s", foobar); + end + 4'b0000 : + $fwrite(fd, " 1403:%s", foo[21:16]); + 4'b0010 : + if (~|foo[21:16]) + $fwrite(fd, " 1404"); + 4'b1010 : + if (~|foo[21:17]) + begin + if (foo[16]) + $fwrite(fd, " 1405"); + else + $fwrite(fd, " 1406"); + end + default : + $fwrite(fd, " 1407"); + endcase + 17'b01_11??_?_????_??_???? : + if (foo[27:23] === 5'h00) + $fwrite(fd, " 1408:%s", foo[22:16]); + else + $fwrite(fd, " 1409:%s", foo[22:16]); + default: $fwrite(fd, " 1410"); + endcase + end + endtask + + //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) + //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_write2.v b/SVIncCompil/Testcases/Verilator/t_case_write2.v new file mode 100644 index 0000000..3110fc3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_write2.v
@@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +`include "verilated.v" + +`define STRINGIFY(x) `"x`" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [63:0] crc; + integer fd; + integer fdtmp; + + t_case_write2_tasks tasks (); + + integer cyc; initial cyc=0; + + always @ (posedge clk) begin + $fwrite(fd, "[%0d] crc=%x ", cyc, crc); + tasks.big_case(fd, crc[31:0]); + $fwrite(fd, "\n"); + end + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==1) begin + crc <= 64'h00000000_00000097; + $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"}); + fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w"); + fd <= fdtmp; + end + if (cyc==90) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_write2_tasks.v b/SVIncCompil/Testcases/Verilator/t_case_write2_tasks.v new file mode 100644 index 0000000..9790eaa --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_write2_tasks.v
@@ -0,0 +1,3773 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +`include "verilated.v" + +module t_case_write2_tasks (); + + // verilator lint_off WIDTH + // verilator lint_off CASEINCOMPLETE + + `define FD_BITS 31:0 + + parameter STRLEN = 78; + task ozonerab; + input [6:0] rab; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (rab[6:0]) + 7'h00 : $fwrite (fd, " 0"); + 7'h01 : $fwrite (fd, " 1"); + 7'h02 : $fwrite (fd, " 2"); + 7'h03 : $fwrite (fd, " 3"); + 7'h04 : $fwrite (fd, " 4"); + 7'h05 : $fwrite (fd, " 5"); + 7'h06 : $fwrite (fd, " 6"); + 7'h07 : $fwrite (fd, " 7"); + 7'h08 : $fwrite (fd, " 8"); + 7'h09 : $fwrite (fd, " 9"); + 7'h0a : $fwrite (fd, " 10"); + 7'h0b : $fwrite (fd, " 11"); + 7'h0c : $fwrite (fd, " 12"); + 7'h0d : $fwrite (fd, " 13"); + 7'h0e : $fwrite (fd, " 14"); + 7'h0f : $fwrite (fd, " 15"); + 7'h10 : $fwrite (fd, " 16"); + 7'h11 : $fwrite (fd, " 17"); + 7'h12 : $fwrite (fd, " 18"); + 7'h13 : $fwrite (fd, " 19"); + 7'h14 : $fwrite (fd, " 20"); + 7'h15 : $fwrite (fd, " 21"); + 7'h16 : $fwrite (fd, " 22"); + 7'h17 : $fwrite (fd, " 23"); + 7'h18 : $fwrite (fd, " 24"); + 7'h19 : $fwrite (fd, " 25"); + 7'h1a : $fwrite (fd, " 26"); + 7'h1b : $fwrite (fd, " 27"); + 7'h1c : $fwrite (fd, " 28"); + 7'h1d : $fwrite (fd, " 29"); + 7'h1e : $fwrite (fd, " 30"); + 7'h1f : $fwrite (fd, " 31"); + 7'h20 : $fwrite (fd, " 32"); + 7'h21 : $fwrite (fd, " 33"); + 7'h22 : $fwrite (fd, " 34"); + 7'h23 : $fwrite (fd, " 35"); + 7'h24 : $fwrite (fd, " 36"); + 7'h25 : $fwrite (fd, " 37"); + 7'h26 : $fwrite (fd, " 38"); + 7'h27 : $fwrite (fd, " 39"); + 7'h28 : $fwrite (fd, " 40"); + 7'h29 : $fwrite (fd, " 41"); + 7'h2a : $fwrite (fd, " 42"); + 7'h2b : $fwrite (fd, " 43"); + 7'h2c : $fwrite (fd, " 44"); + 7'h2d : $fwrite (fd, " 45"); + 7'h2e : $fwrite (fd, " 46"); + 7'h2f : $fwrite (fd, " 47"); + 7'h30 : $fwrite (fd, " 48"); + 7'h31 : $fwrite (fd, " 49"); + 7'h32 : $fwrite (fd, " 50"); + 7'h33 : $fwrite (fd, " 51"); + 7'h34 : $fwrite (fd, " 52"); + 7'h35 : $fwrite (fd, " 53"); + 7'h36 : $fwrite (fd, " 54"); + 7'h37 : $fwrite (fd, " 55"); + 7'h38 : $fwrite (fd, " 56"); + 7'h39 : $fwrite (fd, " 57"); + 7'h3a : $fwrite (fd, " 58"); + 7'h3b : $fwrite (fd, " 59"); + 7'h3c : $fwrite (fd, " 60"); + 7'h3d : $fwrite (fd, " 61"); + 7'h3e : $fwrite (fd, " 62"); + 7'h3f : $fwrite (fd, " 63"); + 7'h40 : $fwrite (fd, " 64"); + 7'h41 : $fwrite (fd, " 65"); + 7'h42 : $fwrite (fd, " 66"); + 7'h43 : $fwrite (fd, " 67"); + 7'h44 : $fwrite (fd, " 68"); + 7'h45 : $fwrite (fd, " 69"); + 7'h46 : $fwrite (fd, " 70"); + 7'h47 : $fwrite (fd, " 71"); + 7'h48 : $fwrite (fd, " 72"); + 7'h49 : $fwrite (fd, " 73"); + 7'h4a : $fwrite (fd, " 74"); + 7'h4b : $fwrite (fd, " 75"); + 7'h4c : $fwrite (fd, " 76"); + 7'h4d : $fwrite (fd, " 77"); + 7'h4e : $fwrite (fd, " 78"); + 7'h4f : $fwrite (fd, " 79"); + 7'h50 : $fwrite (fd, " 80"); + 7'h51 : $fwrite (fd, " 81"); + 7'h52 : $fwrite (fd, " 82"); + 7'h53 : $fwrite (fd, " 83"); + 7'h54 : $fwrite (fd, " 84"); + 7'h55 : $fwrite (fd, " 85"); + 7'h56 : $fwrite (fd, " 86"); + 7'h57 : $fwrite (fd, " 87"); + 7'h58 : $fwrite (fd, " 88"); + 7'h59 : $fwrite (fd, " 89"); + 7'h5a : $fwrite (fd, " 90"); + 7'h5b : $fwrite (fd, " 91"); + 7'h5c : $fwrite (fd, " 92"); + 7'h5d : $fwrite (fd, " 93"); + 7'h5e : $fwrite (fd, " 94"); + 7'h5f : $fwrite (fd, " 95"); + 7'h60 : $fwrite (fd, " 96"); + 7'h61 : $fwrite (fd, " 97"); + 7'h62 : $fwrite (fd, " 98"); + 7'h63 : $fwrite (fd, " 99"); + 7'h64 : $fwrite (fd, " 100"); + 7'h65 : $fwrite (fd, " 101"); + 7'h66 : $fwrite (fd, " 102"); + 7'h67 : $fwrite (fd, " 103"); + 7'h68 : $fwrite (fd, " 104"); + 7'h69 : $fwrite (fd, " 105"); + 7'h6a : $fwrite (fd, " 106"); + 7'h6b : $fwrite (fd, " 107"); + 7'h6c : $fwrite (fd, " 108"); + 7'h6d : $fwrite (fd, " 109"); + 7'h6e : $fwrite (fd, " 110"); + 7'h6f : $fwrite (fd, " 111"); + 7'h70 : $fwrite (fd, " 112"); + 7'h71 : $fwrite (fd, " 113"); + 7'h72 : $fwrite (fd, " 114"); + 7'h73 : $fwrite (fd, " 115"); + 7'h74 : $fwrite (fd, " 116"); + 7'h75 : $fwrite (fd, " 117"); + 7'h76 : $fwrite (fd, " 118"); + 7'h77 : $fwrite (fd, " 119"); + 7'h78 : $fwrite (fd, " 120"); + 7'h79 : $fwrite (fd, " 121"); + 7'h7a : $fwrite (fd, " 122"); + 7'h7b : $fwrite (fd, " 123"); + 7'h7c : $fwrite (fd, " 124"); + 7'h7d : $fwrite (fd, " 125"); + 7'h7e : $fwrite (fd, " 126"); + 7'h7f : $fwrite (fd, " 127"); + default:$fwrite (fd, " 128"); + endcase + end + endtask + + task ozonerb; + input [5:0] rb; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (rb[5:0]) + 6'h10, + 6'h17, + 6'h1e, + 6'h1f: $fwrite (fd, " 129"); + default: ozonerab({1'b1, rb}, fd); + endcase + end + endtask + + task ozonef3f4_iext; + input [1:0] foo; + input [15:0] im16; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo) + 2'h0 : + begin + skyway({4{im16[15]}}, fd); + skyway({4{im16[15]}}, fd); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + $fwrite (fd, " 130"); + end + 2'h1 : + begin + $fwrite (fd, " 131"); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + end + 2'h2 : + begin + skyway({4{im16[15]}}, fd); + skyway({4{im16[15]}}, fd); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + $fwrite (fd, " 132"); + end + 2'h3 : + begin + $fwrite (fd, " 133"); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + end + endcase + end + endtask + + task skyway; + input [ 3:0] hex; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (hex) + 4'h0 : $fwrite (fd, " 134"); + 4'h1 : $fwrite (fd, " 135"); + 4'h2 : $fwrite (fd, " 136"); + 4'h3 : $fwrite (fd, " 137"); + 4'h4 : $fwrite (fd, " 138"); + 4'h5 : $fwrite (fd, " 139"); + 4'h6 : $fwrite (fd, " 140"); + 4'h7 : $fwrite (fd, " 141"); + 4'h8 : $fwrite (fd, " 142"); + 4'h9 : $fwrite (fd, " 143"); + 4'ha : $fwrite (fd, " 144"); + 4'hb : $fwrite (fd, " 145"); + 4'hc : $fwrite (fd, " 146"); + 4'hd : $fwrite (fd, " 147"); + 4'he : $fwrite (fd, " 148"); + 4'hf : $fwrite (fd, " 149"); + endcase + end + endtask + + task ozonesr; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[11: 9]) + 3'h0 : $fwrite (fd, " 158"); + 3'h1 : $fwrite (fd, " 159"); + 3'h2 : $fwrite (fd, " 160"); + 3'h3 : $fwrite (fd, " 161"); + 3'h4 : $fwrite (fd, " 162"); + 3'h5 : $fwrite (fd, " 163"); + 3'h6 : $fwrite (fd, " 164"); + 3'h7 : $fwrite (fd, " 165"); + endcase + end + endtask + + task ozonejk; + input k; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + if (k) + $fwrite (fd, " 166"); + else + $fwrite (fd, " 167"); + end + endtask + + task ozoneae; + input [ 2:0] ae; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (ae) + 3'b000 : $fwrite (fd, " 168"); + 3'b001 : $fwrite (fd, " 169"); + 3'b010 : $fwrite (fd, " 170"); + 3'b011 : $fwrite (fd, " 171"); + 3'b100 : $fwrite (fd, " 172"); + 3'b101 : $fwrite (fd, " 173"); + 3'b110 : $fwrite (fd, " 174"); + 3'b111 : $fwrite (fd, " 175"); + endcase + end + endtask + + task ozoneaee; + input [ 2:0] aee; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (aee) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : $fwrite (fd, " 176"); + 3'b000 : $fwrite (fd, " 177"); + 3'b010 : $fwrite (fd, " 178"); + 3'b100 : $fwrite (fd, " 179"); + 3'b110 : $fwrite (fd, " 180"); + endcase + end + endtask + + task ozoneape; + input [ 2:0] ape; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (ape) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : $fwrite (fd, " 181"); + 3'b000 : $fwrite (fd, " 182"); + 3'b010 : $fwrite (fd, " 183"); + 3'b100 : $fwrite (fd, " 184"); + 3'b110 : $fwrite (fd, " 185"); + endcase + end + endtask + + task ozonef1; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[24:21]) + 4'h0 : + if (foo[26]) + $fwrite (fd, " 186"); + else + $fwrite (fd, " 187"); + 4'h1 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 188"); + 2'b01 : $fwrite (fd, " 189"); + 2'b10 : $fwrite (fd, " 190"); + 2'b11 : $fwrite (fd, " 191"); + endcase + 4'h2 : $fwrite (fd, " 192"); + 4'h3 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 193"); + 2'b01 : $fwrite (fd, " 194"); + 2'b10 : $fwrite (fd, " 195"); + 2'b11 : $fwrite (fd, " 196"); + endcase + 4'h4 : + if (foo[26]) + $fwrite (fd, " 197"); + else + $fwrite (fd, " 198"); + 4'h5 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 199"); + 2'b01 : $fwrite (fd, " 200"); + 2'b10 : $fwrite (fd, " 201"); + 2'b11 : $fwrite (fd, " 202"); + endcase + 4'h6 : $fwrite (fd, " 203"); + 4'h7 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 204"); + 2'b01 : $fwrite (fd, " 205"); + 2'b10 : $fwrite (fd, " 206"); + 2'b11 : $fwrite (fd, " 207"); + endcase + 4'h8 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 208"); + 2'b01 : $fwrite (fd, " 209"); + 2'b10 : $fwrite (fd, " 210"); + 2'b11 : $fwrite (fd, " 211"); + endcase + 4'h9 : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 212"); + 2'b01 : $fwrite (fd, " 213"); + 2'b10 : $fwrite (fd, " 214"); + 2'b11 : $fwrite (fd, " 215"); + endcase + 4'ha : + if (foo[25]) + $fwrite (fd, " 216"); + else + $fwrite (fd, " 217"); + 4'hb : + if (foo[25]) + $fwrite (fd, " 218"); + else + $fwrite (fd, " 219"); + 4'hc : + if (foo[26]) + $fwrite (fd, " 220"); + else + $fwrite (fd, " 221"); + 4'hd : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 222"); + 2'b01 : $fwrite (fd, " 223"); + 2'b10 : $fwrite (fd, " 224"); + 2'b11 : $fwrite (fd, " 225"); + endcase + 4'he : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 226"); + 2'b01 : $fwrite (fd, " 227"); + 2'b10 : $fwrite (fd, " 228"); + 2'b11 : $fwrite (fd, " 229"); + endcase + 4'hf : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 230"); + 2'b01 : $fwrite (fd, " 231"); + 2'b10 : $fwrite (fd, " 232"); + 2'b11 : $fwrite (fd, " 233"); + endcase + endcase + end + endtask + + task ozonef1e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[27:21]) + 7'h00: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 234"); + $fwrite (fd, " 235"); + end + 7'h01: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 236"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 237"); + $fwrite (fd, " 238"); + end + 7'h02: + $fwrite (fd, " 239"); + 7'h03: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 240"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 241"); + $fwrite (fd, " 242"); + end + 7'h04: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 243"); + $fwrite (fd," 244"); + end + 7'h05: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 245"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 246"); + end + 7'h06: + $fwrite (fd, " 247"); + 7'h07: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 248"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 249"); + end + 7'h08: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 250"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 251"); + end + 7'h09: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 252"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 253"); + end + 7'h0a: + begin + ozoneae(foo[17:15], fd); + $fwrite (fd," 254"); + end + 7'h0b: + begin + ozoneae(foo[17:15], fd); + $fwrite (fd," 255"); + end + 7'h0c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 256"); + end + 7'h0d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 257"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 258"); + end + 7'h0e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 259"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 260"); + end + 7'h0f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 261"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 262"); + end + 7'h10: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 263"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 264"); + $fwrite (fd, " 265"); + $fwrite (fd, " 266"); + end + 7'h11: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 267"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 268"); + $fwrite (fd, " 269"); + $fwrite (fd, " 270"); + end + 7'h12: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 271"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 272"); + $fwrite (fd, " 273"); + $fwrite (fd, " 274"); + end + 7'h13: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 275"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 276"); + $fwrite (fd, " 277"); + $fwrite (fd, " 278"); + end + 7'h14: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 279"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 280"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 281"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 282"); + $fwrite (fd, " 283"); + $fwrite (fd, " 284"); + end + 7'h15: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 285"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 286"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 287"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 288"); + $fwrite (fd, " 289"); + $fwrite (fd, " 290"); + end + 7'h16: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 291"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 292"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 293"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 294"); + $fwrite (fd, " 295"); + $fwrite (fd, " 296"); + end + 7'h17: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 297"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 298"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 299"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 300"); + $fwrite (fd, " 301"); + $fwrite (fd, " 302"); + end + 7'h18: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 303"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 304"); + $fwrite (fd, " 305"); + $fwrite (fd, " 306"); + end + 7'h19: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 307"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 308"); + $fwrite (fd, " 309"); + $fwrite (fd, " 310"); + end + 7'h1a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 311"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 312"); + $fwrite (fd, " 313"); + $fwrite (fd, " 314"); + end + 7'h1b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 315"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 316"); + $fwrite (fd, " 317"); + $fwrite (fd, " 318"); + end + 7'h1c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 319"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 320"); + $fwrite (fd, " 321"); + $fwrite (fd, " 322"); + end + 7'h1d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 323"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 324"); + $fwrite (fd, " 325"); + $fwrite (fd, " 326"); + end + 7'h1e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 327"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 328"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 329"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 330"); + $fwrite (fd, " 331"); + $fwrite (fd, " 332"); + end + 7'h1f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 333"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 334"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 335"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 336"); + $fwrite (fd, " 337"); + $fwrite (fd, " 338"); + end + 7'h20: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 339"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 340"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 341"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 342"); + $fwrite (fd, " 343"); + $fwrite (fd, " 344"); + end + 7'h21: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 345"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 346"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 347"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 348"); + $fwrite (fd, " 349"); + $fwrite (fd, " 350"); + end + 7'h22: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 351"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 352"); + $fwrite (fd, " 353"); + $fwrite (fd, " 354"); + end + 7'h23: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 355"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 356"); + $fwrite (fd, " 357"); + $fwrite (fd, " 358"); + end + 7'h24: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 359"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 360"); + $fwrite (fd, " 361"); + $fwrite (fd, " 362"); + end + 7'h25: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 363"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 364"); + $fwrite (fd, " 365"); + $fwrite (fd, " 366"); + end + 7'h26: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 367"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 368"); + $fwrite (fd, " 369"); + $fwrite (fd, " 370"); + end + 7'h27: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 371"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 372"); + $fwrite (fd, " 373"); + $fwrite (fd, " 374"); + end + 7'h28: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 375"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 376"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 377"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 378"); + $fwrite (fd, " 379"); + $fwrite (fd, " 380"); + end + 7'h29: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 381"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 382"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 383"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 384"); + $fwrite (fd, " 385"); + $fwrite (fd, " 386"); + end + 7'h2a: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 387"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 388"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 389"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 390"); + $fwrite (fd, " 391"); + $fwrite (fd, " 392"); + end + 7'h2b: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 393"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 394"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 395"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 396"); + $fwrite (fd, " 397"); + $fwrite (fd, " 398"); + end + 7'h2c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 399"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 400"); + $fwrite (fd, " 401"); + $fwrite (fd, " 402"); + end + 7'h2d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 403"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 404"); + $fwrite (fd, " 405"); + $fwrite (fd, " 406"); + end + 7'h2e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 407"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 408"); + $fwrite (fd, " 409"); + $fwrite (fd, " 410"); + end + 7'h2f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 411"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 412"); + $fwrite (fd, " 413"); + $fwrite (fd, " 414"); + end + 7'h30: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 415"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 416"); + $fwrite (fd, " 417"); + $fwrite (fd, " 418"); + end + 7'h31: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 419"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 420"); + $fwrite (fd, " 421"); + $fwrite (fd, " 422"); + end + 7'h32: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 423"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 424"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 425"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 426"); + $fwrite (fd, " 427"); + $fwrite (fd, " 428"); + end + 7'h33: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 429"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 430"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 431"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 432"); + $fwrite (fd, " 433"); + $fwrite (fd, " 434"); + end + 7'h34: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 435"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 436"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 437"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 438"); + $fwrite (fd, " 439"); + $fwrite (fd, " 440"); + end + 7'h35: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 441"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 442"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 443"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 444"); + $fwrite (fd, " 445"); + $fwrite (fd, " 446"); + end + 7'h36: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 447"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 448"); + $fwrite (fd, " 449"); + $fwrite (fd, " 450"); + end + 7'h37: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 451"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 452"); + $fwrite (fd, " 453"); + $fwrite (fd, " 454"); + end + 7'h38: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 455"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 456"); + $fwrite (fd, " 457"); + end + 7'h39: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 458"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 459"); + $fwrite (fd, " 460"); + end + 7'h3a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 461"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 462"); + $fwrite (fd, " 463"); + end + 7'h3b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 464"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 465"); + $fwrite (fd, " 466"); + end + 7'h3c: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 467"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 468"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 469"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 470"); + $fwrite (fd, " 471"); + end + 7'h3d: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 472"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 473"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 474"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 475"); + $fwrite (fd, " 476"); + end + 7'h3e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 477"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 478"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 479"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 480"); + $fwrite (fd, " 481"); + end + 7'h3f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 482"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 483"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 484"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 485"); + $fwrite (fd, " 486"); + end + 7'h40: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 487"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 488"); + $fwrite (fd, " 489"); + $fwrite (fd, " 490"); + end + 7'h41: + begin + $fwrite (fd, " 491"); + $fwrite (fd, " 492"); + end + 7'h42: + begin + $fwrite (fd, " 493"); + $fwrite (fd, " 494"); + end + 7'h43: + begin + $fwrite (fd, " 495"); + $fwrite (fd, " 496"); + end + 7'h44: + begin + $fwrite (fd, " 497"); + $fwrite (fd, " 498"); + end + 7'h45: + $fwrite (fd, " 499"); + 7'h46: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 500"); + $fwrite (fd, " 501"); + $fwrite (fd, " 502"); + end + 7'h47: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 503"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 504"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 505"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 506"); + $fwrite (fd, " 507"); + $fwrite (fd, " 508"); + end + 7'h48: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 509"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 510"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 511"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 512"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 513"); + end + 7'h49: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 514"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 515"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 516"); + end + 7'h4a: + $fwrite (fd," 517"); + 7'h4b: + $fwrite (fd, " 518"); + 7'h4c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 519"); + $fwrite (fd, " 520"); + $fwrite (fd, " 521"); + end + 7'h4d: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 522"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 523"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 524"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 525"); + $fwrite (fd, " 526"); + $fwrite (fd, " 527"); + end + 7'h4e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 528"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 529"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 530"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 531"); + end + 7'h4f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 532"); + end + 7'h50: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 533"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 534"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 535"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 536"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 537"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 538"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 539"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 540"); + end + 7'h51: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 541"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 542"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 543"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 544"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 545"); + end + 7'h52: + $fwrite (fd, " 546"); + 7'h53: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 547"); + end + 7'h54: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 548"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 549"); + end + 7'h55: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 550"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 551"); + end + 7'h56: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 552"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 553"); + $fwrite (fd, " 554"); + end + 7'h57: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 555"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 556"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 557"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 558"); + end + 7'h58: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 559"); + end + 7'h59: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 560"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 561"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 562"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 563"); + end + 7'h5a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 564"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 565"); + end + 7'h5b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 566"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 567"); + end + 7'h5c: + begin + $fwrite (fd," 568"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 569"); + $fwrite (fd," 570"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 571"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 572"); + ozoneaee(foo[17:15], fd); + $fwrite (fd, " 573"); + end + 7'h5d: + begin + $fwrite (fd," 574"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 575"); + $fwrite (fd," 576"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 577"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 578"); + ozoneaee(foo[17:15], fd); + $fwrite (fd, " 579"); + end + 7'h5e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 580"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 581"); + end + 7'h5f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 582"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 583"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 584"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 585"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 586"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 587"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 588"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 589"); + end + 7'h60: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 590"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 591"); + end + 7'h61: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 592"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 593"); + end + 7'h62: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 594"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 595"); + end + 7'h63: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 596"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 597"); + end + 7'h64: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 598"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 599"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 600"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 601"); + end + 7'h65: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 602"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 603"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 604"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 605"); + end + 7'h66: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 606"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 607"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 608"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 609"); + end + 7'h67: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 610"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 611"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 612"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 613"); + end + 7'h68: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 614"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 615"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 616"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 617"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 618"); + ozoneape(foo[17:15], fd); + end + 7'h69: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 619"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 620"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 621"); + end + 7'h6a: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 622"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 623"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 624"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 625"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 626"); + ozoneae(foo[17:15], fd); + end + 7'h6b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 627"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 628"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 629"); + end + 7'h6c: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 630"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 631"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 632"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 633"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 634"); + ozoneae(foo[17:15], fd); + end + 7'h6d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 635"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 636"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 637"); + end + 7'h6e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 638"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 639"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 640"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 641"); + end + 7'h6f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 642"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 643"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 644"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 645"); + end + 7'h70: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 646"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 647"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 648"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 649"); + end + 7'h71: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 650"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 651"); + end + 7'h72: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 652"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 653"); + end + 7'h73: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 654"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 655"); + ozoneae(foo[17:15], fd); + end + 7'h74: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 656"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 657"); + ozoneae(foo[17:15], fd); + end + 7'h75: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 658"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 659"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 660"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 661"); + $fwrite (fd, " 662"); + $fwrite (fd, " 663"); + end + 7'h76: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 664"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 665"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 666"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 667"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 668"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 669"); + end + 7'h77: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 670"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 671"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 672"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 673"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 674"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 675"); + end + 7'h78, + 7'h79, + 7'h7a, + 7'h7b, + 7'h7c, + 7'h7d, + 7'h7e, + 7'h7f: + $fwrite (fd," 676"); + endcase + end + endtask + + task ozonef2; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[24:21]) + 4'h0 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 677"); + 2'b01 : $fwrite (fd," 678"); + 2'b10 : $fwrite (fd," 679"); + 2'b11 : $fwrite (fd," 680"); + endcase + 4'h1 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 681"); + 2'b01 : $fwrite (fd," 682"); + 2'b10 : $fwrite (fd," 683"); + 2'b11 : $fwrite (fd," 684"); + endcase + 4'h2 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 685"); + 2'b01 : $fwrite (fd," 686"); + 2'b10 : $fwrite (fd," 687"); + 2'b11 : $fwrite (fd," 688"); + endcase + 4'h3 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 689"); + 2'b01 : $fwrite (fd," 690"); + 2'b10 : $fwrite (fd," 691"); + 2'b11 : $fwrite (fd," 692"); + endcase + 4'h4 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 693"); + 2'b01 : $fwrite (fd," 694"); + 2'b10 : $fwrite (fd," 695"); + 2'b11 : $fwrite (fd," 696"); + endcase + 4'h5 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 697"); + 2'b01 : $fwrite (fd," 698"); + 2'b10 : $fwrite (fd," 699"); + 2'b11 : $fwrite (fd," 700"); + endcase + 4'h6 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 701"); + 2'b01 : $fwrite (fd," 702"); + 2'b10 : $fwrite (fd," 703"); + 2'b11 : $fwrite (fd," 704"); + endcase + 4'h7 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 705"); + 2'b01 : $fwrite (fd," 706"); + 2'b10 : $fwrite (fd," 707"); + 2'b11 : $fwrite (fd," 708"); + endcase + 4'h8 : + if (foo[26]) + $fwrite (fd," 709"); + else + $fwrite (fd," 710"); + 4'h9 : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 711"); + 2'b01 : $fwrite (fd," 712"); + 2'b10 : $fwrite (fd," 713"); + 2'b11 : $fwrite (fd," 714"); + endcase + 4'ha : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 715"); + 2'b01 : $fwrite (fd," 716"); + 2'b10 : $fwrite (fd," 717"); + 2'b11 : $fwrite (fd," 718"); + endcase + 4'hb : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 719"); + 2'b01 : $fwrite (fd," 720"); + 2'b10 : $fwrite (fd," 721"); + 2'b11 : $fwrite (fd," 722"); + endcase + 4'hc : + if (foo[26]) + $fwrite (fd," 723"); + else + $fwrite (fd," 724"); + 4'hd : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 725"); + 2'b01 : $fwrite (fd," 726"); + 2'b10 : $fwrite (fd," 727"); + 2'b11 : $fwrite (fd," 728"); + endcase + 4'he : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 729"); + 2'b01 : $fwrite (fd," 730"); + 2'b10 : $fwrite (fd," 731"); + 2'b11 : $fwrite (fd," 732"); + endcase + 4'hf : + case (foo[26:25]) + 2'b00 : $fwrite (fd," 733"); + 2'b01 : $fwrite (fd," 734"); + 2'b10 : $fwrite (fd," 735"); + 2'b11 : $fwrite (fd," 736"); + endcase + endcase + end + endtask + + task ozonef2e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + casez (foo[25:21]) + 5'h00 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 737"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 738"); + end + 5'h01 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 739"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 740"); + end + 5'h02 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 741"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 742"); + end + 5'h03 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 743"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 744"); + end + 5'h04 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 745"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 746"); + end + 5'h05 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 747"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 748"); + end + 5'h06 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 749"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 750"); + end + 5'h07 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 751"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 752"); + end + 5'h08 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 753"); + if (foo[ 6]) + $fwrite (fd," 754"); + else + $fwrite (fd," 755"); + end + 5'h09 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 756"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 757"); + end + 5'h0a : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 758"); + ozoneae(foo[17:15], fd); + end + 5'h0b : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 759"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 760"); + end + 5'h0c : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 761"); + end + 5'h0d : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 762"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 763"); + end + 5'h0e : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 764"); + ozoneae(foo[17:15], fd); + end + 5'h0f : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 765"); + ozoneae(foo[17:15], fd); + end + 5'h10 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 766"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 767"); + end + 5'h11 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 768"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 769"); + end + 5'h18 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 770"); + if (foo[ 6]) + $fwrite (fd," 771"); + else + $fwrite (fd," 772"); + end + 5'h1a : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 773"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 774"); + end + 5'h1b : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 775"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 776"); + if (foo[ 6]) + $fwrite (fd," 777"); + else + $fwrite (fd," 778"); + $fwrite (fd," 779"); + end + 5'h1c : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 780"); + end + 5'h1d : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 781"); + if (foo[ 6]) + $fwrite (fd," 782"); + else + $fwrite (fd," 783"); + $fwrite (fd," 784"); + end + 5'h1e : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 785"); + if (foo[ 6]) + $fwrite (fd," 786"); + else + $fwrite (fd," 787"); + $fwrite (fd," 788"); + end + 5'h1f : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 789"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 790"); + if (foo[ 6]) + $fwrite (fd," 791"); + else + $fwrite (fd," 792"); + $fwrite (fd," 793"); + end + default : + $fwrite (fd," 794"); + endcase + end + endtask + + task ozonef3e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[25:21]) + 5'h00, + 5'h01, + 5'h02: + begin + ozoneae(foo[20:18], fd); + case (foo[22:21]) + 2'h0: $fwrite (fd," 795"); + 2'h1: $fwrite (fd," 796"); + 2'h2: $fwrite (fd," 797"); + endcase + ozoneae(foo[17:15], fd); + $fwrite (fd," 798"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + $fwrite (fd," 799"); + end + 5'h08, + 5'h09, + 5'h0d, + 5'h0e, + 5'h0f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 800"); + ozoneae(foo[17:15], fd); + case (foo[23:21]) + 3'h0: $fwrite (fd," 801"); + 3'h1: $fwrite (fd," 802"); + 3'h5: $fwrite (fd," 803"); + 3'h6: $fwrite (fd," 804"); + 3'h7: $fwrite (fd," 805"); + endcase + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + end + 5'h0a, + 5'h0b: + begin + ozoneae(foo[17:15], fd); + if (foo[21]) + $fwrite (fd," 806"); + else + $fwrite (fd," 807"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + end + 5'h0c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 808"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + $fwrite (fd," 809"); + ozoneae(foo[17:15], fd); + end + 5'h10, + 5'h11, + 5'h12, + 5'h13: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 810"); + ozoneae(foo[17:15], fd); + case (foo[22:21]) + 2'h0, + 2'h2: + $fwrite (fd," 811"); + 2'h1, + 2'h3: + $fwrite (fd," 812"); + endcase + ozoneae(foo[ 8: 6], fd); + $fwrite (fd," 813"); + ozoneae((foo[20:18]+1), fd); + $fwrite (fd," 814"); + ozoneae((foo[17:15]+1), fd); + case (foo[22:21]) + 2'h0, + 2'h3: + $fwrite (fd," 815"); + 2'h1, + 2'h2: + $fwrite (fd," 816"); + endcase + ozoneae((foo[ 8: 6]+1), fd); + end + 5'h18: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 817"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 818"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd," 819"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 820"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 821"); + ozoneae(foo[ 8: 6], fd); + end + default : + $fwrite (fd," 822"); + endcase + end + endtask + task ozonef3e_te; + input [ 2:0] te; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (te) + 3'b100 : $fwrite (fd, " 823"); + 3'b101 : $fwrite (fd, " 824"); + 3'b110 : $fwrite (fd, " 825"); + default: $fwrite (fd, " 826"); + endcase + end + endtask + task ozonearm; + input [ 2:0] ate; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (ate) + 3'b000 : $fwrite (fd, " 827"); + 3'b001 : $fwrite (fd, " 828"); + 3'b010 : $fwrite (fd, " 829"); + 3'b011 : $fwrite (fd, " 830"); + 3'b100 : $fwrite (fd, " 831"); + 3'b101 : $fwrite (fd, " 832"); + 3'b110 : $fwrite (fd, " 833"); + 3'b111 : $fwrite (fd, " 834"); + endcase + end + endtask + task ozonebmuop; + input [ 4:0] f4; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (f4[ 4:0]) + 5'h00, + 5'h04 : + $fwrite (fd, " 835"); + 5'h01, + 5'h05 : + $fwrite (fd, " 836"); + 5'h02, + 5'h06 : + $fwrite (fd, " 837"); + 5'h03, + 5'h07 : + $fwrite (fd, " 838"); + 5'h08, + 5'h18 : + $fwrite (fd, " 839"); + 5'h09, + 5'h19 : + $fwrite (fd, " 840"); + 5'h0a, + 5'h1a : + $fwrite (fd, " 841"); + 5'h0b : + $fwrite (fd, " 842"); + 5'h1b : + $fwrite (fd, " 843"); + 5'h0c, + 5'h1c : + $fwrite (fd, " 844"); + 5'h0d, + 5'h1d : + $fwrite (fd, " 845"); + 5'h1e : + $fwrite (fd, " 846"); + endcase + end + endtask + task ozonef3; + input [ 31:0] foo; + input [`FD_BITS] fd; + reg nacho; + // verilator no_inline_task + begin : f3_body + nacho = 1'b0; + case (foo[24:21]) + 4'h0: + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 847"); + 2'b01 : $fwrite (fd, " 848"); + 2'b10 : $fwrite (fd, " 849"); + 2'b11 : $fwrite (fd, " 850"); + endcase + 4'h1: + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 851"); + 2'b01 : $fwrite (fd, " 852"); + 2'b10 : $fwrite (fd, " 853"); + 2'b11 : $fwrite (fd, " 854"); + endcase + 4'h2: + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 855"); + 2'b01 : $fwrite (fd, " 856"); + 2'b10 : $fwrite (fd, " 857"); + 2'b11 : $fwrite (fd, " 858"); + endcase + 4'h8, + 4'h9, + 4'hd, + 4'he, + 4'hf : + case (foo[26:25]) + 2'b00 : $fwrite (fd, " 859"); + 2'b01 : $fwrite (fd, " 860"); + 2'b10 : $fwrite (fd, " 861"); + 2'b11 : $fwrite (fd, " 862"); + endcase + 4'ha, + 4'hb : + if (foo[25]) + $fwrite (fd, " 863"); + else + $fwrite (fd, " 864"); + 4'hc : + if (foo[26]) + $fwrite (fd, " 865"); + else + $fwrite (fd, " 866"); + default : + begin + $fwrite (fd, " 867"); + nacho = 1'b1; + end + endcase + if (~nacho) + begin + case (foo[24:21]) + 4'h8 : + $fwrite (fd, " 868"); + 4'h9 : + $fwrite (fd, " 869"); + 4'ha, + 4'he : + $fwrite (fd, " 870"); + 4'hb, + 4'hf : + $fwrite (fd, " 871"); + 4'hd : + $fwrite (fd, " 872"); + endcase + if (foo[20]) + case (foo[18:16]) + 3'b000 : $fwrite (fd, " 873"); + 3'b100 : $fwrite (fd, " 874"); + default: $fwrite (fd, " 875"); + endcase + else + ozoneae(foo[18:16], fd); + if (foo[24:21] === 4'hc) + if (foo[25]) + $fwrite (fd, " 876"); + else + $fwrite (fd, " 877"); + case (foo[24:21]) + 4'h0, + 4'h1, + 4'h2: + $fwrite (fd, " 878"); + endcase + end + end + endtask + task ozonerx; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[19:18]) + 2'h0 : $fwrite (fd, " 879"); + 2'h1 : $fwrite (fd, " 880"); + 2'h2 : $fwrite (fd, " 881"); + 2'h3 : $fwrite (fd, " 882"); + endcase + case (foo[17:16]) + 2'h1 : $fwrite (fd, " 883"); + 2'h2 : $fwrite (fd, " 884"); + 2'h3 : $fwrite (fd, " 885"); + endcase + end + endtask + task ozonerme; + input [ 2:0] rme; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (rme) + 3'h0 : $fwrite (fd, " 886"); + 3'h1 : $fwrite (fd, " 887"); + 3'h2 : $fwrite (fd, " 888"); + 3'h3 : $fwrite (fd, " 889"); + 3'h4 : $fwrite (fd, " 890"); + 3'h5 : $fwrite (fd, " 891"); + 3'h6 : $fwrite (fd, " 892"); + 3'h7 : $fwrite (fd, " 893"); + endcase + end + endtask + task ozoneye; + input [5:0] ye; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + $fwrite (fd, " 894"); + ozonerme(ye[5:3], fd); + case ({ye[ 2:0], l}) + 4'h2, + 4'ha: $fwrite (fd, " 895"); + 4'h4, + 4'hb: $fwrite (fd, " 896"); + 4'h6, + 4'he: $fwrite (fd, " 897"); + 4'h8, + 4'hc: $fwrite (fd, " 898"); + endcase + end + endtask + task ozonef1e_ye; + input [5:0] ye; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + $fwrite (fd, " 899"); + ozonerme(ye[5:3], fd); + ozonef1e_inc_dec(ye[5:0], l , fd); + end + endtask + task ozonef1e_h; + input [ 2:0] e; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + if (e[ 2:0] <= 3'h4) + $fwrite (fd, " 900"); + end + endtask + task ozonef1e_inc_dec; + input [5:0] ye; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case ({ye[ 2:0], l}) + 4'h2, + 4'h3, + 4'ha: $fwrite (fd, " 901"); + 4'h4, + 4'h5, + 4'hb: $fwrite (fd, " 902"); + 4'h6, + 4'h7, + 4'he: $fwrite (fd, " 903"); + 4'h8, + 4'h9, + 4'hc: $fwrite (fd, " 904"); + 4'hf: $fwrite (fd, " 905"); + endcase + end + endtask + task ozonef1e_hl; + input [ 2:0] e; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case ({e[ 2:0], l}) + 4'h0, + 4'h2, + 4'h4, + 4'h6, + 4'h8: $fwrite (fd, " 906"); + 4'h1, + 4'h3, + 4'h5, + 4'h7, + 4'h9: $fwrite (fd, " 907"); + endcase + end + endtask + task ozonexe; + input [ 3:0] xe; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (xe[3]) + 1'b0 : $fwrite (fd, " 908"); + 1'b1 : $fwrite (fd, " 909"); + endcase + case (xe[ 2:0]) + 3'h1, + 3'h5: $fwrite (fd, " 910"); + 3'h2, + 3'h6: $fwrite (fd, " 911"); + 3'h3, + 3'h7: $fwrite (fd, " 912"); + 3'h4: $fwrite (fd, " 913"); + endcase + end + endtask + task ozonerp; + input [ 2:0] rp; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (rp) + 3'h0 : $fwrite (fd, " 914"); + 3'h1 : $fwrite (fd, " 915"); + 3'h2 : $fwrite (fd, " 916"); + 3'h3 : $fwrite (fd, " 917"); + 3'h4 : $fwrite (fd, " 918"); + 3'h5 : $fwrite (fd, " 919"); + 3'h6 : $fwrite (fd, " 920"); + 3'h7 : $fwrite (fd, " 921"); + endcase + end + endtask + task ozonery; + input [ 3:0] ry; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (ry) + 4'h0 : $fwrite (fd, " 922"); + 4'h1 : $fwrite (fd, " 923"); + 4'h2 : $fwrite (fd, " 924"); + 4'h3 : $fwrite (fd, " 925"); + 4'h4 : $fwrite (fd, " 926"); + 4'h5 : $fwrite (fd, " 927"); + 4'h6 : $fwrite (fd, " 928"); + 4'h7 : $fwrite (fd, " 929"); + 4'h8 : $fwrite (fd, " 930"); + 4'h9 : $fwrite (fd, " 931"); + 4'ha : $fwrite (fd, " 932"); + 4'hb : $fwrite (fd, " 933"); + 4'hc : $fwrite (fd, " 934"); + 4'hd : $fwrite (fd, " 935"); + 4'he : $fwrite (fd, " 936"); + 4'hf : $fwrite (fd, " 937"); + endcase + end + endtask + task ozonearx; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[1:0]) + 2'h0 : $fwrite (fd, " 938"); + 2'h1 : $fwrite (fd, " 939"); + 2'h2 : $fwrite (fd, " 940"); + 2'h3 : $fwrite (fd, " 941"); + endcase + end + endtask + task ozonef3f4imop; + input [ 4:0] f3f4iml; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + casez (f3f4iml) + 5'b000??: $fwrite (fd, " 942"); + 5'b001??: $fwrite (fd, " 943"); + 5'b?10??: $fwrite (fd, " 944"); + 5'b0110?: $fwrite (fd, " 945"); + 5'b01110: $fwrite (fd, " 946"); + 5'b01111: $fwrite (fd, " 947"); + 5'b10???: $fwrite (fd, " 948"); + 5'b11100: $fwrite (fd, " 949"); + 5'b11101: $fwrite (fd, " 950"); + 5'b11110: $fwrite (fd, " 951"); + 5'b11111: $fwrite (fd, " 952"); + endcase + end + endtask + task ozonecon; + input [ 4:0] con; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (con) + 5'h00 : $fwrite (fd, " 953"); + 5'h01 : $fwrite (fd, " 954"); + 5'h02 : $fwrite (fd, " 955"); + 5'h03 : $fwrite (fd, " 956"); + 5'h04 : $fwrite (fd, " 957"); + 5'h05 : $fwrite (fd, " 958"); + 5'h06 : $fwrite (fd, " 959"); + 5'h07 : $fwrite (fd, " 960"); + 5'h08 : $fwrite (fd, " 961"); + 5'h09 : $fwrite (fd, " 962"); + 5'h0a : $fwrite (fd, " 963"); + 5'h0b : $fwrite (fd, " 964"); + 5'h0c : $fwrite (fd, " 965"); + 5'h0d : $fwrite (fd, " 966"); + 5'h0e : $fwrite (fd, " 967"); + 5'h0f : $fwrite (fd, " 968"); + 5'h10 : $fwrite (fd, " 969"); + 5'h11 : $fwrite (fd, " 970"); + 5'h12 : $fwrite (fd, " 971"); + 5'h13 : $fwrite (fd, " 972"); + 5'h14 : $fwrite (fd, " 973"); + 5'h15 : $fwrite (fd, " 974"); + 5'h16 : $fwrite (fd, " 975"); + 5'h17 : $fwrite (fd, " 976"); + 5'h18 : $fwrite (fd, " 977"); + 5'h19 : $fwrite (fd, " 978"); + 5'h1a : $fwrite (fd, " 979"); + 5'h1b : $fwrite (fd, " 980"); + 5'h1c : $fwrite (fd, " 981"); + 5'h1d : $fwrite (fd, " 982"); + 5'h1e : $fwrite (fd, " 983"); + 5'h1f : $fwrite (fd, " 984"); + endcase + end + endtask + task ozonedr; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[ 9: 6]) + 4'h0 : $fwrite (fd, " 985"); + 4'h1 : $fwrite (fd, " 986"); + 4'h2 : $fwrite (fd, " 987"); + 4'h3 : $fwrite (fd, " 988"); + 4'h4 : $fwrite (fd, " 989"); + 4'h5 : $fwrite (fd, " 990"); + 4'h6 : $fwrite (fd, " 991"); + 4'h7 : $fwrite (fd, " 992"); + 4'h8 : $fwrite (fd, " 993"); + 4'h9 : $fwrite (fd, " 994"); + 4'ha : $fwrite (fd, " 995"); + 4'hb : $fwrite (fd, " 996"); + 4'hc : $fwrite (fd, " 997"); + 4'hd : $fwrite (fd, " 998"); + 4'he : $fwrite (fd, " 999"); + 4'hf : $fwrite (fd, " 1000"); + endcase + end + endtask + task ozoneshift; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo[ 4: 3]) + 2'h0 : $fwrite (fd, " 1001"); + 2'h1 : $fwrite (fd, " 1002"); + 2'h2 : $fwrite (fd, " 1003"); + 2'h3 : $fwrite (fd, " 1004"); + endcase + end + endtask + task ozoneacc; + input foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo) + 2'h0 : $fwrite (fd, " 1005"); + 2'h1 : $fwrite (fd, " 1006"); + endcase + end + endtask + task ozonehl; + input foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin + case (foo) + 2'h0 : $fwrite (fd, " 1007"); + 2'h1 : $fwrite (fd, " 1008"); + endcase + end + endtask + task dude; + input [`FD_BITS] fd; + // verilator no_inline_task + $fwrite(fd," dude"); + endtask + + task big_case; + input [ `FD_BITS] fd; + input [ 31:0] foo; + // verilator no_inline_task + begin + $fwrite(fd," 1009"); + if (&foo === 1'bx) + $fwrite(fd, " 1010"); + else + casez ( {foo[31:26], foo[19:15], foo[5:0]} ) + 17'b00_111?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1011"); + ozoneacc(~foo[26], fd); + ozonehl(foo[20], fd); + $fwrite (fd, " 1012"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1013"); + end + 17'b01_001?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1014"); + ozonerx(foo, fd); + $fwrite (fd, " 1015"); + $fwrite (fd, " 1016:%x", foo[20]); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1017"); + end + 17'b10_100?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1018"); + ozonerx(foo, fd); + $fwrite (fd, " 1019"); + $fwrite (fd, " 1020"); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1021"); + end + 17'b10_101?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1022"); + if (foo[20]) + begin + $fwrite (fd, " 1023"); + ozoneacc(foo[18], fd); + $fwrite (fd, " 1024"); + $fwrite (fd, " 1025"); + if (foo[19]) + $fwrite (fd, " 1026"); + else + $fwrite (fd, " 1027"); + end + else + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1028"); + end + 17'b10_110?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1029"); + $fwrite (fd, " 1030"); + ozonehl(foo[20], fd); + $fwrite (fd, " 1031"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1032"); + end + 17'b10_111?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1033"); + $fwrite (fd, " 1034"); + ozonehl(foo[20], fd); + $fwrite (fd, " 1035"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1036"); + end + 17'b11_001?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1037"); + ozonerx(foo, fd); + $fwrite (fd, " 1038"); + $fwrite (fd, " 1039"); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1040"); + end + 17'b11_111?_?_????_??_???? : + begin + ozonef1(foo, fd); + $fwrite (fd, " 1041"); + $fwrite (fd, " 1042"); + ozonerx(foo, fd); + $fwrite (fd, " 1043"); + if (foo[20]) + $fwrite (fd, " 1044"); + else + $fwrite (fd, " 1045"); + dude(fd); + $fwrite (fd, " 1046"); + end + 17'b00_10??_?_????_?1_1111 : + casez (foo[11: 5]) + 7'b??_0_010_0: + begin + $fwrite (fd, " 1047"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1048"); + ozonef1e(foo, fd); + dude(fd); + $fwrite (fd, " 1049"); + end + 7'b00_?_110_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1050"); + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + $fwrite (fd, " 1051"); + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + end + 2'b01: + begin + $fwrite (fd, " 1052"); + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + end + 2'b10: + begin + $fwrite (fd, " 1053"); + ozoneae(foo[14:12], fd); + end + 2'b11: $fwrite (fd, " 1054"); + endcase + dude(fd); + $fwrite (fd, " 1055"); + end + 7'b01_?_110_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1056"); + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + $fwrite (fd, " 1057"); + end + 2'b01: + begin + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + $fwrite (fd, " 1058"); + end + 2'b10: + begin + ozoneae(foo[14:12], fd); + $fwrite (fd, " 1059"); + end + 2'b11: $fwrite (fd, " 1060"); + endcase + dude(fd); + $fwrite (fd, " 1061"); + end + 7'b10_0_110_0: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1062"); + $fwrite (fd, " 1063"); + if (foo[12]) + $fwrite (fd, " 1064"); + else + ozonerab({4'b1001, foo[14:12]}, fd); + dude(fd); + $fwrite (fd, " 1065"); + end + 7'b10_0_110_1: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1066"); + if (foo[12]) + $fwrite (fd, " 1067"); + else + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1068"); + dude(fd); + $fwrite (fd, " 1069"); + end + 7'b??_?_000_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1070"); + $fwrite (fd, " 1071"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1072"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1073"); + end + 7'b??_?_100_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1074"); + $fwrite (fd, " 1075"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1076"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1077"); + end + 7'b??_?_001_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1078"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1079"); + $fwrite (fd, " 1080"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1081"); + end + 7'b??_?_011_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1082"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1083"); + $fwrite (fd, " 1084"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1085"); + end + 7'b??_?_101_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1086"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1087"); + end + endcase + 17'b00_10??_?_????_?0_0110 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1088"); + ozoneae(foo[ 8: 6], fd); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1089"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1090"); + end + 17'b00_10??_?_????_00_0111 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1091"); + if (foo[ 6]) + $fwrite (fd, " 1092"); + else + ozonerab({4'b1001, foo[ 8: 6]}, fd); + $fwrite (fd, " 1093"); + $fwrite (fd, " 1094"); + ozonerme(foo[14:12], fd); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0, fd); + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1095"); + endcase + dude(fd); + $fwrite (fd, " 1096"); + end + 17'b00_10??_?_????_?0_0100 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1097"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1098"); + ozoneae(foo[ 8: 6], fd); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1099"); + end + 17'b00_10??_?_????_10_0111 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1100"); + $fwrite (fd, " 1101"); + ozonerme(foo[14:12], fd); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0, fd); + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1102"); + endcase + $fwrite (fd, " 1103"); + if (foo[ 6]) + $fwrite (fd, " 1104"); + else + ozonerab({4'b1001, foo[ 8: 6]}, fd); + dude(fd); + $fwrite (fd, " 1105"); + end + 17'b00_10??_?_????_?0_1110 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1106"); + case (foo[11:9]) + 3'h2: + begin + $fwrite (fd, " 1107"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1108"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1109"); + end + 3'h6: + begin + $fwrite (fd, " 1110"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1111"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1112"); + end + 3'h0: + begin + $fwrite (fd, " 1113"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1114"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1115"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1116"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h1: + begin + $fwrite (fd, " 1117"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1118"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1119"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1120"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h4: + begin + $fwrite (fd, " 1121"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1122"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1123"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1124"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h5: + begin + $fwrite (fd, " 1125"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1126"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1127"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1128"); + else + ozonexe(foo[ 8: 5], fd); + end + endcase + dude(fd); + $fwrite (fd, " 1129"); + end + 17'b00_10??_?_????_?0_1111 : + casez (foo[14: 9]) + 6'b001_10_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1130"); + $fwrite (fd, " 1131"); + ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); + $fwrite (fd, " 1132"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1133"); + end + 6'b???_11_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1134"); + ozoneae(foo[14:12], fd); + ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); + $fwrite (fd, " 1135"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1136"); + end + 6'b000_10_1, + 6'b010_10_1, + 6'b100_10_1, + 6'b110_10_1: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1137"); + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1138"); + if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) + $fwrite (fd, " 1139"); + else + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1140"); + end + 6'b000_10_0, + 6'b010_10_0, + 6'b100_10_0, + 6'b110_10_0: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1141"); + $fwrite (fd, " 1142"); + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1143"); + $fwrite (fd, " 1144"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1145"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1146"); + end + 6'b???_00_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1147"); + if (foo[ 9]) + begin + $fwrite (fd, " 1148"); + ozoneae(foo[14:12], fd); + end + else + begin + $fwrite (fd, " 1149"); + ozoneae(foo[14:12], fd); + $fwrite (fd, " 1150"); + end + $fwrite (fd, " 1151"); + $fwrite (fd, " 1152"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1153"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1154"); + end + 6'b???_01_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1155"); + ozoneae(foo[14:12], fd); + if (foo[ 9]) + $fwrite (fd, " 1156"); + else + $fwrite (fd, " 1157"); + $fwrite (fd, " 1158"); + $fwrite (fd, " 1159"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1160"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1161"); + end + 6'b011_10_0: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1162"); + case (foo[ 8: 5]) + 4'h0: $fwrite (fd, " 1163"); + 4'h1: $fwrite (fd, " 1164"); + 4'h2: $fwrite (fd, " 1165"); + 4'h3: $fwrite (fd, " 1166"); + 4'h4: $fwrite (fd, " 1167"); + 4'h5: $fwrite (fd, " 1168"); + 4'h8: $fwrite (fd, " 1169"); + 4'h9: $fwrite (fd, " 1170"); + 4'ha: $fwrite (fd, " 1171"); + 4'hb: $fwrite (fd, " 1172"); + 4'hc: $fwrite (fd, " 1173"); + 4'hd: $fwrite (fd, " 1174"); + default: $fwrite (fd, " 1175"); + endcase + dude(fd); + $fwrite (fd, " 1176"); + end + default: $fwrite (fd, " 1177"); + endcase + 17'b00_10??_?_????_?0_110? : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1178"); + $fwrite (fd, " 1179"); + ozonef1e_hl(foo[11:9], foo[0], fd); + $fwrite (fd, " 1180"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1181"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1182"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1183"); + end + 17'b00_10??_?_????_?1_110? : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1184"); + $fwrite (fd, " 1185"); + ozonef1e_hl(foo[11:9],foo[0], fd); + $fwrite (fd, " 1186"); + ozonef1e_ye(foo[14:9],foo[ 0], fd); + $fwrite (fd, " 1187"); + $fwrite (fd, " 1188"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1189"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1190"); + end + 17'b00_10??_?_????_?0_101? : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1191"); + ozonef1e_ye(foo[14:9],foo[ 0], fd); + $fwrite (fd, " 1192"); + $fwrite (fd, " 1193"); + ozonef1e_hl(foo[11:9],foo[0], fd); + $fwrite (fd, " 1194"); + $fwrite (fd, " 1195"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1196"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1197"); + end + 17'b00_10??_?_????_?0_1001 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1198"); + $fwrite (fd, " 1199"); + ozonef1e_h(foo[11:9], fd); + $fwrite (fd, " 1200"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1201"); + case (foo[ 7: 5]) + 3'h1, + 3'h2, + 3'h3: + $fwrite (fd, " 1202"); + default: + begin + $fwrite (fd, " 1203"); + $fwrite (fd, " 1204"); + ozonexe(foo[ 8: 5], fd); + end + endcase + dude(fd); + $fwrite (fd, " 1205"); + end + 17'b00_10??_?_????_?0_0101 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1206"); + case (foo[11: 9]) + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1207"); + default: + begin + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1208"); + $fwrite (fd, " 1209"); + end + endcase + $fwrite (fd, " 1210"); + $fwrite (fd, " 1211"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1212"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1213"); + end + 17'b00_10??_?_????_?1_1110 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1214"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1215"); + $fwrite (fd, " 1216"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1217"); + $fwrite (fd, " 1218"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1219"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1220"); + end + 17'b00_10??_?_????_?0_1000 : + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1221"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1222"); + $fwrite (fd, " 1223"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1224"); + $fwrite (fd, " 1225"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1226"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1227"); + end + 17'b10_01??_?_????_??_???? : + begin + if (foo[27]) + $fwrite (fd," 1228"); + else + $fwrite (fd," 1229"); + ozonecon(foo[20:16], fd); + $fwrite (fd, " 1230"); + ozonef2(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1231"); + end + 17'b00_1000_?_????_01_0011 : + if (~|foo[ 9: 8]) + begin + if (foo[ 7]) + $fwrite (fd," 1232"); + else + $fwrite (fd," 1233"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1234"); + ozonef2e(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1235"); + end + else + begin + $fwrite (fd, " 1236"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1237"); + ozonef3e(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1238"); + end + 17'b11_110?_1_????_??_???? : + begin + ozonef3(foo[31:0], fd); + dude(fd); + $fwrite(fd, " 1239"); + end + 17'b11_110?_0_????_??_???? : + begin : f4_body + casez (foo[24:20]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite (fd, " 1240"); + end + 5'b0_00??: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1241"); + ozoneacc(foo[25], fd); + ozonebmuop(foo[24:20], fd); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1242"); + dude(fd); + $fwrite(fd, " 1243"); + end + 5'b0_01??: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1244"); + ozoneacc(foo[25], fd); + ozonebmuop(foo[24:20], fd); + ozonearm(foo[18:16], fd); + dude(fd); + $fwrite(fd, " 1245"); + end + 5'b0_1011: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1246"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1247"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1248"); + dude(fd); + $fwrite(fd, " 1249"); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1250"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1251"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1252"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1253"); + dude(fd); + $fwrite(fd, " 1254"); + end + 5'b0_1111 : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1255"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1256"); + ozoneae(foo[18:16], fd); + dude(fd); + $fwrite(fd, " 1257"); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1258"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1259"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1260"); + ozonearm(foo[18:16], fd); + $fwrite (fd, " 1261"); + dude(fd); + $fwrite(fd, " 1262"); + end + endcase + end + 17'b11_100?_?_????_??_???? : + casez (foo[23:19]) + 5'b111??, + 5'b0111?: + begin + ozoneae(foo[26:24], fd); + $fwrite (fd, " 1263"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1264"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1265"); + skyway(foo[15:12], fd); + skyway(foo[11: 8], fd); + skyway(foo[ 7: 4], fd); + skyway(foo[ 3:0], fd); + $fwrite (fd, " 1266"); + dude(fd); + $fwrite(fd, " 1267"); + end + 5'b?0???, + 5'b110??: + begin + ozoneae(foo[26:24], fd); + $fwrite (fd, " 1268"); + if (foo[23:21] == 3'b100) + $fwrite (fd, " 1269"); + ozoneae(foo[18:16], fd); + if (foo[19]) + $fwrite (fd, " 1270"); + else + $fwrite (fd, " 1271"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1272"); + ozonef3f4_iext(foo[20:19], foo[15:0], fd); + dude(fd); + $fwrite(fd, " 1273"); + end + 5'b010??, + 5'b0110?: + begin + ozoneae(foo[18:16], fd); + if (foo[19]) + $fwrite (fd, " 1274"); + else + $fwrite (fd, " 1275"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1276"); + ozonef3f4_iext(foo[20:19], foo[15:0], fd); + dude(fd); + $fwrite(fd, " 1277"); + end + endcase + 17'b00_1000_?_????_11_0011 : + begin + $fwrite (fd," 1278"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1279"); + casez (foo[25:21]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite(fd, " 1280"); + end + 5'b0_00??: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1281"); + ozoneae(foo[17:15], fd); + ozonebmuop(foo[25:21], fd); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1282"); + dude(fd); + $fwrite(fd, " 1283"); + end + 5'b0_01??: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1284"); + ozoneae(foo[17:15], fd); + ozonebmuop(foo[25:21], fd); + ozonearm(foo[ 8: 6], fd); + dude(fd); + $fwrite(fd, " 1285"); + end + 5'b0_1011: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1286"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1287"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1288"); + dude(fd); + $fwrite(fd, " 1289"); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1290"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1291"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1292"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1293"); + dude(fd); + $fwrite(fd, " 1294"); + end + 5'b0_1111 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1295"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1296"); + ozoneae(foo[ 8: 6], fd); + dude(fd); + $fwrite(fd, " 1297"); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1298"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1299"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1300"); + ozonearm(foo[ 8: 6], fd); + $fwrite (fd, " 1301"); + dude(fd); + $fwrite(fd, " 1302"); + end + endcase + end + 17'b00_0010_?_????_??_???? : + begin + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1303"); + skyway(foo[19:16], fd); + dude(fd); + $fwrite(fd, " 1304"); + end + 17'b00_01??_?_????_??_???? : + begin + if (foo[27]) + begin + $fwrite (fd, " 1305"); + if (foo[26]) + $fwrite (fd, " 1306"); + else + $fwrite (fd, " 1307"); + skyway(foo[19:16], fd); + $fwrite (fd, " 1308"); + ozonerab({1'b0, foo[25:20]}, fd); + end + else + begin + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1309"); + if (foo[26]) + $fwrite (fd, " 1310"); + else + $fwrite (fd, " 1311"); + skyway(foo[19:16], fd); + $fwrite (fd, " 1312"); + end + dude(fd); + $fwrite(fd, " 1313"); + end + 17'b01_000?_?_????_??_???? : + begin + if (foo[26]) + begin + ozonerb(foo[25:20], fd); + $fwrite (fd, " 1314"); + ozoneae(foo[18:16], fd); + ozonehl(foo[19], fd); + end + else + begin + ozoneae(foo[18:16], fd); + ozonehl(foo[19], fd); + $fwrite (fd, " 1315"); + ozonerb(foo[25:20], fd); + end + dude(fd); + $fwrite(fd, " 1316"); + end + 17'b01_10??_?_????_??_???? : + begin + if (foo[27]) + begin + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1317"); + ozonerx(foo, fd); + end + else + begin + ozonerx(foo, fd); + $fwrite (fd, " 1318"); + ozonerab({1'b0, foo[25:20]}, fd); + end + dude(fd); + $fwrite(fd, " 1319"); + end + 17'b11_101?_?_????_??_???? : + begin + ozonerab (foo[26:20], fd); + $fwrite (fd, " 1320"); + skyway(foo[19:16], fd); + skyway(foo[15:12], fd); + skyway(foo[11: 8], fd); + skyway(foo[ 7: 4], fd); + skyway(foo[ 3: 0], fd); + dude(fd); + $fwrite(fd, " 1321"); + end + 17'b11_0000_?_????_??_???? : + begin + casez (foo[25:23]) + 3'b00?: + begin + ozonerab(foo[22:16], fd); + $fwrite (fd, " 1322"); + end + 3'b01?: + begin + $fwrite (fd, " 1323"); + if (foo[22:16]>=7'h60) + $fwrite (fd, " 1324"); + else + ozonerab(foo[22:16], fd); + end + 3'b110: + $fwrite (fd, " 1325"); + 3'b10?: + begin + $fwrite (fd, " 1326"); + if (foo[22:16]>=7'h60) + $fwrite (fd, " 1327"); + else + ozonerab(foo[22:16], fd); + end + 3'b111: + begin + $fwrite (fd, " 1328"); + ozonerab(foo[22:16], fd); + $fwrite (fd, " 1329"); + end + endcase + dude(fd); + $fwrite(fd, " 1330"); + end + 17'b00_10??_?_????_?1_0000 : + begin + if (foo[27]) + begin + $fwrite (fd, " 1331"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1332"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + $fwrite (fd, " 1333"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1334"); + else + ozonerab(foo[26:20], fd); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1335"); + $fwrite (fd, " 1336"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1337"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + $fwrite (fd, " 1338"); + end + dude(fd); + $fwrite(fd, " 1339"); + end + 17'b00_101?_1_0000_?1_0010 : + if (~|foo[11: 7]) + begin + if (foo[ 6]) + begin + $fwrite (fd, " 1340"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1341"); + ozonejk(foo[ 5], fd); + $fwrite (fd, " 1342"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1343"); + else + ozonerab(foo[26:20], fd); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1344"); + $fwrite (fd, " 1345"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1346"); + ozonejk(foo[ 5], fd); + $fwrite (fd, " 1347"); + end + dude(fd); + $fwrite(fd, " 1348"); + end + else + $fwrite(fd, " 1349"); + 17'b00_100?_0_0011_?1_0101 : + if (~|foo[ 8: 7]) + begin + if (foo[6]) + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1350"); + ozoneye(foo[14: 9],foo[ 5], fd); + end + else + begin + ozoneye(foo[14: 9],foo[ 5], fd); + $fwrite (fd, " 1351"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1352"); + else + ozonerab(foo[26:20], fd); + end + dude(fd); + $fwrite(fd, " 1353"); + end + else + $fwrite(fd, " 1354"); + 17'b00_1001_0_0000_?1_0010 : + if (~|foo[25:20]) + begin + ozoneye(foo[14: 9],1'b0, fd); + $fwrite (fd, " 1355"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1356"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1357"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1358"); + end + else + $fwrite(fd, " 1359"); + 17'b00_101?_0_????_?1_0010 : + if (~foo[13]) + begin + if (foo[12]) + begin + $fwrite (fd, " 1360"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1361"); + else + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1362"); + $fwrite (fd, " 1363"); + skyway({1'b0,foo[18:16]}, fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1364"); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1365"); + $fwrite (fd, " 1366"); + skyway({1'b0,foo[18:16]}, fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1367"); + end + end + else + $fwrite(fd, " 1368"); + 17'b01_01??_?_????_??_???? : + begin + ozonerab({1'b0,foo[27:26],foo[19:16]}, fd); + $fwrite (fd, " 1369"); + ozonerab({1'b0,foo[25:20]}, fd); + dude(fd); + $fwrite(fd, " 1370"); + end + 17'b00_100?_?_???0_11_0101 : + if (~foo[6]) + begin + $fwrite (fd," 1371"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1372"); + ozonerab({foo[ 9: 7],foo[19:16]}, fd); + $fwrite (fd, " 1373"); + ozonerab({foo[26:20]}, fd); + dude(fd); + $fwrite(fd, " 1374"); + end + else + $fwrite(fd, " 1375"); + 17'b00_1000_?_????_?1_0010 : + if (~|foo[25:24]) + begin + ozonery(foo[23:20], fd); + $fwrite (fd, " 1376"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1377"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1378"); + end + else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) + begin + ozonery(foo[23:20], fd); + $fwrite (fd, " 1379"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1380"); + ozonejk(foo[ 5], fd); + dude(fd); + $fwrite(fd, " 1381"); + end + else + $fwrite(fd, " 1382"); + 17'b11_01??_?_????_??_????, + 17'b10_00??_?_????_??_???? : + if (foo[30]) + $fwrite(fd, " 1383:%x", foo[27:16]); + else + $fwrite(fd, " 1384:%x", foo[27:16]); + 17'b00_10??_?_????_01_1000 : + if (~foo[6]) + begin + if (foo[7]) + $fwrite(fd, " 1385:%x", foo[27: 8]); + else + $fwrite(fd, " 1386:%x", foo[27: 8]); + end + else + $fwrite(fd, " 1387"); + 17'b00_10??_?_????_11_1000 : + begin + $fwrite (fd," 1388"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1389"); + if (foo[15]) + $fwrite (fd, " 1390"); + else + $fwrite (fd, " 1391"); + skyway(foo[27:24], fd); + skyway(foo[23:20], fd); + skyway(foo[19:16], fd); + skyway(foo[ 9: 6], fd); + dude(fd); + $fwrite(fd, " 1392"); + end + 17'b11_0001_?_????_??_???? : + casez (foo[25:22]) + 4'b01?? : + begin + $fwrite (fd," 1393"); + ozonecon(foo[20:16], fd); + case (foo[23:21]) + 3'h0 : $fwrite (fd, " 1394"); + 3'h1 : $fwrite (fd, " 1395"); + 3'h2 : $fwrite (fd, " 1396"); + 3'h3 : $fwrite (fd, " 1397"); + 3'h4 : $fwrite (fd, " 1398"); + 3'h5 : $fwrite (fd, " 1399"); + 3'h6 : $fwrite (fd, " 1400"); + 3'h7 : $fwrite (fd, " 1401"); + endcase + dude(fd); + $fwrite(fd, " 1402"); + end + 4'b0000 : + $fwrite(fd, " 1403:%x", foo[21:16]); + 4'b0010 : + if (~|foo[21:16]) + $fwrite(fd, " 1404"); + 4'b1010 : + if (~|foo[21:17]) + begin + if (foo[16]) + $fwrite(fd, " 1405"); + else + $fwrite(fd, " 1406"); + end + default : + $fwrite(fd, " 1407"); + endcase + 17'b01_11??_?_????_??_???? : + if (foo[27:23] === 5'h00) + $fwrite(fd, " 1408:%x", foo[22:16]); + else + $fwrite(fd, " 1409:%x", foo[22:16]); + default: $fwrite(fd, " 1410"); + endcase + end + endtask + + //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) + //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_x.v b/SVIncCompil/Testcases/Verilator/t_case_x.v new file mode 100644 index 0000000..2052612 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_x.v
@@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005-2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [3:0] value; + reg [3:0] valuex; + + // verilator lint_off CASEOVERLAP + // verilator lint_off CASEWITHX + // verilator lint_off CASEX + + // Note for Verilator Xs must become zeros, or the Xs may match. + + initial begin + value = 4'b1001; + valuex = 4'b1xxx; + case (value) + 4'b1xxx: $stop; + 4'b1???: $stop; + 4'b1001: ; + default: $stop; + endcase + case (valuex) + 4'b1???: $stop; + 4'b1xxx: ; + 4'b1001: ; + 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 + default: $stop; + endcase + // + casex (value) + 4'b100x: ; + default: $stop; + endcase + casex (value) + 4'b100?: ; + default: $stop; + endcase + casex (valuex) + 4'b100x: ; + default: $stop; + endcase + casex (valuex) + 4'b100?: ; + default: $stop; + endcase + // + casez (value) + 4'bxxxx: $stop; + 4'b100?: ; + default: $stop; + endcase + casez (valuex) + 4'b1xx?: ; + 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 + default: $stop; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_x_bad.v b/SVIncCompil/Testcases/Verilator/t_case_x_bad.v new file mode 100644 index 0000000..b2662f7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_x_bad.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + value + ); + + input [3:0] value; + always @ (/*AS*/value) begin + casex (value) + default: $stop; + endcase + case (value) + 4'b0000: $stop; + 4'b1xxx: $stop; + default: $stop; + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_case_zx_bad.v b/SVIncCompil/Testcases/Verilator/t_case_zx_bad.v new file mode 100644 index 0000000..1ba4256 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_case_zx_bad.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + value + ); + + input [3:0] value; + always @ (/*AS*/value) begin + casez (value) + 4'b0000: $stop; + 4'b1xxx: $stop; + default: $stop; + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_cast.v b/SVIncCompil/Testcases/Verilator/t_cast.v new file mode 100644 index 0000000..b17a103 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_cast.v
@@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t; + + typedef logic [3:0] mc_t; + typedef mc_t tocast_t; + + typedef struct packed { + logic [15:0] data; + } packed_t; + + packed_t pdata; + assign pdata.data = 16'h1234; + logic [7:0] logic8bit; + assign logic8bit = $bits(logic8bit)'(pdata >> 8); + + mc_t o; + + logic [15:0] allones = 16'hffff; + parameter FOUR = 4; + + // bug925 + localparam [6:0] RESULT = 7'((6*9+92)%96); + + logic signed [14:0] samp0 = 15'h0000; + logic signed [14:0] samp1 = 15'h0000; + logic signed [14:0] samp2 = 15'h6000; + logic signed [11:0] coeff0 = 12'h009; + logic signed [11:0] coeff1 = 12'h280; + logic signed [11:0] coeff2 = 12'h4C5; + logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11)); + // verilator lint_off WIDTH + logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11)); + // verilator lint_on WIDTH + logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector + (27'(coeff1 * samp1) >>> 11) + + (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings + + initial begin + if (logic8bit != 8'h12) $stop; + if (4'shf > 4'sh0) $stop; + if (signed'(4'hf) > 4'sh0) $stop; + if (4'hf < 4'h0) $stop; + if (unsigned'(4'shf) < 4'h0) $stop; + if (4'(allones) !== 4'hf) $stop; + if (6'(allones) !== 6'h3f) $stop; + if ((4)'(allones) !== 4'hf) $stop; + if ((4+2)'(allones) !== 6'h3f) $stop; + if ((4-2)'(allones) !== 2'h3) $stop; + if ((FOUR+2)'(allones) !== 6'h3f) $stop; + if (50 !== RESULT) $stop; + + o = tocast_t'(4'b1); + if (o != 4'b1) $stop; + + if (15'h6cec != outa) $stop; + if (27'h7ffecec != mida) $stop; + if (27'h7ffecec != midb) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_cdc_async_bad.v b/SVIncCompil/Testcases/Verilator/t_cdc_async_bad.v new file mode 100644 index 0000000..1a5fbf8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_cdc_async_bad.v
@@ -0,0 +1,81 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + q0, q1, q2, q3, q4, q5, q6a, q6b, + // Inputs + clk, d, rst0_n + ); + input clk; + input d; + + // OK -- from primary + input rst0_n; + output wire q0; + Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d)); + + // OK -- from flop + reg rst1_n; + always @ (posedge clk) rst1_n <= rst0_n; + output wire q1; + Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d)); + + // Bad - logic + wire rst2_bad_n = rst0_n | rst1_n; + output wire q2; + Flop flop2 (.q(q2), .rst_n(rst2_bad_n), .clk(clk), .d(d)); + + // Bad - logic in submodule + wire rst3_bad_n; + Sub sub (.z(rst3_bad_n), .a(rst0_n), .b(rst1_n)); + output wire q3; + Flop flop3 (.q(q3), .rst_n(rst3_bad_n), .clk(clk), .d(d)); + + // OK - bit selection + reg [3:0] rst4_n; + always @ (posedge clk) rst4_n <= {4{rst0_n}}; + output wire q4; + Flop flop4 (.q(q4), .rst_n(rst4_n[1]), .clk(clk), .d(d)); + + // Bad - logic, but waived + // verilator lint_off CDCRSTLOGIC + wire rst5_waive_n = rst0_n & rst1_n; + // verilator lint_on CDCRSTLOGIC + output wire q5; + Flop flop5 (.q(q5), .rst_n(rst5_waive_n), .clk(clk), .d(d)); + + // Bad - for graph test - logic feeds two signals, three destinations + wire rst6_bad_n = rst0_n ^ rst1_n; + wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); // $c prevents optimization + wire rst6b_bad_n = rst6_bad_n ^ $c1("1"); + output wire q6a; + output wire q6b; + Flop flop6a (.q(q6a), .rst_n(rst6a_bad_n), .clk(clk), .d(d)); + Flop flop6v (.q(q6b), .rst_n(rst6b_bad_n), .clk(clk), .d(d)); + + initial begin + $display("%%Error: Not a runnable test"); + $stop; + end + +endmodule + +module Flop ( + input clk, + input d, + input rst_n, + output q); + + always @ (posedge clk or negedge rst_n) begin + if (!rst_n) q <= 1'b0; + else q <= d; + end +endmodule + +module Sub (input a, b, + output z); + assign z = a|b; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_cellarray.v b/SVIncCompil/Testcases/Verilator/t_cellarray.v new file mode 100644 index 0000000..6789ec7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_cellarray.v
@@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jie Xu. +// + +// change these two parameters to see the speed differences +`define DATA_WIDTH 8 +`define REP_COUNT4 `DATA_WIDTH/4 +`define REP_COUNT2 `DATA_WIDTH/2 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + reg [3:0] count4 = 0; + reg [1:0] count2 = 0; + + reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}}; + reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] res1; + reg [`DATA_WIDTH-1:0] res2; + reg [`DATA_WIDTH-1:0] res3; + reg [`DATA_WIDTH-1:0] res4; + + drv1 t_drv1 [`DATA_WIDTH-1:0] (.colSelA(a), .datao(res1)); + drv2 t_drv2 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .datao(res2)); + drv3 t_drv3 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .datao(res3)); + drv4 t_drv4 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .colSelD(d), .datao(res4)); + + always@(posedge clk) + begin + count2 <= count2 + 1; + count4 <= count4 + 1; + a <= {`REP_COUNT4{count4}}; + b <= {`REP_COUNT4{count4}}; + c <= {`REP_COUNT2{count2}}; + d <= {`REP_COUNT2{count2}}; + + if (res1 != (a)) begin + $stop; + end + if (res2 != (a&b)) begin + $stop; + end + if (res3 != (a&b&c)) begin + $stop; + end + if (res4 != (a&b&c&d)) begin + $stop; + end + + if (count4 > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + + +module drv1 + (input colSelA, + output datao + ); + assign datao = colSelA; +endmodule + +module drv2 + (input colSelA, + input colSelB, + output datao + ); + assign datao = colSelB & colSelA; +endmodule + +module drv3 + (input colSelA, + input colSelB, + input colSelC, + output datao + ); + assign datao = colSelB & colSelA & colSelC; + +endmodule + +module drv4 + (input colSelA, + input colSelB, + input colSelC, + input colSelD, + output datao + ); + assign datao = colSelB & colSelA & colSelC & colSelD; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_chg_first.v b/SVIncCompil/Testcases/Verilator/t_chg_first.v new file mode 100644 index 0000000..c80ec33 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_chg_first.v
@@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk, fastclk + ); + + input clk; + input fastclk; // surefire lint_off_line UDDIXN + + integer _mode; initial _mode=0; + + reg [31:0] ord1; initial ord1 = 32'h1111; + wire [31:0] ord2; + reg [31:0] ord3; + wire [31:0] ord4; + wire [31:0] ord5; + wire [31:0] ord6; + wire [31:0] ord7; + + // verilator lint_off UNOPT + t_chg_a a ( + .a(ord1), .a_p1(ord2), + .b(ord4), .b_p1(ord5), + .c(ord3), .c_p1(ord4), + .d(ord6), .d_p1(ord7) + ); + + // surefire lint_off ASWEMB + assign ord6 = ord5 + 1; + // verilator lint_on UNOPT + + always @ (/*AS*/ord2) ord3 = ord2 + 1; + + always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR + if (_mode==1) begin + //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); + //if (ord2 == 2 && ord7 != 7) $stop; + end + end + + always @ (posedge clk) begin + if (_mode==0) begin + $write("[%0t] t_chg: Running\n", $time); + _mode<=1; + ord1 <= 1; + end + else if (_mode==1) begin + _mode<=2; + if (ord7 !== 7) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module t_chg_a (/*AUTOARG*/ + // Outputs + a_p1, b_p1, c_p1, d_p1, + // Inputs + a, b, c, d + ); + input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; + input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; + input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; + input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_2in.v.bad b/SVIncCompil/Testcases/Verilator/t_clk_2in.v.bad new file mode 100644 index 0000000..6298c7e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_2in.v.bad
@@ -0,0 +1,162 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +`ifndef VERILATOR +module t; + /*AUTOREGINPUT*/ + // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) + reg c0; // To t2 of t2.v + reg c1; // To t2 of t2.v + reg check; // To t2 of t2.v + reg [1:0] clks; // To t2 of t2.v + // End of automatics + t2 t2 (/*AUTOINST*/ + // Inputs + .clks (clks[1:0]), + .c0 (c0), + .c1 (c1), + .check (check)); + task clockit (input v1, v0); + c1 = v1; + c0 = v0; + clks[1] = v1; + clks[0] = v0; + `ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif + #1; + endtask + initial begin + check = '0; + c0 = '0; + c1 = '0; + clks = '0; + #1 + t2.clear(); + #10; + for (int i=0; i<2; i++) begin + clockit(0, 0); + clockit(0, 0); + clockit(0, 1); + clockit(1, 1); + clockit(0, 0); + clockit(1, 1); + clockit(1, 0); + clockit(0, 0); + clockit(1, 0); + clockit(0, 1); + clockit(0, 0); + end + check = 1; + clockit(0, 0); + end +endmodule +`endif + +`ifdef VERILATOR + `define t2 t +`else + `define t2 t2 +`endif + +module `t2 ( + input [1:0] clks, + input c0, + input c1, + input check + ); + +`ifdef T_CLK_2IN_VEC + wire clk0 = clks[0]; + wire clk1 = clks[1]; +`else + wire clk0 = c0; + wire clk1 = c1; +`endif + + integer p0 = 0; + integer p1 = 0; + integer p01 = 0; + integer n0 = 0; + integer n1 = 0; + integer n01 = 0; + integer vp = 0; + integer vn = 0; + integer vpn = 0; + task clear; +`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif + p0 = 0; + p1 = 0; + p01 = 0; + n0 = 0; + n1 = 0; + n01 = 0; + vp = 0; + vn = 0; + vpn = 0; + endtask + +`define display_counts(text) begin \ + $write("[%0t] ",$time); \ + `ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \ + $write(text); \ + $write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \ + end + + always @ (posedge clk0) begin + p0 = p0 + 1; // Want blocking, so don't miss clock counts +`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif + end + always @ (posedge clk1) begin + p1 = p1 + 1; +`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif + end + always @ (posedge clk0 or posedge clk1) begin + p01 = p01 + 1; +`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif + end + + always @ (negedge clk0) begin + n0 = n0 + 1; +`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif + end + always @ (negedge clk1) begin + n1 = n1 + 1; +`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif + end + always @ (negedge clk0 or negedge clk1) begin + n01 = n01 + 1; +`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif + end + +`ifndef VERILATOR + always @ (posedge clks) begin + vp = vp + 1; +`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif + end + always @ (negedge clks) begin + vn = vn + 1; +`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif + end + always @ (posedge clks or negedge clks) begin + vpn = vpn + 1; +`ifdef TEST_VERBOSE `display_counts("or vec"); `endif + end +`endif + + always @ (posedge check) begin + if (p0!=6) $stop; + if (p1!=6) $stop; + if (p01!=10) $stop; + if (n0!=6) $stop; + if (n1!=6) $stop; + if (n01!=10) $stop; +`ifndef VERILATOR + if (vp!=6) $stop; + if (vn!=6) $stop; + if (vpn!=12) $stop; +`endif + $write("*-* All Finished *-*\n"); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_concat.v b/SVIncCompil/Testcases/Verilator/t_clk_concat.v new file mode 100644 index 0000000..caba2a9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_concat.v
@@ -0,0 +1,97 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// + +module some_module ( + input wrclk + ); + + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; + + always @(posedge wrclk) begin + case (some_state) + 2'b11: + if (some_other_state == 0) + some_state <= 2'b00; + default: + $display ("This is a display statement"); + endcase + + if (wrclk) + some_other_state <= 0; + end + +endmodule + +`define BROKEN + +module t1( + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); + + some_module + some_module + ( +`ifdef BROKEN + .wrclk (i_clks[3]) +`else + .wrclk (i_clk1) +`endif + ); +endmodule + +module t2( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; + + assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0}; + + always @(posedge i_clk0) begin + data_q <= i_data; + end + + t1 t1 + ( + .i_clks (the_clks), + .i_clk0 (i_clk0), + .i_clk1 (i_clk1) + ); +endmodule + +module t( + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); + + logic [2:0] clks; + + assign clks = {1'b0, clk1, clk0}; + + t2 + t2 + ( + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk1), + .i_clk2 (clk2), + .i_data (data_in) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_concat2.v b/SVIncCompil/Testcases/Verilator/t_clk_concat2.v new file mode 100644 index 0000000..746b55d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_concat2.v
@@ -0,0 +1,106 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// + +module some_module ( + input wrclk + ); + + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; + + always @(posedge wrclk) begin + case (some_state) + 2'b11: + if (some_other_state == 0) + some_state <= 2'b00; + default: + $display ("This is a display statement"); + endcase + + if (wrclk) + some_other_state <= 0; + end + +endmodule + +`define BROKEN + +module t1( + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); + + some_module + some_module + ( +`ifdef BROKEN + .wrclk (i_clks[3]) +`else + .wrclk (i_clk1) +`endif + ); +endmodule + +module t2( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; + + assign the_clks[3] = i_clk1; + assign the_clks[2] = i_clk2; + assign the_clks[1] = i_clk1; + assign the_clks[0] = i_clk0; + + always @(posedge i_clk0) begin + data_q <= i_data; + end + + t1 t1 + ( + .i_clks (the_clks), + .i_clk0 (i_clk0), + .i_clk1 (i_clk1) + ); +endmodule + +module t( + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); + + input clk; + + logic [2:0] clks; + + assign clks = {1'b0, clk1, clk0}; + + t2 + t2 + ( + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk), + .i_clk2 (clk2), + .i_data (data_in) + ); + + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_concat3.v b/SVIncCompil/Testcases/Verilator/t_clk_concat3.v new file mode 100644 index 0000000..37c1648 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_concat3.v
@@ -0,0 +1,101 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// + +/* verilator lint_off LITENDIAN */ +module some_module ( + input wrclk + ); + + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; + + always @(posedge wrclk) begin + case (some_state) + 2'b11: + if (some_other_state == 0) + some_state <= 2'b00; + default: + $display ("This is a display statement"); + endcase + + if (wrclk) + some_other_state <= 0; + end + +endmodule + +`define BROKEN + +module t1( + input [-12:-9] i_clks, + input i_clk0, + input i_clk1 + ); + + some_module + some_module + ( +`ifdef BROKEN + .wrclk (i_clks[-12]) +`else + .wrclk (i_clk1) +`endif + ); +endmodule + +module t2( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [-12:-9] the_clks; + logic data_q; + + assign the_clks[-12] = i_clk1; + assign the_clks[-11] = i_clk2; + assign the_clks[-10] = i_clk1; + assign the_clks[-9] = i_clk0; + + always @(posedge i_clk0) begin + data_q <= i_data; + end + + t1 t1 + ( + .i_clks (the_clks), + .i_clk0 (i_clk0), + .i_clk1 (i_clk1) + ); +endmodule + +module t( + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); + + logic [2:0] clks; + + assign clks = {1'b0, clk1, clk0}; + + t2 + t2 + ( + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk1), + .i_clk2 (clk2), + .i_data (data_in) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_concat4.v b/SVIncCompil/Testcases/Verilator/t_clk_concat4.v new file mode 100644 index 0000000..ace301a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_concat4.v
@@ -0,0 +1,105 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// + +module some_module ( + input wrclk + ); + + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; + + always @(posedge wrclk) begin + case (some_state) + 2'b11: + if (some_other_state == 0) + some_state <= 2'b00; + default: + $display ("This is a display statement"); + endcase + + if (wrclk) + some_other_state <= 0; + end + +endmodule + +`define BROKEN + +module t1( + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); + + generate + genvar i; + for (i = 0; i < 2; i = i + 1) begin: a_generate_block + some_module + some_module + ( +`ifdef BROKEN + .wrclk (i_clks[3]) +`else + .wrclk (i_clk1) +`endif + ); + end + endgenerate +endmodule + +module t2( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; + + assign the_clks[3] = i_clk1; + assign the_clks[2] = i_clk2; + assign the_clks[1] = i_clk1; + assign the_clks[0] = i_clk0; + + always @(posedge i_clk0) begin + data_q <= i_data; + end + + t1 t1 + ( + .i_clks (the_clks), + .i_clk0 (i_clk0), + .i_clk1 (i_clk1) + ); +endmodule + +module t( + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); + + logic [2:0] clks; + + assign clks = {1'b0, clk1, clk0}; + + t2 + t2 + ( + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk1), + .i_clk2 (clk2), + .i_data (data_in) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_concat5.v b/SVIncCompil/Testcases/Verilator/t_clk_concat5.v new file mode 100644 index 0000000..1c126e3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_concat5.v
@@ -0,0 +1,104 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// + +module some_module ( + input [3:0] i_clks + ); + + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; + + always @(posedge i_clks[3]) begin + case (some_state) + 2'b11: + if (some_other_state == 0) + some_state <= 2'b00; + default: + $display ("This is a display statement"); + endcase + + if (i_clks[3]) + some_other_state <= 0; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +`define BROKEN + +module t1( + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); + + some_module + some_module + ( + .i_clks (i_clks) + ); +endmodule + +module t2( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; + + assign the_clks[3] = i_clk1; + assign the_clks[2] = i_clk2; + assign the_clks[1] = i_clk1; + assign the_clks[0] = i_clk0; + + always @(posedge i_clk0) begin + data_q <= i_data; + end + + t1 t1 + ( + .i_clks (the_clks), + .i_clk0 (i_clk0), + .i_clk1 (i_clk1) + ); +endmodule + +module t( + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); + + input clk; + + logic [2:0] clks; + + assign clks = {1'b0, clk1, clk0}; + + t2 + t2 + ( + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk), + .i_clk2 (clk2), + .i_data (data_in) + ); + + // initial begin + // $write("*-* All Finished *-*\n"); + // $finish; + // end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_concat6.v b/SVIncCompil/Testcases/Verilator/t_clk_concat6.v new file mode 100644 index 0000000..49acb3d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_concat6.v
@@ -0,0 +1,113 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// + +module some_module ( + input [3:0] i_clks + ); + + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; + logic the_clk; + + assign the_clk = i_clks[3]; + + always @(posedge the_clk) begin + case (some_state) + 2'b11: + if (some_other_state == 0) + some_state <= 2'b00; + default: + $display ("This is a display statement"); + endcase + + if (the_clk) + some_other_state <= 0; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +`define BROKEN + +module t1( + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); + + some_module + some_module + ( + .i_clks (i_clks) + ); +endmodule + +module ident( + input i_ident, + output o_ident + ); + assign o_ident = i_ident; +endmodule + +module t2( + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; + logic ident_clk1; + + always @(posedge i_clk0) begin + data_q <= i_data; + end + + ident + ident + ( + .i_ident (i_clk1), + .o_ident (ident_clk1) + ); + + t1 t1 + ( + .i_clks ({ident_clk1, i_clk2, ident_clk1, i_clk0}), + .i_clk0 (i_clk0), + .i_clk1 (i_clk1) + ); +endmodule + +module t( + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/ /*verilator public_flat*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); + + input clk; + + logic [2:0] clks; + + assign clks = {1'b0, clk1, clk0}; + + t2 + t2 + ( + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk), + .i_clk2 (clk2), + .i_data (data_in) + ); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_condflop.v b/SVIncCompil/Testcases/Verilator/t_clk_condflop.v new file mode 100644 index 0000000..5554ecb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_condflop.v
@@ -0,0 +1,124 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (clk); + input clk; + + reg [0:0] d1; + reg [2:0] d3; + reg [7:0] d8; + + wire [0:0] q1; + wire [2:0] q3; + wire [7:0] q8; + + // verilator lint_off UNOPTFLAT + reg ena; + // verilator lint_on UNOPTFLAT + + condff #(12) condff + (.clk(clk), .sen(1'b0), .ena(ena), + .d({d8,d3,d1}), + .q({q8,q3,q1})); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + //$write("%x %x %x %x\n", cyc, q8, q3, q1); + cyc <= cyc + 1; + if (cyc==1) begin + d1 <= 1'b1; d3<=3'h1; d8<=8'h11; + ena <= 1'b1; + end + if (cyc==2) begin + d1 <= 1'b0; d3<=3'h2; d8<=8'h33; + ena <= 1'b0; + end + if (cyc==3) begin + d1 <= 1'b1; d3<=3'h3; d8<=8'h44; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc==4) begin + d1 <= 1'b1; d3<=3'h4; d8<=8'h77; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc==5) begin + d1 <= 1'b1; d3<=3'h0; d8<=8'h88; + ena <= 1'b1; + if (q8 != 8'h44) $stop; + end + if (cyc==6) begin + if (q8 != 8'h77) $stop; + end + if (cyc==7) begin + if (q8 != 8'h88) $stop; + end + // + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +module condff (clk, sen, ena, d, q); + parameter WIDTH = 1; + input clk; + + input sen; + input ena; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; + + condffimp #(.WIDTH(WIDTH)) + imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); +endmodule + +module condffimp (clk, sen, ena, d, q); + parameter WIDTH = 1; + input clk; + input sen; + input ena; + input [WIDTH-1:0] d; + output reg [WIDTH-1:0] q; + wire gatedclk; + + clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); + + always @(posedge gatedclk) begin + if (gatedclk === 1'bX) begin + q <= {WIDTH{1'bX}}; + end + else begin + q <= d; + end + end + +endmodule + +module clockgate (clk, sen, ena, gatedclk); + input clk; + input sen; + input ena; + output gatedclk; + + reg ena_b; + wire gatedclk = clk & ena_b; + + // verilator lint_off COMBDLY + always @(clk or ena or sen) begin + if (~clk) begin + ena_b <= ena | sen; + end + else begin + if ((clk^sen)===1'bX) ena_b <= 1'bX; + end + end + // verilator lint_on COMBDLY + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_condflop_nord.v b/SVIncCompil/Testcases/Verilator/t_clk_condflop_nord.v new file mode 100644 index 0000000..5554ecb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_condflop_nord.v
@@ -0,0 +1,124 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (clk); + input clk; + + reg [0:0] d1; + reg [2:0] d3; + reg [7:0] d8; + + wire [0:0] q1; + wire [2:0] q3; + wire [7:0] q8; + + // verilator lint_off UNOPTFLAT + reg ena; + // verilator lint_on UNOPTFLAT + + condff #(12) condff + (.clk(clk), .sen(1'b0), .ena(ena), + .d({d8,d3,d1}), + .q({q8,q3,q1})); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + //$write("%x %x %x %x\n", cyc, q8, q3, q1); + cyc <= cyc + 1; + if (cyc==1) begin + d1 <= 1'b1; d3<=3'h1; d8<=8'h11; + ena <= 1'b1; + end + if (cyc==2) begin + d1 <= 1'b0; d3<=3'h2; d8<=8'h33; + ena <= 1'b0; + end + if (cyc==3) begin + d1 <= 1'b1; d3<=3'h3; d8<=8'h44; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc==4) begin + d1 <= 1'b1; d3<=3'h4; d8<=8'h77; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc==5) begin + d1 <= 1'b1; d3<=3'h0; d8<=8'h88; + ena <= 1'b1; + if (q8 != 8'h44) $stop; + end + if (cyc==6) begin + if (q8 != 8'h77) $stop; + end + if (cyc==7) begin + if (q8 != 8'h88) $stop; + end + // + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +module condff (clk, sen, ena, d, q); + parameter WIDTH = 1; + input clk; + + input sen; + input ena; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; + + condffimp #(.WIDTH(WIDTH)) + imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); +endmodule + +module condffimp (clk, sen, ena, d, q); + parameter WIDTH = 1; + input clk; + input sen; + input ena; + input [WIDTH-1:0] d; + output reg [WIDTH-1:0] q; + wire gatedclk; + + clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); + + always @(posedge gatedclk) begin + if (gatedclk === 1'bX) begin + q <= {WIDTH{1'bX}}; + end + else begin + q <= d; + end + end + +endmodule + +module clockgate (clk, sen, ena, gatedclk); + input clk; + input sen; + input ena; + output gatedclk; + + reg ena_b; + wire gatedclk = clk & ena_b; + + // verilator lint_off COMBDLY + always @(clk or ena or sen) begin + if (~clk) begin + ena_b <= ena | sen; + end + else begin + if ((clk^sen)===1'bX) ena_b <= 1'bX; + end + end + // verilator lint_on COMBDLY + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_dpulse.v b/SVIncCompil/Testcases/Verilator/t_clk_dpulse.v new file mode 100644 index 0000000..1fa080c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_dpulse.v
@@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off GENCLK + + reg [7:0] cyc; initial cyc=0; + reg genclk; + // verilator lint_off MULTIDRIVEN + reg [7:0] set_both; + // verilator lint_on MULTIDRIVEN + + wire genthiscyc = ( (cyc % 2) == 1 ); + + always @ (posedge clk) begin + cyc <= cyc + 8'h1; + genclk <= genthiscyc; + set_both <= cyc; + $write ("SB set_both %x <= cyc %x\n", set_both, cyc); + if (genthiscyc) begin + if (cyc>1 && set_both != (cyc - 8'h1)) $stop; + end + else begin + if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + always @ (posedge genclk) begin + set_both <= ~ set_both; + $write ("SB set_both %x <= cyc %x\n", set_both, ~cyc); + if (cyc>1 && set_both != (cyc - 8'h1)) $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_dsp.v b/SVIncCompil/Testcases/Verilator/t_clk_dsp.v new file mode 100644 index 0000000..991b975 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_dsp.v
@@ -0,0 +1,175 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off GENCLK + + reg [7:0] cyc; initial cyc=0; + reg [7:0] padd; + reg dsp_ph1, dsp_ph2, dsp_reset; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] out; // From dspchip of t_dspchip.v + // End of automatics + + t_dspchip dspchip (/*AUTOINST*/ + // Outputs + .out (out[7:0]), + // Inputs + .dsp_ph1 (dsp_ph1), + .dsp_ph2 (dsp_ph2), + .dsp_reset (dsp_reset), + .padd (padd[7:0])); + + always @ (posedge clk) begin + $write("cyc %d\n",cyc); + if (cyc == 8'd0) begin + cyc <= 8'd1; + dsp_reset <= 0; // Need a posedge + padd <= 0; + end + else if (cyc == 8'd20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + cyc <= cyc + 8'd1; + dsp_ph1 <= ((cyc&8'd3) == 8'd0); + dsp_ph2 <= ((cyc&8'd3) == 8'd2); + dsp_reset <= (cyc == 8'd1); + padd <= cyc; + //$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out); + case (cyc) + default: $stop; + 8'd01: ; + 8'd02: ; + 8'd03: ; + 8'd04: ; + 8'd05: ; + 8'd06: ; + 8'd07: ; + 8'd08: ; + 8'd09: if (out!==8'h04) $stop; + 8'd10: if (out!==8'h04) $stop; + 8'd11: if (out!==8'h08) $stop; + 8'd12: if (out!==8'h08) $stop; + 8'd13: if (out!==8'h00) $stop; + 8'd14: if (out!==8'h00) $stop; + 8'd15: if (out!==8'h00) $stop; + 8'd16: if (out!==8'h00) $stop; + 8'd17: if (out!==8'h0c) $stop; + 8'd18: if (out!==8'h0c) $stop; + 8'd19: if (out!==8'h10) $stop; + endcase + end + end + +endmodule + +module t_dspchip (/*AUTOARG*/ + // Outputs + out, + // Inputs + dsp_ph1, dsp_ph2, dsp_reset, padd + ); + input dsp_ph1, dsp_ph2, dsp_reset; + input [7:0] padd; + output [7:0] out; + + wire dsp_ph1, dsp_ph2; + wire [7:0] out; + wire pla_ph1, pla_ph2; + wire out1_r; + wire [7:0] out2_r, padd; + wire clk_en; + + t_dspcore t_dspcore (/*AUTOINST*/ + // Outputs + .out1_r (out1_r), + .pla_ph1 (pla_ph1), + .pla_ph2 (pla_ph2), + // Inputs + .dsp_ph1 (dsp_ph1), + .dsp_ph2 (dsp_ph2), + .dsp_reset (dsp_reset), + .clk_en (clk_en)); + t_dsppla t_dsppla (/*AUTOINST*/ + // Outputs + .out2_r (out2_r[7:0]), + // Inputs + .pla_ph1 (pla_ph1), + .pla_ph2 (pla_ph2), + .dsp_reset (dsp_reset), + .padd (padd[7:0])); + + assign out = out1_r ? 8'h00 : out2_r; + assign clk_en = 1'b1; + +endmodule + +module t_dspcore (/*AUTOARG*/ + // Outputs + out1_r, pla_ph1, pla_ph2, + // Inputs + dsp_ph1, dsp_ph2, dsp_reset, clk_en + ); + input dsp_ph1, dsp_ph2, dsp_reset; + input clk_en; + output out1_r, pla_ph1, pla_ph2; + + wire dsp_ph1, dsp_ph2, dsp_reset; + wire pla_ph1, pla_ph2; + reg out1_r; + + always @(posedge dsp_ph1 or posedge dsp_reset) begin + if (dsp_reset) + out1_r <= 1'h0; + else + out1_r <= ~out1_r; + end + + assign pla_ph1 = dsp_ph1; + assign pla_ph2 = dsp_ph2 & clk_en; + +endmodule + +module t_dsppla (/*AUTOARG*/ + // Outputs + out2_r, + // Inputs + pla_ph1, pla_ph2, dsp_reset, padd + ); + input pla_ph1, pla_ph2, dsp_reset; + input [7:0] padd; + output [7:0] out2_r; + + wire pla_ph1, pla_ph2, dsp_reset; + wire [7:0] padd; + reg [7:0] out2_r; + + reg [7:0] latched_r; + + always @(posedge pla_ph1 or posedge dsp_reset) begin + if (dsp_reset) + latched_r <= 8'h00; + else + latched_r <= padd; + end + + always @(posedge pla_ph2 or posedge dsp_reset) begin + if (dsp_reset) + out2_r <= 8'h00; + else + out2_r <= latched_r; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_first.v b/SVIncCompil/Testcases/Verilator/t_clk_first.v new file mode 100644 index 0000000..32fb1c1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_first.v
@@ -0,0 +1,202 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk, fastclk + ); + + input clk /*verilator sc_clock*/; + input fastclk /*verilator sc_clock*/; + reg reset_l; + + int cyc; + initial reset_l = 0; + always @ (posedge clk) begin + if (cyc==0) reset_l <= 1'b1; + else if (cyc==1) reset_l <= 1'b0; + else if (cyc==10) reset_l <= 1'b1; + end + + t_clk t (/*AUTOINST*/ + // Inputs + .clk (clk), + .fastclk (fastclk), + .reset_l (reset_l)); +endmodule + +module t_clk (/*AUTOARG*/ + // Inputs + clk, fastclk, reset_l + ); + + input clk /*verilator sc_clock*/; + input fastclk /*verilator sc_clock*/; + input reset_l; + + // surefire lint_off STMINI + // surefire lint_off CWECSB + // surefire lint_off NBAJAM + reg _ranit; initial _ranit=0; + // surefire lint_off UDDSMX + reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT + wire [7:0] clk_clocks_d1r; + wire [7:0] clk_clocks_d1sr; + wire [7:0] clk_clocks_cp2_d1r; + wire [7:0] clk_clocks_cp2_d1sr; + // verilator lint_off MULTIDRIVEN + reg [7:0] int_clocks; initial int_clocks = 0; + // verilator lint_on MULTIDRIVEN + reg [7:0] int_clocks_copy; + + // verilator lint_off GENCLK + reg internal_clk; initial internal_clk = 0; + reg reset_int_; + // verilator lint_on GENCLK + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] CLK1 %x\n", $time, reset_l); +`endif + if (!reset_l) begin + clk_clocks <= 0; + int_clocks <= 0; + internal_clk <= 1'b1; + reset_int_ <= 0; + end + else begin + internal_clk <= ~internal_clk; + if (!_ranit) begin + _ranit <= 1; +`ifdef TEST_VERBOSE + $write("[%0t] t_clk: Running\n",$time); +`endif + reset_int_ <= 1; + end + end + end + + reg [7:0] sig_rst; + always @ (posedge clk or negedge reset_l) begin +`ifdef TEST_VERBOSE + $write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst); +`endif + if (!reset_l) begin + sig_rst <= 0; + end + else begin + sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB + end + end + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst); +`endif + if (!reset_l) begin + clk_clocks <= 0; + end + else begin + clk_clocks <= clk_clocks + 8'd1; + if (clk_clocks == 4) begin + if (sig_rst !== 4) $stop; + if (clk_clocks_d1r !== 3) $stop; + if (int_clocks !== 2) $stop; + if (int_clocks_copy !== 2) $stop; + if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop; + if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + reg [7:0] resetted; + always @ (posedge clk or negedge reset_int_) begin +`ifdef TEST_VERBOSE + $write("[%0t] CLK4 %x\n", $time, reset_l); +`endif + if (!reset_int_) begin + resetted <= 0; + end + else begin + resetted <= resetted + 8'd1; + end + end + + always @ (int_clocks) begin + int_clocks_copy = int_clocks; + end + + always @ (negedge internal_clk) begin + int_clocks <= int_clocks + 8'd1; + end + + t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks), + .q(clk_clocks_d1r), .q2(clk_clocks_d1sr)); + t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks), + .q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr)); + t_clk_two two (/*AUTOINST*/ + // Inputs + .fastclk (fastclk), + .reset_l (reset_l)); + +endmodule + +module t_clk_flop (/*AUTOARG*/ + // Outputs + q, q2, + // Inputs + clk, clk2, a + ); + parameter WIDTH=8; + input clk; + input clk2; + input [(WIDTH-1):0] a; + output [(WIDTH-1):0] q; + output [(WIDTH-1):0] q2; + reg [(WIDTH-1):0] q; + reg [(WIDTH-1):0] q2; + always @ (posedge clk) q<=a; + always @ (posedge clk2) q2<=a; +endmodule + +module t_clk_two (/*AUTOARG*/ + // Inputs + fastclk, reset_l + ); + input fastclk; + input reset_l; + // verilator lint_off GENCLK + reg clk2; + // verilator lint_on GENCLK + reg [31:0] count; + + t_clk_twob tb (.*); + + wire reset_h = ~reset_l; + always @ (posedge fastclk) begin + if (reset_h) clk2 <= 0; + else clk2 <= ~clk2; + end + always @ (posedge clk2) begin + if (reset_h) count <= 0; + else count <= count + 1; + end +endmodule + +module t_clk_twob (/*AUTOARG*/ + // Inputs + fastclk, reset_l + ); + input fastclk; + input reset_l; + + always @ (posedge fastclk) begin + // Extra line coverage point, just to make sure coverage + // hierarchy under inlining lands properly + if (reset_l) ; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_gater.v b/SVIncCompil/Testcases/Verilator/t_clk_gater.v new file mode 100644 index 0000000..4a8bdfe --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_gater.v
@@ -0,0 +1,159 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + reg reset; + reg enable; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .reset (reset), + .enable (enable), + .in (in[31:0])); + + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + reset <= (cyc < 5); + enable <= cyc[4] || (cyc < 2); + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'h01e1553da1dcf3af + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, reset, enable, in + ); + + input clk; + input reset; + input enable; + input [31:0] in; + output [31:0] out; + + + // No gating + reg [31:0] d10; + always @(posedge clk) begin + d10 <= in; + end + + reg displayit; +`ifdef VERILATOR // Harder test + initial displayit = $c1("0"); // Something that won't optimize away +`else + initial displayit = '0; +`endif + + // Obvious gating + PLI + reg [31:0] d20; + always @(posedge clk) begin + if (enable) begin + d20 <= d10; // Obvious gating + if (displayit) begin + $display("hello!"); // Must glob with other PLI statements + end + end + end + + // Reset means second-level gating + reg [31:0] d30, d31a, d31b, d32; + always @(posedge clk) begin + d32 <= d31b; + if (reset) begin + d30 <= 32'h0; + d31a <= 32'h0; + d31b <= 32'h0; + d32 <= 32'h0; // Overlaps above, just to make things interesting + end + else begin + // Mix two outputs + d30 <= d20; + if (enable) begin + d31a <= d30; + d31b <= d31a; + end + end + end + + // Multiple ORs for gater + reg [31:0] d40a,d40b; + always @(posedge clk) begin + if (reset) begin + d40a <= 32'h0; + d40b <= 32'h0; + end + if (enable) begin + d40a <= d32; + d40b <= d40a; + end + end + + // Non-optimizable + reg [31:0] d91, d92; + reg [31:0] inverted; + always @(posedge clk) begin + inverted = ~d40b; + if (reset) begin + d91 <= 32'h0; + end + else begin + if (enable) begin + d91 <= inverted; + end + else begin + d92 <= inverted ^ 32'h12341234; // Inverted gating condition + end + end + end + + wire [31:0] out = d91 ^ d92; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_gen.v b/SVIncCompil/Testcases/Verilator/t_clk_gen.v new file mode 100644 index 0000000..8042d28 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_gen.v
@@ -0,0 +1,86 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + // verilator lint_off GENCLK + reg gendlyclk_r; + reg [31:0] gendlydata_r; + reg [31:0] dlydata_gr; + + reg genblkclk; + reg [31:0] genblkdata; + reg [31:0] blkdata_gr; + + wire [31:0] constwire = 32'h11; + reg [31:0] initwire; + + integer i; + initial begin + for (i=0; i<10000; i=i+1) begin + initwire = 32'h2200; + end + end + + wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; + wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; + + always @ (posedge clk) begin + gendlydata_r <= 32'h0011_0000; + gendlyclk_r <= 0; + // surefire lint_off SEQASS + genblkclk = 0; + genblkdata = 0; + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==2) begin + gendlyclk_r <= 1; + gendlydata_r <= 32'h00540000; + genblkclk = 1; + genblkdata = 32'hace; + $write("[%0t] Send pulse\n", $time); + end + if (cyc==3) begin + genblkdata = 32'hdce; + gendlydata_r <= 32'h00ff0000; + if (either != 32'h87542211) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + // surefire lint_on SEQASS + end + + always @ (posedge gendlyclk_r) begin + if ($time>0) begin // Hack, don't split the block + $write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata); + dlydata_gr <= 32'h80000000; + // Delayed activity list will already be completed for gendlydata + // because genclk is from a delayed assignment. + // Thus we get the NEW not old value of gendlydata_r + if (gendlydata_r != 32'h00540000) $stop; + if (genblkdata != 32'hace) $stop; + end + end + + always @ (posedge genblkclk) begin + if ($time>0) begin // Hack, don't split the block + $write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata); + blkdata_gr <= 32'h07000000; + // Clock from non-delayed assignment, we get old value of gendlydata_r +`ifdef verilator `else // V3.2 races... technically legal + if (gendlydata_r != 32'h00110000) $stop; +`endif + if (genblkdata != 32'hace) $stop; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_inp_init.v b/SVIncCompil/Testcases/Verilator/t_clk_inp_init.v new file mode 100644 index 0000000..d9f7b97 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_inp_init.v
@@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Check initialisation of cloned clock variables +// +// This tests issue 1327 (Strange initialisation behaviour with +// "VinpClk" cloned clock variables) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Rupert Swarbrick (Argon Design). + + +// bug1327 +// This models some device under test with an asynchronous reset pin +// which counts to 15. +module dut (input wire clk, + input wire rst_n, + output wire done); + + reg [3:0] counter; + + always @(posedge clk or negedge rst_n) begin + if (rst_n & ! clk) begin + $display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.", + $time, clk, rst_n); + $stop; + end + + if (! rst_n) begin + counter <= 4'd0; + end else begin + counter <= counter < 4'd15 ? counter + 4'd1 : counter; + end + end + + assign done = rst_n & (counter == 4'd15); +endmodule + + +module t(input wire clk, + input wire rst_n); + + wire dut_done; + + // A small FSM for driving the test + // + // This is just designed to be enough to force Verilator to make a + // "VinpClk" variant of dut_rst_n. + + // Possible states: + // + // 0: Device in reset + // 1: Device running + // 2: Device finished + reg [1:0] state; + always @(posedge clk or negedge rst_n) begin + if (! rst_n) begin + state <= 0; + end else begin + if (state == 2'd0) begin + // One clock after resetting the device, we switch to running + // it. + state <= 2'd1; + end + else if (state == 2'd1) begin + // If the device is running, we switch to finished when its + // done signal goes high. + state <= dut_done ? 2'd2 : 2'd1; + end + else begin + // If the dut has finished, the test is done. + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + wire dut_rst_n = rst_n & (state != 0); + + wire done; + dut dut_i (.clk (clk), + .rst_n (dut_rst_n), + .done (dut_done)); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_latch.v b/SVIncCompil/Testcases/Verilator/t_clk_latch.v new file mode 100644 index 0000000..18ec5fe --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_latch.v
@@ -0,0 +1,109 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + fastclk, clk + ); + +`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge + `define posstyle posedge + `define negstyle negedge +`else + `define posstyle + `define negstyle +`endif + + input fastclk; + input clk; + + reg [7:0] data; + reg [7:0] data_a; + reg [7:0] data_a_a; + reg [7:0] data_a_b; + reg [7:0] data_b; + reg [7:0] data_b_a; + reg [7:0] data_b_b; + + reg [8*6-1:0] check [100:0]; + wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b}; + initial begin + check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; + check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; + check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; + check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; + check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; + check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; + check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; + check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; + check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; + check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; + check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; + check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; + check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; + check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; + check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; + end + + // verilator lint_off COMBDLY + always @ (`posstyle clk /*AS*/ or data) begin + if (clk) begin + data_a <= data + 8'd1; + end + end + + always @ (`posstyle clk /*AS*/ or data_a) begin + if (clk) begin + data_a_a <= data_a + 8'd1; + end + end + + always @ (`posstyle clk /*AS*/ or data_b) begin + if (clk) begin + data_b_a <= data_b + 8'd1; + end + end + + always @ (`negstyle clk /*AS*/ or data or data_a) begin + if (~clk) begin + data_b <= data + 8'd1; + data_a_b <= data_a + 8'd1; + data_b_b <= data_b + 8'd1; + end + end + + integer cyc; initial cyc=0; + + always @ (posedge fastclk) begin + cyc <= cyc+1; +`ifdef TEST_VERBOSE + $write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b); +`endif + if (cyc>=19 && cyc<36) begin + if (compare !== check[cyc]) begin + $write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]); + $stop; + end + end + if (cyc == 10) begin + data <= 8'd12; + end + if (cyc == 20) begin + data <= 8'd20; + end + if (cyc == 30) begin + data <= 8'd30; + end + if (cyc == 40) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_latchgate.v b/SVIncCompil/Testcases/Verilator/t_clk_latchgate.v new file mode 100644 index 0000000..1e3503f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_latchgate.v
@@ -0,0 +1,178 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. +// +// -------------------------------------------------------- +// Bug Description: +// +// Issue: The gated clock gclk_vld[0] toggles but dvld[0] +// input to the flop does not propagate to the output +// signal entry_vld[0] correctly. The value that propagates +// is the new value of dvld[0] not the one just before the +// posedge of gclk_vld[0]. +// -------------------------------------------------------- + +// Define to see the bug with test failing with gated clock 'gclk_vld' +// Comment out the define to see the test passing with ungated clock 'clk' +`define GATED_CLK_TESTCASE 1 + +// A side effect of the problem is this warning, disabled by default +//verilator lint_on IMPERFECTSCH + +// Test Bench +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + + // Take CRC data and apply to testblock inputs + wire [7:0] dvld = crc[7:0]; + wire [7:0] ff_en_e1 = crc[15:8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] entry_vld; // From test of Test.v + wire [7:0] ff_en_vld; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .ff_en_vld (ff_en_vld[7:0]), + .entry_vld (entry_vld[7:0]), + // Inputs + .clk (clk), + .dvld (dvld[7:0]), + .ff_en_e1 (ff_en_e1[7:0])); + + reg err_code; + reg ffq_clk_active; + reg [7:0] prv_dvld; + + initial begin + err_code = 0; + ffq_clk_active = 0; + end + always @ (posedge clk) begin + prv_dvld = test.dvld; + end + always @ (negedge test.ff_entry_dvld_0.clk) begin + ffq_clk_active = 1; + if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1; + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc); + $display(" en=%b fen=%b d=%b ev=%b", + test.flop_en_vld[0], test.ff_en_vld[0], + test.dvld[0], test.entry_vld[0]); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc<3) begin + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc); + if (ffq_clk_active == 0) begin + $display ("----"); + $display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs"); + $display ("----"); + $stop; + end + else if (err_code) begin + $display ("----"); + $display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs"); + $display ("----"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module llq (clk, d, q); + parameter WIDTH = 32; + input clk; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; + + reg [WIDTH-1:0] qr; + + /* verilator lint_off COMBDLY */ + + always @(clk or d) + if (clk == 1'b0) + qr <= d; + + /* verilator lint_on COMBDLY */ + + assign q = qr; +endmodule + +module ffq (clk, d, q); + parameter WIDTH = 32; + input clk; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; + + reg [WIDTH-1:0] qr; + + always @(posedge clk) + qr <= d; + + assign q = qr; +endmodule + +// DUT module +module Test (/*AUTOARG*/ + // Outputs + ff_en_vld, entry_vld, + // Inputs + clk, dvld, ff_en_e1 + ); + input clk; + + input [7:0] dvld; + input [7:0] ff_en_e1; + + output [7:0] ff_en_vld; + output wire [7:0] entry_vld; + + wire [7:0] gclk_vld; + wire [7:0] ff_en_vld /*verilator clock_enable*/; + reg [7:0] flop_en_vld; + + always @(posedge clk) flop_en_vld <= ff_en_e1; + + // clock gating +`ifdef GATED_CLK_TESTCASE + assign gclk_vld = {8{clk}} & ff_en_vld; +`else + assign gclk_vld = {8{clk}}; +`endif + + // latch for avoiding glitch on the clock gating control + llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld)); + + // flops that use the gated clock signal + ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0])); + ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1])); + ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2])); + ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3])); + ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4])); + ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5])); + ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6])); + ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7])); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_powerdn.v b/SVIncCompil/Testcases/Verilator/t_clk_powerdn.v new file mode 100644 index 0000000..039bcb0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_powerdn.v
@@ -0,0 +1,122 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg reset_l; + + // verilator lint_off GENCLK + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + // End of automatics + + reg clkgate_e2r; + reg clkgate_e1r_l; + always @(posedge clk or negedge reset_l) begin + if (!reset_l) begin + clkgate_e1r_l <= ~1'b1; + end + else begin + clkgate_e1r_l <= ~clkgate_e2r; + end + end + + reg clkgate_e1f; + always @(negedge clk) begin + // Yes, it's really a = + clkgate_e1f = ~clkgate_e1r_l | ~reset_l; + end + + wire clkgated = clk & clkgate_e1f; + + reg [31:0] countgated; + always @(posedge clkgated or negedge reset_l) begin + if (!reset_l) begin + countgated <= 32'h1000; + end + else begin + countgated <= countgated + 32'd1; + end + end + + reg [31:0] count; + always @(posedge clk or negedge reset_l) begin + if (!reset_l) begin + count <= 32'h1000; + end + else begin + count <= count + 32'd1; + end + end + + reg [7:0] cyc; initial cyc=0; + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n",$time,reset_l,cyc,clkgate_e1f,count,countgated); +`endif + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin + reset_l <= ~1'b0; + clkgate_e2r <= 1'b1; + end + 8'd01: begin + reset_l <= ~1'b0; + end + 8'd02: begin + end + 8'd03: begin + reset_l <= ~1'b1; // Need a posedge + end + 8'd04: begin + end + 8'd05: begin + reset_l <= ~1'b0; + end + 8'd09: begin + clkgate_e2r <= 1'b0; + end + 8'd11: begin + clkgate_e2r <= 1'b1; + end + 8'd20: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + case (cyc) + 8'd00: ; + 8'd01: ; + 8'd02: ; + 8'd03: ; + 8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; + 8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; + 8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; + 8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop; + 8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop; + 8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop; + 8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop; + 8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop; + 8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop; + 8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop; + 8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop; + 8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop; + 8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop; + 8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop; + 8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop; + 8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop; + 8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop; + default: $stop; + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_scope_bad.v b/SVIncCompil/Testcases/Verilator/t_clk_scope_bad.v new file mode 100644 index 0000000..0812d49 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_scope_bad.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + input clk; + input [2:0] in; + output [2:0] out; + + logic [2:0] r_in; + always_ff @ (posedge clk) r_in <= in; + + flop p0 (.clk(clk), .d(r_in[0]), .q(out[0])); + flop p2 (.clk(r_in[1]), .d(clk), .q(out[1])); + flop p1 (.clk(clk), .d(r_in[2]), .q(out[2])); + +endmodule + +module flop + ( + input d, + input clk, + output logic q); + + // verilator no_inline_module + + always_ff @ (posedge clk) begin + q <= d; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_clk_vecgen1.v b/SVIncCompil/Testcases/Verilator/t_clk_vecgen1.v new file mode 100644 index 0000000..089fee0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clk_vecgen1.v
@@ -0,0 +1,123 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [1:0] clkvec = crc[1:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0] count; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .count (count[1:0]), + // Inputs + .clkvec (clkvec[1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {62'h0, count}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +`ifdef T_TEST1 +module Test + ( + input wire [1:0] clkvec, + // verilator lint_off MULTIDRIVEN + output reg [1:0] count + // verilator lint_on MULTIDRIVEN + ); + genvar igen; + generate + for (igen=0; igen<2; igen=igen+1) begin : code_gen + initial count[igen] = 1'b0; + always @ (posedge clkvec[igen]) + count[igen] <= count[igen] + 1; + end + endgenerate + always @ (count) begin + $write("hi\n"); + end +endmodule +`endif + +`ifdef T_TEST2 +module Test + ( + input wire [1:0] clkvec, + // verilator lint_off MULTIDRIVEN + output reg [1:0] count + // verilator lint_on MULTIDRIVEN + ); + genvar igen; + generate + for (igen=0; igen<2; igen=igen+1) begin : code_gen + wire clk_tmp = clkvec[igen]; + // Unsupported: Count is multidriven, though if we did better analysis it wouldn't + // need to be. + initial count[igen] = 1'b0; + always @ (posedge clk_tmp) + count[igen] <= count[igen] + 1; + end + endgenerate +endmodule +`endif + +`ifdef T_TEST3 +module Test + ( + input wire [1:0] clkvec, + output wire [1:0] count + ); + genvar igen; + generate + for (igen=0; igen<2; igen=igen+1) begin : code_gen + wire clk_tmp = clkvec[igen]; + reg tmp_count = 1'b0; + always @ (posedge clk_tmp) begin + tmp_count <= tmp_count + 1; + end + assign count[igen] = tmp_count; + end + endgenerate +endmodule +`endif
diff --git a/SVIncCompil/Testcases/Verilator/t_clocker.v b/SVIncCompil/Testcases/Verilator/t_clocker.v new file mode 100644 index 0000000..1385119 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_clocker.v
@@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Simple test of CLkDATA +// +// Trigger the CLKDATA detection +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Jie Xu. + +localparam ID_MSB = 1; + + +module t (/*AUTOARG*/ + // Inputs + clk, + res, + res8, + res16 + ); + input clk; + output res; + output [7:0] res8; + output [15:0] res16; + + + wire [7:0] clkSet; + wire clk_1; + wire [2:0] clk_3; + wire [3:0] clk_4; + wire clk_final; + reg [7:0] count; + + + assign clkSet = {8{clk}}; + assign clk_4 = clkSet[7:4]; + assign clk_1 = clk_4[0];; + + // arraysel + assign clk_3 = {3{clk_1}}; + assign clk_final = clk_3[0]; + + // the following two assignment triggers the CLKDATA warning + // because on LHS there are a mix of signals both CLOCK and + // DATA + /* verilator lint_off CLKDATA */ + assign res8 = {clk_3, 1'b0, clk_4}; + assign res16 = {count, clk_3, clk_1, clk_4}; + /* verilator lint_on CLKDATA */ + + + initial + count = 0; + + + always @(posedge clk_final or negedge clk_final) begin + count = count + 1; + // the following assignment should trigger the CLKDATA warning + // because CLOCK signal is used as DATA in sequential block + /* verilator lint_off CLKDATA */ + res <= clk_final; + /* verilator lint_on CLKDATA */ + if ( count == 8'hf) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_concat_large.v b/SVIncCompil/Testcases/Verilator/t_concat_large.v new file mode 100644 index 0000000..5e52ce2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_concat_large.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [32767:0] a; + + initial begin + // verilator lint_off WIDTHCONCAT + a = {32768{1'b1}}; + // verilator lint_on WIDTHCONCAT + if (a[32000] != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_concat_large_bad.v b/SVIncCompil/Testcases/Verilator/t_concat_large_bad.v new file mode 100644 index 0000000..7f966fa --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_concat_large_bad.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t (/*AUTOARG*/); + + wire [32767:0] a = {32768{1'b1}}; + + initial begin + $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_concat_opt.v b/SVIncCompil/Testcases/Verilator/t_concat_opt.v new file mode 100644 index 0000000..3eed6fa --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_concat_opt.v
@@ -0,0 +1,70 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Jie Xu. +// +// The test was added together with the concat optimization. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [31:0] in_a; + reg [31:0] in_b; + reg [31:0] in_c; + reg [31:0] in_d; + reg [31:0] in_e; + reg [15:0] in_f; + wire [31:0] in_g; + + assign in_g = in_a << 4; + + reg [31:0] out_x; + reg [31:0] out_y; + reg [31:0] out_z; + reg [31:0] out_o; + reg [31:0] out_p; + reg [31:0] out_q; + + assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f}; + assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]}; + assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]}; + assign out_o = out_z | out_y; + assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]}; + assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}}; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + in_a <= cyc; + in_b <= cyc + 1; + in_c <= cyc + 3; + in_d <= cyc + 8; + in_e <= cyc; + in_f <= cyc[15:0]; + + if (out_x != (in_a & {2{in_f}})) + $stop; + if (out_y != (in_a&in_b)) + $stop; + if (out_z != (in_e&in_d&in_c)) + $stop; + if (out_o != (((in_a&in_b)|(in_c&in_e&in_d)))) + $stop; + if (out_p != (in_a & {2{in_f}} | in_e)) + $stop; + if (out_q != (in_a ^ in_g)) + $stop; + + if (cyc==100) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_const.v b/SVIncCompil/Testcases/Verilator/t_const.v new file mode 100644 index 0000000..22a5c0b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_const.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t(/*AUTOARG*/); + + initial begin + // verilator lint_off WIDTH + if (32'hxxxxxxxx !== 'hx) $stop; + if (32'hzzzzzzzz !== 'hz) $stop; + if (32'h???????? !== 'h?) $stop; + if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + if (68'h?_????????_???????? !== 'd?) $stop; + // verilator lint_on WIDTH + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_const_bad.v b/SVIncCompil/Testcases/Verilator/t_const_bad.v new file mode 100644 index 0000000..66513d6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_const_bad.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t(/*AUTOARG*/); + + initial begin + if (32'hxxxxxxxx !== 'hx) $stop; + if (32'hzzzzzzzz !== 'hz) $stop; + if (32'h???????? !== 'h?) $stop; + if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + if (68'h?_????????_???????? !== 'd?) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_const_dec_mixed_bad.v b/SVIncCompil/Testcases/Verilator/t_const_dec_mixed_bad.v new file mode 100644 index 0000000..5fc3d03 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_const_dec_mixed_bad.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005-2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + parameter [200:0] MIXED = 32'dx_1; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_const_overflow_bad.v b/SVIncCompil/Testcases/Verilator/t_const_overflow_bad.v new file mode 100644 index 0000000..2cb28a8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_const_overflow_bad.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005-2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; // One to many digits + + parameter [200:0] SMALLH = 8'habc; // One to many digits + parameter [200:0] SMALLO = 6'o1234; // One to many digits + parameter [200:0] SMALLB = 3'b1111; // One to many digits + + // We'll allow this though; no reason to be cruel + parameter [200:0] OKH = 8'h000000001; + + // bug1380 + parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_cover_line.v b/SVIncCompil/Testcases/Verilator/t_cover_line.v new file mode 100644 index 0000000..7cb84de --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_cover_line.v
@@ -0,0 +1,168 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg toggle; initial toggle=0; + + integer cyc; initial cyc=1; + wire [7:0] cyc_copy = cyc[7:0]; + + alpha a1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + alpha a2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + beta b1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + beta b2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + tsk t1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + off o1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= '0; + if (cyc==3) begin + toggle <= '1; + end + else if (cyc==5) begin +`ifdef VERILATOR + $c("call_task();"); +`else + call_task(); +`endif + end + else if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + task call_task; + /* verilator public */ + t1.center_task(1'b1); + endtask + +endmodule + +module alpha (/*AUTOARG*/ + // Inputs + clk, toggle + ); + input clk; + input toggle; + always @ (posedge clk) begin + if (toggle) begin + // CHECK_COVER(-1,"top.t.a*",2) + // t.a1 and t.a2 collapse to a count of 2 + end + if (toggle) begin + // CHECK_COVER_MISSING(-1) + // This doesn't even get added + // verilator coverage_block_off + $write(""); + end + end +endmodule + +module beta (/*AUTOARG*/ + // Inputs + clk, toggle + ); + input clk; + input toggle; + + /* verilator public_module */ + + always @ (posedge clk) begin + if (0) begin + // CHECK_COVER(-1,"top.t.b*",0) + // Make sure that we don't optimize away zero buckets + end + if (toggle) begin + // CHECK_COVER(-1,"top.t.b*",2) + // t.b1 and t.b2 collapse to a count of 2 + end + if (toggle) begin + // CHECK_COVER_MISSING(-1) + // This doesn't + // verilator coverage_block_off + $write(""); + end + end +endmodule + +module tsk (/*AUTOARG*/ + // Inputs + clk, toggle + ); + input clk; + input toggle; + + /* verilator public_module */ + + always @ (posedge clk) begin + center_task(1'b0); + end + + task center_task; + input external; + begin + if (toggle) begin + // CHECK_COVER(-1,"top.t.t1",1) + end + if (external) begin + // CHECK_COVER(-1,"top.t.t1",1) + $write("[%0t] Got external pulse\n", $time); + end + end + endtask + +endmodule + +module off (/*AUTOARG*/ + // Inputs + clk, toggle + ); + input clk; + input toggle; + + // verilator coverage_off + always @ (posedge clk) begin + if (toggle) begin + // CHECK_COVER_MISSING(-1) + // because under coverage_module_off + end + end + // verilator coverage_on + always @ (posedge clk) begin + if (toggle) begin + // CHECK_COVER(-1,"top.t.o1",1) + // because under coverage_module_off + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_cover_sva_notflat.v b/SVIncCompil/Testcases/Verilator/t_cover_sva_notflat.v new file mode 100644 index 0000000..59f9207 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_cover_sva_notflat.v
@@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg toggle; + integer cyc; initial cyc=1; + + Test suba (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); + Test subb (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); + Test subc (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==9) begin + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module Test + ( + input clk, + input toggle, + input [31:0] cyc + ); + + // Don't flatten out these modules please: + // verilator no_inline_module + + // Labeled cover + cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_cover_toggle.v b/SVIncCompil/Testcases/Verilator/t_cover_toggle.v new file mode 100644 index 0000000..e1979e6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_cover_toggle.v
@@ -0,0 +1,155 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + typedef struct packed { + union packed { + logic ua; + logic ub; + } u; + logic b; + } str_t; + + reg toggle; initial toggle='0; + + str_t stoggle; initial stoggle='0; + + const reg aconst = '0; + + reg [1:0][1:0] ptoggle; initial ptoggle=0; + + integer cyc; initial cyc=1; + wire [7:0] cyc_copy = cyc[7:0]; + wire toggle_up; + + alpha a1 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); + alpha a2 (/*AUTOINST*/ + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); + + beta b1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle_up (toggle_up)); + + off o1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle)); + + reg [1:0] memory[121:110]; + + reg [1023:0] largeish; + // CHECK_COVER_MISSING(-1) + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; + toggle <= '0; + stoggle.u <= toggle; + stoggle.b <= toggle; + ptoggle[0][0] <= toggle; + if (cyc==3) begin + toggle <= '1; + end + if (cyc==4) begin + toggle <= '0; + end + else if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module alpha (/*AUTOARG*/ + // Outputs + toggle_up, + // Inputs + clk, toggle, cyc_copy + ); + + // t.a1 and t.a2 collapse to a count of 2 + + input clk; + + input toggle; + // CHECK_COVER(-1,"top.t.a*",4) + // 2 edges * (t.a1 and t.a2) + + input [7:0] cyc_copy; + // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22) + // CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10) + // CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4) + // CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2) + // CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0) + // CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0) + // CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0) + // CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0) + + reg toggle_internal; + // CHECK_COVER(-1,"top.t.a*",4) + // 2 edges * (t.a1 and t.a2) + + output reg toggle_up; + // CHECK_COVER(-1,"top.t.a*",4) + // 2 edges * (t.a1 and t.a2) + + always @ (posedge clk) begin + toggle_internal <= toggle; + toggle_up <= toggle; + end +endmodule + +module beta (/*AUTOARG*/ + // Inputs + clk, toggle_up + ); + + input clk; + + input toggle_up; + // CHECK_COVER(-1,"top.t.b1","toggle_up",2) + + /* verilator public_module */ + + always @ (posedge clk) begin + if (0 && toggle_up) begin end + end +endmodule + +module off (/*AUTOARG*/ + // Inputs + clk, toggle + ); + + // verilator coverage_off + input clk; + // CHECK_COVER_MISSING(-1) + + // verilator coverage_on + input toggle; + // CHECK_COVER(-1,"top.t.o1","toggle",2) + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_crazy_sel.v b/SVIncCompil/Testcases/Verilator/t_crazy_sel.v new file mode 100644 index 0000000..985978c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_crazy_sel.v
@@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference +// as the select expression +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +interface foo_intf; + logic a; +endinterface + +function integer the_other_func (input integer val); + return val; +endfunction + +module t (/*AUTOARG*/); + genvar the_genvar; + generate + for (the_genvar = 0; the_genvar < 4; the_genvar++) begin: foo_loop + foo foo_inst(); + end + endgenerate + + bar bar_inst(); + + logic x; + assign x = foo_loop[bar_inst.THE_LP].foo_inst.y; + //localparam N = 2; + //assign x = foo_loop[N].foo_inst.y; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module foo(); + logic y; +endmodule + +module bar(); + localparam THE_LP = 2; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dedupe_clk_gate.v b/SVIncCompil/Testcases/Verilator/t_dedupe_clk_gate.v new file mode 100644 index 0000000..fda3b8d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dedupe_clk_gate.v
@@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Dedupe optimization test. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// Contributed 2012 by Varun Koyyalagunta, Centaur Technology. + +module t(res,d,clk,en); + output res; + input d,en,clk; + wire q0,q1,q2,q3; + + flop_gated_latch f0(q0,d,clk,en); + flop_gated_latch f1(q1,d,clk,en); + flop_gated_flop f2(q2,d,clk,en); + flop_gated_flop f3(q3,d,clk,en); + assign res = (q0 + q1) * (q2 - q3); +endmodule + +module flop_gated_latch(q,d,clk,en); + input d, clk, en; + output q; + wire gated_clock; + clock_gate_latch clock_gate(gated_clock, clk, en); + always @(posedge gated_clock) begin + q <= d; + end +endmodule + +module flop_gated_flop(q,d,clk,en); + input d, clk, en; + output q; + wire gated_clock; + clock_gate_flop clock_gate(gated_clock, clk, en); + always @(posedge gated_clock) begin + q <= d; + end +endmodule + +module clock_gate_latch (gated_clk, clk, clken); + output gated_clk; + input clk, clken; + reg clken_latched /*verilator clock_enable*/; + assign gated_clk = clk & clken_latched ; + + wire clkb = ~clk; + always @(clkb or clken) + if(clkb) clken_latched = clken; + +endmodule + +module clock_gate_flop (gated_clk, clk, clken); + output gated_clk; + input clk, clken; + reg clken_r /*verilator clock_enable*/; + assign gated_clk = clk & clken_r ; + + always @(negedge clk) + clken_r <= clken; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dedupe_seq_logic.v b/SVIncCompil/Testcases/Verilator/t_dedupe_seq_logic.v new file mode 100644 index 0000000..332214f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dedupe_seq_logic.v
@@ -0,0 +1,123 @@ +// DESCRIPTION: Verilator: Dedupe optimization test. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// Contributed 2012 by Varun Koyyalagunta, Centaur Technology. +// +// Test consists of the follow logic tree, which has many obvious +// places for dedupe: +/* + output + + + --------------/ \-------------- + / \ + + + + ----/ \----- ----/ \---- + / + / + + + / \ + / \ + -/ \- a b -/ \- a b + / \ / \ + + + + + + / \ / \ / \ / \ + a b c d a b c d +*/ + +module t(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + wire left,right; + add add(sum,left,right,clk); + l l(left,a,b,c,d,clk); + r r(right,a,b,c,d,clk); +endmodule + +module l(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + wire left, right; + add add(sum,left,right,clk); + ll ll(left,a,b,c,d,clk); + lr lr(right,a,b,c,d,clk); +endmodule + +module ll(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + wire left, right; + add add(sum,left,right,clk); + lll lll(left,a,b,c,d,clk); + llr llr(right,a,b,c,d,clk); +endmodule + +module lll(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + add add(sum,a,b,clk); +endmodule + +module llr(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + add add(sum,c,d,clk); +endmodule + +module lr(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + add add(sum,a,b,clk); +endmodule + +module r(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + wire left, right; + add add(sum,left,right,clk); + rl rl(left,a,b,c,d,clk); + rr rr(right,a,b,c,d,clk); +endmodule + +module rr(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + add add(sum,a,b,clk); +endmodule + +module rl(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + wire left, right; + add add(sum,left,right,clk); + rll rll(left,a,b,c,d,clk); + rlr rlr(right,a,b,c,d,clk); +endmodule + +module rll(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + add2 add(sum,a,b,clk); +endmodule + +module rlr(sum,a,b,c,d,clk); + output sum; + input a,b,c,d,clk; + add2 add(sum,c,d,clk); +endmodule + +module add(sum,x,y,clk); + output sum; + input x,y,clk; + reg t1,t2; + always @(posedge clk) begin + sum <= x + y; + end +endmodule + +module add2(sum,x,y,clk); + output sum; + input x,y,clk; + reg t1,t2; + always @(posedge clk) begin + sum <= x + y; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_delay.v b/SVIncCompil/Testcases/Verilator/t_delay.v new file mode 100644 index 0000000..3b41e41 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_delay.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + parameter PAR = 3; + + input clk; + integer cyc=1; + + reg [31:0] dly0; + wire [31:0] dly1; + wire [31:0] dly2 = dly1 + 32'h1; + + assign #(1.2000000000000000) dly1 = dly0 + 32'h1; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + dly0 <= #0 32'h11; + end + else if (cyc==2) begin + dly0 <= #0.12 dly0 + 32'h12; + end + else if (cyc==3) begin + if (dly0 !== 32'h23) $stop; + if (dly2 !== 32'h25) $stop; + $write("*-* All Finished *-*\n"); + #100 $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_detectarray_1.v b/SVIncCompil/Testcases/Verilator/t_detectarray_1.v new file mode 100644 index 0000000..73834ea --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_detectarray_1.v
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Trigger the DETECTARRAY error. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +localparam ID_MSB = 1; + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + typedef struct packed { + logic [ID_MSB:0] id; + } context_t; + + context_t tsb; + + assign tsb.id = {tsb.id[0], clk}; + + initial begin + tsb.id = 0; + end + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write("tsb.id = %x\n", tsb.id); +`endif + + if (tsb.id[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_detectarray_2.v b/SVIncCompil/Testcases/Verilator/t_detectarray_2.v new file mode 100644 index 0000000..77eb061 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_detectarray_2.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// This should trigger the DETECTARRAY error like t_detectarray_1.v, but in +// fact it casuses a broken link error. The only difference is that the struct +// is defined using a constant rather than a localparam. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +localparam ID_MSB = 1; + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + typedef struct packed { + logic [1:0] id; + } context_t; + + context_t tsb; + + assign tsb.id = {tsb.id[0], clk}; + + initial begin + tsb.id = 0; + end + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write("tsb.id = %x\n", tsb.id); +`endif + + if (tsb.id[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_detectarray_3.v b/SVIncCompil/Testcases/Verilator/t_detectarray_3.v new file mode 100644 index 0000000..932bebb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_detectarray_3.v
@@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Trigger the DETECTARRAY error on packed structure. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jie Xu. + +localparam ID_MSB = 1; + + +module t (/*AUTOARG*/ + // Inputs + clk, + res + ); + input clk; + output [8:0][8:0] res; + + logic a = 1'b1; + logic [8:0] b [8:0]; // where the error is reported + logic [8:0][8:0] c; // where the error is reported + + // following just to make c as circular + assign c[0] = c[0] | a << 1; + assign b[0] = b[0] | a << 2; + + assign res[0] = c[0]; + assign res[1] = b[0]; + + + always @(posedge clk or negedge clk) begin + + if (res != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display.v b/SVIncCompil/Testcases/Verilator/t_display.v new file mode 100644 index 0000000..87fff05 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display.v
@@ -0,0 +1,168 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + reg [40:0] quad; initial quad = 41'ha_bbbb_cccc; + reg [80:0] wide; initial wide = 81'habc_1234_5678_1234_5678; + reg [8:0] nine; initial nine = 12; + reg signed [40:0] quads; initial quads = -(41'sha_bbbb_cccc); + reg signed [80:0] wides; initial wides = -(81'shabc_1234_5678_1234_5678); + reg signed [8:0] nines; initial nines = -12; + reg [31:0] str; initial str = "\000\277\021\n"; + reg [47:0] str2; initial str2 = "\000what!"; + reg [79:0] str3; initial str3 = "\000hmmm!1234"; + string svs = "sv-str"; + + sub sub (); + sub2 sub2 (); + + initial begin + $write("[%0t] In %m: Hi\n", $time); + sub.write_m; + sub2.write_m; + + // Escapes + $display("[%0t] Back \\ Quote \"", $time); // Old bug when \" last on the line. + + // Display formatting - constants + $display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time, + 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + + $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, + 9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc), + 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); + $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, + 9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc), + -(81'shabc_1234_5678_1234_5678), -(81'shabc_1234_5678_1234_5678)); + + // Display formatting + $display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time, + nine, nine, quad, quad, wide, wide); + + $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, + nines, nines, quads, quads, wides, wides); + $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, + nines, nines, quads, quads, wides, wides); + // + // verilator lint_off WIDTH + $display("[%0t] %%C=%C %%0C=%0C", $time, + "a"+nine, "a"+nine); + $display("[%0t] %%c=%c %%0c=%0c", $time, + "a"+nine, "a"+nine); + // verilator lint_on WIDTH + + $display("[%0t] %%v=%v %%0v=%0v %%v=%v %%0v=%0v %%v=%v %%0v=%0v <", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%V=%V %%0V=%0V %%V=%V %%0V=%0V %%V=%V %%0V=%0V <", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%p=%p %%0p=%0p %%p=%p %%0p=%0p %%p=%p %%0p=%0p", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%P=%P %%0P=%0P %%P=%P %%0P=%0P %%P=%P %%0P=%0P", $time, + nine, nine, quad, quad, wide, wide); + $display("[%0t] %%P=%P", $time, + svs); + + $display("[%0t] %%u=%u %%0u=%0u", $time, + {"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output + $display("[%0t] %%U=%U %%0U=%0U", $time, + {"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output + // %z is tested in t_sys_sformat.v + + $display("[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d", $time, + nine, nine, nine, nine, nine); + $display("[%0t] %%t=%t %%03t=%03t %%0t=%0t", $time, + $time, $time, $time); + $display; + // Not testing %0s, it does different things in different simulators + $display("[%0t] %%s=%s %%s=%s %%s=%s", $time, + str2[7:0], str2, str3); + + $display("[%0t] %s%s%s", $time, + "hel", "lo, fr", "om a very long string. Percent %s are literally substituted in."); + $display("hel", "lo, fr", "om a concatenated string."); + $write("hel", "lo, fr", "om a concatenated format string [%0t].\n", $time); + $display("extra argument: ", $time); + $display($time, ": pre argument"); + $write("[%0t] Embedded \r return\n", $time); + $display("[%0t] Embedded\ +multiline", $time); + + // Str check +`ifndef NC // NC-Verilog 5.3 chokes on this test + if (str !== 32'h00_bf_11_0a) $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub; + task write_m; + begin + $write("[%0t] In %m (%l)\n", $time); + begin : subblock + $write("[%0t] In %M (%L)\n", $time); // Uppercase %M test + end + end + endtask +endmodule + +module sub2; + // verilator no_inline_module + task write_m; + begin + $write("[%0t] In %m (%l)\n", $time); + begin : subblock2 + $write("[%0t] In %m (%L)\n", $time); + end + end + endtask +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_bad.v b/SVIncCompil/Testcases/Verilator/t_display_bad.v new file mode 100644 index 0000000..fda28df --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_bad.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + reg [40:0] disp; initial disp = 41'ha_bbbb_cccc; + initial begin + // Display formatting + $display("%x"); // Too few + $display("%x",disp,disp); // Too many + $display("%q"); // Bad escape + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_esc_bad.v b/SVIncCompil/Testcases/Verilator/t_display_esc_bad.v new file mode 100644 index 0000000..ec0b008 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_esc_bad.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t; + initial begin + $display("\x\y\z"); // Illegal escapes + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_l.v b/SVIncCompil/Testcases/Verilator/t_display_l.v new file mode 100644 index 0000000..c299f67 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_l.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: $display() test for %l +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +module t (/*AUTOARG*/); + + initial begin + assert (0 == 0) else $fatal(2, "%l %m : %d", 0); + $display("%l %m"); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_mcd.v b/SVIncCompil/Testcases/Verilator/t_display_mcd.v new file mode 100644 index 0000000..db3c3e1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_mcd.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t; + initial begin + $fwrite(32'h8000_0001, "To stdout\n"); + $fflush(32'h8000_0001); + $fwrite(32'h8000_0002, "To stderr\n"); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_merge.v b/SVIncCompil/Testcases/Verilator/t_display_merge.v new file mode 100644 index 0000000..c8e83b1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_merge.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/); + initial begin + $display("Merge:"); + $write("This "); + $write("should "); + $display("merge"); + + $display("f"); + $display(" a=%m"); + $display(" b=%m"); + $display(" pre"); + $display(" t=%0d",$time); + $display(" t2=%0d",$time); + $display(" post"); + $display(" t3=%0d",$time); + $display(" t4=%0d t5=%0d",$time,$time,$time); + $display("m"); + $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time); + $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time); + $display("mm"); + $display(""); + + $write("f"); + $write(" a=%m"); + $write(" b=%m"); + $write(" pre"); + $write(" t=%0d",$time); + $write(" t2=%0d",$time); + $write(" post"); + $write(" t3=%0d",$time); + $write(" t4=%0d t5=%0d",$time,$time,$time); + $write("m"); + $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time); + $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time); + $display("mm"); + + $write("\n*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_real.v b/SVIncCompil/Testcases/Verilator/t_display_real.v new file mode 100644 index 0000000..67235af --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_real.v
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + real n0; initial n0 = 0.0; + real n1; initial n1 = 1.0; + real n2; initial n2 = 0.1; + real n3; initial n3 = 1.2345e-15; + real n4; initial n4 = 2.579e+15; + reg [7:0] r8; initial r8 = 3; + + initial begin + // Display formatting + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n0,n0,n0,n0); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n0,n0,n0,n0); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n0,n0,n0,n0); + $display; + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n1,n1,n1,n1); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n1,n1,n1,n1); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n1,n1,n1,n1); + $display; + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n2,n2,n2,n2); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n2,n2,n2,n2); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n2,n2,n2,n2); + $display; + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n3,n3,n3,n3); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n3,n3,n3,n3); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n3,n3,n3,n3); + $display; + $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n4,n4,n4,n4); + $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n4,n4,n4,n4); + $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n4,n4,n4,n4); + $display; + $display("r8=%d n1=%g n2=%g", r8, n1, n2); + $display("n1=%g n2=%g r8=%d", n1, n2, r8); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_realtime.v b/SVIncCompil/Testcases/Verilator/t_display_realtime.v new file mode 100644 index 0000000..2ab57a4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_realtime.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + always @ (posedge clk) begin + cyc <= cyc + 1; + $display("TestCase at %1t (%s)", $realtime, cyc[0] ? "Option1" : "Option2"); + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_signed.v b/SVIncCompil/Testcases/Verilator/t_display_signed.v new file mode 100644 index 0000000..1db324f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_signed.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + reg signed [20:0] longp; initial longp = 21'shbbccc; + reg signed [20:0] longn; initial longn = 21'shbbccc; initial longn[20]=1'b1; + reg signed [40:0] quadp; initial quadp = 41'sh1_bbbb_cccc; + reg signed [40:0] quadn; initial quadn = 41'sh1_bbbb_cccc; initial quadn[40]=1'b1; + reg signed [80:0] widep; initial widep = 81'shbc_1234_5678_1234_5678; + reg signed [80:0] widen; initial widen = 81'shbc_1234_5678_1234_5678; initial widen[40]=1'b1; + + initial begin + // Display formatting + $display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time, + longp, longp, longp, longp, longp, longp); + $display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time, + longn, longn, longn, longn, longn, longn); + $display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time, + quadp, quadp, quadp, quadp, quadp, quadp); + $display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time, + quadn, quadn, quadn, quadn, quadn, quadn); + $display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b", $time, + widep, widep, widep, widep); + $display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b", $time, + widen, widen, widen, widen); + $display; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_string.v b/SVIncCompil/Testcases/Verilator/t_display_string.v new file mode 100644 index 0000000..f2bd7de --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_string.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + function automatic string foo(int i); + return $sformatf("'%d'", i); // %0d does not work here + endfunction + real r = 1.234; + string bar = foo(1); + localparam string pbar = foo(1); + initial begin + $write("String: "); $display("' 1'"); + $write("foo(1): "); $display(foo(1)); + $write("s f(1): "); $display("%s", foo(1)); + $write("s parm: "); $display("%s", pbar); + $write("s strg: "); $display("%s", bar); + $write("r: "); $display(r); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_time.v b/SVIncCompil/Testcases/Verilator/t_display_time.v new file mode 100644 index 0000000..33e77dd --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_time.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +`timescale 1ns/1ns + +module t; + initial begin + // Display formatting + $write; // Check missing arguments work + $write("default: [%0t] 0t time [%t] No0 time\n",$time,$time); +`ifndef verilator // Unsupported + $timeformat(-9, 0, "", 0); + $write("-9,0,,0: [%0t] 0t time [%t] No0 time\n",$time,$time); + $timeformat(-9, 0, "", 10); + $write("-9,0,,10: [%0t] 0t time [%t] No0 time\n",$time,$time); + $timeformat(-9, 0, "ns", 5); + $write("-9,0,ns,5: [%0t] 0t time [%t] No0 time\n",$time,$time); + $timeformat(-9, 3, "ns", 8); + $write("-9,3,ns,8: [%0t] 0t time [%t] No0 time\n",$time,$time); +`endif + $write("\n"); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_display_wide.v b/SVIncCompil/Testcases/Verilator/t_display_wide.v new file mode 100644 index 0000000..0e583b5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_display_wide.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [4095:0] crc; + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :) + if (cyc==0) begin + // Setup + crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]); + $write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]); + //Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc); + if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc + ) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dos.v b/SVIncCompil/Testcases/Verilator/t_dos.v new file mode 100755 index 0000000..1b239bf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dos.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +// This file has DOS carrage returns in it! +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule +// This file has DOS carrage returns in it!
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_2exp_bad.v b/SVIncCompil/Testcases/Verilator/t_dpi_2exp_bad.v new file mode 100644 index 0000000..7e540f3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_2exp_bad.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t; + + export "DPI-C" task dpix_twice; + export "DPI-C" dpix_t_int_renamed = task dpix_twice; + task dpix_twice(input int i, output int o); o = ~i; endtask + + initial begin + $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_accessors.v b/SVIncCompil/Testcases/Verilator/t_dpi_accessors.v new file mode 100644 index 0000000..a08b985 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_accessors.v
@@ -0,0 +1,95 @@ +// DESCRIPTION: Verilator: Test for using DPI as general accessors +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. +// +// Contributed by Jeremy Bennett and Jie Xul +// +// This test exercises the use of DPI to access signals and registers in a +// module hierarchy in a uniform fashion. See the discussion at +// +// http://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables +// +// We need to test read and write access to: +// - scalars +// - vectors +// - array elements +// - slices of vectors or array elements +// +// We need to test that writing to non-writable elements generates an error. +// +// This Verilog would run forever. It will be stopped externally by the C++ +// instantiating program. + + +// Define the width of registers and size of memory we use +`define REG_WIDTH 8 +`define MEM_SIZE 256 + + +// Top module defines the accessors and instantiates a sub-module with +// substantive content. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + `include "t_dpi_accessors_macros_inc.vh" + `include "t_dpi_accessors_inc.vh" + + // Put the serious stuff in a sub-module, so we can check hierarchical + // access works OK. + test_sub i_test_sub (.clk (clk)); + +endmodule // t + + +// A sub-module with all sorts of goodies we would like to access + +module test_sub (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer i; // General counter + + // Elements we would like to access from outside + reg a; + reg [`REG_WIDTH - 1:0] b; + reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0]; + wire c; + wire [`REG_WIDTH - 1:0] d; + reg [`REG_WIDTH - 1:0] e; + reg [`REG_WIDTH - 1:0] f; + + // Drive our wires from our registers + assign c = ~a; + assign d = ~b; + + // Initial values for registers and array + initial begin + a = 0; + b = `REG_WIDTH'h0; + + for (i = 0; i < `MEM_SIZE; i++) begin + mem[i] = i [`REG_WIDTH - 1:0]; + end + + e = 0; + f = 0; + end + + // Wipe out one memory cell in turn on the positive clock edge, restoring + // the previous element. We toggle the wipeout value. + always @(posedge clk) begin + mem[b] <= {`REG_WIDTH {a}}; + mem[b - 1] <= b - 1; + a <= ~a; + b <= b + 1; + end + +endmodule // test_sub
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_accessors_inc.vh b/SVIncCompil/Testcases/Verilator/t_dpi_accessors_inc.vh new file mode 100644 index 0000000..02b0de1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_accessors_inc.vh
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Accessor definitions for test of DPI accessors +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by Jeremy Bennett and Jie Xu + +// See t_dpi_accessors.v for details of the test. This file should be included +// by the top level module to define all the accessors needed. + + // Use the macros to provide the desire access to our data. First simple + // access to the registers, array elements and wires. For consistency with + // simulators, we do not attempt to write wires. + `RW_ACCESS([0:0], a, {t.i_test_sub.a}); + `RW_ACCESS([7:0], b, {t.i_test_sub.b}); + `RW_ACCESS([7:0], mem32, {t.i_test_sub.mem[32]}); + `R_ACCESS ([0:0], c, {t.i_test_sub.c}); + `R_ACCESS ([7:0], d, {t.i_test_sub.d}); + `RW_ACCESS([7:0], e, {t.i_test_sub.e}); + `RW_ACCESS([7:0], f, {t.i_test_sub.f}); + + // Slices of vectors and array elements. For consistency with simulators, + // we do not attempt to write wire slices. + `RW_ACCESS([3:0], b_slice, {t.i_test_sub.b[3:0]}); + `RW_ACCESS([4:0], mem32_slice, + {t.i_test_sub.mem[32][7:6], t.i_test_sub.mem[32][2:0]}); + `R_ACCESS([5:0], d_slice, {t.i_test_sub.d[6:1]}); + + // Complex registers, one with distinct read and write. We avoid use of + // wires for consistency with simulators. + `RW_ACCESS([14:0], l1, {t.i_test_sub.b[3:0], + t.i_test_sub.mem[32][7:6], + t.i_test_sub.e[6:1], + t.i_test_sub.mem[32][2:0]}); + `R_ACCESS([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]}); + `W_ACCESS([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]});
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_accessors_macros_inc.vh b/SVIncCompil/Testcases/Verilator/t_dpi_accessors_macros_inc.vh new file mode 100644 index 0000000..18a19b8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_accessors_macros_inc.vh
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Generic accessor macros for test of DPI accessors +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. +// +// Contributed by Jeremy Bennett and Jie Xu +// +// See t_dpi_accessors.v for details of the test. This file should be included +// by the top level module to define the generic accessor macros. + +// Accessor macros, to keep stuff concise +`define R_ACCESS(type_spec, name, expr) \ + export "DPI-C" function name``_read; \ + function bit type_spec name``_read; \ + name``_read = (expr); \ + endfunction + +`define W_ACCESS(type_spec, name, expr) \ + export "DPI-C" task name``_write; \ + task name``_write; \ + input bit type_spec in; \ + expr = in; \ + endtask + +`define RW_ACCESS(type_spec, name, expr) \ + `R_ACCESS (type_spec, name, expr); \ + `W_ACCESS (type_spec, name, expr)
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_context.v b/SVIncCompil/Testcases/Verilator/t_dpi_context.v new file mode 100644 index 0000000..d92fff4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_context.v
@@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (); + + sub a (.inst(1)); + sub b (.inst(2)); + + initial begin + a.test1; + b.test1; + a.test2; + b.test2; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module sub (input integer inst); + + import "DPI-C" context function int dpic_line(); + import "DPI-C" context function int dpic_save(int value); + import "DPI-C" context function int dpic_restore(); + import "DPI-C" context function int unsigned dpic_getcontext(); + + int result; + + task test1; + // Check line numbering +`ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test + result = dpic_line(); if (!result) $stop; +`else + result = dpic_line(); if (result !== `__LINE__) $stop; + // + result = dpic_line(); if (result !== `__LINE__) $stop; +`endif + + // Check save-restore + result = dpic_save(23+inst); + if (result==0) $stop; + endtask + + task test2; + if (dpic_restore() != 23+inst) $stop; + endtask + + int unsigned cntxt1; + int unsigned cntxt2; + + initial begin + cntxt1 = dpic_getcontext(); + begin : caller_context + // call from a different scope - should still get the context of the function declaration + cntxt2 = dpic_getcontext(); + end + // svContext should be the context of the function declaration, not the context of the function call + if (cntxt1 != cntxt2) $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_display.v b/SVIncCompil/Testcases/Verilator/t_dpi_display.v new file mode 100644 index 0000000..3fc8f1a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_display.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (); + +`ifndef VERILATOR + `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." +`endif + + import "DPI-C" context dpii_display_call + = function void \$dpii_display (input string formatted /*verilator sformat*/ ); + + integer a; + + initial begin + // Check variable width constant string conversions + $dpii_display(""); + $dpii_display("c"); + $dpii_display("co"); + $dpii_display("cons"); + $dpii_display("constant"); + $dpii_display("constant_value"); + + a = $c("10"); // Don't optimize away "a" + $display ("one10=%x",a); // Check single arg + $dpii_display("one10=%x",a); + $display ("Mod=%m 16=%d 10=%x",a,a); // Check multiarg + $dpii_display("Mod=%m 16=%d 10=%x",a,a); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_dup_bad.v b/SVIncCompil/Testcases/Verilator/t_dpi_dup_bad.v new file mode 100644 index 0000000..8b59d29 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_dup_bad.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (); + + // Same name w/ different args + import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); + import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); + + initial begin + $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_exp_bad.v b/SVIncCompil/Testcases/Verilator/t_dpi_exp_bad.v new file mode 100644 index 0000000..7659059 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_exp_bad.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t; + + export "DPI-C" function dpix_f_bit48; + function bit [47:0] dpix_f_bit48(bit [47:0] i); dpix_f_bit48 = ~i; endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_export.v b/SVIncCompil/Testcases/Verilator/t_dpi_export.v new file mode 100644 index 0000000..a7eed54 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_export.v
@@ -0,0 +1,89 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VCS + `define NO_TIME +`endif +`ifdef NC + `define NO_TIME +`endif + +module t; + + sub a (.inst(1)); + sub b (.inst(2)); + + // Returns integer line number, or -1 for all ok + import "DPI-C" context function int dpix_run_tests(); + + export "DPI-C" task dpix_t_int; + task dpix_t_int(input int i, output int o); o = ~i; endtask + + export "DPI-C" dpix_t_renamed = task dpix_t_ren; + task dpix_t_ren(input int i, output int o); o = i+2; endtask + + export "DPI-C" function dpix_int123; + function int dpix_int123(); dpix_int123 = 32'h123; endfunction + + export "DPI-C" function dpix_f_bit; + export "DPI-C" function dpix_f_bit15; + export "DPI-C" function dpix_f_int; + export "DPI-C" function dpix_f_byte; + export "DPI-C" function dpix_f_shortint; + export "DPI-C" function dpix_f_longint; + export "DPI-C" function dpix_f_chandle; + + function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction + function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction + function int dpix_f_int (int i); dpix_f_int = ~i; endfunction + function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction + function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction + function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction + function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction + + export "DPI-C" task dpix_t_bit48; + task dpix_t_bit48(input bit [47:0] i, output bit [47:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_bit95; + task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_bit96; + task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask + + export "DPI-C" task dpix_t_reg; + task dpix_t_reg(input reg i, output reg o); o = ~i; endtask + export "DPI-C" task dpix_t_reg15; + task dpix_t_reg15(input reg [14:0] i, output reg [14:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_reg95; + task dpix_t_reg95(input reg [94:0] i, output reg [94:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_integer; + task dpix_t_integer(input integer i, output integer o); o = ~i; endtask +`ifndef NO_TIME + export "DPI-C" task dpix_t_time; +`endif + task dpix_t_time(input time i, output time o); o = ~i; endtask + + int lineno; + + initial begin + lineno = dpix_run_tests(); + if (lineno != -1) begin + $display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno); + $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module sub (input int inst); + + export "DPI-C" function dpix_sub_inst; + + function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_imp_gen.v b/SVIncCompil/Testcases/Verilator/t_dpi_imp_gen.v new file mode 100644 index 0000000..2e43678 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_imp_gen.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter integer BLKS = 3; + + generate + for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice + + import "DPI-C" context function void dpi_genvarTest (); + + initial begin + dpi_genvarTest(); + $display("slice = %0d : %m", blkIdx); + end + end + endgenerate + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_import.v b/SVIncCompil/Testcases/Verilator/t_dpi_import.v new file mode 100644 index 0000000..e78cb28 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_import.v
@@ -0,0 +1,265 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VCS + `define NO_SHORTREAL + `define NO_TIME +`endif +`ifdef NC + `define NO_SHORTREAL + `define NO_TIME +`endif +`ifdef VERILATOR // Unsupported + `define NO_SHORTREAL +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + typedef struct packed { bit [47:0] lo; bit [47:0] hi; } str_t; + typedef struct packed { int a; int b; } substr_t; + + // Allowed import return types: + // void, byte, shortint, int, longint, real, shortreal, chandle, and string + // Scalar bit and logic + // + // Allowed argument types: + // Same as above plus packed arrays + + import "DPI-C" pure function bit dpii_f_bit (input bit i); + import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i); + import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i); + import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i); + import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i); + import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i); + // Illegal to return > 32 bits, so we use longint + import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i); + import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i); + import "DPI-C" pure function int dpii_f_int (input int i); + import "DPI-C" pure function byte dpii_f_byte (input byte i); + import "DPI-C" pure function shortint dpii_f_shortint (input shortint i); + import "DPI-C" pure function longint dpii_f_longint (input longint i); + import "DPI-C" pure function chandle dpii_f_chandle (input chandle i); + import "DPI-C" pure function string dpii_f_string (input string i); + import "DPI-C" pure function real dpii_f_real (input real i); +`ifndef NO_SHORTREAL + import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i); +`endif + + import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o); + import "DPI-C" pure function void dpii_v_int (input int i, output int o); + import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o); + import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o); + import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o); + import "DPI-C" pure function void dpii_v_struct (input str_t i, output str_t o); + import "DPI-C" pure function void dpii_v_substruct(input substr_t i, output int o); + import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o); + import "DPI-C" pure function void dpii_v_string (input string i, inout string o); + import "DPI-C" pure function void dpii_v_real (input real i, output real o); + + import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o); + import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o); + import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o); +`ifndef NO_SHORTREAL + import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o); +`endif + import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o); + import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o); + import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o); + + import "DPI-C" pure function void dpii_v_reg (input reg i, output reg o); + import "DPI-C" pure function void dpii_v_reg15 (input reg [14:0] i, output reg [14:0] o); + import "DPI-C" pure function void dpii_v_reg95 (input reg [94:0] i, output reg [94:0] o); + import "DPI-C" pure function void dpii_v_integer (input integer i, output integer o); +`ifndef NO_TIME + import "DPI-C" pure function void dpii_v_time (input time i, output time o); +`endif + + import "DPI-C" pure function int dpii_f_strlen (input string i); + + import "DPI-C" function void dpii_f_void (); + + // Try a task + import "DPI-C" task dpii_t_void (); + import "DPI-C" context task dpii_t_void_context (); + + import "DPI-C" task dpii_t_int (input int i, output int o); + + // Try non-pure, aliasing with name + import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); + import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i); + + bit i_b, o_b; + bit [7:0] i_b8; + bit [8:0] i_b9; + bit [15:0] i_b16; + bit [16:0] i_b17; + bit [31:0] i_b32; + bit [32:0] i_b33, o_b33; + bit [63:0] i_b64, o_b64; + bit [94:0] i_b95, o_b95; + bit [95:0] i_b96, o_b96; + + int i_i, o_i; + byte i_y, o_y; + shortint i_s, o_s; + longint i_l, o_l; + str_t i_t, o_t; + substr_t i_ss; + int o_ss; + int unsigned i_iu, o_iu; + shortint unsigned i_su, o_su; + longint unsigned i_lu, o_lu; + // verilator lint_off UNDRIVEN + chandle i_c, o_c; + string i_n, o_n; + // verilator lint_on UNDRIVEN + real i_d, o_d; +`ifndef NO_SHORTREAL + shortreal i_f, o_f; +`endif + + reg i_r, o_r; + reg [14:0] i_r15, o_r15; + reg [94:0] i_r95, o_r95; + integer i_in, o_in; + time i_tm, o_tm; + + bit [94:0] wide; + + bit [6*8:1] string6; + + initial begin + wide = 95'h15caff7a73c48afee4ffcb57; + + i_b = 1'b1; + i_b8 = {1'b1,wide[8-2:0]}; + i_b9 = {1'b1,wide[9-2:0]}; + i_b16 = {1'b1,wide[16-2:0]}; + i_b17 = {1'b1,wide[17-2:0]}; + i_b32 = {1'b1,wide[32-2:0]}; + i_b33 = {1'b1,wide[33-2:0]}; + i_b64 = {1'b1,wide[64-2:0]}; + i_b95 = {1'b1,wide[95-2:0]}; + i_b96 = {1'b1,wide[96-2:0]}; + + i_i = {1'b1,wide[32-2:0]}; + i_iu= {1'b1,wide[32-2:0]}; + i_y = {1'b1,wide[8-2:0]}; + i_s = {1'b1,wide[16-2:0]}; + i_su= {1'b1,wide[16-2:0]}; + i_l = {1'b1,wide[64-2:0]}; + i_lu= {1'b1,wide[64-2:0]}; + i_t = {1'b1,wide[95-1:0]}; + i_d = 32.1; + + i_ss.a = 32'h054321ab; + i_ss.b = 32'h05a43b21; + +`ifndef NO_SHORTREAL + i_f = 30.2; +`endif + + i_r = '0; + i_r15 = wide[14:0]; + i_r95 = wide[94:0]; + i_in = -1234; + i_tm = 62; + + if (dpii_f_bit (i_b) !== ~i_b) $stop; + if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop; + if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop; + if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop; + if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop; + if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop; + + // These return different sizes, so we need to truncate + // verilator lint_off WIDTH + o_b33 = dpii_f_bit33 (i_b33); + o_b64 = dpii_f_bit64 (i_b64); + // verilator lint_on WIDTH + if (o_b33 !== ~i_b33) $stop; + if (o_b64 !== ~i_b64) $stop; + + if (dpii_f_bit (i_b) !== ~i_b) $stop; + if (dpii_f_int (i_i) !== ~i_i) $stop; + if (dpii_f_byte (i_y) !== ~i_y) $stop; + if (dpii_f_shortint (i_s) !== ~i_s) $stop; + if (dpii_f_longint (i_l) !== ~i_l) $stop; + if (dpii_f_chandle (i_c) !== i_c) $stop; + if (dpii_f_string (i_n) != i_n) $stop; + if (dpii_f_real (i_d) != i_d+1.5) $stop; +`ifndef NO_SHORTREAL + if (dpii_f_shortreal(i_f) != i_f+1.5) $stop; +`endif + + dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; + dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop; + dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop; + dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop; + dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop; + dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop; + dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop; + dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop; + dpii_v_struct (i_t,o_t); if (o_t !== ~i_t) $stop; + dpii_v_substruct(i_ss,o_ss); if (o_ss !== i_ss.a - i_ss.b) $stop; + dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop; + dpii_v_string (i_n,o_n); if (o_n != i_n) $stop; + dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop; +`ifndef NO_SHORTREAL + dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop; +`endif + dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop; + dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop; + dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop; + + dpii_v_reg (i_r,o_r); if (o_r !== ~i_r) $stop; + dpii_v_reg15 (i_r15,o_r15); if (o_r15 !== ~i_r15) $stop; + dpii_v_reg95 (i_r95,o_r95); if (o_r95 !== ~i_r95) $stop; + dpii_v_integer (i_in,o_in); if (o_in != ~i_in) $stop; +`ifndef NO_TIME + dpii_v_time (i_tm,o_tm); if (o_tm != ~i_tm) $stop; +`endif + + if (dpii_f_strlen ("")!=0) $stop; + if (dpii_f_strlen ("s")!=1) $stop; + if (dpii_f_strlen ("st")!=2) $stop; + if (dpii_f_strlen ("str")!=3) $stop; + if (dpii_f_strlen ("stri")!=4) $stop; + if (dpii_f_strlen ("string_l")!=8) $stop; + if (dpii_f_strlen ("string_len")!=10) $stop; + string6 = "hello6"; +`ifdef VERILATOR + string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function +`endif + if (dpii_f_strlen (string6) != 6) $stop; + + dpii_f_void(); + dpii_t_void(); + dpii_t_void_context(); + + i_i = 32'h456789ab; + dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop; + + // Check alias + if (oth_f_int1(32'd123) !== ~32'd123) $stop; + if (oth_f_int2(32'd124) !== ~32'd124) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + + always @ (posedge clk) begin + i_b <= ~i_b; + // This once mis-threw a BLKSEQ warning + dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_lib.v b/SVIncCompil/Testcases/Verilator/t_dpi_lib.v new file mode 100644 index 0000000..2968896 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_lib.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2017 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/); + + import "DPI-C" function int dpii_failure(); + import "DPI-C" function void dpii_check(); + + initial begin + dpii_check(); + + if (dpii_failure()!=0) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_logic_bad.v b/SVIncCompil/Testcases/Verilator/t_dpi_logic_bad.v new file mode 100644 index 0000000..44f8648 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_logic_bad.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (); + + // Can't handle time (yet?) + import "DPI-C" dpii_fa_bit = function logic [2:0] oth_f_int1(input time i); + + initial begin + $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_name_bad.v b/SVIncCompil/Testcases/Verilator/t_dpi_name_bad.v new file mode 100644 index 0000000..33de526 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_name_bad.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (); + + // Can't handle logic (yet?) + import "DPI-C" function int \badly.named (int i); + + initial begin + $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_open.v b/SVIncCompil/Testcases/Verilator/t_dpi_open.v new file mode 100644 index 0000000..9690dc8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_open.v
@@ -0,0 +1,150 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2017 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VERILATOR + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) +`else + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +`endif + +module t (/*AUTOARG*/); + + // verilator lint_off UNUSED + reg i_rl_p0_u1 [-2:2]; + reg o_rl_p0_u1 [-2:2]; + reg [1:-1] i_rl_p1_u1 [-2:2]; + reg [1:-1] o_rl_p1_u1 [-2:2]; + reg [1:-1] i_rl_p1_u2 [-2:2] [-3:3]; + reg [1:-1] o_rl_p1_u2 [-2:2] [-3:3]; + reg [1:-1] i_rl_p1_u3 [-2:2] [-3:3] [-4:4]; + reg [1:-1] o_rl_p1_u3 [-2:2] [-3:3] [-4:4]; + + reg i_rb_p0_u1 [2:-2]; + reg o_rb_p0_u1 [2:-2]; + reg [1:-1] i_rb_p1_u1 [2:-2]; + reg [1:-1] o_rb_p1_u1 [2:-2]; + reg [1:-1] i_rb_p1_u2 [2:-2] [3:-3]; + reg [1:-1] o_rb_p1_u2 [2:-2] [3:-3]; + reg [1:-1] i_rb_p1_u3 [2:-2] [3:-3] [4:-4]; + reg [1:-1] o_rb_p1_u3 [2:-2] [3:-3] [4:-4]; + + reg i_rw_p0_u1 [2:-2]; + reg o_rw_p0_u1 [2:-2]; + reg [95:1] i_rw_p1_u1 [2:-2]; + reg [95:1] o_rw_p1_u1 [2:-2]; + reg [95:1] i_rw_p1_u2 [2:-2] [3:-3]; + reg [95:1] o_rw_p1_u2 [2:-2] [3:-3]; + reg [95:1] i_rw_p1_u3 [2:-2] [3:-3] [4:-4]; + reg [95:1] o_rw_p1_u3 [2:-2] [3:-3] [4:-4]; + + bit i_bit [1:0]; + bit o_bit [1:0]; + logic i_logic [1:0]; + logic o_logic [1:0]; + byte i_byte [1:0]; + byte o_byte [1:0]; + int i_int [1:0]; + int o_int [1:0]; + integer i_integer [1:0]; + integer o_integer [1:0]; + // verilator lint_on UNUSED + + import "DPI-C" function int dpii_failure(); + + import "DPI-C" function void dpii_unused(input reg u []); + + // [] on packed arrays is unsupported in VCS & NC, so not supporting this + + import "DPI-C" function void dpii_open_p0_u1(input int c,p,u, input reg i [], output reg o []); + import "DPI-C" function void dpii_open_p1_u1(input int c,p,u, input reg [1:-1] i [], output reg [1:-1] o []); + import "DPI-C" function void dpii_open_p1_u2(input int c,p,u, input reg [1:-1] i [] [], output reg [1:-1] o [] []); + import "DPI-C" function void dpii_open_p1_u3(input int c,p,u, input reg [1:-1] i [] [] [], output reg [1:-1] o [] [] []); + + import "DPI-C" function void dpii_open_pw_u1(input int c,p,u, input reg [95:1] i [], output reg [95:1] o []); + import "DPI-C" function void dpii_open_pw_u2(input int c,p,u, input reg [95:1] i [] [], output reg [95:1] o [] []); + import "DPI-C" function void dpii_open_pw_u3(input int c,p,u, input reg [95:1] i [] [] [], output reg [95:1] o [] [] []); + + import "DPI-C" function void dpii_open_bit(input bit i [], output bit o []); + import "DPI-C" function void dpii_open_logic(input logic i [], output logic o []); + import "DPI-C" function void dpii_open_byte(input byte i [], output byte o []); + import "DPI-C" function void dpii_open_int(input int i [], output int o []); + import "DPI-C" function void dpii_open_integer(input integer i [], output integer o []); + + import "DPI-C" function int dpii_failed(); + + reg [95:0] crc; + + initial begin + crc = 96'h8a10a572_5aef0c8d_d70a4497; + + for (int a=0; a<2; a=a+1) begin + i_bit[a] = crc[0]; + i_logic[a] = crc[0]; + i_byte[a] = crc[7:0]; + i_int[a] = crc[31:0]; + i_integer[a] = crc[31:0]; + crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + end + + dpii_open_bit(i_bit, o_bit); + dpii_open_logic(i_logic, o_logic); + dpii_open_byte(i_byte, o_byte); + dpii_open_int(i_int, o_int); + dpii_open_integer(i_integer, o_integer); + + for (int a=-2; a<=2; a=a+1) begin + i_rl_p0_u1[a] = crc[0]; + i_rb_p0_u1[a] = crc[0]; + i_rw_p0_u1[a] = crc[0]; + i_rl_p1_u1[a] = crc[2:0]; + i_rb_p1_u1[a] = crc[2:0]; + i_rw_p1_u1[a] = crc[94:0]; + for (int b=-3; b<=3; b=b+1) begin + i_rl_p1_u2[a][b] = crc[2:0]; + i_rb_p1_u2[a][b] = crc[2:0]; + i_rw_p1_u2[a][b] = crc[94:0]; + for (int c=-4; c<=4; c=c+1) begin + i_rl_p1_u3[a][b][c] = crc[2:0]; + i_rb_p1_u3[a][b][c] = crc[2:0]; + i_rw_p1_u3[a][b][c] = crc[94:0]; + crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; + end + end + end + + dpii_open_p0_u1(0,0,1, i_rl_p0_u1, o_rl_p0_u1); + dpii_open_p0_u1(1,0,1, i_rb_p0_u1, o_rb_p0_u1); + dpii_open_p0_u1(2,0,1, i_rw_p0_u1, o_rw_p0_u1); + dpii_open_p1_u1(0,1,1, i_rl_p1_u1, o_rl_p1_u1); + dpii_open_p1_u2(0,1,2, i_rl_p1_u2, o_rl_p1_u2); + dpii_open_p1_u3(0,1,3, i_rl_p1_u3, o_rl_p1_u3); + dpii_open_p1_u1(1,1,1, i_rb_p1_u1, o_rb_p1_u1); + dpii_open_p1_u2(1,1,2, i_rb_p1_u2, o_rb_p1_u2); + dpii_open_p1_u3(1,1,3, i_rb_p1_u3, o_rb_p1_u3); + dpii_open_pw_u1(2,1,1, i_rw_p1_u1, o_rw_p1_u1); + dpii_open_pw_u2(2,1,2, i_rw_p1_u2, o_rw_p1_u2); + dpii_open_pw_u3(2,1,3, i_rw_p1_u3, o_rw_p1_u3); + + for (int a=-2; a<=2; a=a+1) begin + for (int b=-3; b<=3; b=b+1) begin + for (int c=-4; c<=4; c=c+1) begin + `checkh(o_rw_p1_u3[a][b][c], ~i_rw_p1_u3[a][b][c]); + end + end + end + + if (dpii_failure()!=0) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_openfirst.v b/SVIncCompil/Testcases/Verilator/t_dpi_openfirst.v new file mode 100644 index 0000000..1fba538 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_openfirst.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2017 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VERILATOR + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) +`else + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +`endif + +module t (/*AUTOARG*/); + + int i_i [2:0]; + int o_i [2:0]; + + import "DPI-C" function int dpii_failure(); + import "DPI-C" function void dpii_open_i(input int i [], output int o []); + + reg [95:0] crc; + + initial begin + crc = 96'h8a10a572_5aef0c8d_d70a4497; + + i_i[0] = crc[31:0]; + i_i[1] = crc[63:32]; + i_i[2] = crc[95:64]; + dpii_open_i(i_i, o_i); + `checkh(o_i[0], ~i_i[0]); + `checkh(o_i[1], ~i_i[1]); + `checkh(o_i[2], ~i_i[2]); + + if (dpii_failure()!=0) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_openreg_bad.v b/SVIncCompil/Testcases/Verilator/t_dpi_openreg_bad.v new file mode 100644 index 0000000..f2b5375 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_openreg_bad.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/ + // Inputs + b + ); + + reg a []; + input b []; + + initial begin + $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_qw.v b/SVIncCompil/Testcases/Verilator/t_dpi_qw.v new file mode 100644 index 0000000..9c0cb4b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_qw.v
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t; + + wire [39:0] out; + sub a(.value(out)); + + import "DPI-C" context function void poke_value(input int i); + + + initial begin + poke_value(32'hdeadbeef); + if (out !== 40'hdeadbeef) begin + $display("[%0t] %%Error: t_dpi_qw: failed", $time); + $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module sub(value); + parameter WIDTH = 40; + + output [WIDTH-1:0] value; + + reg [WIDTH-1:0] value; + + task set_value(input bit [WIDTH-1:0] v); + value = v; + endtask + + export "DPI-C" task set_value; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_shortcircuit.v b/SVIncCompil/Testcases/Verilator/t_dpi_shortcircuit.v new file mode 100644 index 0000000..c2ff2ac --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_shortcircuit.v
@@ -0,0 +1,213 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VCS + `define NO_SHORTREAL +`endif +`ifdef NC + `define NO_SHORTREAL +`endif +`ifdef VERILATOR // Unsupported + `define NO_SHORTREAL +`endif + +module t (/*AUTOARG*/); + + // Note these are NOT pure. + import "DPI-C" function int dpii_clear (); + import "DPI-C" function int dpii_count (input int ctr); + import "DPI-C" function bit dpii_inc0 (input int ctr); + import "DPI-C" function bit dpii_inc1 (input int ctr); + import "DPI-C" function bit dpii_incx (input int ctr, input bit value); + + integer i; + integer j; + bit b; + integer errors; + + task check1(integer line, bit got, bit ex); + if (got != ex) begin + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; + end + endtask + task check(integer line, int got, int ex); + if (got != ex) begin + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; + end + endtask + + // Test loop + initial begin + // Spec says && || -> and ?: short circuit, no others do. + // Check both constant & non constants. + dpii_clear(); + check1(`__LINE__, (1'b0 && dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 && dpii_inc0(1)), 1'b0); + check1(`__LINE__, (dpii_inc0(2) && dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) && dpii_inc0(5)), 1'b0); + check1(`__LINE__, (dpii_inc0(6) && dpii_inc1(7)), 1'b0); + check1(`__LINE__, (!(dpii_inc1(8) && dpii_inc1(9))), 1'b0); + check (`__LINE__, dpii_count(0), 0); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 0); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 0); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 & dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 & dpii_inc0(1)), 1'b0); + check1(`__LINE__, (dpii_inc0(2) & dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) & dpii_inc0(5)), 1'b0); + check1(`__LINE__, (dpii_inc0(6) & dpii_inc1(7)), 1'b0); + check1(`__LINE__, (!(dpii_inc1(8) & dpii_inc1(9))), 1'b0); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 || dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 || dpii_inc0(1)), 1'b1); + check1(`__LINE__, (dpii_inc0(2) || dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) || dpii_inc0(5)), 1'b1); + check1(`__LINE__, (dpii_inc0(6) || dpii_inc1(7)), 1'b1); + check1(`__LINE__, (!(dpii_inc1(8) || dpii_inc1(9))), 1'b0); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 0); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 0); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 0); + // + dpii_clear(); + check1(`__LINE__, (1'b0 | dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 | dpii_inc0(1)), 1'b1); + check1(`__LINE__, (dpii_inc0(2) | dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) | dpii_inc0(5)), 1'b1); + check1(`__LINE__, (dpii_inc0(6) | dpii_inc1(7)), 1'b1); + check1(`__LINE__, (!(dpii_inc1(8) | dpii_inc1(9))), 1'b0); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 -> dpii_inc0(0)), 1'b1); + check1(`__LINE__, (1'b1 -> dpii_inc0(1)), 1'b0); + check1(`__LINE__, (dpii_inc0(2) -> dpii_inc0(3)), 1'b1); + check1(`__LINE__, (dpii_inc1(4) -> dpii_inc0(5)), 1'b0); + check1(`__LINE__, (dpii_inc0(6) -> dpii_inc1(7)), 1'b1); + check1(`__LINE__, (!(dpii_inc1(8) -> dpii_inc1(9))), 1'b0); + check (`__LINE__, dpii_count(0), 0); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 0); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 0); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 ? dpii_inc0(0) : dpii_inc0(1)), 1'b0); + check1(`__LINE__, (1'b1 ? dpii_inc0(2) : dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc0(4) ? dpii_inc0(5) : dpii_inc0(6)), 1'b0); + check1(`__LINE__, (dpii_inc1(7) ? dpii_inc0(8) : dpii_inc0(9)), 1'b0); + check (`__LINE__, dpii_count(0), 0); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 0); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 0); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 0); + // + dpii_clear(); + check1(`__LINE__, (1'b0 * dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 * dpii_inc0(1)), 1'b0); + check1(`__LINE__, (dpii_inc0(2) * dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) * dpii_inc0(5)), 1'b0); + check1(`__LINE__, (dpii_inc0(6) * dpii_inc1(7)), 1'b0); + check1(`__LINE__, (!(dpii_inc1(8) * dpii_inc1(9))), 1'b0); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + dpii_clear(); + check1(`__LINE__, (1'b0 + dpii_inc0(0)), 1'b0); + check1(`__LINE__, (1'b1 + dpii_inc0(1)), 1'b1); + check1(`__LINE__, (dpii_inc0(2) + dpii_inc0(3)), 1'b0); + check1(`__LINE__, (dpii_inc1(4) + dpii_inc0(5)), 1'b1); + check1(`__LINE__, (dpii_inc0(6) + dpii_inc1(7)), 1'b1); + check1(`__LINE__, (dpii_inc1(8) + dpii_inc1(9)), 1'b0); + check (`__LINE__, dpii_count(0), 1); + check (`__LINE__, dpii_count(1), 1); + check (`__LINE__, dpii_count(2), 1); + check (`__LINE__, dpii_count(3), 1); + check (`__LINE__, dpii_count(4), 1); + check (`__LINE__, dpii_count(5), 1); + check (`__LINE__, dpii_count(6), 1); + check (`__LINE__, dpii_count(7), 1); + check (`__LINE__, dpii_count(8), 1); + check (`__LINE__, dpii_count(9), 1); + // + // Something a lot more complicated + dpii_clear(); + for (i=0; i<64; i++) begin + b = ( ((dpii_incx(0,i[0]) + && (dpii_incx(1,i[1]) + || dpii_incx(2,i[2]) + | dpii_incx(3,i[3]))) // | not || + || dpii_incx(4,i[4])) + -> dpii_incx(5,i[5])); + end + check (`__LINE__, dpii_count(0), 64); + check (`__LINE__, dpii_count(1), 32); + check (`__LINE__, dpii_count(2), 16); + check (`__LINE__, dpii_count(3), 16); + check (`__LINE__, dpii_count(4), 36); + check (`__LINE__, dpii_count(5), 46); + + if (|errors) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_shortcircuit2.v b/SVIncCompil/Testcases/Verilator/t_dpi_shortcircuit2.v new file mode 100644 index 0000000..81db353 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_shortcircuit2.v
@@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VCS + `define NO_SHORTREAL +`endif +`ifdef NC + `define NO_SHORTREAL +`endif +`ifdef VERILATOR // Unsupported + `define NO_SHORTREAL +`endif + +module t (/*AUTOARG*/); + + // Note these are NOT pure. + import "DPI-C" function int dpii_clear (); + import "DPI-C" function int dpii_count (input int ctr); + import "DPI-C" function bit dpii_inc0 (input int ctr); + import "DPI-C" function bit dpii_inc1 (input int ctr); + import "DPI-C" function bit dpii_incx (input int ctr, input bit value); + + integer i; + integer j; + integer k; + bit b; + integer errors; + + task check1(integer line, bit got, bit ex); + if (got != ex) begin + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; + end + endtask + task check(integer line, int got, int ex); + if (got != ex) begin + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; + end + endtask + + // Test loop + initial begin + // bug963 + // verilator lint_off IGNOREDRETURN + dpii_clear(); + // verilator lint_on IGNOREDRETURN + j = 0; + for (i=0; i<64; i++) begin + if (i[0]) + j = 0; + else + j = {31'b0, dpii_inc1(0)}; + k = k + j; + end + $write("%x\n",k); + check (`__LINE__, dpii_count(0), 32); + + if (|errors) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_string.v b/SVIncCompil/Testcases/Verilator/t_dpi_string.v new file mode 100644 index 0000000..c138754 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_string.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (); + + import "DPI-C" function int dpii_string(input string DSM_NAME); + + generate + begin : DSM + string SOME_STRING; + end + endgenerate + + initial begin + $sformat(DSM.SOME_STRING, "%m"); + if (dpii_string(DSM.SOME_STRING) != 5) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_sys.v b/SVIncCompil/Testcases/Verilator/t_dpi_sys.v new file mode 100644 index 0000000..173d896 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_sys.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +// Global is the most likely usage scenario +import "DPI-C" dpii_sys_task = function void \$dpii_sys (int i); +import "DPI-C" dpii_sys_func = function int \$dpii_func (int i); + +module t (); + +`ifndef verilator + `error "Only Verilator supports PLI-ish DPI calls." +`endif + + initial begin + $dpii_sys(1); + if ($dpii_func(2) != 3) $stop; + $dpii_sys(10); + if ($dpii_func(2) != 12) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_threads.v b/SVIncCompil/Testcases/Verilator/t_dpi_threads.v new file mode 100644 index 0000000..5f982b0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_threads.v
@@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2018 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +import "DPI-C" dpii_sys_task = function void \$dpii_sys (); +import "DPI-C" dpii_failure = function int \$dpii_failure (); + +module t (clk); + input clk; + integer cyc; + integer failure; + + initial cyc = 0; + +`ifndef verilator + `error "Only Verilator supports PLI-ish DPI calls." +`endif + + always @ (posedge clk) begin + if (cyc == 2) begin + failure = $dpii_failure(); + $write("* failure = %0d\n", failure); + if (failure > 0) begin + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + cyc <= cyc + 1; + end + + // The purpose of this test is to confirm that the DPI-call serialization + // code in V3Partition does ensure that these DPI calls do not run + // concurrently. + // + // Alternatively, the test may be run with "--threads-dpi all" in which case + // it should confirm that the calls do run concurrently and do detect a + // collision (they should, if the test is set up right.) This is + // t_dpi_threads_collide.pl. + // + // Q) Is it a risk that the partitioner will merge or serialize these always + // blocks, just by luck, even if the DPI-call serialization code fails? + // + // A) Yes, that's why t_dpi_threads_collide.pl also passes + // --no-threads-do-coaren to disable MTask coarsening. This ensures that + // the MTask graph at the end of FixDataHazards (where we resolve DPI + // hazards) is basically the final MTasks graph, and that data hazards + // which persist beyond FixDataHazards should persist in the final + // generated C code. + + always @ (posedge clk) begin + $dpii_sys(); + end + + always @ (posedge clk) begin + $dpii_sys(); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_vams.v b/SVIncCompil/Testcases/Verilator/t_dpi_vams.v new file mode 100644 index 0000000..09d4580 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_vams.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +//`begin_keywords "VAMS-2.3" +`begin_keywords "1800+VAMS" + +module t (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input in; + wreal in; + output out; + wreal out; + + import "DPI-C" context function void dpii_call(input real in, output real out); + + initial begin + dpii_call(in,out); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_dpi_var.v b/SVIncCompil/Testcases/Verilator/t_dpi_var.v new file mode 100644 index 0000000..8c42c42 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_dpi_var.v
@@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + wire monclk = ~clk; + + int in; + int fr_a; + int fr_b; + int fr_chk; + sub sub (.*); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk); +`endif + cyc <= cyc + 1; + in <= {in[30:0], in[31]^in[2]^in[0]}; + if (cyc==0) begin + // Setup + in <= 32'hd70a4497; + end + else if (cyc<3) begin + end + else if (cyc<10) begin + if (fr_chk != fr_a) $stop; + if (fr_chk != fr_b) $stop; + end + else if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + + always @(posedge t.monclk) begin + mon_eval(); + end + +endmodule + +import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ ); +import "DPI-C" context function void mon_register_b(string name, int isOut); +import "DPI-C" context function void mon_register_done(); +import "DPI-C" context function void mon_eval(); + +module sub (/*AUTOARG*/ + // Outputs + fr_a, fr_b, fr_chk, + // Inputs + in + ); + +`systemc_imp_header + void mon_class_name(const char* namep); + void mon_register_a(const char* namep, void* sigp, bool isOut); +`verilog + + input int in /*verilator public_flat_rd*/; + output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/; + output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/; + output int fr_chk; + + always @* fr_chk = in + 1; + + initial begin + // Test the naming + $c("mon_class_name(name());"); + mon_scope_name("%m"); + // Scheme A - pass pointer directly + $c("mon_register_a(\"in\",&",in,",false);"); + $c("mon_register_a(\"fr_a\",&",fr_a,",true);"); + // Scheme B - use VPIish callbacks to see what signals exist + mon_register_b("in", 0); + mon_register_b("fr_b", 1); + mon_register_done(); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_embed1.v b/SVIncCompil/Testcases/Verilator/t_embed1.v new file mode 100644 index 0000000..d84751f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_embed1.v
@@ -0,0 +1,109 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire bit_in = crc[0]; + wire [30:0] vec_in = crc[31:1]; + wire [123:0] wide_in = {crc[59:0],~crc[63:0]}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire exp_bit_out; // From reference of t_embed1_child.v + wire exp_did_init_out; // From reference of t_embed1_child.v + wire [30:0] exp_vec_out; // From reference of t_embed1_child.v + wire [123:0] exp_wide_out; // From reference of t_embed1_child.v + wire got_bit_out; // From test of t_embed1_wrap.v + wire got_did_init_out; // From test of t_embed1_wrap.v + wire [30:0] got_vec_out; // From test of t_embed1_wrap.v + wire [123:0] got_wide_out; // From test of t_embed1_wrap.v + // End of automatics + + // A non-embedded master + + /* t_embed1_child AUTO_TEMPLATE( + .\(.*_out\) (exp_\1[]), + .is_ref (1'b1)); + */ + t_embed1_child reference + (/*AUTOINST*/ + // Outputs + .bit_out (exp_bit_out), // Templated + .vec_out (exp_vec_out[30:0]), // Templated + .wide_out (exp_wide_out[123:0]), // Templated + .did_init_out (exp_did_init_out), // Templated + // Inputs + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b1)); // Templated + + // The embeded comparison + + /* t_embed1_wrap AUTO_TEMPLATE( + .\(.*_out\) (got_\1[]), + .is_ref (1'b0)); + */ + + t_embed1_wrap test + (/*AUTOINST*/ + // Outputs + .bit_out (got_bit_out), // Templated + .vec_out (got_vec_out[30:0]), // Templated + .wide_out (got_wide_out[123:0]), // Templated + .did_init_out (got_did_init_out), // Templated + // Inputs + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b0)); // Templated + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, + got_wide_out !== exp_wide_out, + got_vec_out !== exp_vec_out, + got_bit_out !== exp_bit_out, + got_did_init_out !== exp_did_init_out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result, + got_vec_out, exp_vec_out); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + end + else if (cyc<90) begin + if (result != 64'h0) begin + $display("Bit mismatch, result=%x\n", result); + $stop; + end + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + //Child prints this: $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_embed1_child.v b/SVIncCompil/Testcases/Verilator/t_embed1_child.v new file mode 100644 index 0000000..84f118a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_embed1_child.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t_embed1_child (/*AUTOARG*/ + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); + + input clk; + input bit_in; + output bit_out; + input [30:0] vec_in; + output [30:0] vec_out; + input [123:0] wide_in; + output [123:0] wide_out; + output did_init_out; + + input is_ref; + + reg did_init; initial did_init = 0; + initial begin + did_init = 1; + end + + reg did_final; initial did_final = 0; + final begin + did_final = 1; + if (!is_ref) $write("*-* All Finished *-*\n"); + //$finish is in parent + end + + // Note async use! + wire bit_out = bit_in; + wire did_init_out = did_init; + + always @ (posedge clk) begin + vec_out <= vec_in; + wide_out <= wide_in; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_embed1_wrap.v b/SVIncCompil/Testcases/Verilator/t_embed1_wrap.v new file mode 100644 index 0000000..9afca7b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_embed1_wrap.v
@@ -0,0 +1,90 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t_embed1_wrap (/*AUTOARG*/ + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); + + /*AUTOINOUTMODULE("t_embed1_child")*/ + // Beginning of automatic in/out/inouts (from specific module) + output bit_out; + output [30:0] vec_out; + output [123:0] wide_out; + output did_init_out; + input clk; + input bit_in; + input [30:0] vec_in; + input [123:0] wide_in; + input is_ref; + // End of automatics + +`ifdef verilator + // Import $t_embed_child__initial etc as a DPI function +`endif + + //TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this + import "DPI-C" context function void t_embed_child_initial(); + import "DPI-C" context function void t_embed_child_final(); + import "DPI-C" context function void t_embed_child_eval(); + import "DPI-C" context function void t_embed_child_io_eval + ( + //TODO we support bit, but not logic + input bit clk, + input bit bit_in, + input bit [30:0] vec_in, + input bit [123:0] wide_in, + input bit is_ref, + output bit bit_out, + output bit [30:0] vec_out, + output bit [123:0] wide_out, + output bit did_init_out); + + initial begin + // Load all values + t_embed_child_initial(); + end + + // Only if system verilog, and if a "final" block in the code + final begin + t_embed_child_final(); + end + + bit _temp_bit_out; + bit _temp_did_init_out; + bit [30:0] _temp_vec_out; + bit [123:0] _temp_wide_out; + always @* begin + t_embed_child_io_eval( + clk, + bit_in, + vec_in, + wide_in, + is_ref, + _temp_bit_out, + _temp_vec_out, + _temp_wide_out, + _temp_did_init_out + ); + // TODO might eliminate these temporaries + bit_out = _temp_bit_out; + did_init_out = _temp_did_init_out; + end + + + // Send all variables every cycle, + // or have a sensitivity routine for each? + // How to make sure we call eval at end of variable changes? + // #0 (though not verilator compatible!) + + // TODO for now, we know what changes when + always @ (posedge clk) begin + vec_out <= _temp_vec_out; + wide_out <= _temp_wide_out; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_emit_constw.v b/SVIncCompil/Testcases/Verilator/t_emit_constw.v new file mode 100644 index 0000000..40757de --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_emit_constw.v
@@ -0,0 +1,157 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +`define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad}; + + bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d}; + + bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06}; + + bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199}; + + bit [9*32-1:0] w9 = {32'hca800ac1, + 32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621}; + + bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32, + 32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8}; + + bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e, + 32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784}; + + bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e, + 32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302}; + + bit [17*32-1:0] w17 = {32'hf1e322ac, + 32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23, + 32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1}; + + function [7:0] bytehash (input [32*32-1:0] data); + integer i; + bytehash = 0; + for (i=0; i<32*32; ++i) begin + bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8]; + end + return bytehash; + endfunction + + // Aggregate outputs into a single result vector + // verilator lint_off WIDTH + wire [63:0] result = (bytehash(w4) + ^ bytehash(w8m) + ^ bytehash(w8) + ^ bytehash(w8p) + ^ bytehash(w9) + ^ bytehash(w16m) + ^ bytehash(w16) + ^ bytehash(w16p) + ^ bytehash(w17)); + // verilator lint_on WIDTH + +`define EXPECTED_SUM 64'hb6fdb64085fc17f5 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + // verilator lint_off SELRANGE + `checkhw(w4,3,32'h7c709753); + `checkhw(w4,2,32'hbc8f6059); + `checkhw(w4,1,32'h3b0db464); + `checkhw(w4,0,32'h721a8fad); + `checkhw(w8m,7,31'h7146e1bf); + `checkhw(w8m,6,32'ha8549e42); + `checkhw(w8m,5,32'hca6960bd); + `checkhw(w8m,4,32'h191b7f9b); + `checkhw(w8m,3,32'h93d79866); + `checkhw(w8m,2,32'hf4489e2b); + `checkhw(w8m,1,32'h8e9a3236); + `checkhw(w8m,0,32'h1d2a2d1d); + `checkhw(w8,7,32'hc211addc); + `checkhw(w8,6,32'he5d4a057); + `checkhw(w8,5,32'h5cbf88fe); + `checkhw(w8,4,32'h42cf42e2); + `checkhw(w8,3,32'heb584263); + `checkhw(w8,2,32'ha585f118); + `checkhw(w8,1,32'h231531c8); + `checkhw(w8,0,32'hc73f7b06); + `checkhw(w8p,8,1'b1); + `checkhw(w8p,7,32'h096aa54b); + `checkhw(w8p,6,32'h48aae18e); + `checkhw(w8p,5,32'hf9502cea); + `checkhw(w8p,4,32'h518c8b61); + `checkhw(w8p,3,32'h9e8641a2); + `checkhw(w8p,2,32'h0dc0249c); + `checkhw(w8p,1,32'hd421a87a); + `checkhw(w8p,0,32'hb8ee9199); + `checkhw(w9,8,32'hca800ac1); + `checkhw(w9,7,32'h0de4823a); + `checkhw(w9,6,32'ha51663ac); + `checkhw(w9,5,32'h96351446); + `checkhw(w9,4,32'h6b0bbcd5); + `checkhw(w9,3,32'h4a64b530); + `checkhw(w9,2,32'h4967d59a); + `checkhw(w9,1,32'hfcc17292); + `checkhw(w9,0,32'h57926621); + `checkhw(w16m,15,31'h77ad72c7); + `checkhw(w16m,14,32'h73aa9cbb); + `checkhw(w16m,13,32'h7ecf026d); + `checkhw(w16m,12,32'h985a3ed2); + `checkhw(w16m,11,32'hfe961c1d); + `checkhw(w16m,10,32'h7a01df72); + `checkhw(w16m,9,32'h79e13d71); + `checkhw(w16m,8,32'hb69e2e32); + `checkhw(w16m,7,32'h09fcbc45); + `checkhw(w16m,6,32'hcfd738c1); + `checkhw(w16m,5,32'hc197ac7c); + `checkhw(w16m,4,32'hc316d727); + `checkhw(w16m,3,32'h903034e4); + `checkhw(w16m,2,32'h92a047d1); + `checkhw(w16m,1,32'h6a5357af); + `checkhw(w16m,0,32'ha82ce9c8); + // verilator lint_on SELRANGE + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + w4 = w4 >>> 1; + w8m = w8m >>> 1; + w8 = w8 >>> 1; + w8p = w8p >>> 1; + w9 = w9 >>> 1; + w16m = w16m >>> 1; + w16 = w16 >>> 1; + w16p = w16p >>> 1; + w17 = w17 >>> 1; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum.v b/SVIncCompil/Testcases/Verilator/t_enum.v new file mode 100644 index 0000000..2724716 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum.v
@@ -0,0 +1,81 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +typedef enum logic [4:0] + { + BIT0 = 5'd0, + BIT1 = 5'd1, + BIT2 = 5'd2 + } three_t; + +module t (/*AUTOARG*/); + + localparam FIVE = 5; + + enum { e0, + e1, + e3=3, + e5=FIVE, + e10_[2] = 10, + e12, + e20_[5:7] = 25, + e20_z, + e30_[7:5] = 30, + e30_z + } EN; + + enum { + z5 = e5 + } ZN; + + typedef enum [2:0] { ONES=~0 } three_t; + three_t three = ONES; + + var logic [ONES:0] sized_based_on_enum; + + var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2}, + QPR={2'b0,2'h3 }, QACK, QRSP } inv; + + initial begin + if (e0 !== 0) $stop; + if (e1 !== 1) $stop; + if (e3 !== 3) $stop; + if (e5 !== 5) $stop; + if (e10_0 !== 10) $stop; + if (e10_1 !== 11) $stop; + if (e12 !== 12) $stop; + if (e20_5 !== 25) $stop; + if (e20_6 !== 26) $stop; + if (e20_7 !== 27) $stop; + if (e20_z !== 28) $stop; + if (e30_7 !== 30) $stop; + if (e30_6 !== 31) $stop; + if (e30_5 !== 32) $stop; + if (e30_z !== 33) $stop; + + if (z5 !== 5) $stop; + + if (three != 3'b111) $stop; + + if ($bits(sized_based_on_enum) != 8) $stop; + if ($bits(three_t) != 3) $stop; + + if (FIVE[BIT0] != 1'b1) $stop; + if (FIVE[BIT1] != 1'b0) $stop; + if (FIVE[BIT2] != 1'b1) $stop; + + if (QINVALID != 15) $stop; + if (QSEND != 0) $stop; + if (QOP != 1) $stop; + if (QCL != 2) $stop; + if (QPR != 3) $stop; + if (QACK != 4) $stop; + if (QRSP != 5) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_bad_hide.v b/SVIncCompil/Testcases/Verilator/t_enum_bad_hide.v new file mode 100644 index 0000000..eafe4d0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_bad_hide.v
@@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +typedef enum { HIDE_VALUE = 0 } hide_enum_t; + +module t; + + typedef enum { HIDE_VALUE = 0 } hide_enum_t; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_func.v b/SVIncCompil/Testcases/Verilator/t_enum_func.v new file mode 100644 index 0000000..1251a1b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_func.v
@@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +typedef enum { EN_ZERO, + EN_ONE + } En_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Insure that we can declare a type with a function declaration + function enum integer { + EF_TRUE = 1, + EF_FALSE = 0 } + f_enum_inv ( input a); + f_enum_inv = a ? EF_FALSE : EF_TRUE; + endfunction + initial begin + if (f_enum_inv(1) != 0) $stop; + if (f_enum_inv(0) != 1) $stop; + end + + En_t a, z; + + sub sub (/*AUTOINST*/ + // Outputs + .z (z), + // Inputs + .a (a)); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= EN_ZERO; + end + if (cyc==2) begin + a <= EN_ONE; + if (z != EN_ONE) $stop; + end + if (cyc==3) begin + if (z != EN_ZERO) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module sub (input En_t a, output En_t z); + always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE; +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_int.v b/SVIncCompil/Testcases/Verilator/t_enum_int.v new file mode 100644 index 0000000..042a004 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_int.v
@@ -0,0 +1,81 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + enum integer { + + EP_State_IDLE , + EP_State_CMDSHIFT0 , + EP_State_CMDSHIFT13 , + EP_State_CMDSHIFT14 , + EP_State_CMDSHIFT15 , + EP_State_CMDSHIFT16 , + EP_State_DWAIT , + EP_State_DSHIFT0 , + EP_State_DSHIFT1 , + EP_State_DSHIFT15 } m_state_xr, m_state2_xr; + + // Beginning of automatic ASCII enum decoding + reg [79:0] m_stateAscii_xr; // Decode of m_state_xr + always @(m_state_xr) begin + case ({m_state_xr}) + EP_State_IDLE: m_stateAscii_xr = "idle "; + EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; + EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; + EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; + EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; + EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; + EP_State_DWAIT: m_stateAscii_xr = "dwait "; + EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; + EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; + EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; + default: m_stateAscii_xr = "%Error "; + endcase + end + // End of automatics + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc==1) begin + m_state_xr <= EP_State_IDLE; + m_state2_xr <= EP_State_IDLE; + end + if (cyc==2) begin + if (m_stateAscii_xr != "idle ") $stop; + m_state_xr <= EP_State_CMDSHIFT13; + if (m_state2_xr != EP_State_IDLE) $stop; + m_state2_xr <= EP_State_CMDSHIFT13; + end + if (cyc==3) begin + if (m_stateAscii_xr != "cmdshift13") $stop; + m_state_xr <= EP_State_CMDSHIFT16; + if (m_state2_xr != EP_State_CMDSHIFT13) $stop; + m_state2_xr <= EP_State_CMDSHIFT16; + end + if (cyc==4) begin + if (m_stateAscii_xr != "cmdshift16") $stop; + m_state_xr <= EP_State_DWAIT; + if (m_state2_xr != EP_State_CMDSHIFT16) $stop; + m_state2_xr <= EP_State_DWAIT; + end + if (cyc==9) begin + if (m_stateAscii_xr != "dwait ") $stop; + if (m_state2_xr != EP_State_DWAIT) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_large_methods.v b/SVIncCompil/Testcases/Verilator/t_enum_large_methods.v new file mode 100644 index 0000000..0e338ca --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_large_methods.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + typedef enum { + E01 = 'h1, + ELARGE = 'hf00d + } my_t; + + integer cyc=0; + my_t e; + + string all; + + // Check runtime + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + e <= E01; + end + else if (cyc==1) begin + `checks(e.name, "E01"); + `checkh(e.next, ELARGE); + e <= ELARGE; + end + else if (cyc==3) begin + `checks(e.name, "ELARGE"); + `checkh(e.next, E01); + `checkh(e.prev, E01); + e <= E01; + end + else if (cyc==20) begin + e <= 'h11; // Unknown + end + else if (cyc==20) begin + `checks(e.name, ""); // Unknown + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_name2.v b/SVIncCompil/Testcases/Verilator/t_enum_name2.v new file mode 100644 index 0000000..6e420bd --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_name2.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jonathon Donaldson. + +package our_pkg; + typedef enum logic [8-1:0] { + ADC_IN2IN = 8'h99, + ADC_IMMED = 8'h88, + ADC_INDIR = 8'h86, + ADC_INIDX = 8'h97 + } T_Opcode; +endpackage : our_pkg + +module t (); + our our (); +endmodule + +module our + import our_pkg::*; + (); + + T_Opcode IR = ADC_IN2IN; + + initial begin + $write ("%s (%t)\n", IR.name, $realtime); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_name3.v b/SVIncCompil/Testcases/Verilator/t_enum_name3.v new file mode 100644 index 0000000..d7613f2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_name3.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jonathon Donaldson. + +// bug855 +module our; + + typedef enum logic {n,N} T_Flg_N; + + typedef struct packed { + T_Flg_N N; + } T_PS_Reg; + + T_PS_Reg PS = 1'b1; + + initial begin + $write ("P:%s\n", PS.N.name); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_overlap_bad.v b/SVIncCompil/Testcases/Verilator/t_enum_overlap_bad.v new file mode 100644 index 0000000..00c84f7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_overlap_bad.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/); + + enum { e0, + e1, + e2, + e1b=1 + } BAD1; + + initial begin + $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_public.v b/SVIncCompil/Testcases/Verilator/t_enum_public.v new file mode 100644 index 0000000..d26a77b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_public.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +package p3; + typedef enum logic [2:0] { + ZERO = 3'b0, + ONE = 3'b1 } e3_t /*verilator public*/; +endpackage + +package p62; + typedef enum logic [62:0] { + ZERO = '0, + ALLONE = '1 } e62_t /*verilator public*/; +endpackage + +module t (/*AUTOARG*/); + + enum integer { + EI_A, + EI_B, + EI_C + } m_state; + + initial begin + m_state = EI_A; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_size.v b/SVIncCompil/Testcases/Verilator/t_enum_size.v new file mode 100644 index 0000000..5fd56ca --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_size.v
@@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // verilator lint_off WIDTH + typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs; + + typedef enum integer {UP=0, UW=1'b1} UNSIZED; + // verilator lint_on WIDTH + + localparam LEN = 3; + localparam COL = 4; + + localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P) + ,LEN'(S), LEN'(E), LEN'(W), LEN'(P) + ,LEN'(S), LEN'(N), LEN'(W), LEN'(P) + ,LEN'(S), LEN'(N), LEN'(E), LEN'(P) + ,LEN'(S), LEN'(N), LEN'(E), LEN'(W)}; + + bit [59:0] SE2 = {N, E, W, P + ,S, E, W, P + ,S, N, W, P + ,S, N, E, P + ,S, N, E, W}; + + initial begin + if (SEQ != 60'o32104210431043204321) $stop; + if (SE2 != 60'o32104210431043204321) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_type_methods.v b/SVIncCompil/Testcases/Verilator/t_enum_type_methods.v new file mode 100644 index 0000000..2713952 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_type_methods.v
@@ -0,0 +1,96 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + typedef enum [3:0] { + E01 = 1, + E03 = 3, + E04 = 4 + } my_t; + + integer cyc=0; + my_t e; + + int arrayfits [e.num]; // Check can use as constant + + string all; + + // Check constification + initial begin + e = E03; + `checkh(e.first, E01); + `checkh(e.last, E04); + `checkh(e.last(), E04); + `checkh(e.next, E04); + `checkh(e.next(), E04); + `checkh(e.next(1), E04); + //Unsup: `checkh(e.next(2), E01); + `checkh(e.prev, E01); + `checkh(e.prev(1), E01); + //Unsup: `checkh(e.prev(2), E04); + `checkh(e.num, 3); + `checks(e.name, "E03"); + // + all = ""; + for (my_t e = e.first; e != e.last; e = e.next) begin + all = {all, e.name}; + end + e = e.last; + all = {all, e.name}; + `checks(all, "E01E03E04"); + end + + // Check runtime + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + e <= E01; + end + else if (cyc==1) begin + `checks(e.name, "E01"); + `checkh(e.next, E03); + `checkh(e.next(1), E03); + //Unsup: `checkh(e.next(2), E04); + `checkh(e.prev, E04); + `checkh(e.prev(1), E04); + //Unsup: `checkh(e.prev(2), E03); + e <= E03; + end + else if (cyc==2) begin + `checks(e.name, "E03"); + `checkh(e.next, E04); + `checkh(e.next(1), E04); + //Unsup: `checkh(e.next(2), E01); + `checkh(e.prev, E01); + `checkh(e.prev(1), E01); + //Unsup: `checkh(e.prev(2), E04); + e <= E04; + end + else if (cyc==3) begin + `checks(e.name, "E04"); + `checkh(e.next, E01); + `checkh(e.next(1), E01); + //Unsup: `checkh(e.next(2), E03); + `checkh(e.prev, E03); + `checkh(e.prev(1), E03); + //Unsup: `checkh(e.prev(2), E01); + e <= E01; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enum_type_pins.v b/SVIncCompil/Testcases/Verilator/t_enum_type_pins.v new file mode 100644 index 0000000..e701df4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enum_type_pins.v
@@ -0,0 +1,104 @@ +// DESCRIPTION: Verilator: System Verilog test of enumerated type methods +// +// This code exercises the various enumeration methods +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty. + +// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. + + + +// **** Pin Identifiers **** +typedef enum int +{ + PINID_A0 = 32'd0, // MUST BE ZERO! + // - Standard Ports - + PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7, + PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7, + PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7, + PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7, + PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7, + PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7, + PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7, + PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7, +// PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1 + PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7, + PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7, + PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7, + PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7, + PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7, +// PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0 + PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7, + PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7, + PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7, + // - AUX Port (Custom) - + PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7, + // - PDI Port - + PINID_D2W_DAT, PINID_D2W_CLK, + // - Power Pins - + PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3, + PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3, + // - Maximum number of pins - + PINID_MAX + } t_pinid; + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire a = clk; + wire b = 1'b0; + reg c; + + test test_i (/*AUTOINST*/ + // Inputs + .clk (clk)); + + // This is a compile time only test. Immediately finish + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + + +module test (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Use the enumeration size to initialize a dynamic array + t_pinid e; + int myarray1 [] = new [e.num]; + + always @(posedge clk) begin + +`ifdef TEST_VERBOSE + $write ("Enumeration has %d members\n", e.num); +`endif + + e = e.first; + + forever begin + myarray1[e] <= e.prev; + +`ifdef TEST_VERBOSE + $write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]); +`endif + + if (e == e.last) begin + break; + end + else begin + e = e.next; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_enumeration.v b/SVIncCompil/Testcases/Verilator/t_enumeration.v new file mode 100644 index 0000000..49bb9b8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_enumeration.v
@@ -0,0 +1,276 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cnt = 0; + integer mod = 0; + + // event counter + always @ (posedge clk) + if (cnt==20) begin + cnt <= 0; + mod <= mod + 1; + end else begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if (mod==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // anonymous type variable declaration + enum logic [2:0] {red=1, orange, yellow, green, blue, indigo, violet} rainbow7; + + // named type + typedef enum logic {OFF, ON} t_switch; + t_switch switch; + + // numbering examples + enum integer {father, mother, son[2], daughter, gerbil, dog[3]=10, cat[3:5]=20, car[3:1]=30} family; + + // test of raibow7 type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.first(); + // check number + if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end + if (rainbow7 !== 3'bxxx ) begin $display("%b", rainbow7 ); $stop(); end + end + else if (cnt== 1) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 2) begin + if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 3) begin + if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 4) begin + if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 5) begin + if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 6) begin + if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 7) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + else if (cnt== 8) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.next(); + end + end else if (mod==1) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.last(); + // check number + if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end + end + else if (cnt== 1) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 2) begin + if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 3) begin + if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 4) begin + if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 5) begin + if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 6) begin + if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 7) begin + if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + else if (cnt== 8) begin + if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end + if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end + rainbow7 <= rainbow7.prev(); + end + end + + // test of t_switch type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + switch <= switch.first(); + // check number + if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end + if (switch !== 1'bx) begin $display("%b", switch ); $stop(); end + end + else if (cnt== 1) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + else if (cnt== 2) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + else if (cnt== 3) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.next(); + end + end else if (mod==1) begin + // write value to array + if (cnt== 0) begin + rainbow7 <= rainbow7.last(); + // check number + if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end + end + else if (cnt== 1) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + else if (cnt== 2) begin + if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end + if (switch !== OFF ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + else if (cnt== 3) begin + if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end + if (switch !== ON ) begin $display("%b", switch ); $stop(); end + switch <= switch.prev(); + end + end + + // test of raibow7 type + always @ (posedge clk) + if (mod==0) begin + // write value to array + if (cnt== 0) begin + family <= family.first(); + // check number + if (family.num() !== 15 ) begin $display("%d", family.num() ); $stop(); end + if (family !== 32'dx ) begin $display("%b", family ); $stop(); end + end + else if (cnt== 1) begin + if (family !== 0 ) begin $display("%b", family ); $stop(); end + if (family !== father ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 2) begin + if (family !== 1 ) begin $display("%b", family ); $stop(); end + if (family !== mother ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 3) begin + if (family !== 2 ) begin $display("%b", family ); $stop(); end + if (family !== son0 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 4) begin + if (family !== 3 ) begin $display("%b", family ); $stop(); end + if (family !== son1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 5) begin + if (family !== 4 ) begin $display("%b", family ); $stop(); end + if (family !== daughter ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 6) begin + if (family !== 5 ) begin $display("%b", family ); $stop(); end + if (family !== gerbil ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 7) begin + if (family !== 10 ) begin $display("%b", family ); $stop(); end + if (family !== dog0 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 8) begin + if (family !== 11 ) begin $display("%b", family ); $stop(); end + if (family !== dog1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 9) begin + if (family !== 12 ) begin $display("%b", family ); $stop(); end + if (family !== dog2 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 10) begin + if (family !== 20 ) begin $display("%b", family ); $stop(); end + if (family !== cat3 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 11) begin + if (family !== 21 ) begin $display("%b", family ); $stop(); end + if (family !== cat4 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 12) begin + if (family !== 22 ) begin $display("%b", family ); $stop(); end + if (family !== cat5 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 13) begin + if (family !== 30 ) begin $display("%b", family ); $stop(); end + if (family !== car3 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 14) begin + if (family !== 31 ) begin $display("%b", family ); $stop(); end + if (family !== car2 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + else if (cnt== 15) begin + if (family !== 32 ) begin $display("%b", family ); $stop(); end + if (family !== car1 ) begin $display("%b", family ); $stop(); end + family <= family.next(); + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_extend.v b/SVIncCompil/Testcases/Verilator/t_extend.v new file mode 100644 index 0000000..31814f1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_extend.v
@@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + /*verilator public_module*/ + + input clk; + // No verilator_public needed, because it's outside the "" in the $c statement + reg [7:0] cyc; initial cyc=0; + reg c_worked; + reg [8:0] c_wider; + + wire one = 1'b1; + + always @ (posedge clk) begin + cyc <= cyc+8'd1; + + // coverage testing + if (one) begin end + if (!one) begin end + if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line + + if (cyc == 8'd1) begin + c_worked <= 0; + end + if (cyc == 8'd2) begin +`ifdef VERILATOR + $c("VL_PRINTF(\"Calling $c, calling $c...\\n\");"); + $c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");"); + c_worked <= $c("my_function()"); + c_wider <= $c9("0x10"); +`else + c_worked <= 1'b1; + c_wider <= 9'h10; +`endif + end + if (cyc == 8'd3) begin + if (c_worked !== 1'b1) $stop; + if (c_wider !== 9'h10) $stop; + $finish; + end + end + +`ifdef verilator + `systemc_header +#define DID_INT_HEADER 1 + `systemc_interface +#ifndef DID_INT_HEADER +#error "`systemc_header didn't work" +#endif + bool m_did_ctor; + vluint32_t my_function() { + if (!m_did_ctor) vl_fatal(__FILE__,__LINE__,__FILE__,"`systemc_ctor didn't work"); + return 1; + } + `systemc_imp_header +#define DID_IMP_HEADER 1 + `systemc_implementation +#ifndef DID_IMP_HEADER +#error "`systemc_imp_header didn't work" +#endif + `systemc_ctor + m_did_ctor = 1; + `systemc_dtor + printf("In systemc_dtor\n"); + printf("*-* All Finished *-*\n"); + `verilog + +// Test verilator comment after a endif +`endif // verilator + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_extend_class.v b/SVIncCompil/Testcases/Verilator/t_extend_class.v new file mode 100644 index 0000000..fa3e3bc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_extend_class.v
@@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg [7:0] cyc; initial cyc=0; + + reg [31:0] in; + wire [31:0] out; + t_extend_class_v sub (.in(in), .out(out)); + + always @ (posedge clk) begin + cyc <= cyc+8'd1; + if (cyc == 8'd1) begin + in <= 32'h10; + end + if (cyc == 8'd2) begin + if (out != 32'h11) $stop; + end + if (cyc == 8'd9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module t_extend_class_v (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [31:0] in; + output [31:0] out; + + always @* begin + // When "in" changes, call my method + out = $c("m_myobjp->my_math(",in,")"); + end + + `systemc_header +#include "t_extend_class_c.h" // Header for contained object + `systemc_interface + t_extend_class_c* m_myobjp; // Pointer to object we are embedding + `systemc_ctor + m_myobjp = new t_extend_class_c(); // Construct contained object + `systemc_dtor + delete m_myobjp; // Destruct contained object + `verilog + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_final.v b/SVIncCompil/Testcases/Verilator/t_final.v new file mode 100644 index 0000000..b66c49e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_final.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Charlie Brej. + +module submodule (); + // This bug only appears when not inlining + // verilator no_inline_module + initial begin + $write("d"); + end + final begin + $write("d"); + end +endmodule + +module t (); + generate + for (genvar i = 0; i < 100; i = i + 1) begin : module_set + submodule u_submodule(); + end + endgenerate + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_bboxsys.v b/SVIncCompil/Testcases/Verilator/t_flag_bboxsys.v new file mode 100644 index 0000000..92f9229 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_bboxsys.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + reg a; + initial begin + $unknown_sys_task_call_to_be_bbox("blah"); + $unkown_sys_task_call_noarg; + a = $unknown_sys_func_call(23); + a = $unknown_sys_func_call_noarg; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_csplit.v b/SVIncCompil/Testcases/Verilator/t_flag_csplit.v new file mode 100644 index 0000000..b90ab14 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_csplit.v
@@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + parameter CNT = 5; + + wire [31:0] w [CNT:0]; + + generate + for (genvar g=0; g<CNT; g++) + sub sub (.clk(clk), .i(w[g]), .z(w[g+1])); + endgenerate + + reg [31:0] w0; + assign w[0] = w0; + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + w0 = 32'h1234; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +`define EXPECTED_SUM 32'h1239 +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, w[CNT]); +`endif + if (w[CNT] !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub (input clk, input [31:0] i, output [31:0] z); + always @(posedge clk) + z <= i+1+$c("0"); // $c so doesn't optimize away +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_debug_noleak.v b/SVIncCompil/Testcases/Verilator/t_flag_debug_noleak.v new file mode 100644 index 0000000..6b86617 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_debug_noleak.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_debugi9.v b/SVIncCompil/Testcases/Verilator/t_flag_debugi9.v new file mode 100644 index 0000000..5d61f1f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_debugi9.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + o, + // Inputs + i + ); + + // Need some logic to get mtask debug fully covered + input i; + output wire o; + assign o = i; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_define.v b/SVIncCompil/Testcases/Verilator/t_flag_define.v new file mode 100644 index 0000000..d26cc18 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_define.v
@@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder + +`define STRINGIFY(x) `"x`" + +module t; + initial begin +`ifdef D1A + if (`STRINGIFY(`D4B) !== "") $stop; +`else + $write("%%Error: Missing define\n"); $stop; +`endif + +`ifdef D2A + if (`STRINGIFY(`D2A) !== "VALA") $stop; +`else + $write("%%Error: Missing define\n"); $stop; +`endif + +`ifdef D3A + if (`STRINGIFY(`D4B) !== "") $stop; +`else + $write("%%Error: Missing define\n"); $stop; +`endif + +`ifdef D3B + if (`STRINGIFY(`D4B) !== "") $stop; +`else + $write("%%Error: Missing define\n"); $stop; +`endif + +`ifdef D4A + if (`STRINGIFY(`D4A) !== "VALA") $stop; +`else + $write("%%Error: Missing define\n"); $stop; +`endif + +`ifdef D4B + if (`STRINGIFY(`D4B) !== "") $stop; +`else + $write("%%Error: Missing define\n"); $stop; +`endif + +`ifdef D5A + if (`STRINGIFY(`D5A) !== "VALA") $stop; +`else + $write("%%Error: Missing define\n"); $stop; +`endif + +`ifdef D5A + if (`STRINGIFY(`D5B) !== "VALB") $stop; +`else + $write("%%Error: Missing define\n"); $stop; +`endif + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_errorlimit_bad.v b/SVIncCompil/Testcases/Verilator/t_flag_errorlimit_bad.v new file mode 100644 index 0000000..2d38974 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_errorlimit_bad.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/); + + int u1; + int u1; + int u1; + int u1; + int u1; + int u1; + int u1; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_f.v b/SVIncCompil/Testcases/Verilator/t_flag_f.v new file mode 100644 index 0000000..5532d93 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_f.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module + +`include "t_flag_f_tsub_inc.v" + +module t; + initial begin +`ifndef GOT_DEF1 + $write("%%Error: NO GOT_DEF1\n"); $stop; +`endif +`ifndef GOT_DEF2 + $write("%%Error: NO GOT_DEF2\n"); $stop; +`endif +`ifndef GOT_DEF3 + $write("%%Error: NO GOT_DEF3\n"); $stop; +`endif +`ifndef GOT_DEF4 + $write("%%Error: NO GOT_DEF4\n"); $stop; +`endif +`ifndef GOT_DEF5 + $write("%%Error: NO GOT_DEF5\n"); $stop; +`endif +`ifndef GOT_DEF6 + $write("%%Error: NO GOT_DEF6\n"); $stop; +`endif +`ifdef NON_DEF + $write("%%Error: NON_DEF\n"); $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_f__3.v b/SVIncCompil/Testcases/Verilator/t_flag_f__3.v new file mode 100644 index 0000000..ccbf697 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_f__3.v
@@ -0,0 +1 @@ +`define GOT_DEF3 1
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_fi.v b/SVIncCompil/Testcases/Verilator/t_flag_fi.v new file mode 100644 index 0000000..5ff0634 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_fi.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2017 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (); + initial begin + $c("myfunction();"); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_future.v b/SVIncCompil/Testcases/Verilator/t_flag_future.v new file mode 100644 index 0000000..4394b97 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_future.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module + +module t; + initial begin + // verilator lint_off FUTURE1 + $write("*-* All Finished *-*\n"); + $finish; + // verilator FUTURE2 + // verilator FUTURE2 blah blah + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_getenv.v b/SVIncCompil/Testcases/Verilator/t_flag_getenv.v new file mode 100644 index 0000000..99a0ead --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_getenv.v
@@ -0,0 +1,6 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`define EMPTY 1
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_language.v b/SVIncCompil/Testcases/Verilator/t_flag_language.v new file mode 100644 index 0000000..4c3c8b6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_language.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/); + + // See also t_preproc_kwd.v + + integer bit; initial bit = 1; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_ldflags.v b/SVIncCompil/Testcases/Verilator/t_flag_ldflags.v new file mode 100644 index 0000000..1efc403 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_ldflags.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +import "DPI-C" pure function void dpii_a_library(); +import "DPI-C" pure function void dpii_c_library(); +import "DPI-C" pure function void dpii_so_library(); + +module t (); + initial begin + dpii_a_library(); // From .a file + dpii_c_library(); // From .cpp file + dpii_so_library(); // From .so file + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_lib.v b/SVIncCompil/Testcases/Verilator/t_flag_lib.v new file mode 100644 index 0000000..012bf71 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_lib.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/); + + liblib_a a (); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_libinc.v b/SVIncCompil/Testcases/Verilator/t_flag_libinc.v new file mode 100644 index 0000000..26769e4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_libinc.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module liblib_a (/*AUTOARG*/); + liblib_b b (); +endmodule + +module liblib_b (/*AUTOARG*/); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module liblib_c (/*AUTOARG*/); + // Unused + initial $stop; + liblib_d d (); +endmodule + +module liblib_d (/*AUTOARG*/); + // Unused + initial $stop; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_names.v b/SVIncCompil/Testcases/Verilator/t_flag_names.v new file mode 100644 index 0000000..8f83f05 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_names.v
@@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +module t; + sub sub (); +endmodule + +module sub; + //verilator no_inline_module + string scope; + initial begin + scope = $sformatf("%m"); + $write("[%0t] In %s\n", $time, scope); +`ifdef VERILATOR + if (scope != "top.l2Name.sub") $stop; +`else + if (scope != "top.t.sub") $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_nomod_bad.v b/SVIncCompil/Testcases/Verilator/t_flag_nomod_bad.v new file mode 100644 index 0000000..99a0ead --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_nomod_bad.v
@@ -0,0 +1,6 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`define EMPTY 1
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_parameter.v b/SVIncCompil/Testcases/Verilator/t_flag_parameter.v new file mode 100644 index 0000000..77dd585 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_parameter.v
@@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder + +`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); $stop; end while(0); + +module t; + parameter string1 = "Original String"; + parameter string2 = "Original String"; + + parameter real11 = 0.1; + parameter real12 = 0.1; + parameter real21 = 0.1; + parameter real22 = 0.1; + parameter real31 = 0.1; + parameter real32 = 0.1; + + parameter int11 = 1; + parameter int12 = 1; + parameter int21 = 1; + parameter int22 = 1; + parameter int31 = 1; + parameter int32 = 1; + parameter int41 = 1; + parameter int42 = 1; + + initial begin + `check(string1,"New String"); + `check(string2,"New String"); + `check(real11,0.2); + `check(real12,0.2); + `check(real21,400); + `check(real22,400); + `check(real31,20); + `check(real32,20); + `check(int11,16); + `check(int12,16); + `check(int21,16); + `check(int22,16); + `check(int31,123); + `check(int32,123); + `check(int41,32'hdeadbeef); + `check(int42,32'hdeadbeef); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_relinc.v b/SVIncCompil/Testcases/Verilator/t_flag_relinc.v new file mode 100644 index 0000000..c9cdf70 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_relinc.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2017 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t; + t_flag_relinc_sub sub (); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_relinc_dir/chip/t_flag_relinc_sub.v b/SVIncCompil/Testcases/Verilator/t_flag_relinc_dir/chip/t_flag_relinc_sub.v new file mode 100644 index 0000000..dd38e5e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_relinc_dir/chip/t_flag_relinc_sub.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2017 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`include "../include/t_flag_relinc.vh" + +module t_flag_relinc_sub (); + initial begin + `all_finished; + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_relinc_dir/include/t_flag_relinc.vh b/SVIncCompil/Testcases/Verilator/t_flag_relinc_dir/include/t_flag_relinc.vh new file mode 100644 index 0000000..6a19cfb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_relinc_dir/include/t_flag_relinc.vh
@@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2017 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`define all_finished $write("*-* All Finished *-*\n")
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_skipidentical.v b/SVIncCompil/Testcases/Verilator/t_flag_skipidentical.v new file mode 100644 index 0000000..7e30bb8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_skipidentical.v
@@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_stats.v b/SVIncCompil/Testcases/Verilator/t_flag_stats.v new file mode 100644 index 0000000..2bd129e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_stats.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (b); + output reg [31:0] b; + initial begin + b = 22; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_topmod2_bad.v b/SVIncCompil/Testcases/Verilator/t_flag_topmod2_bad.v new file mode 100644 index 0000000..9933baf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_topmod2_bad.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module a_top; + a a (); + initial begin + $write("Bad top modules\n"); + $stop; + end +endmodule + +module a; + b b (); + c c (); + d d (); +endmodule + +module b; +endmodule + +module c; +endmodule + +module d; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_topmodule.v b/SVIncCompil/Testcases/Verilator/t_flag_topmodule.v new file mode 100644 index 0000000..ba3e5b7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_topmodule.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module a; + c c (); + initial begin + $write("Bad top modules\n"); + $stop; + end +endmodule + +module a2; + initial begin + $write("Bad top modules\n"); + $stop; + end +endmodule + +module b; + d d (); +endmodule + +module c; + initial begin + $write("Bad mid modules\n"); + $stop; + end +endmodule + +module d; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_topmodule_inline.v b/SVIncCompil/Testcases/Verilator/t_flag_topmodule_inline.v new file mode 100644 index 0000000..1b9b737 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_topmodule_inline.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module a; + a2 a2 (.tmp(1'b0)); + initial begin + $write("Bad top modules\n"); + $stop; + end +endmodule + +module a2 (input tmp); + l3 l3 (.tmp(tmp)); +endmodule + +module b; + l3 l3 (.tmp(1'b1)); +endmodule + +module l3 (input tmp); + initial begin + if (tmp) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_werror.v b/SVIncCompil/Testcases/Verilator/t_flag_werror.v new file mode 100644 index 0000000..11acd86 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_werror.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/); + + // Width error below + wire [3:0] foo = 6'h2e; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_wfatal.v b/SVIncCompil/Testcases/Verilator/t_flag_wfatal.v new file mode 100644 index 0000000..11acd86 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_wfatal.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/); + + // Width error below + wire [3:0] foo = 6'h2e; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_woff.v b/SVIncCompil/Testcases/Verilator/t_flag_woff.v new file mode 100644 index 0000000..7c2936d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_woff.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + + // width warnings off due to command line + wire A = 15'd1234; + + // width warnings off due to command line + manual switch + // verilator lint_off WIDTH + wire B = 15'd1234; + + // this turnon does nothing as off on command line + // verilator lint_on WIDTH + wire C = 15'd1234; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_xinitial_0.v b/SVIncCompil/Testcases/Verilator/t_flag_xinitial_0.v new file mode 100644 index 0000000..fed402a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_xinitial_0.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + value + ); + + output reg [63:0] value; + + initial begin +`ifdef VERILATOR + // Default is all ones, so we assume that here + if (value != '0) $stop; +`else + if (value != {64{1'bx}}) $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_flag_xinitial_unique.v b/SVIncCompil/Testcases/Verilator/t_flag_xinitial_unique.v new file mode 100644 index 0000000..a23f071 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_flag_xinitial_unique.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + value + ); + + output reg [63:0] value; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_for_break.v b/SVIncCompil/Testcases/Verilator/t_for_break.v new file mode 100644 index 0000000..748be30 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_for_break.v
@@ -0,0 +1,143 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [3:0] l_stop = crc[3:0]; + wire [3:0] l_break = crc[7:4]; + wire [3:0] l_continue = crc[11:8]; + + /*AUTOWIRE*/ + + wire [15:0] out0 = Test0(l_stop, l_break, l_continue); + wire [15:0] out1 = Test1(l_stop, l_break, l_continue); + wire [15:0] out2 = Test2(l_stop, l_break, l_continue); + wire [15:0] out3 = Test3(l_stop, l_break, l_continue); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out3,out2,out1,out0}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + if (out0!==out1) $stop; + if (out0!==out2) $stop; + if (out0!==out3) $stop; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h293e9f9798e97da0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + function [15:0] Test0; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer i; + reg broken; + + Test0 = 0; + broken = 0; + begin + for (i=1; i<20; i=i+1) begin + if (!broken) begin + Test0 = Test0 + 1; + if (i[3:0] != loop_continue) begin // continue + if (i[3:0] == loop_break) begin + broken = 1'b1; + end + if (!broken) begin + Test0 = Test0 + i[15:0]; + end + end + end + end + end + endfunction + + function [15:0] Test1; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer i; + + Test1 = 0; + begin : outer_block + for (i=1; i<20; i=i+1) begin : inner_block + Test1 = Test1 + 1; + // continue, IE jump to end-of-inner_block. Must be inside inner_block. + if (i[3:0] == loop_continue) disable inner_block; + // break, IE jump to end-of-outer_block. Must be inside outer_block. + if (i[3:0] == loop_break) disable outer_block; + Test1 = Test1 + i[15:0]; + end : inner_block + end : outer_block + endfunction + + function [15:0] Test2; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer i; + + Test2 = 0; + begin + for (i=1; i<20; i=i+1) begin + Test2 = Test2 + 1; + if (i[3:0] == loop_continue) continue; + if (i[3:0] == loop_break) break; + Test2 = Test2 + i[15:0]; + end + end + endfunction + + function [15:0] Test3; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer i; + + Test3 = 0; + begin + for (i=1; i<20; i=i+1) begin + Test3 = Test3 + 1; + if (i[3:0] == loop_continue) continue; + // return, IE jump to end-of-function optionally setting return value + if (i[3:0] == loop_break) return Test3; + Test3 = Test3 + i[15:0]; + end + end + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_for_comma_bad.v b/SVIncCompil/Testcases/Verilator/t_for_comma_bad.v new file mode 100644 index 0000000..3fec798 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_for_comma_bad.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/); + + integer a, b; + + initial begin + for (; ; ) ; + for (; ; a=a+1) ; + for (; ; a=a+1, b=b+1) ; + for (; a<1; ) ; + for (; a<1; a=a+1) ; + for (; a<1; a=a+1, b=b+1) ; + for (a=0; a<1; ) ; + for (a=0; a<1; a=a+1) ; + for (a=0; a<1; a=a+1, b=b+1) ; + for (integer a=0; a<1; ) ; + for (integer a=0; a<1; a=a+1) ; + for (integer a=0; a<1; a=a+1, b=b+1) ; + for (var integer a=0; a<1; ) ; + for (var integer a=0; a<1; a=a+1) ; + for (var integer a=0; a<1; a=a+1, b=b+1) ; + for (integer a=0, integer b=0; a<1; ) ; + for (integer a=0, integer b=0; a<1; a=a+1) ; + for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_for_count.v b/SVIncCompil/Testcases/Verilator/t_for_count.v new file mode 100644 index 0000000..99ac6d4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_for_count.v
@@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + integer j; + reg [63:0] cam_lookup_hit_vector; + + integer hit_count; + always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin + hit_count = 0; + for (j=0; j < 64; j=j+1) begin + hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]}; + end + end + + integer hit_count2; + always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin + hit_count2 = 0; + for (j=63; j >= 0; j=j-1) begin + hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]}; + end + end + + integer hit_count3; + always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin + hit_count3 = 0; + for (j=63; j > 0; j=j-1) begin + if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1; + end + end + + reg [127:0] wide_for_index; + reg [31:0] wide_for_count; + always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin + wide_for_count = 0; + for (wide_for_index = 128'hff_00000000_00000000; + wide_for_index < 128'hff_00000000_00000100; + wide_for_index = wide_for_index + 2) begin + wide_for_count = wide_for_count+32'h1; + end + end + + // While loop + integer w; + initial begin + while (w<10) w=w+1; + if (w!=10) $stop; + while (w<20) begin w=w+2; end + while (w<20) begin w=w+99999; end // NEVER + if (w!=20) $stop; + end + + // Do-While loop + integer dw; + initial begin + do dw=dw+1; while (dw<10); + if (dw!=10) $stop; + do dw=dw+2; while (dw<20); + if (dw!=20) $stop; + do dw=dw+5; while (dw<20); // Once + if (dw!=25) $stop; + end + + always @ (posedge clk) begin + cam_lookup_hit_vector <= 0; + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + cam_lookup_hit_vector <= 64'h00010000_00010000; + end + if (cyc==2) begin + if (hit_count != 32'd2) $stop; + if (hit_count2 != 32'd2) $stop; + if (hit_count3 != 32'd2) $stop; + cam_lookup_hit_vector <= 64'h01010010_00010001; + end + if (cyc==3) begin + if (hit_count != 32'd5) $stop; + if (hit_count2 != 32'd5) $stop; + if (hit_count3 != 32'd4) $stop; + if (wide_for_count != 32'h80) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_for_funcbound.v b/SVIncCompil/Testcases/Verilator/t_for_funcbound.v new file mode 100644 index 0000000..5a098d4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_for_funcbound.v
@@ -0,0 +1,76 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer j; + integer hit_count; + reg [63:0] cam_lookup_hit_vector; + + strings strings (); + + task show; + input [8*8-1:0] str; + reg [7:0] char; + integer loc; + begin + $write("[%0t] ",$time); + strings.stringStart(8*8-1); + for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin + $write("%c",char); + end + $write("\n"); + end + endtask + + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + show("hello\000xx"); + end + if (cyc==2) begin + show("world\000xx"); + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module strings; + // **NOT** reentrant, just a test! + integer index; + task stringStart; + input [31:0] bits; + begin + index = (bits-1)/8; + end + endtask + + function isNull; + input [7:0] chr; + isNull = (chr == 8'h0); + endfunction + + function [7:0] stringByte; + input [8*8-1:0] str; + begin + if (index<=0) stringByte=8'h0; + else stringByte = str[index*8 +: 8]; + index = index - 1; + end + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_for_init_bug.v b/SVIncCompil/Testcases/Verilator/t_for_init_bug.v new file mode 100644 index 0000000..b00eeb2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_for_init_bug.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + priority_mask, + // Inputs + muxed_requests + ); + + parameter ARW = 7; + + // verilator lint_off UNOPTFLAT + integer i,j; + + output reg [ARW-1:0] priority_mask; + + input [ARW-1:0] muxed_requests; + + always @* begin + for (i=ARW-1;i>0;i=i-1) begin + priority_mask[i]=1'b0; + // vvvv=== note j=j not j=i; was bug + for( j=j;j>=0;j=j-1) + priority_mask[i]=priority_mask[j] | muxed_requests[j]; + end + //Bit zero is always enabled + priority_mask[0]=1'b0; + end + +endmodule + +// Local Variables: +// verilog-auto-inst-param-value: t +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_for_local.v b/SVIncCompil/Testcases/Verilator/t_for_local.v new file mode 100644 index 0000000..de69851 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_for_local.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg [7:0] cyc; initial cyc=0; + + reg [31:0] loops; + reg [31:0] loops2; + + always @ (posedge clk) begin + cyc <= cyc+8'd1; + if (cyc == 8'd1) begin + $write("[%0t] t_loop: Running\n",$time); + // Unwind < + loops = 0; + loops2 = 0; + for (int i=0; i<16; i=i+1) begin + loops = loops + i; // surefire lint_off_line ASWEMB + loops2 = loops2 + i; // surefire lint_off_line ASWEMB + end + if (loops !== 120) $stop; + if (loops2 !== 120) $stop; + // Check we can declare the same signal twice + loops = 0; + for (int i=0; i<=16; i=i+1) begin + loops = loops + 1; + end + if (loops !== 17) $stop; + // Check type is correct + loops = 0; + for (byte unsigned i=5; i>4; i=i+1) begin + loops = loops + 1; + end + if (loops !== 251) $stop; + // Check large loops + loops = 0; + for (int i=0; i<100000; i=i+1) begin + loops = loops + 1; + end + if (loops !== 100000) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_for_loop.v b/SVIncCompil/Testcases/Verilator/t_for_loop.v new file mode 100644 index 0000000..8d8c4ac --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_for_loop.v
@@ -0,0 +1,102 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg [7:0] cyc; initial cyc=0; + + reg [31:0] loops; + reg [31:0] loops2; + integer i; + + always @ (posedge clk) begin + cyc <= cyc+8'd1; + if (cyc == 8'd1) begin + $write("[%0t] t_loop: Running\n",$time); + // Unwind < + loops = 0; + loops2 = 0; + for (i=0; i<16; i=i+1) begin + loops = loops + i; // surefire lint_off_line ASWEMB + loops2 = loops2 + i; // surefire lint_off_line ASWEMB + end + if (i !== 16) $stop; + if (loops !== 120) $stop; + if (loops2 !== 120) $stop; + // Unwind <= + loops = 0; + for (i=0; i<=16; i=i+1) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Don't unwind breaked loops + loops = 0; + for (i=0; i<16; i=i+1) begin + loops = loops + 1; + if (i==7) i=99; // break out of loop + end + if (loops !== 8) $stop; + // Don't unwind large loops! + loops = 0; + for (i=0; i<100000; i=i+1) begin + loops = loops + 1; + end + if (loops !== 100000) $stop; + // Test post-increment + loops = 0; + for (i=0; i<=16; i++) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Test pre-increment + loops = 0; + for (i=0; i<=16; ++i) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Test post-decrement + loops = 0; + for (i=16; i>=0; i--) begin + loops = loops + 1; + end + if (i !== -1) $stop; + if (loops !== 17) $stop; + // Test pre-decrement + loops = 0; + for (i=16; i>=0; --i) begin + loops = loops + 1; + end + if (i !== -1) $stop; + if (loops !== 17) $stop; + // + // 1800-2017 optionals init/expr/incr + loops = 0; + i = 0; + for (; i<10; ++i) ++loops; + if (loops !== 10) $stop; + // + loops = 0; + i = 0; + for (i=0; i<10; ) begin ++loops; ++i; end + if (loops !== 10) $stop; + // + loops = 0; + i = 0; + for (; ; ++i) begin ++loops; break; end + if (loops !== 1) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_foreach.v b/SVIncCompil/Testcases/Verilator/t_foreach.v new file mode 100644 index 0000000..e6dcc5c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_foreach.v
@@ -0,0 +1,92 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/); + + // verilator lint_off LITENDIAN + // verilator lint_off WIDTH + + reg [63:0] sum; + reg [2:1] [4:3] array [5:6] [7:8]; + reg [1:2] [3:4] larray [6:5] [8:7]; + bit [31:0] depth1_array [0:0]; + + function [63:0] crc (input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); + crc = {sum[62:0],sum[63]} ^ {4'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; + endfunction + + initial begin + sum = 0; + // We use 'index_' as the prefix for all loop vars, + // this allows t_foreach.pl to confirm that all loops + // have been unrolled and flattened away and no loop vars + // remain in the generated .cpp + foreach (depth1_array[index_a]) begin + sum = crc(sum, index_a, 0, 0, 0); + + // Ensure the index never goes out of bounds. + // We used to get this wrong for an array of depth 1. + assert (index_a != -1); + assert (index_a != 1); + end + `checkh(sum, 64'h0); + + sum = 0; + foreach (array[index_a]) begin + sum = crc(sum, index_a, 0, 0, 0); + end + `checkh(sum, 64'h000000c000000000); + + sum = 0; + foreach (array[index_a,index_b]) begin + sum = crc(sum, index_a, index_b, 0, 0); + end + `checkh(sum, 64'h000003601e000000); + + sum = 0; + foreach (array[index_a,index_b,index_c]) begin + sum = crc(sum, index_a, index_b, index_c, 0); + end + `checkh(sum, 64'h00003123fc101000); + + sum = 0; + foreach (array[index_a,index_b,index_c,index_d]) begin + sum = crc(sum, index_a, index_b, index_c, index_d); + end + `checkh(sum, 64'h0030128ab2a8e557); + + // + + sum = 0; + foreach (larray[index_a]) begin + sum = crc(sum, index_a, 0, 0, 0); + end + `checkh(sum, 64'h0000009000000000); + + sum = 0; + foreach (larray[index_a,index_b]) begin + sum = crc(sum, index_a, index_b, 0, 0); + sum = sum + {4'b0,index_a[7:0], 4'h0,index_b[7:0]}; + end + `checkh(sum, 64'h000002704b057073); + + sum = 0; + foreach (larray[index_a,index_b,index_c]) begin + sum = crc(sum, index_a, index_b, index_c, 0); + end + `checkh(sum, 64'h00002136f9000000); + + sum = 0; + foreach (larray[index_a,index_b,index_c,index_d]) begin + sum = crc(sum, index_a, index_b, index_c, index_d); + end + `checkh(sum, 64'h0020179aa7aa0aaa); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func.v b/SVIncCompil/Testcases/Verilator/t_func.v new file mode 100644 index 0000000..c9b7119 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func.v
@@ -0,0 +1,155 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + reg [2:0] value; + reg [31:0] rglobal; + reg [31:0] vec [1:0]; + reg [31:0] n; + + initial begin + rglobal = 1; + value = 2; + if (add(value) != 3'd3) $stop; + if (rglobal != 2) $stop; + if (add(add(3'd1)) != 3'd3) $stop; + if (rglobal != 4) $stop; + if (munge4(4'b0010) != 4'b1011) $stop; + if (toint(2) != 3) $stop; + if (rglobal != 5) $stop; + setit; + incr(rglobal,rglobal,32'h10); + if (rglobal != 32'h17) $stop; + nop(32'h11); + empty; + empty(); + + rglobal = 32'h00000001; + flipupperbit(rglobal,4'd4); + flipupperbit(rglobal,4'd12); + if (rglobal !== 32'h10100001) $stop; + + if (nil_func(32'h12,32'h12) != 32'h24) $stop; + nil_task(32'h012,32'h112,rglobal); + if (rglobal !== 32'h124) $stop; + + vec[0] = 32'h333; + vec[1] = 32'habc; + incr(vec[1],vec[0],vec[1]); + if (vec[0] != 32'h333) $stop; + if (vec[1] != 32'hdef) $stop; + + // verilator lint_off SELRANGE + incr(vec[2],vec[0],vec[2]); // Reading/Writing past end of vector! + // verilator lint_on SELRANGE + + n=1; + nil(); + if (n !== 10) $stop; + + // Functions called as tasks + // verilator lint_off IGNOREDRETURN + rglobal = 32'h4; + if (inc_and_return(32'h2) != 32'h6) $stop; + if (rglobal !== 32'h6) $stop; + rglobal = 32'h6; + + inc_and_return(32'h3); + if (rglobal !== 32'h9) $stop; + // verilator lint_on IGNOREDRETURN + + $write("*-* All Finished *-*\n"); + $finish; + end + + function [2:0] add; + input [2:0] fromv; + begin + add = fromv + 3'd1; + begin : named + reg [31:0] flocal; + flocal = 1; + rglobal = rglobal + flocal; + end : named // SystemVerilog end labels + end + endfunction + + function [3:0] munge4; + input [3:0] fromv; // Different fromv than the 'fromv' signal above + reg one; + begin : named + reg [1:0] flocal; + // Function calling a function + one = 1'b1; + munge4 = {one, add(fromv[2:0])}; + end + endfunction + + task setit; + reg [31:0] temp; + begin + temp = rglobal + 32'h1; + rglobal = temp + 32'h1; + end + endtask + + task incr ( + // Check a V2K style input/output list + output [31:0] z, + input [31:0] a, inc + ); + z = a + inc; + endtask + + task nop; + input [31:0] a; + begin + end + endtask + + task empty; + endtask + + task flipupperbit; + inout [31:0] vector; + input [3:0] bitnum; + reg [4:0] bitnum2; + begin + bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation + vector[bitnum2] = vector[bitnum2] ^ 1'b1; + end + endtask + + task nil_task; + input [31:0] a; + input [31:0] b; + output [31:0] q; + // verilator no_inline_task + q = nil_func(a, b); + endtask + + function void nil; + n = 10; + endfunction + + function [31:0] nil_func; + input [31:0] fa; + input [31:0] fb; + // verilator no_inline_task + nil_func = fa + fb; + endfunction + + function integer toint; + input integer fa; + toint = fa + 32'h1; + endfunction + + function [31:0] inc_and_return; + input [31:0] inc; + rglobal = rglobal + inc; + return rglobal; + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_bad.v b/SVIncCompil/Testcases/Verilator/t_func_bad.v new file mode 100644 index 0000000..4ed56fa --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_bad.v
@@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + initial begin + if (add(3'd1) != 0) $stop; // Too few args + if (add(3'd1, 3'd2, 3'd3) != 0) $stop; // Too many args + x; // Too few args + if (hasout(3'd1) != 0) $stop; // outputs + // + f(.j(1), .no_such(2)); // Name mismatch + f(.dup(1), .dup(3)); // Duplicate + f(1,2,3); // Too many + end + + function [2:0] add; + input [2:0] from1; + input [2:0] from2; + begin + add = from1 + from2; + end + endfunction + + task x; + output y; + begin end + endtask + + function hasout; + output [2:0] illegal_output; + hasout = 0; + endfunction + + function int f( int j = 1, int dup = 0 ); + return (j<<16) | dup; + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_bad2.v b/SVIncCompil/Testcases/Verilator/t_func_bad2.v new file mode 100644 index 0000000..b90fa08 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_bad2.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + function recurse; + input i; + recurse = recurse2(i); + endfunction + + function recurse2; + input i; + recurse2 = recurse(i); + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_bad_width.v b/SVIncCompil/Testcases/Verilator/t_func_bad_width.v new file mode 100644 index 0000000..163d9ff --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_bad_width.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + + reg [3:0] out; + reg [38:0] in; + initial begin + in = 39'h0; + out = MUX (in); + $write("bad widths %x", out); + end + + function [31:0] MUX; + input [39:0] XX ; + begin + MUX = XX[39:8]; + end + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_begin2.v b/SVIncCompil/Testcases/Verilator/t_func_begin2.v new file mode 100644 index 0000000..57f5f3c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_begin2.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module init; + + task t1; + reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; + reg ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz; + reg da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn, dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz; + begin : READER + $display ("Time: %0t Instance: %m", $time); + end + endtask + + task t2; + reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; + begin : READER + $display ("Time: %0t Instance: %m", $time); + end + endtask +endmodule + +module test(); + init u_ram1(); + init u_ram2(); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_check.v b/SVIncCompil/Testcases/Verilator/t_func_check.v new file mode 100644 index 0000000..32e391d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_check.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module + +// verilator lint_off WIDTH +// verilator lint_off VARHIDDEN + +module t ( + clk + ); + input clk; + integer cyc=0; + reg [63:0] crc; initial crc = 64'h1; + + chk chk (.clk (clk), + .rst_l (1'b1), + .expr (|crc) + ); + + always @ (posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module chk (input clk, input rst_l, input expr); + + integer errors; initial errors = 0; + + task printerr; + input [8*64:1] msg; + begin + errors = errors + 1; + $write("%%Error: %0s\n", msg); + $stop; + end + endtask + + always @(posedge clk) begin + if (rst_l) begin + if (expr == 1'b0) begin + printerr("expr not asserted"); + end + end + end + + wire noxs = ((expr ^ expr) == 1'b0); + + reg hasx; + always @ (noxs) begin + if (noxs) begin + hasx = 1'b0; + end + else begin + hasx = 1'b1; + end + end + + always @(posedge clk) begin + if (rst_l) begin + if (hasx) begin + printerr("expr has unknowns"); + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_const.v b/SVIncCompil/Testcases/Verilator/t_func_const.v new file mode 100644 index 0000000..fa0ed25 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_const.v
@@ -0,0 +1,129 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +package testpackage; + localparam PARAM = 1024 >> 3; +endpackage +import testpackage::*; + +module t; + + localparam P4 = f_add(P3,1); + localparam P8 = f_add2(P3,P3,f_add(1,1)); + localparam P5 = f_while(7); + localparam P16 = f_for(P4); + localparam P18 = f_case(P4); + localparam P6 = f_return(P4); + localparam P3 = 3; + localparam P128 = f_package(); + + typedef struct packed { + logic [7:0] data; + } type_t; + typedef type_t [1:0] flist; + localparam flist PLIST = {8'd4,8'd8}; + localparam flist PARR = f_list_swap_2(PLIST); + typedef struct packed { + logic first; + logic second; + logic [31:0] data; + } bigstruct_t; + localparam bigstruct_t bigparam = f_return_struct(1'b1, 1'b0, 32'hfff12fff); + + initial begin +`ifdef TEST_VERBOSE + $display("P5=%0d P8=%0d P16=%0d P18=%0d",P5,P8,P16,P18); +`endif + if (P3 !== 3) $stop; + if (P4 !== 4) $stop; + if (P5 !== 5) $stop; + if (P6 !== 6) $stop; + if (P8 !== 8) $stop; + if (P16 !== 16) $stop; + if (P18 !== 18) $stop; + if (PARR[0] != PLIST[1]) $stop; + if (PARR[1] != PLIST[0]) $stop; + if (bigparam.first != 1'b1) $stop; + if (bigparam.second != 1'b0) $stop; + if (bigparam.data != 32'hfff12fff) $stop; + if (P128 != 128) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + + function integer f_package(); + return PARAM; + endfunction + + function integer f_add(input [31:0] a, input [31:0] b); + f_add = a+b; + endfunction + + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + f_add2 = f_add(a,b)+c; + endfunction + + // Speced ok: local variables + function integer f_for(input [31:0] a); + integer i; + integer times; + begin + times = 1; + for (i=0; i<a; i=i+1) times = times*2; + f_for = times; + end + endfunction + + function integer f_while(input [31:0] a); + integer i; + begin + i=0; + begin : named + f_while = 1; + end : named + while (i<=a) begin + if (i[0]) f_while = f_while + 1; + i = i + 1; + end + end + endfunction + + // Speced ok: local variables + function integer f_case(input [31:0] a); + case(a) + 32'd1: f_case = 1; + 32'd0, 32'd4: f_case = 18; + 32'd1234: begin $display("never get here"); $stop; end + default: f_case = 99; + endcase + endfunction + + function integer f_return(input [31:0] a); + integer out = 2; + while (1) begin + out = out+1; + if (a>1) break; + end + while (1) begin + out = out+1; + if (a>1) return 2+out; + end + f_return = 0; + endfunction + + function flist f_list_swap_2(input flist in_list); + f_list_swap_2[0].data = in_list[1].data; + f_list_swap_2[1].data = in_list[0].data; + endfunction + + function bigstruct_t f_return_struct(input first, input second, input [31:0] data); + bigstruct_t result; + result.data = data; + result.first = first; + result.second = second; + return result; + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_const2_bad.v b/SVIncCompil/Testcases/Verilator/t_func_const2_bad.v new file mode 100644 index 0000000..0c863b7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_const2_bad.v
@@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Todd Strader. + +function integer f_add(input [31:0] a, input [31:0] b); + f_add = a+b; + if (f_add == 15) + $fatal(2, "f_add = 15"); +endfunction + +// Speced ok: function called from function +function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + f_add2 = f_add(a,b)+c; +endfunction + +module c9 + #(parameter A = 1, + parameter B = 1); + + localparam SOMEP = f_add2(A, B, 9); + +endmodule + +module b8 + #(parameter A = 1); + + c9 + #(.A (A), + .B (8)) + c9; + +endmodule + +module t; + + localparam P6 = f_add(5, 1); + localparam P14 = f_add2(2, 3, f_add(4, 5)); + //localparam P24 = f_add2(7, 8, 9); + + b8 b8; + b8 #(.A (6)) b8_a6; + b8 #(.A (7)) b8_a7; + + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_const3_bad.v b/SVIncCompil/Testcases/Verilator/t_func_const3_bad.v new file mode 100644 index 0000000..f10970f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_const3_bad.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Todd Strader. + +module c9 + #(parameter A = 1, + parameter B = 1); + + localparam BITS = A*B; + localparam SOMEP = {BITS{1'b0}}; + +endmodule + +module b9 + #(parameter A = 1); + + c9 + #(.A (A), + .B (9)) + c9; + +endmodule + +module t; + + b9 b9; + b9 #(.A (100)) b900; + b9 #(.A (1000)) b9k; + + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_const_bad.v b/SVIncCompil/Testcases/Verilator/t_func_const_bad.v new file mode 100644 index 0000000..3ef441f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_const_bad.v
@@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + + // Speced ignored: system calls. I think this is nasty, so we error instead. + + // Speced Illegal: inout/output/ref not allowed + localparam B1 = f_bad_output(1,2); + function integer f_bad_output(input [31:0] a, output [31:0] o); + f_bad_output = 0; + endfunction + + // Speced Illegal: void + + // Speced Illegal: dotted + localparam EIGHT = 8; + localparam B2 = f_bad_dotted(2); + function integer f_bad_dotted(input [31:0] a); + f_bad_dotted = t.EIGHT; + endfunction + + // Speced Illegal: ref to non-local var + integer modvar; + localparam B3 = f_bad_nonparam(3); + function integer f_bad_nonparam(input [31:0] a); + f_bad_nonparam = modvar; + endfunction + + // Speced Illegal: needs constant function itself + + // Our own - infinite loop + localparam B4 = f_bad_infinite(3); + function integer f_bad_infinite(input [31:0] a); + while (1) begin + f_bad_infinite = 0; + end + endfunction + + // Our own - stop + localparam BSTOP = f_bad_stop(3); + function integer f_bad_stop(input [31:0] a); + $stop; + endfunction + + // Verify $fatal works with sformatf as argument + localparam BFATAL = f_bad_fatal(3); + function integer f_bad_fatal(input [31:0] a); + for (integer i=0;i<3;i++) begin + $display("Printing in loop: %s", $sformatf("%d", i)); + end + $fatal(2, "%s", $sformatf("Fatal Error")); + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_const_packed_array_bad.v b/SVIncCompil/Testcases/Verilator/t_func_const_packed_array_bad.v new file mode 100644 index 0000000..0ed2aa9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_const_packed_array_bad.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Todd Strader. + +module t; + + localparam [ 1 : 0 ] [ 31 : 0 ] P = {32'd5, 32'd1}; + localparam P6 = f_add(P); + localparam P14 = f_add2(2, 3, f_add(P)); + localparam P24 = f_add2(7, 8, 9); + + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end + + function integer f_add(input [ 1 : 0 ] [ 31 : 0 ] params); + f_add = params[0]+params[1]; + if (f_add == 15) + $fatal(2, "f_add = 15"); + endfunction + + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + logic [ 1 : 0 ] [ 31 : 0 ] params; + params[0] = a; + params[1] = b; + f_add2 = f_add(params)+c; + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_const_packed_struct_bad.v b/SVIncCompil/Testcases/Verilator/t_func_const_packed_struct_bad.v new file mode 100644 index 0000000..46d52cc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_const_packed_struct_bad.v
@@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Todd Strader. + +module t; + + typedef struct packed { + logic [ 31 : 0 ] a; + logic [ 31 : 0 ] b; + } params_t; + + localparam P24 = f_add2(7, 8, 9); + + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end + + function integer f_add(input params_t [ 1 : 0 ] params); + f_add = params[0].a+params[1].b; + if (f_add == 15) + $fatal(2, "f_add = 15"); + endfunction + + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + params_t [ 1 : 0 ] params; + params[0] = '{a:a, b:555}; + params[1] = '{a:12345, b:b}; + f_add2 = f_add(params)+c; + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_const_packed_struct_bad2.v b/SVIncCompil/Testcases/Verilator/t_func_const_packed_struct_bad2.v new file mode 100644 index 0000000..01a38a4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_const_packed_struct_bad2.v
@@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Todd Strader. + +module t; + + typedef struct packed { + logic [ 31 : 0 ] b; + logic [ 7 : 0 ] bar; + } sub_params_t; + + typedef struct packed { + logic [ 31 : 0 ] a; + logic [ 5 : 0 ] foo; + sub_params_t sub_params; + } params_t; + + localparam P24 = f_add2(7, 8, 9); + + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end + + function integer f_add(input params_t [ 1 : 0 ] params); + f_add = params[0].a+params[1].sub_params.b; + if (f_add == 15) + $fatal(2, "f_add = 15"); + endfunction + + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + params_t [ 1 : 0 ] params; + sub_params_t sp0; + sub_params_t sp1; + sp0 = '{b:55, bar:111}; + params[0] = '{a:a, foo:11, sub_params:sp0}; + sp1 = '{b:b, bar:112}; + params[1] = '{a:12345, foo:12, sub_params:sp1}; + f_add2 = f_add(params)+c; + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_const_struct_bad.v b/SVIncCompil/Testcases/Verilator/t_func_const_struct_bad.v new file mode 100644 index 0000000..c87514e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_const_struct_bad.v
@@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Todd Strader. + +module t; + + typedef struct packed { + logic [ 31 : 0 ] a; + logic [ 31 : 0 ] b; + } params_t; + + localparam params_t P = '{a:5, b:1}; + localparam P6 = f_add(P); + localparam P14 = f_add2(2, 3, f_add(P)); + localparam P24 = f_add2(7, 8, 9); + + initial begin + // Should never get here + $write("*-* All Finished *-*\n"); + $finish; + end + + function integer f_add(input params_t params); + f_add = params.a+params.b; + if (f_add == 15) + $fatal(2, "f_add = 15"); + endfunction + + // Speced ok: function called from function + function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); + params_t params; + params = '{ + a: a, + b: b + }; + f_add2 = f_add(params)+c; + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_crc.v b/SVIncCompil/Testcases/Verilator/t_func_crc.v new file mode 100644 index 0000000..cd9f98c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_crc.v
@@ -0,0 +1,143 @@ +// DESCRIPTION: Verilator: Verilog Test module + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [63:0] d; + reg [31:0] c; + + wire [31:0] q = crc (d, c); + reg [31:0] q_r; + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + q_r <= q; + c <= q; + d <= {d[62:0], ^d[63:48]}; + //$write("%d crc(%x,%x)=%x\n", cyc, d, c, q); + if (cyc==1) begin + // Assign inputs randomly + q_r <= 32'h12345678; + c <= 32'h12345678; + d <= 64'hffffffff_ffffffff; + end + if (cyc==2) begin + d <= 64'hffffffff_ffffffff; + end + if (cyc==3) begin + d <= 64'hffffffff_ffffffff; + end + if (cyc==4) begin + d <= 64'h50183721_81a04b1a; + end + if (cyc==5) begin + end + if (cyc==9) begin + if (q !== 32'h38295e96) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + function [31:0] crc; + input [63:0] di; + input [31:0] ci; + reg [63:0] drev; + begin + drev = reverse(di); + crc = newcrc(drev, ci); + end + endfunction + + function [63:0] reverse; + input [63:0] di; + integer i; + begin + reverse = 64'b0; + for (i=0; i<64; i=i+1) reverse[i] = di[63-i]; + end + endfunction + + function [31:0] newcrc; + input [63:0] D; + input [31:0] C; + reg [31:0] N; + reg [31:0] DT; + begin + N = 32'b0; + // Note this isn't a real CRC code; it's been munged for privacy + N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0] + ^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1]; + N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0] + ^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0]; + N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11] + ^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7]; + N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0] + ^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1]; + N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0] + ^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2]; + N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1] + ^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1]; + N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1] + ^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0]; + N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0] + ^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4]; + N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2] + ^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6]; + N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7] + ^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1]; + N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1] + ^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2]; + N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1] + ^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1]; + N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2] + ^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6]; + N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11] + ^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9]; + N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0] + ^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1]; + N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2] + ^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5]; + N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1] + ^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6]; + N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0] + ^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0]; + N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7] + ^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0]; + N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2] + ^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0]; + N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1] + ^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4]; + N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1] + ^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2]; + N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3] + ^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5]; + N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3] + ^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1]; + N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0] + ^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0]; + N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2] + ^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6]; + N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0] + ^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1]; + N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2] + ^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3]; + N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0] + ^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0]; + N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0] + ^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0]; + N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0] + ^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0]; + N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0] + ^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2]; + newcrc = N; + end + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_default_warn.v b/SVIncCompil/Testcases/Verilator/t_func_default_warn.v new file mode 100644 index 0000000..3e555a0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_default_warn.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed +// default function argument +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +function logic foo + ( + // Intentionally provide a non-width'ed default value + // This should warn, not error out + input logic x = 0 + ); + return x; +endfunction + +module t (/*AUTOARG*/); + logic foo_val; + + initial begin + foo_val = foo(); + if (foo_val != 1'b0) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_defaults.v b/SVIncCompil/Testcases/Verilator/t_func_defaults.v new file mode 100644 index 0000000..5e3b601 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_defaults.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed +// default function argument +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +parameter logic Bar = 1'b1; + +function automatic logic calc_y; + return 1'b1; +endfunction + +function automatic logic [1:0] foo + ( + input logic x = Bar, + input logic y = calc_y() + ); + return x + y; +endfunction + +module t (/*AUTOARG*/); + logic [1:0] foo_val; + + initial begin + foo_val = foo(); + if (foo_val != 2'b10) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_dotted.v b/SVIncCompil/Testcases/Verilator/t_func_dotted.v new file mode 100644 index 0000000..df17433 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_dotted.v
@@ -0,0 +1,140 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + // verilator lint_off MULTIDRIVEN + + ma ma0 (); + + global_mod #(32'hf00d) global_cell (); + global_mod #(32'hf22d) global_cell2 (); + + input clk; + integer cyc=1; + + function [31:0] getName; input fake; getName = "t "; endfunction + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==2) begin + if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop; + if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop; + end + if (cyc==3) begin + if (ma0. getName(1'b0) !== "ma ") $stop; + if (ma0.mb0. getName(1'b0) !== "mb ") $stop; + if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop; + end + if (cyc==4) begin + if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop; + if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; + if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; + end + if (cyc==5) begin + ma0. checkName(ma0. getName(1'b0)); + ma0.mb0. checkName(ma0.mb0. getName(1'b0)); + ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +`ifdef USE_INLINE_MID + `define INLINE_MODULE /*verilator inline_module*/ + `define INLINE_MID_MODULE /*verilator no_inline_module*/ +`else + `ifdef USE_INLINE + `define INLINE_MODULE /*verilator inline_module*/ + `define INLINE_MID_MODULE /*verilator inline_module*/ + `else + `define INLINE_MODULE /*verilator public_module*/ + `define INLINE_MID_MODULE /*verilator public_module*/ + `endif +`endif + +module global_mod; + `INLINE_MODULE + parameter INITVAL = 0; + integer globali; + + initial globali = INITVAL; + function [31:0] getName; input fake; getName = "gmod"; endfunction + function [31:0] getGlob; input fake; getGlob = globali; endfunction +endmodule + +module ma (); + `INLINE_MODULE + + mb #(0) mb0 (); + reg [31:0] gName; initial gName = "ma "; + function [31:0] getName; input fake; getName = "ma "; endfunction + task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask + + initial begin + if (ma.getName(1'b0) !== "ma ") $stop; + if (mb0.getName(1'b0) !== "mb ") $stop; + if (mb0.mc0.getName(1'b0) !== "mc ") $stop; + end +endmodule + +module mb (); + `INLINE_MID_MODULE + parameter P2 = 0; + + mc #(P2,0) mc0 (); + mc #(P2,1) mc1 (); + global_mod #(32'hf33d) global_cell2 (); + + reg [31:0] gName; initial gName = "mb "; + function [31:0] getName; input fake; getName = "mb "; endfunction + function [31:0] getP2 ; input fake; getP2 = P2; endfunction + task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask + + initial begin +`ifndef verilator #1; `endif + if (ma. getName(1'b0) !== "ma ") $stop; + if ( getName(1'b0) !== "mb ") $stop; + if (mc1.getName(1'b0) !== "mc ") $stop; + + ma. checkName (ma. gName); + /**/checkName ( gName); + mc1.checkName (mc1.gName); + ma. checkName (ma. getName(1'b0)); + /**/checkName ( getName(1'b0)); + mc1.checkName (mc1.getName(1'b0)); + end +endmodule + +module mc (); + `INLINE_MODULE + parameter P2 = 0; + parameter P3 = 0; + + reg [31:0] gName; initial gName = "mc "; + function [31:0] getName; input fake; getName = "mc "; endfunction + function [31:0] getP3 ; input fake; getP3 = P3; endfunction + task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask + + initial begin +`ifndef verilator #1; `endif + if (ma.getName(1'b0) !== "ma ") $stop; + if (mb.getName(1'b0) !== "mb ") $stop; + if (mc.getName(1'b0) !== "mc ") $stop; + ma.checkName (ma.gName); + mb.checkName (mb.gName); + mc.checkName (mc.gName); + ma.checkName (ma.getName(1'b0)); + mb.checkName (mb.getName(1'b0)); + mc.checkName (mc.getName(1'b0)); + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_endian.v b/SVIncCompil/Testcases/Verilator/t_func_endian.v new file mode 100644 index 0000000..1fe1d3f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_endian.v
@@ -0,0 +1,98 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + wire noswap = crc[32]; + wire nibble = crc[33]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .noswap (noswap), + .nibble (nibble), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h89522c3f5e5ca324) $stop; + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, noswap, nibble, in + ); + input clk; + + input noswap; + input nibble; + + input [31:0] in; + output [31:0] out; + + function [7:0] EndianSwap; + input Nibble; + input [7:0] Data; + begin + EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], + Data[4], Data[5], Data[6], Data[7] } + : { 4'h0, Data[0], Data[1], Data[2], Data[3] }); + end + endfunction + + assign out[31:24] = (noswap ? in[31:24] + : EndianSwap(nibble, in[31:24])); + assign out[23:16] = (noswap ? in[23:16] + : EndianSwap(nibble, in[23:16])); + assign out[15:8] = (noswap ? in[15:8] + : EndianSwap(nibble, in[15:8])); + assign out[7:0] = (noswap ? in[7:0] + : EndianSwap(nibble, in[7:0])); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_first.v b/SVIncCompil/Testcases/Verilator/t_func_first.v new file mode 100644 index 0000000..1ee1f80 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_first.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg [7:0] cyc; initial cyc=0; + reg set_in_task; + + always @ (posedge clk) begin + if (cyc == 8'd0) begin + cyc <= 8'd1; + set_in_task <= 0; + end + if (cyc == 8'd1) begin + cyc <= 8'h2; + ttask; + end + if (cyc == 8'd2) begin + if (!set_in_task) $stop; + cyc <= 8'hf; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + task ttask; + begin + set_in_task <= 1'b1; + end + endtask + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_flip.v b/SVIncCompil/Testcases/Verilator/t_func_flip.v new file mode 100644 index 0000000..3628599 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_flip.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +`define INT_RANGE 31:0 +`define INT_RANGE 31:0 // Duplicate identical defs are OK +`define INT_RANGE_MAX 31 +`define VECTOR_RANGE 511:0 + +module t (clk); + + // verilator lint_off WIDTH + + parameter WIDTH = 16; // Must be a power of 2 + parameter WIDTH_LOG2 = 4; // set to log2(WIDTH) + parameter USE_BS = 1; // set to 1 for enable + + input clk; + + function [`VECTOR_RANGE] func_tree_left; + input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector + reg [`VECTOR_RANGE] flip; + begin + flip = 'd0; + func_tree_left = flip; + end + endfunction + + reg [WIDTH-1:0] a; // value to be shifted + reg [WIDTH-1:0] tree_left; + always @(a) begin : barrel_shift + tree_left = func_tree_left (a); + end // barrel_shift + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a = 5; + end + if (cyc==2) begin + $display ("%x\n",tree_left); + //if (tree_left != 'd15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_gen.v b/SVIncCompil/Testcases/Verilator/t_func_gen.v new file mode 100644 index 0000000..d5ef80e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_gen.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2012 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + genvar g; + logic [1:0] mask = 0; + generate + for (g=0; g<2; g++) + begin : picker + logic block_passed = 0; // Just for visualizing V3LinkDot debug + function [3:0] pick; + input [3:0] randnum; + pick = randnum+g[3:0]; + endfunction + always @(posedge clk) begin + if (pick(3)!=3+g[3:0]) $stop; + else mask[g] = 1'b1; + if (mask == 2'b11) begin // All iterations must be finished + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_graphcirc.v b/SVIncCompil/Testcases/Verilator/t_func_graphcirc.v new file mode 100644 index 0000000..bc28e5b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_graphcirc.v
@@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (clk); + input clk; + + integer cyc; initial cyc=0; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + ReadContDisps; + end + else if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end +`ifndef verilator + DispContDisps; +`endif + end + + task ReadContDisps; + begin + $display("%m: Here: %d", cyc); + end + endtask + + integer dindex; + + task DispContDisps; + /* verilator public */ + begin + if (cyc >= 2) begin + if ( cyc >= 4 ) begin + dindex = dindex + 2; //*** Error line + $display("%m: DIndex increment %d", cyc); +`ifdef VERILATOR + $c("VL_PRINTF(\"Hello1?\\n\");"); +`endif + end +`ifdef VERILATOR + $c("VL_PRINTF(\"Hello2?\\n\");"); + $c("VL_PRINTF(\"Hello3?\\n\");"); +`endif + end + end + endtask + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_grey.v b/SVIncCompil/Testcases/Verilator/t_func_grey.v new file mode 100644 index 0000000..fac1346 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_grey.v
@@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + // surefire lint_off _NETNM + // surefire lint_off STMINI + + input clk; + integer _mode; initial _mode = 0; + + wire [2:0] b3; reg [2:0] g3; + wire [5:0] b6; reg [5:0] g6; + + t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3)); + t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6)); + + always @ (posedge clk) begin + if (_mode==0) begin + _mode <= 1; + g3 <= 3'b101; + g6 <= 6'b110101; + end + else if (_mode==1) begin + if (b3 !== 3'b110) $stop; + if (b6 !== 6'b100110) $stop; + _mode <= 2; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +// Module gray2bin +// convert an arbitrary width gray coded number to binary. The conversion +// of a 4 bit gray (represented as "g") to binary ("b") would go as follows: +// b[3] = ^g[3] = g[3] +// b[2] = ^g[3:2] +// b[1] = ^g[3:1] +// b[0] = ^g[3:[SZ-1:0] cur0] + +module t_func_grey2bin (/*AUTOARG*/ + // Outputs + b, + // Inputs + g + ); + + // surefire lint_off STMFOR + + parameter SZ = 5; + output [SZ-1:0] b; + input [SZ-1:0] g; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [SZ-1:0] b; + // End of automatics + + integer i; + always @(/*AUTOSENSE*/g) + for (i=0; i<SZ; i=i+1) + b[i] = ^(g >> i); // surefire lint_off_line LATASS + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_lib.v b/SVIncCompil/Testcases/Verilator/t_func_lib.v new file mode 100644 index 0000000..cd5d555 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_lib.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_lib_sub.v b/SVIncCompil/Testcases/Verilator/t_func_lib_sub.v new file mode 100644 index 0000000..fcc8cc7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_lib_sub.v
@@ -0,0 +1,100 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +`define zednkw 200 + +module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr); +input zfghtn; +input [4:0] cjtmau; +input vipmpg; +input [7:0] knquim; +input [7:0] kqxkkr; + +reg covfok; + +reg [15:0] xwieqw; +reg [2:0] ofnjjt; + +reg [37:0] hdsejo[1:0]; + +reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq; +reg vrqrih, ryyjxy; +reg fgzsox; + +wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr; +wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10]; +wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10]; +wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr; +wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr; + +wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1); +wire smxixw = vrqrih | (ryyjxy & ktsveg); + +wire [7:0] grvsrs, kyxrft, uxhkka; + +wire [7:0] eianuv = 8'h01 << ofnjjt; +wire [7:0] jvpnxn = {8{qnpfus}} & eianuv; +wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv; +wire [7:0] nahzat = {8{iytyol}} & eianuv; + +genvar i; +generate + for (i=0;i<8;i=i+1) + begin : dnlpyw + DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i], + knquim[3:0], covfok, grvsrs[i]); + DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i], + knquim[7:4], covfok, kyxrft[i]); + DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i], + kqxkkr[3:0], covfok, uxhkka[i]); + end +endgenerate + +endmodule + +module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh); +input clk, fgzsox, fckiyr, covfok; +input [3:0] uezcjy; +output juvlsh; + +task Xinit; +begin +`ifdef TEST_HARNESS + khgawe = 1'b0; +`endif +end +endtask +function X; +input vrdejo; +begin +`ifdef TEST_HARNESS + if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1; +`endif + X = vrdejo; +end +endfunction +task Xcheck; +input vzpwwy; +begin +end +endtask + +reg [3:0] udbvtl; + +assign juvlsh = |udbvtl; +wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1)); + +wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox; + +always @(posedge clk) +begin + Xinit; + if (X(qqibou)) + udbvtl <= #`zednkw mppedc; + + Xcheck(fgzsox); +end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_mlog2.v b/SVIncCompil/Testcases/Verilator/t_func_mlog2.v new file mode 100644 index 0000000..bddb2c8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_mlog2.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2008 by Wilson Snyder. + +module t (clk); + input clk; + + integer cyc; initial cyc=1; + integer sum; + integer cpre; + always @ (posedge clk) begin + if (cyc!=0) begin + cpre = cyc; + cyc <= cyc + 1; + if (cyc==1) begin + if (mlog2(32'd0) != 32'd0) $stop; + if (mlog2(32'd1) != 32'd0) $stop; + if (mlog2(32'd3) != 32'd2) $stop; + sum <= 32'd0; + end + else if (cyc<90) begin + // (cyc) so if we trash the variable things will get upset. + sum <= mlog2(cyc) + sum * 32'd42; + if (cpre != cyc) $stop; + end + else if (cyc==90) begin + if (sum !== 32'h0f12bb51) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + function integer mlog2; + input [31:0] value; + integer i; + begin + if(value < 32'd1) begin + mlog2 = 0; + end + else begin + value = value - 32'd1; + mlog2 = 0; + for(i=0;i<32;i=i+1) begin + if(value > 32'd0) begin + mlog2 = mlog2 + 1; + end + value = value >> 1; + end + end + end + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_named.v b/SVIncCompil/Testcases/Verilator/t_func_named.v new file mode 100644 index 0000000..f51fd99 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_named.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/); + + function int f( int j = 1, int s = 0 ); + return (j<<16) | s; + endfunction + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + + initial begin + `checkh( f(.j(2), .s(1)) , 32'h2_0001 ); + `checkh( f(.s(1)) , 32'h1_0001 ); + `checkh( f(, 1) , 32'h1_0001 ); + `checkh( f(.j(2)) , 32'h2_0000 ); + `checkh( f(.s(1), .j(2)) , 32'h2_0001 ); + `checkh( f(.s(), .j()) , 32'h1_0000 ); + `checkh( f(2) , 32'h2_0000 ); + `checkh( f() , 32'h1_0000 ); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_noinl.v b/SVIncCompil/Testcases/Verilator/t_func_noinl.v new file mode 100644 index 0000000..4b6e40e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_noinl.v
@@ -0,0 +1,115 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [31:0] inp = crc[31:0]; + wire reset = (cyc < 5); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] outp; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .outp (outp[31:0]), + // Inputs + .reset (reset), + .clk (clk), + .inp (inp[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, outp}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'ha7f0a34f9cf56ccb + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + outp, + // Inputs + reset, clk, inp + ); + + input reset; + input clk; + input [31:0] inp; + output [31:0] outp; + + function [31:0] no_inline_function; + input [31:0] var1; + input [31:0] var2; + /*verilator no_inline_task*/ + reg [31*2:0] product1 ; + reg [31*2:0] product2 ; + integer i; + reg [31:0] tmp; + + begin + product2 = {(31*2+1){1'b0}}; + + for (i = 0; i < 32; i = i + 1) + if (var2[i]) begin + product1 = { {31*2+1-32{1'b0}}, var1} << i; + product2 = product2 ^ product1; + end + no_inline_function = 0; + + for (i= 0; i < 31; i = i + 1 ) + no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; + end + endfunction + + reg [31:0] outp; + reg [31:0] inp_d; + + always @( posedge clk ) begin + if( reset ) begin + outp <= 0; + end + else begin + inp_d <= inp; + outp <= no_inline_function(inp, inp_d); + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_numones.v b/SVIncCompil/Testcases/Verilator/t_func_numones.v new file mode 100644 index 0000000..e47fa50 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_numones.v
@@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + + reg [31:0] r32; + wire [3:0] w4; + wire [4:0] w5; + + assign w4 = NUMONES_8 ( r32[7:0] ); + assign w5 = NUMONES_16( r32[15:0] ); + + function [3:0] NUMONES_8; + input [7:0] i8; + reg [7:0] i8; + begin + NUMONES_8 = 4'b1; + end + endfunction // NUMONES_8 + + function [4:0] NUMONES_16; + input [15:0] i16; + reg [15:0] i16; + begin + NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] )); + end + endfunction + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + r32 <= 32'h12345678; + end + if (cyc==2) begin + if (w4 !== 1) $stop; + if (w5 !== 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_outfirst.v b/SVIncCompil/Testcases/Verilator/t_func_outfirst.v new file mode 100644 index 0000000..14d72b4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_outfirst.v
@@ -0,0 +1,113 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +`define DDIFF_BITS 9 +`define AOA_BITS 8 +`define HALF_DDIFF `DDIFF_BITS'd256 +`define MAX_AOA `AOA_BITS'd255 +`define BURP_DIVIDER 9'd16 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0]; + wire reset = (cyc<7); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .AOA_B (AOA_B[`AOA_BITS-1:0]), + // Inputs + .DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]), + .reset (reset), + .clk (clk)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {56'h0, AOA_B}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h3a74e9d34771ad93 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + AOA_B, + // Inputs + DDIFF_B, reset, clk + ); + + input [`DDIFF_BITS-1:0] DDIFF_B; + input reset; + input clk; + output reg [`AOA_BITS-1:0] AOA_B; + + reg [`AOA_BITS-1:0] AOA_NEXT_B; + reg [`AOA_BITS-1:0] tmp; + + always @(posedge clk) begin + if (reset) begin + AOA_B <= 8'h80; + end + else begin + AOA_B <= AOA_NEXT_B; + end + end + + always @* begin + // verilator lint_off WIDTH + tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER); + t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER)); + // verilator lint_on WIDTH + end + + task t_aoa_update; + output [`AOA_BITS-1:0] aoa_reg_next; + input [`AOA_BITS-1:0] aoa_reg; + input [`AOA_BITS-1:0] aoa_delta_update; + begin + if ((`MAX_AOA-aoa_reg)<aoa_delta_update) //Overflow protection + aoa_reg_next=`MAX_AOA; + else + aoa_reg_next=aoa_reg+aoa_delta_update; + end + endtask +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_outp.v b/SVIncCompil/Testcases/Verilator/t_func_outp.v new file mode 100644 index 0000000..e0d6651 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_outp.v
@@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + + input clk; + + reg [7:0] a,b; + wire [7:0] z; + + mytop u0 ( a, b, clk, z ); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x\n", cyc, z); + if (cyc==1) begin + a <= 8'h07; + b <= 8'h20; + end + if (cyc==2) begin + a <= 8'h8a; + b <= 8'h12; + end + if (cyc==3) begin + if (z !== 8'hdf) $stop; + a <= 8'h71; + b <= 8'hb2; + end + if (cyc==4) begin + if (z !== 8'hed) $stop; + end + if (cyc==5) begin + if (z !== 8'h4d) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule // mytop + +module inv( + input [ 7:0 ] a, + output wire [ 7:0 ] z + ); + assign z = ~a; +endmodule + + +module ftest( + input [ 7:0 ] a, + b, // Test legal syntax + input clk, + output reg [ 7:0 ] z + ); + + wire [7:0] zi; + + inv u1 (.a(myadd(a,b)), + .z(zi)); + + + always @ ( posedge clk ) begin + z <= myadd( a, zi ); + end + + function [ 7:0 ] myadd; + input [7:0] ina; + input [7:0] inb; + + begin + myadd = ina + inb; + end + endfunction // myadd + +endmodule // ftest + +module mytop ( + input [ 7:0 ] a, + b, + input clk, + output [ 7:0 ] z + ); + + ftest u0( a, b, clk, z ); + +endmodule // mytop
diff --git a/SVIncCompil/Testcases/Verilator/t_func_paramed.v b/SVIncCompil/Testcases/Verilator/t_func_paramed.v new file mode 100644 index 0000000..c9ccf9b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_paramed.v
@@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [11:0] in_a; + reg [31:0] sel; + wire [2:0] out_x; + + extractor #(4,3) extractor ( + // Outputs + .out (out_x), + // Inputs + .in (in_a), + .sel (sel)); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, in_a, sel, out_x); + if (cyc==1) begin + in_a <= 12'b001_101_111_010; + sel <= 32'd0; + end + if (cyc==2) begin + sel <= 32'd1; + if (out_x != 3'b010) $stop; + end + if (cyc==3) begin + sel <= 32'd2; + if (out_x != 3'b111) $stop; + end + if (cyc==4) begin + sel <= 32'd3; + if (out_x != 3'b101) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +module extractor (/*AUTOARG*/ + // Outputs + out, + // Inputs + in, sel + ); + parameter IN_WIDTH=8; + parameter OUT_WIDTH=2; + + input [IN_WIDTH*OUT_WIDTH-1:0] in; + output [OUT_WIDTH-1:0] out; + input [31:0] sel; + + wire [OUT_WIDTH-1:0] out = selector(in,sel); + + function [OUT_WIDTH-1:0] selector; + input [IN_WIDTH*OUT_WIDTH-1:0] inv; + input [31:0] selv; + integer i; + begin + selector = 0; + for (i=0; i<OUT_WIDTH; i=i+1) begin + selector[i] = inv[selv*OUT_WIDTH+i]; + end + end + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_plog.v b/SVIncCompil/Testcases/Verilator/t_func_plog.v new file mode 100644 index 0000000..fe3b9f9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_plog.v
@@ -0,0 +1,102 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + reg rst_n; + + // Take CRC data and apply to testblock inputs + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [2:0] pos1; // From test of Test.v + wire [2:0] pos2; // From test of Test.v + // End of automatics + + Test test ( + // Outputs + .pos1 (pos1[2:0]), + .pos2 (pos2[2:0]), + /*AUTOINST*/ + // Inputs + .clk (clk), + .rst_n (rst_n)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {61'h0, pos1}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h039ea4d039c2e70b + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + rst_n <= ~1'b0; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + rst_n <= ~1'b1; + end + else if (cyc<10) begin + sum <= 64'h0; + rst_n <= ~1'b1; + end + else if (cyc<90) begin + if (pos1 !== pos2) $stop; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + #(parameter SAMPLE_WIDTH = 5 ) + ( +`ifdef verilator // Some simulators don't support clog2 + output reg [$clog2(SAMPLE_WIDTH)-1:0] pos1, +`else + output reg [log2(SAMPLE_WIDTH-1)-1:0] pos1, +`endif + output reg [log2(SAMPLE_WIDTH-1)-1:0] pos2, + // System + input clk, + input rst_n + ); + + function integer log2(input integer arg); + begin + for(log2=0; arg>0; log2=log2+1) + arg = (arg >> 1); + end + endfunction + + always @ (posedge clk or negedge rst_n) + if (!rst_n) begin + pos1 <= 0; + pos2 <= 0; + end + else begin + pos1 <= pos1 + 1; + pos2 <= pos2 + 1; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_public.v b/SVIncCompil/Testcases/Verilator/t_func_public.v new file mode 100644 index 0000000..6b3da7b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_public.v
@@ -0,0 +1,228 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + tpub p1 (.clk(clk), .i(32'd1)); + tpub p2 (.clk(clk), .i(32'd2)); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin +`ifdef verilator + $c("publicTop();"); +`endif + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + task publicTop; + // verilator public + // We have different optimizations if only one of something, so try it out. + $write("Hello in publicTop\n"); + endtask + +endmodule + +module tpub ( + input clk, + input [31:0] i); + + reg [23:0] var_long; + reg [59:0] var_quad; + reg [71:0] var_wide; + reg var_bool; + + // verilator lint_off BLKANDNBLK + reg [11:0] var_flop; + // verilator lint_on BLKANDNBLK + + reg [23:0] got_long /*verilator public*/; + reg [59:0] got_quad /*verilator public*/; + reg [71:0] got_wide /*verilator public*/; + reg got_bool /*verilator public*/; + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + // cyc==1 is in top level + if (cyc==2) begin + publicNoArgs; + publicSetBool(1'b1); + publicSetLong(24'habca); + publicSetQuad(60'h4444_3333_2222); + publicSetWide(72'h12_5678_9123_1245_2352); + var_flop <= 12'habe; + end + if (cyc==3) begin + if (1'b1 != publicGetSetBool(1'b0)) $stop; + if (24'habca != publicGetSetLong(24'h1234)) $stop; + if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop; + if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop; + end + if (cyc==4) begin + publicGetBool(got_bool); + if (1'b0 != got_bool) $stop; + publicGetLong(got_long); + if (24'h1234 != got_long) $stop; + publicGetQuad(got_quad); + if (60'h123_4567_89ab != got_quad) $stop; + publicGetWide(got_wide); + if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; + end + // +`ifdef VERILATOR_PUBLIC_TASKS + if (cyc==11) begin + $c("publicNoArgs();"); + $c("publicSetBool(true);"); + $c("publicSetLong(0x11bca);"); + $c("publicSetQuad(VL_ULL(0x66655554444));"); + $c("publicSetFlop(0x321);"); + //Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);"); + end + if (cyc==12) begin + $c("got_bool = publicGetSetBool(true);"); + $c("got_long = publicGetSetLong(0x11bca);"); + $c("got_quad = publicGetSetQuad(VL_ULL(0xaaaabbbbcccc));"); + end + if (cyc==13) begin + $c("{ bool gb; publicGetBool(gb); got_bool=gb; }"); + if (1'b1 != got_bool) $stop; + $c("publicGetLong(got_long);"); + if (24'h11bca != got_long) $stop; + $c("{ vluint64_t qq; publicGetQuad(qq); got_quad=qq; }"); + if (60'haaaa_bbbb_cccc != got_quad) $stop; + $c("{ WData gw[3]; publicGetWide(gw); VL_ASSIGN_W(72,got_wide,gw); }"); + if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; + //Below doesn't work, because we're calling it inside the loop that sets var_flop + // if (12'h321 != var_flop) $stop; + end + if (cyc==14) begin + if ($c32("publicInstNum()") != i) $stop; + end +`endif + end + end + + task publicEmpty; + // verilator public + begin end + endtask + + task publicNoArgs; + // verilator public + $write("Hello in publicNoArgs\n"); + endtask + + task publicSetBool; + // verilator public + input in_bool; + var_bool = in_bool; + endtask + + task publicSetLong; + // verilator public + input [23:0] in_long; + reg [23:0] not_long; + begin + not_long = ~in_long; // Test that we can have local variables + var_long = ~not_long; + end + endtask + + task publicSetQuad; + // verilator public + input [59:0] in_quad; + var_quad = in_quad; + endtask + + task publicSetFlop; + // verilator public + input [11:0] in_flop; + var_flop = in_flop; + endtask + + task publicSetWide; + // verilator public + input [71:0] in_wide; + var_wide = in_wide; + endtask + + task publicGetBool; + // verilator public + output out_bool; + out_bool = var_bool; + endtask + + task publicGetLong; + // verilator public + output [23:0] out_long; + out_long = var_long; + endtask + + task publicGetQuad; + // verilator public + output [59:0] out_quad; + out_quad = var_quad; + endtask + + task publicGetWide; + // verilator public + output [71:0] out_wide; + out_wide = var_wide; + endtask + + function publicGetSetBool; + // verilator public + input in_bool; + begin + publicGetSetBool = var_bool; + var_bool = in_bool; + end + endfunction + + function [23:0] publicGetSetLong; + // verilator public + input [23:0] in_long; + begin + publicGetSetLong = var_long; + var_long = in_long; + end + endfunction + + function [59:0] publicGetSetQuad; + // verilator public + input [59:0] in_quad; + begin + publicGetSetQuad = var_quad; + var_quad = in_quad; + end + endfunction + + function [71:0] publicGetSetWide; + // Can't be public, as no wide return types in C++ + input [71:0] in_wide; + begin + publicGetSetWide = var_wide; + var_wide = in_wide; + end + endfunction + +`ifdef VERILATOR_PUBLIC_TASKS + function [31:0] publicInstNum; + // verilator public + publicInstNum = i; + endfunction +`endif + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_rand.v b/SVIncCompil/Testcases/Verilator/t_func_rand.v new file mode 100644 index 0000000..0d525bb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_rand.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (clk, Rand); + input clk; + output reg [31:0] Rand; + +`ifdef verilator + `systemc_interface + unsigned int QxRandTbl (unsigned int tbl, unsigned int idx) { return 0xfeed0fad; } + `verilog +`endif + + function [31:0] QxRand32; + /* verilator public */ + input [7:0] tbl; + input [7:0] idx; + begin +`ifdef verilator + QxRand32 = $c ("QxRandTbl(",tbl,",",idx,")"); +`else + QxRand32 = 32'hfeed0fad; +`endif + end + endfunction + + always @(posedge clk) begin + Rand <= #1 QxRand32 (8'h0, 8'h7); + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_range.v b/SVIncCompil/Testcases/Verilator/t_func_range.v new file mode 100644 index 0000000..fc29e9e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_range.v
@@ -0,0 +1,63 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + // verilator lint_off WIDTH + +`define INT_RANGE 31:0 +`define INT_RANGE_MAX 31 +`define VECTOR_RANGE 63:0 + + reg [`INT_RANGE] stashb, stasha, stashn, stashm; + + function [`VECTOR_RANGE] copy_range; + input [`VECTOR_RANGE] y; + input [`INT_RANGE] b; + input [`INT_RANGE] a; + + input [`VECTOR_RANGE] x; + input [`INT_RANGE] n; + input [`INT_RANGE] m; + + begin + copy_range = y; + stashb = b; + stasha = a; + stashn = n; + stashm = m; + end + endfunction + + parameter DATA_SIZE = 16; + parameter NUM_OF_REGS = 32; + + reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; + reg [DATA_SIZE-1:0] memread_rf_reg; + always @(memread_rf) begin : memread_convert + memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, + DATA_SIZE-'d1, DATA_SIZE-'d1); + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + memread_rf = 512'haa; + end + if (cyc==3) begin + if (stashb != 'd15) $stop; + if (stasha != 'd15) $stop; + if (stashn != 'd15) $stop; + if (stashm != 'd15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_real_abs.v b/SVIncCompil/Testcases/Verilator/t_func_real_abs.v new file mode 100644 index 0000000..33719a7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_real_abs.v
@@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +//bug591 + +module t (/*AUTOARG*/); + + function real ABS (real num); + ABS = (num < 0) ? -num : num; + endfunction + + function logic range_chk; + input real last; + input real period; + input real cmp; + range_chk = 0; + if ( last >= 0 ) begin + if ( ABS(last - period) > cmp ) begin + range_chk = 1; + end + end + endfunction + + function integer ceil; + input num; + real num; + if (num > $rtoi(num)) + ceil = $rtoi(num) + 1; + else + // verilator lint_off REALCVT + ceil = num; + // verilator lint_on REALCVT + endfunction + + initial begin + if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop; + if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop; + if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop; + if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop; + if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop; + if (ceil(-2.1) != -2) $stop; + if (ceil(2.1) != 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_real_param.v b/SVIncCompil/Testcases/Verilator/t_func_real_param.v new file mode 100644 index 0000000..62c8a18 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_real_param.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// bug475 + +module t(); + + function real get_real_one; + input ignored; + get_real_one = 1.1; + endfunction + + localparam R_PARAM = get_real_one(1'b0); + localparam R_PARAM_2 = (R_PARAM > 0); + + generate + initial begin + if (R_PARAM != 1.1) $stop; + if (R_PARAM_2 != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_regfirst.v b/SVIncCompil/Testcases/Verilator/t_func_regfirst.v new file mode 100644 index 0000000..ca3e2dc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_regfirst.v
@@ -0,0 +1,77 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (clk); + input clk; + + reg [2:0] a; + reg [2:0] b; + reg q; + + f6 f6 (/*AUTOINST*/ + // Outputs + .q (q), + // Inputs + .a (a[2:0]), + .b (b[2:0]), + .clk (clk)); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 3'b000; + b <= 3'b100; + end + if (cyc==2) begin + a <= 3'b011; + b <= 3'b001; + if (q != 1'b0) $stop; + end + if (cyc==3) begin + a <= 3'b011; + b <= 3'b011; + if (q != 1'b0) $stop; + end + if (cyc==9) begin + if (q != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module f6 (a, b, clk, q); + input [2:0] a; + input [2:0] b; + input clk; + output q; + reg out; + + function func6; + reg result; + input [5:0] src; + begin + if (src[5:0] == 6'b011011) begin + result = 1'b1; + end + else begin + result = 1'b0; + end + func6 = result; + end + endfunction + + wire [5:0] w6 = {a, b}; + always @(posedge clk) begin + out <= func6(w6); + end + + assign q = out; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_return.v b/SVIncCompil/Testcases/Verilator/t_func_return.v new file mode 100644 index 0000000..8926ae8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_return.v
@@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +// bug420 +typedef logic [7-1:0] wb_ind_t; +typedef logic [7-1:0] id_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + + wire [6:0] out = line_wb_ind( in[6:0] ); + + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hc918fa0aa882a206 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + function wb_ind_t line_wb_ind( id_t id ); + if( id[$bits(id_t)-1] == 0 ) + return {2'b00, id[$bits(wb_ind_t)-3:0]}; + else + return {2'b01, id[$bits(wb_ind_t)-3:0]}; + endfunction // line_wb_ind + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_sum.v b/SVIncCompil/Testcases/Verilator/t_func_sum.v new file mode 100644 index 0000000..5a652a9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_sum.v
@@ -0,0 +1,92 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008-2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [9:0] I1 = crc[9:0]; + wire [9:0] I2 = crc[19:10]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [9:0] S; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .S (S[9:0]), + // Inputs + .I1 (I1[9:0]), + .I2 (I2[9:0])); + + wire [63:0] result = {32'h0, 22'h0, S}; + +`define EXPECTED_SUM 64'h24c38b77b0fcc2e7 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + S, + // Inputs + I1, I2 + ); + + input [9:0] I1/*verilator public*/; + input [9:0] I2/*verilator public*/; + output reg [9:0] S/*verilator public*/; + + always @(I1 or I2) + t2(I1,I2,S); + + task t1; + input In1,In2; + output Sum; + Sum = In1 ^ In2; + endtask + + task t2; + input[9:0] In1,In2; + output [9:0] Sum; + integer I; + begin + for (I=0;I<10;I=I+1) + t1(In1[I],In2[I],Sum[I]); + end + endtask +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_task_bad.v b/SVIncCompil/Testcases/Verilator/t_func_task_bad.v new file mode 100644 index 0000000..c1623fd --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_task_bad.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/); + + initial begin + if (task_as_func(1'b0)) $stop; + end + + task task_as_func; + input ign; + endtask + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_tie_bad.v b/SVIncCompil/Testcases/Verilator/t_func_tie_bad.v new file mode 100644 index 0000000..350a5e3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_tie_bad.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/); + + initial begin + // verilator lint_off IGNOREDRETURN + func(0, 1'b1); + end + + function automatic int func + ( + input int a, + output bit b ); + return 0; + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_twocall.v b/SVIncCompil/Testcases/Verilator/t_func_twocall.v new file mode 100644 index 0000000..324166c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_twocall.v
@@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (clk); + input clk; + + reg [7:0] crc; + + wire [61:59] ah = crc[5:3]; + wire [61:59] bh = ~crc[4:2]; + wire [41:2] al = {crc,crc,crc,crc,crc}; + wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]}; + reg sel; + + wire [61:28] q = ( sel + ? func(ah, al) + : func(bh, bl)); + + function [61:28] func; + input [61:59] inh; + input [41:2] inl; + reg [42:28] func_mid; + reg carry; + begin + carry = &inl[27:2]; + func_mid = {1'b0,inl[41:28]} + {14'b0, carry}; + func[61:59] = inh + {2'b0, func_mid[42]}; + func[58:42] = {17{func_mid[41]}}; + func[41:28] = func_mid[41:28]; + end + endfunction + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + //$write("%d %x\n", cyc, q); + if (cyc!=0) begin + cyc <= cyc + 1; + sel <= ~sel; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==1) begin + sel <= 1'b1; + crc <= 8'h12; + end + if (cyc==2) if (q!=34'h100000484) $stop; + if (cyc==3) if (q!=34'h37fffeddb) $stop; + if (cyc==4) if (q!=34'h080001212) $stop; + if (cyc==5) if (q!=34'h1fffff7ef) $stop; + if (cyc==6) if (q!=34'h200000848) $stop; + if (cyc==7) if (q!=34'h380001ebd) $stop; + if (cyc==8) if (q!=34'h07fffe161) $stop; + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_types.v b/SVIncCompil/Testcases/Verilator/t_func_types.v new file mode 100644 index 0000000..9ee81c3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_types.v
@@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + + function int int123(); int123 = 32'h123; endfunction + + function bit f_bit ; input bit i; f_bit = ~i; endfunction + function int f_int ; input int i; f_int = ~i; endfunction + function byte f_byte ; input byte i; f_byte = ~i; endfunction + function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction + function longint f_longint ; input longint i; f_longint = ~i; endfunction + function chandle f_chandle ; input chandle i; f_chandle = i; endfunction + + // Note there's no "input" here vvvv, it's the default + function bit g_bit (bit i); g_bit = ~i; endfunction + function int g_int (int i); g_int = ~i; endfunction + function byte g_byte (byte i); g_byte = ~i; endfunction + function shortint g_shortint(shortint i); g_shortint = ~i; endfunction + function longint g_longint (longint i); g_longint = ~i; endfunction + function chandle g_chandle (chandle i); g_chandle = i; endfunction + + chandle c; + + initial begin + + if (int123() !== 32'h123) $stop; + + if (f_bit(1'h1) !== 1'h0) $stop; + if (f_bit(1'h0) !== 1'h1) $stop; + if (f_int(32'h1) !== 32'hfffffffe) $stop; + if (f_byte(8'h1) !== 8'hfe) $stop; + if (f_shortint(16'h1) !== 16'hfffe) $stop; + if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop; + if (f_chandle(c) !== c) $stop; + + if (g_bit(1'h1) !== 1'h0) $stop; + if (g_bit(1'h0) !== 1'h1) $stop; + if (g_int(32'h1) !== 32'hfffffffe) $stop; + if (g_byte(8'h1) !== 8'hfe) $stop; + if (g_shortint(16'h1) !== 16'hfffe) $stop; + if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop; + if (g_chandle(c) !== c) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_under.v b/SVIncCompil/Testcases/Verilator/t_func_under.v new file mode 100644 index 0000000..ec7d7e6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_under.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [3:0] counter = 0; + integer l2; + function log2 (input [3:0] x); + integer log2 = (x < 2) ? 1 : (x < 4) ? 2 : (x < 8) ? 3 : 4; + endfunction + always @(posedge clk) begin + counter <= counter + 1; + l2 <= log2(counter); + // bug589: This failed with (%Error: Internal Error: Function not underneath a statement): + $display("log2(%d) == %d", counter, log2(counter)); + // + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_under2.v b/SVIncCompil/Testcases/Verilator/t_func_under2.v new file mode 100644 index 0000000..ad54fe4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_under2.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// bug598 + +module t (/*AUTOARG*/ + // Outputs + val, + // Inputs + clk + ); + + input clk; + output integer val; + integer dbg_addr = 0; + + function func1; + input en; + input [31:0] a; + func1 = en && (a == 1); + endfunction + + function func2; + input en; + input [31:0] a; + func2 = en && (a == 2); + endfunction + + always @(posedge clk) begin + case( 1'b1 ) + // This line is OK: + func1(1'b1, dbg_addr) : val = 1; + // This fails: + // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement + // %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance. + func2(1'b1, dbg_addr) : val = 2; + default : val = 0; + endcase + // + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_unit.v b/SVIncCompil/Testcases/Verilator/t_func_unit.v new file mode 100644 index 0000000..14d533f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_unit.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +task tsk(output fo); + assign fo = 1'b0; +endtask + +module t (/*AUTOARG*/ + // Outputs + to + ); + output to[2:0]; + + integer i = 0; + + initial begin + tsk(to[i]); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_v.v b/SVIncCompil/Testcases/Verilator/t_func_v.v new file mode 100644 index 0000000..7f65b60 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_v.v
@@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Chandan Egbert. + +// See bug569 + +module t(); +`ifdef T_FUNC_V_NOINL + // verilator no_inline_module +`endif + level1 ul1(); + initial ul1.doit(4'b0); +endmodule + +module level1(); +`ifdef T_FUNC_V_NOINL + // verilator no_inline_module +`endif + level2 ul2(); + + task doit(input logic [3:0] v); + ul2.mem = v; + $write("*-* All Finished *-*\n"); + $finish; + endtask +endmodule + +module level2(); +`ifdef T_FUNC_V_NOINL + // verilator no_inline_module +`endif + logic [3:0] mem; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_void.v b/SVIncCompil/Testcases/Verilator/t_func_void.v new file mode 100644 index 0000000..4241c57 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_void.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + int side_effect; + + function int f1; + input int in; + f1 = in + 1; + side_effect += in + 1; + endfunction + + initial begin + int got; + side_effect = 1; + // + got = f1(10); + if (got != 11) $stop; + if (side_effect != 12) $stop; + // verilator lint_off IGNOREDRETURN + f1(20); + // verilator lint_on IGNOREDRETURN + if (side_effect != 33) $stop; + // + void'(f1(30)); + if (side_effect != 64) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_void_bad.v b/SVIncCompil/Testcases/Verilator/t_func_void_bad.v new file mode 100644 index 0000000..228d520 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_void_bad.v
@@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + int side_effect; + + function int f1; + input int in; + f1 = in + 1; + side_effect += in + 1; + endfunction + + initial begin + int got; + side_effect = 1; + // + got = f1(10); + if (got != 11) $stop; + if (side_effect != 12) $stop; + // + f1(20); + if (side_effect != 33) $stop; + // +// void'f1(30); +// if (side_effect != 64) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_while.v b/SVIncCompil/Testcases/Verilator/t_func_while.v new file mode 100644 index 0000000..1591d05 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_while.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Julien Margetts. + +module t #(parameter sz = 4096) + ( + input wire clk, + output reg [tdw(sz)-1:0] data + ); + + // bug1330 + function integer clog2(input integer value); + integer tmp; + tmp = value-1; + clog2 = 0; + for (clog2=0; (tmp>0) && (clog2<32); clog2=clog2+1) + tmp = tmp>>1; + endfunction + + function integer tdw(input integer sz); + tdw = clog2(sz); + endfunction + + integer b; + + always @(posedge clk) + for (b=0; b<tdw(sz); b=b+1) + if ((data[b] === 1'bx)) + $display("WARNING: %1t Writing X's to tag RAM [%m]", $time); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_wide.v b/SVIncCompil/Testcases/Verilator/t_func_wide.v new file mode 100644 index 0000000..b7e398e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_wide.v
@@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + reg [43:0] mi; + wire [31:0] mo; + muxtop um ( mi, mo); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + mi <= 44'h1234567890; + end + if (cyc==3) begin + if (mo !== 32'h12345678) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module muxtop ( + input [ 43:0 ] i, + output reg [ 31:0 ] o + ); + + always @ ( i[43:0] ) // Verify we ignore ranges on always statement sense lists + o = MUX( i[39:0] ); + + function [31:0] MUX; + input [39:0] XX ; + begin + MUX = XX[39:8]; + end + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_func_wide_out_bad.v b/SVIncCompil/Testcases/Verilator/t_func_wide_out_bad.v new file mode 100644 index 0000000..6bf3a7e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_func_wide_out_bad.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (); + + parameter MSG_PORT_WIDTH = 4350; + localparam PAYLOAD_MAX_BITS = 4352; + + reg [MSG_PORT_WIDTH-1:0] msg; + + initial begin + // Operator TASKREF 'func' expects 4352 bits on the Function Argument, but Function Argument's VARREF 'msg' generates 4350 bits. + // verilator lint_off WIDTH + func(msg); + // verilator lint_on WIDTH + if (msg !== {MSG_PORT_WIDTH{1'b1}}) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + + function integer func (output bit [PAYLOAD_MAX_BITS-1:0] data); + /*verilator no_inline_task*/ + data = {PAYLOAD_MAX_BITS{1'b1}}; + return (1); + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gate_array.v b/SVIncCompil/Testcases/Verilator/t_gate_array.v new file mode 100644 index 0000000..6fcf23c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gate_array.v
@@ -0,0 +1,88 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [7:0] a = crc[7:0]; + wire [7:0] b = crc[15:8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[63:0]), + // Inputs + .clk (clk), + .a (a[7:0]), + .b (b[7:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h0908a1f2194d24ee + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, a, b + ); + + input clk; + input [7:0] a; + input [7:0] b; + output reg [63:0] out; + + and u0[7:0] (out[7:0], a[7:0], b[7:0]); + and u1[7:0] (out[15:8], a[0], b[7:0]); + and u2[7:0] (out[23:16], a[0], b[0]); + nand u3[7:0] (out[31:24], a[0], b[7:0]); + or u4[7:0] (out[39:32], a[0], b[7:0]); + nor u5[7:0] (out[47:40], a[0], b[7:0]); + xor u6[7:0] (out[55:48], a[0], b[7:0]); + xnor u7[7:0] (out[63:56], a[0], b[7:0]); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gate_basic.v b/SVIncCompil/Testcases/Verilator/t_gate_basic.v new file mode 100644 index 0000000..4d5e87c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gate_basic.v
@@ -0,0 +1,90 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [31:0] a; + reg [31:0] b; + + wire [2:0] bf; buf BF0 (bf[0], a[0]), + BF1 (bf[1], a[1]), + BF2 (bf[2], a[2]); + + // verilator lint_off IMPLICIT + not #(0.108) NT0 (nt0, a[0]); + and #1 AN0 (an0, a[0], b[0]); + nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); + or OR0 (or0, a[0], b[0]); + nor NR0 (nr0, a[0], b[0], b[2]); + xor (xo0, a[0], b[0]); + xnor (xn0, a[0], b[0], b[2]); + // verilator lint_on IMPLICIT + + parameter BITS=32; + wire [BITS-1:0] ba; + buf BARRAY [BITS-1:0] (ba, a); + +`ifdef verilator + specify + specparam CDS_LIBNAME = "foobar"; + (nt0 *> nt0) = (0, 0); + endspecify + + specify + // delay parameters + specparam + a$A1$Y = 1.0, + b$A0$Z = 1.0; + + // path delays + (A1 *> Q) = (a$A1$Y, a$A1$Y); + (A0 *> Q) = (b$A0$Y, a$A0$Z); + endspecify +`endif + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 32'h18f6b034; + b <= 32'h834bf892; + end + if (cyc==2) begin + a <= 32'h529ab56f; + b <= 32'h7835a237; + if (bf !== 3'b100) $stop; + if (nt0 !== 1'b1) $stop; + if (an0 !== 1'b0) $stop; + if (nd0 !== 1'b1) $stop; + if (or0 !== 1'b0) $stop; + if (nr0 !== 1'b1) $stop; + if (xo0 !== 1'b0) $stop; + if (xn0 !== 1'b1) $stop; + if (ba != 32'h18f6b034) $stop; + end + if (cyc==3) begin + if (bf !== 3'b111) $stop; + if (nt0 !== 1'b0) $stop; + if (an0 !== 1'b1) $stop; + if (nd0 !== 1'b0) $stop; + if (or0 !== 1'b1) $stop; + if (nr0 !== 1'b0) $stop; + if (xo0 !== 1'b0) $stop; + if (xn0 !== 1'b0) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gate_delref.v b/SVIncCompil/Testcases/Verilator/t_gate_delref.v new file mode 100644 index 0000000..154559b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gate_delref.v
@@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +// bug1475 +module t (/*AUTOARG*/ + // Outputs + ID_45, IDa_f4c, + // Inputs + clk, ID_d9f, IDa_657, ID_477 + ); + input clk; + output reg ID_45; + input ID_d9f; + input IDa_657; + output reg IDa_f4c; + + reg ID_13; + input ID_477; + reg ID_489; + reg ID_8d1; + reg IDa_183; + reg IDa_91c; + reg IDa_a96; + reg IDa_d6b; + reg IDa_eb9; + wire ID_fc8 = ID_d9f & ID_13; //<< + wire ID_254 = ID_d9f & ID_13; + wire ID_f40 = ID_fc8 ? ID_8d1 : 0; + wire ID_f4c = ID_fc8 ? 0 : ID_477; + wire ID_442 = IDa_91c; + wire ID_825 = ID_489; + always @(posedge clk) begin + ID_13 <= ID_f40; + ID_8d1 <= IDa_eb9; + ID_489 <= ID_442; + ID_45 <= ID_825; + IDa_d6b <= IDa_a96; + IDa_f4c <= ID_f4c; + if (ID_254) begin + IDa_91c <= IDa_d6b; + IDa_183 <= IDa_657; + IDa_a96 <= IDa_657; + IDa_eb9 <= IDa_183; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gate_elim.v b/SVIncCompil/Testcases/Verilator/t_gate_elim.v new file mode 100644 index 0000000..2a145be --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gate_elim.v
@@ -0,0 +1,121 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg b; + + wire vconst1 = 1'b0; + wire vconst2 = !(vconst1); + wire vconst3 = !vconst2; + wire vconst = vconst3; + + wire qa; + wire qb; + wire qc; + wire qd; + wire qe; + ta ta (.b(b), .vconst(vconst), .q(qa)); + tb tb (.clk(clk), .vconst(vconst), .q(qb)); + tc tc (.b(b), .vconst(vconst), .q(qc)); + td td (.b(b), .vconst(vconst), .q(qd)); + te te (.clk(clk), .b(b), .vconst(vconst), .q(qe)); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $display("%b",{qa,qb,qc,qd,qe}); +`endif + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + b <= 1'b1; + end + if (cyc==2) begin + if (qa!=1'b1) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + b <= 1'b0; + end + if (cyc==3) begin + if (qa!=1'b0) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + if (qe!=1'b0) $stop; + b <= 1'b1; + end + if (cyc==4) begin + if (qa!=1'b1) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + if (qe!=1'b1) $stop; + b <= 1'b0; + end + if (cyc==5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +module ta ( + input vconst, + input b, + output reg q); + + always @ (/*AS*/b or vconst) begin + q = vconst | b; + end +endmodule + +module tb ( + input vconst, + input clk, + output reg q); + + always @ (posedge clk) begin + q <= vconst; + end +endmodule + +module tc ( + input vconst, + input b, + output reg q); + always @ (posedge vconst) begin + q <= b; + $stop; + end +endmodule + +module td ( + input vconst, + input b, + output reg q); + + always @ (/*AS*/vconst) begin + q = vconst; + end +endmodule + +module te ( + input clk, + input vconst, + input b, + output reg q); + reg qmid; + always @ (posedge vconst or posedge clk) begin + qmid <= b; + end + always @ (posedge clk or posedge vconst) begin + q <= qmid; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gate_fdup.v b/SVIncCompil/Testcases/Verilator/t_gate_fdup.v new file mode 100644 index 0000000..eb17788 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gate_fdup.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Thomas Dzetkulic. + +module fnor2(f, a, b); + parameter W = 1; + + output [W-1:0]f; + input [W-1:0] a, b; + + supply0 gnd; + supply1 vcc; + + generate + genvar i; + for (i = 0; i < W; i = i + 1) begin + wire w; + pmos(f[i], w, a[i]); + pmos(w, vcc, b[i]); + nmos(f[i], gnd, a[i]); + nmos(f[i], gnd, b[i]); + end + endgenerate +endmodule + +module t(f, a, b); + output [1:0] f; + input [1:0] a, b; + + fnor2 #(2) n(f, a, b); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gate_implicit.v b/SVIncCompil/Testcases/Verilator/t_gate_implicit.v new file mode 100644 index 0000000..4255ff2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gate_implicit.v
@@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire RBL2; // From t of Test.v + // End of automatics + + wire RWL1 = crc[2]; + wire RWL2 = crc[3]; + + Test t (/*AUTOINST*/ + // Outputs + .RBL2 (RBL2), + // Inputs + .RWL1 (RWL1), + .RWL2 (RWL2)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, RBL2}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hb6d6b86aa20a882a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test ( + output RBL2, + input RWL1, RWL2); + + // verilator lint_off IMPLICIT + not I1 (RWL2_n, RWL2); + bufif1 I2 (RBL2, n3, 1'b1); + Mxor I3 (n3, RWL1, RWL2_n); + // verilator lint_on IMPLICIT + +endmodule + +module Mxor (output out, input a, b); + assign out = (a ^ b); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gate_unsup.v b/SVIncCompil/Testcases/Verilator/t_gate_unsup.v new file mode 100644 index 0000000..2e78fd2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gate_unsup.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/); + + wire d, en, nc, pc; + + // verilator lint_off IMPLICIT + cmos (cm0, d, nc, pc); + rcmos (rc0, d, nc, pc); + + nmos (nm0, d, en); + pmos (pm0, d, en); + rnmos (rn0, d, en); + rpmos (rp0, d, en); + + rtran (rt0, d); + tran (tr0, d); + + rtranif0 (r00, d, en); + rtranif1 (r10, d, en); + tranif0 (t00, d, en); + tranif1 (t10, d, en); + // verilator lint_on IMPLICIT + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gated_clk_1.v b/SVIncCompil/Testcases/Verilator/t_gated_clk_1.v new file mode 100644 index 0000000..a638cb6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gated_clk_1.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Test of gated clock detection +// +// The code as shown generates a result by a delayed assignment from PC. The +// creation of the result is from a clock gated from the clock that sets +// PC. Howevever since they are essentially the same clock, the result should +// be delayed by one cycle. +// +// Standard Verilator treats them as different clocks, so the result stays in +// step with the PC. An event drive simulator always allows the clock to win. +// +// The problem is caused by the extra loop added by Verilator to the +// evaluation of all internally generated clocks (effectively removed by +// marking the clock enable). +// +// This test is added to facilitate experiments with solutions. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett <jeremy.bennett@embecosm.com>. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg gated_clk_en = 1'b0 ; + reg [1:0] pc = 2'b0; + reg [1:0] res = 2'b0; + + wire gated_clk = gated_clk_en & clk; + + always @(posedge clk) begin + pc <= pc + 1; + gated_clk_en <= 1'b1; + end + + always @(posedge gated_clk) begin + res <= pc; + end + + always @(posedge clk) begin + if (pc == 2'b11) begin + // Correct behaviour is that res should be lagging pc in the count + // by one cycle + if (res == 2'b10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_alw.v b/SVIncCompil/Testcases/Verilator/t_gen_alw.v new file mode 100644 index 0000000..fd114b1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_alw.v
@@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [9:0] in = crc[9:0]; + + /*AUTOWIRE*/ + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[9:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {64'h0}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Inputs + clk, in + ); + input clk; + input [9:0] in; + + reg a [9:0]; + integer ai; + always @* begin + for (ai=0;ai<10;ai=ai+1) begin + a[ai]=in[ai]; + end + end + + reg [1:0] b [9:0]; + integer j; + + generate + genvar i; + for (i=0; i<2; i=i+1) begin + always @(posedge clk) begin + for (j=0; j<10; j=j+1) begin + if (a[j]) + b[i][j] <= 1'b0; + else + b[i][j] <= 1'b1; + end + end + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_assign.v b/SVIncCompil/Testcases/Verilator/t_gen_assign.v new file mode 100644 index 0000000..838d880 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_assign.v
@@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +`timescale 1ns / 1ps + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [31:0] sum; + + wire [8:0] Output; + wire [8:0] Input = crc[8:0]; + + assigns assigns (/*AUTOINST*/ + // Outputs + .Output (Output[8:0]), + // Inputs + .Input (Input[8:0])); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 32'h0; + end + else if (cyc>10 && cyc<90) begin + sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]}; + end + else if (cyc==99) begin + if (sum !== 32'he8bbd130) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module assigns(Input, Output); + input [8:0] Input; + output [8:0] Output; + + genvar i; + generate + for (i = 0; i < 8; i = i + 1) begin : ap + assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8]; + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_cond_bitrange.v b/SVIncCompil/Testcases/Verilator/t_gen_cond_bitrange.v new file mode 100644 index 0000000..67f6379 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_cond_bitrange.v
@@ -0,0 +1,139 @@ +// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if" +// +// The given generate loops should only access valid bits of mask, since that +// is defined by SIZE. However since the loop range is larger, this only works +// if short-circuited evaluation of the generate loop is in place. + +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2012 by Jeremy Bennett. + + +`define MAX_SIZE 4 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen + #(.SIZE (2), + .MASK (2'b11)) + i_test_gen (.clk (clk)); + + // This is only a compilation test, but for good measure we do one clock + // cycle. + integer count; + + initial begin + count = 0; + end + + always @(posedge clk) begin + if (count == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + count = count + 1; + end + end + +endmodule // t + + +module test_gen + + #( parameter + SIZE = `MAX_SIZE, + MASK = `MAX_SIZE'b0) + + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Generate blocks that rely on short-circuiting of the logic to avoid errors. + generate + genvar g; + + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < SIZE) && MASK[g]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g >= SIZE) || ~MASK[g])) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g < SIZE) -> ~MASK[g])) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ( g < SIZE ? MASK[g] : 1'b0) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + + // The other way round + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ( g >= SIZE ? 1'b0 : MASK[g]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_cond_bitrange_bad.v b/SVIncCompil/Testcases/Verilator/t_gen_cond_bitrange_bad.v new file mode 100644 index 0000000..90b7856 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_cond_bitrange_bad.v
@@ -0,0 +1,106 @@ +// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if" +// that should not work. +// +// The given generate loops should attempt to access invalid bits of mask and +// trigger errors. +// is defined by SIZE. However since the loop range is larger, this only works +// if short-circuited evaluation of the generate loop is in place. + +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2012 by Jeremy Bennett. + + +`define MAX_SIZE 3 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen + #(.SIZE (2), + .MASK (2'b11)) + i_test_gen (.clk (clk)); + + // This is only a compilation test, so we can immediately finish + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule // t + + +module test_gen + + #( parameter + SIZE = `MAX_SIZE, + MASK = `MAX_SIZE'b0) + + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Generate blocks that all have errors in applying short-circuting to + // generate "if" conditionals. + + // Attempt to access invalid bits of MASK in different ways + generate + genvar g; + + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < (SIZE + 1)) && MASK[g]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + end + end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < SIZE) && MASK[g + 1]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + end + end + end + endgenerate + + // Attempt to short-circuit bitwise AND + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < (SIZE)) & MASK[g]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + end + end + end + endgenerate + + // Attempt to short-circuit bitwise OR + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g >= SIZE) | ~MASK[g])) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + end + end + end + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_cond_const.v b/SVIncCompil/Testcases/Verilator/t_gen_cond_const.v new file mode 100644 index 0000000..e23daf4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_cond_const.v
@@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test for generate IF constants +// +// The given generate loop should have a constant expression as argument. This +// test checks it really does evaluate as constant. + +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2012 by Jeremy Bennett. + + +`define MAX_SIZE 4 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen + #(.SIZE (2), + .MASK (4'b1111)) + i_test_gen (.clk (clk)); + + // This is only a compilation test, but for good measure we do one clock + // cycle. + integer count; + + initial begin + count = 0; + end + + always @(posedge clk) begin + if (count == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + count = count + 1; + end + end + +endmodule // t + + +module test_gen + + #( parameter + SIZE = `MAX_SIZE, + MASK = `MAX_SIZE'b0) + + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Generate blocks that rely on short-circuiting of the logic to avoid + // errors. + generate + if ((SIZE < 8'h04) && MASK[0]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Generate IF MASK[0] = %d\n", MASK[0]); +`endif + end + end + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_defparam.v b/SVIncCompil/Testcases/Verilator/t_gen_defparam.v new file mode 100644 index 0000000..041cf29 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_defparam.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + parameter PAR = 3; + + wire [31:0] o1a,o1b; + + m1 #(0) m1a(.o(o1a)); + m1 #(1) m1b(.o(o1b)); + + always @ (posedge clk) begin + if (o1a != 8) $stop; + if (o1b != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module m1 (output wire [31:0] o); + parameter W = 0; + generate + if (W == 0) begin + m2 m2 (.o(o)); + defparam m2.PAR2 = 8; + end + else begin + m2 m2 (.o(o)); + defparam m2.PAR2 = 4; + end + endgenerate +endmodule + +module m2 (output wire [31:0] o); + parameter PAR2 = 10; + assign o = PAR2; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_div0.v b/SVIncCompil/Testcases/Verilator/t_gen_div0.v new file mode 100644 index 0000000..2a55271 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_div0.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOINST*/); + + Test #( + .BIT_WIDTH (72), + .BYTE_WIDTH (9) + ) + + u_test_inst(); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module Test (); + + parameter BIT_WIDTH = ""; + parameter BYTE_WIDTH = ""; + + localparam BYTES = BIT_WIDTH / BYTE_WIDTH; + + wire [BYTES - 1:0] i; + wire [BYTES - 1:0] o; + + genvar g; + generate + for (g = 0; g < BYTES; g = g + 1) begin: gen + assign o[g] = (i[g] !== 1'b0); + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_for.v b/SVIncCompil/Testcases/Verilator/t_gen_for.v new file mode 100644 index 0000000..d034950 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_for.v
@@ -0,0 +1,172 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + reg [7:0] crc; + genvar g; + + wire [7:0] out_p1; + wire [15:0] out_p2; + wire [7:0] out_p3; + wire [7:0] out_p4; + + paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1)); + paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2)); + paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3)); + gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4)); + + wire [7:0] out_ef; + enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef); + cyc <= cyc + 1; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==0) begin + // Setup + crc <= 8'hed; + end + else if (cyc==1) begin + end + else if (cyc==3) begin + if (out_p1 !== 8'h2d) $stop; + if (out_p2 !== 16'h2d2d) $stop; + if (out_p3 !== 8'h78) $stop; + if (out_p4 !== 8'h44) $stop; + if (out_ef !== 8'hda) $stop; + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module gencase (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + parameter MODE = 0; + input [7:0] in; + output [7:0] out; + generate // : genblk1 + begin + case (MODE) + 2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]})); + default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]})); + endcase + end + endgenerate + +endmodule + +module paramed (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + parameter WIDTH = 1; + parameter MODE = 0; + input [WIDTH-1:0] in; + output [WIDTH-1:0] out; + + generate + if (MODE==0) initial $write("Mode=0\n"); + // No else + endgenerate + +`ifndef NC // for(genvar) unsupported + `ifndef ATSIM // for(genvar) unsupported + generate + // Empty loop body, local genvar + for (genvar j=0; j<3; j=j+1) begin end + // Ditto to make sure j has new scope + for (genvar j=0; j<5; j=j+1) begin end + endgenerate + `endif +`endif + + generate + endgenerate + + genvar i; + generate + if (MODE==0) begin + // Flip bitorder, direct assign method + for (i=0; i<WIDTH; i=i+1) begin + assign out[i] = in[WIDTH-i-1]; + end + end + else if (MODE==1) begin + // Flip using instantiation + for (i=0; i<WIDTH; i=i+1) begin + integer from = WIDTH-i-1; + if (i==0) begin // Test if's within a for + mbuf m0 (.q(out[i]), .a(in[from])); + end + else begin + mbuf ma (.q(out[i]), .a(in[from])); + end + end + end + else begin + for (i=0; i<WIDTH; i=i+1) begin + mbuf ma (.q(out[i]), .a(in[i^1])); + end + end + endgenerate + +endmodule + +module mbuf ( + input a, + output q + ); + assign q = a; +endmodule + +module enflop (clk, oe_e1, a,q); + parameter WIDTH=1; + + input clk; + input oe_e1; + input [WIDTH-1:0] a; + output [WIDTH-1:0] q; + + reg [WIDTH-1:0] oe_r; + reg [WIDTH-1:0] q_r; + genvar i; + + generate + for (i = 0; i < WIDTH; i = i + 1) begin : datapath_bits + enflop_one enflop_one + (.clk (clk), + .d (a[i]), + .q_r (q_r[i])); + + always @(posedge clk) oe_r[i] <= oe_e1; + + assign q[i] = oe_r[i] ? q_r[i] : 1'bx; + end + endgenerate +endmodule + +module enflop_one ( + input clk, + input d, + output reg q_r + ); + always @(posedge clk) q_r <= d; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_for0.v b/SVIncCompil/Testcases/Verilator/t_gen_for0.v new file mode 100644 index 0000000..1f5c8f2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_for0.v
@@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + Testit testit (/*AUTOINST*/ + // Inputs + .clk (clk)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + end + else if (cyc<10) begin + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Testit (clk); + input clk; + + genvar igen; + generate + for (igen=0; igen<0; igen=igen+1) begin : test_gen + always @ (posedge clk) begin + $display("igen1 = %d", igen); + $stop; + end + end + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_for1.v b/SVIncCompil/Testcases/Verilator/t_gen_for1.v new file mode 100644 index 0000000..469817e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_for1.v
@@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire b; + reg reset; + integer cyc=0; + + Testit testit (/*AUTOINST*/ + // Outputs + .b (b), + // Inputs + .clk (clk), + .reset (reset)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + reset <= 1'b0; + end + else if (cyc<10) begin + reset <= 1'b1; + end + else if (cyc<90) begin + reset <= 1'b0; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Testit (clk, reset, b); + input clk; + input reset; + output b; + + wire [0:0] c; + wire my_sig; + wire [0:0] d; + + genvar i; + generate + for(i = 0; i >= 0; i = i-1) begin: fnxtclk1 + fnxtclk fnxtclk1 + (.u(c[i]), + .reset(reset), + .clk(clk), + .w(d[i]) ); + end + endgenerate + + assign b = d[0]; + assign c[0] = my_sig; + assign my_sig = 1'b1; + +endmodule + +module fnxtclk (u, reset, clk, w ); + input u; + input reset; + input clk; + output reg w; + + always @ (posedge clk or posedge reset) begin + if (reset == 1'b1) begin + w <= 1'b0; + end + else begin + w <= u; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_for2.v b/SVIncCompil/Testcases/Verilator/t_gen_for2.v new file mode 100644 index 0000000..f4f83a8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_for2.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. + +parameter N = 5; + +interface intf; + logic [N-1:0] data; +endinterface + +module t ( + input logic clk + ); + intf localinterface [N-1:0](); + + generate + genvar i,j; + for(i = 0; i < N; i++) begin + logic [N-1:0] dummy; + for(j = 0; j < N; j++) begin + assign dummy[j] = localinterface[j].data[i]; + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_for_overlap.v b/SVIncCompil/Testcases/Verilator/t_gen_for_overlap.v new file mode 100644 index 0000000..87da513 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_for_overlap.v
@@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +// bug749 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + genvar g; + for (g=1; g<3; ++g) begin : gblk + sub2 #(.IN(g)) u (); + //sub #(.IN(g)) u2 (); + end + + sub1 #(.IN(0)) u (); + + always @ (posedge clk) begin + if (t.u.IN != 0) $stop; + if (t.u.FLAVOR != 1) $stop; + //if (t.u2.IN != 0) $stop; // This should be not found + if (t.gblk[1].u.IN != 1) $stop; + if (t.gblk[2].u.IN != 2) $stop; + if (t.gblk[1].u.FLAVOR != 2) $stop; + if (t.gblk[2].u.FLAVOR != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub1 (/*AUTOARG*/); + parameter [31:0] IN = 99; + parameter FLAVOR = 1; +`ifdef TEST_VERBOSE + initial $display("%m"); +`endif +endmodule + +module sub2 (/*AUTOARG*/); + parameter [31:0] IN = 99; + parameter FLAVOR = 2; +`ifdef TEST_VERBOSE + initial $display("%m"); +`endif +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_for_shuffle.v b/SVIncCompil/Testcases/Verilator/t_gen_for_shuffle.v new file mode 100644 index 0000000..92048f4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_for_shuffle.v
@@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h3e3a62edb61f8c7f + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [31:0] in; + output [31:0] out; + + genvar i; + generate + for (i=0; i<16; i=i+1) begin : gblk + assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)]; + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_forif.v b/SVIncCompil/Testcases/Verilator/t_gen_forif.v new file mode 100644 index 0000000..6e542f0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_forif.v
@@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [3:0] Value = crc[3:0]; + + wire [3:0] Result; + wire [3:0] Result2; + + Testit testit (/*AUTOINST*/ + // Outputs + .Result (Result[3:0]), + .Result2 (Result2[3:0]), + // Inputs + .clk (clk), + .Value (Value[3:0])); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {56'h0, Result, Result2} + ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h4af37965592f64f9) $stop; + $finish; + end + end + +endmodule + +module Test (clk, Value, Result); + input clk; + input Value; + output Result; + + reg Internal; + + assign Result = Internal ^ clk; + + always @(posedge clk) + Internal <= #1 Value; +endmodule + +module Test_wrap1 (clk, Value, Result); + input clk; + input Value; + output Result; + + Test t (clk, Value, Result); +endmodule + +module Test_wrap2 (clk, Value, Result); + input clk; + input Value; + output Result; + + Test t (clk, Value, Result); +endmodule + +module Testit (clk, Value, Result, Result2); + input clk; + input [3:0] Value; + output [3:0] Result; + output [3:0] Result2; + + genvar i; + generate + for (i = 0; i < 4; i = i + 1) + begin : a + if ((i == 0) || (i == 2)) begin : gblk + Test_wrap1 test (clk, Value[i] , Result[i]); + end + else begin : gblk + Test_wrap2 test (clk, Value[i], Result[i]); + end + end + endgenerate + + assign Result2[0] = a[0].gblk.test.t.Internal; + assign Result2[1] = a[1].gblk.test.t.Internal; + assign Result2[2] = a[2].gblk.test.t.Internal; + assign Result2[3] = a[3].gblk.test.t.Internal; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_if.v b/SVIncCompil/Testcases/Verilator/t_gen_if.v new file mode 100644 index 0000000..33ef710 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_if.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// simplistic example, should choose 1st conditional generate and assign straight through +// the tool also compiles the special case and determines an error (replication value is 0) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +`timescale 1ns / 1ps + +module t(data_i, data_o, single); + parameter op_bits = 32; + input [op_bits -1:0] data_i; + output [31:0] data_o; + input single; + + //simplistic example, should choose 1st conditional generate and assign straight through + //the tool also compiles the special case and determines an error (replication value is 0 + generate + if (op_bits == 32) begin : general_case + assign data_o = data_i; + // Test implicit signals + /* verilator lint_off IMPLICIT */ + assign imp = single; + /* verilator lint_on IMPLICIT */ + end + else begin : special_case + assign data_o = {{(32 -op_bits){1'b0}},data_i}; + /* verilator lint_off IMPLICIT */ + assign imp = single; + /* verilator lint_on IMPLICIT */ + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_inc.v b/SVIncCompil/Testcases/Verilator/t_gen_inc.v new file mode 100644 index 0000000..2a9884f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_inc.v
@@ -0,0 +1,114 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + genvar g; + integer i; + + reg [31:0] v; + + reg [31:0] gen_pre_PLUSPLUS = 32'h0; + reg [31:0] gen_pre_MINUSMINUS = 32'h0; + reg [31:0] gen_post_PLUSPLUS = 32'h0; + reg [31:0] gen_post_MINUSMINUS = 32'h0; + reg [31:0] gen_PLUSEQ = 32'h0; + reg [31:0] gen_MINUSEQ = 32'h0; + reg [31:0] gen_TIMESEQ = 32'h0; + reg [31:0] gen_DIVEQ = 32'h0; + reg [31:0] gen_MODEQ = 32'h0; + reg [31:0] gen_ANDEQ = 32'h0; + reg [31:0] gen_OREQ = 32'h0; + reg [31:0] gen_XOREQ = 32'h0; + reg [31:0] gen_SLEFTEQ = 32'h0; + reg [31:0] gen_SRIGHTEQ = 32'h0; + reg [31:0] gen_SSRIGHTEQ = 32'h0; + + generate + for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1; + for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1; + for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1; + for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1; + for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1; + for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1; +`ifndef verilator //UNSUPPORTED + for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1; + for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1; + for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1; + for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1; + for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1; + for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1; + for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1; + for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1; + for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1; +`endif + endgenerate + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 3) begin +`ifdef TEST_VERBOSE + $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); + $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); + $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); + $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); + $write("gen_PLUSEQ %b\n", gen_PLUSEQ); + $write("gen_MINUSEQ %b\n", gen_MINUSEQ); + $write("gen_TIMESEQ %b\n", gen_TIMESEQ); + $write("gen_DIVEQ %b\n", gen_DIVEQ); + $write("gen_MODEQ %b\n", gen_MODEQ); + $write("gen_ANDEQ %b\n", gen_ANDEQ); + $write("gen_OREQ %b\n", gen_OREQ); + $write("gen_XOREQ %b\n", gen_XOREQ); + $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); + $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); + $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); +`endif + if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; + if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; + if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; +`ifndef verilator //UNSUPPORTED + if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; + if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; + if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; + if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; + if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; +`endif + + v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; + v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; +`ifndef verilator //UNSUPPORTED + v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; + v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; + v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop; + v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; + v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop; + v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; + v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop; + v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; + v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_index.v b/SVIncCompil/Testcases/Verilator/t_gen_index.v new file mode 100644 index 0000000..cf56444 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_index.v
@@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Test generate index usage. +// +// The code illustrates a problem in Verilator's handling of constant +// expressions inside generate indexes. +// +// This is a regression test against issue 517. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + + +`define START 8 +`define SIZE 4 +`define END (`START + `SIZE) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [`END-1:0] y; + wire [`END-1:0] x; + + foo foo_i (.y (y), + .x (x), + .clk (clk)); + + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule // t + + +module foo(output wire [`END-1:0] y, + input wire [`END-1:0] x, + input wire clk); + + function peek_bar; + peek_bar = bar_inst[`START].i_bar.r; // this is ok + peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not. + endfunction + + genvar g; + generate + for (g = `START; g < `END; g = g + 1) begin: bar_inst + bar i_bar(.x (x[g]), + .y (y[g]), + .clk (clk)); + end + endgenerate + +endmodule : foo + + +module bar(output wire y, + input wire x, + input wire clk); + + reg r = 0; + assign y = r; + + always @(posedge clk) begin + r = x ? ~x : y; + end + +endmodule : bar
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_intdot.v b/SVIncCompil/Testcases/Verilator/t_gen_intdot.v new file mode 100644 index 0000000..fe457f5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_intdot.v
@@ -0,0 +1,119 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +`define STRINGIFY(x) `"x`" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + wire out; + reg in; + + Genit g (.clk(clk), .value(in), .result(out)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + in <= 1'b1; + end + else if (cyc==1) begin + in <= 1'b0; + end + else if (cyc==2) begin + if (out != 1'b1) $stop; + end + else if (cyc==3) begin + if (out != 1'b0) $stop; + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +//`define WAVES +`ifdef WAVES + initial begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"}); + $dumpvars(12, t); + end +`endif + +endmodule + +module Generate (clk, value, result); + input clk; + input value; + output result; + + reg Internal; + + assign result = Internal ^ clk; + + always @(posedge clk) + Internal <= #1 value; +endmodule + +module Checker (clk, value); + input clk, value; + + always @(posedge clk) begin + $write ("[%0t] value=%h\n", $time, value); + end + +endmodule + +module Test (clk, value, result); + input clk; + input value; + output result; + + Generate gen (clk, value, result); + Checker chk (clk, gen.Internal); + +endmodule + +module Genit (clk, value, result); + input clk; + input value; + output result; + +`ifndef ATSIM // else unsupported + `ifndef NC // else unsupported + `define WITH_FOR_GENVAR + `endif +`endif + +`define WITH_GENERATE +`ifdef WITH_GENERATE + `ifndef WITH_FOR_GENVAR + genvar i; + `endif + generate + for ( + `ifdef WITH_FOR_GENVAR + genvar + `endif + i = 0; i < 1; i = i + 1) + begin : foo + Test tt (clk, value, result); + end + endgenerate +`else + Test tt (clk, value, result); +`endif + + wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change! + always @ (posedge clk) begin + $write("[%0t] Result2 = %x\n", $time, Result2); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_intdot2.v b/SVIncCompil/Testcases/Verilator/t_gen_intdot2.v new file mode 100644 index 0000000..75a4d51 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_intdot2.v
@@ -0,0 +1,166 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +`define STRINGIFY(x) `"x`" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + reg check; + initial check = 1'b0; + Genit g (.clk(clk), .check(check)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + check <= 1'b0; + end + else if (cyc==1) begin + check <= 1'b1; + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +//`define WAVES +`ifdef WAVES + initial begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"}); + $dumpvars(12, t); + end +`endif + +endmodule + +module One; + wire one = 1'b1; +endmodule + +module Genit ( + input clk, + input check); + + // ARRAY + One cellarray1[1:0] (); //cellarray[0..1][0..1] + always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop; + always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop; + + // IF + generate + // genblk1 refers to the if's name, not the "generate" itself. + if (1'b1) // IMPLIED begin: genblk1 + One ifcell1(); // genblk1.ifcell1 + else + One ifcell1(); // genblk1.ifcell1 + endgenerate + // On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc +`ifdef verilator + always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop; +//`else // NOT SUPPORTED accoring to spec - generic block references +`endif + + generate + begin : namedif2 + if (1'b1) + One ifcell2(); // namedif2.genblk1.ifcell2 + end + endgenerate +`ifdef verilator + always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop; +//`else // NOT SUPPORTED accoring to spec - generic block references +`endif + + generate + if (1'b1) + begin : namedif3 + One ifcell3(); // namedif3.ifcell3 + end + endgenerate + always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop; + + // CASE + generate + case (1'b1) + 1'b1 : + One casecell10(); // genblk3.casecell10 + endcase + endgenerate +`ifdef verilator + always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop; +//`else // NOT SUPPORTED accoring to spec - generic block references +`endif + + generate + case (1'b1) + 1'b1 : begin : namedcase11 + One casecell11(); + end + endcase + endgenerate + always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop; + + genvar i; + genvar j; + + // IF + generate + for (i = 0; i < 2; i = i + 1) + One cellfor20 (); // genblk4[0..1].cellfor20 + endgenerate +`ifdef verilator + always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop; + always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop; +//`else // NOT SUPPORTED accoring to spec - generic block references +`endif + + // COMBO + generate + for (i = 0; i < 2; i = i + 1) + begin : namedfor21 + One cellfor21 (); // namedfor21[0..1].cellfor21 + end + endgenerate + always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop; + + generate + for (i = 0; i < 2; i = i + 1) + begin : namedfor30 + for (j = 0; j < 2; j = j + 1) + begin : forb30 + if (j == 0) + begin : forif30 + One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a + end + else +`ifdef verilator + begin : forif30b +`else + begin : forif30 // forif30 seems to work on some simulators, not verilator yet +`endif + One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b + end + end + end + endgenerate + always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; +`ifdef verilator + always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; +`else + always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; +`endif + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_local.v b/SVIncCompil/Testcases/Verilator/t_gen_local.v new file mode 100644 index 0000000..dcb7354 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_local.v
@@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + localparam N = 31; + + wire [31:0] vec; + + generate + genvar g; // bug461 + begin : topgen + for (g=0; g<N; ++g) begin : gfor + assign vec[g] = (g<2); + end + end + endgenerate + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 3) begin + if (vec != 32'b0011) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_lsb.v b/SVIncCompil/Testcases/Verilator/t_gen_lsb.v new file mode 100644 index 0000000..27a7857 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_lsb.v
@@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [3:0] datai = crc[3:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [3:0] datao; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .datao (datao[3:0]), + // Inputs + .clk (clk), + .datai (datai[3:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, datao}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h3db7bc8bfe61f983 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( + input logic clk, + input logic [3:0] datai, + output logic [3:0] datao +); + genvar i; + + parameter SIZE = 4; + + logic [SIZE:1][3:0] delay; + + always_ff @(posedge clk) begin + delay[1][3:0] <= datai; + end + + generate + for (i = 2; i < (SIZE+1); i++) begin + always_ff @(posedge clk) begin + delay[i][3:0] <= delay[i-1][3:0]; + end + end + endgenerate + + always_comb datao = delay[SIZE][3:0]; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_mislevel.v b/SVIncCompil/Testcases/Verilator/t_gen_mislevel.v new file mode 100644 index 0000000..e7edfcf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_mislevel.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +/// We define the modules in "backward" order. + +module d; +endmodule + +module b; + generate if (1) begin + c c1 (); + c c2 (); + end + endgenerate +endmodule + +module c; + generate if (1) begin + d d1 (); + d d2 (); + end + endgenerate +endmodule + +module a; + generate if (1) begin + b b1 (); + b b2 (); + end + endgenerate +endmodule + +module t (/*AUTOARG*/); + + a a1 (); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_missing.v b/SVIncCompil/Testcases/Verilator/t_gen_missing.v new file mode 100644 index 0000000..a491964 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_missing.v
@@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t; + // verilator lint_off PINMISSING +`ifdef T_GEN_MISSING_BAD + foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module +`elsif T_GEN_MISSING + foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0 +`else + `error "Bad Test" +`endif +endmodule + + +module foobar + #( parameter + FOO_START = 0, + FOO_NUM = 2, + FOO_TYPE = 1 + ) + ( + input wire[FOO_NUM-1:0] foo, + output wire[FOO_NUM-1:0] bar); + + + generate + begin: g + genvar j; + for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1) + begin: foo_inst; + if (FOO_TYPE == 0) + begin: foo_0 + // instatiate foo0 + foo0 i_foo(.x(foo[j]), .y(bar[j])); + end + if (FOO_TYPE == 1) + begin: foo_1 + // instatiate foo1 + foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); + end + end + end + endgenerate +endmodule + + + +module foo0(input wire x, output wire y); + + assign y = ~x; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_self_return.v b/SVIncCompil/Testcases/Verilator/t_gen_self_return.v new file mode 100644 index 0000000..9af9d9e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_self_return.v
@@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Roman Popov. + +module dut + #( + parameter DEPTH = 16, + parameter WIDTH = 32, + parameter RAM_SPLIT_WIDTH = 16 + ) + ( + output logic [WIDTH-1:0] ram_dataout + ); + + localparam RAM_ADDR_WIDTH = $clog2(DEPTH); // = 4 + localparam NUM_RAM_BLOCKS = (WIDTH/RAM_SPLIT_WIDTH) + {31'h0, ((WIDTH % RAM_SPLIT_WIDTH) > 0)}; // = 2 + typedef logic [NUM_RAM_BLOCKS:0][31:0] block_index_t; // width 96 + + function automatic block_index_t index_calc(input int WIDTH, NUM_RAM_BLOCKS); + index_calc[0] = '0; + for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = WIDTH/NUM_RAM_BLOCKS + {31'h0, (i < (WIDTH%NUM_RAM_BLOCKS))}; + for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = index_calc[i+1] + index_calc[i]; + // bug1467 was this return + return index_calc; + endfunction + + localparam block_index_t RAM_BLOCK_INDEX = index_calc(WIDTH, NUM_RAM_BLOCKS); + + generate + begin : ram_dataout_gen + for (genvar i = 0; i < NUM_RAM_BLOCKS; i++) begin + always_comb ram_dataout[RAM_BLOCK_INDEX[i+1]-1:RAM_BLOCK_INDEX[i]] = 0; + end + end + endgenerate + + initial begin + if (RAM_BLOCK_INDEX != {32'd32, 32'd16, 32'd0}) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module t + ( + input clk, + output logic [31:0] ram_dataout + ); + + dut dut0(.*); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_upscope.v b/SVIncCompil/Testcases/Verilator/t_gen_upscope.v new file mode 100644 index 0000000..474658b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_upscope.v
@@ -0,0 +1,84 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +/* Acceptable answer 1 +created tag with scope = top.t.tag +created tag with scope = top.t.b.gen[0].tag +created tag with scope = top.t.b.gen[1].tag +mod a has scope = top.t +mod a has tag = top.t.tag +mod b has scope = top.t.b +mod b has tag = top.t.tag +mod c has scope = top.t.b.gen[0].c +mod c has tag = top.t.b.gen[0].tag +mod c has scope = top.t.b.gen[1].c +mod c has tag = top.t.b.gen[1].tag +*/ +/* Acceptable answer 2 +created tag with scope = top.t.tag +created tag with scope = top.t.b.gen[0].tag +created tag with scope = top.t.b.gen[1].tag +mod a has scope = top.t +mod a has tag = top.t.tag +mod b has scope = top.t.b +mod b has tag = top.t.tag +mod c has scope = top.t.b.gen[0].c +mod c has tag = top.t.tag +mod c has scope = top.t.b.gen[1].c +mod c has tag = top.t.tag +*/ + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + tag tag (); + b b (); + + always @ (t.cyc) begin + if (t.cyc == 2) $display("mod a has scope = %m"); + if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope); + end + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module b (); + genvar g; + generate + for (g=0; g<2; g++) begin : gen + tag tag (); + c c (); + end + endgenerate + always @ (t.cyc) begin + if (t.cyc == 3) $display("mod b has scope = %m"); + if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope); + end +endmodule + +module c (); + always @ (t.cyc) begin + if (t.cyc == 4) $display("mod c has scope = %m"); + if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope); + end +endmodule + +module tag (); + bit [100*8-1:0] scope; + initial begin + $sformat(scope,"%m"); + $display("created tag with scope = %0s",scope); + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_gen_var_bad.v b/SVIncCompil/Testcases/Verilator/t_gen_var_bad.v new file mode 100644 index 0000000..177667c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_gen_var_bad.v
@@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t; + integer i; + generate + for (i=0; i<3; i=i+1) begin // Bad: i is not a genvar + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_generate_fatal_bad.v b/SVIncCompil/Testcases/Verilator/t_generate_fatal_bad.v new file mode 100644 index 0000000..f8f3181 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_generate_fatal_bad.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Todd Strader. + +function integer get_baz(input integer bar); + get_baz = bar; + $fatal(2, "boom"); +endfunction + +module foo #(parameter BAR = 0); + localparam integer BAZ = get_baz(BAR); +endmodule + +module foo2 #(parameter QUX = 0); + genvar x; + generate + for (x = 0; x < 2; x++) begin: foo2_loop + foo #(.BAR (QUX + x)) foo_in_foo2_inst(); + end + endgenerate +endmodule + +module t; + genvar i, j; + generate + for (i = 0; i < 2; i++) begin: genloop + foo #(.BAR (i)) foo_inst(); + end + for (i = 2; i < 4; i++) begin: gen_l1 + for (j = 0; j < 2; j++) begin: gen_l2 + foo #(.BAR (i + j*2)) foo_inst2(); + end + end + if (1 == 1) begin: cond_true + foo #(.BAR (6)) foo_inst3(); + end + if (1 == 1) begin // unnamed + foo #(.BAR (7)) foo_inst4(); + end + for (i = 8; i < 12; i = i + 2) begin: nested_loop + foo2 #(.QUX (i)) foo2_inst(); + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_genfor_hier.v b/SVIncCompil/Testcases/Verilator/t_genfor_hier.v new file mode 100644 index 0000000..cf69e3f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_genfor_hier.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Demonstrate deferred linking across module +// bondaries +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +module m1(); + logic v1; +endmodule + +module t (/*AUTOARG*/); + for (genvar the_genvar = 0; the_genvar < 4; the_genvar++) begin : m1_b + m1 m1_inst(); + end + for (genvar the_other_genvar = 0; the_other_genvar < 4; the_other_genvar++) begin + always_comb m1_b[the_other_genvar].m1_inst.v1 = 1'b0; + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_genvar_misuse_bad.v b/SVIncCompil/Testcases/Verilator/t_genvar_misuse_bad.v new file mode 100644 index 0000000..7ab4592 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_genvar_misuse_bad.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. +// See bug408 + +module top + ( + output logic [1:0] q, + input logic [1:0] d, + input logic clk + ); + + genvar i; + assign q[i] = d[i]; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_hierarchy_identifier.v b/SVIncCompil/Testcases/Verilator/t_hierarchy_identifier.v new file mode 100644 index 0000000..3774c78 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_hierarchy_identifier.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + parameter SIZE = 8; + + integer cnt = 0; + + logic [SIZE-1:0] vld_for; + logic vld_if = 1'b0; + logic vld_else = 1'b0; + + genvar i; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if (cnt==SIZE) begin : \0escaped___name + $write("*-* All Finished *-*\n"); + $finish; + end : \0escaped___name + + generate + for (i=0; i<SIZE; i=i+1) begin : generate_for + always @ (posedge clk) + if (cnt == i) vld_for[i] <= 1'b1; + end : generate_for + endgenerate + + generate + if (SIZE>0) begin : generate_if_if + always @ (posedge clk) + vld_if <= 1'b1; + end : generate_if_if + else begin : generate_if_else + always @ (posedge clk) + vld_else <= 1'b1; + end : generate_if_else + endgenerate + +endmodule : t
diff --git a/SVIncCompil/Testcases/Verilator/t_hierarchy_identifier_bad.v b/SVIncCompil/Testcases/Verilator/t_hierarchy_identifier_bad.v new file mode 100644 index 0000000..f8f12de --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_hierarchy_identifier_bad.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + parameter SIZE = 8; + + integer cnt = 0; + + logic [SIZE-1:0] vld_for; + logic vld_if = 1'b0; + logic vld_else = 1'b0; + + genvar i; + + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if (cnt==SIZE) begin : if_cnt_finish + $write("*-* All Finished *-*\n"); + $finish; + end : if_cnt_finish_bad + + generate + for (i=0; i<SIZE; i=i+1) begin : generate_for + always @ (posedge clk) + if (cnt == i) vld_for[i] <= 1'b1; + end : generate_for_bad + endgenerate + + generate + if (SIZE>0) begin : generate_if_if + always @ (posedge clk) + vld_if <= 1'b1; + end : generate_if_if_bad + else begin : generate_if_else + always @ (posedge clk) + vld_else <= 1'b1; + end : generate_if_else_bad + endgenerate + +endmodule : t_bad
diff --git a/SVIncCompil/Testcases/Verilator/t_hierarchy_unnamed.v b/SVIncCompil/Testcases/Verilator/t_hierarchy_unnamed.v new file mode 100644 index 0000000..37b55d4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_hierarchy_unnamed.v
@@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Chandan Egbert. + +module sub(); +endmodule + +module t(input logic a, input logic b, + output logic x, output logic y); + + always_comb begin + integer i; + x = a; + end + + sub u0(); + + always_comb begin + integer j; + y = b; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_if_deep.v b/SVIncCompil/Testcases/Verilator/t_if_deep.v new file mode 100644 index 0000000..2cdf4a8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_if_deep.v
@@ -0,0 +1,140 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h966e272fd829e672 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + output [31:0] out; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [31:0] out; + // End of automatics + +`ifdef verilator + `define dontOptimize $c1("1") +`else + `define dontOptimize 1'b1 +`endif + + always @(posedge clk) begin + out <= in; + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (in[0]) + out <= ~in; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_iff.v b/SVIncCompil/Testcases/Verilator/t_iff.v new file mode 100644 index 0000000..422c3db --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_iff.v
@@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Use this file as a template for submitting bugs, etc. +// This module takes a single clock input, and should either +// $write("*-* All Finished *-*\n"); +// $finish; +// on success, or $stop. +// +// The code as shown applies a random vector to the Test +// module, then calculates a CRC on the Test module's outputs. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by ____YOUR_NAME_HERE____. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] result; // From test of Test.v + // End of automatics + Test test (.*); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'he58508de5310b541 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( + input clk, + input [63:0] crc, + input [31:0] cyc, + output wire [31:0] result); + + wire enable = crc[32]; + wire [31:0] d = crc[31:0]; + logic [31:0] y; + always @(d iff enable == 1) begin + y <= d; + end + + wire reset = (cyc < 10); + assert property (@(posedge clk iff enable) + disable iff (reset) + (crc != '0)); + + // Aggregate outputs into a single result vector + assign result = {32'h0, y}; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_init_concat.v b/SVIncCompil/Testcases/Verilator/t_init_concat.v new file mode 100644 index 0000000..4629ae2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_init_concat.v
@@ -0,0 +1,86 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [31:0] wr_data; + reg wr_en; + wire [31:0] rd_data; + wire [1:0] rd_guards; + wire [1:0] rd_guardsok; + + regfile regfile (/*AUTOINST*/ + // Outputs + .rd_data (rd_data[31:0]), + .rd_guards (rd_guards[1:0]), + .rd_guardsok (rd_guardsok[1:0]), + // Inputs + .wr_data (wr_data[31:0]), + .wr_en (wr_en), + .clk (clk)); + + initial wr_en = 0; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + if (!rd_guards[0]) $stop; + if (!rd_guardsok[0]) $stop; + wr_en <= 1'b1; + wr_data <= 32'hfeedf; + end + if (cyc==2) begin + wr_en <= 0; + end + if (cyc==3) begin + wr_en <= 0; + if (rd_data != 32'hfeedf) $stop; + if (rd_guards != 2'b11) $stop; + if (rd_guardsok != 2'b11) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module regfile ( + input [31:0] wr_data, + input wr_en, + output reg [31:0] rd_data, + output [1:0] rd_guards /*verilator public*/, + output [1:0] rd_guardsok /*verilator public*/, + input clk + ); + + always @(posedge clk) begin + if (wr_en) + begin + rd_data <= wr_data; + end + end + + // this initial statement will induce correct initialize behavior + // initial rd_guards= { 2'b11 }; + + assign rd_guards= { + rd_data[0], + 1'b1 + }; + + assign rd_guardsok[0] = 1'b1; + assign rd_guardsok[1] = rd_data[0]; + +endmodule // regfile
diff --git a/SVIncCompil/Testcases/Verilator/t_initarray_nonarray.v b/SVIncCompil/Testcases/Verilator/t_initarray_nonarray.v new file mode 100644 index 0000000..b1a9f6c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_initarray_nonarray.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// The code here is used to trigger Verilator internal error +// "InitArray on non-array" +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Jie Xu. + +typedef logic [7:0] mask_t [7:0]; + +// parameter logic [7:0] IMP_MASK[7:0] = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37}; + +parameter mask_t IMP_MASK = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37}; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + mask_t a; + //logic [7:0] a[7:0]; + + assign a = IMP_MASK; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_initial.v b/SVIncCompil/Testcases/Verilator/t_initial.v new file mode 100644 index 0000000..ef38c11 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_initial.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + reg _ranit; + + `include "t_initial_inc.vh" + + // surefire lint_off STMINI + initial assign user_loaded_value = 1; + + initial _ranit = 0; + + always @ (posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + + // Test $time + // surefire lint_off CWECBB + if ($time<20) $write("time<20\n"); + // surefire lint_on CWECBB + + // Test $write + $write ("[%0t] %m: User loaded ", $time); + $display ("%b", user_loaded_value); + if (user_loaded_value!=1) $stop; + + // Test $c +`ifdef VERILATOR + $c ("VL_PRINTF(\"Hi From C++\\n\");"); +`endif + user_loaded_value <= 2; + + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_initial_dlyass.v b/SVIncCompil/Testcases/Verilator/t_initial_dlyass.v new file mode 100644 index 0000000..820ec5c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_initial_dlyass.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc; initial cyc = 0; + integer a; + integer b; + + initial begin + a <= 22; + b <= 33; + end + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==99) begin + if (a != 22) $stop; + if (b != 33) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_initial_edge.v b/SVIncCompil/Testcases/Verilator/t_initial_edge.v new file mode 100644 index 0000000..f45fce5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_initial_edge.v
@@ -0,0 +1,101 @@ +// DESCRIPTION: Verilator: initial edge issue +// +// The module initial_edge drives the output "res" high when the reset signal, +// rst, goes high. +// +// The module initial_edge_n drives the output "res_n" high when the reset +// signal, rst_n, goes low. +// +// For 4-state simulators, that edge occurs when the initial value of rst_n, +// X, goes to zero. However, by default for Verilator, being 2-state, the +// initial value is zero, so no edge is seen. +// +// This is not a bug in verilator (it is bad design to rely on an edge +// transition from an unitialized signal), but the problem is that there are +// quite a few instances of code out there that seems to be dependent on this +// behaviour to get out of reset. +// +// The Verilator --x-initial-edge flag causes these initial edges to trigger, +// thus matching the behaviour of a 4-state simulator. This is reportedly also +// the behaviour of commercial cycle accurate modelling tools as well. +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2012 by Wilson Snyder. + +`timescale 1ns/1ns + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire res; + wire res_n; + reg rst; + reg rst_n; + + integer count = 0; + + initial_edge i_edge (.res (res), + .rst (rst)); + + initial_edge_n i_edge_n (.res_n (res_n), + .rst_n (rst_n)); + + // run for 3 cycles, with one cycle of reset. + always @(posedge clk) begin + + rst <= (count == 0) ? 1 : 0; + rst_n <= (count == 0) ? 0 : 1; + + if (count == 3) begin + if ((res == 1) && (res_n == 1)) begin + $write ("*-* All Finished *-*\n"); + $finish; + end + else begin +`ifdef TEST_VERBOSE + $write ("FAILED: res = %b, res_n = %b\n", res, res_n); +`endif + $stop; + end + end + + count = count + 1; + + end + +endmodule + + +module initial_edge_n (res_n, + rst_n); + output res_n; + input rst_n; + + reg res_n = 1'b0; + + always @(negedge rst_n) begin + if (rst_n == 1'b0) begin + res_n <= 1'b1; + end + end + +endmodule // initial_edge_n + + +module initial_edge (res, + rst); + output res; + input rst; + + reg res = 1'b0; + + always @(posedge rst) begin + if (rst == 1'b1) begin + res <= 1'b1; + end + end + +endmodule // initial_edge
diff --git a/SVIncCompil/Testcases/Verilator/t_initial_inc.vh b/SVIncCompil/Testcases/Verilator/t_initial_inc.vh new file mode 100644 index 0000000..9aad43c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_initial_inc.vh
@@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +`define foo bar +`ifdef foo + `ifdef baz `else +// Test file to make sure includes work; + integer user_loaded_value; + `endif +`endif
diff --git a/SVIncCompil/Testcases/Verilator/t_inside.v b/SVIncCompil/Testcases/Verilator/t_inside.v new file mode 100644 index 0000000..de6baba --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inside.v
@@ -0,0 +1,69 @@ +// DESCRIPTION::Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t; + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + + typedef enum logic [1:0] + { ZERO = 2'd0, + ONE = 2'd1, + TWO = 2'd2, + THREE = 2'd3, + XXX = 2'dx + } num_t; + + function automatic logic is_odd; + input en; + input num_t number; + case (en) + 1'b1: begin + unique if (number inside {ONE, THREE}) + is_odd = 1'b1; + else if (number inside {ZERO, TWO}) + is_odd = 1'b0; + else + is_odd = 1'bx; + end + 1'b0: is_odd = 1'bx; + default: is_odd = 1'bx; + endcase + endfunction + + initial begin + `checkh ((4'd4 inside {4'd1,4'd5}), 1'b0); + `checkh ((4'd4 inside {4'd1,4'd4}), 1'b1); + // + `checkh ((4'b1011 inside {4'b1001}), 1'b0); + `checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==? + `checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==? + `checkh ((4'b1001 inside {4'b1??1}), 1'b1); +`ifndef VERILATOR + `checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx); +`endif + // Range + `checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches + `checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); + `checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); + `checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); + // + // Unsupported $ bound + // + // Unsupported if unpacked array, elements tranversed + //int unpackedarray [$] = '{8,9}; + //( expr inside {2, 3, unpackedarray}) // { 2,3,8,9} + // + `checkh (is_odd(1'b1, ZERO), 1'd0); + `checkh (is_odd(1'b1, ONE), 1'd1); + `checkh (is_odd(1'b1, TWO), 1'd0); + `checkh (is_odd(1'b1, THREE),1'd1); +`ifndef VERILATOR + `checkh (is_odd(1'b1, XXX), 1'dx); +`endif + // + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inside_wild.v b/SVIncCompil/Testcases/Verilator/t_inside_wild.v new file mode 100644 index 0000000..d0ed5f3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inside_wild.v
@@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [4:0] in = crc[4:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out), + // Inputs + .clk (clk), + .in (in[4:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h7a7bd4ee927e7cc3 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + //bug718 + + input clk; + + input logic [4:0] in; + + output logic out; + + always @(posedge clk) begin + out <= in inside {5'b1_1?1?}; + end + +endmodule // t \ No newline at end of file
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_aport.v b/SVIncCompil/Testcases/Verilator/t_inst_aport.v new file mode 100644 index 0000000..a5a258f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_aport.v
@@ -0,0 +1,109 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [15:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[15:0]), + // Inputs + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module callee (input [7:0] port [7:0], output [7:0] o); + assign o = ^{port[0], port[1], port[2], port[3], + port[4], port[5], port[6], port[7]}; +endmodule // callee + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [31:0] in; + output reg [15:0] out; + + wire [7:0] port [15:0]; + wire [7:0] goodport [7:0]; + + always_comb begin + port[0][7:0] = in[7:0]; + port[1][7:0] = in[16:8]; + port[2] = '0; + port[3] = '0; + port[4] = '0; + port[5] = '0; + port[6] = '0; + port[7] = '0; + end + + always_comb begin + goodport[0][7:0] = in[7:0]; + goodport[1][7:0] = in[16:8]; + goodport[2] = '0; + goodport[3] = '0; + goodport[4] = '0; + goodport[5] = '0; + goodport[6] = '0; + goodport[7] = '0; + end + + callee good (.port(goodport), .o(out[7:0])); + + // This is a slice, unsupported by other tools, bug711 + callee bad (.port(port[7:0]), .o(out[15:8])); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_array.v b/SVIncCompil/Testcases/Verilator/t_inst_array.v new file mode 100644 index 0000000..be559dc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_array.v
@@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + parameter ONE = 1; + + wire [17:10] bitout; + reg [7:0] allbits; + reg [15:0] onebit; + + sub sub [7:0] (allbits, onebit, bitout); + + integer x; + + always @ (posedge clk) begin + //$write("%x\n", bitout); + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + allbits <= 8'hac; + onebit <= 16'hc01a; + end + if (cyc==2) begin + if (bitout !== 8'h07) $stop; + allbits <= 8'hca; + onebit <= 16'h1f01; + end + if (cyc==3) begin + if (bitout !== 8'h41) $stop; + if (sub[0].bitout !== 1'b1) $stop; + if (sub[1].bitout !== 1'b0) $stop; +`ifndef verilator // Hacky array subscripting + if (sub[ONE].bitout !== 1'b0) $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +`ifdef USE_INLINE + `define INLINE_MODULE /*verilator inline_module*/ +`else + `define INLINE_MODULE /*verilator public_module*/ +`endif + +module sub (input [7:0] allbits, input [1:0] onebit, output bitout); + `INLINE_MODULE + assign bitout = (^ onebit) ^ (^ allbits); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_array_bad.v b/SVIncCompil/Testcases/Verilator/t_inst_array_bad.v new file mode 100644 index 0000000..f5f5989 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_array_bad.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + wire [7:0] bitout; + reg [7:0] allbits; + reg [7:0] onebit; + reg [8:0] onebitbad; // Wrongly sized + + sub sub [7:0] (allbits, onebitbad, bitout); + + // This is ok. + wire [9:8] b; + wire [1:0] c; + sub sub2 [9:8] (allbits,b,c); + +endmodule + +module sub (input [7:0] allbits, input onebit, output bitout); + assign bitout = onebit ^ (^ allbits); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_array_partial.v b/SVIncCompil/Testcases/Verilator/t_inst_array_partial.v new file mode 100644 index 0000000..f126015 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_array_partial.v
@@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [19:10] bitout; + wire [29:24] short_bitout; + wire [7:0] allbits; + wire [15:0] twobits; + + sub + i_sub1 [7:4] (.allbits (allbits), + .twobits (twobits[15:8]), + .bitout (bitout[17:14])), + i_sub2 [3:0] (.allbits (allbits), + .twobits (twobits[7:0]), + .bitout (bitout[13:10])); + + sub + i_sub3 [7:4] (.allbits (allbits), + .twobits (twobits[15:8]), + .bitout (bitout[17:14])); + + sub + i_sub4 [7:4] (.allbits (allbits), + .twobits (twobits[15:8]), + .bitout (short_bitout[27:24])); + + sub + i_sub5 [7:0] (.allbits (allbits), + .twobits (twobits), + .bitout (bitout[17:10])); + + sub + i_sub6 [7:4] (.allbits (allbits), + .twobits (twobits[15:8]), + .bitout ({bitout[18+:2],short_bitout[28+:2]})); + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Signals under test + assign allbits = crc[7:0]; + assign twobits = crc[15:0]; + wire [63:0] result = {48'h0, short_bitout, bitout}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'ha1da9ff8082a4ff6 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule // t + + +module sub + ( input wire [7:0] allbits, + input wire [1:0] twobits, + output wire bitout); + + assign bitout = (^ twobits) ^ (^ allbits); + +endmodule // sub
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_ccall.v b/SVIncCompil/Testcases/Verilator/t_inst_ccall.v new file mode 100644 index 0000000..42a69d5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_ccall.v
@@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + // verilator lint_on GENCLK + reg [31:0] long; + reg [63:0] quad; + wire [31:0] longout; + wire [63:0] quadout; + wire [7:0] narrow = long[7:0]; + sub sub (/*AUTOINST*/ + // Outputs + .longout (longout[31:0]), + .quadout (quadout[63:0]), + // Inputs + .narrow (narrow[7:0]), + .quad (quad[63:0])); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + long <= 32'h12345678; + quad <= 64'h12345678_abcdef12; + end + if (cyc==2) begin + if (longout !== 32'h79) $stop; + if (quadout !== 64'h12345678_abcdef13) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout); + // verilator public_module +`ifdef verilator + assign longout = $c32("(",narrow,"+1)"); + assign quadout = $c64("(",quad,"+1)"); +`else + assign longout = narrow + 8'd1; + assign quadout = quad + 64'd1; +`endif +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_comma.v b/SVIncCompil/Testcases/Verilator/t_inst_comma.v new file mode 100644 index 0000000..b8c6e43 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_comma.v
@@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + parameter ONE = 1; + + wire [17:10] bitout; + reg [7:0] allbits; + reg [15:0] onebit; + + sub #(1) + sub0 (allbits, onebit[1:0], bitout[10]), + sub1 (allbits, onebit[3:2], bitout[11]), + sub2 (allbits, onebit[5:4], bitout[12]), + sub3 (allbits, onebit[7:6], bitout[13]), + sub4 (allbits, onebit[9:8], bitout[14]), + sub5 (allbits, onebit[11:10], bitout[15]), + sub6 (allbits, onebit[13:12], bitout[16]), + sub7 (allbits, onebit[15:14], bitout[17]); + + integer x; + + always @ (posedge clk) begin + //$write("%x\n", bitout); + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + allbits <= 8'hac; + onebit <= 16'hc01a; + end + if (cyc==2) begin + if (bitout !== 8'h07) $stop; + allbits <= 8'hca; + onebit <= 16'h1f01; + end + if (cyc==3) begin + if (bitout !== 8'h41) $stop; + if (sub0.bitout !== 1'b1) $stop; + if (sub1.bitout !== 1'b0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +`ifdef USE_INLINE + `define INLINE_MODULE /*verilator inline_module*/ +`else + `define INLINE_MODULE /*verilator public_module*/ +`endif + +module sub (input [7:0] allbits, input [1:0] onebit, output bitout); + `INLINE_MODULE + parameter integer P = 0; + initial if (P != 1) $stop; + assign bitout = (^ onebit) ^ (^ allbits); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_darray.v b/SVIncCompil/Testcases/Verilator/t_inst_darray.v new file mode 100644 index 0000000..acf610e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_darray.v
@@ -0,0 +1,85 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by John Stevenson. + +typedef logic [63:0] uid_t; +typedef logic [31:0] value_t; + +interface the_intf #(parameter M = 5); + logic valid; + uid_t uid; + value_t [M-1:0] values; + + modport i( + output valid, + output uid, + output values + ); + modport t( + input valid, + input uid, + input values + ); +endinterface + +module Contemplator #( + parameter IMPL = 0, + parameter M = 5, + parameter N = 1 ) + ( + input logic clk, + the_intf.i out [N-1:0] + ); + + the_intf #(.M(M)) inp[N-1:0] (); + + DeepThought #( + .N ( N )) + ultimateAnswerer( + .src ( inp ), + .dst ( out )); +endmodule + +module DeepThought #( + parameter N = 1 ) + ( + the_intf.t src[N-1:0], + the_intf.i dst[N-1:0] + ); +endmodule + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + localparam M = 5; + localparam N = 1; + + the_intf #(.M(M)) out0 [N-1:0] (); + the_intf #(.M(M)) out1 [N-1:0] (); + + Contemplator #( + .IMPL ( 0 ), + .M ( M ), + .N ( N )) + contemplatorOfTheZerothKind( + .clk ( clk ), + .out ( out0 )); + + Contemplator #( + .IMPL ( 1 ), + .M ( M ), + .N ( N )) + contemplatorOfTheFirstKind( + .clk ( clk ), + .out ( out1 )); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_dff.v b/SVIncCompil/Testcases/Verilator/t_inst_dff.v new file mode 100644 index 0000000..053b427 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_dff.v
@@ -0,0 +1,131 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + localparam WIDTH = 31; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [WIDTH-1:0] b; // From test of Test.v + wire [WIDTH-1:0] c; // From test of Test.v + // End of automatics + reg rst_l; + + Test #(.WIDTH(WIDTH)) + test (/*AUTOINST*/ + // Outputs + .b (b[WIDTH-1:0]), + .c (c[WIDTH-1:0]), + // Inputs + .clk (clk), + .rst_l (rst_l), + .in (in[WIDTH-1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {1'h0, c, 1'b0, b}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + rst_l <= ~1'b1; + end + else if (cyc<10) begin + sum <= 64'h0; + rst_l <= ~1'b1; + // Hold reset while summing + end + else if (cyc<20) begin + rst_l <= ~1'b0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hbcfcebdb75ec9d32 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + b, c, + // Inputs + clk, rst_l, in + ); + + parameter WIDTH = 5; + + input clk; + input rst_l; + + input [WIDTH-1:0] in; + output wire [WIDTH-1:0] b; + output wire [WIDTH-1:0] c; + + dff # ( .WIDTH (WIDTH), + .RESET ('0), // Although this is a single bit, the parameter must be the specified type + .RESET_WIDTH (1) ) + sub1 + ( .clk(clk), .rst_l(rst_l), .q(b), .d(in) ); + + dff # ( .WIDTH (WIDTH), + .RESET ({ 1'b1, {(WIDTH-1){1'b0}} }), + .RESET_WIDTH (WIDTH)) + sub2 + ( .clk(clk), .rst_l(rst_l), .q(c), .d(in) ); + +endmodule + +module dff (/*AUTOARG*/ + // Outputs + q, + // Inputs + clk, rst_l, d + ); + + parameter WIDTH = 1; + parameter RESET = {WIDTH{1'b0}}; + parameter RESET_WIDTH = WIDTH; + + input clk; + input rst_l; + input [WIDTH-1:0] d; + output reg [WIDTH-1:0] q; + + always_ff @(posedge clk or negedge rst_l) begin + if ($bits(RESET) != RESET_WIDTH) $stop; + // verilator lint_off WIDTH + if (~rst_l) q <= RESET; + // verilator lint_on WIDTH + else q <= d; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_dtree.v b/SVIncCompil/Testcases/Verilator/t_inst_dtree.v new file mode 100644 index 0000000..11cfa9a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_dtree.v
@@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + +`ifdef INLINE_A //verilator inline_module +`else //verilator no_inline_module +`endif + + bmod bsub3 (.clk, .n(3)); + bmod bsub2 (.clk, .n(2)); + bmod bsub1 (.clk, .n(1)); + bmod bsub0 (.clk, .n(0)); +endmodule + +module bmod + (input clk, + input [31:0] n); + +`ifdef INLINE_B //verilator inline_module +`else //verilator no_inline_module +`endif + + cmod csub (.clk, .n); + +endmodule + +module cmod + (input clk, input [31:0] n); + +`ifdef INLINE_C //verilator inline_module +`else //verilator no_inline_module +`endif + + reg [31:0] clocal; + always @ (posedge clk) clocal <= n; + + dmod dsub (.clk, .n); +endmodule + +module dmod (input clk, input [31:0] n); + +`ifdef INLINE_D //verilator inline_module +`else //verilator no_inline_module +`endif + + reg [31:0] dlocal; + always @ (posedge clk) dlocal <= n; + + int cyc; + always @(posedge clk) begin + cyc <= cyc+1; + end + always @(posedge clk) begin + if (cyc>10) begin +`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif + if (csub.clocal !== n) $stop; + if (dlocal !== n) $stop; + end + if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_first.v b/SVIncCompil/Testcases/Verilator/t_inst_first.v new file mode 100644 index 0000000..293cb8f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_first.v
@@ -0,0 +1,128 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk, fastclk + ); + + input clk; + input fastclk; + + genvar unused; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire o_com; // From b of t_inst_first_b.v + wire o_seq_d1r; // From b of t_inst_first_b.v + // End of automatics + + integer _mode; // initial _mode=0 + reg na,nb,nc,nd,ne; + wire ma,mb,mc,md,me; + wire da,db,dc,dd,de; + reg [7:0] wa,wb,wc,wd,we; + wire [7:0] qa,qb,qc,qd,qe; + + wire [5:0] ra; + wire [4:0] rb; + wire [29:0] rc; + wire [63:0] rd; + reg [5:0] sa; + reg [4:0] sb; + reg [29:0] sc; + reg [63:0] sd; + + reg _guard1; initial _guard1=0; + wire [104:0] r_wide = {ra,rb,rc,rd}; + reg _guard2; initial _guard2=0; + wire [98:0] r_wide0 = {rb,rc,rd}; + reg _guard3; initial _guard3=0; + wire [93:0] r_wide1 = {rc,rd}; + reg _guard4; initial _guard4=0; + wire [63:0] r_wide2 = {rd}; + reg _guard5; initial _guard5=0; + wire [168:0] r_wide3 = {ra,rb,rc,rd,rd}; + reg [127:0] _guard6; initial _guard6=0; + + t_inst_first_a a ( + .clk (clk), + // Outputs + .o_w5 ({ma,mb,mc,md,me}), + .o_w5_d1r ({da,db,dc,dd,de}), + .o_w40 ({qa,qb,qc,qd,qe}), + .o_w104 ({ra,rb,rc,rd}), + // Inputs + .i_w5 ({na,nb,nc,nd,ne}), + .i_w40 ({wa,wb,wc,wd,we}), + .i_w104 ({sa,sb,sc,sd}) + ); + + reg i_seq; + reg i_com; + wire [15:14] o2_comhigh; + + t_inst_first_b b ( + .o2_com (o2_comhigh), + .i2_com ({i_com,~i_com}), + .wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd), + .wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd), + /*AUTOINST*/ + // Outputs + .o_seq_d1r (o_seq_d1r), + .o_com (o_com), + // Inputs + .clk (clk), + .i_seq (i_seq), + .i_com (i_com)); + + // surefire lint_off STMINI + initial _mode = 0; + + always @ (posedge fastclk) begin + if (_mode==1) begin + if (o_com !== ~i_com) $stop; + if (o2_comhigh !== {~i_com,i_com}) $stop; + end + end + + always @ (posedge clk) begin + //$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode, + // {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de}); + $write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r); + if (_mode==0) begin + $write("[%0t] t_inst: Running\n", $time); + _mode<=1; + {na,nb,nc,nd,ne} <= 5'b10110; + {wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he}; + {sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}; + // + i_seq <= 1'b1; + i_com <= 1'b1; + end + else if (_mode==1) begin + _mode<=2; + if ({ma,mb,mc,md,me} !== 5'b10110) $stop; + if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop; + if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop; + end + else if (_mode==2) begin + _mode<=3; + if ({da,db,dc,dd,de} !== 5'b10110) $stop; + if (o_seq_d1r !== ~i_seq) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin + $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); + $stop; + end + end + + // surefire lint_off UDDSDN + wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide}; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_first_a.v b/SVIncCompil/Testcases/Verilator/t_inst_first_a.v new file mode 100644 index 0000000..9fded34 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_first_a.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_inst_first_a (/*AUTOARG*/ + // Outputs + o_w5, o_w5_d1r, o_w40, o_w104, + // Inputs + clk, i_w5, i_w40, i_w104 + ); + + input clk; + + input [4:0] i_w5; + output [4:0] o_w5; + output [4:0] o_w5_d1r; + input [39:0] i_w40; + output [39:0] o_w40; + input [104:0] i_w104; + output [104:0] o_w104; + + wire [4:0] o_w5 = i_w5; + wire [39:0] o_w40 = i_w40; + wire [104:0] o_w104 = i_w104; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [4:0] o_w5_d1r; + // End of automatics + + always @ (posedge clk) begin + o_w5_d1r <= i_w5; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_first_b.v b/SVIncCompil/Testcases/Verilator/t_inst_first_b.v new file mode 100644 index 0000000..0984293 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_first_b.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_inst_first_b (/*AUTOARG*/ + // Outputs + o_seq_d1r, o_com, o2_com, + // Inputs + clk, i_seq, i_com, i2_com, wide_for_trace, wide_for_trace_2 + ); + // verilator inline_module + + input clk; + + input i_seq; + output o_seq_d1r; + input i_com; + output o_com; + input [1:0] i2_com; + output [1:0] o2_com; + input [127:0] wide_for_trace; + input [127:0] wide_for_trace_2; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + // End of automatics + + reg o_seq_d1r; + always @ (posedge clk) begin + o_seq_d1r <= ~i_seq; + end + + wire [1:0] o2_com = ~i2_com; + wire o_com = ~i_com; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_implicit.v b/SVIncCompil/Testcases/Verilator/t_inst_implicit.v new file mode 100644 index 0000000..f1875ce --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_implicit.v
@@ -0,0 +1,50 @@ +// DESCRIPTION:tor:ilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [31:0] o; + wire [31:0] oe; + + Test test (/*AUTOINST*/ + // Outputs + .o (o[31:0]), + .oe (oe[31:0])); + + // Test loop + always @ (posedge clk) begin + if (o !== 32'h00000001) $stop; + if (oe !== 32'h00000001) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module subimp(o,oe); + output [31:0] o; + assign o = 32'h12345679; + output [31:0] oe; + assign oe = 32'hab345679; +endmodule + +module Test(o,oe); + output [31:0] o; + output [31:0] oe; + wire [31:0] xe; + assign xe[31:1] = 0; + // verilator lint_off IMPLICIT + // verilator lint_off WIDTH + subimp subimp(x, // x is implicit and one bit + xe[0]); // xe explicit one bit + assign o = x; + assign oe = xe; + // verilator lint_on WIDTH + // verilator lint_on IMPLICIT +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_misarray_bad.v b/SVIncCompil/Testcases/Verilator/t_inst_misarray_bad.v new file mode 100644 index 0000000..3af9f7b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_misarray_bad.v
@@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + logic foo; initial foo = 0; + +// dut #(.W(4)) udut(.*); + dut #(.W(4)) udut(.clk(clk), + .foo(foo)); // Assigning logic to logic array + +endmodule + +module dut + #(parameter W = 1) + (input logic clk, + input logic foo[W-1:0]); + + genvar i; + generate + for (i = 0; i < W; i++) begin + suba ua(.clk(clk), .foo(foo[i])); + end + endgenerate +endmodule + +module suba + (input logic clk, + input logic foo); + + always @(posedge clk) + $display("foo=%b", foo); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_mism.v b/SVIncCompil/Testcases/Verilator/t_inst_mism.v new file mode 100644 index 0000000..bf1710b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_mism.v
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Alex Solomatnikov. + +//bug595 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + logic [6-1:0] foo; initial foo = 20; + + dut #(.W(6)) udut(.clk(clk), + .foo(foo-16)); +endmodule + +module dut + #(parameter W = 1) + (input logic clk, + input logic [W-1:0] foo); + + genvar i; + generate + for (i = 0; i < W; i++) begin + suba ua(.clk(clk), .foo(foo[i])); + end + endgenerate +endmodule + +module suba + (input logic clk, + input logic foo); + + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_missing.v b/SVIncCompil/Testcases/Verilator/t_inst_missing.v new file mode 100644 index 0000000..e2ea9c1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_missing.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/); + wire ok = 1'b0; + // verilator lint_off PINNOCONNECT + // verilator lint_off PINCONNECTEMPTY + sub sub (.ok(ok), , .nc()); + // verilator lint_on PINCONNECTEMPTY + // verilator lint_on PINNOCONNECT +endmodule + +module sub (input ok, input none, input nc); + initial if (ok && none && nc) begin end // No unused warning +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_missing_bad.v b/SVIncCompil/Testcases/Verilator/t_inst_missing_bad.v new file mode 100644 index 0000000..74089d3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_missing_bad.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/); + wire ok = 1'b0; + sub sub (.ok(ok), , .nc()); +endmodule + +module sub (input ok, input none, input nc, input missing); + initial if (ok && none && nc && missing) begin end // No unused warning +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_mnpipe.v b/SVIncCompil/Testcases/Verilator/t_inst_mnpipe.v new file mode 100644 index 0000000..1839e7b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_mnpipe.v
@@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + + reg [7:0] crc; + reg [2:0] sum; + wire [2:0] in = crc[2:0]; + wire [2:0] out; + + MxN_pipeline pipe (in, out, clk); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum); + cyc <= cyc + 1; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==0) begin + // Setup + crc <= 8'hed; + sum <= 3'h0; + end + else if (cyc>10 && cyc<90) begin + sum <= {sum[1:0],sum[2]} ^ out; + end + else if (cyc==99) begin + if (crc !== 8'b01110000) $stop; + if (sum !== 3'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module dffn (q,d,clk); + parameter BITS = 1; + + input [BITS-1:0] d; + output reg [BITS-1:0] q; + input clk; + + always @ (posedge clk) begin + q <= d; + end + +endmodule + +module MxN_pipeline (in, out, clk); + parameter M=3, N=4; + + input [M-1:0] in; + output [M-1:0] out; + input clk; + + // Unsupported: Per-bit array instantiations with output connections to non-wires. + //wire [M*(N-1):1] t; + //dffn #(M) p[N:1] ({out,t},{t,in},clk); + + wire [M*(N-1):1] w; + wire [M*N:1] q; + dffn #(M) p[N:1] (q,{w,in},clk); + assign {out,w} = q; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_notunsized.v b/SVIncCompil/Testcases/Verilator/t_inst_notunsized.v new file mode 100644 index 0000000..bf62f8f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_notunsized.v
@@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [71:0] muxed; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .muxed (muxed[71:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {muxed[63:0]}; + + wire [5:0] width_check = cyc[5:0] + 1; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h20050a66e7b253d1 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + muxed, + // Inputs + clk, in + ); + input clk; + input [31:0] in; + output [71:0] muxed; + + wire [71:0] a = {in[7:0],~in[31:0],in[31:0]}; + wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]}; + + /*AUTOWIRE*/ + Muxer muxer ( + .sa (0), + .sb (in[0]), + /*AUTOINST*/ + // Outputs + .muxed (muxed[71:0]), + // Inputs + .a (a[71:0]), + .b (b[71:0])); +endmodule + +module Muxer (/*AUTOARG*/ + // Outputs + muxed, + // Inputs + sa, sb, a, b + ); + input sa; + input sb; + + output wire [71:0] muxed; + input [71:0] a; + input [71:0] b; + + // Constification wasn't sizing with inlining and gave + // unsized error on below + // v + assign muxed = (({72{sa}} & a) + | ({72{sb}} & b)); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_overwide.v b/SVIncCompil/Testcases/Verilator/t_inst_overwide.v new file mode 100644 index 0000000..339cfc0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_overwide.v
@@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + outc_w30, outd_w73, + // Inputs + clk, ina_w1, inb_w61 + ); + + input clk; + + input ina_w1; + input [60:0] inb_w61; + output [29:0] outc_w30; + output [72:0] outd_w73; + + sub sub ( + // Outputs + .outy_w92 (outc_w30), // .large => (small) + .outz_w22 (outd_w73), // .small => (large) + // Inputs + .clk (clk), + .inw_w31 (ina_w1), // .large <= (small) + .inx_w11 (inb_w61) // .small <= (large) + ); + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + outy_w92, outz_w22, + // Inputs + clk, inw_w31, inx_w11 + ); + + input clk; + input [30:0] inw_w31; + input [10:0] inx_w11; + output reg [91:0] outy_w92 /*verilator public*/; + output reg [21:0] outz_w22 /*verilator public*/; + + always @(posedge clk) begin + outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00}; + outz_w22 <= {inx_w11[10:0],inx_w11[10:0]}; + end + +endmodule // regfile
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_port_array.v b/SVIncCompil/Testcases/Verilator/t_inst_port_array.v new file mode 100644 index 0000000..dd697f0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_port_array.v
@@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Alex Solomatnikov. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + logic [6-1:0] foo[4-1:0]; + + //initial $display("%m: %p\n", foo); + //initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice + //logic [6-1:0] foo2[4-1:0][5:6]; + //initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal + + dut #(.W(6), + .D(4)) udut(.clk(clk), + .foo(foo[4-1:0])); +endmodule + +module dut + #(parameter W = 1, + parameter D = 1) + (input logic clk, + input logic [W-1:0] foo[D-1:0]); + + genvar i, j; + generate + for (j = 0; j < D; j++) begin + for (i = 0; i < W; i++) begin + suba ua(.clk(clk), .foo(foo[j][i])); + end + end + endgenerate +endmodule + +module suba + (input logic clk, + input logic foo); + + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_prepost.v b/SVIncCompil/Testcases/Verilator/t_inst_prepost.v new file mode 100644 index 0000000..a00ecf9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_prepost.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t; + sub #(10,11,12,13) sub (); + +endmodule + +module sub (); + parameter A = 0; + parameter B = 1; + + ip ip(); + + parameter C = 2; + parameter D = 3; + + initial begin + if (A!=10) $stop; + if (B!=11) $stop; + if (C!=12) $stop; + if (D!=13) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module ip; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_recurse2_bad.v b/SVIncCompil/Testcases/Verilator/t_inst_recurse2_bad.v new file mode 100644 index 0000000..bbf6496 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_recurse2_bad.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + looped looped (); + +endmodule + +module looped (/*AUTOARG*/); + looped looped (); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_recurse_bad.v b/SVIncCompil/Testcases/Verilator/t_inst_recurse_bad.v new file mode 100644 index 0000000..f0a28be --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_recurse_bad.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + looped looped (); + +endmodule + +module looped (/*AUTOARG*/); + looped2 looped2 (); +endmodule + +module looped2 (/*AUTOARG*/); + looped looped (); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_signed.v b/SVIncCompil/Testcases/Verilator/t_inst_signed.v new file mode 100644 index 0000000..c92c0e3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_signed.v
@@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + + wire signed [7:0] sgn_wide; + wire [7:0] unsgn_wide; + + // The instantiation will Z extend, not sign extend + // verilator lint_off WIDTH + sub sub (.clk, + .sgn(sgn_wide), .unsgn(unsgn_wide), + .iss(3'sh7), .isu(3'h7), + .ius(3'sh7), .iuu(3'h7)); + // verilator lint_on WIDTH + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide); +`endif + if (sgn_wide[2:0] != 3'sh7) $stop; + if (unsgn_wide[2:0] != 3'h7) $stop; + // Simulators differ here. + if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC + && sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS + if (unsgn_wide !== 8'sbzzzzz111 + && unsgn_wide!== 8'sb00000111) $stop; + cyc <= cyc + 1; + if (cyc==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub ( + input clk, + output wire signed [2:0] sgn, + output wire [2:0] unsgn, + input signed [7:0] iss, + input signed [7:0] isu, + input [7:0] ius, + input [7:0] iuu); + assign sgn = 3'sh7; + assign unsgn = 3'h7; + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("in: %x %x %x %x\n", iss, isu, ius, iuu); + if (iss != 8'hff) $stop; + if (isu != 8'h07) $stop; + if (ius != 8'hff) $stop; + if (iuu != 8'h07) $stop; +`endif + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_signed1.v b/SVIncCompil/Testcases/Verilator/t_inst_signed1.v new file mode 100644 index 0000000..df32510 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_signed1.v
@@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg signed i; + wire signed o1; + wire signed o2; + + integer cyc; initial cyc=0; + + sub1 sub1 (.i(i), .o(o1)); + sub2 sub2 (.i(o1), .o(o2)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + i <= 1'b0; + end + else if (cyc==1) begin + if (o2 != 1'b0) $stop; + i <= 1'b1; + end + else if (cyc==2) begin + if (o2 != 1'b1) $stop; + end + if (cyc==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +//msg2540 +module sub1 ( + input signed i, + output wire signed o); + assign o = ~i; +endmodule + +module sub2 (i,o); + input signed i; + output signed o; + wire signed o = ~i; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_slice.v b/SVIncCompil/Testcases/Verilator/t_inst_slice.v new file mode 100644 index 0000000..55a4c35 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_slice.v
@@ -0,0 +1,84 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Varun Koyyalagunta. + +// bug1015 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [1:0] i = crc[1:0]; + logic [1:0] o [13:10] ; + + Test test (/*AUTOINST*/ + // Outputs + .o (o/*[1:0].[3:0]*/), + // Inputs + .i (i[1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n",$time, cyc, crc, result, sum); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hb42b2f48a0a9375a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( + output logic [1:0] o [3:0], + //but this works + //logic [N-1:0] o + input [1:0] i); + + parameter N = 4; + + logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3}; + + sub sub [N-1:0] (.o (o), // many-to-many + .a (a), // many-to-many + .i (i)); // many-to-one +endmodule + +module sub + ( + input logic [1:0] i, + input logic [1:0] a, + output logic [1:0] o + ); + assign o = i + a; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_sv.v b/SVIncCompil/Testcases/Verilator/t_inst_sv.v new file mode 100644 index 0000000..e92973c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_sv.v
@@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + +`ifdef verilator // Otherwise need it in every module, including test, but that'll make a mess + timeunit 1ns; + timeprecision 1ns; +`endif + + input clk; + integer cyc; initial cyc=1; + + supply0 [1:0] low; + supply1 [1:0] high; + + reg [7:0] isizedwire; + reg ionewire; + + wire oonewire; + wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v + + t_inst sub + ( + .osizedreg, + .oonewire, + // Inputs + .isizedwire (isizedwire[7:0]), + .* + //.ionewire (ionewire) + ); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + ionewire <= 1'b1; + isizedwire <= 8'd8; + end + if (cyc==2) begin + if (low != 2'b00) $stop; + if (high != 2'b11) $stop; + if (oonewire !== 1'b1) $stop; + if (isizedwire !== 8'd8) $stop; + end + if (cyc==3) begin + ionewire <= 1'b0; + isizedwire <= 8'd7; + end + if (cyc==4) begin + if (oonewire !== 1'b0) $stop; + if (isizedwire !== 8'd7) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +module t_inst + ( + output reg [7:0] osizedreg, + output wire oonewire /*verilator public*/, + input [7:0] isizedwire, + input wire ionewire + ); + + assign oonewire = ionewire; + + always @* begin + osizedreg = isizedwire; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_tree.v b/SVIncCompil/Testcases/Verilator/t_inst_tree.v new file mode 100644 index 0000000..9065d6b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_tree.v
@@ -0,0 +1,104 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + // verilator lint_off GENCLK + reg printclk; + // verilator lint_on GENCLK + ps ps (printclk); + + reg [7:0] a; + wire [7:0] z; + + l1 u (~a,z); + + always @ (posedge clk) begin + printclk <= 0; + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + printclk <= 1'b1; + end + if (cyc==2) begin + a <= 8'b1; + end + if (cyc==3) begin + if (z !== 8'hf8) $stop; + //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; + //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; + //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; + //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; + //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; + //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +`ifdef USE_INLINE + `define INLINE_MODULE /*verilator inline_module*/ +`else + `define INLINE_MODULE /*verilator public_module*/ +`endif + +`ifdef USE_PUBLIC + `define PUBLIC /*verilator public*/ +`else + `define PUBLIC +`endif + +module ps (input printclk); + `INLINE_MODULE + // Check that %m stays correct across inlines + always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time); +endmodule + +module l1 (input [7:0] a, output [7:0] z `PUBLIC); + `INLINE_MODULE + wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; + assign z = z0+z1; + l2 u0 (a, z0); l2 u1 (a, z1); +endmodule + +module l2 (input [7:0] a, output [7:0] z `PUBLIC); + `INLINE_MODULE + wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l3 u0 (a, z0); l3 u1 (a1, z1); +endmodule + +module l3 (input [7:0] a, output [7:0] z `PUBLIC); + `INLINE_MODULE + wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l4 u0 (a, z0); l4 u1 (a1, z1); +endmodule + +module l4 (input [7:0] a, output [7:0] z `PUBLIC); + `INLINE_MODULE + wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1); +endmodule + +module l5 (input [7:0] a, output [7:0] z `PUBLIC); + `INLINE_MODULE + parameter PARAM = 5; + wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; + assign z = a; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_v2k.v b/SVIncCompil/Testcases/Verilator/t_inst_v2k.v new file mode 100644 index 0000000..b2340e0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_v2k.v
@@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + supply0 [1:0] low; + supply1 [1:0] high; + + reg [7:0] isizedwire; + reg ionewire; + +`ifdef never_just_for_verilog_mode + wire oonewire; // From sub of t_inst_v2k__sub.v +`endif + + wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v + wire [1:0] tied; + wire [3:0] tied_also; + + hello hsub (.tied_also); + + // Double underscore tests bug631 + t_inst_v2k__sub sub + ( + // Outputs + .osizedreg (osizedreg[7:0]), + // verilator lint_off IMPLICIT + .oonewire (oonewire), + // verilator lint_on IMPLICIT + .tied (tied[1:0]), + // Inputs + .isizedwire (isizedwire[7:0]), + .ionewire (ionewire)); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + ionewire <= 1'b1; + isizedwire <= 8'd8; + end + if (cyc==2) begin + if (low != 2'b00) $stop; + if (high != 2'b11) $stop; + if (oonewire !== 1'b1) $stop; + if (isizedwire !== 8'd8) $stop; + if (tied != 2'b10) $stop; + if (tied_also != 4'b1010) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module hello(tied_also); + initial $write ("Hello\n"); + output reg [3:0] tied_also = 4'b1010; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_inst_wideconst.v b/SVIncCompil/Testcases/Verilator/t_inst_wideconst.v new file mode 100644 index 0000000..5e84235 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_inst_wideconst.v
@@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [41:0] aaa; + wire [41:0] bbb; + + // verilator public_module + wire [41:0] z_0; + wire [41:0] z_1; + + wide w_0( + .xxx( { {40{1'b0}},2'b11 } ), + .yyy( aaa[1:0] ), + .zzz( z_0 ) + ); + + wide w_1( + .xxx( aaa ), + .yyy( 2'b10 ), + .zzz( z_1 ) + ); + + assign bbb= z_0 + z_1; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + aaa <= 42'b01; + end + if (cyc==2) begin + aaa <= 42'b10; + if (z_0 != 42'h4) $stop; + if (z_1 != 42'h3) $stop; + end + if (cyc==3) begin + if (z_0 != 42'h5) $stop; + if (z_1 != 42'h4) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module wide ( + input [41:0] xxx, + input [1:0] yyy, + output [41:0] zzz + ); + // verilator public_module + + assign zzz = xxx+ { {40{1'b0}},yyy }; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface.v b/SVIncCompil/Testcases/Verilator/t_interface.v new file mode 100644 index 0000000..1a9b8f0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface.v
@@ -0,0 +1,169 @@ +// DESCRIPTION: Verilator: SystemVerilog interface test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic rst = 1'b1; // reset + integer rst_cnt = 0; + + // reset is removed after a delay + always @ (posedge clk) + begin + rst_cnt <= rst_cnt + 1; + rst <= rst_cnt <= 3; + end + + // counters + int cnt; + int cnt_src; + int cnt_drn; + + // add all counters + assign cnt = cnt_src + cnt_drn + inf.cnt; + + // finish report + always @ (posedge clk) + if (cnt == 3*16) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // interface instance + handshake inf ( + .clk (clk), + .rst (rst) + ); + + // source instance + source #( + .RW (8), + .RP (8'b11100001) + ) source ( + .clk (clk), + .rst (rst), + .inf (inf), + .cnt (cnt_src) + ); + + // drain instance + drain #( + .RW (8), + .RP (8'b11010100) + ) drain ( + .clk (clk), + .rst (rst), + .inf (inf), + .cnt (cnt_drn) + ); + +endmodule : t + + +// interface definition +interface handshake #( + parameter int unsigned WC = 32 +)( + input logic clk, + input logic rst +); + + // modport signals + logic req; // request + logic grt; // grant + logic inc; // increment + + // local signals + integer cnt; // counter + + // source + modport src ( + output req, + input grt + ); + + // drain + modport drn ( + input req, + output grt + ); + + // incremet condition + assign inc = req & grt; + + // local logic (counter) + always @ (posedge clk, posedge rst) + if (rst) cnt <= '0; + else cnt <= cnt + {31'h0, inc}; + +endinterface : handshake + + +// source module +module source #( + // random generator parameters + parameter int unsigned RW=1, // LFSR width + parameter bit [RW-1:0] RP='0, // LFSR polinom + parameter bit [RW-1:0] RR='1 // LFSR reset state +)( + input logic clk, + input logic rst, + handshake.src inf, + output integer cnt +); + + // LFSR + logic [RW-1:0] rnd; + + // LFSR in Galois form + always @ (posedge clk, posedge rst) + if (rst) rnd <= RR; + else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); + + // counter + always @ (posedge clk, posedge rst) + if (rst) cnt <= 32'd0; + else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; + + // request signal + assign inf.req = rnd[0]; + +endmodule : source + + +// drain module +module drain #( + // random generator parameters + parameter int unsigned RW=1, // LFSR width + parameter bit [RW-1:0] RP='0, // LFSR polinom + parameter bit [RW-1:0] RR='1 // LFSR reset state +)( + input logic clk, + input logic rst, + handshake.drn inf, + output integer cnt +); + + // LFSR + logic [RW-1:0] rnd; + + // LFSR in Galois form + always @ (posedge clk, posedge rst) + if (rst) rnd <= RR; + else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); + + // counter + always @ (posedge clk, posedge rst) + if (rst) cnt <= 32'd0; + else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; + + // grant signal + assign inf.grt = rnd[0]; + +endmodule : drain
diff --git a/SVIncCompil/Testcases/Verilator/t_interface1.v b/SVIncCompil/Testcases/Verilator/t_interface1.v new file mode 100644 index 0000000..3b3f916 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface1.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// Very simple test for interface pathclearing + +interface ifc; + logic [3:0] value; +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc itop(); + + sub c1 (.isub(itop), + .i_value(4'h4)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison + if (itop.value != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub + ( + ifc isub, + input logic [3:0] i_value + ); + + always @* begin + isub.value = i_value; + end +endmodule : sub
diff --git a/SVIncCompil/Testcases/Verilator/t_interface1_modport.v b/SVIncCompil/Testcases/Verilator/t_interface1_modport.v new file mode 100644 index 0000000..bf69233 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface1_modport.v
@@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// Very simple test for interface pathclearing + +interface ifc; + integer hidden_from_isub; + integer value; + modport out_modport (output value); +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc itop(); + + sub c1 (.isub(itop), + .i_value(4)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (itop.value != 4) $stop; + itop.hidden_from_isub = 20; + if (itop.hidden_from_isub != 20) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub +`ifdef NANSI // bug868 + ( + isub, i_value + ); + ifc.out_modport isub; // Note parenthesis are not legal here + input integer i_value; +`else + ( + ifc.out_modport isub, + input integer i_value + ); +`endif + + always @* begin + isub.value = i_value; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface2.v b/SVIncCompil/Testcases/Verilator/t_interface2.v new file mode 100644 index 0000000..efe2611 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface2.v
@@ -0,0 +1,108 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + counter_io c1_data(); + counter_io c2_data(); + //counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells + counter_io c3_data(); + + counter_ansi c1 (.clkm(clk), + .c_data(c1_data), + .i_value(4'h1)); + counter_ansi c2 (.clkm(clk), + .c_data(c2_data), + .i_value(4'h2)); +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + /**/ c3 (.clkm(clk), + .c_data(c3_data), + .i_value(4'h3)); + + initial begin + c1_data.value = 4'h4; + c2_data.value = 4'h5; + c3_data.value = 4'h6; + end + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc<2) begin + c1_data.reset <= 1; + c2_data.reset <= 1; + c3_data.reset <= 1; + end + if (cyc==2) begin + c1_data.reset <= 0; + c2_data.reset <= 0; + c3_data.reset <= 0; + end + if (cyc==3) begin + if (c1_data.get_lcl() != 12345) $stop; + end + if (cyc==20) begin + $write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc, + c1_data.value, c1_data.reset, + c2_data.value, c2_data.reset, + c3_data.value, c3_data.reset); + if (c1_data.value != 2) $stop; + if (c2_data.value != 3) $stop; + if (c3_data.value != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +interface counter_io; + logic [3:0] value; + logic reset; + integer lcl; + task set_lcl (input integer a); lcl=a; endtask + function integer get_lcl (); return lcl; endfunction +endinterface + +interface ifunused; + logic unused; +endinterface + +module counter_ansi + ( + input clkm, + counter_io c_data, + input logic [3:0] i_value + ); + + initial begin + c_data.set_lcl(12345); + end + + always @ (posedge clkm) begin + c_data.value <= c_data.reset ? i_value : c_data.value + 1; + end +endmodule : counter_ansi + +`ifndef VERILATOR +// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. +module counter_nansi(clkm, c_data, i_value); + input clkm; + counter_io c_data; + input logic [3:0] i_value; + + always @ (posedge clkm) begin + c_data.value <= c_data.reset ? i_value : c_data.value + 1; + end +endmodule : counter_nansi +`endif + +module modunused (ifunused ifinunused); + ifunused ifunused(); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_array.v b/SVIncCompil/Testcases/Verilator/t_interface_array.v new file mode 100644 index 0000000..820b7f3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_array.v
@@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +interface foo_intf; + logic a; + + modport source ( + output a + ); + + modport sink ( + input a + ); +endinterface + +function integer identity (input integer val); + return val; +endfunction + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam N = 5; + + logic [N-1:0] a_in; + logic [N-1:0] a_out; + logic [N-1:0] ack_out; + + foo_intf foos [N-1:0] (); + + // Deferred link dotting with genvars + generate + genvar i; + for (i = 0; i < N-4; i++) begin : someLoop + assign ack_out[i] = a_in[i]; + assign foos[i].a = a_in[i]; + assign a_out[i] = foos[i].a; + end + endgenerate + + // Defferred link dotting with localparam + localparam THE_LP = N-3; + assign ack_out[THE_LP] = a_in[THE_LP]; + assign foos[THE_LP].a = a_in[THE_LP]; + assign a_out[THE_LP] = foos[THE_LP].a; + + // Defferred link dotting with arithmetic expression + assign ack_out[N-2] = a_in[N-2]; + assign foos[N-2].a = a_in[N-2]; + assign a_out[N-2] = foos[N-2].a; + + // Defferred link dotting with funcrefs + assign ack_out[identity(N-1)] = a_in[identity(N-1)]; + assign foos[identity(N-1)].a = a_in[identity(N-1)]; + assign a_out[identity(N-1)] = foos[identity(N-1)].a; + + initial a_in = '0; + always @(posedge clk) begin + a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; + + if (ack_out != a_out) begin + $display("%%Error: Interface and non-interface paths do not match: 0b%b 0b%b", + ack_out, a_out); + $stop; + end + + if (& a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_array_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_array_bad.v new file mode 100644 index 0000000..2f55084 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_array_bad.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Demonstrate deferred linking error messages +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +interface foo_intf; + logic a; +endinterface + +function integer the_other_func (input integer val); + return val; +endfunction + +module t (/*AUTOARG*/); + + localparam N = 4; + + foo_intf foos [N-1:0] (); + logic [ 7 : 0 ] bar; + + // Non-constant dotted select is not allowed + assign foos[bar].a = 1'b1; + + baz baz_inst (); + + // Unsure how to produce V3Param AstCellRef visitor errors + //assign baz_inst.x = 1'b1; + //assign baz_inst.N = 1'b1; + //assign baz_inst.7 = 1'b1; + //assign baz_inst.qux_t = 1'b1; + //assign baz_inst.the_func = 1'b1; + //assign baz_inst.the_lp = 1'b1; + + //assign bar.x = 1'b1; + //assign fake_inst.x = 1'b1; + //assign the_other_func.x = 1'b1; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module baz; + typedef integer qux_t; + + function integer the_func (input integer val); + return val; + endfunction + + localparam the_lp = 5; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_array_modport.v b/SVIncCompil/Testcases/Verilator/t_interface_array_modport.v new file mode 100644 index 0000000..cc6c5dc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_array_modport.v
@@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Connecting an interface array slice to a module's portmap +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +interface foo_intf; + logic a; + + modport m(input a); +endinterface + +module foo_mod + ( + foo_intf foo, + foo_intf.m bars[4] + ); +endmodule + +module t (/*AUTOARG*/); + + localparam N = 4; + + foo_intf foos [N-1:0] (); + foo_intf bars [N] (); + //foo_intf foos (); + + foo_mod + foo_mod + ( + .foo (foos[2]), + .bars (bars) + //.foo (foos) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_array_nocolon.v b/SVIncCompil/Testcases/Verilator/t_interface_array_nocolon.v new file mode 100644 index 0000000..a30690a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_array_nocolon.v
@@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Mike Popoloski. + +interface foo_intf + ( + input x + ); +endinterface + +module foo_subm + ( + input x + ); +endmodule + +module t (); + + localparam N = 3; + + wire [2:0] X = 3'b110; + + // Should not cause LITENDIAN warning, as no harm in array selections. + // verilator lint_on LITENDIAN + foo_intf foo1 [N] (.x(1'b1)); + foo_subm sub1 [N] (.x(1'b1)); + + // Will cause LITENDIAN warning? + // verilator lint_off LITENDIAN + foo_intf foos [N] (.x(X)); + foo_intf fool [1:3] (.x(X)); + foo_intf foom [3:1] (.x(X)); + + foo_subm subs [N] (.x(X)); + foo_subm subl [1:3] (.x(X)); + foo_subm subm [3:1] (.x(X)); + + initial begin + // Check numbering with 0 first + // NC has a bug here + if (foos[0].x !== 1'b1) $stop; + if (foos[1].x !== 1'b1) $stop; + if (foos[2].x !== 1'b0) $stop; + // + if (fool[1].x !== 1'b1) $stop; + if (fool[2].x !== 1'b1) $stop; + if (fool[3].x !== 1'b0) $stop; + // + if (foom[1].x !== 1'b0) $stop; + if (foom[2].x !== 1'b1) $stop; + if (foom[3].x !== 1'b1) $stop; + // + if (subs[0].x !== 1'b1) $stop; + if (subs[1].x !== 1'b1) $stop; + if (subs[2].x !== 1'b0) $stop; + // + if (subl[1].x !== 1'b1) $stop; + if (subl[2].x !== 1'b1) $stop; + if (subl[3].x !== 1'b0) $stop; + // + if (subm[1].x !== 1'b0) $stop; + if (subm[2].x !== 1'b1) $stop; + if (subm[3].x !== 1'b1) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_array_nocolon_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_array_nocolon_bad.v new file mode 100644 index 0000000..0056d5d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_array_nocolon_bad.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Mike Popoloski. + +interface foo_intf + ( + input x + ); +endinterface + +module foo_subm + ( + input x + ); +endmodule + +module t (); + + localparam N = 3; + + wire [2:0] X = 3'b110; + + // Will cause LITENDIAN warning? + foo_intf foos [N] (.x(X)); // bad + foo_intf fool [1:3] (.x(X)); // bad + foo_intf foom [3:1] (.x(X)); // ok + + foo_subm subs [N] (.x(X)); // bad + foo_subm subl [1:3] (.x(X)); // bad + foo_subm subm [3:1] (.x(X)); // ok +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_arraymux.v b/SVIncCompil/Testcases/Verilator/t_interface_arraymux.v new file mode 100644 index 0000000..e9345a5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_arraymux.v
@@ -0,0 +1,120 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by John Stevenson. + +package pkg; + typedef logic [31:0] unique_id_t; + typedef struct packed { + unique_id_t foo; + } inner_thing_t; + typedef struct packed { + inner_thing_t bar; + inner_thing_t baz; + } outer_thing_t; + +endpackage + +import pkg::*; + +interface the_intf + #(parameter M=5); + outer_thing_t [M-1:0] things; + logic valid; + modport i ( + output things, + output valid); + modport t ( + input things, + input valid); +endinterface + +module ThingMuxOH + #( + parameter NTHINGS = 1, + parameter M = 5 ) + ( + input logic [NTHINGS-1:0] select_oh, + the_intf.t things_in [NTHINGS-1:0], + the_intf.i thing_out + ); +endmodule + +module Thinker + #( + parameter M = 5, + parameter N = 2) + ( + input logic clk, + input logic reset, + input unique_id_t uids[0:N-1], + the_intf.t thing_inp, + the_intf.i thing_out + ); + + the_intf #(.M(M)) curr_things [N-1:0] (); + the_intf #(.M(M)) prev_things [N-1:0] (); + the_intf #(.M(M)) curr_thing (); + the_intf #(.M(M)) prev_thing (); + + logic [N-1:0] select_oh; + + // 1st mux: + ThingMuxOH #( + .NTHINGS ( N ), + .M ( M )) + curr_thing_mux( + .select_oh( select_oh ), + .things_in( curr_things ), + .thing_out( curr_thing )); + + // 2nd mux, comment this out and no problem: + ThingMuxOH #( + .NTHINGS ( N ), + .M ( M )) + prev_thing_mux( + .select_oh( select_oh ), + .things_in( prev_things ), + .thing_out( prev_thing )); + +endmodule + +module t + ( + input logic clk, + input logic reset + ); + + localparam M = 5; + localparam N = 2; + + unique_id_t uids[0:N-1]; + + the_intf #(.M(M)) thing_inp(); + the_intf #(.M(M)) thing_out(); + + Thinker #( + .M ( M ), + .N ( N )) + thinker( + .clk ( clk ), + .reset ( reset ), + .uids ( uids ), + .thing_inp( thing_inp ), + .thing_out( thing_out )); + + // Previously there was a problem in V3Inst if non-default parameters was used + localparam K = 2; + the_intf #(.M(K)) thing_inp2(); + the_intf #(.M(K)) thing_out2(); + + Thinker #( + .M ( K ), + .N ( N )) + thinker2( + .clk ( clk ), + .reset ( reset ), + .uids ( uids ), + .thing_inp( thing_inp2 ), + .thing_out( thing_out2 )); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_bind_public.v b/SVIncCompil/Testcases/Verilator/t_interface_bind_public.v new file mode 100644 index 0000000..c108517 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_bind_public.v
@@ -0,0 +1,129 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Alex Solomatnikov. + +interface hex2ram_if + ( + input bit trigger + ); + + string instance_path = $sformatf("%m"); + string testfile = ""; + bit has_testfile = |($value$plusargs("testfile=%s", testfile)); + bit armed = 1'b1; + bit armed_trigger; + + initial begin + $display("successfully bound hex2ram_if to %s", instance_path); + armed = has_testfile && 1'b1; + end + + assign armed_trigger = armed && trigger; + + always @(posedge armed_trigger) begin + $display("%m(%0t): saw deassertion of reset", $time); + end + +endinterface : hex2ram_if + +module t + ( + clk + ); + + input clk /*verilator clocker*/; + bit reset; + + wire success; + SimpleTestHarness testHarness + ( + .clk(clk), + .reset(reset), + .io_success(success) + ); + + integer cyc=0; + + always @ (posedge clk) begin + cyc = cyc + 1; + if (cyc<10) begin + reset <= '0; + end + else if (cyc<20) begin + reset <= '1; + end + else if (cyc<30) begin + reset <= '0; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset)); + +module testharness_ext + ( + input W0_clk, + input [24:0] W0_addr, + input W0_en, + input [127:0] W0_data, + input [0:0] W0_mask, + input R0_clk, + input [24:0] R0_addr, + input R0_en, + output [127:0] R0_data + ); + + reg [24:0] reg_R0_addr; + wire [127:0] R0_rdata_mask; + reg [127:0] ram [33554431:0]; + wire [127:0] W0_wdata_mask; + + always @(posedge R0_clk) + if (R0_en) reg_R0_addr <= R0_addr; + + always @(posedge W0_clk) + if (W0_en) begin + if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask; + end + assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;; + assign R0_rdata_mask = 0; + assign W0_wdata_mask = 0; + +endmodule + +module SimpleTestHarness + ( + input clk, + input reset, + output io_success); + + wire [24:0] testharness_ext_R0_addr; + wire testharness_ext_R0_en; + wire testharness_ext_R0_clk; + wire [127:0] testharness_ext_R0_data; + wire [24:0] testharness_ext_W0_addr; + wire testharness_ext_W0_en; + wire testharness_ext_W0_clk; + wire [127:0] testharness_ext_W0_data; + wire [0:0] testharness_ext_W0_mask; + + testharness_ext testharness_ext + ( + .R0_addr(testharness_ext_R0_addr), + .R0_en(testharness_ext_R0_en), + .R0_clk(testharness_ext_R0_clk), + .R0_data(testharness_ext_R0_data), + .W0_addr(testharness_ext_W0_addr), + .W0_en(testharness_ext_W0_en), + .W0_clk(testharness_ext_W0_clk), + .W0_data(testharness_ext_W0_data), + .W0_mask(testharness_ext_W0_mask) + ); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_down.v b/SVIncCompil/Testcases/Verilator/t_interface_down.v new file mode 100644 index 0000000..bec0b2d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_down.v
@@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +interface ifc; + integer value; +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); +`ifdef INLINE_A //verilator inline_module +`else //verilator no_inline_module +`endif + input clk; + integer cyc=1; + + ifc itop1a(); + ifc itop1b(); + ifc itop2a(); + ifc itop2b(); + + wrapper c1 (.isuba(itop1a), + .isubb(itop1b), + .i_valuea(14), + .i_valueb(15)); + wrapper c2 (.isuba(itop2a), + .isubb(itop2b), + .i_valuea(24), + .i_valueb(25)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (itop1a.value != 14) $stop; + if (itop1b.value != 15) $stop; + if (itop2a.value != 24) $stop; + if (itop2b.value != 25) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module wrapper + ( + ifc isuba, + ifc isubb, + input integer i_valuea, + input integer i_valueb + ); +`ifdef INLINE_B //verilator inline_module +`else //verilator no_inline_module +`endif + lower subsuba (.isub(isuba), .i_value(i_valuea)); + lower subsubb (.isub(isubb), .i_value(i_valueb)); +endmodule + +module lower + ( + ifc isub, + input integer i_value + ); +`ifdef INLINE_C //verilator inline_module +`else //verilator no_inline_module +`endif + always @* begin + isub.value = i_value; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_down_gen.v b/SVIncCompil/Testcases/Verilator/t_interface_down_gen.v new file mode 100644 index 0000000..31117d3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_down_gen.v
@@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// This test demonstrates how not only parameters but the type of a parent +// interface could propagate down to child modules, changing their data type +// determinations. Note presently unsupported in all commercial simulators. + +interface ifc; + parameter MODE = 0; + generate + // Note block must be named per SystemVerilog 2005 + if (MODE==1) begin : g + integer value; + end + else if (MODE==2) begin : g + real value; + end + endgenerate +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc #(1) itop1a(); + ifc #(1) itop1b(); + ifc #(2) itop2a(); + ifc #(2) itop2b(); + + wrapper c1 (.isuba(itop1a), + .isubb(itop1b), + .i_valuea(14.1), + .i_valueb(15.2)); + wrapper c2 (.isuba(itop2a), + .isubb(itop2b), + .i_valuea(24.3), + .i_valueb(25.4)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (itop1a.g.value != 14) $stop; + if (itop1b.g.value != 15) $stop; + if (itop2a.g.value != 24) $stop; + if (itop2b.g.value != 25) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module wrapper + ( + ifc isuba, + ifc isubb, + input real i_valuea, + input real i_valueb + ); + lower subsuba (.isub(isuba), .i_value(i_valuea)); + lower subsubb (.isub(isubb), .i_value(i_valueb)); +endmodule + +module lower + ( + ifc isub, + input real i_value + ); + always @* begin +`error Commercial sims choke on cross ref here + isub.g.value = i_value; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_dups.v b/SVIncCompil/Testcases/Verilator/t_interface_dups.v new file mode 100644 index 0000000..aa4281f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_dups.v
@@ -0,0 +1,167 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [4:0] din_data = crc[4:0]; + wire [0:0] din_valid = crc[6]; + wire [0:0] dout0_ready = crc[16]; + wire [0:0] dout1_ready = crc[17]; + wire [0:0] dout2_ready = crc[18]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic din_ready; // From test of Test.v + logic [0:0] dout0_data; // From test of Test.v + logic dout0_valid; // From test of Test.v + logic [1:0] dout1_data; // From test of Test.v + logic dout1_valid; // From test of Test.v + logic [2:0] dout2_data; // From test of Test.v + logic dout2_valid; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .din_ready (din_ready), + .dout0_valid (dout0_valid), + .dout0_data (dout0_data[0:0]), + .dout1_valid (dout1_valid), + .dout1_data (dout1_data[1:0]), + .dout2_valid (dout2_valid), + .dout2_data (dout2_data[2:0]), + // Inputs + .din_valid (din_valid), + .din_data (din_data[4:0]), + .dout0_ready (dout0_ready), + .dout1_ready (dout1_ready), + .dout2_ready (dout2_ready)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, din_ready, + 2'd0, dout2_valid, dout2_data, + 2'd0, dout1_valid, dout1_data, + 2'd0, dout0_valid, dout0_data}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h6fd1bead9df31b07 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +interface dti + #(W_DATA = 64 + )(); + + logic [W_DATA-1:0] data; + logic valid; + logic ready; + + modport producer (output data, + output valid, + input ready); + modport consumer (input data, + input valid, + output ready); +endinterface : dti + +module Test + ( + output logic din_ready, + input logic din_valid, + input logic [4:0] din_data, + input logic dout0_ready, + output logic dout0_valid, + output logic [0:0] dout0_data, + input logic dout1_ready, + output logic dout1_valid, + output logic [1:0] dout1_data, + input logic dout2_ready, + output logic dout2_valid, + output logic [2:0] dout2_data + ); + + // Interface declarations + dti #(.W_DATA(5)) din(); + dti #(.W_DATA(1)) dout0(); + dti #(.W_DATA(2)) dout1(); + dti #(.W_DATA(3)) dout2(); + + // Interface wiring to top level ports + assign din.valid = din_valid; + assign din.data = din_data; + assign din_ready = din.ready; + + assign dout0_valid = dout0.valid; + assign dout0_data = dout0.data; + assign dout0.ready = dout0_ready; + + assign dout1_valid = dout1.valid; + assign dout1_data = dout1.data; + assign dout1.ready = dout1_ready; + + assign dout2_valid = dout2.valid; + assign dout2_data = dout2.data; + assign dout2.ready = dout2_ready; + + assign din.ready = 0; + assign dout0.data = 0; + assign dout1.data = 0; + assign dout2.data = 0; + + typedef struct packed { + logic [1:0] ctrl; + logic [2:0] data; + } din_t; + + din_t din_s; + assign din_s = din.data; + + always_comb begin + dout0.valid = 0; + dout1.valid = 0; + dout2.valid = 0; + + case (din_s.ctrl) + 0 : dout0.valid = din.valid; + 1 : dout1.valid = din.valid; + 2 : dout2.valid = din.valid; + default: ; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen.v b/SVIncCompil/Testcases/Verilator/t_interface_gen.v new file mode 100644 index 0000000..37f0dc2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen.v
@@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// Very simple test for interface pathclearing + +`ifdef VCS + `define UNSUPPORTED_MOD_IN_GENS +`endif +`ifdef VERILATOR + `define UNSUPPORTED_MOD_IN_GENS +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc #(1) itopa(); + ifc #(2) itopb(); + + sub #(1) ca (.isub(itopa), + .i_value(4)); + sub #(2) cb (.isub(itopb), + .i_value(5)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + if (itopa.MODE != 1) $stop; + if (itopb.MODE != 2) $stop; + end + if (cyc==20) begin + if (itopa.get_value() != 4) $stop; + if (itopb.get_value() != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub + #(parameter MODE = 0) + ( + ifc.out_modport isub, + input integer i_value + ); + +`ifdef UNSUPPORTED_MOD_IN_GENS + always @* isub.value = i_value; +`else + generate if (MODE == 1) begin + always @* isub.valuea = i_value; + end + else if (MODE == 2) begin + always @* isub.valueb = i_value; + end + endgenerate +`endif + +endmodule + +interface ifc; + parameter MODE = 0; + // Modports under generates not supported by all commercial simulators +`ifdef UNSUPPORTED_MOD_IN_GENS + integer value; + modport out_modport (output value); + function integer get_value(); return value; endfunction +`else + generate if (MODE == 0) begin + integer valuea; + modport out_modport (output valuea); + function integer get_valuea(); return valuea; endfunction + end + else begin + integer valueb; + modport out_modport (output valueb); + function integer get_valueb(); return valueb; endfunction + end + endgenerate +`endif +endinterface
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen10.v b/SVIncCompil/Testcases/Verilator/t_interface_gen10.v new file mode 100644 index 0000000..0c7c73f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen10.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// bug998 + +interface intf + #(parameter PARAM = 0) + (); + logic val; + function integer func (); return 5; endfunction +endinterface + +module t1(intf mod_intf); + initial begin + $display("%m %d", mod_intf.val); + end +endmodule + +module t(); + generate + begin : TestIf + intf #(.PARAM(1)) my_intf [0:0] (); + t1 t (.mod_intf(my_intf[0])); + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen11.v b/SVIncCompil/Testcases/Verilator/t_interface_gen11.v new file mode 100644 index 0000000..9ce1913 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen11.v
@@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// bug998 + +interface intf + #(parameter PARAM = 0) + (); + logic val; + function integer func (); return 5; endfunction +endinterface + +module t1(intf mod_intf); + initial begin + $display("%m %d", mod_intf.val); + end +endmodule + +module t2(intf mod_intfs [1:0]); + generate + begin + t1 t(.mod_intf(mod_intfs[0])); + end + endgenerate +endmodule + +module t(); + + intf #(.PARAM(1)) my_intf [1:0] (); + + t2 t2 (.mod_intfs(my_intf)); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen12.v b/SVIncCompil/Testcases/Verilator/t_interface_gen12.v new file mode 100644 index 0000000..d93315b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen12.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// bug1005 + +module foo_module; + generate + for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block + logic baz; + end + endgenerate +endmodule + +module bar_module; + foo_module foo(); +endmodule + +module t; + bar_module bar(); + initial begin + bar.foo.my_gen_block[0].baz = 1; + if (bar.foo.my_gen_block[0].baz) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen2.v b/SVIncCompil/Testcases/Verilator/t_interface_gen2.v new file mode 100644 index 0000000..13f0acb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen2.v
@@ -0,0 +1,70 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// Very simple test for interface pathclearing + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc #(2) itopa(); + ifc #(4) itopb(); + + sub ca (.isub(itopa), + .clk); + sub cb (.isub(itopb), + .clk); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo); +`endif + cyc <= cyc + 1; + itopa.valuei <= cyc[1:0]; + itopb.valuei <= cyc[3:0]; + if (cyc==1) begin + if (itopa.WIDTH != 2) $stop; + if (itopb.WIDTH != 4) $stop; + if ($bits(itopa.valueo) != 2) $stop; + if ($bits(itopb.valueo) != 4) $stop; + if ($bits(itopa.out_modport.valueo) != 2) $stop; + if ($bits(itopb.out_modport.valueo) != 4) $stop; + end + if (cyc==4) begin + if (itopa.valueo != 2'b11) $stop; + if (itopb.valueo != 4'b0011) $stop; + end + if (cyc==5) begin + if (itopa.valueo != 2'b00) $stop; + if (itopb.valueo != 4'b0100) $stop; + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +interface ifc + #(parameter WIDTH = 1); + // verilator lint_off MULTIDRIVEN + logic [WIDTH-1:0] valuei; + logic [WIDTH-1:0] valueo; + // verilator lint_on MULTIDRIVEN + modport out_modport (input valuei, output valueo); +endinterface + +// Note not parameterized +module sub + ( + ifc.out_modport isub, + input clk + ); + always @(posedge clk) isub.valueo <= isub.valuei + 1; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen3.v b/SVIncCompil/Testcases/Verilator/t_interface_gen3.v new file mode 100644 index 0000000..e3c107c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen3.v
@@ -0,0 +1,70 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// Very simple test for interface pathclearing + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc #(2) itopa(); + ifc #(4) itopb(); + + sub ca (.isub(itopa.out_modport), + .clk); + sub cb (.isub(itopb.out_modport), + .clk); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo); +`endif + cyc <= cyc + 1; + itopa.valuei <= cyc[1:0]; + itopb.valuei <= cyc[3:0]; + if (cyc==1) begin + if (itopa.WIDTH != 2) $stop; + if (itopb.WIDTH != 4) $stop; + if ($bits(itopa.valueo) != 2) $stop; + if ($bits(itopb.valueo) != 4) $stop; + if ($bits(itopa.out_modport.valueo) != 2) $stop; + if ($bits(itopb.out_modport.valueo) != 4) $stop; + end + if (cyc==4) begin + if (itopa.valueo != 2'b11) $stop; + if (itopb.valueo != 4'b0011) $stop; + end + if (cyc==5) begin + if (itopa.valueo != 2'b00) $stop; + if (itopb.valueo != 4'b0100) $stop; + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +interface ifc + #(parameter WIDTH = 1); + // verilator lint_off MULTIDRIVEN + logic [WIDTH-1:0] valuei; + logic [WIDTH-1:0] valueo; + // verilator lint_on MULTIDRIVEN + modport out_modport (input valuei, output valueo); +endinterface + +// Note not parameterized +module sub + ( + ifc.out_modport isub, + input clk + ); + always @(posedge clk) isub.valueo <= isub.valuei + 1; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen4.v b/SVIncCompil/Testcases/Verilator/t_interface_gen4.v new file mode 100644 index 0000000..7678ac0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen4.v
@@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// bug789 generates + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc #(1) itopa(); + ifc #(2) itopb(); + + sub #(1) ca (.isub(itopa), + .i_value(4)); + sub #(2) cb (.isub(itopb), + .i_value(5)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + if (itopa.MODE != 1) $stop; + if (itopb.MODE != 2) $stop; + end + if (cyc==20) begin + if (itopa.i != 4) $stop; + if (itopb.i != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub + #(parameter MODE = 0) + ( + ifc isub, + input integer i_value + ); + + // Commercial unsupported Xmrs into scopes within interfaces + generate + always_comb isub.i = i_value; + endgenerate +endmodule + +interface ifc; + parameter MODE = 0; + // Commercial unsupported Xmrs into scopes within interfaces + generate + integer i; + endgenerate +endinterface
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen5.v b/SVIncCompil/Testcases/Verilator/t_interface_gen5.v new file mode 100644 index 0000000..e497673 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen5.v
@@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// bug998 + +interface intf + #(parameter PARAM = 0) + (); + logic val; + function integer func (); return 5; endfunction +endinterface + +module t1(intf mod_intf); + initial begin + $display("%m %d", mod_intf.val); + end +endmodule + +module t(); + generate + begin : TestIf + intf #(.PARAM(1)) my_intf (); + assign my_intf.val = '0; + t1 t (.mod_intf(my_intf)); +// initial $display("%0d", my_intf.func()); + end + endgenerate + + generate + begin + intf #(.PARAM(1)) my_intf (); + assign my_intf.val = '1; + t1 t (.mod_intf(my_intf)); +// initial $display("%0d", my_intf.func()); + end + endgenerate + + localparam LP = 1; + logic val; + + generate begin + if (LP) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + assign val = my_intf.val; + end else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '1; + assign val = my_intf.val; + end + end endgenerate + + initial begin + $display("%0d", val); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen6.v b/SVIncCompil/Testcases/Verilator/t_interface_gen6.v new file mode 100644 index 0000000..dfcec09 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen6.v
@@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// bug1001 + +interface intf + #(parameter PARAM = 0) + (); + logic val; +endinterface + +module t(); + + generate + if (1) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + end else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end + endgenerate + + generate + begin + if (1) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + end else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end + end + endgenerate + + generate + begin + begin + if (1) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + end else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen7.v b/SVIncCompil/Testcases/Verilator/t_interface_gen7.v new file mode 100644 index 0000000..dcec132 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen7.v
@@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// bug998 + +interface intf + #(parameter PARAM = 0) + (); + logic val; + function integer func (); return 5; endfunction +endinterface + +module t1(intf mod_intf); + initial begin + $display("%m %d", mod_intf.val); + end +endmodule + +module t(); + + intf #(.PARAM(1)) my_intf [1:0] (); + + generate + genvar the_genvar; + begin + for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf + begin + assign my_intf[the_genvar].val = '1; + t1 t (.mod_intf(my_intf[the_genvar])); + end + end + end + endgenerate + + generate + genvar the_second_genvar; + begin + intf #(.PARAM(1)) my_intf [1:0] (); + for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf + begin + assign my_intf[the_second_genvar].val = '1; + t1 t (.mod_intf(my_intf[the_second_genvar])); + end + end + end + endgenerate + + generate + genvar the_third_genvar; + begin + for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf + begin + intf #(.PARAM(1)) my_intf [1:0] (); + assign my_intf[the_third_genvar].val = '1; + t1 t (.mod_intf(my_intf[the_third_genvar])); + end + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen8.v b/SVIncCompil/Testcases/Verilator/t_interface_gen8.v new file mode 100644 index 0000000..be7080b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen8.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// bug998 + +interface intf + #(parameter PARAM = 0) + (); + logic val; + function integer func (); return 5; endfunction +endinterface + +module t1(intf mod_intf); + initial begin + $display("%m %d", mod_intf.val); + end +endmodule + +module t(); + + //intf #(.PARAM(1)) my_intf [1:0] (); + intf #(.PARAM(1)) my_intf (); + + generate + genvar the_genvar; + for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf + //assign my_intf[the_genvar].val = '1; + //t1 t (.mod_intf(my_intf[the_genvar])); + t1 t (.mod_intf(my_intf)); + end + endgenerate + +// t1 t (.mod_intf(my_intf[1])); + +// generate +// begin : TestIf +// assign my_intf[1].val = '1; +// t1 t (.mod_intf(my_intf[1])); +// end +// endgenerate + +// generate +// begin +// assign my_intf[0].val = '1; +// t1 t (.mod_intf(my_intf[0])); +// end +// endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_gen9.v b/SVIncCompil/Testcases/Verilator/t_interface_gen9.v new file mode 100644 index 0000000..10a2f83 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_gen9.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// bug998 + +module t1(input logic foo); + initial begin + $display("%m %d", foo); + end +endmodule + +module t(); + + logic [1:0] my_foo; + + generate + genvar the_genvar; + for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf + //logic tmp_foo; + //assign tmp_foo = my_foo[the_genvar]; + t1 t (.foo(my_foo[the_genvar])); + //t1 t (.foo(tmp_foo)); + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_mismodport_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_mismodport_bad.v new file mode 100644 index 0000000..80e6f01 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_mismodport_bad.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +interface ifc; + integer ok; + integer bad; + modport out_modport (output ok); +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc itop(); + + counter_ansi c1 (.isub(itop), + .i_value(4'h4)); + +endmodule + +module counter_ansi + ( + ifc.out_modport isub, + input logic [3:0] i_value + ); + + always @* begin + isub.ok = i_value; + isub.bad = i_value; // Illegal access + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_missing_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_missing_bad.v new file mode 100644 index 0000000..9e72099 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_missing_bad.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Missing interface test +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +// Interface intentionally not defined +//interface foo_intf; +// logic a; +//endinterface + +module foo_mod + ( + foo_intf foo + ); +endmodule + +module t (/*AUTOARG*/); + + foo_intf the_foo (); + + foo_mod + foo_mod + ( + .foo (the_foo) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_modport.v b/SVIncCompil/Testcases/Verilator/t_interface_modport.v new file mode 100644 index 0000000..9544463 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_modport.v
@@ -0,0 +1,131 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +interface counter_if; + logic [3:0] value; + logic reset; + modport counter_mp (input reset, output value); + modport core_mp (output reset, input value); +endinterface + +// Check can have inst module before top module +module counter_ansi + ( + input clkm, + counter_if c_data, + input logic [3:0] i_value + ); + + always @ (posedge clkm) begin + c_data.value <= c_data.reset ? i_value : c_data.value + 1; + end +endmodule : counter_ansi + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + counter_if c1_data(); + counter_if c2_data(); + counter_if c3_data(); + counter_if c4_data(); + + counter_ansi c1 (.clkm(clk), + .c_data(c1_data.counter_mp), + .i_value(4'h1)); +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + /**/ c2 (.clkm(clk), + .c_data(c2_data.counter_mp), + .i_value(4'h2)); + counter_ansi_m c3 (.clkm(clk), + .c_data(c3_data), + .i_value(4'h3)); +`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif + /**/ c4 (.clkm(clk), + .c_data(c4_data), + .i_value(4'h4)); + + initial begin + c1_data.value = 4'h4; + c2_data.value = 4'h5; + c3_data.value = 4'h6; + c4_data.value = 4'h7; + end + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc<2) begin + c1_data.reset <= 1; + c2_data.reset <= 1; + c3_data.reset <= 1; + c4_data.reset <= 1; + end + if (cyc==2) begin + c1_data.reset <= 0; + c2_data.reset <= 0; + c3_data.reset <= 0; + c4_data.reset <= 0; + end + if (cyc==20) begin + $write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc, + c1_data.value, c1_data.reset, + c2_data.value, c2_data.reset, + c3_data.value, c3_data.reset, + c4_data.value, c4_data.reset); + if (c1_data.value != 2) $stop; + if (c2_data.value != 3) $stop; + if (c3_data.value != 4) $stop; + if (c4_data.value != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +`ifndef VERILATOR +// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. +module counter_nansi + (clkm, c_data, i_value); + + input clkm; + counter_if c_data; + input logic [3:0] i_value; + + always @ (posedge clkm) begin + c_data.value <= c_data.reset ? i_value : c_data.value + 1; + end +endmodule : counter_nansi +`endif + +module counter_ansi_m + ( + input clkm, + counter_if.counter_mp c_data, + input logic [3:0] i_value + ); + + always @ (posedge clkm) begin + c_data.value <= c_data.reset ? i_value : c_data.value + 1; + end +endmodule : counter_ansi_m + +`ifndef VERILATOR +// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. +module counter_nansi_m + (clkm, c_data, i_value); + + input clkm; + counter_if.counter_mp c_data; + input logic [3:0] i_value; + + always @ (posedge clkm) begin + c_data.value <= c_data.reset ? i_value : c_data.value + 1; + end +endmodule : counter_nansi_m +`endif
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_modport_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_modport_bad.v new file mode 100644 index 0000000..012aef1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_modport_bad.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +interface ifc; + integer ok; + modport out_modport (output ok); +endinterface + +module t (/*AUTOARG*/); + + ifc itop(); + + counter_ansi c1 (.isub(itop), + .i_value(4'h4)); + +endmodule + +module counter_ansi + ( + ifc.oop_modport isub, // Bad + input logic [3:0] i_value + ); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_modport_export.v b/SVIncCompil/Testcases/Verilator/t_interface_modport_export.v new file mode 100644 index 0000000..11a59f1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_modport_export.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the export parameter used with modport +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +interface test_if; + + // Pre-declare function + extern function myfunc (input logic val); + + // Interface variable + logic data; + + // Modport + modport mp_e( + export myfunc, + output data + ); + + // Modport + modport mp_i( + import myfunc, + output data + ); + +endinterface // test_if + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + test_if i (); + + testmod_callee testmod_callee_i (.ie (i.mp_e)); + testmod_caller testmod_caller_i (.clk (clk), + .ii (i.mp_i)); +endmodule + + +module testmod_callee + ( + test_if.mp_e ie + ); + + function automatic logic ie.myfunc (input logic val); + begin + myfunc = (val == 1'b0); + end + endfunction +endmodule // testmod_caller + + +module testmod_caller + ( + input clk, + test_if.mp_i ii + ); + + always @(posedge clk) begin + ii.data = 1'b0; + if (ii.myfunc (1'b0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_modport_import.v b/SVIncCompil/Testcases/Verilator/t_interface_modport_import.v new file mode 100644 index 0000000..c963fbf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_modport_import.v
@@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the import parameter used with modport +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +interface test_if; + + // Interface variable + logic data; + + // Modport + modport mp( + import myfunc, + output data + ); + + function automatic logic myfunc (input logic val); + begin + myfunc = (val == 1'b0); + end + endfunction + +endinterface // test_if + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + test_if i (); + + testmod testmod_i (.clk (clk), + .i (i.mp)); + +endmodule + + +module testmod + ( + input clk, + test_if.mp i + ); + + always @(posedge clk) begin + i.data = 1'b0; + if (i.myfunc (1'b0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_modportlist.v b/SVIncCompil/Testcases/Verilator/t_interface_modportlist.v new file mode 100644 index 0000000..20ac024 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_modportlist.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Adrian Wise + +//bug1246 + +module t(input clk); + my_interface iface(); + my_module m(.clk(clk), iface); +endmodule + +module my_module(input clk, my_interface.my_port iface); + always @(posedge clk) begin + iface.b <= iface.a; + iface.c <= iface.a; + end +endmodule + +interface my_interface; + logic a, b, c; + modport my_port(input a, output b, c); +endinterface
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_mp_func.v b/SVIncCompil/Testcases/Verilator/t_interface_mp_func.v new file mode 100644 index 0000000..c52ce67 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_mp_func.v
@@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +interface pads_if(); + modport mp_dig( + import fIn, + import fOut ); + + integer exists[8]; + function automatic integer fIn (integer i); + fIn = exists[i]; + endfunction + task automatic fOut (integer i); + exists[i] = 33; + endtask +endinterface + +module t(); + pads_if padsif[1:0](); + pads_if padsif_arr[1:0](); + initial begin + padsif[0].fOut(3); + if (padsif[0].fIn(3) != 33) $stop; + + padsif_arr[0].fOut(3); + if (padsif_arr[0].fIn(3) != 33) $stop; + padsif_arr[1].fOut(3); + if (padsif_arr[1].fIn(3) != 33) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_nest.v b/SVIncCompil/Testcases/Verilator/t_interface_nest.v new file mode 100644 index 0000000..e0eeddf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_nest.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by ____YOUR_NAME_HERE____. + +interface if1; + integer var1; +endinterface + +interface if2; + if1 i1 (); + integer var2; +endinterface + +module mod1 + ( + input clk, + input integer modnum, // Don't use parameter, want same module twice for better checking + if2 foo + ); + + logic l1, l2; + + always_ff @(posedge clk) begin + if (modnum==1) begin + if (foo.i1.var1 != 1) $stop; + if (foo.var2 != 2) $stop; + end + if (modnum==2) begin + if (foo.i1.var1 != 1) $stop; + if (foo.var2 != 2) $stop; + end + end + +endmodule + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + if2 i2a (); + if2 i2b (); + + assign i2a.i1.var1 = 1; + assign i2a.var2 = 2; + assign i2b.i1.var1 = 3; + assign i2b.var2 = 4; + + mod1 mod1a + ( + .modnum (1), + .clk (clk), + .foo (i2a) + ); + + mod1 mod1b + ( + .modnum (2), + .clk (clk), + .foo (i2a) + ); + + integer cyc = 0; + always_ff @(posedge clk) begin + cyc <= cyc+1; + if (cyc==2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_param1.v b/SVIncCompil/Testcases/Verilator/t_interface_param1.v new file mode 100644 index 0000000..61d018a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_param1.v
@@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jie Xu. + +//bug692 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input wire clk; + + wire [31:0] result; + test_if #(.id(3)) s(); + sub_test U_SUB_TEST(s.a.b, result); // the line causing error +endmodule : t + +// --------------------------------------------------------------------------- + +module sub_test + ( + input [31:0] b, + output [31:0] c + ); + assign c = b; +endmodule + +// --------------------------------------------------------------------------- + +interface test_if + #(parameter id = 0) + (); + + typedef struct packed { + logic a; + logic [31:0] b; + } aType; + + aType a; + + typedef struct packed { + logic c; + logic [31:0] d; + } bType; + + bType b; + + modport master (input a, output b); + +endinterface
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_param2.v b/SVIncCompil/Testcases/Verilator/t_interface_param2.v new file mode 100644 index 0000000..0b2afd5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_param2.v
@@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Adrian Wise + +//bug1104 + +module t (input clk); + simple_bus sb_intf(clk); + simple_bus #(.DWIDTH(16)) wide_intf(clk); + mem mem(sb_intf.slave); + cpu cpu(sb_intf.master); + mem memW(wide_intf.slave); + cpu cpuW(wide_intf.master); +endmodule + +interface simple_bus #(AWIDTH = 8, DWIDTH = 8) + (input logic clk); // Define the interface + + logic req, gnt; + logic [AWIDTH-1:0] addr; + logic [DWIDTH-1:0] data; + + modport slave( input req, addr, clk, + output gnt, + input data); + + modport master(input gnt, clk, + output req, addr, + output data); + + initial begin + if (DWIDTH != 16) $stop; + end +endinterface: simple_bus + +module mem(interface a); + logic avail; + always @(posedge a.clk) + a.gnt <= a.req & avail; + initial begin + if ($bits(a.data) != 16) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module cpu(interface b); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_param_another_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_param_another_bad.v new file mode 100644 index 0000000..13a6fde --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_param_another_bad.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Johan Bjork. + +module t (); + simple_bus sb_intf(); + simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +interface simple_bus #(PARAMETER = 0); + logic dummy; +endinterface
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_parameter_access.v b/SVIncCompil/Testcases/Verilator/t_interface_parameter_access.v new file mode 100644 index 0000000..918a636 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_parameter_access.v
@@ -0,0 +1,89 @@ +// DESCRIPTION: Verilator: Interface parameter getter +// +// A test of the import parameter used with modport +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader + +interface test_if #(parameter integer FOO = 1); + + // Interface variable + logic data; + + // Modport + modport mp( + import getFoo, + output data + ); + + function integer getFoo (); + return FOO; + endfunction + +endinterface // test_if + +function integer identity (input integer x); + return x; +endfunction + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + test_if #( .FOO (identity(5)) ) the_interface (); + + testmod testmod_i (.clk (clk), + .intf (the_interface), + .intf_no_mp (the_interface) + ); + + localparam THE_TOP_FOO = the_interface.FOO; + + initial begin + if (THE_TOP_FOO != 5) begin + $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO); + $stop; + end + end + +endmodule + + +module testmod + ( + input clk, + test_if.mp intf, + test_if intf_no_mp + ); + + localparam THE_FOO = intf.FOO; + localparam THE_OTHER_FOO = intf_no_mp.FOO; + + always @(posedge clk) begin + if (THE_FOO != 5) begin + $display("%%Error: THE_FOO = %0d", THE_FOO); + $stop; + end + if (THE_OTHER_FOO != 5) begin + $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO); + $stop; + end + if (intf.FOO != 5) begin + $display("%%Error: intf.FOO = %0d", intf.FOO); + $stop; + end + if (intf_no_mp.FOO != 5) begin + $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO); + $stop; + end + // if (i.getFoo() != 5) begin + // $display("%%Error: i.getFoo() = %0d", i.getFoo()); + // $stop; + // end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_size_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_size_bad.v new file mode 100644 index 0000000..4066254 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_size_bad.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Demonstrate deferred linking error messages +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Johan Bjork. + +interface foo_intf; + logic a; +endinterface + +module t (/*AUTOARG*/); + localparam N = 4; + foo_intf foo4 [N-1:0] (); + foo_intf foo6 [5:0] (); + + baz baz4_inst (.foo(foo4)); + baz baz6_inst (.foo(foo6)); + +endmodule + +module baz(foo_intf foo[4:0] ); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_star.v b/SVIncCompil/Testcases/Verilator/t_interface_star.v new file mode 100644 index 0000000..e3e4b3b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_star.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + counter_io c_data(); + + counter_ansi c1 (.clk, .*); + + counter_ansi c2 (.clk, .c_data); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (c_data.value != 12345) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +interface counter_io; + integer value; +endinterface + +module counter_ansi + ( + input clk, + counter_io c_data + ); + + always_ff @ (posedge clk) begin + c_data.value <= 12345; + end +endmodule : counter_ansi
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_top_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_top_bad.v new file mode 100644 index 0000000..2334789 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_top_bad.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +interface ifc; + logic [3:0] value; + logic reset; + modport counter_mp (input reset, output value); + modport core_mp (output reset, input value); +endinterface + +module t + (// Inputs + input clk, + ifc.counter_mp c_data + ); + + integer cyc=1; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_twod.v b/SVIncCompil/Testcases/Verilator/t_interface_twod.v new file mode 100644 index 0000000..4fe47a6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_twod.v
@@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +interface ifc; + integer value; + modport i (output value); + modport o (input value); +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=1; + + ifc itop1a(), + itop1b(); + + wrapper c1 (.isuba(itop1a), + .isubb(itop1b), + .i_valuea(14), + .i_valueb(15)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (itop1a.value != 14) $stop; + if (itop1b.value != 15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module wrapper + ( + ifc.i isuba, isubb, + input integer i_valuea, i_valueb + ); + always @* begin + isuba.value = i_valuea; + isubb.value = i_valueb; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_typo_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_typo_bad.v new file mode 100644 index 0000000..d91f339 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_typo_bad.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Todd Strader. + +//bug1097 + +interface foo_intf; +endinterface + +module submod + ( + foo_intf foo + ); + +endmodule + +module t (/*AUTOARG*/); + // Intentional typo, compiler should point this out, or that fo_intf does + // not match foo_intf on the submod port map + fo_intf the_foo; + + submod + submod_inst + ( + .foo (the_foo) + ); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_interface_wrong_bad.v b/SVIncCompil/Testcases/Verilator/t_interface_wrong_bad.v new file mode 100644 index 0000000..233b9a6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_interface_wrong_bad.v
@@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Using the wrong kind of interface in a portmap +// should cause an error +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Todd Strader. + +interface foo_intf; + logic [7:0] a; +endinterface + +interface bar_intf; + logic [7:0] a; +endinterface + +module foo_mod (foo_intf foo_port); +// initial begin +// $display("a = %0d", foo_port.a); +// end +endmodule + +module t (/*AUTOARG*/); + + foo_intf foo (); + bar_intf bar (); + +// assign foo.a = 8'd1; +// assign bar.a = 8'd2; + + foo_mod + foo_mod ( + .foo_port (bar) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_langext_1.v b/SVIncCompil/Testcases/Verilator/t_langext_1.v new file mode 100644 index 0000000..bd8728f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_langext_1.v
@@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +verilog1995ext+ and +verilog2001ext+ flags. +// +// This source code contains constructs that are valid in Verilog 2001 and +// SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we +// set the language to be 1995, but not 2001. +// +// Compile only test, so no need for "All Finished" output. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [1:0] res; + + // Instantiate the test + test test_i (// Outputs + .res (res[1:0]), + // Inputs + .clk (clk), + .in (1'b1)); + +endmodule + +module test (// Outputs + res, + // Inputs + clk, + in + ); + output reg [1:0] res; + input clk; + input in; + + // This is a Verilog 2001 test + generate + genvar i; + for (i=0; i<2; i=i+1) begin + always @(posedge clk) begin + res[i:i] <= in; + end + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_langext_2.v b/SVIncCompil/Testcases/Verilator/t_langext_2.v new file mode 100644 index 0000000..96c00d8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_langext_2.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +1364-1995ext+ and +systemverilogext+ flags. +// +// This source code contains constructs that are valid in SystemVerilog 2009 +// but not in Verilog 1995. So it should fail if we set the language to be +// Verilog 1995, but not SystemVerilog 2009. +// +// Compile only test, so no need for "All Finished" output. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [1:0] res; + + + // Instantiate the test + test test_i (/*AUTOINST*/ + // Outputs + .res (res), + // Inputs + .clk (clk), + .in (1'b1)); + +endmodule + +module test (// Outputs + res, + // Inputs + clk, + in + ); + output [1:0] res; + input clk; + input in; + + // This is a SystemVerilog 2009 only test + generate + genvar i; + for (i=0; i<2; i=i+1) begin + always @(posedge clk) begin + unique0 case (i) + 0: res[0:0] <= in; + 1: res[1:1] <= in; + endcase + end + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_langext_3.v b/SVIncCompil/Testcases/Verilator/t_langext_3.v new file mode 100644 index 0000000..eecc026 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_langext_3.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +verilog2001ext+ and +verilog2005ext+ flags. +// +// This source code uses the uwire declaration, which is only valid in Verilog +// 2005. +// +// Compile only test, so no need for "All Finished" output. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + uwire w; // Only in Verilog 2005 + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_langext_order.v b/SVIncCompil/Testcases/Verilator/t_langext_order.v new file mode 100644 index 0000000..aea0dc0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_langext_order.v
@@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +verilog2001ext+ and +verilog2005ext+ flags. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +// verilator lint_off SYMRSVDWORD + +module t(input do); + t_langext_order_sub sub (.do(do)); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_langext_order_sub.v b/SVIncCompil/Testcases/Verilator/t_langext_order_sub.v new file mode 100644 index 0000000..79cdaaa --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_langext_order_sub.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +verilog2001ext+ and +verilog2005ext+ flags. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +// verilator lint_off SYMRSVDWORD + +module t_langext_order_sub(input do); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_leak.v b/SVIncCompil/Testcases/Verilator/t_leak.v new file mode 100644 index 0000000..667d998 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_leak.v
@@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (clk); + + sub sub (); + + input clk; + integer cyc=1; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==2) begin + // Not $finish; as we don't want a message to scroll by + $c("Verilated::gotFinish(true);"); + end + end +endmodule + +module sub; + /* verilator public_module */ +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_always_comb_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_always_comb_bad.v new file mode 100644 index 0000000..789eaef --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_always_comb_bad.v
@@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + mid, o3, + // Inputs + clk, i3 + ); + input clk; + output logic mid; + input i3; + output logic o3; + + wire [15:0] temp1; + wire [15:0] temp1_d1r; + + logic setbefore; + always_comb begin + setbefore = 1'b1; + if (setbefore) setbefore = 1'b0; // fine + end + + always_comb begin + if (mid) + temp1 = 'h0; + else + temp1 = (temp1_d1r - 'h1); + mid = (temp1_d1r == 'h0); // BAD + end + + always_comb begin + o3 = 'h0; + case (i3) + 1'b1: begin + o3 = i3; + end + default: ; + endcase + end + + always_ff @ (posedge clk) begin + temp1_d1r <= temp1; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_always_comb_iface.v b/SVIncCompil/Testcases/Verilator/t_lint_always_comb_iface.v new file mode 100644 index 0000000..0017a5e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_always_comb_iface.v
@@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Josh Redford. + +interface my_if; + + logic valid; + logic [7:0] data ; + + modport slave_mp ( + input valid, + input data + ); + + modport master_mp ( + output valid, + output data + ); + +endinterface + +module t + ( + input wire in_valid, + input wire [7:0] in_data + ); + + my_if in_i (); + my_if out1_i (); + my_if out2_i (); + my_if out3_i (); + + assign in_i.valid = in_valid; + assign in_i.data = in_data ; + + my_module1 my_module1_i ( + .in_i (in_i ), + .out_i (out1_i) + ); + + my_module2 my_module2_i ( + .in_i (in_i ), + .out_i (out2_i) + ); + + my_module3 my_module3_i ( + .in_i (in_i ), + .out_i (out3_i) + ); + +endmodule + +module my_module1 ( + my_if.slave_mp in_i, + my_if.master_mp out_i + ); + + // Gives ALWCOMBORDER warning + always_comb + begin + out_i.valid = in_i.valid; + out_i.data = in_i.data ; + end + +endmodule + +module my_module2 ( + my_if.slave_mp in_i, + my_if.master_mp out_i + ); + + // Works if you initialise to non-interface signal first + always_comb + begin + out_i.valid = '0; + out_i.data = 'X; + out_i.valid = in_i.valid; + out_i.data = in_i.data ; + end + +endmodule + +module my_module3 ( + my_if.slave_mp in_i, + my_if.master_mp out_i + ); + + // Works if you use assign signal + assign out_i.valid = in_i.valid; + assign out_i.data = in_i.data ; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_blksync_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_blksync_bad.v new file mode 100644 index 0000000..ff0f933 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_blksync_bad.v
@@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer i; + + reg sync_blk; + reg sync_blk2; + reg sync_nblk; + reg sync2_ok; + reg sync3_ok; + reg combo_blk; + reg combo_nblk; + + always @(posedge clk) begin + sync_blk = 1'b1; + sync_blk2 = 1'b1; // Only warn once per block + sync_nblk <= 1'b1; + end + + always @* begin + combo_blk = 1'b1; + combo_nblk <= 1'b1; + end + + always @(posedge clk) begin + for (int i=0; i<20; i++) begin + sync2_ok <= 1'b1; + end + end + + always @(posedge clk) begin + sync3_ok <= f(sync3_ok); + end + + function f (input v); + f = ~v; + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_blksync_loop.v b/SVIncCompil/Testcases/Verilator/t_lint_blksync_loop.v new file mode 100644 index 0000000..2bf1ef4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_blksync_loop.v
@@ -0,0 +1,108 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + data_out, + // Inputs + wr, wa, rst_l, rd, ra, data_in, clk + ); + input clk; + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input [31:0] data_in; // To sub of reg_1r1w.v + input [7:0] ra; // To sub of reg_1r1w.v + input rd; // To sub of reg_1r1w.v + input rst_l; // To sub of reg_1r1w.v + input [7:0] wa; // To sub of reg_1r1w.v + input wr; // To sub of reg_1r1w.v + // End of automatics + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [31:0] data_out; // From sub of reg_1r1w.v + // End of automatics + + reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8)) + sub + (/*AUTOINST*/ + // Outputs + .data_out (data_out[31:0]), + // Inputs + .data_in (data_in[31:0]), + .ra (ra[7:0]), + .wa (wa[7:0]), + .wr (wr), + .rd (rd), + .clk (clk), + .rst_l (rst_l)); + +endmodule + +module reg_1r1w + #( + parameter WIDTH=32, + parameter ADRWID=10, + parameter DEPTH=1024, + parameter RST=0 + ) + (/*AUTOARG*/ + // Outputs + data_out, + // Inputs + data_in, ra, wa, wr, rd, clk, rst_l + ); + + input [WIDTH-1:0] data_in; + input [ADRWID-1:0] ra; + input [ADRWID-1:0] wa; + input wr; + input rd; + input clk; + input rst_l; + + output [WIDTH-1:0] data_out; + + reg [WIDTH-1:0] array [DEPTH-1:0]; + reg [ADRWID-1:0] ra_r, wa_r; + reg [WIDTH-1:0] data_in_r; + reg wr_r; + reg rd_r; + + integer x; + + // Message 679 + always @(posedge clk) begin + int tmp = x + 1; + if (tmp !== x + 1) $stop; + end + + always @(posedge clk or negedge rst_l) begin + if (!rst_l) begin + for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE + if (RST == 1) begin + array[x] <= 0; + end + end + ra_r <= 0; + wa_r <= 0; + wr_r <= 0; + rd_r <= 0; + data_in_r <= 0; + end + else begin + ra_r <= ra; + wa_r <= wa; + wr_r <= wr; + rd_r <= rd; + data_in_r <= data_in; + if (wr_r) array[wa_r] <= data_in_r; + end + end +endmodule + +// Local Variables: +// verilog-auto-inst-param-value: t +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_block_redecl_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_block_redecl_bad.v new file mode 100644 index 0000000..1bc434e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_block_redecl_bad.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +//bug485, but see t_gen_forif.v for an OK example. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + always_comb begin + integer i; + + for(i=0; i<10; i++ ) begin: COMB + end + + for(i=0; i<9; i++ ) begin: COMB + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_bsspace_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_bsspace_bad.v new file mode 100644 index 0000000..b37bdbf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_bsspace_bad.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +// Fake binary character here '', so is treated as binary and +// don't get whitespace violation. + +`define FOO blak \ + blak + +module t; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_colonplus_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_colonplus_bad.v new file mode 100644 index 0000000..9bea31d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_colonplus_bad.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + z + ); + + reg [3:0] r = 4'b1010; + output [2:1] z = r[2 :+ 1]; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_comb_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_comb_bad.v new file mode 100644 index 0000000..360fb33 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_comb_bad.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + always_comb @(*) begin + $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_comb_use.v b/SVIncCompil/Testcases/Verilator/t_lint_comb_use.v new file mode 100644 index 0000000..cd9a978 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_comb_use.v
@@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + hval, + // Inputs + sel + ); + + input logic [2:0] sel; + output logic [3:0] hval; + + /*AUTOINPUT*/ + /*AUTOOUTPUT*/ + + always_comb begin + unique case (sel) + 3'h0: hval = 4'hd; + 3'h1: hval = 4'hc; + 3'h7: hval = 4'hf; + default: begin + $ignore ("ERROR : %s [%m]", $sformatf ("Illegal sel = %x", sel)); + hval = 4'bx; + end + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_declfilename.v b/SVIncCompil/Testcases/Verilator/t_lint_declfilename.v new file mode 100644 index 0000000..862be67 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_declfilename.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t; + t_lint_declfilename sub (); +endmodule + +module t_lint_declfilename; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_defparam.v b/SVIncCompil/Testcases/Verilator/t_lint_defparam.v new file mode 100644 index 0000000..079fb0b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_defparam.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t; + + sub sub (); + defparam sub.P = 2; + +endmodule + +module sub; + parameter P = 6; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_ifdepth_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_ifdepth_bad.v new file mode 100644 index 0000000..5b5b880 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_ifdepth_bad.v
@@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t; + + integer value = 19; + + initial begin + if (value==1) begin end + else if (value==2) begin end + else if (value==3) begin end + else if (value==4) begin end + else if (value==5) begin end + else if (value==6) begin end + else if (value==7) begin end + else if (value==8) begin end + else if (value==9) begin end + else if (value==10) begin end + else if (value==11) begin end // Warn about this one + else if (value==12) begin end + end + + initial begin + unique0 if (value==1) begin end + else if (value==2) begin end + else if (value==3) begin end + else if (value==4) begin end + else if (value==5) begin end + else if (value==6) begin end + else if (value==7) begin end + else if (value==8) begin end + else if (value==9) begin end + else if (value==10) begin end + else if (value==11) begin end // Warn about this one + else if (value==12) begin end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_implicit.v b/SVIncCompil/Testcases/Verilator/t_lint_implicit.v new file mode 100644 index 0000000..5d56d49 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_implicit.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (a,z); + input a; + output z; + + assign b = 1'b1; + + or OR0 (nt0, a, b); + + logic [1:0] dummy_ip; + assign {dummy1, dummy2} = dummy_ip; + + assign z = nt0; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_implicit_def_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_implicit_def_bad.v new file mode 100644 index 0000000..071ccbf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_implicit_def_bad.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (a,z); + input a; + output z; + + assign imp_warn = 1'b1; + // verilator lint_off IMPLICIT + assign imp_ok = 1'b1; + +`default_nettype none + assign imp_err = 1'b1; + +`default_nettype wire + assign imp_ok2 = 1'b1; + +`default_nettype none +`resetall + assign imp_ok3 = 1'b1; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_implicit_port.v b/SVIncCompil/Testcases/Verilator/t_lint_implicit_port.v new file mode 100644 index 0000000..d3f76bc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_implicit_port.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + logic oe; + + read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) ); + set s (.clk(clk), .enable(implicit_write)); + read u (.clk(clk), .data(~implicit_also)); + +endmodule + +module set ( + input clk, + output enable + ); + assign enable = 1'b0; +endmodule + +module read ( + input clk, + input data + ); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_import_name_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_import_name_bad.v new file mode 100644 index 0000000..8ffea87 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_import_name_bad.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +package defs; + int sig; +endpackage + +import defs::sigs; + +module t; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_importstar_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_importstar_bad.v new file mode 100644 index 0000000..bea7837 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_importstar_bad.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +package defs; + int sig; +endpackage + +import defs::*; + +module t; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad.v new file mode 100644 index 0000000..54cab89 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad.v
@@ -0,0 +1,6 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +`include "t_lint_in_inc_bad_1.vh"
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad_1.vh b/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad_1.vh new file mode 100644 index 0000000..086d289 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad_1.vh
@@ -0,0 +1,6 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +`include "t_lint_in_inc_bad_2.vh"
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad_2.vh b/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad_2.vh new file mode 100644 index 0000000..13e39c8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_in_inc_bad_2.vh
@@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module x; + // Syntax error + if if if; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_incabspath.v b/SVIncCompil/Testcases/Verilator/t_lint_incabspath.v new file mode 100644 index 0000000..47a56c2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_incabspath.v
@@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +`include "/dev/null" + +module t; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_infinite.v b/SVIncCompil/Testcases/Verilator/t_lint_infinite.v new file mode 100644 index 0000000..7afebb5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_infinite.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (); + + initial begin + forever begin end + // verilator lint_off UNSIGNED + for (reg [31:0] i=0; i>=0; i=i+1) begin end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_inherit.v b/SVIncCompil/Testcases/Verilator/t_lint_inherit.v new file mode 100644 index 0000000..1d30cf9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_inherit.v
@@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + q, + // Inputs + clk, d + ); + input clk; + input d; + output wire [1:0] q; + + // This demonstrates how warning disables should be propagated across module boundaries. + + m1 m1 (/*AUTOINST*/ + // Outputs + .q (q[1:0]), + // Inputs + .clk (clk), + .d (d)); +endmodule + +module m1 + ( + input clk, + input d, + output wire [1:0] q + ); + + m2 m2 (/*AUTOINST*/ + // Outputs + .q (q[1:0]), + // Inputs + .clk (clk), + .d (d)); +endmodule + +module m2 + ( + input clk, + input d, + // Due to bug the below disable used to be ignored. + // verilator lint_off UNOPT + output reg [1:0] q + // verilator lint_on UNOPT + ); + + always @* begin + q[1] = d; + end + + always @* begin + q[0] = q[1]; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_input_eq_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_input_eq_bad.v new file mode 100644 index 0000000..809247f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_input_eq_bad.v
@@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t + ( + input wire i, + input wire i2 = i // BAD + ); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_latch_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_latch_bad.v new file mode 100644 index 0000000..8446ad5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_latch_bad.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + bl, cl, bc, cc, + // Inputs + a + ); + + input logic a; + output logic bl; + output logic cl; + always_latch begin + bl <= a; // No warning + cl = a; + end + + output logic bc; + output logic cc; + always_comb begin + bc <= a; // Warning + cc = a; + end + + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_literal_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_literal_bad.v new file mode 100644 index 0000000..521bd10 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_literal_bad.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Todd Strader. + +module t ( +); + + localparam the_localparam = 8'd256; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_mod_paren_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_mod_paren_bad.v new file mode 100644 index 0000000..353dd2a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_mod_paren_bad.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +// Should have been: +//module t #( + +module t + ( + FOO=1 + ) ( + output bar + ); + + assign bar = FOO; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_modport_dir_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_modport_dir_bad.v new file mode 100644 index 0000000..57ba33f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_modport_dir_bad.v
@@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +interface dummy_if (); + logic signal; + + modport slave + (output signal); + + modport master + (input signal); +endinterface: dummy_if + +module sub + ( + input wire signal_i, + output wire signal_o, + + dummy_if.master dummy_in, + dummy_if.slave dummy_out + ); + + assign dummy_in.signal = signal_i; + assign signal_o = dummy_out.signal; +endmodule + + +module t (/*AUTOARG*/ + // Outputs + signal_o, + // Inputs + signal_i + ); + input signal_i; + output signal_o; + + dummy_if dummy_if (); + + sub sub + ( + .signal_i(signal_i), + .signal_o(signal_o), + .dummy_in(dummy_if), + .dummy_out(dummy_if) + ); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_multidriven_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_multidriven_bad.v new file mode 100644 index 0000000..0eaa068 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_multidriven_bad.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + out, out2, + // Inputs + clk, a0, d0, d1 + ); + + input clk; + input [1:0] a0; + input [7:0] d0; + input [7:0] d1; + output reg [31:0] out; + output reg [15:0] out2; + + reg [7:0] mem [4]; + + always @(posedge clk) begin + mem[a0] <= d0; + end + always @(negedge clk) begin + mem[a0] <= d1; + end + assign out = {mem[3],mem[2],mem[1],mem[0]}; + + always @(posedge clk) begin + out2[7:0] <= d0; + end + always @(negedge clk) begin + out2[15:8] <= d0; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_once_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_once_bad.v new file mode 100644 index 0000000..c70b88e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_once_bad.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +// Check that we report warnings only once on parameterized modules +// Also check that we don't suppress warnings on the same line + +module t (); + sub #(.A(1)) sub1(); + sub #(.A(2)) sub2(); + sub #(.A(3)) sub3(); +endmodule + +module sub; + parameter A = 0; + + reg [A:0] unus1; reg [A:0] unus2; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_only.v b/SVIncCompil/Testcases/Verilator/t_lint_only.v new file mode 100644 index 0000000..ce955f7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_only.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (); + initial begin + $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_pindup_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_pindup_bad.v new file mode 100644 index 0000000..971de76 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_pindup_bad.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t + ( + output wire o, + input wire i, + input wire i2 + ); + + sub + #(, // Not found + .NEXIST(1), // Not found + .P(2), + .P(3)) // Dup + sub (.o(o), + .i(i), + .i(i2), // Dup + .nexist(i2) // Not found + ); + +endmodule + +module sub + #(parameter P=1, + parameter EXIST=9) + ( + output wire o, + input wire i, + input wire exists + ); + + assign o = ~i; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_pkg_colon_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_pkg_colon_bad.v new file mode 100644 index 0000000..1f813e8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_pkg_colon_bad.v
@@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (input mispkg::foo_t a); + reg mispkgb::bar_t b; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_realcvt_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_realcvt_bad.v new file mode 100644 index 0000000..54b659e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_realcvt_bad.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module sub; + integer i; + initial begin + i = 23.2; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_repeat_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_repeat_bad.v new file mode 100644 index 0000000..f0ab52b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_repeat_bad.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Test of select from constant +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (); + + sub #(.Z(0)) sub1 (); + sub #(.Z(1)) sub2 (); + sub #(.Z(2)) sub3 (); + +endmodule + +module sub; + parameter Z = 0; + wire [1:0] a = 2'b11; + wire [0:0] b = a; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_restore_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_restore_bad.v new file mode 100644 index 0000000..7f26375 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_restore_bad.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (); + + reg [3:0] four; + reg [4:0] five; + + // verilator lint_save + + // verilator lint_off WIDTH + initial four = 64'h1; + + // verilator lint_restore + + initial five = 64'h1; + + initial $stop; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_rsvd_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_rsvd_bad.v new file mode 100644 index 0000000..4639f03 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_rsvd_bad.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +config cfgBad; +endconfig + +module t; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_setout_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_setout_bad.v new file mode 100644 index 0000000..0b8b01f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_setout_bad.v
@@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t + ( + input wire reset_l, + input wire clk + ); + + sub sub_I + ( + .clk(clk), + .reset_l(reset_l), + .cpu_if_timeout(1'b0) + ); +endmodule + +module sub + ( + input wire clk, reset_l, + output reg cpu_if_timeout + ); + + always @(posedge clk) begin + if (!reset_l) begin + cpu_if_timeout <= 1'b0; + end + else begin + cpu_if_timeout <= 1'b0; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_subout_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_subout_bad.v new file mode 100644 index 0000000..475803d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_subout_bad.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +// verilator lint_off UNDRIVEN + +module t(); + wire sig; + sub sub0(.out(33'b0)); + sub sub1(.out({32'b0, sig})); + sub sub2(.out({32'b1, sig})); +endmodule + +module sub(output reg [32 : 0] out); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_syncasyncnet_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_syncasyncnet_bad.v new file mode 100644 index 0000000..2335dbc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_syncasyncnet_bad.v
@@ -0,0 +1,98 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + rst_sync_l, rst_both_l, rst_async_l, d, clk + ); + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input clk; // To sub1 of sub1.v, ... + input d; // To sub1 of sub1.v, ... + input rst_async_l; // To sub2 of sub2.v + input rst_both_l; // To sub1 of sub1.v, ... + input rst_sync_l; // To sub1 of sub1.v + // End of automatics + + sub1 sub1 (/*AUTOINST*/ + // Inputs + .clk (clk), + .rst_both_l (rst_both_l), + .rst_sync_l (rst_sync_l), + .d (d)); + sub2 sub2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .rst_both_l (rst_both_l), + .rst_async_l (rst_async_l), + .d (d)); +endmodule + +module sub1 (/*AUTOARG*/ + // Inputs + clk, rst_both_l, rst_sync_l, d + ); + + input clk; + input rst_both_l; + input rst_sync_l; + //input rst_async_l; + input d; + reg q1; + reg q2; + + always @(posedge clk) begin + if (~rst_sync_l) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + q1 <= 1'h0; + // End of automatics + end else begin + q1 <= d; + end + end + + always @(posedge clk) begin + q2 <= (rst_both_l) ? d : 1'b0; + if (0 && q1 && q2) ; + end + +endmodule + +module sub2 (/*AUTOARG*/ + // Inputs + clk, rst_both_l, rst_async_l, d + ); + + input clk; + input rst_both_l; + //input rst_sync_l; + input rst_async_l; + input d; + reg q1; + reg q2; + reg q3; + + always @(posedge clk or negedge rst_async_l) begin + if (~rst_async_l) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + q1 <= 1'h0; + // End of automatics + end else begin + q1 <= d; + end + end + + always @(posedge clk or negedge rst_both_l) begin + q2 <= (~rst_both_l) ? 1'b0 : d; + end + // Make there be more async uses than sync uses + always @(posedge clk or negedge rst_both_l) begin + q3 <= (~rst_both_l) ? 1'b0 : d; + if (0 && q1 && q2 && q3) ; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_unsized_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_unsized_bad.v new file mode 100644 index 0000000..1157b47 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_unsized_bad.v
@@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t; + bit [256:0] num = 'd123456789123456789123456789; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_unsup_deassign.v b/SVIncCompil/Testcases/Verilator/t_lint_unsup_deassign.v new file mode 100644 index 0000000..c931e62 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_unsup_deassign.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +module t + ( + input wire rst + ); + + integer q; + + always @(*) + if (rst) + assign q = 0; + else + deassign q; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_unsup_mixed.v b/SVIncCompil/Testcases/Verilator/t_lint_unsup_mixed.v new file mode 100644 index 0000000..779b039 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_unsup_mixed.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +module t + ( + input wire clk, + input wire a, + input wire b + ); + + integer q; + + // bug1120 + always @ (a or posedge clk) + begin + if (a) + q = 0; + else + q = q + 1; + end + + // bug934 + integer qb; + always @((a && b) or posedge clk) begin + if (a) + qb = 0; + else + qb = qb + 1; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_unused.v b/SVIncCompil/Testcases/Verilator/t_lint_unused.v new file mode 100644 index 0000000..801e50f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_unused.v
@@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +`define STRINGIFY(x) `"x`" + +module t (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input in; // inputs don't get flagged as undriven + output out; // outputs don't get flagged as unused + + sub sub (); + + // Check we don't warn about unused UDP signals + udp_mux2 udpsub (out, in, in, in); + + // Check ignoreds mark as used + reg sysused; + initial $bboxed(sysused); + + // Check file IO. The fopen is the "driver" all else a usage. + integer infile; + integer outfile; + initial begin + outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w"); + $fwrite(outfile, "1\n"); + $fclose(outfile); + infile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "r"); + if ($fgetc(infile) != "1") begin end + end + + wire _unused_ok; + +endmodule + +module sub; + + wire pub /*verilator public*/; // Ignore publics + + localparam THREE = 3; + +endmodule + +primitive udp_mux2 (q, a, b, s); + output q; + input a, b, s; + table + //a b s : out + 1 ? 0 : 1 ; + 0 ? 0 : 0 ; + ? 1 1 : 1 ; + ? 0 1 : 0 ; + 0 0 x : 0 ; + 1 1 x : 1 ; + endtable +endprimitive
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_unused_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_unused_bad.v new file mode 100644 index 0000000..1c17495 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_unused_bad.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/); + + sub sub (); + +endmodule + +module sub; + + wire pub /*verilator public*/; // Ignore publics + + wire [5:0] assunu1 = 0; // Assigned but unused + + wire [3:0] assunub2 = 0; // Assigned but bit 2 unused + + wire [15:10] udrb2; // [14:13,11] is undriven + assign udrb2[15] = 0; + assign udrb2[12] = 0; + assign udrb2[10] = 0; + + wire unu3; // Totally unused + + wire [3:0] mixed; // [3] unused & undr, [2] unused, [1] undr, [0] ok + assign mixed[2] = 0; + assign mixed[0] = 0; + + localparam THREE = 3; + + initial begin + if (0 && assunu1[0] != 0 && udrb2 != 0) begin end + if (0 && assunub2[THREE] && assunub2[1:0]!=0) begin end + if (0 && mixed[1:0] != 0) begin end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_unused_iface.v b/SVIncCompil/Testcases/Verilator/t_lint_unused_iface.v new file mode 100644 index 0000000..cef4386 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_unused_iface.v
@@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +interface dummy_if (); + logic signal; + + modport slave + ( + input signal + ); + + modport master + ( + output signal + ); +endinterface: dummy_if + +module sub + ( + input wire signal_i, + output wire signal_o, + + dummy_if.master dummy_in, + dummy_if.slave dummy_out + ); + + assign dummy_in.signal = signal_i; + assign signal_o = dummy_out.signal; +endmodule + + +module t (/*AUTOARG*/ + // Outputs + signal_o, + // Inputs + signal_i + ); + input signal_i; + output signal_o; + + // verila tor lint_off UUSD + // verila tor lint_off UNDRIVEN + dummy_if dummy_if (); + // verila tor lint_on UUSD + // verila tor lint_on UNDRIVEN + + dummy_if uusd_if (); + + sub sub + ( + .signal_i(signal_i), + .signal_o(signal_o), + .dummy_in(dummy_if), + .dummy_out(dummy_if) + ); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_unused_iface_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_unused_iface_bad.v new file mode 100644 index 0000000..92edeee --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_unused_iface_bad.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +interface dummy_if (); + logic sig_udrv; + logic sig_uusd; +endinterface: dummy_if + +module sub + ( + dummy_if dummy + ); + + assign dummy.sig_uusd = 1'b0 | dummy.sig_udrv; +endmodule + + +module t (/*AUTOARG*/); + + dummy_if dummy (); + + sub sub + (.dummy(dummy) + ); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_width.v b/SVIncCompil/Testcases/Verilator/t_lint_width.v new file mode 100644 index 0000000..06635b6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_width.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (); + + // This isn't a width violation, as +/- 1'b1 is a common idiom + // that's fairly harmless + wire [4:0] five = 5'd5; + wire [4:0] suma = five + 1'b1; + wire [4:0] sumb = 1'b1 + five; + wire [4:0] sumc = five - 1'b1; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_width_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_width_bad.v new file mode 100644 index 0000000..3496242 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_width_bad.v
@@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (); + + // See also t_math_width + + // This shows the uglyness in width warnings across param modules + // TODO: Would be nice to also show relevant parameter settings + p #(.WIDTH(4)) p4 (.in(4'd0)); + p #(.WIDTH(5)) p5 (.in(5'd0)); + + //==== + localparam [3:0] XS = 'hx; // User presumably intended to use 'x + + //==== + wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax + wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is + + //==== + localparam WIDTH = 6; + wire one_bit; + wire [2:0] shifter = 1; + wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); + + //==== + // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS + wire one = 1; + wire [2:0] cnt = (one + one + one + one); + +endmodule + +module p + #(parameter WIDTH=64) + (input [WIDTH-1:0] in); + wire [4:0] out = in; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_width_genfor.v b/SVIncCompil/Testcases/Verilator/t_lint_width_genfor.v new file mode 100644 index 0000000..5cb1c00 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_width_genfor.v
@@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + rc, rg, ri, rp + ); + + parameter P = 15; + + output reg [3:0] rc; + output reg [3:0] rg; + output reg [3:0] ri; + output reg [3:0] rp; + + for (genvar g=0; g < 15; ++g) begin + // bug1487 + // This isn't a width violation, as genvars are generally 32 bits + initial begin + rg = g; + rp = P; + rc = 1; + end + end + initial begin + for (integer i=0; i < 15; ++i) begin + /* verilator lint_off WIDTH */ + ri = i; + /* verilator lint_on WIDTH */ + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_lint_width_genfor_bad.v b/SVIncCompil/Testcases/Verilator/t_lint_width_genfor_bad.v new file mode 100644 index 0000000..2641c90 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_lint_width_genfor_bad.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + rc, rg, ri, rp, rw + ); + + parameter P = 17; + wire [4:0] w = 5'd1; + + output reg [3:0] rc; + output reg [3:0] rg; + output reg [3:0] ri; + output reg [3:0] rp; + + output reg [3:0] rw; + + for (genvar g=16; g < 17; ++g) begin + // Index 17 makes a width violation + initial begin + rg = g; // WidthMin mismatch + rp = P; // WidthMin mismatch + rw = w; // Always a mismatch + rc = 64'h1; // Always a mismatch (as sized) + end + end + initial begin + for (integer i=16; i < 17; ++i) begin + ri = i; // WidthMin mismatch + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_arith.v b/SVIncCompil/Testcases/Verilator/t_math_arith.v new file mode 100644 index 0000000..b9287c6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_arith.v
@@ -0,0 +1,170 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + reg _ranit; + + reg [2:0] xor3; + reg [1:0] xor2; + reg [0:0] xor1; + reg [2:0] ma, mb; + reg [9:0] mc; + reg [4:0] mr1; + reg [30:0] mr2; + + reg [67:0] sh1; + reg [67:0] shq; + + wire foo, bar; assign {foo,bar} = 2'b1_0; + + // surefire lint_off STMINI + initial _ranit = 0; + + wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1 + : (xor2 == 2'b00) ? 5'h2 + : (xor2 == 2'b01) ? 5'h3 + : 5'h4); + + wire ctrue = 1'b1 ? cond_check[1] : cond_check[0]; + wire cfalse = 1'b0 ? cond_check[1] : cond_check[0]; + wire cif = cond_check[2] ? cond_check[1] : cond_check[0]; + wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0]; + + wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1}; + + wire zero = 1'b0; + wire one = 1'b1; + wire [5:0] rep6 = {6{one}}; + + // verilator lint_off WIDTH + localparam [3:0] bug764_p11 = 1'bx; + // verilator lint_on WIDTH + + always @ (posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + + if (rep6 != 6'b111111) $stop; + if (!one) $stop; + if (~one) $stop; + + if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop; + // verilator lint_off WIDTH + if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ? + // verilator lint_on WIDTH + + // surefire lint_off SEQASS + xor1 = 1'b1; + xor2 = 2'b11; + xor3 = 3'b111; + // verilator lint_off WIDTH + if (1'b1 & | (!xor3)) $stop; + // verilator lint_on WIDTH + if ({1{xor1}} != 1'b1) $stop; + if ({4{xor1}} != 4'b1111) $stop; + if (!(~xor1) !== ~(!xor1)) $stop; + if ((^xor1) !== 1'b1) $stop; + if ((^xor2) !== 1'b0) $stop; + if ((^xor3) !== 1'b1) $stop; + if (~(^xor2) !== 1'b1) $stop; + if (~(^xor3) !== 1'b0) $stop; + if ((^~xor1) !== 1'b0) $stop; + if ((^~xor2) !== 1'b1) $stop; + if ((^~xor3) !== 1'b0) $stop; + if ((~^xor1) !== 1'b0) $stop; + if ((~^xor2) !== 1'b1) $stop; + if ((~^xor3) !== 1'b0) $stop; + xor1 = 1'b0; + xor2 = 2'b10; + xor3 = 3'b101; + if ((^xor1) !== 1'b0) $stop; + if ((^xor2) !== 1'b1) $stop; + if ((^xor3) !== 1'b0) $stop; + if (~(^xor2) !== 1'b0) $stop; + if (~(^xor3) !== 1'b1) $stop; + if ((^~xor1) !== 1'b1) $stop; + if ((^~xor2) !== 1'b0) $stop; + if ((^~xor3) !== 1'b1) $stop; + if ((~^xor1) !== 1'b1) $stop; + if ((~^xor2) !== 1'b0) $stop; + if ((~^xor3) !== 1'b1) $stop; + + ma = 3'h3; + mb = 3'h4; + mc = 10'h5; + + mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch + mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch + if (mr1 !== 5'd12) $stop; + if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch + + sh1 = 68'hf_def1_9abc_5678_1234; + shq = sh1 >> 16; + if (shq !== 68'hf_def1_9abc_5678) $stop; + shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch + if (shq !== 68'h1_9abc_5678_1234_0000) $stop; + + // surefire lint_on SEQASS + + // Test display extraction widthing + $display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]); + + // bug736 + //verilator lint_off WIDTH + if ((~| 4'b0000) != 4'b0001) $stop; + if ((~| 4'b0010) != 4'b0000) $stop; + if ((~& 4'b1111) != 4'b0000) $stop; + if ((~& 4'b1101) != 4'b0001) $stop; + //verilator lint_on WIDTH + + // bug764 + //verilator lint_off WIDTH + // X does not sign extend + if (bug764_p11 !== 4'b000x) $stop; + if (~& bug764_p11 !== 1'b1) $stop; + //verilator lint_on WIDTH + // However IEEE 2017 5.7.1 says for constants that smaller-sizes do extend + if (4'bx !== 4'bxxxx) $stop; + if (4'bz !== 4'bzzzz) $stop; + if (4'b1 !== 4'b0001) $stop; + + if ((0 -> 0) != 1'b1) $stop; + if ((0 -> 1) != 1'b1) $stop; + if ((1 -> 0) != 1'b0) $stop; + if ((1 -> 1) != 1'b1) $stop; + + if ((0 <-> 0) != 1'b1) $stop; + if ((0 <-> 1) != 1'b0) $stop; + if ((1 <-> 0) != 1'b0) $stop; + if ((1 <-> 1) != 1'b1) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + end + + + reg [63:0] m_data_pipe2_r; + reg [31:0] m_corr_data_w0, m_corr_data_w1; + reg [7:0] m_corr_data_b8; + initial begin + m_data_pipe2_r = 64'h1234_5678_9abc_def0; + {m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0] + m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0] + m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16] + m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8] + m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4] + m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0] + }; + if (m_corr_data_w0 != 32'haf36de00) $stop; + if (m_corr_data_w1 != 32'h1a2b3c4c) $stop; + if (m_corr_data_b8 != 8'h12) $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_clog2.v b/SVIncCompil/Testcases/Verilator/t_math_clog2.v new file mode 100644 index 0000000..3fad0bc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_clog2.v
@@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`ifdef verilator + `define CLOG2 $clog2 +`else + `define CLOG2 clog2_emulate +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Need temp wires as function has different width rules than $clog2 + wire [127:0] pows = 128'h1<<crc[7:0]; + wire [127:0] npows = ~pows; + + wire [31:0] out = `CLOG2(crc[7:0]); + wire [31:0] out2 = `CLOG2(crc); + wire [31:0] out3 = `CLOG2(pows); + wire [31:0] out4 = `CLOG2(npows); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out4[15:0], out3[15:0], out2[15:0], out[15:0]}; + +`define EXPECTED_SUM 64'h73c48afee4f0cb57 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + crc <= 64'h0; + if (`CLOG2(32'h0) != 0) $stop; + if (`CLOG2(32'h1) != 0) $stop; + if (`CLOG2(32'h4) != 2) $stop; + if (`CLOG2(32'h7) != 3) $stop; + if (`CLOG2(32'h8) != 3) $stop; + if (`CLOG2(32'h9) != 4) $stop; + if (`CLOG2({32{1'b1}}) != 32) $stop; + if (`CLOG2({1'b1,32'b0}) != 32) $stop; + if (`CLOG2({64{1'b1}}) != 64) $stop; + if (`CLOG2({1'b1,64'b0}) != 64) $stop; + if (`CLOG2({128{1'b1}}) != 128) $stop; + if (`CLOG2({1'b1,128'b0}) != 128) $stop; + if (`CLOG2({2'b10,128'b0}) != 129) $stop; + end + else if (cyc==1) begin + crc <= 64'h1; + if (result[31:0] != {16'd0, 16'd0}) $stop; + end + else if (cyc==2) begin + crc <= 64'h3; + if (result[31:0] != {16'd0, 16'd0}) $stop; + end + else if (cyc==3) begin + crc <= {64{1'b1}}; + if (result[31:0] != {16'd2, 16'd2}) $stop; + end + else if (cyc==4) begin + if (result[31:0] != {16'd64, 16'd8}) $stop; + end + else if (cyc==8) begin + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hcbc77bb9b3784ea0) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + function integer clog2_emulate(input [130:0] arg); + begin + if (arg!=0) arg = arg - 1; + for (clog2_emulate=0; arg!=0; clog2_emulate=clog2_emulate+1) + arg = (arg >> 1); + end + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_cmp.v b/SVIncCompil/Testcases/Verilator/t_math_cmp.v new file mode 100644 index 0000000..6402e20 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_cmp.v
@@ -0,0 +1,166 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [2:0] index_a; + reg [2:0] index_b; + + prover #(4) p4 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(32) p32 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(63) p63 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(64) p64 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(72) p72 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(126) p126 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(128) p128 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + + integer cyc; initial cyc=0; + initial index_a = 3'b0; + initial index_b = 3'b0; + always @* begin + index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4; + index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4; + end + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module prover ( + input clk, + input [2:0] index_a, + input [2:0] index_b + ); + + parameter WIDTH = 4; + + + reg signed [WIDTH-1:0] as; + reg signed [WIDTH-1:0] bs; + wire [WIDTH-1:0] b = bs; + + always @* begin + casez (index_a) + 3'd0: as = {(WIDTH){1'd0}}; // 0 + 3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 + 3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv + 3'd3: as = {(WIDTH){1'd1}}; // -1 + 3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv + default: $stop; + endcase + casez (index_b) + 3'd0: bs = {(WIDTH){1'd0}}; // 0 + 3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 + 3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv + 3'd3: bs = {(WIDTH){1'd1}}; // -1 + 3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv + default: $stop; + endcase + end + + reg [7:0] results[4:0][4:0]; + + wire gt = as>b; + wire gts = as>bs; + wire gte = as>=b; + wire gtes = as>=bs; + wire lt = as<b; + wire lts = as<bs; + wire lte = as<=b; + wire ltes = as<=bs; + + reg [7:0] exp; + reg [7:0] got; + + integer cyc=0; + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc>2) begin +`ifdef TEST_VERBOSE + $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", + index_a, index_b, + gt, gts, gte, gtes, lt, lts, lte, ltes); +`endif + exp = results[index_a][index_b]; + got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; + if (exp !== got) begin + $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp); + $stop; + end + end + end + + // Result table + initial begin + // Indexes: 0, 1, -1, 127, -128 + // Gt Gts Gte Gtes Lt Lts Lte Ltes + results[0][0] = 8'b0_0_1_1_0_0_1_1; + results[0][1] = 8'b0_0_0_0_1_1_1_1; + results[0][2] = 8'b0_0_1_1_0_0_1_1; + results[0][3] = 8'b0_1_0_1_1_0_1_0; + results[0][4] = 8'b0_1_0_1_1_0_1_0; + results[1][0] = 8'b1_1_1_1_0_0_0_0; + results[1][1] = 8'b0_0_1_1_0_0_1_1; + results[1][2] = 8'b1_1_1_1_0_0_0_0; + results[1][3] = 8'b0_1_0_1_1_0_1_0; + results[1][4] = 8'b0_1_0_1_1_0_1_0; + results[2][0] = 8'b0_0_1_1_0_0_1_1; + results[2][1] = 8'b0_0_0_0_1_1_1_1; + results[2][2] = 8'b0_0_1_1_0_0_1_1; + results[2][3] = 8'b0_1_0_1_1_0_1_0; + results[2][4] = 8'b0_1_0_1_1_0_1_0; + results[3][0] = 8'b1_0_1_0_0_1_0_1; + results[3][1] = 8'b1_0_1_0_0_1_0_1; + results[3][2] = 8'b1_0_1_0_0_1_0_1; + results[3][3] = 8'b0_0_1_1_0_0_1_1; + results[3][4] = 8'b1_1_1_1_0_0_0_0; + results[4][0] = 8'b1_0_1_0_0_1_0_1; + results[4][1] = 8'b1_0_1_0_0_1_0_1; + results[4][2] = 8'b1_0_1_0_0_1_0_1; + results[4][3] = 8'b0_0_0_0_1_1_1_1; + results[4][4] = 8'b0_0_1_1_0_0_1_1; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_concat.v b/SVIncCompil/Testcases/Verilator/t_math_concat.v new file mode 100644 index 0000000..7a6a79f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_concat.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [255:0] i; + wire [255:0] q; + + assign q = { + i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], + i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], + i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], + i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], + i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], + i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], + i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], + i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], + i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], + i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], + i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], + i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], + i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], + i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], + i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], + i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], + i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], + i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], + i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], + i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], + i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], + i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], + i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], + i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], + i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], + i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], + i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], + i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], + i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], + i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], + i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], + i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] + }; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%x %x\n", q, i); +`endif + if (cyc==1) begin + i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; + end + if (cyc==2) begin + i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; + end + if (cyc==3) begin + if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_concat0.v b/SVIncCompil/Testcases/Verilator/t_math_concat0.v new file mode 100644 index 0000000..eab897d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_concat0.v
@@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [15:0] in = crc[15:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [15:0] outa; // From test of Test.v + wire [15:0] outb; // From test of Test.v + wire [15:0] outc; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .outa (outa[15:0]), + .outb (outb[15:0]), + .outc (outc[15:0]), + // Inputs + .clk (clk), + .in (in[15:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {16'h0, outa, outb, outc}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h09be74b1b0f8c35d + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + outa, outb, outc, + // Inputs + clk, in + ); + + input clk; + input [15:0] in; + output reg [15:0] outa; + output reg [15:0] outb; + output reg [15:0] outc; + + parameter WIDTH = 0; + always @(posedge clk) begin + outa <= {in}; + outb <= {{WIDTH{1'b0}}, in}; + outc <= {in, {WIDTH{1'b0}}}; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_concat64.v b/SVIncCompil/Testcases/Verilator/t_math_concat64.v new file mode 100644 index 0000000..f40739b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_concat64.v
@@ -0,0 +1,130 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [127:0] i; + wire [127:0] q1; + wire [127:0] q32; + wire [127:0] q64; + wire [63:0] q64_low; + + assign q1 = { + i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], + i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], + i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], + i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], + + i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], + i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], + i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], + i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1], + + i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], + i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], + i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], + i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], + + i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], + i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], + i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], + i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; + + assign q64[127:64] = { + i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], + i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], + i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], + i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], + + i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], + i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], + i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], + i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; + assign q64[63:0] = { + i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], + i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], + i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], + i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], + + i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], + i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], + i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], + i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; + + assign q64_low = { + i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], + i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], + i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], + i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], + + i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], + i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], + i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], + i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; + + assign q32[127:96] = { + i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], + i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], + i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], + i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]}; + assign q32[95:64] = { + i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], + i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], + i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], + i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; + assign q32[63:32] = { + i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], + i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], + i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], + i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]}; + assign q32[31:0] = { + i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], + i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], + i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], + i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%x %x\n", q1, i); +`endif + if (cyc==1) begin + i <= 128'hed388e646c843d35de489bab2413d770; + end + if (cyc==2) begin + i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3; + if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==3) begin + i <= 128'he236ddfddddbdad20a48e039c9f395b8; + if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==4) begin + i <= 128'h45e0eb7642b148537491f3da147e7f26; + if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_concat_sel_bad.v b/SVIncCompil/Testcases/Verilator/t_math_concat_sel_bad.v new file mode 100644 index 0000000..78ec137 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_concat_sel_bad.v
@@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [3:0] a = crc[3:0]; + wire [3:0] b = crc[19:16]; + + // TEST + wire [3:0] out1 = {a,b}[2 +: 4]; + wire [3:0] out2 = {a,b}[5 -: 4]; + wire [3:0] out3 = {a,b}[5 : 2]; + wire [0:0] out4 = {a,b}[2]; + + // Aggregate outputs into a single result vector + wire [63:0] result = {51'h0, out4, out3, out2, out1}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_cond_huge.v b/SVIncCompil/Testcases/Verilator/t_math_cond_huge.v new file mode 100644 index 0000000..1205c6c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_cond_huge.v
@@ -0,0 +1,415 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [7:0] sel = crc[7:0]; + wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] out; // From test of Test.v + // End of automatics + + /* Test AUTO_TEMPLATE ( + .i\([0-9]+\) (in[\1 +:4]), + ); */ + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + // Inputs + .sel (sel[7:0]), + .i0 (in[0 +:4]), // Templated + .i1 (in[1 +:4]), // Templated + .i2 (in[2 +:4]), // Templated + .i3 (in[3 +:4]), // Templated + .i4 (in[4 +:4]), // Templated + .i5 (in[5 +:4]), // Templated + .i6 (in[6 +:4]), // Templated + .i7 (in[7 +:4]), // Templated + .i8 (in[8 +:4]), // Templated + .i9 (in[9 +:4]), // Templated + .i10 (in[10 +:4]), // Templated + .i11 (in[11 +:4]), // Templated + .i12 (in[12 +:4]), // Templated + .i13 (in[13 +:4]), // Templated + .i14 (in[14 +:4]), // Templated + .i15 (in[15 +:4]), // Templated + .i16 (in[16 +:4]), // Templated + .i17 (in[17 +:4]), // Templated + .i18 (in[18 +:4]), // Templated + .i19 (in[19 +:4]), // Templated + .i20 (in[20 +:4]), // Templated + .i21 (in[21 +:4]), // Templated + .i22 (in[22 +:4]), // Templated + .i23 (in[23 +:4]), // Templated + .i24 (in[24 +:4]), // Templated + .i25 (in[25 +:4]), // Templated + .i26 (in[26 +:4]), // Templated + .i27 (in[27 +:4]), // Templated + .i28 (in[28 +:4]), // Templated + .i29 (in[29 +:4]), // Templated + .i30 (in[30 +:4]), // Templated + .i31 (in[31 +:4]), // Templated + .i32 (in[32 +:4]), // Templated + .i33 (in[33 +:4]), // Templated + .i34 (in[34 +:4]), // Templated + .i35 (in[35 +:4]), // Templated + .i36 (in[36 +:4]), // Templated + .i37 (in[37 +:4]), // Templated + .i38 (in[38 +:4]), // Templated + .i39 (in[39 +:4]), // Templated + .i40 (in[40 +:4]), // Templated + .i41 (in[41 +:4]), // Templated + .i42 (in[42 +:4]), // Templated + .i43 (in[43 +:4]), // Templated + .i44 (in[44 +:4]), // Templated + .i45 (in[45 +:4]), // Templated + .i46 (in[46 +:4]), // Templated + .i47 (in[47 +:4]), // Templated + .i48 (in[48 +:4]), // Templated + .i49 (in[49 +:4]), // Templated + .i50 (in[50 +:4]), // Templated + .i51 (in[51 +:4]), // Templated + .i52 (in[52 +:4]), // Templated + .i53 (in[53 +:4]), // Templated + .i54 (in[54 +:4]), // Templated + .i55 (in[55 +:4]), // Templated + .i56 (in[56 +:4]), // Templated + .i57 (in[57 +:4]), // Templated + .i58 (in[58 +:4]), // Templated + .i59 (in[59 +:4]), // Templated + .i60 (in[60 +:4]), // Templated + .i61 (in[61 +:4]), // Templated + .i62 (in[62 +:4]), // Templated + .i63 (in[63 +:4]), // Templated + .i64 (in[64 +:4]), // Templated + .i65 (in[65 +:4]), // Templated + .i66 (in[66 +:4]), // Templated + .i67 (in[67 +:4]), // Templated + .i68 (in[68 +:4]), // Templated + .i69 (in[69 +:4]), // Templated + .i70 (in[70 +:4]), // Templated + .i71 (in[71 +:4]), // Templated + .i72 (in[72 +:4]), // Templated + .i73 (in[73 +:4]), // Templated + .i74 (in[74 +:4]), // Templated + .i75 (in[75 +:4]), // Templated + .i76 (in[76 +:4]), // Templated + .i77 (in[77 +:4]), // Templated + .i78 (in[78 +:4]), // Templated + .i79 (in[79 +:4]), // Templated + .i80 (in[80 +:4]), // Templated + .i81 (in[81 +:4]), // Templated + .i82 (in[82 +:4]), // Templated + .i83 (in[83 +:4]), // Templated + .i84 (in[84 +:4]), // Templated + .i85 (in[85 +:4]), // Templated + .i86 (in[86 +:4]), // Templated + .i87 (in[87 +:4]), // Templated + .i88 (in[88 +:4]), // Templated + .i89 (in[89 +:4]), // Templated + .i90 (in[90 +:4]), // Templated + .i91 (in[91 +:4]), // Templated + .i92 (in[92 +:4]), // Templated + .i93 (in[93 +:4]), // Templated + .i94 (in[94 +:4]), // Templated + .i95 (in[95 +:4]), // Templated + .i96 (in[96 +:4]), // Templated + .i97 (in[97 +:4]), // Templated + .i98 (in[98 +:4]), // Templated + .i99 (in[99 +:4]), // Templated + .i100 (in[100 +:4]), // Templated + .i101 (in[101 +:4]), // Templated + .i102 (in[102 +:4]), // Templated + .i103 (in[103 +:4]), // Templated + .i104 (in[104 +:4]), // Templated + .i105 (in[105 +:4]), // Templated + .i106 (in[106 +:4]), // Templated + .i107 (in[107 +:4]), // Templated + .i108 (in[108 +:4]), // Templated + .i109 (in[109 +:4]), // Templated + .i110 (in[110 +:4]), // Templated + .i111 (in[111 +:4]), // Templated + .i112 (in[112 +:4]), // Templated + .i113 (in[113 +:4]), // Templated + .i114 (in[114 +:4]), // Templated + .i115 (in[115 +:4]), // Templated + .i116 (in[116 +:4]), // Templated + .i117 (in[117 +:4]), // Templated + .i118 (in[118 +:4]), // Templated + .i119 (in[119 +:4]), // Templated + .i120 (in[120 +:4]), // Templated + .i121 (in[121 +:4]), // Templated + .i122 (in[122 +:4]), // Templated + .i123 (in[123 +:4]), // Templated + .i124 (in[124 +:4]), // Templated + .i125 (in[125 +:4]), // Templated + .i126 (in[126 +:4]), // Templated + .i127 (in[127 +:4]), // Templated + .i128 (in[128 +:4]), // Templated + .i129 (in[129 +:4]), // Templated + .i130 (in[130 +:4]), // Templated + .i131 (in[131 +:4]), // Templated + .i132 (in[132 +:4]), // Templated + .i133 (in[133 +:4]), // Templated + .i134 (in[134 +:4]), // Templated + .i135 (in[135 +:4]), // Templated + .i136 (in[136 +:4]), // Templated + .i137 (in[137 +:4]), // Templated + .i138 (in[138 +:4]), // Templated + .i139 (in[139 +:4]), // Templated + .i140 (in[140 +:4]), // Templated + .i141 (in[141 +:4]), // Templated + .i142 (in[142 +:4]), // Templated + .i143 (in[143 +:4]), // Templated + .i144 (in[144 +:4]), // Templated + .i145 (in[145 +:4]), // Templated + .i146 (in[146 +:4]), // Templated + .i147 (in[147 +:4]), // Templated + .i148 (in[148 +:4]), // Templated + .i149 (in[149 +:4]), // Templated + .i150 (in[150 +:4]), // Templated + .i151 (in[151 +:4]), // Templated + .i152 (in[152 +:4]), // Templated + .i153 (in[153 +:4]), // Templated + .i154 (in[154 +:4]), // Templated + .i155 (in[155 +:4]), // Templated + .i156 (in[156 +:4]), // Templated + .i157 (in[157 +:4]), // Templated + .i158 (in[158 +:4]), // Templated + .i159 (in[159 +:4]), // Templated + .i160 (in[160 +:4]), // Templated + .i161 (in[161 +:4]), // Templated + .i162 (in[162 +:4]), // Templated + .i163 (in[163 +:4]), // Templated + .i164 (in[164 +:4]), // Templated + .i165 (in[165 +:4]), // Templated + .i166 (in[166 +:4]), // Templated + .i167 (in[167 +:4]), // Templated + .i168 (in[168 +:4]), // Templated + .i169 (in[169 +:4]), // Templated + .i170 (in[170 +:4]), // Templated + .i171 (in[171 +:4]), // Templated + .i172 (in[172 +:4]), // Templated + .i173 (in[173 +:4]), // Templated + .i174 (in[174 +:4]), // Templated + .i175 (in[175 +:4]), // Templated + .i176 (in[176 +:4]), // Templated + .i177 (in[177 +:4]), // Templated + .i178 (in[178 +:4]), // Templated + .i179 (in[179 +:4]), // Templated + .i180 (in[180 +:4]), // Templated + .i181 (in[181 +:4]), // Templated + .i182 (in[182 +:4]), // Templated + .i183 (in[183 +:4]), // Templated + .i184 (in[184 +:4]), // Templated + .i185 (in[185 +:4]), // Templated + .i186 (in[186 +:4]), // Templated + .i187 (in[187 +:4]), // Templated + .i188 (in[188 +:4]), // Templated + .i189 (in[189 +:4]), // Templated + .i190 (in[190 +:4]), // Templated + .i191 (in[191 +:4]), // Templated + .i192 (in[192 +:4]), // Templated + .i193 (in[193 +:4]), // Templated + .i194 (in[194 +:4]), // Templated + .i195 (in[195 +:4]), // Templated + .i196 (in[196 +:4]), // Templated + .i197 (in[197 +:4]), // Templated + .i198 (in[198 +:4]), // Templated + .i199 (in[199 +:4]), // Templated + .i200 (in[200 +:4]), // Templated + .i201 (in[201 +:4]), // Templated + .i202 (in[202 +:4]), // Templated + .i203 (in[203 +:4]), // Templated + .i204 (in[204 +:4]), // Templated + .i205 (in[205 +:4]), // Templated + .i206 (in[206 +:4]), // Templated + .i207 (in[207 +:4]), // Templated + .i208 (in[208 +:4]), // Templated + .i209 (in[209 +:4]), // Templated + .i210 (in[210 +:4]), // Templated + .i211 (in[211 +:4]), // Templated + .i212 (in[212 +:4]), // Templated + .i213 (in[213 +:4]), // Templated + .i214 (in[214 +:4]), // Templated + .i215 (in[215 +:4]), // Templated + .i216 (in[216 +:4]), // Templated + .i217 (in[217 +:4]), // Templated + .i218 (in[218 +:4]), // Templated + .i219 (in[219 +:4]), // Templated + .i220 (in[220 +:4]), // Templated + .i221 (in[221 +:4]), // Templated + .i222 (in[222 +:4]), // Templated + .i223 (in[223 +:4]), // Templated + .i224 (in[224 +:4]), // Templated + .i225 (in[225 +:4]), // Templated + .i226 (in[226 +:4]), // Templated + .i227 (in[227 +:4]), // Templated + .i228 (in[228 +:4]), // Templated + .i229 (in[229 +:4]), // Templated + .i230 (in[230 +:4]), // Templated + .i231 (in[231 +:4]), // Templated + .i232 (in[232 +:4]), // Templated + .i233 (in[233 +:4]), // Templated + .i234 (in[234 +:4]), // Templated + .i235 (in[235 +:4]), // Templated + .i236 (in[236 +:4]), // Templated + .i237 (in[237 +:4]), // Templated + .i238 (in[238 +:4]), // Templated + .i239 (in[239 +:4]), // Templated + .i240 (in[240 +:4]), // Templated + .i241 (in[241 +:4]), // Templated + .i242 (in[242 +:4]), // Templated + .i243 (in[243 +:4]), // Templated + .i244 (in[244 +:4]), // Templated + .i245 (in[245 +:4]), // Templated + .i246 (in[246 +:4]), // Templated + .i247 (in[247 +:4]), // Templated + .i248 (in[248 +:4]), // Templated + .i249 (in[249 +:4]), // Templated + .i250 (in[250 +:4]), // Templated + .i251 (in[251 +:4]), // Templated + .i252 (in[252 +:4]), // Templated + .i253 (in[253 +:4]), // Templated + .i254 (in[254 +:4]), // Templated + .i255 (in[255 +:4])); // Templated + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h36f3051d15caf07a + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( output wire [3:0] out, + + input [7:0] sel, + + input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, + i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, + i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, + i51, i52, i53, i54, i55, i56, i57, i58, i59, i60, i61, i62, i63, i64, i65, i66, i67, + i68, i69, i70, i71, i72, i73, i74, i75, i76, i77, i78, i79, i80, i81, i82, i83, i84, + i85, i86, i87, i88, i89, i90, i91, i92, i93, i94, i95, i96, i97, i98, i99, i100, i101, + i102, i103, i104, i105, i106, i107, i108, i109, i110, i111, i112, i113, i114, i115, + i116, i117, i118, i119, i120, i121, i122, i123, i124, i125, i126, i127, i128, i129, + i130, i131, i132, i133, i134, i135, i136, i137, i138, i139, i140, i141, i142, i143, + i144, i145, i146, i147, i148, i149, i150, i151, i152, i153, i154, i155, i156, i157, + i158, i159, i160, i161, i162, i163, i164, i165, i166, i167, i168, i169, i170, i171, + i172, i173, i174, i175, i176, i177, i178, i179, i180, i181, i182, i183, i184, i185, + i186, i187, i188, i189, i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, + i200, i201, i202, i203, i204, i205, i206, i207, i208, i209, i210, i211, i212, i213, + i214, i215, i216, i217, i218, i219, i220, i221, i222, i223, i224, i225, i226, i227, + i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241, + i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255 + ); + + assign out + = (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3 + : (sel==8'h04) ? i4 : (sel==8'h05) ? i5 : (sel==8'h06) ? i6 : (sel==8'h07) ? i7 + : (sel==8'h08) ? i8 : (sel==8'h09) ? i9 : (sel==8'h0a) ? i10 : (sel==8'h0b) ? i11 + : (sel==8'h0c) ? i12 : (sel==8'h0d) ? i13 : (sel==8'h0e) ? i14 : (sel==8'h0f) ? i15 + : (sel==8'h10) ? i16 : (sel==8'h11) ? i17 : (sel==8'h12) ? i18 : (sel==8'h13) ? i19 + : (sel==8'h14) ? i20 : (sel==8'h15) ? i21 : (sel==8'h16) ? i22 : (sel==8'h17) ? i23 + : (sel==8'h18) ? i24 : (sel==8'h19) ? i25 : (sel==8'h1a) ? i26 : (sel==8'h1b) ? i27 + : (sel==8'h1c) ? i28 : (sel==8'h1d) ? i29 : (sel==8'h1e) ? i30 : (sel==8'h1f) ? i31 + : (sel==8'h20) ? i32 : (sel==8'h21) ? i33 : (sel==8'h22) ? i34 : (sel==8'h23) ? i35 + : (sel==8'h24) ? i36 : (sel==8'h25) ? i37 : (sel==8'h26) ? i38 : (sel==8'h27) ? i39 + : (sel==8'h28) ? i40 : (sel==8'h29) ? i41 : (sel==8'h2a) ? i42 : (sel==8'h2b) ? i43 + : (sel==8'h2c) ? i44 : (sel==8'h2d) ? i45 : (sel==8'h2e) ? i46 : (sel==8'h2f) ? i47 + : (sel==8'h30) ? i48 : (sel==8'h31) ? i49 : (sel==8'h32) ? i50 : (sel==8'h33) ? i51 + : (sel==8'h34) ? i52 : (sel==8'h35) ? i53 : (sel==8'h36) ? i54 : (sel==8'h37) ? i55 + : (sel==8'h38) ? i56 : (sel==8'h39) ? i57 : (sel==8'h3a) ? i58 : (sel==8'h3b) ? i59 + : (sel==8'h3c) ? i60 : (sel==8'h3d) ? i61 : (sel==8'h3e) ? i62 : (sel==8'h3f) ? i63 + : (sel==8'h40) ? i64 : (sel==8'h41) ? i65 : (sel==8'h42) ? i66 : (sel==8'h43) ? i67 + : (sel==8'h44) ? i68 : (sel==8'h45) ? i69 : (sel==8'h46) ? i70 : (sel==8'h47) ? i71 + : (sel==8'h48) ? i72 : (sel==8'h49) ? i73 : (sel==8'h4a) ? i74 : (sel==8'h4b) ? i75 + : (sel==8'h4c) ? i76 : (sel==8'h4d) ? i77 : (sel==8'h4e) ? i78 : (sel==8'h4f) ? i79 + : (sel==8'h50) ? i80 : (sel==8'h51) ? i81 : (sel==8'h52) ? i82 : (sel==8'h53) ? i83 + : (sel==8'h54) ? i84 : (sel==8'h55) ? i85 : (sel==8'h56) ? i86 : (sel==8'h57) ? i87 + : (sel==8'h58) ? i88 : (sel==8'h59) ? i89 : (sel==8'h5a) ? i90 : (sel==8'h5b) ? i91 + : (sel==8'h5c) ? i92 : (sel==8'h5d) ? i93 : (sel==8'h5e) ? i94 : (sel==8'h5f) ? i95 + : (sel==8'h60) ? i96 : (sel==8'h61) ? i97 : (sel==8'h62) ? i98 : (sel==8'h63) ? i99 + : (sel==8'h64) ? i100 : (sel==8'h65) ? i101 : (sel==8'h66) ? i102 : (sel==8'h67) ? i103 + : (sel==8'h68) ? i104 : (sel==8'h69) ? i105 : (sel==8'h6a) ? i106 : (sel==8'h6b) ? i107 + : (sel==8'h6c) ? i108 : (sel==8'h6d) ? i109 : (sel==8'h6e) ? i110 : (sel==8'h6f) ? i111 + : (sel==8'h70) ? i112 : (sel==8'h71) ? i113 : (sel==8'h72) ? i114 : (sel==8'h73) ? i115 + : (sel==8'h74) ? i116 : (sel==8'h75) ? i117 : (sel==8'h76) ? i118 : (sel==8'h77) ? i119 + : (sel==8'h78) ? i120 : (sel==8'h79) ? i121 : (sel==8'h7a) ? i122 : (sel==8'h7b) ? i123 + : (sel==8'h7c) ? i124 : (sel==8'h7d) ? i125 : (sel==8'h7e) ? i126 : (sel==8'h7f) ? i127 + : (sel==8'h80) ? i128 : (sel==8'h81) ? i129 : (sel==8'h82) ? i130 : (sel==8'h83) ? i131 + : (sel==8'h84) ? i132 : (sel==8'h85) ? i133 : (sel==8'h86) ? i134 : (sel==8'h87) ? i135 + : (sel==8'h88) ? i136 : (sel==8'h89) ? i137 : (sel==8'h8a) ? i138 : (sel==8'h8b) ? i139 + : (sel==8'h8c) ? i140 : (sel==8'h8d) ? i141 : (sel==8'h8e) ? i142 : (sel==8'h8f) ? i143 + : (sel==8'h90) ? i144 : (sel==8'h91) ? i145 : (sel==8'h92) ? i146 : (sel==8'h93) ? i147 + : (sel==8'h94) ? i148 : (sel==8'h95) ? i149 : (sel==8'h96) ? i150 : (sel==8'h98) ? i151 + : (sel==8'h99) ? i152 : (sel==8'h9a) ? i153 : (sel==8'h9b) ? i154 : (sel==8'h9c) ? i155 + : (sel==8'h9d) ? i156 : (sel==8'h9e) ? i157 : (sel==8'h9f) ? i158 : (sel==8'ha0) ? i159 + : (sel==8'ha1) ? i160 : (sel==8'ha2) ? i161 : (sel==8'ha3) ? i162 : (sel==8'ha4) ? i163 + : (sel==8'ha5) ? i164 : (sel==8'ha6) ? i165 : (sel==8'ha7) ? i166 : (sel==8'ha8) ? i167 + : (sel==8'ha9) ? i168 : (sel==8'haa) ? i169 : (sel==8'hab) ? i170 : (sel==8'hac) ? i171 + : (sel==8'had) ? i172 : (sel==8'hae) ? i173 : (sel==8'haf) ? i174 : (sel==8'hb0) ? i175 + : (sel==8'hb1) ? i176 : (sel==8'hb2) ? i177 : (sel==8'hb3) ? i178 : (sel==8'hb4) ? i179 + : (sel==8'hb5) ? i180 : (sel==8'hb6) ? i181 : (sel==8'hb7) ? i182 : (sel==8'hb8) ? i183 + : (sel==8'hb9) ? i184 : (sel==8'hba) ? i185 : (sel==8'hbb) ? i186 : (sel==8'hbc) ? i187 + : (sel==8'hbd) ? i188 : (sel==8'hbe) ? i189 : (sel==8'hbf) ? i190 : (sel==8'hc0) ? i191 + : (sel==8'hc1) ? i192 : (sel==8'hc2) ? i193 : (sel==8'hc3) ? i194 : (sel==8'hc4) ? i195 + : (sel==8'hc5) ? i196 : (sel==8'hc6) ? i197 : (sel==8'hc7) ? i198 : (sel==8'hc8) ? i199 + : (sel==8'hc9) ? i200 : (sel==8'hca) ? i201 : (sel==8'hcb) ? i202 : (sel==8'hcc) ? i203 + : (sel==8'hcd) ? i204 : (sel==8'hce) ? i205 : (sel==8'hcf) ? i206 : (sel==8'hd0) ? i207 + : (sel==8'hd1) ? i208 : (sel==8'hd2) ? i209 : (sel==8'hd3) ? i210 : (sel==8'hd4) ? i211 + : (sel==8'hd5) ? i212 : (sel==8'hd6) ? i213 : (sel==8'hd7) ? i214 : (sel==8'hd8) ? i215 + : (sel==8'hd9) ? i216 : (sel==8'hda) ? i217 : (sel==8'hdb) ? i218 : (sel==8'hdc) ? i219 + : (sel==8'hdd) ? i220 : (sel==8'hde) ? i221 : (sel==8'hdf) ? i222 : (sel==8'he0) ? i223 + : (sel==8'he1) ? i224 : (sel==8'he2) ? i225 : (sel==8'he3) ? i226 : (sel==8'he4) ? i227 + : (sel==8'he5) ? i228 : (sel==8'he6) ? i229 : (sel==8'he7) ? i230 : (sel==8'he8) ? i231 + : (sel==8'he9) ? i232 : (sel==8'hea) ? i233 : (sel==8'heb) ? i234 : (sel==8'hec) ? i235 + : (sel==8'hed) ? i236 : (sel==8'hee) ? i237 : (sel==8'hef) ? i238 : (sel==8'hf0) ? i239 + : (sel==8'hf1) ? i240 : (sel==8'hf2) ? i241 : (sel==8'hf3) ? i242 : (sel==8'hf4) ? i243 + : (sel==8'hf5) ? i244 : (sel==8'hf6) ? i245 : (sel==8'hf7) ? i246 : (sel==8'hf8) ? i247 + : (sel==8'hf9) ? i248 : (sel==8'hfa) ? i249 : (sel==8'hfb) ? i250 : (sel==8'hfc) ? i251 + : (sel==8'hfd) ? i252 : (sel==8'hfe) ? i253 : (sel==8'hff) ? i254 : i255; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_const.v b/SVIncCompil/Testcases/Verilator/t_math_const.v new file mode 100644 index 0000000..abd6478 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_const.v
@@ -0,0 +1,141 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [39:0] con1,con2, con3; + reg [31:0] w32; + reg [31:0] v32 [2]; + + // surefire lint_off UDDSCN + reg [200:0] conw3, conw4; + // surefire lint_on UDDSCN + + reg [16*8-1:0] con__ascii; + + reg [31:0] win; + // Test casting is proper on narrow->wide->narrow conversions + // verilator lint_off WIDTH + wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111; + wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111; + // verilator lint_on WIDTH + wire [31:0] narrow = wider[31:0]; + wire [31:0] narrow2 = wider2[31:0]; + + // surefire lint_off ASWEMB + // surefire lint_off ASWCMB + // surefire lint_off CWECBB + // surefire lint_off CWECSB + + // surefire lint_off STMINI + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + $write("[%0t] t_const: Running\n",$time); + + con1 = 4_0'h1000_0010; // Odd but legal _ in width + con2 = 40'h10_0000_0010; + con3 = con1 + 40'h10_1100_0101; + if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop; + $display("%x %x %x\n", con2, con2[31:0], con2[39:32]); + if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop; + if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; + + // verilator lint_off WIDTH + con1 = 10'h10 + 40'h80_1100_0131; + // verilator lint_on WIDTH + con2 = 40'h80_0000_0000 + 40'h13_7543_0107; + if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop; + if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop; + + // verilator lint_off WIDTH + conw3 = 94'h000a_5010_4020_3030_2040_1050; + // verilator lint_on WIDTH + if (conw3[31:00]!== 32'h2040_1050 || + conw3[63:32]!== 32'h4020_3030 || + conw3[95:64]!== 32'h000a_5010 || + conw3[128:96]!==33'h0) $stop; + $display("%x... %x\n", conw3[15:0], ~| conw3[15:0]); + if ((~| conw3[15:0]) !== 1'h0) $stop; + if ((~& conw3[15:0]) !== 1'h1) $stop; + + // verilator lint_off WIDTH + conw4 = 112'h7010_602a_5030_4040_3050_2060_1070; + // verilator lint_on WIDTH + if (conw4[31:00]!== 32'h2060_1070 || + conw4[63:32]!== 32'h4040_3050 || + conw4[95:64]!== 32'h602a_5030 || + conw4[127:96]!==32'h7010) $stop; + // conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070; + + w32 = 12; + win <= 12; + if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop; + + con__ascii = "abcdefghijklmnop"; + if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop; + con__ascii = "abcdefghijklm"; + if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop; + + if ( 3'dx !== 3'hx) $stop; + + // Wide decimal + if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop; + if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop; + + // Increments + w32 = 12; w32++; if (w32 != 13) $stop; + w32 = 12; ++w32; if (w32 != 13) $stop; + w32 = 12; w32--; if (w32 != 11) $stop; + w32 = 12; --w32; if (w32 != 11) $stop; + w32 = 12; w32 += 2; if (w32 != 14) $stop; + w32 = 12; w32 -= 2; if (w32 != 10) $stop; + w32 = 12; w32 *= 2; if (w32 != 24) $stop; + w32 = 12; w32 /= 2; if (w32 != 6) $stop; + w32 = 12; w32 &= 6; if (w32 != 4) $stop; + w32 = 12; w32 |= 15; if (w32 != 15) $stop; + w32 = 12; w32 ^= 15; if (w32 != 3) $stop; + w32 = 12; w32 >>= 1; if (w32 != 6) $stop; + w32 = 12; w32 <<= 1; if (w32 != 24) $stop; + + // Increments + v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop; + v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop; + v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop; + v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop; + v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop; + v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop; + v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop; + v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop; + v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop; + v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop; + v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop; + v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop; + v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop; + end + if (cyc==2) begin + win <= 32'h123123; + if (narrow !== 32'hfffffefb) $stop; + if (narrow2 !== 32'hffffff9d) $stop; + end + if (cyc==3) begin + if (narrow !== 32'h00123012) $stop; + if (narrow2 !== 32'h001230b4) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_div.v b/SVIncCompil/Testcases/Verilator/t_math_div.v new file mode 100644 index 0000000..46d0541 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_div.v
@@ -0,0 +1,96 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [255:0] a; + reg [60:0] divisor; + reg [60:0] qq; + reg [60:0] rq; + reg signed [60:0] qqs; + reg signed [60:0] rqs; + + always @* begin + qq = a[60:0] / divisor; + rq = a[60:0] % divisor; + qqs = $signed(a[60:0]) / $signed(divisor); + rqs = $signed(a[60:0]) % $signed(divisor); + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs); + if (cyc==1) begin + a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; + divisor <= 61'h12371; + a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned + end + if (cyc==2) begin + a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + divisor <= 61'h1238123771; + a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned + if (qq!==61'h00000403ad81c0da) $stop; + if (rq!==61'h00000000000090ec) $stop; + if (qqs!==61'h00000403ad81c0da) $stop; + if (rqs!==61'h00000000000090ec) $stop; + end + if (cyc==3) begin + a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8; + divisor <= 61'hf1b; + a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed + if (qq!==61'h000000000090832e) $stop; + if (rq!==61'h0000000334becc6a) $stop; + if (qqs!==61'h000000000090832e) $stop; + if (rqs!==61'h0000000334becc6a) $stop; + end + if (cyc==4) begin + a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed + if (qq!==61'h0001eda37cca1be8) $stop; + if (rq!==61'h0000000000000c40) $stop; + if (qqs!==61'h1fffcf5187c76510) $stop; + if (rqs!==61'h1ffffffffffffd08) $stop; + end + if (cyc==5) begin + a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed + if (qq!==61'h0000000000000000) $stop; + if (rq!==61'h0d20a48e00f395b8) $stop; + if (qqs!==61'h0000000000000000) $stop; + if (rqs!==61'h0d20a48e00f395b8) $stop; + end + if (cyc==6) begin + if (qq!==61'h0000000000000001) $stop; + if (rq!==61'h0d20a48e00f3869d) $stop; + if (qqs!==61'h0000000000000000) $stop; + if (rqs!==61'h1d20a48e00f395b8) $stop; + end + // Div by zero + if (cyc==9) begin + divisor <= 61'd0; + end + if (cyc==10) begin +`ifdef verilator + if (qq !== {61{1'b0}}) $stop; + if (rq !== {61{1'b0}}) $stop; +`else + if (qq !== {61{1'bx}}) $stop; + if (rq !== {61{1'bx}}) $stop; +`endif + if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors + if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors + end + if (cyc==19) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_div0.v b/SVIncCompil/Testcases/Verilator/t_math_div0.v new file mode 100644 index 0000000..2d6fb09 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_div0.v
@@ -0,0 +1,11 @@ +module t(y); + output [3:0] y; + // bug775 + // verilator lint_off WIDTH + assign y = ((0/0) ? 1 : 2) % 0; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_divw.v b/SVIncCompil/Testcases/Verilator/t_math_divw.v new file mode 100644 index 0000000..f8c5d89 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_divw.v
@@ -0,0 +1,145 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off WIDTH + + //============================================================ + + reg bad; + initial begin + bad=0; + c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888); + c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888); + c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0); + + c96(96'h0003, 96'h0002, 96'h0001, 96'h0001); + c96(96'h0003, 96'h0003, 96'h0001, 96'h0000); + c96(96'h0003, 96'h0004, 96'h0000, 96'h0003); + c96(96'h0000, 96'hffff, 96'h0000, 96'h0000); + c96(96'hffff, 96'h0001, 96'hffff, 96'h0000); + c96(96'hffff, 96'hffff, 96'h0001, 96'h0000); + c96(96'hffff, 96'h0003, 96'h5555, 96'h0000); + c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000); + c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000); + c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe); + c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70); + c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000); + c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000); + c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005); + c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000); + c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001); + c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000); + c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001); + c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899); + c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000); + c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff); + c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab); + c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff); + c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000); + + c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000); + c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000); + c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000); + + c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000); + c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000); + c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000); + c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000); + c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000); + c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); + c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000); + c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000); + c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002); + c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff); + c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888); + + if (bad) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + + task c96; + input [95:0] u; + input [95:0] v; + input [95:0] expq; + input [95:0] expr; + c96u( u, v, expq, expr); + c96s( u, v, expq, expr); + c96s(-u, v,-expq,-expr); + c96s( u,-v,-expq, expr); + c96s(-u,-v, expq,-expr); + endtask + + task c96u; + input [95:0] u; + input [95:0] v; + input [95:0] expq; + input [95:0] expr; + reg [95:0] gotq; + reg [95:0] gotr; + gotq = u/v; + gotr = u%v; + if (gotq != expq && v!=0) begin + bad = 1; + end + if (gotr != expr && v!=0) begin + bad = 1; + end + if (bad +`ifdef TEST_VERBOSE + || 1 +`endif + ) begin + $write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); + // Test for v=0 to prevent Xs causing grief + if (gotq != expq && v!=0) $write(" BADQ"); + if (gotr != expr && v!=0) $write(" BADR"); + $write("\n"); + end + endtask + + task c96s; + input signed [95:0] u; + input signed [95:0] v; + input signed [95:0] expq; + input signed [95:0] expr; + reg signed [95:0] gotq; + reg signed [95:0] gotr; + gotq = u/v; + gotr = u%v; + if (gotq != expq && v!=0) begin + bad = 1; + end + if (gotr != expr && v!=0) begin + bad = 1; + end + if (bad +`ifdef TEST_VERBOSE + || 1 +`endif + ) begin + $write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); + // Test for v=0 to prevent Xs causing grief + if (gotq != expq && v!=0) $write(" BADQ"); + if (gotr != expr && v!=0) $write(" BADR"); + $write("\n"); + end + endtask + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_eq.v b/SVIncCompil/Testcases/Verilator/t_math_eq.v new file mode 100644 index 0000000..dad6aea --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_eq.v
@@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h1a0d07009b6a30d2 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + output [3:0] out; + + assign out[0] = in[3:0] ==? 4'b1001; + assign out[1] = in[3:0] !=? 4'b1001; + assign out[2] = in[3:0] ==? 4'bx01x; + assign out[3] = in[3:0] !=? 4'bx01x; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_equal.v b/SVIncCompil/Testcases/Verilator/t_math_equal.v new file mode 100644 index 0000000..437bd0f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_equal.v
@@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer _mode; + + reg _guard1; + reg [127:0] r_wide0; + reg _guard2; + wire [63:0] r_wide1; + reg _guard3; + reg _guard4; + reg _guard5; + reg _guard6; + + assign r_wide1 = r_wide0[127:64]; + + // surefire lint_off STMINI + initial _mode = 0; + + always @ (posedge clk) begin + if (_mode==0) begin + $write("[%0t] t_equal: Running\n", $time); + _guard1 <= 0; + _guard2 <= 0; + _guard3 <= 0; + _guard4 <= 0; + _guard5 <= 0; + _guard6 <= 0; + + _mode<=1; + r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; + end + else if (_mode==1) begin + _mode<=2; + // + if (5'd10 != 5'b1010) $stop; + if (5'd10 != 5'd10) $stop; + if (5'd10 != 5'ha) $stop; + if (5'd10 != 5'o12) $stop; + if (5'd10 != 5'B 1010) $stop; + if (5'd10 != 5'D10) $stop; + if (5'd10 != 5'H a) $stop; + if (5'd10 != 5 'O 12) $stop; + // + if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; + if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; + if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin + $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_imm.v b/SVIncCompil/Testcases/Verilator/t_math_imm.v new file mode 100644 index 0000000..709fcae --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_imm.v
@@ -0,0 +1,113 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. +// +// Example module to create problem. +// +// generate a 64 bit value with bits +// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 +// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 +// all other bits zero. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [7:0] crc; + reg [63:0] sum; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] HighLogicImm; // From example of example.v + wire [63:0] LogicImm; // From example of example.v + wire [63:0] LowLogicImm; // From example of example.v + // End of automatics + + wire [5:0] LowMaskSel_Top = crc[5:0]; + wire [5:0] LowMaskSel_Bot = crc[5:0]; + wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]}; + wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]}; + + example example (/*AUTOINST*/ + // Outputs + .LogicImm (LogicImm[63:0]), + .LowLogicImm (LowLogicImm[63:0]), + .HighLogicImm (HighLogicImm[63:0]), + // Inputs + .LowMaskSel_Top (LowMaskSel_Top[5:0]), + .HighMaskSel_Top (HighMaskSel_Top[5:0]), + .LowMaskSel_Bot (LowMaskSel_Bot[5:0]), + .HighMaskSel_Bot (HighMaskSel_Bot[5:0])); + + always @ (posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc, + LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, + LowLogicImm, HighLogicImm, LogicImm); +`endif + if (cyc==0) begin + // Single case + crc <= 8'h0; + sum <= 64'h0; + end + else if (cyc==1) begin + // Setup + crc <= 8'hed; + sum <= 64'h0; + end + else if (cyc<90) begin + sum <= {sum[62:0],sum[63]} ^ LogicImm; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum); + if (crc !== 8'b00111000) $stop; + if (sum !== 64'h58743ffa61e41075) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module example (/*AUTOARG*/ + // Outputs + LogicImm, LowLogicImm, HighLogicImm, + // Inputs + LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot + ); + + input [5:0] LowMaskSel_Top, HighMaskSel_Top; + input [5:0] LowMaskSel_Bot, HighMaskSel_Bot; + output [63:0] LogicImm; + + output [63:0] LowLogicImm, HighLogicImm; + + + wire [63:0] LowLogicImm, HighLogicImm; + + /* verilator lint_off UNSIGNED */ + /* verilator lint_off CMPCONST */ + genvar i; + generate + for (i=0;i<64;i=i+1) begin : MaskVal + if (i >= 32) begin + assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]); + assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]); + end + else begin + assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]); + assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]); + end + end + endgenerate + /* verilator lint_on UNSIGNED */ + /* verilator lint_on CMPCONST */ + + assign LogicImm = LowLogicImm & HighLogicImm; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_imm2.v b/SVIncCompil/Testcases/Verilator/t_math_imm2.v new file mode 100644 index 0000000..a14b9d8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_imm2.v
@@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. +// +// Example module to create problem. +// +// generate a 64 bit value with bits +// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 +// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 +// all other bits zero. + +module t_math_imm2 (/*AUTOARG*/ + // Outputs + LogicImm, LowLogicImm, HighLogicImm, + // Inputs + LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot + ); + input [4:0] LowMaskSel_Top, HighMaskSel_Top; + input [4:0] LowMaskSel_Bot, HighMaskSel_Bot; + output [63:0] LogicImm; + + output [63:0] LowLogicImm, HighLogicImm; + + /* verilator lint_off UNSIGNED */ + /* verilator lint_off CMPCONST */ + genvar i; + generate + for (i=0;i<64;i=i+1) begin : MaskVal + if (i >= 32) begin + assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]); + assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]); + end + else begin + assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]); + assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]); + end + end + endgenerate + + assign LogicImm = LowLogicImm & HighLogicImm; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_msvc_64.v b/SVIncCompil/Testcases/Verilator/t_math_msvc_64.v new file mode 100644 index 0000000..e5052f4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_msvc_64.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + reg [89:0] in; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [89:0] out; // From test of Test.v + wire [44:0] line0; + wire [44:0] line1; + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[89:0]), + .line0 (line0[44:0]), + .line1 (line1[44:0]), + // Inputs + .clk (clk), + .in (in[89:0])); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out); +`endif + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; + end + else if (cyc==10) begin + if (in==out) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("*-* Failed!! *-*\n"); + $finish; + end + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + line0, line1, out, + // Inputs + clk, in + ); + + input clk; + input [89:0] in; + + output reg [44:0] line0; + output reg [44:0] line1; + output reg [89:0] out; + + assign {line0,line1} = in; + always @(posedge clk) begin + out <= {line0,line1}; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_mul.v b/SVIncCompil/Testcases/Verilator/t_math_mul.v new file mode 100644 index 0000000..5f987ec --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_mul.v
@@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [31:0] out1; + wire [31:0] out2; + sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1}; + if (cyc==1) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc==90) begin + if (sum !== 64'he396068aba3898a2) $stop; + end + else if (cyc==91) begin + end + else if (cyc==92) begin + end + else if (cyc==93) begin + end + else if (cyc==94) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + out1, out2, + // Inputs + in1, in2 + ); + + input [15:0] in1; + input [15:0] in2; + output reg signed [31:0] out1; + output reg unsigned [31:0] out2; + + always @* begin + // verilator lint_off WIDTH + out1 = $signed(in1) * $signed(in2); + out2 = $unsigned(in1) * $unsigned(in2); + // verilator lint_on WIDTH + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_pick.v b/SVIncCompil/Testcases/Verilator/t_math_pick.v new file mode 100644 index 0000000..1e865f8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_pick.v
@@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire pick1 = crc[0]; + wire [13:0][1:0] data1 = crc[27+1:1]; + wire [3:0][2:0][1:0] data2 = crc[23+29:29]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [15:0] [1:0] datao; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .datao (datao/*[15:0][1:0]*/), + // Inputs + .pick1 (pick1), + .data1 (data1/*[13:0][1:0]*/), + .data2 (data2/*[2:0][3:0][1:0]*/)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, datao}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h3ff4bf0e6407b281 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( + input logic pick1, + input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits + input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits + output logic [15:0] [1:0] datao // 16 x 2 = 32 bits + ); + // verilator lint_off WIDTH + always_comb datao[13: 0] // 28 bits + = (pick1) + ? {data1} // 28 bits + : {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized + // verilator lint_on WIDTH + always_comb datao[15:14] = '0; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_pow.v b/SVIncCompil/Testcases/Verilator/t_math_pow.v new file mode 100644 index 0000000..285d0b6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_pow.v
@@ -0,0 +1,104 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +`ifdef VERILATOR + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) +`else + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [60:0] p; + reg [60:0] a; + reg [20:0] b; + reg [60:0] shifted; + + always @* begin + p = a[60:0] ** b[20:0]; + shifted = 2 ** b[20:0]; + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%0x %x %x\n", cyc, p, shifted); +`endif + // Constant versions + `checkh(61'h1 ** 21'h31, 61'h1); + `checkh(61'h2 ** 21'h10, 61'h10000); + `checkh(61'd10 ** 21'h3, 61'h3e8); + `checkh(61'h3 ** 21'h7, 61'h88b); +`ifndef VCS + `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); +`endif + if (cyc==1) begin + a <= 61'h0; + b <= 21'h0; + end + if (cyc==2) begin + a <= 61'h0; + b <= 21'h3; + end + if (cyc==3) begin + a <= 61'h1; + b <= 21'h31; + end + if (cyc==4) begin + a <= 61'h2; + b <= 21'h10; + end + if (cyc==5) begin + a <= 61'd10; + b <= 21'd3; + end + if (cyc==6) begin + a <= 61'd3; + b <= 21'd7; + end + if (cyc==7) begin + a <= 61'h7ab3811219; + b <= 21'ha6e30; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + case (cyc) + 32'd00: ; + 32'd01: ; + 32'd02: ; // 0^x is indeterminate + 32'd03: ; // 0^x is indeterminate + 32'd04: `checkh(p, 61'h1); + 32'd05: `checkh(p, 61'h10000); + 32'd06: `checkh(p, 61'h3e8); + 32'd07: `checkh(p, 61'h88b); + 32'd08: `checkh(p, 61'h01ea58c703687e81); + 32'd09: `checkh(p, 61'h01ea58c703687e81); + default: $stop; + endcase + case (cyc) + 32'd00: ; + 32'd01: ; + 32'd02: `checkh(shifted, 61'h0000000000000001); + 32'd03: `checkh(shifted, 61'h0000000000000008); + 32'd04: `checkh(shifted, 61'h0002000000000000); + 32'd05: `checkh(shifted, 61'h0000000000010000); + 32'd06: `checkh(shifted, 61'h0000000000000008); + 32'd07: `checkh(shifted, 61'h0000000000000080); + 32'd08: `checkh(shifted, 61'h0000000000000000); + 32'd09: `checkh(shifted, 61'h0000000000000000); + default: $stop; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_pow2.v b/SVIncCompil/Testcases/Verilator/t_math_pow2.v new file mode 100644 index 0000000..e15c5b6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_pow2.v
@@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Aggregate outputs into a single result vector + //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows + wire [3:0] pow4b = crc[7:4]**crc[3:0]; + wire [63:0] result = {60'h0, pow4b}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h1fec4b2b71cf8024 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_pow3.v b/SVIncCompil/Testcases/Verilator/t_math_pow3.v new file mode 100644 index 0000000..be35aa2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_pow3.v
@@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0) + +module t (/*AUTOARG*/); + + bit fail; + + // IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below. + + initial begin + // NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21 + $display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110); + // NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed) + $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2))); + // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 + $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2))); + // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 + $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14))); + // NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321 + $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321); + $display("\n"); + + `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); + `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 + `checkh( (-4'd1 ** -4'd2), 4'h1); + `checkh( (4'd15 ** 4'd14), 4'h1); + `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321); + + `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27) + `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1 + `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 + `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27) + `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27) + `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216) + `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216) + + `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b + `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 + `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 + `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) + `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) + `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) + `checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216) + + `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + + `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + + `checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug + `checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1 +// `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug + `checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1 + `checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug + `checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug + + + if (fail) $stop; + else $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_pow4.v b/SVIncCompil/Testcases/Verilator/t_math_pow4.v new file mode 100644 index 0000000..392eb3f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_pow4.v
@@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Clifford Wolf. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + wire [31:0] y; + reg a; + test004 sub (/*AUTOINST*/ + // Outputs + .y (y[31:0]), + // Inputs + .a (a)); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d a=%x y=%x\n",$time, cyc, a, y); +`endif + cyc <= cyc + 1; + if (cyc==0) begin + a <= 0; + end + else if (cyc==1) begin + a <= 1; + if (y != 32'h0) $stop; + end + else if (cyc==2) begin + if (y != 32'h010000ff) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module test004(a, y); + input a; + output [31:0] y; + + wire [7:0] y0; + wire [7:0] y1; + wire [7:0] y2; + wire [7:0] y3; + assign y = {y0,y1,y2,y3}; + + localparam [7:0] v0 = +8'sd1 ** -8'sd2; //'h01 + localparam [7:0] v1 = +8'sd2 ** -8'sd2; //'h00 + localparam [7:0] v2 = -8'sd2 ** -8'sd3; //'h00 + localparam [7:0] v3 = -8'sd1 ** -8'sd3; //'hff + localparam [7:0] zero = 0; + + initial $display("v0=%x v1=%x v2=%x v3=%x", v0,v1,v2,v3); + + assign y0 = a ? v0 : zero; + assign y1 = a ? v1 : zero; + assign y2 = a ? v2 : zero; + assign y3 = a ? v3 : zero; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_pow5.v b/SVIncCompil/Testcases/Verilator/t_math_pow5.v new file mode 100644 index 0000000..1224836 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_pow5.v
@@ -0,0 +1,73 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [67:0] q; + reg signed [67:0] qs; + + initial begin + q = 68'he_12345678_9abcdef0 ** 68'h3; + if (q != 68'hcee3cb96ce96cf000) $stop; + // + q = 68'he_12345678_9abcdef0 ** 68'h5_6789abcd_ef012345; + if (q != 68'h0) $stop; + // + qs = 68'she_12345678_9abcdef0 ** 68'sh3; + if (qs != 68'shcee3cb96ce96cf000) $stop; + // + qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345; + if (qs != 68'h0) $stop; + end + + reg [67:0] left; + reg [67:0] right; + + wire [67:0] outu = left ** right; + wire signed [67:0] outs = $signed(left) ** $signed(right); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%d %x %x %x %x\n", cyc, left, right, outu, outs); +`endif + if (cyc==1) begin + left <= 68'h1; + right <= '0; + end + if (cyc==2) begin + if (outu != 68'h1) $stop; + if (outs != 68'h1) $stop; + end + if (cyc==3) begin + left <= 68'he_12345678_9abcdef0; + right <= 68'h3; + end + if (cyc==4) begin + if (outu != 68'hcee3cb96ce96cf000) $stop; + if (outs != 68'hcee3cb96ce96cf000) $stop; + end + if (cyc==5) begin + left <= 68'he_12345678_9abcdef0; + right <= 68'h5_6789abcd_ef012345; + end + if (cyc==6) begin + if (outu != 68'h0) $stop; + if (outs != 68'h0) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_pow6.v b/SVIncCompil/Testcases/Verilator/t_math_pow6.v new file mode 100644 index 0000000..b3c8852 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_pow6.v
@@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33, + x33, w30, x30, + // Inputs + a, a40, a70 + ); + + input [3:0] a; + input [39:0] a40; + input [69:0] a70; + + // -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI() + // verilator lint_off WIDTH + output [3:0] i65 = 65'd3 ** a; // WWI + output [3:0] j65 = a ** 65'd3; // IIW + output [3:0] i33 = 33'd3 ** a; // QQI + output [3:0] j33 = a ** 33'd3; // IIQ + output [3:0] i30 = 30'd3 ** a; // III + output [3:0] j30 = a ** 30'd3; // III + + output [39:0] q65 = 65'd3 ** a40; // WWQ + output [39:0] r65 = a40 ** 65'd3; // WWQ + output [39:0] q33 = 33'd3 ** a40; // QQQ + output [39:0] r33 = a40 ** 33'd3; // QQQ + output [39:0] q30 = 30'd3 ** a40; // QQI + output [39:0] r30 = a40 ** 30'd3; // QQI + + output [69:0] w65 = 65'd3 ** a70; // WWW + output [69:0] x65 = a70 ** 65'd3; // WWW + output [69:0] w33 = 33'd3 ** a70; // WWW + output [69:0] x33 = a70 ** 33'd3; // WWW + output [69:0] w30 = 30'd3 ** a70; // WWW + output [69:0] x30 = a70 ** 30'd3; // WWW + // verilator lint_on WIDTH + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_precedence.v b/SVIncCompil/Testcases/Verilator/t_math_precedence.v new file mode 100644 index 0000000..b22042c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_precedence.v
@@ -0,0 +1,161 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [1:0] a = crc[1 +: 2]; + wire [1:0] b = crc[3 +: 2]; + wire [1:0] c = crc[5 +: 2]; + wire [1:0] d = crc[7 +: 2]; + wire [1:0] e = crc[9 +: 2]; + wire [1:0] f = crc[11+: 2]; + wire [1:0] g = crc[13+: 2]; + + // left () [] :: . + // unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary) + // left ** + // left * / % + // left + - (binary) + // left << >> <<< >>> + // left < <= > >= inside dist + // left == != === !== ==? !=? + // left & (binary) + // left ^ ~^ ^~ (binary) + // left | (binary) + // left && + // left || + // left ? : + // right -> + // none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <= + // {} {{}} concatenation + + wire [1:0] bnz = (b==2'b0) ? 2'b11 : b; + wire [1:0] cnz = (c==2'b0) ? 2'b11 : c; + wire [1:0] dnz = (d==2'b0) ? 2'b11 : d; + wire [1:0] enz = (e==2'b0) ? 2'b11 : e; + + // verilator lint_off WIDTH + // Do a few in each group + wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse + wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse + wire [1:0] o3 = a ** b ** c; // Some simulators botch this + + wire [1:0] o4 = a * b / cnz % dnz * enz; + wire [1:0] o5 = a + b - c + d; + wire [1:0] o6 = a << b >> c <<< d >>> e <<< f; + wire [1:0] o7 = a < b <= c; + wire [1:0] o8 = a == b != c === d == e; + wire [1:0] o9 = a & b & c; + wire [1:0] o10 = a ^ b ~^ c ^~ d ^ a; + wire [1:0] o11 = a | b | c; + wire [1:0] o12 = a && b && c; + wire [1:0] o13 = a || b || c; + wire [1:0] o14 = a ? b ? c : d : e; + wire [1:0] o15 = a ? b : c ? d : e; + + // Now cross each pair of groups + wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this + wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this + wire [1:0] x3 = a + b * c + d; + wire [1:0] x4 = a + b << c + d; + wire [1:0] x5 = a == b << c == d; + wire [1:0] x6 = a & b << c & d; + wire [1:0] x7 = a ^ b & c ^ d; + wire [1:0] x8 = a | b ^ c | d; + wire [1:0] x9 = a && b | c && d; + wire [1:0] x10 = a || b && c || d; + wire [1:0] x11 = a ? b || c : d ? e : f; + + // verilator lint_on WIDTH + + function [1:0] pow (input [1:0] x, input [1:0] y); + casez ({x,y}) + 4'b00_??: pow = 2'b00; + 4'b01_00: pow = 2'b01; + 4'b01_01: pow = 2'b01; + 4'b01_10: pow = 2'b01; + 4'b01_11: pow = 2'b01; + 4'b10_00: pow = 2'b01; + 4'b10_01: pow = 2'b10; + 4'b10_10: pow = 2'b00; + 4'b10_11: pow = 2'b00; + 4'b11_00: pow = 2'b01; + 4'b11_01: pow = 2'b11; + 4'b11_10: pow = 2'b01; + 4'b11_11: pow = 2'b11; + endcase + endfunction + + // Aggregate outputs into a single result vector + wire [63:0] result = {12'h0, + x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1, + o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x ",$time, cyc, crc, result); + $write(" %b",o1); + $write(" %b",o2); + $write(" %b",o3); + $write(" %b",o4); + $write(" %b",o5); + $write(" %b",o6); + $write(" %b",o7); + $write(" %b",o8); + $write(" %b",o9); + $write(" %b",o10); + $write(" %b",o11); + $write(" %b",o12); + $write(" %b",o13); + $write(" %b",o14); + $write(" %b",o15); + // Now cross each pair of groups + $write(" %b",x1); + $write(" %b",x2); + $write(" %b",x3); + $write(" %b",x4); + $write(" %b",x5); + $write(" %b",x6); + $write(" %b",x7); + $write(" %b",x8); + $write(" %b",x9); + $write(" %b",x10); + $write(" %b",x11); + $write("\n"); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h2756ea365ec7520e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_real.v b/SVIncCompil/Testcases/Verilator/t_math_real.v new file mode 100644 index 0000000..a376b77 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_real.v
@@ -0,0 +1,151 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer i; + reg [63:0] b; + real r, r2; + integer cyc=0; + + realtime uninit; + initial if (uninit != 0.0) $stop; + + sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*); + + initial begin + if (1_00_0.0_1 != 1000.01) $stop; + // rtoi truncates + if ($rtoi(36.7) != 36) $stop; + if ($rtoi(36.5) != 36) $stop; + if ($rtoi(36.4) != 36) $stop; + // casting rounds + if ((integer '(36.7)) != 37) $stop; + if ((integer '(36.5)) != 37) $stop; + if ((integer '(36.4)) != 36) $stop; + // assignment rounds + // verilator lint_off REALCVT + i = 36.7; if (i != 37) $stop; + i = 36.5; if (i != 37) $stop; + i = 36.4; if (i != 36) $stop; + r = 10'd38; if (r!=38.0) $stop; + // verilator lint_on REALCVT + // operators + if ((-(1.5)) != -1.5) $stop; + if ((+(1.5)) != 1.5) $stop; + if (((1.5)+(1.25)) != 2.75) $stop; + if (((1.5)-(1.25)) != 0.25) $stop; + if (((1.5)*(1.25)) != 1.875) $stop; + if (((1.5)/(1.25)) != 1.2) $stop; + // + if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0 + if (((1.5)!=(2)) != 1'b1) $stop; + if (((1.5)> (2)) != 1'b0) $stop; + if (((1.5)>=(2)) != 1'b0) $stop; + if (((1.5)< (2)) != 1'b1) $stop; + if (((1.5)<=(2)) != 1'b1) $stop; + if (((1.5)==(1.5)) != 1'b1) $stop; + if (((1.5)!=(1.5)) != 1'b0) $stop; + if (((1.5)> (1.5)) != 1'b0) $stop; + if (((1.5)>=(1.5)) != 1'b1) $stop; + if (((1.5)< (1.5)) != 1'b0) $stop; + if (((1.5)<=(1.5)) != 1'b1) $stop; + if (((1.6)==(1.5)) != 1'b0) $stop; + if (((1.6)!=(1.5)) != 1'b1) $stop; + if (((1.6)> (1.5)) != 1'b1) $stop; + if (((1.6)>=(1.5)) != 1'b1) $stop; + if (((1.6)< (1.5)) != 1'b0) $stop; + if (((1.6)<=(1.5)) != 1'b0) $stop; + // + if (((0.0)?(2.0):(1.1)) != 1.1) $stop; + if (((1.5)?(2.0):(1.1)) != 2.0) $stop; + // + if (!1.7) $stop; + if (!(!0.0)) $stop; + if (1.8 && 0.0) $stop; + if (!(1.8 || 0.0)) $stop; + // + i=0; + for (r=1.0; r<2.0; r=r+0.1) i++; + if (i!=10) $stop; + // bug + r = $bitstoreal($realtobits(1.414)); + if (r != 1.414) $stop; + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + end + else if (cyc<90) begin + if ($time != {32'h0, $rtoi($realtime)}) $stop; + if ($itor(cyc) != cyc) $stop; + //Unsup: if ((real `($time)) != $realtime) $stop; + r = $itor(cyc*2); + i = $rtoi(r); + if (i!=cyc*2) $stop; + // + r = $itor(cyc)/1.5; + b = $realtobits(r); + r2 = $bitstoreal(b); + if (r != r2) $stop; + // + // Trust the integer math as a comparison + r = $itor(cyc); + if ($rtoi(-r) != -cyc) $stop; + if ($rtoi(+r) != cyc) $stop; + if ($rtoi(r+2.0) != (cyc+2)) $stop; + if ($rtoi(r-2.0) != (cyc-2)) $stop; + if ($rtoi(r*2.0) != (cyc*2)) $stop; + if ($rtoi(r/2.0) != (cyc/2)) $stop; + r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash + // + r2 = $itor(cyc); + case (r) + (r2-1.0): $stop; + r2: ; + default: $stop; + endcase + // + r = $itor(cyc); + if ((r==50.0) != (cyc==50)) $stop; + if ((r!=50.0) != (cyc!=50)) $stop; + if ((r> 50.0) != (cyc> 50)) $stop; + if ((r>=50.0) != (cyc>=50)) $stop; + if ((r< 50.0) != (cyc< 50)) $stop; + if ((r<=50.0) != (cyc<=50)) $stop; + // + if ($rtoi((r-50.0) ? 10.0 : 20.0) + != (((cyc-50)!=0) ? 10 : 20)) $stop; + // + if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub_cast_bug374(input clk, input [4:0] cyc5); + integer i; + + always @(posedge clk) begin + i <= integer'(cyc5); + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_real_public.v b/SVIncCompil/Testcases/Verilator/t_math_real_public.v new file mode 100644 index 0000000..4ddb203 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_real_public.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Alex Solomatnikov + +module t; + sub #(.REAL(2.0)) sub; +endmodule + +module sub (); + timeunit 1ns; + timeprecision 1ps; + + parameter REAL = 0.0; + + initial begin + $display("REAL %g", REAL); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_repl.v b/SVIncCompil/Testcases/Verilator/t_math_repl.v new file mode 100644 index 0000000..b93d647 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_repl.v
@@ -0,0 +1,109 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [63:0] rf; + reg [63:0] rf2; + reg [63:0] biu; + reg b; + + always @* begin + rf[63:32] = biu[63:32] & {32{b}}; + rf[31:0] = {32{b}}; + rf2 = rf; + rf2[31:0] = ~{32{b}}; + end + + reg [31:0] src1, src0, sr, mask; + wire [31:0] dualasr + = ((| src1[31:4]) + ? {{16{src0[31]}}, {16{src0[15]}}} + : ( ( sr & {2{mask[31:16]}}) + | ( {{16{src0[31]}}, {16{src0[15]}}} + & {2{~mask[31:16]}}))); + + wire [31:0] sl_mask + = (32'hffffffff << src1[4:0]); + + wire [31:0] sr_mask + = {sl_mask[0], sl_mask[1], + sl_mask[2], sl_mask[3], sl_mask[4], + sl_mask[5], sl_mask[6], sl_mask[7], + sl_mask[8], sl_mask[9], + sl_mask[10], sl_mask[11], + sl_mask[12], sl_mask[13], sl_mask[14], + sl_mask[15], sl_mask[16], + sl_mask[17], sl_mask[18], sl_mask[19], + sl_mask[20], sl_mask[21], + sl_mask[22], sl_mask[23], sl_mask[24], + sl_mask[25], sl_mask[26], + sl_mask[27], sl_mask[28], sl_mask[29], + sl_mask[30], sl_mask[31]}; + + wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; + wire [1:0] w = {2{b}}; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("cyc=%0d d=%x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask); +`endif + if (cyc==1) begin + biu <= 64'h12451282_abadee00; + b <= 1'b0; + src1 <= 32'h00000001; + src0 <= 32'h9a4f1235; + sr <= 32'h0f19f567; + mask <= 32'h7af07ab4; + end + if (cyc==2) begin + biu <= 64'h12453382_abad8801; + b <= 1'b1; + if (rf != 64'h0) $stop; + if (rf2 != 64'h00000000ffffffff) $stop; + src1 <= 32'h0010000f; + src0 <= 32'h028aa336; + sr <= 32'h42ad0377; + mask <= 32'h1ab3b906; + if (dualasr != 32'h8f1f7060) $stop; + if (sl_mask != 32'hfffffffe) $stop; + if (sr_mask != 32'h7fffffff) $stop; + if (widerep != '0) $stop; + end + if (cyc==3) begin + biu <= 64'h12422382_77ad8802; + b <= 1'b1; + if (rf != 64'h12453382ffffffff) $stop; + if (rf2 != 64'h1245338200000000) $stop; + src1 <= 32'h0000000f; + src0 <= 32'h5c158f71; + sr <= 32'h7076c40a; + mask <= 32'h33eb3d44; + if (dualasr != 32'h0000ffff) $stop; + if (sl_mask != 32'hffff8000) $stop; + if (sr_mask != 32'h0001ffff) $stop; + if (widerep != '1) $stop; + end + if (cyc==4) begin + if (rf != 64'h12422382ffffffff) $stop; + if (rf2 != 64'h1242238200000000) $stop; + if (dualasr != 32'h3062cc1e) $stop; + if (sl_mask != 32'hffff8000) $stop; + if (sr_mask != 32'h0001ffff) $stop; + $write("*-* All Finished *-*\n"); + if (widerep != '1) $stop; + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_reverse.v b/SVIncCompil/Testcases/Verilator/t_math_reverse.v new file mode 100644 index 0000000..90bebd5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_reverse.v
@@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [7:0] crc; + + // Build up assignments + wire [7:0] bitrev; + assign bitrev[7] = crc[0]; + assign bitrev[6] = crc[1]; + assign bitrev[5] = crc[2]; + assign bitrev[4] = crc[3]; + assign bitrev[0] = crc[7]; + assign bitrev[1] = crc[6]; + assign bitrev[2] = crc[5]; + assign bitrev[3] = crc[4]; + + // Build up always assignments + reg [7:0] bitrevb; + always @ (/*AS*/crc) begin + bitrevb[7] = crc[0]; + bitrevb[6] = crc[1]; + bitrevb[5] = crc[2]; + bitrevb[4] = crc[3]; + bitrevb[0] = crc[7]; + bitrevb[1] = crc[6]; + bitrevb[2] = crc[5]; + bitrevb[3] = crc[4]; + end + + // Build up always assignments + reg [7:0] bitrevr; + always @ (posedge clk) begin + bitrevr[7] <= crc[0]; + bitrevr[6] <= crc[1]; + bitrevr[5] <= crc[2]; + bitrevr[4] <= crc[3]; + bitrevr[0] <= crc[7]; + bitrevr[1] <= crc[6]; + bitrevr[2] <= crc[5]; + bitrevr[3] <= crc[4]; + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + //$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev); + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==1) begin + crc <= 8'hed; + end + if (cyc==2 && bitrev!=8'hb7) $stop; + if (cyc==3 && bitrev!=8'h5b) $stop; + if (cyc==4 && bitrev!=8'h2d) $stop; + if (cyc==5 && bitrev!=8'h16) $stop; + if (cyc==6 && bitrev!=8'h8b) $stop; + if (cyc==7 && bitrev!=8'hc5) $stop; + if (cyc==8 && bitrev!=8'he2) $stop; + if (cyc==9 && bitrev!=8'hf1) $stop; + if (bitrevb != bitrev) $stop; + if (cyc==3 && bitrevr!=8'hb7) $stop; + if (cyc==4 && bitrevr!=8'h5b) $stop; + if (cyc==5 && bitrevr!=8'h2d) $stop; + if (cyc==6 && bitrevr!=8'h16) $stop; + if (cyc==7 && bitrevr!=8'h8b) $stop; + if (cyc==8 && bitrevr!=8'hc5) $stop; + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_shift.v b/SVIncCompil/Testcases/Verilator/t_math_shift.v new file mode 100644 index 0000000..12de701 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_shift.v
@@ -0,0 +1,124 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + ign, ign2, ign3, + // Inputs + clk + ); + + input clk; + output [31:0] ign; + output [3:0] ign2; + output [11:0] ign3; + + parameter [95:0] P6 = 6; + localparam P64 = (1 << P6); + + // verilator lint_off WIDTH + localparam [4:0] PBIG23 = 1'b1 << ~73'b0; + localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; + // verilator lint_on WIDTH + + reg [31:0] right; + reg [31:0] left; + reg [P64-1:0] qright; + reg [P64-1:0] qleft; + reg [31:0] amt; + + assign ign = {31'h0, clk} >>> 4'bx; // bug760 + assign ign2 = {amt[1:0] >> {22{amt[5:2]}}, amt[1:0] << (0 <<< amt[5:2])}; // bug1174 + assign ign3 = {amt[1:0] >> {22{amt[5:2]}}, + amt[1:0] >> {11{amt[5:2]}}, + $signed(amt[1:0]) >>> {22{amt[5:2]}}, + $signed(amt[1:0]) >>> {11{amt[5:2]}}, + amt[1:0] << {22{amt[5:2]}}, + amt[1:0] << {11{amt[5:2]}}}; + + + always @* begin + right = 32'h819b018a >> amt; + left = 32'h819b018a << amt; + qright = 64'hf784bf8f_12734089 >> amt; + qleft = 64'hf784bf8f_12734089 >> amt; + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%d %x %x %x %x\n", cyc, left, right, qleft, qright); +`endif + if (cyc==1) begin + amt <= 32'd0; + if (P64 != 64) $stop; + if (5'b10110>>2 != 5'b00101) $stop; + if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness + if (5'b10110<<2 != 5'b11000) $stop; + if (5'b10110<<<2 != 5'b11000) $stop; + if (5'sb10110>>2 != 5'sb00101) $stop; + if (5'sb10110>>>2 != 5'sb11101) $stop; + if (5'sb10110<<2 != 5'sb11000) $stop; + if (5'sb10110<<<2 != 5'sb11000) $stop; + // Allow >64 bit shifts if the shift amount is a constant + if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; + end + if (cyc==2) begin + amt <= 32'd28; + if (left != 32'h819b018a) $stop; + if (right != 32'h819b018a) $stop; + if (qleft != 64'hf784bf8f_12734089) $stop; + if (qright != 64'hf784bf8f_12734089) $stop; + end + if (cyc==3) begin + amt <= 32'd31; + if (left != 32'ha0000000) $stop; + if (right != 32'h8) $stop; + if (qleft != 64'h0000000f784bf8f1) $stop; + if (qright != 64'h0000000f784bf8f1) $stop; + end + if (cyc==4) begin + amt <= 32'd32; + if (left != 32'h0) $stop; + if (right != 32'h1) $stop; + if (qleft != 64'h00000001ef097f1e) $stop; + if (qright != 64'h00000001ef097f1e) $stop; + end + if (cyc==5) begin + amt <= 32'd33; + if (left != 32'h0) $stop; + if (right != 32'h0) $stop; + if (qleft != 64'h00000000f784bf8f) $stop; + if (qright != 64'h00000000f784bf8f) $stop; + end + if (cyc==6) begin + amt <= 32'd64; + if (left != 32'h0) $stop; + if (right != 32'h0) $stop; + if (qleft != 64'h000000007bc25fc7) $stop; + if (qright != 64'h000000007bc25fc7) $stop; + end + if (cyc==7) begin + amt <= 32'd128; + if (left != 32'h0) $stop; + if (right != 32'h0) $stop; + if (qleft != 64'h0) $stop; + if (qright != 64'h0) $stop; + end + if (cyc==8) begin + if (left != 32'h0) $stop; + if (right != 32'h0) $stop; + if (qleft != 64'h0) $stop; + if (qright != 64'h0) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_shift_over_bad.v b/SVIncCompil/Testcases/Verilator/t_math_shift_over_bad.v new file mode 100644 index 0000000..c700581 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_shift_over_bad.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + o, + // Inputs + clk, i + ); + + input clk; + + input [31:0] i; + output [31:0] o; + + assign o = i << 64'h01234567_89abcdef; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_shift_rep.v b/SVIncCompil/Testcases/Verilator/t_math_shift_rep.v new file mode 100644 index 0000000..cca83d1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_shift_rep.v
@@ -0,0 +1,77 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + //bug765; disappears if add this wire + //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values + wire [7:0] a = crc[7:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [15:0] y; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .y (y[15:0]), + // Inputs + .a (a[7:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, y}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + y, + // Inputs + a + ); + input signed [7:0] a; + output [15:0] y; + // verilator lint_off WIDTH + assign y = ~66'd0 <<< {4{a}}; + // verilator lint_on WIDTH +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_shift_sel.v b/SVIncCompil/Testcases/Verilator/t_math_shift_sel.v new file mode 100644 index 0000000..ecb3917 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_shift_sel.v
@@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [106:0] in = {~crc[42:0], crc[63:0]}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] out1; // From test of Test.v + wire [7:0] out2; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out1 (out1[7:0]), + .out2 (out2[7:0]), + // Inputs + .in (in[106:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, out1, out1}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hc746017202a24ecc + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out1, out2, + // Inputs + in + ); + + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. + + input [106:0] in; + output [7:0] out1, out2; + + // verilator lint_off WIDTH + // Better written as onibble[99 +: 8]. Verilator will convert it. + wire [7:0] out1 = (in >>> 99) & 255; + // verilator lint_on WIDTH + wire [7:0] out2 = in[106:99]; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_shiftrs.v b/SVIncCompil/Testcases/Verilator/t_math_shiftrs.v new file mode 100644 index 0000000..3248a94 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_shiftrs.v
@@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg signed [64+15:0] data; + integer i; + integer b; + reg signed [64+15:0] srs; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==2) begin + data <= 80'h0; + data[75] <= 1'b1; + data[10] <= 1'b1; + end + if (cyc==3) begin + for (i=0; i<85; i=i+1) begin + srs = data>>>i; + //$write (" %x >>> %d == %x\n",data,i,srs); + for (b=0; b<80; b=b+1) begin + if (srs[b] != (b==(75-i) || b==(10-i))) $stop; + end + end + end + if (cyc==10) begin + data <= 80'h0; + data[79] <= 1'b1; + data[10] <= 1'b1; + end + if (cyc==12) begin + for (i=0; i<85; i=i+1) begin + srs = data>>>i; + //$write (" %x >>> %d == %x\n",data,i,srs); + for (b=0; b<80; b=b+1) begin + if (srs[b] != (b>=(79-i) || b==(10-i))) $stop; + end + end + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_sign_extend.v b/SVIncCompil/Testcases/Verilator/t_math_sign_extend.v new file mode 100644 index 0000000..0dcba05 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_sign_extend.v
@@ -0,0 +1,131 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This test demonstrates an issue with sign extension. +// Assigning to localparms larger than 32 bits broke in 3.862 +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Mike Thyer. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + + localparam [ 0:0] one1_lp = 1; + localparam [ 1:0] one2_lp = 1; + localparam [ 2:0] one3_lp = 1; + localparam [ 3:0] one4_lp = 1; + localparam [ 4:0] one5_lp = 1; + localparam [ 5:0] one6_lp = 1; + localparam [ 6:0] one7_lp = 1; + localparam [ 7:0] one8_lp = 1; + localparam [ 8:0] one9_lp = 1; + localparam [ 9:0] one10_lp = 1; + localparam [19:0] one20_lp = 1; + localparam [29:0] one30_lp = 1; + localparam [30:0] one31_lp = 1; + localparam [31:0] one32_lp = 1; + localparam [32:0] one33_lp = 1; + localparam [33:0] one34_lp = 1; + localparam [34:0] one35_lp = 1; + localparam [35:0] one36_lp = 1; + localparam [36:0] one37_lp = 1; + localparam [37:0] one38_lp = 1; + localparam [38:0] one39_lp = 1; + localparam [39:0] one40_lp = 1; + localparam [49:0] one50_lp = 1; + localparam [59:0] one60_lp = 1; + localparam [60:0] one61_lp = 1; + localparam [61:0] one62_lp = 1; + localparam [62:0] one63_lp = 1; + localparam [63:0] one64_lp = 1; + localparam [64:0] one65_lp = 1; + localparam [65:0] one66_lp = 1; + localparam [66:0] one67_lp = 1; + localparam [67:0] one68_lp = 1; + localparam [68:0] one69_lp = 1; + localparam [69:0] one70_lp = 1; + + bit all_ok = 1; + + initial begin +`ifdef TEST_VERBOSE + $display("one1_lp : %x %d", one1_lp, one1_lp==1); + $display("one2_lp : %x %d", one2_lp, one2_lp==1); + $display("one3_lp : %x %d", one3_lp, one3_lp==1); + $display("one4_lp : %x %d", one4_lp, one4_lp==1); + $display("one5_lp : %x %d", one5_lp, one5_lp==1); + $display("one6_lp : %x %d", one6_lp, one6_lp==1); + $display("one7_lp : %x %d", one7_lp, one7_lp==1); + $display("one8_lp : %x %d", one8_lp, one8_lp==1); + $display("one9_lp : %x %d", one9_lp, one9_lp==1); + $display("one10_lp: %x %d", one10_lp, one10_lp==1); + $display("one20_lp: %x %d", one20_lp, one20_lp==1); + $display("one30_lp: %x %d", one30_lp, one30_lp==1); + $display("one31_lp: %x %d", one31_lp, one31_lp==1); + $display("one32_lp: %x %d", one32_lp, one32_lp==1); + $display("one33_lp: %x %d", one33_lp, one33_lp==1); + $display("one34_lp: %x %d", one34_lp, one34_lp==1); + $display("one35_lp: %x %d", one35_lp, one35_lp==1); + $display("one36_lp: %x %d", one36_lp, one36_lp==1); + $display("one37_lp: %x %d", one37_lp, one37_lp==1); + $display("one38_lp: %x %d", one38_lp, one38_lp==1); + $display("one39_lp: %x %d", one39_lp, one39_lp==1); + $display("one40_lp: %x %d", one40_lp, one40_lp==1); + $display("one50_lp: %x %d", one50_lp, one50_lp==1); + $display("one60_lp: %x %d", one60_lp, one60_lp==1); + $display("one61_lp: %x %d", one61_lp, one61_lp==1); + $display("one62_lp: %x %d", one62_lp, one62_lp==1); + $display("one63_lp: %x %d", one63_lp, one63_lp==1); + $display("one64_lp: %x %d", one64_lp, one64_lp==1); + $display("one65_lp: %x %d", one65_lp, one65_lp==1); + $display("one66_lp: %x %d", one66_lp, one66_lp==1); + $display("one67_lp: %x %d", one67_lp, one67_lp==1); + $display("one68_lp: %x %d", one68_lp, one68_lp==1); + $display("one69_lp: %x %d", one69_lp, one69_lp==1); + $display("one70_lp: %x %d", one70_lp, one70_lp==1); +`endif + + all_ok &= one1_lp == 1; + all_ok &= one2_lp == 1; + all_ok &= one3_lp == 1; + all_ok &= one4_lp == 1; + all_ok &= one5_lp == 1; + all_ok &= one6_lp == 1; + all_ok &= one7_lp == 1; + all_ok &= one8_lp == 1; + all_ok &= one9_lp == 1; + all_ok &= one10_lp == 1; + all_ok &= one20_lp == 1; + all_ok &= one30_lp == 1; + all_ok &= one31_lp == 1; + all_ok &= one32_lp == 1; + all_ok &= one33_lp == 1; + all_ok &= one34_lp == 1; + all_ok &= one35_lp == 1; + all_ok &= one36_lp == 1; + all_ok &= one37_lp == 1; + all_ok &= one38_lp == 1; + all_ok &= one39_lp == 1; + all_ok &= one40_lp == 1; + all_ok &= one50_lp == 1; + all_ok &= one60_lp == 1; + all_ok &= one61_lp == 1; + all_ok &= one62_lp == 1; + all_ok &= one63_lp == 1; + all_ok &= one64_lp == 1; + all_ok &= one65_lp == 1; + all_ok &= one66_lp == 1; + all_ok &= one67_lp == 1; + all_ok &= one68_lp == 1; + all_ok &= one69_lp == 1; + all_ok &= one70_lp == 1; + + if (!all_ok) $stop; + $write("*-* All Finished *-*\n"); + $finish; + + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_signed.v b/SVIncCompil/Testcases/Verilator/t_math_signed.v new file mode 100644 index 0000000..2d176c0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_signed.v
@@ -0,0 +1,205 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + by_width #(1) w1 (.clk(clk)); + by_width #(31) w31 (.clk(clk)); + by_width #(32) w32 (.clk(clk)); + by_width #(33) w33 (.clk(clk)); + by_width #(63) w63 (.clk(clk)); + by_width #(64) w64 (.clk(clk)); + by_width #(65) w65 (.clk(clk)); + by_width #(95) w95 (.clk(clk)); + by_width #(96) w96 (.clk(clk)); + by_width #(97) w97 (.clk(clk)); + + reg signed [15:0] a; + reg signed [4:0] b; + + reg signed [15:0] sr,srs,sl,sls; + + reg [15:0] b_s; + reg [15:0] b_us; + + task check_s(input signed [7:0] i, input [7:0] expval); + //$display("check_s %x\n", i); + if (i !== expval) $stop; + endtask + task check_us(input signed [7:0] i, input [7:0] expval); + //$display("check_us %x\n", i); + if (i !== expval) $stop; + endtask + + always @* begin + sr = a>>b; + srs = copy_signed(a)>>>b; + sl = a<<b; + sls = a<<<b; + // verilator lint_off WIDTH + b_s = b>>>4; // Signed + b_us = b[4:0]>>>4; // Unsigned, due to extract + check_s ( 3'b111, 8'h07); + check_s (3'sb111, 8'hff); + check_us( 3'b111, 8'h07); + check_us(3'sb111, 8'hff); // Note we sign extend ignoring function's input requirements + // verilator lint_on WIDTH + end + + reg signed [32:0] bug349; + + initial + begin + end + integer i; + initial begin + if ((-1 >>> 3) != -1) $stop; // Decimals are signed + // verilator lint_off WIDTH + if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned + if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers + // verilator lint_on WIDTH + if ( (3'sb000 > 3'sb000)) $stop; + if (!(3'sb000 > 3'sb111)) $stop; + if ( (3'sb111 > 3'sb000)) $stop; + if ( (3'sb000 < 3'sb000)) $stop; + if ( (3'sb000 < 3'sb111)) $stop; + if (!(3'sb111 < 3'sb000)) $stop; + if (!(3'sb000 >= 3'sb000)) $stop; + if (!(3'sb000 >= 3'sb111)) $stop; + if ( (3'sb111 >= 3'sb000)) $stop; + if (!(3'sb000 <= 3'sb000)) $stop; + if ( (3'sb000 <= 3'sb111)) $stop; + if (!(3'sb111 <= 3'sb000)) $stop; + // When we multiply overflow, the sign bit stays correct. + if ( (4'sd2*4'sd8) != 4'd0) $stop; + // From the spec: + // verilator lint_off WIDTH + i = -12 /3; if (i !== 32'hfffffffc) $stop; + i = -'d12 /3; if (i !== 32'h55555551) $stop; + i = -'sd12 /3; if (i !== 32'hfffffffc) $stop; + i = -4'sd12 /3; if (i !== 32'h00000001) $stop; + // verilator lint_on WIDTH + + // verilator lint_off WIDTH + bug349 = 4'sb1111 - 1'b1; + if (bug349 != 32'he) $stop; + end + + function signed [15:0] copy_signed; + input [15:0] ai; + copy_signed = ai; + endfunction + + integer cyc; initial cyc=0; + wire [31:0] ucyc = cyc; + always @ (posedge clk) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%x %x %x %x %x %x %x\n", cyc, sr,srs,sl,sls, b_s,b_us); +`endif + case (cyc) + 0: begin + a <= 16'sh8b1b; b <= 5'sh1f; // -1 + end + 1: begin + // Check spaces in constants + a <= 16 'sh 8b1b; b <= 5'sh01; // -1 + end + 2: begin + a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned + if (ucyc / 1 != 32'd2) $stop; + if (ucyc / 2 != 32'd1) $stop; + if (ucyc * 1 != 32'd2) $stop; + if (ucyc * 2 != 32'd4) $stop; + if (ucyc * 3 != 32'd6) $stop; + if (cyc * 32'sd1 != 32'sd2) $stop; + if (cyc * 32'sd2 != 32'sd4) $stop; + if (cyc * 32'sd3 != 32'sd6) $stop; + end + 3: begin + a <= 16'sh0048; b <= 5'sh1f; + if (ucyc * 1 != 32'd3) $stop; + if (ucyc * 2 != 32'd6) $stop; + if (ucyc * 3 != 32'd9) $stop; + if (ucyc * 4 != 32'd12) $stop; + if (cyc * 32'sd1 != 32'sd3) $stop; + if (cyc * 32'sd2 != 32'sd6) $stop; + if (cyc * 32'sd3 != 32'sd9) $stop; + end + 4: begin + a <= 16'sh4154; b <= 5'sh02; + end + 5: begin + a <= 16'shc3e8; b <= 5'sh12; + end + 6: begin + a <= 16'sh488b; b <= 5'sh02; + end + 9: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + case (cyc) + 0: ; + 1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop; + 3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop; + 5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop; + 6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop; + 8: ; + 9: ; + endcase + end +endmodule + + +module by_width ( + input clk + ); + parameter WIDTH=1; + + reg signed i1; + reg signed [62:0] i63; + reg signed [64:0] i65; + + // verilator lint_off WIDTH + wire signed [WIDTH-1:0] i1extp /*verilator public*/ = i1; + wire signed [WIDTH-1:0] i1ext = i1; + wire signed [WIDTH-1:0] i63ext = i63; + wire signed [WIDTH-1:0] i65ext = i65; + // verilator lint_on WIDTH + + integer cyc; initial cyc=0; + always @ (posedge clk) begin + cyc <= cyc + 1; + i1 <= cyc[0]; + i63 <= {63{cyc[0]}}; + i65 <= {65{cyc[0]}}; + case (cyc) + 1: begin + if (i1extp != {WIDTH{1'b0}}) $stop; + if (i1ext != {WIDTH{1'b0}}) $stop; + if (i63ext != {WIDTH{1'b0}}) $stop; + if (i65ext != {WIDTH{1'b0}}) $stop; + end + 2: begin + if (i1extp != {WIDTH{1'b1}}) $stop; + if (i1ext != {WIDTH{1'b1}}) $stop; + if (i63ext != {WIDTH{1'b1}}) $stop; + if (i65ext != {WIDTH{1'b1}}) $stop; + end + default: ; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_signed2.v b/SVIncCompil/Testcases/Verilator/t_math_signed2.v new file mode 100644 index 0000000..1250f99 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_signed2.v
@@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Peter Debacker. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [10:0] in; + reg signed[7:0] min; + reg signed[7:0] max; + wire signed[7:0] filtered_data; + reg signed[7:0] delay_minmax[31:0]; + integer k; + + initial begin + in = 11'b10000001000; + for(k=0;k<32;k=k+1) + delay_minmax[k] = 0; + end + + assign filtered_data = $signed(in[10:3]); + + always @(posedge clk) begin + in = in + 8; +`ifdef TEST_VERBOSE + $write("filtered_data: %d\n", filtered_data); +`endif + // delay line shift + for (k=31;k>0;k=k-1) begin + delay_minmax[k] = delay_minmax[k-1]; + end + delay_minmax[0] = filtered_data; +`ifdef TEST_VERBOSE + $write("delay_minmax[0] = %d\n", delay_minmax[0]); + $write("delay_minmax[31] = %d\n", delay_minmax[31]); +`endif + // find min and max + min = 127; + max = -128; +`ifdef TEST_VERBOSE + $write("max init: %d\n", max); + $write("min init: %d\n", min); +`endif + for(k=0;k<32;k=k+1) begin + if ((delay_minmax[k]) > $signed(max)) + max = delay_minmax[k]; + if ((delay_minmax[k]) < $signed(min)) + min = delay_minmax[k]; + end +`ifdef TEST_VERBOSE + $write("max: %d\n", max); + $write("min: %d\n", min); +`endif + if (min == 127) begin + $stop; + end + else if (filtered_data >= -61) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_signed3.v b/SVIncCompil/Testcases/Verilator/t_math_signed3.v new file mode 100644 index 0000000..c932ac3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_signed3.v
@@ -0,0 +1,100 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + +module t (/*AUTOARG*/); + + // verilator lint_off WIDTH + wire [1:0] bug729_au = ~0; + wire signed [1:0] bug729_as = ~0; + wire [2:0] bug729_b = ~0; + // the $signed output is unsigned because the input is unsigned; the signedness does not change. + wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 + wire [0:0] bug729_ysu = $signed(2'sb11) == 3'b111; //1'b0 + wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 + wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 + wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0 + wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0 + wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1 + wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1 + + wire [3:0] bug733_a = 4'b0010; + wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned + wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111 + + wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111 + wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111 + + // When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign + + wire [3:0] bug733_qu = 2'sb11; // 4'b1111 + wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111 + reg signed [32:0] bug349_s; + reg signed [32:0] bug349_u; + + wire signed [1:0] sb11 = 2'sb11; + + wire [3:0] subout_u; + sub sub (.a(2'sb11), .z(subout_u)); + initial `checkh(subout_u, 4'b1111); + + wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111; + initial `checkh(cond_a, 6'b111111); + wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; + initial `checkh(cond_b, 6'b111111); + + initial begin + // verilator lint_on WIDTH + `checkh(bug729_yuu, 1'b0); + `checkh(bug729_ysu, 1'b0); + `checkh(bug729_yus, 1'b1); + `checkh(bug729_yss, 1'b1); + + `checkh(bug729_zuu, 1'b0); + `checkh(bug729_zsu, 1'b0); + `checkh(bug729_zus, 1'b1); + `checkh(bug729_zss, 1'b1); + + `checkh(bug733_yu, 4'b1111); + `checkh(bug733_ys, 4'b1111); + + `checkh(bug733_zu, 4'b1111); + `checkh(bug733_zs, 4'b1111); + + `checkh(bug733_qu, 4'b1111); + `checkh(bug733_qs, 4'b1111); + + // verilator lint_off WIDTH + bug349_s = 4'sb1111; + `checkh(bug349_s, 33'h1ffffffff); + bug349_u = 4'sb1111; + `checkh(bug349_u, 33'h1ffffffff); + + bug349_s = 4'sb1111 - 1'b1; + `checkh(bug349_s,33'he); + + bug349_s = 4'sb1111 - 5'b00001; + `checkh(bug349_s,33'he); + + case (2'sb11) + 4'b1111: ; + default: $stop; + endcase + + case (sb11) + 4'b1111: ; + default: $stop; + endcase + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub (input [3:0] a, + output [3:0] z); + assign z = a; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_signed4.v b/SVIncCompil/Testcases/Verilator/t_math_signed4.v new file mode 100644 index 0000000..200cb47 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_signed4.v
@@ -0,0 +1,140 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) +`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) + +module t (/*AUTOARG*/); + + bit fail; + + localparam signed [3:0] bug737_p1 = 4'b1000; + + wire [3:0] bug737_a = 4'b1010; + reg [5:0] bug737_y; + reg signed [3:0] w4_s; + reg signed [4:0] w5_s; + reg [3:0] w4_u; + reg [4:0] w5_u; + reg signed [8:0] w9_s; + real r; + initial begin + // verilator lint_off WIDTH + bug737_y = bug737_a + (bug737_p1 + 4'sb0); + `checkh(bug737_y, 6'b010010); //bug737 + + // 6u +[6u] 4s +[6s] 6s + bug737_y = 6'b001010 + (4'sb1000 + 6'sb0); + `checkh(bug737_y, 6'b010010); //bug737, getx 000010 + + // 6u +[6u] 4s +[6s] 6s + bug737_y = 6'b001010 + (4'b1000 + 6'sb0); + `checkh(bug737_y, 6'b010010); //ok + + bug737_y = 6'b001010 + (6'sb111000 + 6'sb0); + `checkh(bug737_y, 6'b000010); //ok + + // v--- sign extends to 6-bits + bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0); + `checkh(bug737_y, 6'b000010); //ok + + // From t_math_signed_3 + w4_s = 4'sb1111 - 1'b1; + `checkh(w4_s,33'he); + + w4_s = 4'sb1111 - 5'b00001; + `checkh(w4_s,33'he); + + w4_s = 4'sb1111 - 1'sb1; + `checkh(w4_s,4'h0); + w5_s = 4'sb1111 - 1'sb1; + `checkh(w5_s,4'h0); + + w4_s = 4'sb1111 - 4'sb1111; + `checkh(w4_s,4'h0); + w5_s = 4'sb1111 - 4'sb1111; + `checkh(w5_s,5'h0); + + // The assign LHS being signed or unsigned does not matter per IEEE + // The upper add being signed DOES matter propagating to lower + w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add + `checkh(w4_s,4'he); + w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend + `checkh(w4_s,4'h0); + w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend + `checkh(w4_s,4'he); // BUG, Verilator says 'h0 + + w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS + `checkh(w5_u, 5'b10000); + w4_u = 4'b1111 + 4'b0001; // Normal case + `checkh(w4_u, 4'b0000); + + // Another example of promotion, the add is 4 bits wide + w4_u = 3'b111 + 3'b010; + `checkh(w4_u, 4'b1001); + // + w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter + `checkh(w4_u, 4'sb1111); + w4_s = 3'sb111 * 3'sb001; // Signed output + `checkh(w4_s, 4'sb1111); + w4_s = 3'b111 * 3'sb001; // Unsigned output + `checkh(w4_s, 4'b0111); + + // Conditionals get width from parent; are assignment-like + w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11); + `checkh(w4_u, 4'b0100); + w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000); + `checkh(w4_u, 4'b0000); + + // If RHS is larger, that larger size is used + w4_u = 5'b10000 / 5'b00100; + `checkh(w4_u, 4'b0100); + + // bug754 + w5_u = 4'sb0010 << -2'sd1; // << 3 +`ifdef VCS + `checkh(w5_u, 5'b00000); // VCS E-2014.03 bug +`else + `checkh(w5_u, 5'b10000); // VCS E-2014.03 bug +`endif + w5_u = 4'sb1000 << 0; // Sign extends + `checkh(w5_u, 5'b11000); + + // Reals do not propagate to children + r = 1.0 + ( 1 + (1 / 2)); + `checkf(r, 2.0); + + // Self determined sign extension + r = $itor(3'sb111); + `checkf(r, -1.0); + + // If any part of case is real, all is real + case (22) + 22.0: ; + 22.1: $stop; + default: $stop; + endcase + + // bug759 + w5_u = { -4'sd7 }; + `checkh(w5_u, 5'b01001); + w5_u = {2{ -2'sd1 }}; + `checkh(w5_u, 5'b01111); + // Don't break concats.... + w5_u = {{0{1'b1}}, -4'sd7 }; + `checkh(w5_u, 5'b01001); + w9_s = { -4'sd7, -4'sd7 }; + `checkh(w9_s, 9'b010011001); + {w5_u, {w4_u}} = 9'b10101_1100; + `checkh(w5_u, 5'b10101); + `checkh(w4_u, 4'b1100); + {w4_u} = 4'b1011; + `checkh(w4_u, 4'b1011); + + if (fail) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_signed5.v b/SVIncCompil/Testcases/Verilator/t_math_signed5.v new file mode 100644 index 0000000..c2f4ef3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_signed5.v
@@ -0,0 +1,190 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) +`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) +`ifdef VERILATOR + `define c(v,vs) ($c(vs)) // Don't constify a value +`else + `define c(v,vs) (v) +`endif + + module t (/*AUTOARG*/ + // Outputs + ow4_u + ); + + bit fail; + + reg signed [3:0] w4_s; + reg signed [4:0] w5_s; + reg [2:0] w3_u; + reg [3:0] w4_u; + reg [4:0] w5_u; + reg [5:0] w6_u; + reg [15:0] w16a_u; + reg [15:0] w16_u; + reg [31:0] w32_u; + real r; + + reg signed [4:0] bug754_a; + + integer i; + + //verilator lint_off WIDTH + wire a = (5'b0 == (5'sb11111 >>> 3'd7)); + wire b = (5'sb11111 == (5'sb11111 >>> 3'd7)); + wire c = (1'b0+(5'sb11111 >>> 3'd7)); + wire d = (1'sb0+(5'sb11111 >>> 3'd7)); + wire e = (5'b0 == (5'sb11111 / 5'sd3)); + wire f = (5'sb0 == (5'sb11111 / 5'sd3)); + wire g = (5'b01010 == (5'b11111 / 5'sd3)); + initial begin + // verilator lint_off STMTDLY + #1; +`ifdef VCS // I-2014.03 + `checkh({a, b, c, d, e, f, g}, 7'b1101111); +`else + `checkh({a, b, c, d, e, f, g}, 7'b1101011); +`endif + + //====================================================================== + + if ((-1 >>> 3) != -1) $stop; // Decimals are signed + + i = 3'sb111 >>> 3; + `checkh(i, -1); + i = -1 >>> 3; + `checkh(i, -1); + + bug754_a = -1; + w4_u = |0 != (bug754_a >>> 3'd7); + `checkh(w4_u, 4'b0); + + // Sanity check: -1>>7 == -1 + w5_u = (5'sb11111 >>> 3'd7); + `checkh(w5_u, 5'b11111); + + // bug756 + w4_u = (5'b0 == (5'sb11111 >>> 3'd7)); + `checkh(w4_u, 4'b0001); + w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0 + `checkh(w4_u, 4'b0001); + w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>> +`ifdef VCS // I-2014.03 + `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate +`else + `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... +`endif + + // Does == sign propagate from lhs to rhs? Yes, but not in VCS + w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero +`ifdef VCS // I-2014.03 + `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate + // Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others +`else + `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... +`endif + + w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter + `checkh(w4_u, 4'b0000); + + w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero + `checkh(w4_u, 4'b0001); + // Does == width propagate from lhs to rhs? Yes + w4_u = (3'b100==(3'b111 << 2)); + `checkh(w4_u, 4'b0001); + w4_u = (4'b100==(3'b111 << 2)); + `checkh(w4_u, 4'b0000); + w4_u = (4'b1100==(3'b111 << 2)); + `checkh(w4_u, 4'b0001); + + // Does >>> sign propagate from input same as for +? Yes + w4_u = (1'b0+(5'sb11111 >>> 3'd7)); + `checkh(w4_u, 4'b0000); + w4_u = (1'sb0+(5'sb11111 >>> 3'd7)); + `checkh(w4_u, 4'b1111); + + // Does << width propagate from input same as for +? Yes + w4_u = (3'b0+(3'b111 << 2)); + `checkh(w4_u, 4'b1100); // width 4 =='s LHS + w4_u = (4'b0+(3'b111 << 2)); + `checkh(w4_u, 4'b1100); + + w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==????? + `checkh(w4_u, 4'b0001); + w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); + `checkh(w4_u, 4'b0001); + + // bug756 + w5_s = -1; + w3_u = 7; + w4_u = |0 != (w5_s >>> w3_u); + `checkh(w4_u, 4'b0000); + + // bug763 + w3_u = 2; + w4_u = (w3_u >> 2'b11) >> 1; + `checkh(w4_u, 4'b0000); + + // bug766 + w16a_u = 16'h1234; + w16_u = (w16a_u >> 16) >>> 32'h7ffffff1; + `checkh(w16_u, 16'h0000); + + // bug768 + w4_s = 4'sd4; + w4_u = $signed(5'd1 > w4_s-w4_s); + `checkh(w4_u, 4'b1111); + w4_s = `c(4,"4"); // Eval at runtime + w4_u = $signed(5'd1 > w4_s-w4_s); + `checkh(w4_u, 4'b1111); + + // bug772 + w4_s = w4_u << 1 <<< 0/0; +`ifndef VERILATOR // In v4 can't check value as not 4-state + `checkh(w4_s, 4'bxxxx); +`endif + + // bug773 + w5_u = `c(31, 31); + w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u); + `checkh(w5_s, 5'b0); + + // bug774 + w4_u = `c(4, 5); + w6_u = `c(6, 35); + w4_u = 64'd0 | (w4_u << w6_u); + `checkh(w4_u, 0); + + // bug776 + w4_u = `c(4, 1); + w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u); + `checkh(w4_u, 4'b1111); + + // bug828 + // verilator lint_off WIDTH + w32_u = 32'(signed'({4'b0001,5'b10000}) << 3); + `checkh(w32_u, 32'h0000_0180); + w32_u = 32'(signed'({4'b0011,5'b10000}) << 3); + `checkh(w32_u, 32'h0000_0380); + w32_u = signed'(32'({4'b0001,5'b10000}) << 3); + `checkh(w32_u, 32'h0000_0180); + w32_u = signed'(32'({4'b0011,5'b10000}) << 3); + `checkh(w32_u, 32'h0000_0380); + // verilator lint_on WIDTH + w32_u = 32'(signed'({4'b0011,5'b10000})) << 3; // Check no width warning + `checkh(w32_u, 32'h0000_0380); + + if (fail) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + + // bug775 + output [3:0] ow4_u; // Must be consumed + assign ow4_u = ((0/0) ? 1 : 2) % 0; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_signed6.v b/SVIncCompil/Testcases/Verilator/t_math_signed6.v new file mode 100644 index 0000000..6652225 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_signed6.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Iztok Jeras. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + + module t (/*AUTOARG*/); + + // signed source + logic signed [8-1:0] src; + + // destination structure + struct packed { + logic signed [16-1:0] s; + logic unsigned [16-1:0] u; + } dst; + + initial begin + // bug882 + // verilator lint_off WIDTH + src = 8'sh05; + dst = '{s: src, u: src}; + `checkh (dst.s, 16'h0005); + `checkh (dst.u, 16'h0005); + + src = 8'shf5; + dst = '{s: src, u: src}; + `checkh (dst.s, 16'hfff5); + `checkh (dst.u, 16'hfff5); + // verilator lint_on WIDTH + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_signed7.v b/SVIncCompil/Testcases/Verilator/t_math_signed7.v new file mode 100644 index 0000000..421fde7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_signed7.v
@@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Iztok Jeras. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg alu_ltu, alu_lts; + logic [3:0] in_op1; + logic [3:0] in_op2; + + + reg aaa_ltu, aaa_lts; + always @(posedge clk) begin + in_op1 = 4'sb1110; + in_op2 = 4'b0010; + aaa_ltu = in_op1 < in_op2; + // bug999 + aaa_lts = $signed(in_op1) < $signed(in_op2); + `checkh (aaa_ltu, 1'b0); + `checkh (aaa_lts, 1'b1); + end + + generate if (1) begin + always @(posedge clk) begin + in_op1 = 4'sb1110; + in_op2 = 4'b0010; + alu_ltu = in_op1 < in_op2; + // bug999 + alu_lts = $signed(in_op1) < $signed(in_op2); + `checkh (alu_ltu, 1'b0); + `checkh (alu_lts, 1'b1); + $write("*-* All Finished *-*\n"); + $finish; + end + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_signed_wire.v b/SVIncCompil/Testcases/Verilator/t_math_signed_wire.v new file mode 100644 index 0000000..faa7e53 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_signed_wire.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// bug511 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [7:0] au; + wire [7:0] as; + + Test1 test1 (.au); + Test2 test2 (.as); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] result=%x %x\n",$time, au, as); +`endif + if (au != 'h12) $stop; + if (as != 'h02) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module Test1 (output [7:0] au); + wire [7:0] b; + wire signed [3:0] c; + + // verilator lint_off WIDTH + assign c=-1; // 'hf + assign b=3; // 'h3 + assign au=b+c; // 'h12 + // verilator lint_on WIDTH +endmodule + + +module Test2 (output [7:0] as); + wire signed [7:0] b; + wire signed [3:0] c; + + // verilator lint_off WIDTH + assign c=-1; // 'hf + assign b=3; // 'h3 + assign as=b+c; // 'h12 + // verilator lint_on WIDTH +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_strwidth.v b/SVIncCompil/Testcases/Verilator/t_math_strwidth.v new file mode 100644 index 0000000..87dc82e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_strwidth.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008-2008 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [4*8:1] strg; + + initial begin + strg = "CHK"; + if (strg != "CHK") $stop; + if (strg == "JOE") $stop; + $write("String = %s = %x\n", strg, strg); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_svl.v b/SVIncCompil/Testcases/Verilator/t_math_svl.v new file mode 100644 index 0000000..8f68717 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_svl.v
@@ -0,0 +1,141 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [15:0] l; + reg [49:0] q; + reg [79:0] w; + reg [4:0] lc; + reg lo; + reg l0; + reg [5:0] qc; + reg qo; + reg q0; + reg [6:0] wc; + reg wo; + reg w0; + + always @* begin + lc = $countones(l); + lo = $onehot(l); + l0 = $onehot0(l); + wc = $countones(w); + wo = $onehot(w); + w0 = $onehot0(w); + qc = $countones(q); + qo = $onehot(q); + q0 = $onehot0(q); + end + + integer cyc; initial cyc=1; + integer cyc_com; + always_comb begin + cyc_com = cyc; + end + + integer cyc_d1; + always_ff @ (posedge clk) begin + cyc_d1 <= cyc_com; + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n", + // cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0); + if (cyc_com != cyc_com) $stop; + if (cyc_d1 != cyc-1) $stop; + if (cyc==0) begin + // Constification check + if ($countones(32'b11001011101) != 7) $stop; + if ($countones(32'b0) != 0) $stop; + if ($isunknown(32'b11101x11111) != 1) $stop; + if ($isunknown(32'b11101011111) != 0) $stop; + if ($isunknown(32'b10zzzzzzzzz) != 0) $stop; + if ($bits(0) != 32'd32) $stop; + if ($bits(lc) != 5) $stop; + if ($onehot(32'b00000001000000) != 1'b1) $stop; + if ($onehot(32'b00001001000000) != 1'b0) $stop; + if ($onehot(32'b0) != 1'b0) $stop; + if ($onehot0(32'b00000001000000) != 1'b1) $stop; + if ($onehot0(32'b00001001000000) != 1'b0) $stop; + if ($onehot0(32'b0) != 1'b1) $stop; + end + if (cyc==1) begin + l <= 16'b0; + q <= 50'h0; + w <= 80'h0; + end + if (cyc==2) begin + l <= ~16'b0; + q <= ~50'h0; + w <= ~80'h0; + // + if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop; + if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop; + if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop; + end + if (cyc==3) begin + l <= 16'b0010110010110111; + q <= 50'h01_1111_0001; + w <= 80'h0100_0000_0f00_00f0_0000; + // + if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop; + if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop; + if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop; + end + if (cyc==4) begin + l <= 16'b0000010000000000; + q <= 50'h1_0000_0000; + w <= 80'h010_00000000_00000000; + // + if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop; + if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop; + if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop; + end + if (cyc==5) begin + l <= 16'b0000000100000000; + q <= 50'h8000_0000_0000; + w <= 80'h10_00000000_00000000; + // + if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop; + if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop; + if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop; + end + if (cyc==6) begin + l <= 16'b0000100100000000; + q <= 50'h01_00000100; + w <= 80'h01_00000100_00000000; + // + if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop; + if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop; + if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop; + end + if (cyc==7) begin + // + if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop; + if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop; + if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop; + end + if (cyc==8) begin + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + final begin + $write("Goodbye world, at cycle %0d\n", cyc); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_svl2.v b/SVIncCompil/Testcases/Verilator/t_math_svl2.v new file mode 100644 index 0000000..bb6f7e4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_svl2.v
@@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + // New number format + if ('0 !== {66{1'b0}}) $stop; + if ('1 !== {66{1'b1}}) $stop; + if ('x !== {66{1'bx}}) $stop; + if ('z !== {66{1'bz}}) $stop; +`ifndef NC // NC-Verilog 5.50-s09 chokes on this test + if ("\v" != 8'd11) $stop; + if ("\f" != 8'd12) $stop; + if ("\a" != 8'd7) $stop; + if ("\x9a" != 8'h9a) $stop; + if ("\xf1" != 8'hf1) $stop; +`endif + end + if (cyc==8) begin + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_swap.v b/SVIncCompil/Testcases/Verilator/t_math_swap.v new file mode 100644 index 0000000..96daf42 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_swap.v
@@ -0,0 +1,164 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] Operand1 = crc[31:0]; + wire [15:0] Operand2 = crc[47:32]; + wire Unsigned = crc[48]; + reg rst; + + parameter wl = 16; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [wl-1:0] Quotient; // From test of Test.v + wire [wl-1:0] Remainder; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .Quotient (Quotient[wl-1:0]), + .Remainder (Remainder[wl-1:0]), + // Inputs + .Operand1 (Operand1[wl*2-1:0]), + .Operand2 (Operand2[wl-1:0]), + .clk (clk), + .rst (rst), + .Unsigned (Unsigned)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, Quotient, Remainder}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h98d41f89a8be5693 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration); +`endif + cyc <= cyc + 1; + if (cyc < 20 || test.Iteration==4'd15) begin + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + end + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + rst <= 1'b1; + end + else if (cyc<20) begin + sum <= 64'h0; + rst <= 1'b0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'h8dd70a44972ad809) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); + + parameter wl = 16; + + input [wl*2-1:0] Operand1; + input [wl-1:0] Operand2; + input clk, rst, Unsigned; + output [wl-1:0] Quotient, Remainder; + + reg Cy, Overflow, Sign1, Sign2, Zero, Negative; + reg [wl-1:0] ah,al,Quotient, Remainder; + reg [3:0] Iteration; + reg [wl-1:0] sub_quot,op; + reg ah_ext; + + reg [1:0] a,b,c,d,e; + + always @(posedge clk) begin + if (!rst) begin + {a,b,c,d,e} = Operand1[9:0]; + {a,b,c,d,e} = {e,d,c,b,a}; + if (a != Operand1[1:0]) $stop; + if (b != Operand1[3:2]) $stop; + if (c != Operand1[5:4]) $stop; + if (d != Operand1[7:6]) $stop; + if (e != Operand1[9:8]) $stop; + end + end + + always @(posedge clk) begin + if (rst) begin + Iteration <= 0; + Quotient <= 0; + Remainder <= 0; + end + else begin + if (Iteration == 0) begin + {ah,al} = Operand1; + op = Operand2; + Cy = 0; + Overflow = 0; + Sign1 = (~Unsigned)&ah[wl-1]; + Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]); + if (Sign1) {ah,al} = -{ah,al}; + end +`define BUG1 +`ifdef BUG1 + {ah_ext,ah,al} = {ah,al,Cy}; +`else + ah_ext = ah[15]; + ah[15:1] = ah[14:0]; + ah[0] = al[15]; + al[15:1] = al[14:0]; + al[0] = Cy; +`endif +`ifdef TEST_VERBOSE + $display("%x %x %x %x %x %x %x %x %x", + Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); +`endif + {Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op}; + if (Cy) + begin + {ah_ext,ah} = {1'b0,sub_quot}; + end + if (Iteration != 15 ) + begin + if (ah_ext) Overflow = 1; + end + else + begin + if (al[14] && ~Unsigned) Overflow = 1; + Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy}; + Remainder <= Sign1 ? -ah : ah; + if (Overflow) + begin + Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}}; + Remainder <= Unsigned ? 16'hffff : 16'h8000; + Zero = 1; + Negative = 1; + end + end + Iteration <= Iteration + 1; // Count number of times this instruction is repeated + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_tri.v b/SVIncCompil/Testcases/Verilator/t_math_tri.v new file mode 100644 index 0000000..96a8737 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_tri.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [3:0] a; + reg [99:0] x; + + initial begin + a = 4'b010x; + if (a[3:2] !== 2'b01) $stop; + if (|a !== 1'b1) $stop; + if (&a !== 1'b0) $stop; + x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_trig.v b/SVIncCompil/Testcases/Verilator/t_math_trig.v new file mode 100644 index 0000000..2fa5815 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_trig.v
@@ -0,0 +1,152 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + real r, r2; + integer cyc=0; + + task check(integer line, real got, real ex); + if (got != ex) begin + if ((got > ex ? got - ex : ex - got) > 0.000001) begin + $display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex); + $stop; + end + end + endtask + + initial begin + // Check constant propagation + // Note $abs is not defined in SystemVerilog (as of 2012) + check(`__LINE__, $ceil(-1.2), -1); + check(`__LINE__, $ceil(1.2), 2); + check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125); + check(`__LINE__, $exp(0.0), 1); + check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375); + check(`__LINE__, $floor(-1.2), -2); + check(`__LINE__, $floor(1.2), 1); + check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625); + //check(`__LINE__, $ln(0), 0); // Bad value + //check(`__LINE__, $ln(-1.2), 0); // Bad value + check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875); + //check(`__LINE__, $log10(0), 0); // Bad value + //check(`__LINE__, $log10(-1.2), 0); + check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375); + check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875); + //check(`__LINE__, $pow(-2.3,1.2),0); // Bad value + check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125); + //check(`__LINE__, $sqrt(-1.2), 0); // Bad value + check(`__LINE__, ((1.5)**(1.25)), 1.660023); + check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1 + check(`__LINE__, $acosh(1.2), 0.622362503); + check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1 + check(`__LINE__, $asinh(1.2), 1.015973134); + check(`__LINE__, $atan (0.2), 0.197395559); + check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1 + check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1 + check(`__LINE__, $cos (1.2), 0.362357754); + check(`__LINE__, $cosh (1.2), 1.810655567); + check(`__LINE__, $hypot(1.2,2.3), 2.594224354); + check(`__LINE__, $sin (1.2), 0.932039085); + check(`__LINE__, $sinh (1.2), 1.509461355); + check(`__LINE__, $tan (1.2), 2.572151622); + check(`__LINE__, $tanh (1.2), 0.833654607); + end + + real sum_ceil; + real sum_exp; + real sum_floor; + real sum_ln; + real sum_log10; + real sum_pow1; + real sum_pow2; + real sum_sqrt; + + real sum_acos; + real sum_acosh; + real sum_asin; + real sum_asinh; + real sum_atan; + real sum_atan2; + real sum_atanh; + real sum_cos ; + real sum_cosh; + real sum_hypot; + real sum_sin; + real sum_sinh; + real sum_tan; + real sum_tanh; + + // Test loop + always @ (posedge clk) begin + r = $itor(cyc)/10.0 - 5.0; // Crosses 0 +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n",$time, cyc, r, sum_ln); +`endif + cyc <= cyc + 1; + if (cyc==0) begin + end + else if (cyc<90) begin + // Setup + sum_ceil += 1.0+$ceil(r); + sum_exp += 1.0+$exp(r); + sum_floor += 1.0+$floor(r); + if (r > 0.0) sum_ln += 1.0+$ln(r); + if (r > 0.0) sum_log10 += 1.0+$log10(r); + // Pow requires if arg1<0 then arg1 integral + sum_pow1 += 1.0+$pow(2.3,r); + if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3); + if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r); + + if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r); + if (r>=1.0) sum_acosh += 1.0+$acosh(r); + if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r); + sum_asinh += 1.0+$asinh(r); + sum_atan += 1.0+$atan (r); + if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3); + if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r); + sum_cos += 1.0+$cos (r); + sum_cosh += 1.0+$cosh (r); + sum_hypot += 1.0+$hypot(r,2.3); + sum_sin += 1.0+$sin (r); + sum_sinh += 1.0+$sinh (r); + sum_tan += 1.0+$tan (r); + sum_tanh += 1.0+$tanh (r); + end + else if (cyc==99) begin + check (`__LINE__, sum_ceil, 85); + check (`__LINE__, sum_exp, 608.06652950); + check (`__LINE__, sum_floor, 4); + check (`__LINE__, sum_ln, 55.830941633); + check (`__LINE__, sum_log10, 46.309585076); + check (`__LINE__, sum_pow1, 410.98798177); + check (`__LINE__, sum_pow2, 321.94765689); + check (`__LINE__, sum_sqrt, 92.269677253); + check (`__LINE__, sum_acos, 53.986722862); + check (`__LINE__, sum_acosh, 72.685208498); + check (`__LINE__, sum_asin, 21); + check (`__LINE__, sum_asinh, 67.034973416); + check (`__LINE__, sum_atan, 75.511045389); + check (`__LINE__, sum_atan2, 21); + check (`__LINE__, sum_atanh, 0); + check (`__LINE__, sum_cos, 72.042023124); + check (`__LINE__, sum_cosh, 1054.0178222); + check (`__LINE__, sum_hypot, 388.92858406); + check (`__LINE__, sum_sin, 98.264184989); + check (`__LINE__, sum_sinh, -356.9512927); + check (`__LINE__, sum_tan, 1.7007946043); + check (`__LINE__, sum_tanh, 79.003199681); + + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_vgen.v b/SVIncCompil/Testcases/Verilator/t_math_vgen.v new file mode 100644 index 0000000..fc98f93 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_vgen.v
@@ -0,0 +1,307 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + reg check; initial check = 1'b0; + + // verilator lint_off WIDTH + + //============================================================ + + reg [ 1:0] W0095; //=3 + reg [ 58:0] W0101; //=0000000FFFFFFFF + always @(posedge clk) begin + if (cyc==1) begin + W0095 = ((2'h3)); + W0101 = ({27'h0,({16{(W0095)}})}); + end + end + always @(posedge clk) begin + if (cyc==2) begin + if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop; + end + end + + //============================================================ + + reg [ 0:0] W1243; //=1 + always @(posedge clk) begin + if (cyc==1) begin + W1243 = ((1'h1)); + end + end + always @(posedge clk) begin + if (cyc==2) begin + // Width violation, but still... + if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop; + if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop; + end + end + + //============================================================ + + reg [ 0:0] W0344; //=0 + always @(posedge clk) begin + if (cyc==1) begin + W0344 = 1'b0; + end + end + always @(posedge clk) begin + if (cyc==2) begin + if ((W0344) != (1'h0)) if (check) $stop; + if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop; + end + end + + //============================================================ + + reg [ 63:0] W0372; //=FFFFFFFFFFFFFFFF + reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF + reg [115:0] W0421; //=00000000000000000000000000000 + always @(posedge clk) begin + if (cyc==1) begin + W0372 = ({64{((1'h1))}}); + W0421 = 116'h0; + W0420 = ({119{((W0372) <= (W0372))}}); + end + end + always @(posedge clk) begin + if (cyc==2) begin + if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop; + end + end + + //============================================================ + + // gcc_2_96_bug + reg [ 31:0] W0161; //=FFFFFFFF + reg [ 62:0] W0217; //=0000000000000000 + reg [ 53:0] W0219; //=00000000000000 + always @(posedge clk) begin + if (cyc==1) begin + W0161 = 32'hFFFFFFFF; + W0217 = 63'h0; + W0219 = 54'h0; + end + end + always @(posedge clk) begin + if (cyc==2) begin + if ((W0161) != (32'hFFFFFFFF)) if (check) $stop; + if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop; + end + end + + //============================================================ + + reg [119:0] W0592; //=000000000000000000000000000000 + reg [ 7:0] W0593; //=70 + always @(posedge clk) begin + if (cyc==1) begin + W0593 = (((8'h90)) * ((8'hFF))); + W0592 = 120'h000000000000000000000000000000; + end + end + always @(posedge clk) begin + if (cyc==2) begin + if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop; + end + end + + //============================================================ + + reg [127:0] WA1063 ; //=00000000000000000000000000000001 + reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF + reg [ 62:0] WA1065 ; //=0000000000000000 + reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001 + reg [ 34:0] WA1067 ; //=7FFFFFFFF + reg [111:0] WA1068; + + always @(check) begin + WA1067 = (~ (35'h0)); + WA1066 = (90'h00000000000000000000001); + WA1065 = (WA1066[89:27]); + WA1064 = (WA1067); + WA1063 = (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); + end + always @(posedge clk) begin + if (cyc==2) begin + if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; + end + end + + //============================================================ + + reg [127:0] WB1063 ; //=00000000000000000000000000000001 + reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF + reg [ 62:0] WB1065 ; //=0000000000000000 + reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001 + reg [ 34:0] WB1067 ; //=7FFFFFFFF + reg [111:0] WB1068; + + always @(posedge clk) begin + if (cyc==1) begin + WB1067 = (~ (35'h0)); + WB1066 = (90'h00000000000000000000001); + end + if (cyc==2) WB1065 <= (WB1066[89:27]); + if (cyc==3) WB1064 <= (WB1067); + if (cyc==4) WB1063 <= (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); + if (cyc==5) WB1068 <= (WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]); + end + always @(posedge clk) begin + if (cyc==9) begin + if (WB1068 != 112'h0) if (check) $stop; + if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; + end + end + + //============================================================ + + reg signed [ 60:0] WC0064 ; //=1FFFFFFFFFFFFFFF + reg signed [ 6:0] WC0065 ; //=00 + reg signed [ 62:0] WC0067 /*verilator public*/; //=33250A3BFFFFFFFF + + always @(check) begin + WC0064 = 61'sh1FFFFFFFFFFFFFFF; + WC0065 = 7'sh0; + if (((WC0064) >>> (WC0065)) != 61'sh1fffffffffffffff) if (check) $stop; + end + + //============================================================ + + reg signed [ 76:0] W0234 ; //=00000000000000000000 + reg signed [ 7:0] W0235 /*verilator public*/; //=B6 + always @(check) begin + W0235 = 8'shb6; + W0234 = ((77'sh0001ffffffffffffffff) >>> (W0235)); + if ((W0234) != 77'sh0) if (check) $stop; + end + + //============================================================ + + reg signed [ 30:0] W0146 ; //=00000001 + always @(check) begin : Block71 + W0146 = (31'sh00000001); + if ((W0146 >>> 6'sh3f) != 31'sh0) if (check) $stop; + end + + //============================================================ + + reg signed [ 54:0] W0857 /*verilator public*/; //=7FFFFFFFFFFFFF + + always @(check) begin : Block405 + W0857 = 55'sh7fffffffffffff; + if ((63'sh7fffffffffffffff >>> (W0857[54:54] ? 7'sh56 : 7'sh7f)) != 63'sh7fffffffffffffff) if (check) $stop; + end + + //============================================================ + + always @(posedge clk) begin + if ((((122'sh3ffffffffffffffd3e48e0900000001 >>> 8'shff) >>> 8'b1) ) != 122'sh3ffffffffffffffffffffffffffffff) if (check) $stop; + if (((95'sh7fff_ffff_ffffffff_ffffffff < 95'sh4a76_3d8b_0f4e3995_1146e342) != 1'h0)) if (check) $stop; + end + + //============================================================ + + reg signed [ 82:0] W0226 ; //=47A4301EE3FB4133EE3DA + + always @* begin : Block144 + W0226 = 83'sh47A4301EE3FB4133EE3DA; + if ((W0226 >>> 8'sh1a) != 83'sh7ffffff1e90c07b8fed04) if (check) $stop; + end + + //============================================================ + + reg signed [ 68:0] W0792 /*verilator public*/; //=169351569551247E0C + reg signed [ 68:0] W0793 ; //=1FFFFFFFFF4EB1A91A + + always @(posedge clk) begin + W0793 <= 69'sh1f_ffffffff_4eb1a91a; + W0792 <= (W0793 * 69'sh1F_0E989F3E_F15F509E); + if (W0792 != 69'sh16_93515695_51247E0C) if (check) $stop; + end + + //============================================================ + + reg signed [ 2:0] DW0515 /*verilator public*/; //=7 + + always @(posedge clk) begin + DW0515 <= 3'sh7; + if ($signed({62'h0,DW0515[1'h1]}) != 63'sh0000000000000001) if (check) $stop; + end + + //============================================================ + + reg signed [ 62:0] W0753 ; //=004E20004ED93E26 + reg [ 2:0] W0772 /*verilator public*/; //=7 + + always @(posedge clk) begin + W0753 <= 63'sh004E20004ED93E26; //(63'sh7fffffffffffffff + (63'sh464eac8c4ed93e27 & (63'sh08cf6243ffffffff))); + W0772 <= 3'h7; + if ((W0772[(W0753 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; + if ((W0772[(63'sh004E20004ED93E26 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; + end + + //============================================================ + + reg [ 98:0] W1027 ; //=7FFFFFFFFFFFFFFFFFFFFFFFF + always @(posedge clk) begin + W1027 <= ~99'h0; + // verilator lint_off CMPCONST + if (((1'sb1 < (95'sh7fffffffffffffffffffffff >= 95'sh09deb904ffffffffe062d44c))) != 1'h0) if (check) $stop; + // verilator lint_on CMPCONST + end + + //============================================================ + + reg signed [ 5:0] W123_is_3f ; //=3F + + always @(posedge clk) begin + W123_is_3f <= 6'sh3f; + end + always @(posedge clk) begin + if (((~ ((32'sh088d1bcb) <<< W123_is_3f)) >>> 6'sh3f) != 32'shffffffff) if (check) $stop; + end + + //============================================================ + + reg signed [105: 0] W0032 /*verilator public*/; //=106'h3ff0000000100000000bd597bb1 + always @(check) begin : Block237 + W0032 = 106'sh3ff0000000100000000bd597bb1; + if ((106'sh1ca0000000000000000b96b8dc2 / 106'sh3ff0000000100000000bd597bb1) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; + if ((106'sh1ca0000000000000000b96b8dc2 / W0032) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; + end + + //============================================================ + + reg signed [ 83: 0] W0024 ; //=84'h0000000000000e1fe9094 + reg signed [ 83: 0] W0025 ; //=84'h0f66afffffffe308b3d7c + always @(posedge clk) begin + W0024 <= 84'h0000000000000e1fe9094; + W0025 <= 84'h0f66afffffffe308b3d7c; + if ((W0024 % W0025) != 84'sh0000000000000e1fe9094) if (check) $stop; + end + + //============================================================ + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==18) begin + check <= 1'b1; + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_vliw.v b/SVIncCompil/Testcases/Verilator/t_math_vliw.v new file mode 100644 index 0000000..98821cd --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_vliw.v
@@ -0,0 +1,103 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [7:0] crc; + reg [223:0] sum; + + wire [255:0] mglehy = {32{~crc}}; + wire [215:0] drricx = {27{crc}}; + wire [15:0] apqrli = {2{~crc}}; + wire [2:0] szlfpf = crc[2:0]; + wire [15:0] dzosui = {2{crc}}; + wire [31:0] zndrba = {16{crc[1:0]}}; + wire [223:0] bxiouf; + + vliw vliw ( + // Outputs + .bxiouf (bxiouf), + // Inputs + .mglehy (mglehy[255:0]), + .drricx (drricx[215:0]), + .apqrli (apqrli[15:0]), + .szlfpf (szlfpf[2:0]), + .dzosui (dzosui[15:0]), + .zndrba (zndrba[31:0])); + + always @ (posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==0) begin + // Setup + crc <= 8'hed; + sum <= 224'h0; + end + else if (cyc<90) begin + //$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf); + sum <= {sum[222:0],sum[223]} ^ bxiouf; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum); + if (crc !== 8'b01110000) $stop; + if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module vliw ( + input[255:0] mglehy, + input[215:0] drricx, + input[15:0] apqrli, + input[2:0] szlfpf, + input[15:0] dzosui, + input[31:0] zndrba, + output wire [223:0] bxiouf + ); + + wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]}) + | ({29{apqrli}} & {mglehy[247:0], drricx}); + wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128]) + | ({21{dzosui}} & zhknfc[335:0]); + wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000}; + wire [223:0] rzyeut = viuvoc[335:112]; + assign bxiouf = {rzyeut[7:0], + rzyeut[15:8], + rzyeut[23:16], + rzyeut[31:24], + rzyeut[39:32], + rzyeut[47:40], + rzyeut[55:48], + rzyeut[63:56], + rzyeut[71:64], + rzyeut[79:72], + rzyeut[87:80], + rzyeut[95:88], + rzyeut[103:96], + rzyeut[111:104], + rzyeut[119:112], + rzyeut[127:120], + rzyeut[135:128], + rzyeut[143:136], + rzyeut[151:144], + rzyeut[159:152], + rzyeut[167:160], + rzyeut[175:168], + rzyeut[183:176], + rzyeut[191:184], + rzyeut[199:192], + rzyeut[207:200], + rzyeut[215:208], + rzyeut[223:216]}; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_math_width.v b/SVIncCompil/Testcases/Verilator/t_math_width.v new file mode 100644 index 0000000..114996a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_math_width.v
@@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (); + + // See also t_lint_width + + parameter A_ONE = '1; + // verilator lint_off WIDTH + parameter [3:0] A_W4 = A_ONE; + // verilator lint_on WIDTH + initial begin + if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop; + if ($bits(A_W4) != 4) $stop; + if (A_W4 != 4'b0001) $stop; + end + + b #(.B_WIDTH(48)) b (); + + reg [4:0] c; + integer c_i; + initial begin + c_i = 3; + c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax + if (c != 5'b1000) $stop; + end + + localparam D_TT = 32'd23; + localparam D_SIX = 6; + // verilator lint_off WIDTH + localparam [5:0] D_SUB = D_TT - D_SIX; + // verilator lint_on WIDTH + initial begin + if (D_SUB != 17) $stop; + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + + +module b; + parameter B_WIDTH = 1; + localparam B_VALUE0 = {B_WIDTH{1'b0}}; + localparam B_VALUE1 = {B_WIDTH{1'b1}}; + reg [47:0] b_val; + initial begin + b_val = B_VALUE0; + if (b_val != 48'b0) $stop; + b_val = B_VALUE1; + if (b_val != ~48'b0) $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem.v b/SVIncCompil/Testcases/Verilator/t_mem.v new file mode 100644 index 0000000..4da2ad5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem.v
@@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + // [16] is SV syntax for [0:15] + reg [7:0] memory8_16 [16]; + + reg m_we; + reg [3:1] m_addr; + reg [15:0] m_data; + + always @ (posedge clk) begin + // Load instructions from cache + memory8_16[{m_addr,1'd0}] <= 8'hfe; + if (m_we) begin + {memory8_16[{m_addr,1'd1}], + memory8_16[{m_addr,1'd0}]} <= m_data; + end + end + + reg [7:0] memory8_16_4; + reg [7:0] memory8_16_5; + // Test complicated sensitivity lists + always @ (memory8_16[4][7:1] or memory8_16[5]) begin + memory8_16_4 = memory8_16[4]; + memory8_16_5 = memory8_16[5]; + end + + always @ (posedge clk) begin + m_we <= 0; + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + m_we <= 1'b1; + m_addr <= 3'd2; + m_data <= 16'h55_44; + end + if (cyc==2) begin + m_we <= 1'b1; + m_addr <= 3'd3; + m_data <= 16'h77_66; + end + if (cyc==3) begin + m_we <= 0; // Check we really don't write this + m_addr <= 3'd3; + m_data <= 16'h0bad; + end + if (cyc==5) begin + if (memory8_16_4 != 8'h44) $stop; + if (memory8_16_5 != 8'h55) $stop; + if (memory8_16[6] != 8'hfe) $stop; + if (memory8_16[7] != 8'h77) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_banks.v b/SVIncCompil/Testcases/Verilator/t_mem_banks.v new file mode 100644 index 0000000..27eb695 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_banks.v
@@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [5:0] addr; + + parameter BANKS = 6; + parameter ROWS = 8; + + wire [2:0] bank; + wire [2:0] row; + + integer a; + integer used[BANKS][ROWS]; + + // Test loop + initial begin + for (a = 0; a < BANKS*ROWS; ++a) begin + addr[5:0] = a[5:0]; + hash (addr, bank, row); + used [bank][row] ++; + if (used [bank][row] > 1) begin + $write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row); + end + end + $write("*-* All Finished *-*\n"); + $finish; + end + + task hash (input [5:0] addr, + output [2:0] bank, + output [2:0] row); + + reg [1:0] third; + reg [1:0] fourth; + + third = {addr[5], addr[4]}; + fourth = {addr[3] ^ addr[1], + addr[2] ^ addr[0]}; + + case (third) + 2'h0: + case (fourth) + 2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end + 2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end + 2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end + 2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end + endcase + + 2'h1: + case (fourth) + 2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end + 2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end + 2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end + 2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end + endcase + + 2'h2: + case (fourth) + 2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end + 2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end + 2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end + 2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end + endcase + + 2'h3: $stop; + endcase + endtask +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_cond.v b/SVIncCompil/Testcases/Verilator/t_mem_cond.v new file mode 100644 index 0000000..5583400 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_cond.v
@@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + b, + // Inputs + clk, en, a + ); + + // bug1017 + + input clk; + + input en; + input a[1]; + output logic b[1]; + + always_ff @ (posedge clk) begin + b <= en ? a : b; + end + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_fifo.v b/SVIncCompil/Testcases/Verilator/t_mem_fifo.v new file mode 100644 index 0000000..12beb06 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_fifo.v
@@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + + wire [65:0] outData; // From fifo of fifo.v + wire [15:0] inData = crc[15:0]; + wire [1:0] inWordPtr = crc[17:16]; + wire wrEn = crc[20]; + wire [1:0] wrPtr = crc[33:32]; + wire [1:0] rdPtr = crc[34:33]; + + fifo fifo ( + // Outputs + .outData (outData[65:0]), + // Inputs + .clk (clk), + .inWordPtr (inWordPtr[1:0]), + .inData (inData[15:0]), + .rdPtr (rdPtr), + .wrPtr (wrPtr), + .wrEn (wrEn)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc==90) begin + if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; + end + else if (cyc==91) begin + if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; + end + else if (cyc==92) begin + if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; + end + else if (cyc==93) begin + if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; + end + else if (cyc==94) begin + if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module fifo (/*AUTOARG*/ + // Outputs + outData, + // Inputs + clk, inWordPtr, inData, wrPtr, rdPtr, wrEn + ); + + parameter fifoDepthLog2 = 1; + parameter fifoDepth = 1<<fifoDepthLog2; + +`define PTRBITS (fifoDepthLog2+1) +`define PTRBITSM1 fifoDepthLog2 +`define PTRBITSM2 (fifoDepthLog2-1) + + input clk; + input [1:0] inWordPtr; + input [15:0] inData; + input [`PTRBITSM1:0] wrPtr; + input [`PTRBITSM1:0] rdPtr; + + output [65:0] outData; + input wrEn; + + reg [65:0] outData; + + // verilator lint_off VARHIDDEN + // verilator lint_off LITENDIAN + reg [65:0] fifo[0:fifoDepth-1]; + // verilator lint_on LITENDIAN + // verilator lint_on VARHIDDEN + + //reg [65:0] temp; + + always @(posedge clk) begin + //$write ("we=%x PT=%x ID=%x D=%x\n", wrEn, wrPtr[`PTRBITSM2:0], {1'b0,~inWordPtr,4'b0}, inData[15:0]); + if (wrEn) begin + fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0]; + // Equivelent to: + //temp = fifo[ wrPtr[`PTRBITSM2:0] ]; + //temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0]; + //fifo[ wrPtr[`PTRBITSM2:0] ] <= temp; + end + outData <= fifo[rdPtr[`PTRBITSM2:0]]; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_file.v b/SVIncCompil/Testcases/Verilator/t_mem_file.v new file mode 100644 index 0000000..9d8af04 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_file.v
@@ -0,0 +1,165 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire r1_en /*verilator public*/ = crc[12]; + wire [1:0] r1_ad /*verilator public*/ = crc[9:8]; + wire r2_en /*verilator public*/ = 1'b1; + wire [1:0] r2_ad /*verilator public*/ = crc[11:10]; + wire w1_en /*verilator public*/ = crc[5]; + wire [1:0] w1_a /*verilator public*/ = crc[1:0]; + wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}}; + wire w2_en /*verilator public*/ = crc[4]; + wire [1:0] w2_a /*verilator public*/ = crc[3:2]; + wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] r1_d_d2r; // From file of file.v + wire [63:0] r2_d_d2r; // From file of file.v + // End of automatics + + file file (/*AUTOINST*/ + // Outputs + .r1_d_d2r (r1_d_d2r[63:0]), + .r2_d_d2r (r2_d_d2r[63:0]), + // Inputs + .clk (clk), + .r1_en (r1_en), + .r1_ad (r1_ad[1:0]), + .r2_en (r2_en), + .r2_ad (r2_ad[1:0]), + .w1_en (w1_en), + .w1_a (w1_a[1:0]), + .w1_d (w1_d[63:0]), + .w2_en (w2_en), + .w2_a (w2_a[1:0]), + .w2_d (w2_d[63:0])); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + // We've manually verified all X's are out of the design by this point + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h5e9ea8c33a97f81e) $stop; + $finish; + end + end + +endmodule + +module file (/*AUTOARG*/ + // Outputs + r1_d_d2r, r2_d_d2r, + // Inputs + clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d + ); + + input clk; + input r1_en; + input [1:0] r1_ad; + output [63:0] r1_d_d2r; + input r2_en; + input [1:0] r2_ad; + output [63:0] r2_d_d2r; + input w1_en; + input [1:0] w1_a; + input [63:0] w1_d; + input w2_en; + input [1:0] w2_a; + input [63:0] w2_d; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + // End of automatics + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [63:0] r1_d_d2r; + reg [63:0] r2_d_d2r; + // End of automatics + + // Writes + wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a)); + wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a)); + + wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d; + wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d; + wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d; + wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d; + + wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe; + + // Storage + reg [63:0] m_rg0_r; + reg [63:0] m_rg1_r; + reg [63:0] m_rg2_r; + reg [63:0] m_rg3_r; + + always @ (posedge clk) begin + if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat; + if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat; + if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat; + if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat; + end + + // Reads + reg [1:0] m_r1_ad_d1r; + reg [1:0] m_r2_ad_d1r; + reg [1:0] m_ren_d1r; + + always @ (posedge clk) begin + if (r1_en) m_r1_ad_d1r <= r1_ad; + if (r2_en) m_r2_ad_d1r <= r2_ad; + m_ren_d1r <= {r2_en, r1_en}; + end + + // Scheme1: shift... + wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r); + // Scheme2: bit mask + reg [3:0] m_r2_onehot_d1; + always @* begin + m_r2_onehot_d1 = 4'd0; + m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1; + end + + wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) | + ({64{m_r1_onehot_d1[1]}} & m_rg1_r) | + ({64{m_r1_onehot_d1[2]}} & m_rg2_r) | + ({64{m_r1_onehot_d1[3]}} & m_rg3_r)); + + wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) | + ({64{m_r2_onehot_d1[1]}} & m_rg1_r) | + ({64{m_r2_onehot_d1[2]}} & m_rg2_r) | + ({64{m_r2_onehot_d1[3]}} & m_rg3_r)); + + always @ (posedge clk) begin + if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1; + if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_first.v b/SVIncCompil/Testcases/Verilator/t_mem_first.v new file mode 100644 index 0000000..f994375 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_first.v
@@ -0,0 +1,106 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer _mode; initial _mode = 0; + + // verilator lint_off LITENDIAN + reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM + reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM + reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM + reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM + reg [34:0] vec_wide; + // verilator lint_on LITENDIAN + + reg [31:0] wrd0 [15:0]; + wire [3:0] sel = 4'h3; + wire [31:0] selout = wrd0[sel]; + + // Must take LSBs into account in bit extract widths. + wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB + wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB + wire [3:0] sixfrom = 13; + wire [4:0] sixfrom2 = 16; + wire sixtext = sixt[sixfrom]; + wire sixtext2 = sixt2[sixfrom2]; + + // Non-power of 2 memory overwriting checks + reg [2:0] np2_mem [5:0] /*verilator public*/; + reg [2:0] np2_guard [7:6] /*verilator public*/; + + integer i; + + always @ (posedge clk) begin + if (_mode!=0) begin + wrd0[0] = 32'h1; + // + for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR + mem_narrow[i] = i[7:0]; + mem_wide[i] = {i[7:0],70'hfeed}; + end + // + for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR + if (mem_narrow[i] !== i[7:0]) $stop; + if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop; + end + // + vec_wide <= 0; + // + np2_guard[6] = 0; + np2_guard[7] = 0; + // + $write("selout %b %b %b\n", selout, sixtext, sixtext2); + end + if (_mode == 1) begin + _mode <= 2; + // + i=0; + mem_dly_narrow[0] <= ~i[7:0]; + mem_dly_wide[0] <= {~i[7:0],70'hface}; + i=1; + mem_dly_narrow[i] <= ~i[7:0]; + mem_dly_wide[i] <= {~i[7:0],70'hface}; + // + for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR + // verilator lint_off width + np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB + // verilator lint_on width + if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop; + end + // verilator lint_off SELRANGE + if (np2_mem[6] !== np2_mem[7]) begin + $write("Mem[6]!=Mem[7] during randomize...\n"); + //$stop; // Random value, so this can happen + end + // verilator lint_on SELRANGE + //if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's + // + vec_wide[32:31] <= 2'b11; + vec_wide[34] <= 1'b1; + $display("%x",vec_wide); + end + if (_mode == 2) begin + _mode <= 3; + // + for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR + if (mem_dly_narrow[i] !== ~i[7:0]) $stop; + if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop; + end + // + //$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]); + if (vec_wide != {4'b101_1,31'd0}) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + _mode <= _mode + 1; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_func.v b/SVIncCompil/Testcases/Verilator/t_mem_func.v new file mode 100644 index 0000000..972dfe4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_func.v
@@ -0,0 +1,123 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [2:0] q; // From test of Test.v + // End of automatics + + Test test ( + // Outputs + .q (q[2:0]), + // Inputs + .clk (clk), + .reset_l (crc[0]), + .enable (crc[2]), + .q_var0 (crc[19:10]), + .q_var2 (crc[29:20]), + .q_var4 (crc[39:30]), + .q_var6 (crc[49:40]) + /*AUTOINST*/); + + // Aggregate outputs into a single result vector + wire [63:0] result = {61'h0,q}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'h58b162c58d6e35ba + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + + +module Test + ( + input clk, + input reset_l, + input enable, + + input [ 9:0] q_var0, + input [ 9:0] q_var2, + input [ 9:0] q_var4, + input [ 9:0] q_var6, + + output reg [2:0] q + ); + + reg [7:0] p1_r [6:0]; + + always @(posedge clk) begin + if (!reset_l) begin + p1_r[0] <= 'b0; + p1_r[1] <= 'b0; + p1_r[2] <= 'b0; + p1_r[3] <= 'b0; + p1_r[4] <= 'b0; + p1_r[5] <= 'b0; + p1_r[6] <= 'b0; + end + else if (enable) begin : pass1 + match(q_var0, q_var2, q_var4, q_var6); + end + end + + // verilator lint_off WIDTH + always @(posedge clk) begin : l + reg [10:0] bd; + reg [3:0] idx; + + q = 0; + bd = 0; + for (idx=0; idx<7; idx=idx+1) begin + q = idx+1; + bd = bd + p1_r[idx]; + end + end + + + task match; + input [9:0] p0, p1, p2, p3; + reg [9:0] p[3:0]; + begin + p[0] = p0; + p[1] = p1; + p[2] = p2; + p[3] = p3; + p1_r[0] <= p[0]; + p1_r[1] <= p[1]; + end + endtask +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_iforder.v b/SVIncCompil/Testcases/Verilator/t_mem_iforder.v new file mode 100644 index 0000000..3a66900 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_iforder.v
@@ -0,0 +1,102 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [31:0] sum; + + wire [15:0] out0; + wire [15:0] out1; + wire [15:0] inData = crc[15:0]; + wire wr0a = crc[16]; + wire wr0b = crc[17]; + wire wr1a = crc[18]; + wire wr1b = crc[19]; + + fifo fifo ( + // Outputs + .out0 (out0[15:0]), + .out1 (out1[15:0]), + // Inputs + .clk (clk), + .wr0a (wr0a), + .wr0b (wr0b), + .wr1a (wr1a), + .wr1b (wr1b), + .inData (inData[15:0])); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 32'h0; + end + else if (cyc>10 && cyc<90) begin + sum <= {sum[30:0],sum[31]} ^ {out1, out0}; + end + else if (cyc==99) begin + if (sum !== 32'he8bbd130) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module fifo (/*AUTOARG*/ + // Outputs + out0, out1, + // Inputs + clk, wr0a, wr0b, wr1a, wr1b, inData + ); + + input clk; + input wr0a; + input wr0b; + input wr1a; + input wr1b; + input [15:0] inData; + + output [15:0] out0; + output [15:0] out1; + + reg [15:0] mem [1:0]; + reg [15:0] memtemp2 [1:0]; + reg [15:0] memtemp3 [1:0]; + + assign out0 = {mem[0] ^ memtemp2[0]}; + assign out1 = {mem[1] ^ memtemp3[1]}; + + always @(posedge clk) begin + // These mem assignments must be done in order after processing + if (wr0a) begin + memtemp2[0] <= inData; + mem[0] <= inData; + end + if (wr0b) begin + memtemp3[0] <= inData; + mem[0] <= ~inData; + end + if (wr1a) begin + memtemp3[1] <= inData; + mem[1] <= inData; + end + if (wr1b) begin + memtemp2[1] <= inData; + mem[1] <= ~inData; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_multi_io.v b/SVIncCompil/Testcases/Verilator/t_mem_multi_io.v new file mode 100644 index 0000000..5c1c096 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_multi_io.v
@@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic [7:0] arr [7:0]; + logic [7:0] arri [7:0]; + + has_array am1 (.clk(clk), .arri(arr), .arro(arri)); + + integer cyc; initial cyc = 0; + + initial begin + for (int i = 0; i < 8; i++) begin + arr[i] = 0; + end + end + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5 && arri[1] != 8) begin + $stop; + end + for (int i = 0; i < 7; ++i) begin + arr[i+1] <= arr[i]; + end + arr[0] <= arr[0] + 1; + end + +endmodule : t + +module has_array ( + input clk, + input logic [7:0] arri [7:0], + output logic [7:0] arro [7:0] + ); + + integer cyc; initial cyc = 0; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (arri[0] == 10 && cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + always @(posedge clk) begin + for (integer i = 0; i < 7; ++i) begin + arro[i+1] <= arro[i]; + end + arro[0] = arro[0] + 2; + end + +endmodule : has_array
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_multi_io2.v b/SVIncCompil/Testcases/Verilator/t_mem_multi_io2.v new file mode 100644 index 0000000..33d8cfa --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_multi_io2.v
@@ -0,0 +1,37 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks + +module t (/*AUTOARG*/ + // Outputs + o3, o34, o345, + // Inputs + i3, i34, i345 + ); + input [15:0] i3; + output wire [15:0] o3; + input [15:0] i34 [3:0]; + output wire [15:0] o34 [3:0]; + input [15:0] i345 [3:0][4:0]; + output wire [15:0] o345 [3:0][4:0]; + + sub sub (.*); +endmodule + +module sub (/*AUTOARG*/ + // Outputs + o3, o34, o345, + // Inputs + i3, i34, i345 + ); + input [15:0] i3; + output wire [15:0] o3; + input [15:0] i34 [3:0]; + output wire [15:0] o34 [3:0]; + input [15:0] i345 [3:0][4:0]; + output wire [15:0] o345 [3:0][4:0]; + + assign o3 = i3; + assign o34 = i34; + assign o345 = i345; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_multi_io3.v b/SVIncCompil/Testcases/Verilator/t_mem_multi_io3.v new file mode 100644 index 0000000..76878fb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_multi_io3.v
@@ -0,0 +1,52 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013. + +module t + ( + input logic clk, + input logic daten, + input logic [8:0] datval, + output logic signed [3:0][3:0][35:0] datao + ); + + logic signed [3:0][3:0][3:0][8:0] datat; + + genvar i; + generate + for (i=0; i<4; i++)begin + testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i])); + end + endgenerate + + genvar j; + generate + for (i=0; i<4; i++) begin + for (j=0; j<4; j++) begin + always_comb datat[i][j][0] = daten ? 9'h0 : datval; + always_comb datat[i][j][1] = daten ? 9'h1 : datval; + always_comb datat[i][j][2] = daten ? 9'h2 : datval; + always_comb datat[i][j][3] = daten ? 9'h3 : datval; + end + end + endgenerate +endmodule + +module testio + ( + input clk, + input logic signed [3:0] [3:0] [8:0] arr3d_in, + output logic signed [3:0] [35:0] arr2d_out + ); + logic signed [3:0] [35:0] ar2d_out_pre; + + always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + + always_ff @(posedge clk) begin + if (clk) + arr2d_out <= ar2d_out_pre; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_multi_ref_bad.v b/SVIncCompil/Testcases/Verilator/t_mem_multi_ref_bad.v new file mode 100644 index 0000000..099640e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_multi_ref_bad.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/); + reg dimn; + reg [1:0] dim0; + reg [1:0] dim1 [1:0]; + reg [1:0] dim2 [1:0][1:0]; + reg dim0nv[1:0]; + + initial begin + dimn[1:0] = 0; // Bad: Not ranged + dim0[1][1] = 0; // Bad: Not arrayed + dim1[1][1][1] = 0; // Bad: Not arrayed to right depth + dim2[1][1][1] = 0; // OK + dim2[0 +: 1][1] = 0; // Bad: Range on non-bits + dim2[1 : 0][1] = 0; // Bad: Range on non-bits + dim2[1][1:0] = 0; // Bad: Bitsel too soon + dim0nv[1:0] = 0; // Bad: Not vectored + dim0nv[1][1] = 0; // Bad: Not arrayed to right depth + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_multidim.v b/SVIncCompil/Testcases/Verilator/t_mem_multidim.v new file mode 100644 index 0000000..4cdbf80 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_multidim.v
@@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off LITENDIAN + // verilator lint_off BLKANDNBLK + // 3 3 4 + reg [71:0] memw [2:0][1:3][5:2]; + reg [7:0] memn [2:0][1:3][5:2]; + // verilator lint_on BLKANDNBLK + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [71:0] wide; + reg [7:0] narrow; + reg [1:0] index0; + reg [1:0] index1; + reg [2:0] index2; + integer i0,i1,i2; + + integer imem[2:0][1:3]; + reg [2:0] cstyle[2]; + // verilator lint_on LITENDIAN + + initial begin + for (i0=0; i0<3; i0=i0+1) begin + for (i1=1; i1<4; i1=i1+1) begin + imem[i0[1:0]] [i1[1:0]] = i1; + for (i2=2; i2<6; i2=i2+1) begin + memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]}; + memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001; + end + end + end + end + + reg [71:0] wread; + reg wreadb; + + always @ (posedge clk) begin + //$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + narrow <= 8'h0; + wide <= 72'h0; + index0 <= 2'b0; + index1 <= 2'b0; + index2 <= 3'b0; + end + else if (cyc<90) begin + index0 <= crc[1:0]; + index1 <= crc[3:2]; + index2 <= crc[6:4]; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + + // We never read past bounds, or get unspecific results + // We also never read lowest indexes, as writing outside of range may corrupt them + if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin + narrow <= ({narrow[6:0], narrow[7]^narrow[0]} + ^ {memn[index0][index1][index2]}); + wread = memw[index0][index1][index2]; + wreadb = memw[index0][index1][index2][2]; + wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); + //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); + end + // We may write past bounds of memory + memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; + memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; + memw[index0][index1][index2] <= {~crc[7:0],crc}; + //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); + cstyle[cyc[0]] <= cyc[2:0]; + if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop; + end + else if (cyc==90) begin + memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; + end + else if (cyc==91) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide); + if (crc != 64'h65e3bddcd9bc2750) $stop; + if (narrow != 8'hca) $stop; + if (wide != 72'h4edafed31ba6873f73) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_multiwire.v b/SVIncCompil/Testcases/Verilator/t_mem_multiwire.v new file mode 100644 index 0000000..016b141 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_multiwire.v
@@ -0,0 +1,86 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off LITENDIAN + wire [7:0] array [2:0][1:3]; + wire [7:0] arrayNoColon [2][3]; + // verilator lint_on LITENDIAN + + integer cyc; initial cyc=0; + integer i0,i1,i2; + genvar g0,g1,g2; + + generate + for (g0=0; g0<3; g0=g0+1) begin + for (g1=1; g1<4; g1=g1+1) begin + inst inst (.q(array[g0[1:0]] [g1[1:0]]), + .cyc(cyc), + .i0(g0[1:0]), + .i1(g1[1:0])); + end + end + endgenerate + + always @ (posedge clk) begin + //$write("cyc==%0d\n",cyc); + cyc <= cyc + 1; + if (cyc==2) begin + if (array[2][1] !== 8'h92) $stop; + for (i0=0; i0<3; i0=i0+1) begin + for (i1=1; i1<4; i1=i1+1) begin + //$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]); + if (array[i0[1:0]] [i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop; + end + end + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module inst (/*AUTOARG*/ + // Outputs + q, + // Inputs + cyc, i0, i1 + ); + output reg [7:0] q; + input [31:0] cyc; + input [1:0] i0; + input [1:0] i1; + + inst2 inst2 (/*AUTOINST*/ + // Inputs + .cyc (cyc[31:0]), + .i0 (i0[1:0]), + .i1 (i1[1:0])); + + always @* begin + q = {i0, i1, cyc[3:0]}; + end +endmodule + +module inst2 (/*AUTOARG*/ + // Inputs + cyc, i0, i1 + ); + /*verilator no_inline_module*/ // So we'll get a CELL under a GENFOR, without inlining + input [31:0] cyc; + input [1:0] i0; + input [1:0] i1; + initial begin + if (cyc==32'h1) $write("[%0t] i0=%d i1=%d\n", $time, i0, i1); + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_packed.v b/SVIncCompil/Testcases/Verilator/t_mem_packed.v new file mode 100644 index 0000000..14b2fa1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_packed.v
@@ -0,0 +1,179 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + //Simple debug: + //wire [1:1] wir_a [3:3] [2:2]; //11 + //logic [1:1] log_a [3:3] [2:2]; //12 + //wire [3:3] [2:2] [1:1] wir_p; //13 + //logic [3:3] [2:2] [1:1] log_p; //14 + + integer cyc; initial cyc = 0; +`ifdef iverilog + reg [7:0] arr [3:0]; + wire [7:0] arr_w [3:0]; +`else + reg [3:0] [7:0] arr; + wire [3:0] [7:0] arr_w; +`endif + reg [7:0] sum; + reg [7:0] sum_w; + integer i0; + + initial begin + for (i0=0; i0<5; i0=i0+1) begin + arr[i0] = 1 << (i0[1:0]*2); + end + end + + assign arr_w = arr; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + sum <= 0; + sum_w <= 0; + end + else if (cyc >= 10 && cyc < 14) begin + sum <= sum + arr[cyc-10]; + + sum_w <= sum_w + arr_w[cyc-10]; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum); + if (sum != 8'h55) $stop; + if (sum != sum_w) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // Test ordering of packed dimensions + logic [31:0] data_out; + logic [31:0] data_out2; + logic [0:0] [2:0] [31:0] data_in; + logic [31:0] data_in2 [0:0] [2:0]; + assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2]; + assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2]; + + logic [31:0] last_data_out; + always @ (posedge clk) begin + if (cyc <= 2) begin + data_in[0][0] <= 0; + data_in[0][1] <= 0; + data_in[0][2] <= 0; + data_in2[0][0] <= 0; + data_in2[0][1] <= 0; + data_in2[0][2] <= 0; + end + else if (cyc > 2 && cyc < 99) begin + data_in[0][0] <= data_in[0][0] + 1; + data_in[0][1] <= data_in[0][1] + 1; + data_in[0][2] <= data_in[0][2] + 1; + data_in2[0][0] <= data_in2[0][0] + 1; + data_in2[0][1] <= data_in2[0][1] + 1; + data_in2[0][2] <= data_in2[0][2] + 1; + last_data_out <= data_out; +`ifdef TEST_VERBOSE + $write("data_out %0x %0x\n", data_out, last_data_out); +`endif + if (cyc > 4 && data_out != last_data_out + 3) $stop; + if (cyc > 4 && data_out != data_out2) $stop; + end + end + + // Test for mixed implicit/explicit dimensions and all implicit packed + bit [3:0][7:0][1:0] vld [1:0][1:0]; + bit [3:0][7:0][1:0] vld2; + + // There are specific nodes for Or, Xor, Xnor and And + logic vld_or; + logic vld2_or; + assign vld_or = |vld[0][0]; + assign vld2_or = |vld2; + + logic vld_xor; + logic vld2_xor; + assign vld_xor = ^vld[0][0]; + assign vld2_xor = ^vld2; + + logic vld_xnor; + logic vld2_xnor; + assign vld_xnor = ~^vld[0][0]; + assign vld2_xnor = ~^vld2; + + logic vld_and; + logic vld2_and; + assign vld_and = &vld[0][0]; + assign vld2_and = &vld2; + + // Bit reductions should be cloned, other unary operations should clone the + // entire assign. + bit [3:0][7:0][1:0] not_lhs; + bit [3:0][7:0][1:0] not_rhs; + assign not_lhs = ~not_rhs; + + // Test an AstNodeUniop that shouldn't be expanded + bit [3:0][7:0][1:0] vld2_inv; + assign vld2_inv = ~vld2; + + initial begin + for (int i=0; i<4; i=i+2) begin + for (int j=0; j<8; j=j+2) begin + vld[0][0][i][j] = 2'b00; + vld[0][0][i+1][j+1] = 2'b00; + vld2[i][j] = 2'b00; + vld2[i+1][j+1] = 2'b00; + not_rhs[i][j] = i[1:0]; + not_rhs[i+1][j+1] = i[1:0]; + end + end + end + + + logic [3:0] expect_cyc; initial expect_cyc = 'd15; + + always @(posedge clk) begin + expect_cyc <= expect_cyc + 1; + for (int i=0; i<4; i=i+1) begin + for (int j=0; j<8; j=j+1) begin + vld[0][0][i][j] <= vld[0][0][i][j] + 1; + vld2[i][j] <= vld2[i][j] + 1; + if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; + not_rhs[i][j] <= not_rhs[i][j] + 1; + end + end + if (cyc % 8 == 0) begin + vld[0][0][0][0] <= vld[0][0][0][0] - 1; + vld2[0][0] <= vld2[0][0] - 1; + end + if (expect_cyc < 8 && !vld_xor) $stop; + else if (expect_cyc > 7 && vld_xor) $stop; + + if (expect_cyc < 8 && vld_xnor) $stop; + else if (expect_cyc > 7 && !vld_xnor) $stop; + + if (expect_cyc == 15 && vld_or) $stop; + else if (expect_cyc == 11 && vld_or) $stop; + else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop; + + if (expect_cyc == 10 && !vld_and) $stop; + else if (expect_cyc == 14 && !vld_and) $stop; + else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop; + + if (vld_xor != vld2_xor) $stop; + if (vld_xnor != vld2_xnor) $stop; + if (vld_or != vld2_or) $stop; + if (vld_and != vld2_and) $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_packed_assign.v b/SVIncCompil/Testcases/Verilator/t_mem_packed_assign.v new file mode 100644 index 0000000..98613d8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_packed_assign.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + /* verilator lint_off WIDTH */ + + input clk; + + integer cyc; initial cyc = 0; + logic [31:0] arr_c; initial arr_c = 0; + logic [7:0] [3:0] arr; + + logic [31:0] arr2_c; initial arr2_c = 0; + logic [7:0] [3:0] arr2; + assign arr2_c = arr2; + + always @ (posedge clk) begin + cyc <= cyc + 1; + arr_c <= arr_c + 1; + arr2 <= arr2 + 1; +`ifdef TEST_VERBOSE + $write("cyc%0d c:%0x a0:%0x a1:%0x a2:%0x a3:%0x\n", cyc, arr_c, arr[0], arr[1], arr[2], arr[3]); +`endif + if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + /* verilator lint_on WIDTH */ + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_packed_bad.v b/SVIncCompil/Testcases/Verilator/t_mem_packed_bad.v new file mode 100644 index 0000000..28453ca --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_packed_bad.v
@@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc = 0; + + logic [1:0][27:0] ch01; + logic [1:0][27:0] ch02; + logic [1:0][27:0] ch03; + logic [27:0] ch04[1:0]; + + /* verilator lint_off WIDTH */ + always @ (posedge clk) begin + // LHS is a 2D packed array, RHS is 1D packed or Const. Allowed now. + ch01 <= {{2{28'd4}}}; + ch02 <= {{2{cyc}}}; + ch03 <= 56'd0; + // LHS is 1D packed, 1D unpacked, this should never work. + ch04 <= 56'd0; + $display("ch01: %0x %0x", ch01[0], ch01[1]); + $display("ch01: %0x %0x", ch02[0], ch02[1]); + $display("ch01: %0x %0x", ch03[0], ch03[1]); + $display("ch01: %0x %0x", ch04[0], ch04[1]); + end + /* verilator lint_on WIDTH */ + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_shift.v b/SVIncCompil/Testcases/Verilator/t_mem_shift.v new file mode 100644 index 0000000..9d2ee0f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_shift.v
@@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + + integer i; + reg [63:0] mem [7:0]; + + always @ (posedge clk) begin + if (cyc==1) begin + for (i=0; i<8; i=i+1) begin + mem[i] <= 64'h0; + end + end + else begin + mem[0] <= crc; + for (i=1; i<8; i=i+1) begin + mem[i] <= mem[i-1]; + end + end + end + + wire [63:0] outData = mem[7]; + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc==90) begin + if (outData != 64'h1265e3bddcd9bc27) $stop; + end + else if (cyc==91) begin + if (outData != 64'h24cbc77bb9b3784e) $stop; + end + else if (cyc==92) begin + end + else if (cyc==93) begin + end + else if (cyc==94) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_slice.v b/SVIncCompil/Testcases/Verilator/t_mem_slice.v new file mode 100644 index 0000000..8181517 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_slice.v
@@ -0,0 +1,123 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic use_AnB; + logic [1:0] active_command [8:0]; + logic [1:0] command_A [8:0]; + logic [1:0] command_B [8:0]; + + logic [1:0] active_command2 [8:0]; + logic [1:0] command_A2 [8:0]; + logic [1:0] command_B2 [8:0]; + + logic [1:0] active_command3 [1:0][2:0][3:0]; + logic [1:0] command_A3 [1:0][2:0][3:0]; + logic [1:0] command_B3 [1:0][2:0][3:0]; + + logic [2:0] use_A4nB4; + logic [8:0][1:0] active_command4; + logic [8:0][1:0] command_A4; + logic [8:0][1:0] command_B4; + + logic [8:0] pipe1 [7:0]; + logic [8:0] pipe1_input; + + integer cyc; + + assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0]; + assign active_command2 = (use_AnB) ? command_A2 : command_B2; + // Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing + assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0]; + + // Check we can cope with things other than packed arrays + assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4; + + always @ (posedge clk) begin + pipe1_input <= pipe1_input + 1; + pipe1[0] <= pipe1_input; + pipe1[7:1] <= pipe1[6:0]; + end + + logic [3:0][13:0] iq_read_data [15:0]; + logic [3:0][13:0] iq_data; + logic [3:0] sel; + + assign iq_data = iq_read_data[sel]; + + always @ (posedge clk) begin + sel = sel + 1; + end + + initial begin + cyc = 0; + use_AnB = 0; + for (int i = 0; i < 7; ++i) begin + command_A[i] = 2'b00; + command_B[i] = 2'b11; + command_A2[i] = 2'b00; + command_B2[i] = 2'b11; + pipe1_input = 9'b0; + end + for (int i = 0; i < 2; ++i) begin + for (int j = 0; j < 3; ++j) begin + for (int k = 0; k < 4; ++k) begin + command_A3[i][j][k] = 2'b00; + command_B3[i][j][k] = 2'b11; + end + end + end + end + + always @ (posedge clk) begin + use_AnB <= ~use_AnB; + cyc <= cyc + 1; + if (use_AnB) begin + if (active_command[3] != 2'b00) begin + $stop; + end + if (active_command2[3] != 2'b00) begin + $stop; + end + if (active_command3[0][1][2] != 2'b00) begin + $stop; + end + end + if (!use_AnB) begin + if (active_command[3] != 2'b11) begin + $stop; + end + if (active_command2[3] != 2'b11) begin + $stop; + end + end + end + + logic [8:0] last_pipe; + always @(posedge clk) begin + if (cyc < 3) begin + last_pipe <= pipe1[0]; + end + else begin + if (last_pipe + 1 != pipe1[0]) begin + $stop; + end + else begin + last_pipe <= pipe1[0]; + end + end + if (cyc > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule : t
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_slice_bad.v b/SVIncCompil/Testcases/Verilator/t_mem_slice_bad.v new file mode 100644 index 0000000..f14bc22 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_slice_bad.v
@@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic use_AnB; + + logic [1:0] active_command [8:0]; + logic [1:0] command_A [8:0]; + logic [1:0] command_B [8:0]; + + logic [1:0] active_command2 [8:0]; + logic [1:0] command_A2 [7:0]; + logic [1:0] command_B2 [8:0]; + + logic [1:0] active_command3 [1:0][2:0][3:0]; + logic [1:0] command_A3 [1:0][2:0][3:0]; + logic [1:0] command_B3 [1:0][2:0][3:0]; + + logic [1:0] active_command4 [8:0]; + logic [1:0] command_A4 [7:0]; + + logic [1:0] active_command5 [8:0]; + logic [1:0] command_A5 [7:0]; + + // Single dimension assign + assign active_command[3:0] = (use_AnB) ? command_A[7:0] : command_B[7:0]; + // Assignment of entire arrays + assign active_command2 = (use_AnB) ? command_A2 : command_B2; + // Multi-dimension assign + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + + // Supported: Delayed assigment with RHS Var == LHS Var + logic [7:0] arrd [7:0]; + always_ff @(posedge clk) arrd[7:4] <= arrd[3:0]; + + // Unsupported: Non-delayed assigment with RHS Var == LHS Var + logic [7:0] arr [7:0]; + assign arr[7:4] = arr[3:0]; + + // Delayed assign + always @(posedge clk) begin + active_command4[7:0] <= command_A4[8:0]; + end + + // Combinational assign + always_comb begin + active_command5[8:0] = command_A5[7:0]; + end + +endmodule : t
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_slice_conc_bad.v b/SVIncCompil/Testcases/Verilator/t_mem_slice_conc_bad.v new file mode 100644 index 0000000..214fd64 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_slice_conc_bad.v
@@ -0,0 +1,118 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. +// +// bug354 + +typedef logic [5:0] data_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire rst; + data_t iii_in = crc[5:0]; + data_t jjj_in = crc[11:6]; + data_t iii_out; + data_t jjj_out; + logic [1:0] ctl0 = crc[63:62]; + + aaa aaa (.*); + + // Aggregate outputs into a single result vector + wire [63:0] result = {64'h0}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + rst <= 1'b0; + end + else if (cyc<10) begin + sum <= 64'h0; + rst <= 1'b1; + end + else if (cyc<90) begin + rst <= 1'b0; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module bbb + ( + output data_t ggg_out[1:0], + input data_t ggg_in [1:0], + input [1:0] [1:0] ctl, + + input logic clk, + input logic rst + ); + + genvar i; + + generate + for (i=0; i<2; i++) begin: PPP + always_ff @(posedge clk) begin + if (rst) begin + ggg_out[i] <= 6'b0; + end + else begin + if (ctl[i][0]) begin + if (ctl[i][1]) begin + ggg_out[i] <= ~ggg_in[i]; + end else begin + ggg_out[i] <= ggg_in[i]; + end + end + end + end + end + endgenerate + +endmodule + +module aaa + ( + input data_t iii_in, + input data_t jjj_in, + input [1:0] ctl0, + output data_t iii_out, + output data_t jjj_out, + input logic clk, + input logic rst + ); + + // Below is a bug; {} concat isn't used to make arrays + bbb bbb ( + .ggg_in ({jjj_in, iii_in}), + .ggg_out ({jjj_out, iii_out}), + .ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}), + .*); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_slice_dtype_bad.v b/SVIncCompil/Testcases/Verilator/t_mem_slice_dtype_bad.v new file mode 100644 index 0000000..71876b7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_slice_dtype_bad.v
@@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Alex Solomatnikov. + +typedef logic [$clog2(26+1)-1:0] way_cnt_t; + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input logic clk; + int cyc; + + //bug795 + way_cnt_t completed_cnt [31:0][1:0]; + way_cnt_t completed_cnt_dp [1:0]; + + assign completed_cnt_dp = completed_cnt[id]; + + always_ff @(posedge clk) begin + completed_cnt[id] <= completed_cnt_dp + 1; + end + + // bug796 + logic [4:0] id; + logic [39:0] way_mask; + logic [39:0] addr[31:0][1:0]; + always_ff @(posedge clk) begin + cyc <= cyc + 1; + id <= cyc[4:0]; + if (cyc==1) begin + way_mask <= '0; + id <= 1; + end + else if (cyc==2) begin + assert((addr[id] & way_mask) == 0); + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_slot.v b/SVIncCompil/Testcases/Verilator/t_mem_slot.v new file mode 100644 index 0000000..bc35f28 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_slot.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +`define RegDel 1 + +module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal); + + input Clk; + input [1:0] SlotIdx; + input BitToChange; + input BitVal; + input [1:0] SlotToReturn; + output [1:0] OutputVal; + + reg [1:0] Array[2:0]; + + always @(posedge Clk) + begin + Array[SlotIdx][BitToChange] <= #`RegDel BitVal; + + OutputVal = Array[SlotToReturn]; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mem_twoedge.v b/SVIncCompil/Testcases/Verilator/t_mem_twoedge.v new file mode 100644 index 0000000..6974040 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mem_twoedge.v
@@ -0,0 +1,117 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // verilator lint_off MULTIDRIVEN + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + wire [15:0] out2; // From test of Test.v + // End of automatics + // verilator lint_on MULTIDRIVEN + + Test test ( + .en (crc[21:20]), + .a1 (crc[19:18]), + .a0 (crc[17:16]), + .d1 (crc[15:8]), + .d0 (crc[7:0]), + /*AUTOINST*/ + // Outputs + .out (out[31:0]), + .out2 (out2[15:0]), + // Inputs + .clk (clk)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out2, 16'h0, out}; + + // Test loop +`ifdef TEST_VERBOSE + always @ (negedge clk) begin + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); + end +`endif + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + test.clear(); + end + else if (cyc<10) begin + sum <= 64'h0; + test.clear(); + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hc68a94a34ec970aa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, out2, + // Inputs + clk, en, a0, a1, d0, d1 + ); + + input clk; + input [1:0] en; + input [1:0] a0; + input [1:0] a1; + input [7:0] d0; + input [7:0] d1; + output reg [31:0] out; + output reg [15:0] out2; + + // verilator lint_off MULTIDRIVEN + reg [7:0] mem [4]; + // verilator lint_on MULTIDRIVEN + + task clear(); + for (int i=0; i<4; ++i) mem[i] = 0; + endtask + + always @(posedge clk) begin + if (en[0]) begin + mem[a0] <= d0; + out2[7:0] <= d0; + end + end + always @(negedge clk) begin + if (en[1]) begin + mem[a1] <= d1; + out2[15:8] <= d0; + end + end + + assign out = {mem[3],mem[2],mem[1],mem[0]}; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_metacmt_onoff.v b/SVIncCompil/Testcases/Verilator/t_metacmt_onoff.v new file mode 100644 index 0000000..4b0cda5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_metacmt_onoff.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module + +module t; + // Test turning on and off a message on the same line; only middle reg shouldn't warn + reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_dup_bad.v b/SVIncCompil/Testcases/Verilator/t_mod_dup_bad.v new file mode 100644 index 0000000..296f098 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_dup_bad.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module a(); +endmodule + +module test(); + a a(); +endmodule + +module a(); +endmodule + +module b(); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_dup_ign.v b/SVIncCompil/Testcases/Verilator/t_mod_dup_ign.v new file mode 100644 index 0000000..7283d08 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_dup_ign.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t; + sub sub (); +endmodule + +module sub; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +// verilator lint_off MODDUP +module sub; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_interface_array.v b/SVIncCompil/Testcases/Verilator/t_mod_interface_array.v new file mode 100644 index 0000000..30a2a2a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_interface_array.v
@@ -0,0 +1,63 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. + +parameter N = 4; + +interface a_if #(parameter PARAM = 0) (); + logic long_name; + modport source (output long_name); + modport sink (input long_name); +endinterface + +module intf_source + ( + input logic [N-1:0] intf_input, + a_if.source i_intf_source[N-1:0] + ); + generate + for (genvar i=0; i < N;i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate +endmodule + +module intf_sink + ( + output [N-1:0] a_out, + a_if.sink i_intf_sink[N-1:0] + ); + generate + for (genvar i=0; i < N;i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate +endmodule + +module t + ( + clk + ); + input clk; + logic [N-1:0] a_in; + logic [N-1:0] a_out; + logic [N-1:0] ack_out; + a_if #(.PARAM(1)) tl_intf [N-1:0] (); + intf_source source(a_in, tl_intf); + intf_sink sink(a_out, tl_intf); + + initial a_in = '0; + always @(posedge clk) begin + a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; + ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; + if (ack_out != a_out) begin + $stop; + end + + if (& a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_interface_array1.v b/SVIncCompil/Testcases/Verilator/t_mod_interface_array1.v new file mode 100644 index 0000000..0ae3acb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_interface_array1.v
@@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. + +parameter N = 4; + +interface a_if #(parameter PARAM = 0) (); + logic long_name; + modport source (output long_name); + modport sink (input long_name); +endinterface + +module intf_source + ( + input logic [N-1:0] intf_input, + a_if.source i_intf_source[N-1:0] + ); + generate + for (genvar i=0; i < N;i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate +endmodule + +module intf_sink + ( + output [N-1:0] a_out, + a_if.sink i_intf_sink[N-1:0] + ); + generate + for (genvar i=0; i < N;i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate +endmodule + +module t + ( + clk + ); + input clk; + logic [N-1:0] a_in; + logic [N-1:0] a_out; + logic [N-1:0] ack_out; + // verilator lint_off LITENDIAN + a_if #(.PARAM(1)) tl_intf [N] (); + // verilator lint_on LITENDIAN + intf_source source(a_in, tl_intf); + intf_sink sink(a_out, tl_intf); + + initial a_in = '0; + always @(posedge clk) begin + a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; + ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; + if (ack_out != a_out) begin + $stop; + end + + if (& a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_interface_array2.v b/SVIncCompil/Testcases/Verilator/t_mod_interface_array2.v new file mode 100644 index 0000000..2ff66d6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_interface_array2.v
@@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. + +parameter N = 4; +// verilator lint_off LITENDIAN + +interface a_if #(parameter PARAM = 0) (); + logic long_name; + modport source (output long_name); + modport sink (input long_name); +endinterface + +module intf_source + ( + input logic [0:N-1] intf_input, + a_if.source i_intf_source[0:N-1] + ); + generate + for (genvar i=0; i < N;i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate +endmodule + +module intf_sink + ( + output [0:N-1] a_out, + a_if.sink i_intf_sink[0:N-1] + ); + generate + for (genvar i=0; i < N;i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate +endmodule + +module t + ( + clk + ); + input clk; + logic [0:N-1] a_in; + logic [0:N-1] a_out; + logic [0:N-1] ack_out; + a_if #(.PARAM(1)) tl_intf [0:N-1] (); + intf_source source(a_in, tl_intf); + intf_sink sink(a_out, tl_intf); + + initial a_in = '0; + always @(posedge clk) begin + a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; + ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; + if (ack_out != a_out) begin + $stop; + end + + if (& a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_longname.v b/SVIncCompil/Testcases/Verilator/t_mod_longname.v new file mode 100644 index 0000000..8198fda --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_longname.v
@@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// The code as shown makes a really big file name with Verilator. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +`define LONG_NAME_MOD modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie +`define LONG_NAME_SUB sublongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie +`define LONG_NAME_VAR varlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie + +module t (); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + + logic `LONG_NAME_VAR; + + `LONG_NAME_MOD + `LONG_NAME_SUB + (); + +endmodule + +module `LONG_NAME_MOD (); + // Force Verilator to make a new class + logic a1 /* verilator public */; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_nomod.v b/SVIncCompil/Testcases/Verilator/t_mod_nomod.v new file mode 100644 index 0000000..bb6c642 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_nomod.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +//bug 1381 + +logic root_var; + +// No module statements....
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_recurse.v b/SVIncCompil/Testcases/Verilator/t_mod_recurse.v new file mode 100644 index 0000000..031e97f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_recurse.v
@@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Sean Moore. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [7:0] tripline = crc[7:0]; + + /*AUTOWIRE*/ + + wire valid; + wire [3-1:0] value; + + PriorityChoice #(.OCODEWIDTH(3)) + pe (.out(valid), .outN(value[2:0]), .tripline(tripline)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, valid, value}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hc5fc632f816568fb + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module PriorityChoice (out, outN, tripline); + parameter OCODEWIDTH = 1; + localparam CODEWIDTH=OCODEWIDTH-1; + localparam SCODEWIDTH= (CODEWIDTH<1) ? 1 : CODEWIDTH; + + output reg out; + output reg [OCODEWIDTH-1:0] outN; + input wire [(1<<OCODEWIDTH)-1:0] tripline; + wire left; + wire [SCODEWIDTH-1:0] leftN; + wire right; + wire [SCODEWIDTH-1:0] rightN; + + generate + if(OCODEWIDTH==1) begin + assign left = tripline[1]; + assign right = tripline[0]; + + always @(*) begin + out = left || right ; + if(right) begin outN = {1'b0}; end + else begin outN = {1'b1}; end + end + end else begin + PriorityChoice #(.OCODEWIDTH(OCODEWIDTH-1)) + leftMap + ( + .out(left), + .outN(leftN), + .tripline(tripline[(2<<CODEWIDTH)-1:(1<<CODEWIDTH)]) + ); + PriorityChoice #(.OCODEWIDTH(OCODEWIDTH-1)) + rightMap + ( + .out(right), + .outN(rightN), + .tripline(tripline[(1<<CODEWIDTH)-1:0]) + ); + always @(*) begin + if(right) begin + out = right; + outN = {1'b0, rightN[OCODEWIDTH-2:0]}; + end else begin + out = left; + outN = {1'b1, leftN[OCODEWIDTH-2:0]}; + end + end + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_mod_recurse1.v b/SVIncCompil/Testcases/Verilator/t_mod_recurse1.v new file mode 100644 index 0000000..ae49398 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_mod_recurse1.v
@@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Sean Moore. + +module t (/*AUTOARG*/); + + rec rec (); + +endmodule + +module rec; + parameter DEPTH = 1; + + generate + if (DEPTH==1) begin + rec #(.DEPTH(DEPTH+1)) sub; + end + else if (DEPTH==2) begin + rec #(.DEPTH(DEPTH+1)) subb; + end + else if (DEPTH==3) begin + bottom #(.DEPTH(DEPTH+1)) bot; + end + endgenerate +endmodule + +module bottom; + parameter DEPTH = 1; + initial begin + if (DEPTH!=4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_multitop1.v b/SVIncCompil/Testcases/Verilator/t_multitop1.v new file mode 100644 index 0000000..1eaaea7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_multitop1.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + t_multitop1s s (); + initial $display("In '%m'"); + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_multitop1s.v b/SVIncCompil/Testcases/Verilator/t_multitop1s.v new file mode 100644 index 0000000..2fc35f0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_multitop1s.v
@@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t_multitop1s; + initial $display("In '%m'"); +endmodule + +module in_subfile; + initial $display("In '%m'"); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_multitop_sig.v b/SVIncCompil/Testcases/Verilator/t_multitop_sig.v new file mode 100644 index 0000000..cc20c32 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_multitop_sig.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module a(in, out); + input in; + output out; + assign out = !in; + sub sub (); + initial $display("In '%m'"); +endmodule + +module b(in, out); + input in; + output out; + assign out = in; + sub sub (); + initial $display("In '%m'"); +endmodule + +module c(uniq_in, uniq_out); + input uniq_in; + output uniq_out; + assign uniq_out = !uniq_in; + sub sub (); + initial $display("In '%m'"); +endmodule + +module sub; + initial $display("In '%m'"); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_optm_if_array.v b/SVIncCompil/Testcases/Verilator/t_optm_if_array.v new file mode 100644 index 0000000..bfcd1f0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_optm_if_array.v
@@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + dinitout, + // Inputs + clk, rstn + ); + + input clk; + input rstn; + output [31:0] dinitout; + + wire zero; + assign zero = 1'd0; + + reg [31:0] dinit [0:1]; + wire [31:0] dinitout = dinit[0] | dinit[1]; + + reg rstn_r; // .pl file checks that this signal gets optimized away + always @(posedge clk) begin + rstn_r <= rstn; + end + + always @(posedge clk) begin + if ((rstn_r == 0)) begin // Will optimize away + dinit[0] <= '0; + end + else begin + dinit[0] <= {31'd0, zero}; + end + end + + always @(posedge clk) begin + if ((rstn_r == 0)) begin // Will optimize away + dinit[1] <= 1234; + end + else begin + dinit[1] <= 1234; + end + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_optm_redor.v b/SVIncCompil/Testcases/Verilator/t_optm_redor.v new file mode 100644 index 0000000..b82e58b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_optm_redor.v
@@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [15:0] in = crc[15:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out), + // Inputs + .in (in[15:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h162c58b1635b8d6e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [15:0] in; + output reg out; + + // TODO this should flatten into a reduction OR + always_comb begin + out = 0; + for (int i=0; i<16; i=i+1) begin + if (in[i]) begin + out = 1; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order.v b/SVIncCompil/Testcases/Verilator/t_order.v new file mode 100644 index 0000000..84fbeda --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order.v
@@ -0,0 +1,107 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB + // surefire lint_off STMINI + // surefire lint_off CSEBEQ + + input clk; + + reg [7:0] a_to_clk_levm3; + reg [7:0] b_to_clk_levm1; + reg [7:0] c_com_levs10; + reg [7:0] d_to_clk_levm2; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v + wire [7:0] n_from_clk_lev2; // From a of t_order_a.v + wire [7:0] o_from_com_levs11; // From a of t_order_a.v + wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v + wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v + // End of automatics + + reg [7:0] cyc; initial cyc=0; + + t_order_a a ( + .one (8'h1), + /*AUTOINST*/ + // Outputs + .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]), + .n_from_clk_lev2 (n_from_clk_lev2[7:0]), + .o_from_com_levs11 (o_from_com_levs11[7:0]), + .o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), + // Inputs + .clk (clk), + .a_to_clk_levm3 (a_to_clk_levm3[7:0]), + .b_to_clk_levm1 (b_to_clk_levm1[7:0]), + .c_com_levs10 (c_com_levs10[7:0]), + .d_to_clk_levm2 (d_to_clk_levm2[7:0])); + + t_order_b b ( + /*AUTOINST*/ + // Outputs + .o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]), + // Inputs + .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0])); + + reg [7:0] o_from_com_levs12; + reg [7:0] o_from_com_levs13; + always @ (/*AS*/o_from_com_levs11) begin + o_from_com_levs12 = o_from_com_levs11 + 8'h1; + o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize + o_from_com_levs13 = o_from_com_levs12; + end + + reg sepassign_in; + // verilator lint_off UNOPTFLAT + wire [3:0] sepassign; + // verilator lint_on UNOPTFLAT + + // verilator lint_off UNOPT + assign #0.1 sepassign[0] = 0, + sepassign[1] = sepassign[2], + sepassign[2] = sepassign[3], + sepassign[3] = sepassign_in; + wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2; + // verilator lint_on UNOPT + + always @ (posedge clk) begin + cyc <= cyc+8'd1; + sepassign_in <= 0; + if (cyc == 8'd1) begin + a_to_clk_levm3 <= 0; + d_to_clk_levm2 <= 1; + b_to_clk_levm1 <= 1; + c_com_levs10 <= 2; + sepassign_in <= 1; + end + if (cyc == 8'd2) begin + if (sepassign !== 4'b1110) $stop; + end + if (cyc == 8'd3) begin + + $display("%d %d %d %d",m_from_clk_lev1_r, + n_from_clk_lev2, + o_from_com_levs11, + o_from_comandclk_levs12); + + if (m_from_clk_lev1_r !== 8'h2) $stop; + if (o_subfrom_clk_lev3 !== 8'h2) $stop; + if (n_from_clk_lev2 !== 8'h2) $stop; + if (o_from_com_levs11 !== 8'h3) $stop; + if (o_from_com_levs13 !== 8'h5) $stop; + if (o_from_comandclk_levs12 !== 8'h5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_2d.v b/SVIncCompil/Testcases/Verilator/t_order_2d.v new file mode 100644 index 0000000..35f0c35 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_2d.v
@@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire input_signal = crc[0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire output_signal; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .output_signal (output_signal), + // Inputs + .input_signal (input_signal)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, output_signal}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h765b2e12b25ec97b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test ( + input input_signal, + output output_signal + ); + + // bug872 + + // verilator lint_off UNOPTFLAT + wire some_signal[1:0][1:0]; + assign some_signal[0][0] = input_signal; + assign some_signal[0][1] = some_signal[0][0]; + assign some_signal[1][0] = some_signal[0][1]; + assign some_signal[1][1] = some_signal[1][0]; + assign output_signal = some_signal[1][1]; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_a.v b/SVIncCompil/Testcases/Verilator/t_order_a.v new file mode 100644 index 0000000..199272d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_a.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_order_a (/*AUTOARG*/ + // Outputs + m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, + o_from_comandclk_levs12, + // Inputs + clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one + ); + + input clk; + input [7:0] a_to_clk_levm3; + input [7:0] b_to_clk_levm1; + input [7:0] c_com_levs10; + input [7:0] d_to_clk_levm2; + input [7:0] one; + output [7:0] m_from_clk_lev1_r; + output [7:0] n_from_clk_lev2; + output [7:0] o_from_com_levs11; + output [7:0] o_from_comandclk_levs12; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [7:0] m_from_clk_lev1_r; + // End of automatics + + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB + + wire [7:0] a_to_clk_levm1; + wire [7:0] a_to_clk_levm2; + wire [7:0] c_com_levs11; + reg [7:0] o_from_comandclk_levs12; + wire [7:0] n_from_clk_lev2; + wire [7:0] n_from_clk_lev3; + + assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2; + assign a_to_clk_levm2 = a_to_clk_levm3 + 0; + + always @ (posedge clk) begin + m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1; + end + + assign c_com_levs11 = c_com_levs10 + one; + always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3; + assign n_from_clk_lev2 = m_from_clk_lev1_r; + assign n_from_clk_lev3 = n_from_clk_lev2; + wire [7:0] o_from_com_levs11 = c_com_levs10 + 1; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_b.v b/SVIncCompil/Testcases/Verilator/t_order_b.v new file mode 100644 index 0000000..c19f566 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_b.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_order_b (/*AUTOARG*/ + // Outputs + o_subfrom_clk_lev2, + // Inputs + m_from_clk_lev1_r + ); + + input [7:0] m_from_clk_lev1_r; + output [7:0] o_subfrom_clk_lev2; + + wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_clkinst.v b/SVIncCompil/Testcases/Verilator/t_order_clkinst.v new file mode 100644 index 0000000..a1ed555 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_clkinst.v
@@ -0,0 +1,117 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // verilator lint_off COMBDLY + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + // verilator lint_off BLKANDNBLK + + reg c1_start; initial c1_start = 0; + wire [31:0] c1_count; + comb_loop c1 (.count(c1_count), .start(c1_start)); + + wire s2_start = c1_start; + wire [31:0] s2_count; + seq_loop s2 (.count(s2_count), .start(s2_start)); + + wire c3_start = (s2_count[0]); + wire [31:0] c3_count; + comb_loop c3 (.count(c3_count), .start(c3_start)); + + reg [7:0] cyc; initial cyc=0; + always @ (posedge clk) begin + //$write("[%0t] %x counts %x %x %x\n",$time,cyc,c1_count,s2_count,c3_count); + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin + c1_start <= 1'b0; + end + 8'd01: begin + c1_start <= 1'b1; + end + default: ; + endcase + case (cyc) + 8'd02: begin + // On Verilator, we expect these comparisons to match exactly, + // confirming that our settle loop repeated the exact number of + // iterations we expect. No '$stop' should be called here, and we + // should reach the normal '$finish' below on the next cycle. + if (c1_count!=32'h3) $stop; + if (s2_count!=32'h3) $stop; + if (c3_count!=32'h5) $stop; + end + 8'd03: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + end +endmodule + +module comb_loop (/*AUTOARG*/ + // Outputs + count, + // Inputs + start + ); + input start; + output reg [31:0] count; initial count = 0; + + reg [31:0] runnerm1, runner; initial runner = 0; + + always @ (posedge start) begin + runner = 3; + end + + always @ (/*AS*/runner) begin + runnerm1 = runner - 32'd1; + end + + always @ (/*AS*/runnerm1) begin + if (runner > 0) begin + count = count + 1; + runner = runnerm1; + $write ("%m count=%d runner =%x\n",count, runnerm1); + end + end + +endmodule + +module seq_loop (/*AUTOARG*/ + // Outputs + count, + // Inputs + start + ); + input start; + output reg [31:0] count; initial count = 0; + + reg [31:0] runnerm1, runner; initial runner = 0; + + always @ (posedge start) begin + runner <= 3; + end + + always @ (/*AS*/runner) begin + runnerm1 = runner - 32'd1; + end + + always @ (/*AS*/runnerm1) begin + if (runner > 0) begin + count = count + 1; + runner <= runnerm1; + $write ("%m count=%d runner<=%x\n",count, runnerm1); + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_comboclkloop.v b/SVIncCompil/Testcases/Verilator/t_order_comboclkloop.v new file mode 100644 index 0000000..e750675 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_comboclkloop.v
@@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // verilator lint_off BLKANDNBLK + // verilator lint_off COMBDLY + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + // verilator lint_off MULTIDRIVEN + + reg [31:0] runnerm1, runner; initial runner = 0; + reg [31:0] runcount; initial runcount = 0; + reg [31:0] clkrun; initial clkrun = 0; + reg [31:0] clkcount; initial clkcount = 0; + always @ (/*AS*/runner) begin + runnerm1 = runner - 32'd1; + end + reg run0; + always @ (/*AS*/runnerm1) begin + if ((runner & 32'hf)!=0) begin + runcount = runcount + 1; + runner = runnerm1; + $write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1); + end + run0 = (runner[8:4]!=0 && runner[3:0]==0); + end + + always @ (posedge run0) begin + // Do something that forces another combo run + clkcount <= clkcount + 1; + runner[8:4] <= runner[8:4] - 1; + runner[3:0] <= 3; + $write ("[%0t] posedge runner=%0x\n", $time, runner); + end + + reg [7:0] cyc; initial cyc=0; + always @ (posedge clk) begin + $write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount); + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin + runner <= 0; + end + 8'd01: begin + runner <= 32'h35; + end + default: ; + endcase + case (cyc) + 8'd02: begin + if (runcount!=32'he) $stop; + if (clkcount!=32'h3) $stop; + end + 8'd03: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_comboloop.v b/SVIncCompil/Testcases/Verilator/t_order_comboloop.v new file mode 100644 index 0000000..0d98f10 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_comboloop.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc; initial cyc=1; + + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + reg [31:0] runner; initial runner = 5; + reg [31:0] runnerm1; + reg [59:0] runnerq; + reg [89:0] runnerw; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin +`ifdef verilator + if (runner != 0) $stop; // Initial settlement failed +`endif + end + if (cyc==2) begin + runner = 20; + runnerq = 60'h0; + runnerw = 90'h0; + end + if (cyc==3) begin + if (runner != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + // This forms a "loop" where we keep going through the always till runner=0 + // This isn't "regular" beh code, but ensures our change detection is working properly + always @ (/*AS*/runner) begin + runnerm1 = runner - 32'd1; + end + + always @ (/*AS*/runnerm1) begin + if (runner > 0) begin + runner = runnerm1; + runnerq = runnerq - 60'd1; + runnerw = runnerw - 90'd1; + $write ("[%0t] runner=%d\n", $time, runner); + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_doubleloop.v b/SVIncCompil/Testcases/Verilator/t_order_doubleloop.v new file mode 100644 index 0000000..d8e1729 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_doubleloop.v
@@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc; initial cyc=1; + + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + // verilator lint_off MULTIDRIVEN + // verilator lint_off BLKANDNBLK + + reg [31:0] comcnt; + reg [31:0] dlycnt; initial dlycnt=0; + reg [31:0] lastdlycnt; initial lastdlycnt = 0; + + reg [31:0] comrun; initial comrun = 0; + reg [31:0] comrunm1; + reg [31:0] dlyrun; initial dlyrun = 0; + reg [31:0] dlyrunm1; + always @ (posedge clk) begin + $write("[%0t] cyc %d\n",$time,cyc); + cyc <= cyc + 1; + if (cyc==2) begin + // Test # of iters + lastdlycnt = 0; + comcnt = 0; + dlycnt <= 0; + end + if (cyc==3) begin + dlyrun <= 5; + dlycnt <= 0; + end + if (cyc==4) begin + comrun = 4; + end + end + always @ (negedge clk) begin + if (cyc==5) begin + $display("%d %d\n", dlycnt, comcnt); + if (dlycnt != 32'd5) $stop; + if (comcnt != 32'd19) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // This forms a "loop" where we keep going through the always till comrun=0 + reg runclk; initial runclk = 1'b0; + always @ (/*AS*/comrunm1 or dlycnt) begin + if (lastdlycnt != dlycnt) begin + comrun = 3; + $write ("[%0t] comrun=%0d start\n", $time, comrun); + end + else if (comrun > 0) begin + comrun = comrunm1; + if (comrunm1==1) begin + runclk = 1; + $write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun); + end + else $write ("[%0t] comrun=%0d\n", $time, comrun); + end + lastdlycnt = dlycnt; + end + + always @ (/*AS*/comrun) begin + if (comrun!=0) begin + comrunm1 = comrun - 32'd1; + comcnt = comcnt + 32'd1; + $write("[%0t] comcnt=%0d\n",$time,comcnt); + end + end + + // This forms a "loop" where we keep going through the always till dlyrun=0 + reg runclkrst; + always @ (posedge runclk) begin + runclkrst <= 1; + $write ("[%0t] runclk\n", $time); + if (dlyrun > 0) begin + dlyrun <= dlyrun - 32'd1; + dlycnt <= dlycnt + 32'd1; + $write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1); + end + end + + always @* begin + if (runclkrst) begin + $write ("[%0t] runclk reset\n", $time); + runclkrst = 0; + runclk = 0; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_first.v b/SVIncCompil/Testcases/Verilator/t_order_first.v new file mode 100644 index 0000000..645d133 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_first.v
@@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + fastclk + ); + input fastclk; + + t_netlist tnetlist + (.also_fastclk (fastclk), + /*AUTOINST*/ + // Inputs + .fastclk (fastclk)); + +endmodule + +module t_netlist (/*AUTOARG*/ + // Inputs + fastclk, also_fastclk + ); + + // surefire lint_off ASWEMB + + input fastclk; + input also_fastclk; + integer _mode; initial _mode = 0; + + // This entire module should optimize to nearly nothing... + + // verilator lint_off UNOPTFLAT + reg [4:0] a,a2,b,c,d,e; + // verilator lint_on UNOPTFLAT + + initial a=5'd1; + + always @ (posedge fastclk) begin + b <= a+5'd1; + c <= b+5'd1; // Better for ordering if this moves before previous statement + end + + // verilator lint_off UNOPT + always @ (d or /*AS*/a or c) begin + e = d+5'd1; + a2 = a+5'd1; // This can be pulled out of the middle of the always + d = c+5'd1; // Better for ordering if this moves before previous statement + end + // verilator lint_on UNOPT + + always @ (posedge also_fastclk) begin + if (_mode==5) begin + if (a2 != 5'd2) $stop; + if (e != 5'd5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + _mode <= _mode + 1; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_loop_bad.v b/SVIncCompil/Testcases/Verilator/t_order_loop_bad.v new file mode 100644 index 0000000..6b6b51a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_loop_bad.v
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Non-cutable edge in loop +// +// This code (stripped down from a much larger application) has a loop between +// the use of ready in the first two always blocks. However it should +// trivially trigger the $write on the first clk posedge. +// +// This is a regression test against issue 513. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg ready; + + initial begin + ready = 1'b0; + end + + always @(posedge ready) begin + if ((ready === 1'b1)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + always @(posedge ready) begin + if ((ready === 1'b0)) begin + ready = 1'b1 ; + end + end + + always @(posedge clk) begin + ready = 1'b1; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_multialways.v b/SVIncCompil/Testcases/Verilator/t_order_multialways.v new file mode 100644 index 0000000..23e1626 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_multialways.v
@@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [31:0] in_a; + reg [31:0] in_b; + + reg [31:0] e,f,g,h; + + always @ (/*AS*/in_a) begin + e = in_a; + f = {e[15:0], e[31:16]}; + g = {f[15:0], f[31:16]}; + h = {g[15:0], g[31:16]}; + end + + // verilator lint_off UNOPTFLAT + reg [31:0] e2,f2,g2,h2; + always @ (/*AS*/f2) begin + h2 = {g2[15:0], g2[31:16]}; + g2 = {f2[15:0], f2[31:16]}; + end + always @ (/*AS*/in_a) begin + f2 = {e2[15:0], e2[31:16]}; + e2 = in_a; + end + // verilator lint_on UNOPTFLAT + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %x\n", cyc, h, h2); + if (h != h2) $stop; + if (cyc==1) begin + in_a <= 32'h89a14fab; + in_b <= 32'h7ab512fa; + end + if (cyc==2) begin + in_a <= 32'hf4c11a42; + in_b <= 32'h359967c6; + if (h != 32'h4fab89a1) $stop; + end + if (cyc==3) begin + if (h != 32'h1a42f4c1) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_multidriven.v b/SVIncCompil/Testcases/Verilator/t_order_multidriven.v new file mode 100644 index 0000000..d3202df --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_multidriven.v
@@ -0,0 +1,192 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Ted Campbell. + +//With MULTI_CLK defined shows bug, without it is hidden +`define MULTI_CLK + +//bug634 + +module t ( + input i_clk_wr, + input i_clk_rd + ); + + wire wr$wen; + wire [7:0] wr$addr; + wire [7:0] wr$wdata; + wire [7:0] wr$rdata; + + wire rd$wen; + wire [7:0] rd$addr; + wire [7:0] rd$wdata; + wire [7:0] rd$rdata; + + wire clk_wr; + wire clk_rd; + + `ifdef MULTI_CLK + assign clk_wr = i_clk_wr; + assign clk_rd = i_clk_rd; + `else + assign clk_wr = i_clk_wr; + assign clk_rd = i_clk_wr; + `endif + + FooWr u_wr ( + .i_clk ( clk_wr ), + + .o_wen ( wr$wen ), + .o_addr ( wr$addr ), + .o_wdata ( wr$wdata ), + .i_rdata ( wr$rdata ) + ); + + FooRd u_rd ( + .i_clk ( clk_rd ), + + .o_wen ( rd$wen ), + .o_addr ( rd$addr ), + .o_wdata ( rd$wdata ), + .i_rdata ( rd$rdata ) + ); + + FooMem u_mem ( + .iv_clk ( {clk_wr, clk_rd } ), + .iv_wen ( {wr$wen, rd$wen } ), + .iv_addr ( {wr$addr, rd$addr } ), + .iv_wdata ( {wr$wdata,rd$wdata} ), + .ov_rdata ( {wr$rdata,rd$rdata} ) + ); + +endmodule + + +// Memory Writer +module FooWr( + input i_clk, + + output o_wen, + output [7:0] o_addr, + output [7:0] o_wdata, + input [7:0] i_rdata + ); + + reg [7:0] cnt = 0; + + // Count [0,200] + always @( posedge i_clk ) + if ( cnt < 8'd50 ) + cnt <= cnt + 8'd1; + + // Write addr in (10,30) if even + assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 ); + assign o_addr = cnt; + assign o_wdata = cnt; + +endmodule + + +// Memory Reader +module FooRd( + input i_clk, + + output o_wen, + output [7:0] o_addr, + output [7:0] o_wdata, + input [7:0] i_rdata + ); + + reg [7:0] cnt = 0; + reg [7:0] addr_r; + reg en_r; + + // Count [0,200] + always @( posedge i_clk ) + if ( cnt < 8'd200 ) + cnt <= cnt + 8'd1; + + // Read data + assign o_wen = 0; + assign o_addr = cnt - 8'd100; + + // Track issued read + always @( posedge i_clk ) + begin + addr_r <= o_addr; + en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 ); + end + + // Display to console 100 cycles after writer + always @( negedge i_clk ) + if ( en_r ) begin +`ifdef TEST_VERBOSE + $display( "MEM[%x] == %x", addr_r, i_rdata ); +`endif + if (addr_r != i_rdata) $stop; + end + +endmodule + + +// Multi-port memory abstraction +module FooMem( + input [2 -1:0] iv_clk, + input [2 -1:0] iv_wen, + input [2*8-1:0] iv_addr, + input [2*8-1:0] iv_wdata, + output [2*8-1:0] ov_rdata + ); + + FooMemImpl u_impl ( + .a_clk ( iv_clk [0*1+:1] ), + .a_wen ( iv_wen [0*1+:1] ), + .a_addr ( iv_addr [0*8+:8] ), + .a_wdata ( iv_wdata[0*8+:8] ), + .a_rdata ( ov_rdata[0*8+:8] ), + + .b_clk ( iv_clk [1*1+:1] ), + .b_wen ( iv_wen [1*1+:1] ), + .b_addr ( iv_addr [1*8+:8] ), + .b_wdata ( iv_wdata[1*8+:8] ), + .b_rdata ( ov_rdata[1*8+:8] ) + ); + +endmodule + + +// Dual-Port L1 Memory Implementation +module FooMemImpl( + input a_clk, + input a_wen, + input [7:0] a_addr, + input [7:0] a_wdata, + output [7:0] a_rdata, + + input b_clk, + input b_wen, + input [7:0] b_addr, + input [7:0] b_wdata, + output [7:0] b_rdata + ); + + /* verilator lint_off MULTIDRIVEN */ + reg [7:0] mem[0:255]; + /* verilator lint_on MULTIDRIVEN */ + + always @( posedge a_clk ) + if ( a_wen ) + mem[a_addr] <= a_wdata; + + always @( posedge b_clk ) + if ( b_wen ) + mem[b_addr] <= b_wdata; + + always @( posedge a_clk ) + a_rdata <= mem[a_addr]; + + always @( posedge b_clk ) + b_rdata <= mem[b_addr]; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_quad.v b/SVIncCompil/Testcases/Verilator/t_order_quad.v new file mode 100644 index 0000000..60635c5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_quad.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +//bug 762 +module t(a0, y); + input [3:0] a0; + output [44:0] y; + + assign y[40] = 0; + assign y[30] = 0; + // verilator lint_off UNOPTFLAT + assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 }; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_order_wireloop.v b/SVIncCompil/Testcases/Verilator/t_order_wireloop.v new file mode 100644 index 0000000..b1156cf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_order_wireloop.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + bar + ); + + wire foo; + output bar; + + // Oh dear. + assign foo = bar; + assign bar = foo; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package.v b/SVIncCompil/Testcases/Verilator/t_package.v new file mode 100644 index 0000000..3273062 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package.v
@@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +typedef int unit_type_t; + +function [3:0] unit_plusone(input [3:0] i); + unit_plusone = i+1; +endfunction + +package p; + typedef int package_type_t; + integer pi = 123; + function [3:0] plusone(input [3:0] i); + plusone = i+1; + endfunction +endpackage + +package p2; + typedef int package2_type_t; + function [3:0] plustwo(input [3:0] i); + plustwo = i+2; + endfunction +endpackage + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + unit_type_t vu; + $unit::unit_type_t vdu; + p::package_type_t vp; + + t2 t2 (); + + initial begin + if (unit_plusone(1) !== 2) $stop; + if ($unit::unit_plusone(1) !== 2) $stop; + if (p::plusone(1) !== 2) $stop; + p::pi = 124; + if (p::pi !== 124) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + always @ (posedge clk) begin + p::pi += 1; + if (p::pi < 124) $stop; + end +endmodule + +module t2; + import p::*; + import p2::plustwo; + import p2::package2_type_t; + package_type_t vp; + package2_type_t vp2; + initial begin + if (plusone(1) !== 2) $stop; + if (plustwo(1) !== 3) $stop; + if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_abs.v b/SVIncCompil/Testcases/Verilator/t_package_abs.v new file mode 100644 index 0000000..00c0f42 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_abs.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// see bug491 + +package functions; + function real abs (real num); + abs = (num <0) ? -num : num; + endfunction + function real neg (real num); + return -abs(num); // Check package funcs can call package funcs + endfunction +endpackage + +module t (); + import functions::*; + localparam P = 1; + generate + if (P == 1) begin + initial begin + if (abs(-2.1) != 2.1) $stop; + if (abs(2.2) != 2.2) $stop; + if (neg(-2.1) != -2.1) $stop; + if (neg(2.2) != -2.2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + endgenerate +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_ddecl.v b/SVIncCompil/Testcases/Verilator/t_package_ddecl.v new file mode 100644 index 0000000..310ff2b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_ddecl.v
@@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// see bug 474 +package functions; + localparam LP_PACK = 512; + localparam LP_PACK_AND_MOD = 19; + task check_param; + $display("In %m\n"); // "In functions::check_param" + if (LP_PACK_AND_MOD != 19) $stop; + endtask +endpackage + +module t (); + // synthesis translate off + import functions::*; + // synthesis translate on + localparam LP_PACK_AND_MOD = 20; + initial begin + // verilator lint_off STMTDLY + #10; + // verilator lint_on STMTDLY + if (LP_PACK_AND_MOD != 20) $stop; + check_param(); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_dimport.v b/SVIncCompil/Testcases/Verilator/t_package_dimport.v new file mode 100644 index 0000000..2305c58 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_dimport.v
@@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +package defs; + function automatic integer max; + input integer a; + input integer b; + max = (a > b) ? a : b; + endfunction + + function automatic integer log2; + input integer value; + value = value >> 1; + for (log2 = 0; value > 0; log2 = log2 + 1) + value = value >> 1; + endfunction + + function automatic integer ceil_log2; + input integer value; + value = value - 1; + for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) + value = value >> 1; + endfunction +endpackage + +module sub(); + + import defs::*; + + parameter RAND_NUM_MAX = ""; + + localparam DATA_RANGE = RAND_NUM_MAX + 1; + localparam DATA_WIDTH = ceil_log2(DATA_RANGE); + localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1)); + +endmodule + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + import defs::*; + + parameter WHICH = 0; + parameter MAX_COUNT = 10; + + localparam MAX_EXPONENT = log2(MAX_COUNT); + localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); + + input clk; + + generate + if (WHICH == 1) + begin : which_true + sub sub_true(); + defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; + end + else + begin : which_false + sub sub_false(); + defparam sub_false.RAND_NUM_MAX = MAX_COUNT; + end + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_dot.v b/SVIncCompil/Testcases/Verilator/t_package_dot.v new file mode 100644 index 0000000..b848b22 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_dot.v
@@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +package pkg; + typedef struct packed { + logic [3:0] msk; + logic [3:0] dat; + } STR_t; +endpackage; + +package csr_pkg; + typedef pkg::STR_t reg_t; + localparam reg_t REG_RST = 8'h34; +endpackage + +module t (/*AUTOARG*/); + initial begin + if (csr_pkg::REG_RST.msk != 4'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_enum.v b/SVIncCompil/Testcases/Verilator/t_package_enum.v new file mode 100644 index 0000000..c3402e5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_enum.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +package pkg; + typedef enum bit [1:0] + { + E__NOT = 2'b00, + E__VAL = 2'b11 + } E_t; +endpackage + +module t; + reg [1:0] ttype; + reg m; + + enum bit [1:0] { LOCAL } l; + + always @ (m or 1'b0 or LOCAL) begin + // Don't complain about constants in sensitivity lists + end + + initial begin + ttype = pkg::E__NOT; + m = (ttype == pkg::E__VAL); + if (m != 1'b0) $stop; + + ttype = pkg::E__VAL; + m = (ttype == pkg::E__VAL); + if (m != 1'b1) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_export.v b/SVIncCompil/Testcases/Verilator/t_package_export.v new file mode 100644 index 0000000..e8dbece --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_export.v
@@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett + +// see bug 591 + +package pkg1; + parameter PARAM2 = 16; + parameter PARAM3 = 16; +endpackage : pkg1 + + +package pkg10; + import pkg1::*; + import pkg1::*; // Ignore if already +`ifdef T_PACKAGE_EXPORT + export *::*; // Not supported on all simulators +`endif + parameter PARAM1 = 8; +endpackage +package pkg11; + import pkg10::*; +endpackage + +package pkg20; + import pkg1::*; +`ifdef T_PACKAGE_EXPORT + export pkg1::*; +`endif + parameter PARAM1 = 8; +endpackage +package pkg21; + import pkg20::*; +endpackage + +package pkg30; + import pkg1::*; +`ifdef T_PACKAGE_EXPORT + export pkg1::PARAM2; + export pkg1::PARAM3; +`endif + parameter PARAM1 = 8; +endpackage +package pkg31; + import pkg30::*; +endpackage + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [pkg11::PARAM1 : 0] bus11; + reg [pkg11::PARAM2 : 0] bus12; + reg [pkg11::PARAM3 : 0] bus13; + + reg [pkg21::PARAM1 : 0] bus21; + reg [pkg21::PARAM2 : 0] bus22; + reg [pkg21::PARAM3 : 0] bus23; + + reg [pkg31::PARAM1 : 0] bus31; + reg [pkg31::PARAM2 : 0] bus32; + reg [pkg31::PARAM3 : 0] bus33; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_param.v b/SVIncCompil/Testcases/Verilator/t_package_param.v new file mode 100644 index 0000000..fe4e492 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_param.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// IEEE 1800-2009 requires that any local definitions take precedence over +// definitions in wildcard imported packages (section 26.3). Thus the code +// below is valid SystemVerilog. +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2013 by Jie Xu + +package defs; + parameter NUMBER = 8; + localparam NUM = NUMBER; +endpackage + + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + import defs::*; + + // This also fails if we use localparam + parameter NUM = 32; + + // Check we have the right definition + always @(posedge clk) begin + if (NUM == 32) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_twodeep.v b/SVIncCompil/Testcases/Verilator/t_package_twodeep.v new file mode 100644 index 0000000..3008e1c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_twodeep.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett + +// see bug 591 + +package pkg2; + parameter PARAM2 = 16; +endpackage // pkg2 + +package pkg1; + import pkg2::*; + parameter PARAM1 = 8; +endpackage // pkg1 + +module t + import pkg1::*; // Test SV 2012 import format + (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [PARAM1:0] bus1; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_package_verb.v b/SVIncCompil/Testcases/Verilator/t_package_verb.v new file mode 100644 index 0000000..bc3191d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_package_verb.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// bug474 +package verb_pkg; + typedef enum int {VERB_I, + VERB_W} Verb_t; + Verb_t verb = VERB_I; + string message = " "; +endpackage + +module t; + import verb_pkg::*; + + string message = "*x*"; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param.v b/SVIncCompil/Testcases/Verilator/t_param.v new file mode 100644 index 0000000..8418cf4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param.v
@@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + parameter PAR = 3; + + m1 #(PAR) m1(); + m3 #(PAR) m3(); + mnooverride #(10) mno(); + + input clk; + integer cyc=1; + reg [4:0] bitsel; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + bitsel = 0; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 1; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 2; + if (PAR[bitsel]!==1'b0) $stop; + end + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module m1; + localparam PAR1MINUS1 = PAR1DUP-2-1; + localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly + parameter PAR1 = 0; + m2 #(PAR1MINUS1) m2 (); + + // Packed arrays + localparam [1:0][3:0] PACKED_PARAM = { 4'h3, 4'h6 }; + initial if (PACKED_PARAM != 8'h36) $stop; +endmodule + +// bug 810 +module m2 #(/*parameter*/ integer PAR2 = 10); + initial begin + $display("%x",PAR2); + if (PAR2 !== 2) $stop; + end +endmodule + +module m3; + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 3) $stop; + end +endmodule + +module mnooverride; + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 10) $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_array.v b/SVIncCompil/Testcases/Verilator/t_param_array.v new file mode 100644 index 0000000..7084c65 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_array.v
@@ -0,0 +1,86 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +module t (/*AUTOARG*/); + + typedef enum int { + PADTYPE_DEFAULT = 32'd0, + PADTYPE_GPIO, + PADTYPE_VDD, + PADTYPE_GND + } t_padtype; + + localparam int STR_PINID [0:15] + = '{ + "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" + }; + + typedef struct packed { + t_padtype padtype; + int aux; + } t_pin_descriptor; + + localparam t_pin_descriptor + PINOUT[ 1: 6] + = '{ + '{default:0, padtype:PADTYPE_GPIO, aux:1}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_VDD}, + '{default:0, padtype:PADTYPE_GND} + }; + + localparam int PINOUT_SIZE = 6; + localparam int PINOUT_WA[1:PINOUT_SIZE][3] + = '{ + '{0, PADTYPE_GPIO, 0}, + '{1, PADTYPE_GPIO, 0}, + '{2, PADTYPE_GPIO, 0}, + '{5, PADTYPE_GPIO, 0}, + '{6, PADTYPE_VDD, 0}, + '{8, PADTYPE_GND , 0} + }; + + const int pinout_static_const[1:PINOUT_SIZE][3] + = '{ + '{0, PADTYPE_GPIO, 0}, + '{1, PADTYPE_GPIO, 0}, + '{2, PADTYPE_GPIO, 0}, + '{5, PADTYPE_GPIO, 0}, + '{6, PADTYPE_VDD, 0}, + '{8, PADTYPE_GND , 0} + }; + + // Make sure consants propagate + checkstr #(.PINID(STR_PINID[1]), + .EXP("ERR")) + substr1 (); + checkstr #(.PINID(STR_PINID[8]), + .EXP("PA0")) + substr8 (); + + initial begin + $display("PINID1 %s", STR_PINID[1]); + $display("PINID8 %s", STR_PINID[8]); + if (STR_PINID[1] != "ERR") $stop; + if (STR_PINID[8] != "PA0") $stop; + if (pinout_static_const[1][0] != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module checkstr; + parameter int PINID = " "; + parameter int EXP = " "; + initial begin + $display("PID %s EXP %s", PINID, EXP); + if (EXP != "ERR" && EXP != "PA0") $stop; + if (PINID != EXP) $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_array2.v b/SVIncCompil/Testcases/Verilator/t_param_array2.v new file mode 100644 index 0000000..93bde7d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_array2.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t; + localparam int c[4] = '{5, 6, 7, 8}; + a #(.p(c)) i_a (); +endmodule + +module a + #( parameter int p[4] = '{1, 2, 3, 4} ); + initial begin + if (p[0] != 5) $stop; + if (p[1] != 6) $stop; + if (p[2] != 7) $stop; + if (p[3] != 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_array3.v b/SVIncCompil/Testcases/Verilator/t_param_array3.v new file mode 100644 index 0000000..3a3c9f5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_array3.v
@@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t; + parameter int SIZES [3:0] = '{1,2,3,4}; + typedef int calc_sums_t [3:0]; + + function calc_sums_t calc_sums; + int sum = 0; + for (int i=0; i<4; i++) begin + sum = sum + SIZES[i]; + calc_sums[i][31:0] = sum; + end + endfunction + + parameter int SUMS[3:0] = calc_sums(); + + initial begin + $display("%d ",SUMS[0]); + if (SUMS[0] != 4) $stop; + if (SUMS[1] != 4+3) $stop; + if (SUMS[2] != 4+3+2) $stop; + if (SUMS[3] != 4+3+2+1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_avec.v b/SVIncCompil/Testcases/Verilator/t_param_avec.v new file mode 100644 index 0000000..809f437 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_avec.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + sub #(.IDX(0), .CHK(10)) i0; + sub #(.IDX(2), .CHK(12)) i2; + sub #(.IDX(7), .CHK(17)) i7; + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub (); + function integer get_element; + input integer index; + input integer array_arg[7:0]; + get_element = array_arg[index]; + endfunction + + parameter integer IDX = 5; + parameter integer CHK = 5; + localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; + localparam element1 = array[IDX]; + localparam elementf = get_element(IDX, array); + initial begin + `checkh (element1, CHK); + `checkh (elementf, CHK); + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_bit_sel.v b/SVIncCompil/Testcases/Verilator/t_param_bit_sel.v new file mode 100644 index 0000000..f28d56c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_bit_sel.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// We see Verilator assumes a 1-bit parameter is a scalar rather than a 1-bit +// long vector. This causes the following code to fail. +// +// Other event drive simulators accept this. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // At this point it is ambiguous whether a is scalar or vector + parameter a = 1'b0; + wire b = a[0]; + // Note however b[0] is illegal. + + always @(posedge clk) begin + if (b == 1'b0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_ceil.v b/SVIncCompil/Testcases/Verilator/t_param_ceil.v new file mode 100644 index 0000000..14008fa --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_ceil.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] O_out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .O_out (O_out[31:0])); + + initial begin + if (O_out != 32'h4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module Test + ( + output [31:0] O_out + ); + + test + #( + .pFOO(5), + .pBAR(2) + ) U_test + ( + .O_out(O_out) + ); +endmodule + +module test + #(parameter pFOO = 7, + parameter pBAR = 3, + parameter pBAZ = ceiling(pFOO, pBAR) + ) + ( + output [31:0] O_out + ); + + assign O_out = pBAZ; + + function integer ceiling; + input [31:0] x, y; + ceiling = ((x%y == 0) ? x/y : (x/y)+1) + 1; + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_chain.v b/SVIncCompil/Testcases/Verilator/t_param_chain.v new file mode 100644 index 0000000..543a178 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_chain.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/); + + function integer max2; + input integer x; + input integer y; + begin + begin : blk + automatic int temp; + temp = x; + end + end + max2 = ( x > y ) ? x : y; + endfunction + + function integer max4; + input integer x; + input integer y; + input integer z; + input integer w; + // MAX2 is used multiple times + max4 = max2( max2( x, y ), max2( z, w ) ); + endfunction + + localparam MAX4 = max4( 1, 1, 0, 0 ); + + initial begin + if (MAX4 != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_circ_bad.v b/SVIncCompil/Testcases/Verilator/t_param_circ_bad.v new file mode 100644 index 0000000..0775dc4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_circ_bad.v
@@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/); + sub sub (); +endmodule + +module sub #(parameter WIDTH=X, parameter X=WIDTH) + (); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_concat.v b/SVIncCompil/Testcases/Verilator/t_param_concat.v new file mode 100644 index 0000000..11fde4e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_concat.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter UNSIZED = 10; + + integer cyc=1; + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; + if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_const_part.v b/SVIncCompil/Testcases/Verilator/t_param_const_part.v new file mode 100644 index 0000000..1de26f4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_const_part.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t; + function integer bottom_4bits; + input [7:0] i; + bottom_4bits = 0; + bottom_4bits[3:0] = i[3:0]; + endfunction + + function integer bottom_2_unknown; + input [7:0] i; + // bottom_4bits = 0; 'x + bottom_2_unknown[1:0] = i[1:0]; + endfunction + + localparam p = bottom_4bits(8'h13); + localparam bu = bottom_2_unknown(8'h13); + + initial begin + if (p != 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_ddeep_width.v b/SVIncCompil/Testcases/Verilator/t_param_ddeep_width.v new file mode 100644 index 0000000..54cb9f9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_ddeep_width.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use. + +// bug541 +module t(clk,odata); + input clk; + output [7:0] odata; + paramtest_DFFRE #(1) dffre0(clk,odata[7]); + paramtest_WRAP #(7) dffe0(clk,odata[6:0]); +endmodule + +module paramtest_WRAP(clk,q); + parameter W=1; + input clk; + output [W-1:0] q; + paramtest_DFFRE #(W) dffre0(clk,q); +endmodule + +module paramtest_DFFRE(clk,q); + parameter W=1; + parameter [W-1:0] INIT={W{1'b0}}; + input clk; + output [W-1:0] q; + reg [W-1:0] q; + always @(posedge clk) begin + q <= INIT; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_default.v b/SVIncCompil/Testcases/Verilator/t_param_default.v new file mode 100644 index 0000000..1175699 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_default.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module m #(parameter int Foo); +endmodule + +module t (/*AUTOARG*/); + + m #(10) foo(); + + initial begin + if (foo.Foo != 10) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_default_bad.v b/SVIncCompil/Testcases/Verilator/t_param_default_bad.v new file mode 100644 index 0000000..16ab64e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_default_bad.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module m #(parameter int Foo); +endmodule + +module t (/*AUTOARG*/); + + m foo(); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_first.v b/SVIncCompil/Testcases/Verilator/t_param_first.v new file mode 100644 index 0000000..e9a8391 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_first.v
@@ -0,0 +1,146 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg _ranit; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [4:0] par1; // From a1 of t_param_first_a.v + wire [4:0] par2; // From a2 of t_param_first_a.v + wire [4:0] par3; // From a3 of t_param_first_a.v + wire [4:0] par4; // From a4 of t_param_first_a.v + wire [1:0] varwidth1; // From a1 of t_param_first_a.v + wire [2:0] varwidth2; // From a2 of t_param_first_a.v + wire [3:0] varwidth3; // From a3 of t_param_first_a.v + wire [3:0] varwidth4; // From a4 of t_param_first_a.v + // End of automatics + /*t_param_first_a AUTO_TEMPLATE ( + .par (par@[])); + .varwidth (varwidth@[])); + */ + + parameter XX = 2'bXX; + + parameter THREE = 3; + + t_param_first_a #(1,5) a1 + ( + // Outputs + .varwidth (varwidth1[1:0]), + /*AUTOINST*/ + // Outputs + .par (par1[4:0])); // Templated + t_param_first_a #(2,5) a2 + ( + // Outputs + .varwidth (varwidth2[2:0]), + /*AUTOINST*/ + // Outputs + .par (par2[4:0])); // Templated + t_param_first_a #(THREE,5) a3 + ( + // Outputs + .varwidth (varwidth3[3:0]), + /*AUTOINST*/ + // Outputs + .par (par3[4:0])); // Templated + t_param_first_a #(THREE,5) a4 + ( + // Outputs + .varwidth (varwidth4[3:0]), + /*AUTOINST*/ + // Outputs + .par (par4[4:0])); // Templated + + parameter THREE_BITS_WIDE = 3'b011; + parameter THREE_2WIDE = 2'b11; + parameter ALSO_THREE_WIDE = THREE_BITS_WIDE; + parameter THREEPP_32_WIDE = 2*8*2+3; + parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide + + // Width propagation doesn't care about LHS vs RHS + // But the width of a RHS/LHS on a upper node does affect lower nodes; + // Thus must double-descend in width analysis. + // VCS 7.0.1 is broken on this test! + parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop; + parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop; + + // Parameters assign LHS is affectively width zero. + parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop; + parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop; + + // Must be careful about LSB's with extracts + parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop; + + // + parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3; + parameter THREE_32_WIDE = 3%32; + parameter THIRTYTWO = 2; // Param is 32 bits + parameter [40:0] WIDEPARAM = 41'h12_3456789a; + parameter [40:0] WIDEPARAM2 = WIDEPARAM; + + reg [7:0] eightb; + reg [3:0] fourb; + wire [7:0] eight = 8'b00010000; + wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE]; + wire [2:0] threebits = ALSO_THREE_WIDE; + + // surefire lint_off CWCCXX + + initial _ranit = 0; + + always @ (posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + $write("[%0t] t_param: Running\n", $time); + // + $write(" %d %d %d\n", par1,par2,par3); + if (par1!==5'd1) $stop; + if (par2!==5'd2) $stop; + if (par3!==5'd3) $stop; + if (par4!==5'd3) $stop; + if (varwidth1!==2'd2) $stop; + if (varwidth2!==3'd2) $stop; + if (varwidth3!==4'd2) $stop; + if (varwidth4!==4'd2) $stop; + if (threebits !== 3'b011) $stop; + if (eight !== 8'b00010000) $stop; + if (eight2two !== 2'b10) $stop; + $write(" Params = %b %b\n %b %b\n", + THREEPP_32_WIDE,THREEPP_3_WIDE, + THIRTYTWO, THREEPP_32P_WIDE); + if (THREEPP_32_WIDE !== 32'h23) $stop; + if (THREEPP_3_WIDE !== 3'h3) $stop; + if (THREEPP_32P_WIDE !== 32'h23) $stop; + if (THIRTYTWO[1:0] !== 2'h2) $stop; + if (THIRTYTWO !== 32'h2) $stop; + if (THIRTYTWO !== 2) $stop; + if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop; + if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop; + if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1 + // + // Example of assignment LHS affecting expression widths. + // verilator lint_off WIDTH + // surefire lint_off ASWCMB + // surefire lint_off ASWCBB + eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop; + fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop; + fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop; + // verilator lint_on WIDTH + // surefire lint_on ASWCMB + // surefire lint_on ASWCBB + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_first_a.v b/SVIncCompil/Testcases/Verilator/t_param_first_a.v new file mode 100644 index 0000000..4dbd52f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_first_a.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_param_first_a (/*AUTOARG*/ + // Outputs + varwidth, par + ); + + parameter X = 1; + parameter FIVE = 0; // Overridden + parameter TWO = 2; + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [4:0] par; // From b of t_param_first_b.v + output [X:0] varwidth; // From b of t_param_first_b.v + // End of automatics + + t_param_first_b #(X,FIVE,TWO) b + (/*AUTOINST*/ + // Outputs + .par (par[4:0]), + .varwidth (varwidth[X:0])); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_first_b.v b/SVIncCompil/Testcases/Verilator/t_param_first_b.v new file mode 100644 index 0000000..60d6304 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_first_b.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_param_first_b (/*AUTOARG*/ + // Outputs + par, varwidth + ); + + parameter X = 1; + parameter FIVE = 0; // Overridden + parameter TWO = 2; + + output [4:0] par; + output [X:0] varwidth; + + wire [4:0] par = X; + wire [X:0] varwidth = (FIVE==5)?TWO:0; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_func.v b/SVIncCompil/Testcases/Verilator/t_param_func.v new file mode 100644 index 0000000..4706a83 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_func.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This test examines Verilator against paramter definition with functions. +// Particularly the function takes in argument which is multi-dimentional. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Roland Kruse and Jie Xu. + +module test#( + parameter size = 4, + parameter p = sum({32'h1,32'h2,32'h3,32'h4}, size)) + + (input clk, + input logic sel, + output [p:0] res); + + logic [p:0] cc = 'h45; + + assign res = sel ? cc : {(p+1){1'b1}}; + + function integer sum; + input [3:0][31:0] values; + input int size; + + sum = 0; + + begin + for (int i = 0; i < size; i ++) + sum += values[i]; + end + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_if_blk.v b/SVIncCompil/Testcases/Verilator/t_param_if_blk.v new file mode 100644 index 0000000..1ff45e6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_if_blk.v
@@ -0,0 +1,140 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013. + +// bug648 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [7:0] datai = crc[7:0]; + wire enable = crc[8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [7:0] datao; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .datao (datao[7:0]), + // Inputs + .clk (clk), + .datai (datai[7:0]), + .enable (enable)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {56'h0, datao}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h9d550d82d38926fa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +`define FAIL 1 + +module Nested + ( + input logic clk, + input logic x, + output logic y + ); + logic t; + always_comb t = x ^ 1'b1; + + always_ff @(posedge clk) begin + if (clk) + y <= t; + end +endmodule + +module Test + ( + input logic clk, + input logic [7:0] datai, + input logic enable, + output logic [7:0] datao + ); + + // verilator lint_off BLKANDNBLK + logic [7:0] datat; + // verilator lint_on BLKANDNBLK + + for (genvar i = 0; i < 8; i++) begin + if (i%4 != 3) begin +`ifndef FAIL + logic t; + always_comb begin + t = datai[i] ^ 1'b1; + end + always_ff @(posedge clk) begin + if (clk) + datat[i] <= t; + end +`else + Nested nested_i + ( + .clk(clk), + .x(datai[i]), + .y(datat[i]) //<== via Vcellout wire + ); +`endif + + always_comb begin + casez (enable) + 1'b1: datao[i] = datat[i]; + 1'b0: datao[i] = '0; + default: datao[i] = 'x; + endcase + end + end + else begin + always_ff @(posedge clk) begin + if (clk) + datat[i] <= 0; //<== assign delayed + end + always_comb begin + casez (enable) + 1'b1: datao[i] = datat[i] ^ 1'b1; + 1'b0: datao[i] = '1; + default: datao[i] = 'x; + endcase + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_local.v b/SVIncCompil/Testcases/Verilator/t_param_local.v new file mode 100644 index 0000000..a500bf9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_local.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + a, y + ); + + input [1:0] a; + output [3:0] y; + + Test #(.C(2)) + test (.*); +endmodule + +module Test + #(C = 3, + localparam O = 1 << C) + (input [C-1:0] a, + output reg [O-1:0] y); + initial begin + if (O != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_long.v b/SVIncCompil/Testcases/Verilator/t_param_long.v new file mode 100644 index 0000000..ebf6c0a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_long.v
@@ -0,0 +1,174 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + parameter PAR = 3; + input clk; + + defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; + defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG"; + defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG"; + defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG"; + + i i (.clk(clk)); + + integer cyc=1; + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module i + (/*AUTOARG*/ + // Inputs + clk + ); + + // verilator public_module + + input clk; + + parameter [255:0] L00 = 256'h0; + parameter [255:0] L01 = 256'h0; + parameter [255:0] L02 = 256'h0; + parameter [255:0] L03 = 256'h0; + parameter [255:0] L04 = 256'h0; + parameter [255:0] L05 = 256'h0; + parameter [255:0] L06 = 256'h0; + parameter [255:0] L07 = 256'h0; + parameter [255:0] L08 = 256'h0; + parameter [255:0] L09 = 256'h0; + parameter [255:0] L0A = 256'h0; + parameter [255:0] L0B = 256'h0; + parameter [255:0] L0C = 256'h0; + parameter [255:0] L0D = 256'h0; + parameter [255:0] L0E = 256'h0; + parameter [255:0] L0F = 256'h0; + parameter [255:0] L10 = 256'h0; + parameter [255:0] L11 = 256'h0; + parameter [255:0] L12 = 256'h0; + parameter [255:0] L13 = 256'h0; + parameter [255:0] L14 = 256'h0; + parameter [255:0] L15 = 256'h0; + parameter [255:0] L16 = 256'h0; + parameter [255:0] L17 = 256'h0; + parameter [255:0] L18 = 256'h0; + parameter [255:0] L19 = 256'h0; + parameter [255:0] L1A = 256'h0; + parameter [255:0] L1B = 256'h0; + parameter [255:0] L1C = 256'h0; + parameter [255:0] L1D = 256'h0; + parameter [255:0] L1E = 256'h0; + parameter [255:0] L1F = 256'h0; + parameter [255:0] L20 = 256'h0; + parameter [255:0] L21 = 256'h0; + parameter [255:0] L22 = 256'h0; + parameter [255:0] L23 = 256'h0; + parameter [255:0] L24 = 256'h0; + parameter [255:0] L25 = 256'h0; + parameter [255:0] L26 = 256'h0; + parameter [255:0] L27 = 256'h0; + parameter [255:0] L28 = 256'h0; + parameter [255:0] L29 = 256'h0; + parameter [255:0] L2A = 256'h0; + parameter [255:0] L2B = 256'h0; + parameter [255:0] L2C = 256'h0; + parameter [255:0] L2D = 256'h0; + parameter [255:0] L2E = 256'h0; + parameter [255:0] L2F = 256'h0; + parameter [255:0] L30 = 256'h0; + parameter [255:0] L31 = 256'h0; + parameter [255:0] L32 = 256'h0; + parameter [255:0] L33 = 256'h0; + parameter [255:0] L34 = 256'h0; + parameter [255:0] L35 = 256'h0; + parameter [255:0] L36 = 256'h0; + parameter [255:0] L37 = 256'h0; + parameter [255:0] L38 = 256'h0; + parameter [255:0] L39 = 256'h0; + parameter [255:0] L3A = 256'h0; + parameter [255:0] L3B = 256'h0; + parameter [255:0] L3C = 256'h0; + parameter [255:0] L3D = 256'h0; + parameter [255:0] L3E = 256'h0; + parameter [255:0] L3F = 256'h0; + parameter [255:0] A0 = 256'h0; + parameter [255:0] A1 = 256'h0; + parameter [255:0] A2 = 256'h0; + + always @ (posedge clk) begin + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_mem_attr.v b/SVIncCompil/Testcases/Verilator/t_param_mem_attr.v new file mode 100644 index 0000000..0499d40 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_mem_attr.v
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test case for parameterized module. +// +// When a module is instantiatied with parameter, there will be two modules in +// the tree and eventually one will be removed after param and deadifyModules. +// +// This test is to check that the removal of dead module will not cause +// compilation error. Possible error was/is seen as: +// +// pure virtual method called +// terminate called without an active exception +// %Error: Verilator aborted. Consider trying --debug --gdbbt +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jie Xu. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + wire [71:0] ctrl; + wire [7:0] cl; // this line is added + + memory #(.words(72)) i_memory (.clk (clk)); + + assign ctrl = i_memory.mem[0]; + assign cl = i_memory.mem[0][7:0]; // and this line +endmodule + + +// memory module, which is used with parameter +module memory (clk); + input clk; + + parameter words = 16384, bits = 72; + + reg [bits-1 :0] mem[words-1 : 0]; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_module.v b/SVIncCompil/Testcases/Verilator/t_param_module.v new file mode 100644 index 0000000..3ba3d5d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_module.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This test case is used for testing a modeule parameterized with a typed +// localparam. +// +// We find Verilator appears to mis-evaluate the parameter WIDTH as -16 when +// used in the test module to set the value of MSB. A number of warnings and +// errors follow, starting with: +// +// %Warning-LITENDIAN: t/t_param_module.v:42: Little bit endian vector: MSB +// < LSB of bit range: -17:0 +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2013 by Jie Xu. + +// bug606 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + localparam logic[4:0] WID = 16; + //localparam WID = 16; // No problem if defined like this + wire [15:0] b33; + + test #(WID) i_test_33(.clk (clk), + .b (b33)); + +endmodule + + +module test (/*AUTOARG*/ + //Inputs + clk, + // Outputs + b + ); + parameter WIDTH = 10; + localparam MSB = WIDTH - 1; + + input clk; + output wire [MSB:0] b; + + wire [MSB:0] a; + assign b = {~a[MSB-1:0], clk}; + + initial begin + if ($bits(WIDTH)!=5) $stop; // Comes from the parent! + if ($bits(MSB)!=32) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_named.v b/SVIncCompil/Testcases/Verilator/t_param_named.v new file mode 100644 index 0000000..bdbc290 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_named.v
@@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + parameter PAR = 3; + input clk; + +`ifdef verilator + // Else it becomes a localparam, per IEEE 4.10.1, but we don't check it + defparam m3.FROMDEFP = 19; +`endif + + m3 #(.P3(PAR), + .P2(2)) + m3(.clk(clk)); + + integer cyc=1; + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module m3 + #( + parameter UNCH = 99, + parameter P1 = 10, + parameter P2 = 20, + P3 = 30 + ) + (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + localparam LOC = 13; + + parameter FROMDEFP = 11; + + initial begin + $display("%x %x %x",P1,P2,P3); + end + always @ (posedge clk) begin + if (UNCH !== 99) $stop; + if (P1 !== 10) $stop; + if (P2 !== 2) $stop; + if (P3 !== 3) $stop; +`ifdef verilator + if (FROMDEFP !== 19) $stop; +`endif + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_named_2.v b/SVIncCompil/Testcases/Verilator/t_param_named_2.v new file mode 100644 index 0000000..f4e4126 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_named_2.v
@@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + parameter PAR = 3; + input clk; + + m3 m3_inst (.clk(clk)); + defparam m3_inst.FROMDEFP = 19; + defparam m3_inst.P2 = 2; + //defparam m3_inst.P3 = PAR; + defparam m3_inst.P3 = 3; + + integer cyc=1; + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module m3 + (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + localparam LOC = 13; + + parameter UNCH = 99; + parameter P1 = 10; + parameter P2 = 20; + parameter P3 = 30; + + parameter FROMDEFP = 11; + + initial begin + $display("%x %x %x",P1,P2,P3); + end + always @ (posedge clk) begin + if (UNCH !== 99) $stop; + if (P1 !== 10) $stop; + if (P2 !== 2) $stop; + if (P3 !== 3) $stop; + if (FROMDEFP !== 19) $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_no_parentheses.v b/SVIncCompil/Testcases/Verilator/t_param_no_parentheses.v new file mode 100644 index 0000000..f992cbe --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_no_parentheses.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. +// +// This is a copy of t_param.v with the parentheses around the module parameters +// removed. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + parameter PAR = 3; + + m1 #PAR m1(); + m3 #PAR m3(); + mnooverride #10 mno(); + + input clk; + integer cyc=1; + reg [4:0] bitsel; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + bitsel = 0; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 1; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 2; + if (PAR[bitsel]!==1'b0) $stop; + end + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module m1; + localparam PAR1MINUS1 = PAR1DUP-2-1; + localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly + parameter PAR1 = 0; + m2 #PAR1MINUS1 m2 (); +endmodule + +module m2; + parameter PAR2 = 10; + initial begin + $display("%x",PAR2); + if (PAR2 !== 2) $stop; + end +endmodule + +module m3; + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 3) $stop; + end +endmodule + +module mnooverride; + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 10) $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_package.v b/SVIncCompil/Testcases/Verilator/t_param_package.v new file mode 100644 index 0000000..21be7f1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_package.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module + +module t; + Test0 t0 (.val0('0)); + Test1 t1 (.val1('0)); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +package params; + parameter P = 7; +endpackage + +module Test0 (val0); + parameter Z = 1; + input [Z : 0] val0; +endmodule + +module Test1 (val1); + input logic [params::P : 0] val1; // Fully qualified parameter +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_public.v b/SVIncCompil/Testcases/Verilator/t_param_public.v new file mode 100644 index 0000000..e8b815f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_public.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +//bug505 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + a #(1) a1 (); + b #(2) b2 (); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module a; + parameter ONE /*verilator public*/ = 22; + initial if (ONE != 1) $stop; +`ifdef VERILATOR + initial if ($c32("ONE") != 1) $stop; +`endif +endmodule + +module b #( + parameter TWO /*verilator public*/ = 22 + ); + initial if (TWO != 2) $stop; +`ifdef VERILATOR + initial if ($c32("TWO") != 2) $stop; +`endif +endmodule + +//bug804 +package p; + localparam INPACK /*verilator public*/ = 6; +endpackage
diff --git a/SVIncCompil/Testcases/Verilator/t_param_real.v b/SVIncCompil/Testcases/Verilator/t_param_real.v new file mode 100644 index 0000000..f7b1f4c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_real.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork + +module mod #( + parameter real HZ = 0 +); + //verilator no_inline_module + initial begin + if ((HZ-$floor(HZ)) - 0.45 > 0.01) $stop; + if ((HZ-$floor(HZ)) - 0.45 < -0.01) $stop; + end +endmodule + +module t(); + mod #(.HZ(123.45)) mod1(); + mod #(.HZ(24.45)) mod2(); + + initial begin + if (mod1.HZ != 123.45) $stop; + if (mod2.HZ != 24.45) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_real2.v b/SVIncCompil/Testcases/Verilator/t_param_real2.v new file mode 100644 index 0000000..dc49725 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_real2.v
@@ -0,0 +1,32 @@ +module foo +#( parameter real bar = 2.0) +(); + +endmodule + +module t(); + + genvar m, r; + generate + for (m = 10; m <= 20; m+=10) begin : gen_m + for (r = 0; r <= 1; r++) begin : gen_r + localparam real lparam = m + (r + 0.5); + initial begin + if (lparam != foo_inst.bar) begin + $display("%m: lparam != foo_inst.bar (%f, %f)", + lparam, foo_inst.bar); + $stop(); + end + end + + foo #(.bar (lparam)) foo_inst (); + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_repl.v b/SVIncCompil/Testcases/Verilator/t_param_repl.v new file mode 100644 index 0000000..2043bce --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_repl.v
@@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter [31:0] TWENTY4 = 24; + parameter [31:0] PA = TWENTY4/8; + parameter [1:0] VALUE = 2'b10; + parameter [5:0] REPL = {PA{VALUE}}; + parameter [7:0] CONC = {REPL,VALUE}; + + parameter DBITS = 32; + parameter INIT_BYTE = 8'h1F; + parameter DWORDS_LOG2 = 7; + parameter DWORDS = (1<<DWORDS_LOG2); + parameter DBYTES=DBITS/8; + // verilator lint_off LITENDIAN + reg [DBITS-1:0] mem [0:DWORDS-1]; + // verilator lint_on LITENDIAN + + integer i; + + integer cyc=1; + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + if (REPL != {2'b10,2'b10,2'b10}) $stop; + if (CONC != {2'b10,2'b10,2'b10,2'b10}) $stop; + end + if (cyc==2) begin + for (i = 0; i < DWORDS; i = i + 1) + mem[i] = {DBYTES{INIT_BYTE}}; + end + if (cyc==3) begin + for (i = 0; i < DWORDS; i = i + 1) + if (mem[i] != {DBYTES{INIT_BYTE}}) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_scope_bad.v b/SVIncCompil/Testcases/Verilator/t_param_scope_bad.v new file mode 100644 index 0000000..5c7fbf5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_scope_bad.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + value + ); + input [1:0] value; + + sub #(.CASEVAL(2'h0)) p0 (.value); + sub #(.CASEVAL(2'h1)) p1 (.value); + sub #(.CASEVAL(2'h2)) p2 (.value); + sub #(.CASEVAL(2'h3)) p3 (.value); + +endmodule + +module sub + ( + input [1:0] value); + + parameter [1:0] CASEVAL = 2'h0; + always_comb begin + case (value) + CASEVAL: ; + 2'h2: $stop; + default: ; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_seg.v b/SVIncCompil/Testcases/Verilator/t_param_seg.v new file mode 100644 index 0000000..1b87803 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_seg.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Mandy Xu. + +// verilator lint_off WIDTH + +//bug1088 + +module t (/*AUTOARG*/ + // Outputs + err_count, + // Inputs + clk, syndromes + ); + + input clk; + input [7:0] syndromes; + output reg [1:0] err_count = 0; + + localparam [95:0] M = 96'h4; + wire [3:0] syn1 = syndromes[0+:M]; + always @(posedge clk) begin + err_count <= {1'b0, |syn1}; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_sel.v b/SVIncCompil/Testcases/Verilator/t_param_sel.v new file mode 100644 index 0000000..e12ff52 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_sel.v
@@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test #(16,2) test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hf9b3a5000165ed38 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + output [31:0] out; + + parameter N = 0; + parameter PASSDOWN = 1; + + add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]), + .out (out)); + +endmodule + +module add (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + parameter PASSDOWN = 9999; + input [31:0] in; + output [31:0] out; + wire out = in + PASSDOWN; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_sel_range.v b/SVIncCompil/Testcases/Verilator/t_param_sel_range.v new file mode 100644 index 0000000..26bb6be --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_sel_range.v
@@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module + +// bug477 + +module t ( + input rst_n, + input clk, + output out + ); + + submod #(.STAGES(5)) u2(.*); + +endmodule + +module submod (/*AUTOARG*/ + // Outputs + out, + // Inputs + rst_n, clk + ); + + parameter STAGES = 4; + + input rst_n; + input clk; + output out; + + reg [STAGES-1:0] r_rst; + + generate + // for i=0..5 (5+1-1) + for (genvar i=0; i<STAGES+1-1; i=i+1) begin + always @(posedge clk or negedge rst_n) begin + if (~rst_n) + r_rst[i] <= 1'b0; + else begin + if (i==0) + r_rst[i] <= 1'b1; + else + r_rst[i] <= r_rst[i-1]; // i=0, so -1 wraps to 7 + end + end + end + endgenerate + + wire out = r_rst[STAGES-1]; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_shift.v b/SVIncCompil/Testcases/Verilator/t_param_shift.v new file mode 100644 index 0000000..cc493a1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_shift.v
@@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Mandy Xu. + +module t + #(parameter[95:0] P = 1) + (input clk); + + localparam [32:0] M = 4; + + function [M:0] gen_matrix; + gen_matrix[0] = 1>> M; + endfunction + + reg [95: 0] lfsr = 0; + always @(posedge clk) begin + lfsr <= (1 >> P); + end + + wire [95: 0] lfsr_w = 1 >> P; + + localparam [95: 0] lfsr_p = 1 >> P; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_type.v b/SVIncCompil/Testcases/Verilator/t_param_type.v new file mode 100644 index 0000000..7820f6e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_type.v
@@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // counters + int cnt; + int cnt_bit ; + int cnt_byte; + int cnt_int ; + int cnt_ar1d; + int cnt_ar2d; + + // sizes + int siz_bit ; + int siz_byte; + int siz_int ; + int siz_ar1d; + int siz_ar2d; + + // add all counters + assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; + + // finish report + always @ (posedge clk) + if (cnt == 5) begin + if (siz_bit != 1) $stop(); + if (siz_byte != 8) $stop(); + if (siz_int != 32) $stop(); + if (siz_ar1d != 24) $stop(); + if (siz_ar2d != 16) $stop(); + end else if (cnt > 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // instances with various types + mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); + mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); + mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); + mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); + mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); + +endmodule : t + + +module mod_typ #( + parameter type TYP = byte +)( + input logic clk, + output TYP cnt, + output int siz +); + + initial cnt = 0; + + always @ (posedge clk) + cnt <= cnt + 1; + + assign siz = $bits (cnt); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_type2.v b/SVIncCompil/Testcases/Verilator/t_param_type2.v new file mode 100644 index 0000000..e103c1c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_type2.v
@@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +package tt_pkg; + typedef enum logic [1:0] {L0, L1, L2, L3} test_t; +endpackage + +module t (/*AUTOARG*/ + // Outputs + ob + ); + + output [1:0] ob; + + import tt_pkg::*; + + test_t a; + test_t b; + + assign a = L0; + assign ob = b; + + tt_buf #(.T_t(test_t)) + u_test + (.i(a), .o(b)); + +endmodule + +module tt_buf + #( + parameter type T_t = logic [0:0] + ) + ( + input T_t i, + output T_t o + ); + assign o = i; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_up_bad.v b/SVIncCompil/Testcases/Verilator/t_param_up_bad.v new file mode 100644 index 0000000..d69afcb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_up_bad.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Ian Thompson. + +//bug1099 + +typedef struct packed { + logic foo; +} some_struct_t; + +module child (); + logic a_bad; + // bar is in the parent module, but illegal to reference without module name + assign a_bad = bar.foo; +endmodule + +module parent + #( + parameter PARAM = 0 + ) + ( + ); + some_struct_t bar; + child c (); +endmodule + +module t (); + // The parameter must be anything other than the default + parent #( 1 ) p (); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_value.v b/SVIncCompil/Testcases/Verilator/t_param_value.v new file mode 100644 index 0000000..5aed9de --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_value.v
@@ -0,0 +1,63 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2012 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/); + +`define ASSERT(x) initial if (!(x)) $stop + // See IEEE 6.20.2 on value parameters + + localparam unsigned [63:0] UNSIGNED =64'h99934567_89abcdef; + localparam signed [63:0] SIGNED =64'sh99934567_89abcdef; + localparam real REAL=1.234; + `ASSERT(UNSIGNED > 0); + `ASSERT(SIGNED < 0); + + // bullet 1 + localparam A1_WIDE = UNSIGNED; + `ASSERT($bits(A1_WIDE)==64); + + localparam A2_REAL = REAL; + `ASSERT(A2_REAL == 1.234); + + localparam A3_SIGNED = SIGNED; + `ASSERT($bits(A3_SIGNED)==64 && A3_SIGNED < 0); + + localparam A4_EXPR = (2'b01 + 2'b10); + `ASSERT($bits(A4_EXPR)==2 && A4_EXPR==2'b11); + + // bullet 2 + localparam [63:0] B_UNSIGNED = SIGNED; + `ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0); + + // bullet 3 + localparam signed C_SIGNED = UNSIGNED; + `ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0); + + localparam unsigned C_UNSIGNED = SIGNED; + `ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0); + + // bullet 4 + // verilator lint_off WIDTH + localparam signed [59:0] D_SIGNED = UNSIGNED; + `ASSERT($bits(D_SIGNED)==60 && D_SIGNED < 0); + // verilator lint_on WIDTH + + // verilator lint_off WIDTH + localparam unsigned [59:0] D_UNSIGNED = SIGNED; + `ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0); + // verilator lint_on WIDTH + + // bullet 6 + localparam UNSIZED = 23; + `ASSERT($bits(UNSIZED)>=32); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_while.v b/SVIncCompil/Testcases/Verilator/t_param_while.v new file mode 100644 index 0000000..211be1f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_while.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +//bug505 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter WIDTH = 33; + localparam MAX_WIDTH = 11; + localparam NUM_OUT = num_out(WIDTH); + + wire [NUM_OUT-1:0] z; + + function integer num_out; + input integer width; + num_out = 1; + while ((width + num_out - 1) / num_out > MAX_WIDTH) + num_out = num_out * 2; + endfunction + + initial begin + if (NUM_OUT != 4) $stop; + if ($bits(z) != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_param_wide_io.v b/SVIncCompil/Testcases/Verilator/t_param_wide_io.v new file mode 100644 index 0000000..d10a8ca --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_param_wide_io.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +// issue 1991 + +module t + #( + parameter[96:0] P = 97'h12344321_12344321_12344327 + ) + ( + input [P&7 - 1:0] in, + output [P&7 - 1:0] out + ); + + assign out = in; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_parse_delay.v b/SVIncCompil/Testcases/Verilator/t_parse_delay.v new file mode 100644 index 0000000..ba51cba --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_parse_delay.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/); + + // verilator lint_off WIDTH + reg [6:0] myreg1; + + initial begin + myreg1 = # 100 7'd0; + myreg1 = # 100 'b0; // [#] [100] ['b0] + myreg1 = #100'b0; // [#] [100] ['b0] + myreg1 = 100'b0; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_past.v b/SVIncCompil/Testcases/Verilator/t_past.v new file mode 100644 index 0000000..2388be2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_past.v
@@ -0,0 +1,98 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[31:0])); + + Test2 test2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[31:0])); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + + reg [31:0] dly0; + reg [31:0] dly1; + reg [31:0] dly2; + reg [31:0] dly3; + + // If called in an assertion, sequence, or property, the appropriate clocking event. + // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. + // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. + // Otherwise, if called in a procedure, the inferred clock + // Otherwise, default clocking + + always @(posedge clk) begin + dly0 <= in; + dly1 <= dly0; + dly2 <= dly1; + dly3 <= dly2; + // $past(expression, ticks, expression, clocking) + // In clock expression + if (dly0 != $past(in)) $stop; + if (dly0 != $past(in,1)) $stop; + if (dly1 != $past(in,2)) $stop; + end + + assert property (@(posedge clk) dly0 == $past(in)); + +endmodule + +module Test2 (/*AUTOARG*/ + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + + reg [31:0] dly0; + reg [31:0] dly1; + + default clocking @(posedge clk); endclocking + assert property (@(posedge clk) dly1 == $past(in, 2)); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_past_bad.v b/SVIncCompil/Testcases/Verilator/t_past_bad.v new file mode 100644 index 0000000..0bada01 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_past_bad.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (d, clk); + input d; + input clk; + + always @ (posedge clk) begin + if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >- 0 + if ($past(d, 10000)) $stop; // TICKCOUNT + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_past_unsup_bad.v b/SVIncCompil/Testcases/Verilator/t_past_unsup_bad.v new file mode 100644 index 0000000..2ee5017 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_past_unsup_bad.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (d, clk); + input d; + input clk; + + always @ (posedge clk) begin + // Unsupported + if ($past(d, 0, 0, 0)) $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_pipe_filter.v b/SVIncCompil/Testcases/Verilator/t_pipe_filter.v new file mode 100644 index 0000000..42930b3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pipe_filter.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +//=========================================================================== +// Includes + + +example line 10; +example line 11; + +`include "t_pipe_filter_inc.vh" +// Twice to check caching of includes +`include "t_pipe_filter_inc.vh" + +example line 15; +example line 16;
diff --git a/SVIncCompil/Testcases/Verilator/t_pipe_filter_inc.vh b/SVIncCompil/Testcases/Verilator/t_pipe_filter_inc.vh new file mode 100644 index 0000000..021ede6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pipe_filter_inc.vh
@@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +inc line 6; +inc line 7; // example_lint_off_line FOO +inc line 8; // example_lint_off_line BAR +inc line 9;
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_circdef_bad.v b/SVIncCompil/Testcases/Verilator/t_pp_circdef_bad.v new file mode 100644 index 0000000..7db7add --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_circdef_bad.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. +// +// bug445 + +`define WIDTH 12 +`define SEL_NUM_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS +`define SEL_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS +`define ADDR_BITS 0 +: `WIDTH-`SEL_NUM_BITS + +typedef logic [`SEL_NUM_BITS-1:0] d_t;
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_display.v b/SVIncCompil/Testcases/Verilator/t_pp_display.v new file mode 100644 index 0000000..1cbd456 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_display.v
@@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + wire d1 = 1'b1; + wire d2 = 1'b1; + wire d3 = 1'b1; + wire o1,o2,o3; + add1 add1 (d1,o1); + add2 add2 (d2,o2); + +`define ls left_side +`define rs right_side +`define noarg na//note extra space +`define thru(x) x +`define thruthru `ls `rs // Doesn't expand +`define msg(x,y) `"x: `\`"y`\`"`" +`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string + initial begin + //$display(`msg( \`, \`)); // Illegal + $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); + $display(`msg(left side,right side)); + $display(`msg( left side , right side )); + $display(`msg( `ls , `rs )); + $display(`msg( `noarg , `rs )); + $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); + $display(`msg(`noarg,`noarg`noarg)); + $display(`msg( `thruthru , `thruthru )); // Results vary between simulators + $display(`left(`msg( left side , right side ), left_replaced)); + //$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error +`ifndef VCS // Sim bug - wrong number of arguments, but we're right + $display(`msg(`thru(),)); // Empty +`endif + $display(`msg(`thru(left side),`thru(right side))); + $display(`msg( `thru( left side ) , `thru( right side ) )); +`ifndef NC + $display(`"standalone`"); +`endif + +`ifdef VERILATOR + // Illegal on some simulators, as the "..." crosses two lines +`define twoline first \ + second + $display(`msg(twoline, `twoline)); +`endif + + $display("Line %0d File \"%s\"",`__LINE__,`__FILE__); + + //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +`define ADD_UP(a,c) \ +wire tmp_``a = a; \ +wire tmp_``c = tmp_``a + 1; \ +assign c = tmp_``c ; + +module add1 ( input wire d1, output wire o1); + `ADD_UP(d1,o1) // expansion is OK +endmodule +module add2 ( input wire d2, output wire o2); + `ADD_UP( d2 , o2 ) // expansion is bad +endmodule +// `ADD_UP( \d3 , \o3 ) // This really is illegal
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_dupdef.v b/SVIncCompil/Testcases/Verilator/t_pp_dupdef.v new file mode 100644 index 0000000..19a3dd5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_dupdef.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + +`define DUP fred +`define DUP barney + +`define DUPP paramed(x) (x) +`define DUPP paramed(x,z) (x*z) + + initial $stop; // Should have failed + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_lib.v b/SVIncCompil/Testcases/Verilator/t_pp_lib.v new file mode 100644 index 0000000..4c066fb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_lib.v
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`include "t_pp_lib_inc.vh" +module t(); + wire [`WIDTH-1:0] a; + library_cell n1(a); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_lib_inc.vh b/SVIncCompil/Testcases/Verilator/t_pp_lib_inc.vh new file mode 100644 index 0000000..4c32a16 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_lib_inc.vh
@@ -0,0 +1,6 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`define WIDTH 10
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_lib_library.v b/SVIncCompil/Testcases/Verilator/t_pp_lib_library.v new file mode 100644 index 0000000..1059eed --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_lib_library.v
@@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module library_cell(a); + input [`WIDTH-1:0] a; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_misdef_bad.v b/SVIncCompil/Testcases/Verilator/t_pp_misdef_bad.v new file mode 100644 index 0000000..1a2eaa1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_misdef_bad.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t; +`define DEFINED + + // NDEFINED isn't defined here: + `NDEFINED + + // Botched directive (`timescale) + `imescale + + initial $stop; // Should have failed + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_pragmas.v b/SVIncCompil/Testcases/Verilator/t_pp_pragmas.v new file mode 100644 index 0000000..83ff9c1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_pragmas.v
@@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`timescale 1ns/10ps +`verilog + +`suppress_faults +`nosuppress_faults +`enable_portfaults +`disable_portfaults + +`delay_mode_distributed +`delay_mode_path +`delay_mode_unit +`delay_mode_zero + +`default_decay_time 1 +`default_decay_time 1.0 +`default_decay_time infinite +// unsupported (recommended not to): `default_trireg_strength 10 + +`default_nettype wire +// unsupported: `default_nettype tri +// unsupported: `default_nettype tri0 +// unsupported: `default_nettype wand +// unsupported: `default_nettype triand +// unsupported: `default_nettype wor +// unsupported: `default_nettype trior +// unsupported: `default_nettype trireg +`default_nettype none + +`autoexpand_vectornets + +`accelerate +`noaccelerate +`expand_vectornets +`noexpand_vectornets +`remove_gatenames +`noremove_gatenames +`remove_netnames +`noremove_netnames +`resetall + +// unsupported: `unconnected_drive pull1 +// unsupported: `unconnected_drive pull0 +`nounconnected_drive + +`line 100 "hallo.v" 0 + +// unsupported: `uselib file=../moto_lib.v +// unsupported: `uselib dir=../lib.dir libext=.v + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_pp_underline_bad.v b/SVIncCompil/Testcases/Verilator/t_pp_underline_bad.v new file mode 100644 index 0000000..28e1b26 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_pp_underline_bad.v
@@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t; + // verilator_no_inline_module + initial $stop; // Should have failed +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc.v b/SVIncCompil/Testcases/Verilator/t_preproc.v new file mode 100644 index 0000000..1898dd9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc.v
@@ -0,0 +1,654 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2011 by Wilson Snyder. + +//=========================================================================== +// Includes +`include "t_preproc_inc2.vh" + +//=========================================================================== +// Comments + +/* verilator pass_thru comment */ + +// verilator pass_thru_comment2 + +//=========================================================================== +// Defines + +`define DEF_A3 +`define DEF_A1 +// DEF_A0 set by command line + wire [3:0] q = { + `ifdef DEF_A3 1'b1 `else 1'b0 `endif , + `ifdef DEF_A2 1'b1 `else 1'b0 `endif , + `ifdef DEF_A1 1'b1 `else 1'b0 `endif , + `ifdef DEF_A0 1'b1 `else 1'b0 `endif + }; + +text. + +`define FOOBAR foo /*this */ bar /* this too */ +`define FOOBAR2 foobar2 // but not +`FOOBAR +`FOOBAR2 + +`define MULTILINE first part \ + second part \ + third part + +`define MOREMULTILINE {\ + a,\ + b,\ + c} + +/*******COMMENT*****/ +`MULTILINE +`MOREMULTILINE +Line_Preproc_Check `__LINE__ + +//=========================================================================== + +`define syn_negedge_reset_l or negedge reset_l + +`define DEEP deep +`define DEEPER `DEEP `DEEP +`DEEPER + +`define nosubst NOT_SUBSTITUTED +`define WITHTICK "`nosubst" +"Inside: `nosubst" +`WITHTICK + +`define withparam(a, b) a b LLZZ a b +`withparam(x,y) +`withparam(`withparam(p,q),`withparam ( r , s )) + +`withparam(firstline + , + comma","line) + +`define withquote(a, bar) a bar LLZZ "a" bar +`withquote( x , y) // Simulators disagree here; some substitute "a" others do not + +`define noparam (a,b) +`noparam(a,b) + +`define msg(x,y) `"x: `\`"y`\`"`" +$display(`msg(left side, right side)) + +`define foo(f) f``_suffix +`foo(bar) more + +`define zap(which) \ + $c("Zap(\"",which,"\");"); +`zap(bug1); +`zap("bug2"); + +/* Define inside comment: `DEEPER and `WITHTICK */ +// More commentary: `zap(bug1); `zap("bug2"); + +//====================================================================== +// display passthru + +`define ls left_side +`define rs right_side +`define noarg na +`define thru(x) x +`define thruthru `ls `rs // Doesn't expand +`define msg(x,y) `"x: `\`"y`\`"`" + initial begin + //$display(`msg( \`, \`)); // Illegal + $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); + $display(`msg(left side,right side)); + $display(`msg( left side , right side )); + $display(`msg( `ls , `rs )); + $display(`msg( `noarg , `rs )); + $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); + $display(`msg(`noarg,`noarg`noarg)); + $display(`msg( `thruthru , `thruthru )); // Results vary between simulators + $display(`msg(`thru(),)); // Empty + $display(`msg(`thru(left side),`thru(right side))); + $display(`msg( `thru( left side ) , `thru( right side ) )); + $display(`"standalone`"); + + // Unspecified when the stringification has multiple lines +`define twoline first \ + second + $display(`msg(twoline, `twoline)); + //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +//====================================================================== +// rt.cpan.org bug34429 + +`define ADD_UP(a,c) \ +wire tmp_``a = a; \ +wire tmp_``c = tmp_``a + 1; \ +assign c = tmp_``c ; + +module add1 ( input wire d1, output wire o1); + `ADD_UP(d1,o1) // expansion is OK +endmodule +module add2 ( input wire d2, output wire o2); + `ADD_UP( d2 , o2 ) // expansion is bad +endmodule + + `define check(mod, width, flopname, gate, path) \ + generate for (i=0; i<(width); i=i+1) begin \ + psl cover { path.d[i] & ~path.q[i] & !path.cond & (gate)} report `"fondNoRise: mod.flopname`"; \ + psl cover { ~path.d[i] & path.q[i] & !path.cond & (gate)} report `"fondNoFall: mod.flopname`"; \ + end endgenerate + +// parameterized macro with arguments that are macros + `define MK m5k.f + `define MF `MK .ctl + `define CK_fr (`MF.alive & `MF.alive_m1) + + `check(m5kc_fcl, 3, _ctl_mvldx_m1, `CK_fr, `MF._ctl_mvldx_m1) // ignorecmt + +//====================================================================== +// Quotes are legal in protected blocks. Grr. +module prot(); +`protected + I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) + #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] +`endprotected +endmodule +//" + +//====================================================================== +// macro call with define that has comma +`define REG_H 6 +`define REG_L 7 +`define _H regs[`REG_H] +`define _L regs[`REG_L] +`define _HL {`_H, `_L} +`define EX_WRITE(ad, da) begin addr <= (ad); wdata <= (da); wr <= 1; end +`define EX_READ(ad) begin addr <= (ad); rd <= 1; end + +`EX_READ((`_HL + 1)) and `EX_WRITE((`_HL), rdata) +`EX_READ(`_HL + 1) +`EX_WRITE(`_HL, rdata) more + +//====================================================================== +// include of parameterized file +`define INCNAME "t_preproc_inc4.vh" +`include `INCNAME +`ifndef T_PREPROC_INC4 + `error "No Inc4" +`endif +`undef T_PREPROC_INC4 + +`ifdef NOT_DEFINED_INC + `include NOT_DEFINED_INC +`endif + +//====================================================================== +// macro call with , in {} + +`define xxerror(logfile, msg) $blah(logfile,msg) +`xxerror("ab,cd","e,f"); +`xxerror(this.logfile, vec); +`xxerror(this.logfile, vec[1,2,3]); +`xxerror(this.logfile, {blah.name(), " is not foo"}); + +//====================================================================== +// pragma/default net type + +`pragma foo = 1 +`default_nettype none +`default_nettype uwire + +//====================================================================== +// Ifdef + +`define EMPTY_TRUE +`ifndef EMPTY_TRUE + `error "Empty is still true" +`endif +Line_Preproc_Check `__LINE__ + +//====================================================================== +// bug84 + +`define ARGPAR(a, // Hello, comments MIGHT not be legal + /*more,,)cmts*/ b // But newlines ARE legal... who speced THAT? + ) (a,b) +`ARGPAR(p,q) +`ARGPAR( //Here + x, + y //Too + ) +Line_Preproc_Check `__LINE__ + +//====================================================================== +// defines split arguments + +`define BEGIN begin +`define END end +`define BEGINEND `BEGIN`END +`define quoteit(x) `"x`" +`BEGIN`END // 2001 spec doesn't require two tokens, so "beginend" ok +`BEGINEND // 2001 spec doesn't require two tokens, so "beginend" ok +`quoteit(`BEGIN`END) // No space "beginend" + +//====================================================================== +// bug106 +`define \esc`def got_escaped +`ifdef \esc`def + `\esc`def +`endif +Not a \`define + +//====================================================================== +// misparsed comma in submacro +`define sb bee +`define appease_emacs_paren_matcher ( +`define sa(l) x,y) +`define sfoo(q,r) q--r +`sfoo(`sa(el),`sb) submacro has comma paren + +//====================================================================== +// bug191 +`define bug191(bits) $display("bits %d %d", $bits(foo), bits); +`bug191(10) + +//====================================================================== +// 1800-2009 +`define UDALL +`ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif +`undefineall +`ifdef UDALL `error "undefineall failed" `endif +`ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif + +//====================================================================== +// bug202 +`define FC_INV3(out, in) \ + `ifdef DC \ + cell \inv_``out <$typeof(out)> (.a(<in>), .o(<out>)); \ + /* multi-line comment \ + multi-line comment */ \ + `else \ + `ifdef MACRO_ATTRIBUTE \ + (* macro_attribute = `"INV (out``,in``)`" *) \ + `endif \ + assign out = ~in ; \ + `endif + +`FC_INV3(a3,b3) + +`define /* multi \ + line1*/ \ + bug202( i /*multi \ + line2*/ \ + ) \ + /* multi \ + line 3*/ \ + def i \ + +`bug202(foo) + +//====================================================================== + +`define CMT1 // verilator NOT IN DEFINE +`define CMT2 /* verilator PART OF DEFINE */ +`define CMT3 /* verilator NOT PART + OF DEFINE */ +`define CMT4 /* verilator PART \ + OF DEFINE */ +`define CMT5 // CMT NOT \ + also in // BUT TEXT IS \ + also3 // CMT NOT + +1 `CMT1 (nodef) +2 `CMT2 (hasdef) +3 `CMT3 (nodef) +4 `CMT4 (nodef) +5 `CMT5 (nodef) +`define NL HAS a NEW \ +LINE +`NL + +//====================================================================== + +`define msg_fatal(log, msg) \ + do \ + /* synopsys translate_off */ \ +`ifdef NEVER \ + `error "WTF" \ +`else \ + if (start(`__FILE__, `__LINE__)) begin \ +`endif \ + message(msg); \ + end \ + /* synopsys translate_on */ \ + while(0) + +`define msg_scen_(cl) cl``_scen +`define MSG_MACRO_TO_STRING(x) `"x`" + +EXP: clxx_scen +`msg_scen_(clxx) +EXP: clxx_scen +`MSG_MACRO_TO_STRING(`msg_scen_(clxx)) +`define mf(clx) `msg_fatal(this.log, {"Blah-", `MSG_MACRO_TO_STRING(`msg_scen_(clx)), " end"}); +EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); +`mf(clx) + +//====================================================================== + +`define makedefine(name) \ + `define def_``name This is name \ + `define def_``name``_2 This is name``_2 \ + +`makedefine(fooed) +`ifndef def_fooed `error "No def_fooed" `endif +//`ifndef def_fooed_2 `error "No def_fooed_2" `endif +EXP: This is fooed +`def_fooed +EXP: This is fooed_2 +`def_fooed_2 + +//====================================================================== +`define NOPARAM() np +`NOPARAM() +`NOPARAM( ) +//====================================================================== +// It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? +`define NODS_DEFINED +`define NODS_INDIRECT(x) x +`ifndef `NODS_INDIRECT(NODS_DEFINED) + `error "Indirect failed" +`endif +`ifdef `NODS_INDIRECT(NODS_UNDEFINED) + `error "Indirect2 failed" +`endif +//====================================================================== +// Metaprogramming +`define REPEAT_0(d) +`define REPEAT_1(d) d +`define REPEAT_2(d) `REPEAT_1(d)d +`define REPEAT_3(d) `REPEAT_2(d)d +`define REPEAT_4(d) `REPEAT_3(d)d + +`define CONCAT(a, b) a``b +`define REPEATC(n, d) `CONCAT(`REPEAT_, n)(d) +`define REPEATT(n, d) `REPEAT_``n(d) + +`REPEATC(3, hello3 ) +`REPEATT(4, hello4 ) +//====================================================================== +// Include from stringification +`undef T_PREPROC_INC4 +`define NODS_CONC_VH(m) `"m.vh`" +`include `NODS_CONC_VH(t_preproc_inc4) +`ifndef T_PREPROC_INC4 `error_here `endif +//====================================================================== +// Defines doing defines +// Note the newline on the end - required to form the end of a define +`define DEFINEIT(d) d \ + +`define _DEFIF_Z_0 1 +`define DEFIF_NZ(d,n) `undef d `ifndef _DEFIF_Z_``n `DEFINEIT(`define d 1) `endif +`DEFIF_NZ(TEMP,1) +`ifndef TEMP `error "bad" `endif +`DEFIF_NZ(TEMP,0) +`ifdef TEMP `error "bad0" `endif +Line_Preproc_Check `__LINE__ +//====================================================================== +// Quoted multiline - track line numbers, and insure \\n gets propagated +`define MULQUOTE "FOO \ + BAR " +`define MULQUOTE2(mq) `MULQUOTE mq `MULQUOTE +Line_Preproc_Check `__LINE__ +`MULQUOTE2("arg_line1 \ + arg_line2") +Line_Preproc_Check `__LINE__ +//====================================================================== +// bug283 + +`define A a +`define B b +`define C c +// EXP: abc +`define C5 `A``b```C +`C5 +`undef A +`undef B +`undef C + +`define XTYPE sonet +`define XJOIN(__arg1, __arg2) __arg1``__arg2 +`define XACTION `XJOIN(`XTYPE, _frame) +EXP: sonet_frame +`XACTION +// +`define XFRAME frame +`define XACTION2 `XJOIN(sonet_, `XFRAME) +EXP: sonet_frame +`XACTION2 +// This result varies between simulators +`define sonet_frame other_frame +`define XACTION3 `XTYPE``_frame +EXP: sonet_frame +`XACTION3 + +// The existance of non-existance of a base define can make a difference +`define QA_b zzz +`define Q1 `QA``_b +EXP: module zzz ; endmodule +module `Q1 ; endmodule +module `Q1 ; endmodule + +`define QA a +EXP: module a_b ; endmodule +module `Q1 ; endmodule +module `Q1 ; endmodule + +//====================================================================== +// bug311 +integer/*NEED_SPACE*/foo; +//====================================================================== +// bug441 +module t; + //----- + // case provided + // note this does NOT escape as suggested in the mail +`define LEX_CAT(lexem1, lexem2) lexem1``lexem2 +`define LEX_ESC(name) \name \ + + initial begin : `LEX_ESC( `LEX_CAT(a[0],_assignment) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end + //----- + // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from + // substituting and the \ staying in the expansion + // Note space after name is important so when substitute it has ending whitespace +`define ESC_CAT(name,name2) \name``_assignment_``name2 \ + + initial begin : `ESC_CAT( a[0],a[1] ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end +`undef ESC_CAT + //----- +`define CAT(a,b) a``b +`define ESC(name) \`CAT(name,suffix) + // RULE: Ignoring backslash does NOT allow an additional expansion level + // (Because ESC gets expanded then the \ has it's normal escape meaning) + initial begin : `ESC(pp) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end +`undef CAT `undef ESC + //----- +`define CAT(a,b) a``b +`define ESC(name) \name \ + + // Similar to above; \ does not allow expansion after substitution + initial begin : `ESC( `CAT(ff,bb) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end +`undef CAT `undef ESC + //----- +`define ESC(name) \name \ + + // MUST: Unknown macro with backslash escape stays as escaped symbol name + initial begin : `ESC( `zzz ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end +`undef ESC + //----- +`define FOO bar +`define ESC(name) \name \ + + // SHOULD(simulator-dependant): Known macro with backslash escape expands + initial begin : `ESC( `FOO ) $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end + // SHOULD(simulator-dependant): Prefix breaks the above + initial begin : `ESC( xx`FOO ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end +`undef FOO `undef ESC + //----- + // MUST: Unknown macro not under call with backslash escape doesn't expand +`undef UNKNOWN + initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end + //----- + // MUST: Unknown macro not under call doesn't expand +`define DEF_NO_EXPAND error_dont_expand + initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end +`undef DEF_NO_EXPAND + //----- + // bug441 derivative + // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) +`define STR(name) "foo name baz" + initial $write("GOT='%s' EXP='%s'\n", `STR(bar), "foo bar baz"); +`undef STR + //----- + // RULE: Because there are quotes after substituting STR, the `A does NOT expand +`define STR(name) "foo name baz" +`define A(name) boo name hiss + initial $write("GOT='%s' EXP='%s'\n", `STR(`A(bar)), "foo `A(bar) baz"); +`undef A `undef STR + //---- + // bug845 +`define SLASHED "1//2.3" + initial $write("Slashed=`%s'\n", `SLASHED); + //---- + // bug915 +`define BUG915(a,b,c) \ + $display("%s%s",a,`"b``c``\n`") + initial `BUG915("a1",b2,c3); +endmodule + +//====================================================================== +//bug1225 + +`define X_ITEM(SUB,UNIT) `X_STRING(SUB``UNIT) +`define X_STRING(A) `"A`" +$display(`X_ITEM(RAM,0)); +$display(`X_ITEM(CPU,)); + +`define EMPTY +`define EMPTYP(foo) +`define SOME some +`define SOMEP(foo) foo + +`define XXE_FAMILY XXE_```EMPTY +XXE_FAMILY = `XXE_FAMILY +`define XXE_```EMPTY +`ifdef XXE_ + $display("XXE_ is defined"); +`endif + +`define XYE_FAMILY XYE_```EMPTYP(foo) +XYE_FAMILY = `XYE_FAMILY +`define XYE_```EMPTYP(foo) +`ifdef XYE_ + $display("XYE_ is defined"); +`endif + +`define XXS_FAMILY XXS_```SOME +XXS_FAMILY = `XXS_FAMILY +`define XXS_```SOME +`ifdef XXS_some + $display("XXS_some is defined"); +`endif + +`define XYS_FAMILY XYS_```SOMEP(foo) +XYS_FAMILY = `XYS_FAMILY +`define XYS_```SOMEP(foo) +`ifdef XYS_foo + $display("XYS_foo is defined"); +`endif + +//==== + +`ifdef NEVER + `define NXE_FAMILY NXE_```EMPTY +NXE_FAMILY = `NXE_FAMILY + `define NXE_```EMPTY + `ifdef NXE_ + $display("NXE_ is defined"); + `endif + + `define NYE_FAMILY NYE_```EMPTYP(foo) +NYE_FAMILY = `NYE_FAMILY + `define NYE_```EMPTYP(foo) + `ifdef NYE_ + $display("NYE_ is defined"); + `endif + + `define NXS_FAMILY NXS_```SOME +NXS_FAMILY = `NXS_FAMILY + `define NXS_```SOME + `ifdef NXS_some + $display("NXS_some is defined"); + `endif + + `define NYS_FAMILY NYS_```SOMEP(foo) +NYS_FAMILY = `NYS_FAMILY + `define NYS_```SOMEP(foo) + `ifdef NYS_foo + $display("NYS_foo is defined"); + `endif + + `include `EMPTY + +`endif // NEVER + +//bug1227 +`define INSTANCE(NAME) (.mySig (myInterface.``NAME), +`INSTANCE(pa5) + +//====================================================================== +// Stringify bug + +`define hack(GRP) `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); +`hack(paramgrp) + +`define dbg_hdl(LVL, MSG) $display ("DEBUG : %s [%m]", $sformatf MSG) +`define svfcov_new(GRP) \ + initial do begin `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); end while(0) +`define simple_svfcov_clk(LBL, CLK, RST, ARG) \ + covergroup LBL @(posedge CLK); \ + c: coverpoint ARG iff ((RST) === 1'b1); endgroup \ + LBL u_``LBL; `svfcov_new(u_``LBL) + +module pcc2_cfg; + generate + `simple_svfcov_clk(a, b, c, d); + endgenerate +endmodule + +//====================================================================== +// IEEE mandated predefines +`undefineall // undefineall should have no effect on these +predef `SV_COV_START 0 +predef `SV_COV_STOP 1 +predef `SV_COV_RESET 2 +predef `SV_COV_CHECK 3 +predef `SV_COV_MODULE 10 +predef `SV_COV_HIER 11 +predef `SV_COV_ASSERTION 20 +predef `SV_COV_FSM_STATE 21 +predef `SV_COV_STATEMENT 22 +predef `SV_COV_TOGGLE 23 +predef `SV_COV_OVERFLOW -2 +predef `SV_COV_ERROR -1 +predef `SV_COV_NOCOV 0 +predef `SV_COV_OK 1 +predef `SV_COV_PARTIAL 2 +//====================================================================== +// After `undefineall above, for testing --dump-defines +`define WITH_ARG(a) (a)(a)
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_def09.v b/SVIncCompil/Testcases/Verilator/t_preproc_def09.v new file mode 100644 index 0000000..88c27c2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_def09.v
@@ -0,0 +1,73 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +`undefineall + +// Definitions as speced +// Note there are trailing spaces, which spec doesn't show properly +`define D(x,y) initial $display("start", x , y, "end"); +'`D( "msg1" , "msg2" )' +'initial $display("start", "msg1" , "msg2" , "end");' +'`D( " msg1", )' +'initial $display("start", " msg1" , , "end");' +'`D(, "msg2 ")' +'initial $display("start", , "msg2 ", "end");' +'`D(,)' +'initial $display("start", , , "end");' +'`D( , )' +'initial $display("start", , , "end");' +//`D("msg1") // ILLEGAL: only one argument +//`D() // ILLEGAL: only one empty argument +//`D(,,) // ILLEGAL: more actual than formal arguments + +// Defaults: +`define MACRO1(a=5,b="B",c) $display(a,,b,,c); +'`MACRO1 ( , 2, 3 )' +'$display(5,,2,,3);' +'`MACRO1 ( 1 , , 3 )' +'$display(1 ,,"B",,3 );' +'`MACRO1 ( , 2, )' +'$display(5,,2,,);' +//`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c + +`define MACRO2(a=5, b, c="C") $display(a,,b,,c); +'`MACRO2 (1, , 3)' +'$display(5,,,,"C");' +'`MACRO2 (, 2, )' +'$display(5,,2,,"C");' +'`MACRO2 (, 2)' +'$display(5,,2,,"C");' + +`define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); +'`MACRO3 ( 1 )' +'$display(1 ,,0,,"C");' +'`MACRO3 ( )' +'$display(5,,0,,"C");' +//`MACRO3 // ILLEGAL: parentheses required + +`define DTOP(a,b) a + b +'`DTOP( `DTOP(b,1), `DTOP(42,a) )' +'b + 1 + 42 + a' + +// Local tests +`define MACROQUOTE(a="==)",b="((((",c=() ) 'a b c' +`MACROQUOTE(); +'"==)" "((((" () '; + +// Also check our line counting doesn't go bad +`define MACROPAREN(a=(6), + b=(eq=al), + c) 'a b c' +`MACROPAREN( + + + + ,, + + + ZOT) +HERE-`__LINE__ - Line71 + +//======================================================================
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_ifdef.v b/SVIncCompil/Testcases/Verilator/t_preproc_ifdef.v new file mode 100644 index 0000000..7c5e23b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_ifdef.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + integer num; + initial begin + num = 0; + +`define EMPTY_TRUE +`ifndef EMPTY_TRUE + `error "Empty is still true" +`endif + +`define A +`ifdef A $display("1A"); num = num + 1; + `ifdef C $stop; + `elsif A $display("2A"); num = num + 1; + `ifdef C $stop; + `elsif B $stop; + `else $display("3A"); num = num + 1; + `endif + `else $stop; + `endif + `elsif B $stop; + `ifdef A $stop; + `elsif A $stop; + `else + `endif +`elsif C $stop; +`else $stop; +`endif + if (num == 3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("%%Error: Bad count: %d\n", num); + $stop; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_inc2.vh b/SVIncCompil/Testcases/Verilator/t_preproc_inc2.vh new file mode 100644 index 0000000..77d993e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_inc2.vh
@@ -0,0 +1,6 @@ +// DESCRIPTION: Verilog::Preproc: Example source code +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2007 by Wilson Snyder. +At file `__FILE__ line `__LINE__ +`define INCFILE <t_preproc_inc3.vh> +`include `INCFILE
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_inc3.vh b/SVIncCompil/Testcases/Verilator/t_preproc_inc3.vh new file mode 100644 index 0000000..04e8a5a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_inc3.vh
@@ -0,0 +1,17 @@ +`line 2 "inc3_a_filename_from_line_directive" 0 +// DESCRIPTION: Verilog::Preproc: Example source code +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2007 by Wilson Snyder. + +`ifndef _EXAMPLE_INC2_V_ + `define _EXAMPLE_INC2_V_ 1 + `define _EMPTY + // FOO + At file `__FILE__ line `__LINE__ +`else + `error "INC2 File already included once" +`endif // guard + +`ifdef not_defined + `include "NotToBeInced.vh" +`endif
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_inc4.vh b/SVIncCompil/Testcases/Verilator/t_preproc_inc4.vh new file mode 100644 index 0000000..f472075 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_inc4.vh
@@ -0,0 +1,5 @@ +// DESCRIPTION: Verilog::Preproc: Example source code +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2011 by Wilson Snyder. + +`define T_PREPROC_INC4
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_inc_bad.v b/SVIncCompil/Testcases/Verilator/t_preproc_inc_bad.v new file mode 100644 index 0000000..1c8b9ff --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_inc_bad.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +//See bug289 + +`include "t_preproc_inc_inc_bad.vh" + +module t; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_inc_inc_bad.vh b/SVIncCompil/Testcases/Verilator/t_preproc_inc_inc_bad.vh new file mode 100644 index 0000000..329c771 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_inc_inc_bad.vh
@@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module xx; + + xx // intentional error + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_inc_notfound_bad.v b/SVIncCompil/Testcases/Verilator/t_preproc_inc_notfound_bad.v new file mode 100644 index 0000000..e225ca5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_inc_notfound_bad.v
@@ -0,0 +1,6 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +`include "this_file_is_not_found.vh"
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_kwd.v b/SVIncCompil/Testcases/Verilator/t_preproc_kwd.v new file mode 100644 index 0000000..f62e512 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_kwd.v
@@ -0,0 +1,77 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + v95 v95 (); + v01 v01 (); + v05 v05 (); + s05 s05 (); + s09 s09 (); + s12 s12 (); + s17 s17 (); + + a23 a23 (); + + initial begin + $finish; + end +endmodule + +`begin_keywords "1364-1995" +module v95; + integer signed; initial signed = 1; +endmodule +`end_keywords + +`begin_keywords "1364-2001" +module v01; + integer bit; initial bit = 1; +endmodule +`end_keywords + +`begin_keywords "1364-2005" +module v05; + integer final; initial final = 1; +endmodule +`end_keywords + +`begin_keywords "1800-2005" +module s05; + integer global; initial global = 1; +endmodule +`end_keywords + +`begin_keywords "1800-2009" +module s09; + integer soft; initial soft = 1; +endmodule +`end_keywords + +`begin_keywords "1800-2012" +module s12; + final begin + $write("*-* All Finished *-*\n"); + end +endmodule +`end_keywords + +`begin_keywords "1800-2017" +module s17; + final begin + $write("*-* All Finished *-*\n"); + end +endmodule +`end_keywords + +`begin_keywords "VAMS-2.3" +module a23; + real foo; initial foo = sqrt(2.0); +endmodule +`end_keywords
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_noline.v b/SVIncCompil/Testcases/Verilator/t_preproc_noline.v new file mode 100644 index 0000000..8d89b0e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_noline.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define CHECK text \ + multiline + +Hello in t_preproc_psl.v + +`ifdef NEVER + not +`else + yes +`endif + +Multi `CHECK line + +// Did we end up right? +Line: `__LINE__
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_persist.v b/SVIncCompil/Testcases/Verilator/t_preproc_persist.v new file mode 100644 index 0000000..0f3f456 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_persist.v
@@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +Inside `__FILE__. + +`include "t_preproc_persist_inc.v"
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_persist2.v b/SVIncCompil/Testcases/Verilator/t_preproc_persist2.v new file mode 100644 index 0000000..0f3f456 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_persist2.v
@@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +Inside `__FILE__. + +`include "t_preproc_persist_inc.v"
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_persist_inc.v b/SVIncCompil/Testcases/Verilator/t_preproc_persist_inc.v new file mode 100644 index 0000000..0e62c6b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_persist_inc.v
@@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +`ifndef COMMON_GUARD + `define COMMON_GUARD 1 +Inside `__FILE__. +`endif
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_ttempty.v b/SVIncCompil/Testcases/Verilator/t_preproc_ttempty.v new file mode 100644 index 0000000..572108d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_ttempty.v
@@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +//`define TARGET_PACKAGE + +`define TARGET_PACKAGE_```TARGET_PACKAGE
diff --git a/SVIncCompil/Testcases/Verilator/t_preproc_undefineall.v b/SVIncCompil/Testcases/Verilator/t_preproc_undefineall.v new file mode 100644 index 0000000..2f86b17 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_preproc_undefineall.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + +`define UDALL +`ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif + +`undefineall + +`ifdef UDALL `error "undefineall failed" `endif +`ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif + + initial begin + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_program.v b/SVIncCompil/Testcases/Verilator/t_program.v new file mode 100644 index 0000000..4f2436f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_program.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +program t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endprogram
diff --git a/SVIncCompil/Testcases/Verilator/t_real_param.v b/SVIncCompil/Testcases/Verilator/t_real_param.v new file mode 100644 index 0000000..99b07ac --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_real_param.v
@@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Todd Strader. + +module foo + #( parameter real bar = 2.0) + (); +endmodule + +module t(); + genvar m, r; + generate + for (m = 10; m <= 20; m+=10) begin : gen_m + for (r = 0; r <= 1; r++) begin : gen_r + localparam real lparam = m + (r + 0.5); + initial begin + if (lparam != foo_inst.bar) begin + $display("%m: lparam != foo_inst.bar (%f, %f)", + lparam, foo_inst.bar); + $stop(); + end + end + + foo #(.bar (lparam)) foo_inst (); + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_reloop_cam.v b/SVIncCompil/Testcases/Verilator/t_reloop_cam.v new file mode 100644 index 0000000..cda3547 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_reloop_cam.v
@@ -0,0 +1,176 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + reg rst; + + // Two phases, random so nothing optimizes away, and focused so get hits + logic inval; + wire [30:0] wdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); + wire [30:0] cdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); + wire wdat_val = 1'b1; + wire camen = crc[32]; + wire ren = crc[33]; + wire wen = crc[34]; + wire [7:0] rwidx = (cyc < 50 ? crc[63:56] : {6'h0, crc[57:56]}); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic hit_d2r; // From cam of cam.v + logic [7:0] hitidx_d1r; // From cam of cam.v + logic [255:0] hitvec_d1r; // From cam of cam.v + logic [30:0] rdat_d2r; // From cam of cam.v + logic rdat_val_d2r; // From cam of cam.v + // End of automatics + + cam cam (/*AUTOINST*/ + // Outputs + .hitvec_d1r (hitvec_d1r[255:0]), + .hitidx_d1r (hitidx_d1r[7:0]), + .hit_d2r (hit_d2r), + .rdat_d2r (rdat_d2r[30:0]), + .rdat_val_d2r (rdat_val_d2r), + // Inputs + .clk (clk), + .rst (rst), + .camen (camen), + .inval (inval), + .cdat (cdat[30:0]), + .ren (ren), + .wen (wen), + .wdat (wdat[30:0]), + .wdat_val (wdat_val), + .rwidx (rwidx[7:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {hitvec_d1r[15:0], 15'h0, hit_d2r, rdat_val_d2r, rdat_d2r}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + rst <= 1'b1; + end + else if (cyc<10) begin + sum <= '0; + rst <= 1'b0; + end + else if (cyc==70) begin + inval <= 1'b1; + end + else if (cyc==71) begin + inval <= 1'b0; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'h5182640870b07199 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module cam + ( + input clk, + input rst, + + input camen, + input inval, + input [30:0] cdat, + output logic [255:0] hitvec_d1r, + output logic [7:0] hitidx_d1r, + output logic hit_d2r, + + input ren, + input wen, + input [30:0] wdat, + input wdat_val, + input [7:0] rwidx, + output logic [30:0] rdat_d2r, + output logic rdat_val_d2r + ); + + logic camen_d1r; + logic inval_d1r; + logic ren_d1r; + logic wen_d1r; + logic [7:0] rwidx_d1r; + logic [30:0] cdat_d1r; + logic [30:0] wdat_d1r; + logic wdat_val_d1r; + + always_ff @(posedge clk) begin + camen_d1r <= camen; + inval_d1r <= inval; + ren_d1r <= ren; + wen_d1r <= wen; + + cdat_d1r <= cdat; + rwidx_d1r <= rwidx; + wdat_d1r <= wdat; + wdat_val_d1r <= wdat_val; + end + + typedef struct packed { + logic [30:0] data; + logic valid; + } entry_t; + entry_t [255:0] entries; + + always_ff @(posedge clk) begin + if (camen_d1r) begin + for (int i = 0; i < 256; i = i + 1) begin + hitvec_d1r[i] <= entries[i].valid & (entries[i].data == cdat_d1r); + end + end + end + always_ff @(posedge clk) begin + hit_d2r <= | hitvec_d1r; + end + + always_ff @(posedge clk) begin + if (rst) begin + for (int i = 0; i < 256; i = i + 1) begin + entries[i] <= '0; + end + end + else if (wen_d1r) begin + entries[rwidx_d1r] <= '{valid:wdat_val_d1r, data:wdat_d1r}; + end + else if (inval_d1r) begin + for (int i = 0; i < 256; i = i + 1) begin + entries[i] <= '{valid:'0, data:entries[i].data}; + end + end + end + + always_ff @(posedge clk) begin + if (ren_d1r) begin + rdat_d2r <= entries[rwidx_d1r].data; + rdat_val_d2r <= entries[rwidx_d1r].valid; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_repeat.v b/SVIncCompil/Testcases/Verilator/t_repeat.v new file mode 100644 index 0000000..9d0c1a3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_repeat.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg signed [2:0] negcnt; + integer times; + initial begin + times = 0; + repeat (1) begin + repeat (0) $stop; + repeat (-1) $stop; + negcnt = 'sb111; + // Not all commercial simulators agree on the below stopping or not + // verilator lint_off WIDTH + repeat (negcnt) $stop; + // verilator lint_on WIDTH + repeat (5) begin + repeat (2) begin + times = times + 1; + end + end + end + if (times != 10) $stop; + // + // verilator lint_off INFINITELOOP + forever begin + // verilator lint_on INFINITELOOP + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_rnd.v b/SVIncCompil/Testcases/Verilator/t_rnd.v new file mode 100644 index 0000000..c080df8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_rnd.v
@@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg _ranit; + + reg [2:0] a; + reg [33:0] wide; + reg unused_r; + + initial _ranit = 0; + + always @ (posedge clk) begin : blockName + begin // Verify begin/begin is legal + unused_r <= 1'b1; + end + begin end // Verify empty is legal + end + + wire one = 1'b1; + wire [7:0] rand_bits = 8'b01xx_xx10; + + always @ (posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + // + a = 3'b1xx; + wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000; + if (one !== 1'b1) $stop; + if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // verilator lint_off UNUSED + wire _unused_ok = |{1'b1, wide}; + // verilator lint_on UNUSED + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_runflag.v b/SVIncCompil/Testcases/Verilator/t_runflag.v new file mode 100644 index 0000000..5edda93 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_runflag.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_runflag_seed.v b/SVIncCompil/Testcases/Verilator/t_runflag_seed.v new file mode 100644 index 0000000..16e901d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_runflag_seed.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t; + initial begin + integer r = $random; + integer ex; + if ($value$plusargs("SEED=%x", ex) !== 1) $stop; + `checkh(r, ex); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_savable.v b/SVIncCompil/Testcases/Verilator/t_savable.v new file mode 100644 index 0000000..bef0ad5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_savable.v
@@ -0,0 +1,95 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + /*verilator no_inline_module*/ // So we'll get hiearachy we can test + input clk; + + sub sub (/*AUTOINST*/ + // Inputs + .clk (clk)); +endmodule + +module sub (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + /*verilator no_inline_module*/ // So we'll get hiearachy we can test + + integer cyc=0; + + reg [127:0] save128; + reg [47:0] save48; + reg [1:0] save2; + reg [255:0] cycdone; // Make sure each cycle executes exactly once + reg [31:0] vec[2:1][2:1]; + reg [2:1][2:1][31:0] pvec; + real r; + string s,s2; + string sarr[2:1]; + + string si; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d\n",$time, cyc); +`endif + si = "siimmed"; + cyc <= cyc + 1; + if (cycdone[cyc[7:0]]) $stop; + cycdone[cyc[7:0]] <= '1; + if (cyc==0) begin + // Setup + save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e; + save48 <= 48'h4afe43fb79d7; + save2 <= 2'b10; + vec[1][1] <= 32'h0101; + vec[1][2] <= 32'h0102; + vec[2][1] <= 32'h0201; + vec[2][2] <= 32'h0202; + pvec[1][1] <= 32'h10101; + pvec[1][2] <= 32'h10102; + pvec[2][1] <= 32'h10201; + pvec[2][2] <= 32'h10202; + r <= 1.234; + s <= "hello"; + sarr[1] <= "sarr[1]"; + sarr[2] <= "sarr[2]"; + end + if (cyc==1) begin + if ($test$plusargs("save_restore")!=0) begin + // Don't allow the restored model to run from time 0, it must run from a restore + $write("%%Error: didn't really restore\n"); + $stop; + end + end + else if (cyc==99) begin + if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop; + if (save48 !== 48'h4afe43fb79d7) $stop; + if (save2 !== 2'b10) $stop; + if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop; + if (vec[1][1] !== 32'h0101) $stop; + if (vec[1][2] !== 32'h0102) $stop; + if (vec[2][1] !== 32'h0201) $stop; + if (vec[2][2] !== 32'h0202) $stop; + if (pvec[1][1] !== 32'h10101) $stop; + if (pvec[1][2] !== 32'h10102) $stop; + if (pvec[2][1] !== 32'h10201) $stop; + if (pvec[2][2] !== 32'h10202) $stop; + if (r != 1.234) $stop; + $display("%s",s); + $display("%s",sarr[1]); + $display("%s",sarr[2]); + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_scope_map.v b/SVIncCompil/Testcases/Verilator/t_scope_map.v new file mode 100644 index 0000000..a69acdb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_scope_map.v
@@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Test symbol table scope map and general public +// signal reflection +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +module t + ( + input wire CLK + ); + + foo #(.WIDTH (1)) foo1 (.*); + foo #(.WIDTH (7)) foo7 (.*); + foo #(.WIDTH (8)) foo8 (.*); + foo #(.WIDTH (32)) foo32 (.*); + foo #(.WIDTH (33)) foo33 (.*); + foo #(.WIDTH (40)) foo40 (.*); + foo #(.WIDTH (41)) foo41 (.*); + foo #(.WIDTH (64)) foo64 (.*); + foo #(.WIDTH (65)) foo65 (.*); + foo #(.WIDTH (96)) foo96 (.*); + foo #(.WIDTH (97)) foo97 (.*); + foo #(.WIDTH (128)) foo128 (.*); + foo #(.WIDTH (256)) foo256 (.*); + foo #(.WIDTH (1024)) foo1024 (.*); + bar #(.WIDTH (1024)) bar1024 (.*); + +endmodule + +module foo + #( + parameter WIDTH = 32 + ) + ( + input CLK + ); + + logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value; + logic [ WIDTH - 1 : 0 ] value_q /* verilator public */; + integer i; + + initial begin + initial_value = '1; + + for (i = 0; i < WIDTH / 8; i++) + initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ]; + + value_q = initial_value[ WIDTH - 1 : 0 ]; + end + + always @(posedge CLK) + value_q <= ~value_q; + +endmodule + +module bar + #( + parameter WIDTH = 32 + ) + ( + input CLK + ); + + foo #(.WIDTH (WIDTH)) foo (.*); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_bad_msb.v b/SVIncCompil/Testcases/Verilator/t_select_bad_msb.v new file mode 100644 index 0000000..26198e9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_bad_msb.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (clk); + input clk; + + reg [43:0] mi; + reg [3:0] sel2; + reg [0:22] backwd; + + always @ (posedge clk) begin + mi = 44'h123; + sel2 = mi[1:4]; + $write ("Bad select %x\n", sel2); + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_bad_range.v b/SVIncCompil/Testcases/Verilator/t_select_bad_range.v new file mode 100644 index 0000000..dee1f04 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_bad_range.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + reg [43:0] mi; + reg sel; + reg [3:0] sel2; + + always @ (posedge clk) begin + mi = 44'h123; + sel = mi[44]; + sel2 = mi[44:41]; + $write ("Bad select %x %x\n", sel, sel2); + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_bad_range2.v b/SVIncCompil/Testcases/Verilator/t_select_bad_range2.v new file mode 100644 index 0000000..942195c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_bad_range2.v
@@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [1:0] in; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0] out10; // From test of Test.v + wire [1:0] out32; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out32 (out32[1:0]), + .out10 (out10[1:0]), + // Inputs + .in (in[1:0])); + + // Test loop + always @ (posedge clk) begin + in <= in + 1; +`ifdef TEST_VERBOSE + $write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10); +`endif + if (in==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out32, out10, + // Inputs + in + ); + input [1:0] in; + output [1:0] out32; + output [1:0] out10; + + assign out32 = in[3:2]; + assign out10 = in[1:0]; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_bad_range3.v b/SVIncCompil/Testcases/Verilator/t_select_bad_range3.v new file mode 100644 index 0000000..11e2928 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_bad_range3.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + outwires, + // Inputs + inwires + ); + + input [7:0] inwires [12:10]; + output wire [7:0] outwires [12:10]; + + assign outwires[10] = inwires[11]; + assign outwires[11] = inwires[12]; + assign outwires[12] = inwires[13]; // must be an error here + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_bad_tri.v b/SVIncCompil/Testcases/Verilator/t_select_bad_tri.v new file mode 100644 index 0000000..e7eed14 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_bad_tri.v
@@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [72:1] in; + initial begin + if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_bound1.v b/SVIncCompil/Testcases/Verilator/t_select_bound1.v new file mode 100644 index 0000000..8c57e18 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_bound1.v
@@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +// bug823 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [2:0] in = crc[2:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + .mask (mask[3:0]), + // Inputs + .clk (clk), + .in (in[2:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out & mask}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'ha9d3a7a69d2bea75 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, mask, + // Inputs + clk, in + ); + + input clk; + input [2:0] in; + output reg [3:0] out; + output reg [3:0] mask; + localparam [15:5] p = 11'h1ac; + + always @(posedge clk) begin + // verilator lint_off WIDTH + out <= p[15 + in -: 5]; + // verilator lint_on WIDTH + mask[3] <= ((15 + in - 5) < 12); + mask[2] <= ((15 + in - 5) < 13); + mask[1] <= ((15 + in - 5) < 14); + mask[0] <= ((15 + in - 5) < 15); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_bound2.v b/SVIncCompil/Testcases/Verilator/t_select_bound2.v new file mode 100644 index 0000000..ff6600d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_bound2.v
@@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +// bug823 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [6:0] in = crc[6:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + .mask (mask[3:0]), + // Inputs + .clk (clk), + .in (in[6:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out & mask}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4e9d3a74e9d3f656 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, mask, + // Inputs + clk, in + ); + + input clk; + input [6:0] in; // Note much wider than any index + output reg [3:0] out; + output reg [3:0] mask; + localparam [15:5] p = 11'h1ac; + + always @(posedge clk) begin + // verilator lint_off WIDTH + out <= p[15 + in -: 5]; + // verilator lint_on WIDTH + mask[3] <= ((15 + in - 5) < 12); + mask[2] <= ((15 + in - 5) < 13); + mask[1] <= ((15 + in - 5) < 14); + mask[0] <= ((15 + in - 5) < 15); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_index.v b/SVIncCompil/Testcases/Verilator/t_select_index.v new file mode 100644 index 0000000..53ab685 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_index.v
@@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + // surefire lint_off NBAJAM + + input clk; + reg [7:0] _ranit; + + reg [2:0] a; + reg [7:0] vvector; + reg [7:0] vvector_flip; + + // surefire lint_off STMINI + initial _ranit = 0; + + always @ (posedge clk) begin + a <= a + 3'd1; + vvector[a] <= 1'b1; // This should use "old" value for a + vvector_flip[~a] <= 1'b1; // This should use "old" value for a + // + //======== + if (_ranit==8'd0) begin + _ranit <= 8'd1; + $write("[%0t] t_select_index: Running\n", $time); + vvector <= 0; + vvector_flip <= 0; + a <= 3'b1; + end + else _ranit <= _ranit + 8'd1; + // + if (_ranit==8'd3) begin + $write("%x %x\n",vvector,vvector_flip); + if (vvector !== 8'b0000110) $stop; + if (vvector_flip !== 8'b0110_0000) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_index2.v b/SVIncCompil/Testcases/Verilator/t_select_index2.v new file mode 100644 index 0000000..475550c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_index2.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [7:0] x; + wire [3:0] en; + wire sel; + wire a; + + // bug675 + generate + genvar g_k; + for ( g_k = 0; g_k < 8; g_k = g_k + 1 ) + begin: g_index + always @* begin + // Note this isn't a genif, but normal if + // verilator lint_off SELRANGE + if(g_k<4) begin + x[g_k] = (sel == 1'b1) ? 1'b1 : (en[g_k] == 1'b0) ? 1'b1 : a; + end + else begin + x[g_k] = (sel == 1'b0) ? 1'b1 : (en[g_k-4] == 1'b0) ? 1'b1 : a; + end + // verilator lint_on SELRANGE + end + end + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_lhs_oob.v b/SVIncCompil/Testcases/Verilator/t_select_lhs_oob.v new file mode 100644 index 0000000..82dc65a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_lhs_oob.v
@@ -0,0 +1,92 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + reg [6:0] mem1d; + reg [6:0] mem2d [5:0]; + reg [6:0] mem3d [4:0][5:0]; + + integer i,j,k; + + // Four different test cases for out of bounds + // = + // <= + // Continuous assigns + // Output pin interconnect (also covers cont assigns) + // Each with both bit selects and array selects + + initial begin + mem1d[0] = 1'b0; + i=7; + mem1d[i] = 1'b1; + if (mem1d[0] !== 1'b0) $stop; + // + for (i=0; i<8; i=i+1) begin + for (j=0; j<8; j=j+1) begin + for (k=0; k<8; k=k+1) begin + mem1d[k] = k[0]; + mem2d[j][k] = j[0]+k[0]; + mem3d[i][j][k] = i[0]+j[0]+k[0]; + end + end + end + for (i=0; i<5; i=i+1) begin + for (j=0; j<6; j=j+1) begin + for (k=0; k<7; k=k+1) begin + if (mem1d[k] !== k[0]) $stop; + if (mem2d[j][k] !== j[0]+k[0]) $stop; + if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop; + end + end + end + end + + integer wi; + wire [31:0] wd = cyc; + reg [31:0] reg2d[6:0]; + always @ (posedge clk) reg2d[wi[2:0]] <= wd; + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd); +`endif + cyc <= cyc + 1; + if (cyc<10) begin + wi <= 0; + end + else if (cyc==10) begin + wi <= 1; + end + else if (cyc==11) begin + if (reg2d[0] !== 10) $stop; + wi <= 6; + end + else if (cyc==12) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + wi <= 7; // Will be ignored + end + else if (cyc==13) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + if (reg2d[6] !== 12) $stop; + end + else if (cyc==14) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + if (reg2d[6] !== 12) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_lhs_oob2.v b/SVIncCompil/Testcases/Verilator/t_select_lhs_oob2.v new file mode 100644 index 0000000..1c33db9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_lhs_oob2.v
@@ -0,0 +1,141 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] out; // From test of Test.v + // End of automatics + + wire reset_l = ~(cyc<15); + wire [63:0] d = crc[63:0]; + wire [8:0] t_wa = crc[8:0]; + wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]}; + + Test test (/*AUTOINST*/ + // Outputs + .out (out[63:0]), + // Inputs + .clk (clk), + .reset_l (reset_l), + .t_wa (t_wa[8:0]), + .d (d[63:0]), + .t_addr (t_addr[8:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h421a41d1541ea652 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, reset_l, t_wa, d, t_addr + ); + input clk; + input reset_l; + + reg [63:0] m_w0 [47:0]; + reg [63:0] m_w1 [23:0]; + reg [63:0] m_w2 [23:0]; + reg [63:0] m_w3 [23:0]; + reg [63:0] m_w4 [23:0]; + reg [63:0] m_w5 [23:0]; + + input [8:0] t_wa; + input [63:0] d; + + always @ (posedge clk) begin + if (~reset_l) begin : blk + integer i; + + for (i=0; i<48; i=i+1) begin + m_w0[i] <= 64'h0; + end + + for (i=0; i<24; i=i+1) begin + m_w1[i] <= 64'h0; + m_w2[i] <= 64'h0; + m_w3[i] <= 64'h0; + m_w4[i] <= 64'h0; + m_w5[i] <= 64'h0; + end + end + else begin + casez (t_wa[8:6]) + 3'd0: m_w0[t_wa[5:0]] <= d; + 3'd1: m_w1[t_wa[4:0]] <= d; + 3'd2: m_w2[t_wa[4:0]] <= d; + 3'd3: m_w3[t_wa[4:0]] <= d; + 3'd4: m_w4[t_wa[4:0]] <= d; + default: m_w5[t_wa[4:0]] <= d; + endcase + end + end + + input [8:0] t_addr; + + wire [63:0] t_w0 = m_w0[t_addr[5:0]]; + wire [63:0] t_w1 = m_w1[t_addr[4:0]]; + wire [63:0] t_w2 = m_w2[t_addr[4:0]]; + wire [63:0] t_w3 = m_w3[t_addr[4:0]]; + wire [63:0] t_w4 = m_w4[t_addr[4:0]]; + wire [63:0] t_w5 = m_w5[t_addr[4:0]]; + + output reg [63:0] out; + always @* begin + casez (t_addr[8:6]) + 3'd0: out = t_w0; + 3'd1: out = t_w1; + 3'd2: out = t_w2; + 3'd3: out = t_w3; + 3'd4: out = t_w4; + default: out = t_w5; + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_little.v b/SVIncCompil/Testcases/Verilator/t_select_little.v new file mode 100644 index 0000000..8840fcb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_little.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // verilator lint_off LITENDIAN + wire [10:41] sel2 = crc[31:0]; + wire [10:100] sel3 = {crc[26:0],crc}; + + wire out20 = sel2[{1'b0,crc[3:0]} + 11]; + wire [3:0] out21 = sel2[13 : 16]; + wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; + wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; + + wire out30 = sel3[{2'b0,crc[3:0]} + 11]; + wire [3:0] out31 = sel3[13 : 16]; + wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; + wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; + + // Aggregate outputs into a single result vector + wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; + + reg [19:50] sel1; + initial begin + // Path clearing + // 122333445 + // 826048260 + sel1 = 32'h12345678; + if (sel1 != 32'h12345678) $stop; + if (sel1[47 : 50] != 4'h8) $stop; + if (sel1[31 : 34] != 4'h4) $stop; + if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] + if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33); + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'h28bf65439eb12c00 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_little_pack.v b/SVIncCompil/Testcases/Verilator/t_select_little_pack.v new file mode 100644 index 0000000..cf2b8b3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_little_pack.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // No endian warning here + reg [7:0] pack [3:0]; + + initial begin + pack[0] = 8'h78; + pack[1] = 8'h88; + pack[2] = 8'h98; + pack[3] = 8'hA8; + if (pack[0] !== 8'h78) $stop; + if (pack[1] !== 8'h88) $stop; + if (pack[2] !== 8'h98) $stop; + if (pack[3] !== 8'hA8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_loop.v b/SVIncCompil/Testcases/Verilator/t_select_loop.v new file mode 100644 index 0000000..42dc360 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_loop.v
@@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [255:0] a; + reg [255:0] q; + reg [63:0] qq; + + integer i; + always @* begin + for (i=0; i<256; i=i+1) begin + q[255-i] = a[i]; + end + q[27:16] = 12'hfed; + for (i=0; i<64; i=i+1) begin + qq[63-i] = a[i]; + end + qq[27:16] = 12'hfed; + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%x/%x %x\n", q, qq, a); +`endif + if (cyc==1) begin + a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; + end + if (cyc==2) begin + a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; + if (qq != 64'h64fe7e285fed892e) $stop; + end + if (cyc==3) begin + if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; + if (qq != 64'h1da9cf939fed1250) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_negative.v b/SVIncCompil/Testcases/Verilator/t_select_negative.v new file mode 100644 index 0000000..a75eb06 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_negative.v
@@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [15:-16] sel2 = crc[31:0]; + wire [80:-10] sel3 = {crc[26:0],crc}; + + wire [3:0] out21 = sel2[-3 : -6]; + wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4]; + wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4]; + + wire [3:0] out31 = sel3[-3 : -6]; + wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4]; + wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4]; + + // Aggregate outputs into a single result vector + wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33}; + + reg [15:-16] sel1; + initial begin + // Path clearing + sel1 = 32'h12345678; + if (sel1 != 32'h12345678) $stop; + if (sel1[-13 : -16] != 4'h8) $stop; + if (sel1[3:0] != 4'h4) $stop; + if (sel1[4 +: 4] != 4'h3) $stop; + if (sel1[11 -: 4] != 4'h2) $stop; + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33); + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'hba7fe1e7ac128362 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_param.v b/SVIncCompil/Testcases/Verilator/t_select_param.v new file mode 100644 index 0000000..12b8357 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_param.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + parameter [ BMSB : BLSB ] B = A[23:20]; // 3 + parameter A = 32'h12345678; + parameter BLSB = A[16+:4]; // 4 + parameter BMSB = A[7:4]; // 7 + + initial begin + if (B !== 4'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_plus.v b/SVIncCompil/Testcases/Verilator/t_select_plus.v new file mode 100644 index 0000000..0d078c3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_plus.v
@@ -0,0 +1,76 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [83:4] from; + reg [83:4] to; + reg [6:0] bitn; + reg [3:0] nibblep; + reg [3:0] nibblem; + + reg [7:0] cyc; initial cyc=0; + + always @* begin + nibblep = from[bitn +: 4]; + nibblem = from[bitn -: 4]; + to = from; + to[bitn +: 4] = cyc[3:0]; + to[bitn -: 4] = cyc[3:0]; + end + + always @ (posedge clk) begin + //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n",$time, cyc, nibblep, nibblem, from^to); + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end + 8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end + 8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -: + 8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end + 8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +: + 8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc + 8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc + 8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end + 8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate + 8'd09: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + case (cyc) + 8'd00: ; + 8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end + 8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end + 8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + 8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end + 8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end + 8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + 8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end + 8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end + 8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + default: $stop; + endcase + case (cyc) + 8'd00: ; + 8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end + 8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end + 8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end + 8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end + 8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0 + 8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0 + 8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end + 8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end + 8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end + default: $stop; + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_plusloop.v b/SVIncCompil/Testcases/Verilator/t_select_plusloop.v new file mode 100644 index 0000000..b15b010 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_plusloop.v
@@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [31:0] narrow; + reg [63:0] quad; + reg [127:0] wide; + + integer cyc; initial cyc=0; + reg [7:0] crc; + reg [6:0] index; + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b n=%x\n",$time, cyc, crc, narrow); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + narrow <= 32'h0; + quad <= 64'h0; + wide <= 128'h0; + crc <= 8'hed; + index <= 7'h0; + end + else if (cyc<90) begin + index <= index + 7'h2; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + // verilator lint_off WIDTH + if (index < 9'd20) narrow[index +: 3] <= crc[2:0]; + if (index < 9'd60) quad [index +: 3] <= crc[2:0]; + if (index < 9'd120) wide [index +: 3] <= crc[2:0]; + // + narrow[index[3:0]] <= ~narrow[index[3:0]]; + quad [~index[3:0]]<= ~quad [~index[3:0]]; + wide [~index[3:0]] <= ~wide [~index[3:0]]; + // verilator lint_on WIDTH + end + else if (cyc==90) begin + wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6; + wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6; + wide[82 +: 4] <=4'h6; + end + else if (cyc==91) begin + wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1; + wide[41] <=1'b1; quad[41] <=1'b1; + wide[81] <=1'b1; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n",$time, cyc, crc, narrow, quad, wide); + if (crc != 8'b01111001) $stop; + if (narrow != 32'h001661c7) $stop; + if (quad != 64'h16d49b6f64266039) $stop; + if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_runtime_range.v b/SVIncCompil/Testcases/Verilator/t_select_runtime_range.v new file mode 100644 index 0000000..85e3201 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_runtime_range.v
@@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + reg [43:0] mi; + reg [5:0] index; + integer indexi; + reg read; + + initial begin + // Static + mi = 44'b01010101010101010101010101010101010101010101; + if (mi[0] !== 1'b1) $stop; + if (mi[1 -: 2] !== 2'b01) $stop; +`ifdef VERILATOR + // verilator lint_off SELRANGE + if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop; + if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop; + if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop; + // verilator lint_on SELRANGE +`else + if (mi[-1] !== 1'bx) $stop; + if (mi[0 -: 2] !== 2'b1x) $stop; + if (mi[-1 -: 2] !== 2'bxx) $stop; +`endif + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + mi = 44'h123; + end + if (cyc==2) begin + index = 6'd43; + indexi = 43; + end + if (cyc==3) begin + read = mi[index]; + if (read!==1'b0) $stop; + read = mi[indexi]; + if (read!==1'b0) $stop; + end + if (cyc==4) begin + index = 6'd44; + indexi = 44; + end + if (cyc==5) begin + read = mi[index]; + $display("-Illegal read value: %x",read); + //if (read!==1'b1 && read!==1'bx) $stop; + read = mi[indexi]; + $display("-Illegal read value: %x",read); + //if (read!==1'b1 && read!==1'bx) $stop; + end + if (cyc==6) begin + indexi = -1; + end + if (cyc==7) begin + read = mi[indexi]; + $display("-Illegal read value: %x",read); + //if (read!==1'b1 && read!==1'bx) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_select_set.v b/SVIncCompil/Testcases/Verilator/t_select_set.v new file mode 100644 index 0000000..ff6d97b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_select_set.v
@@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + reg [63:0] inwide; + reg [39:0] addr; + + integer cyc; initial cyc=1; + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write ("%x %x\n", cyc, addr); +`endif + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + addr <= 40'h12_3456_7890; + end + if (cyc==2) begin + if (addr !== 40'h1234567890) $stop; + addr[31:0] <= 32'habcd_efaa; + end + if (cyc==3) begin + if (addr !== 40'h12abcdefaa) $stop; + addr[39:32] <= 8'h44; + inwide <= 64'hffeeddcc_11334466; + end + if (cyc==4) begin + if (addr !== 40'h44abcdefaa) $stop; + addr[31:0] <= inwide[31:0]; + end + if (cyc==5) begin + if (addr !== 40'h4411334466) $stop; + $display ("Flip [%x]\n", inwide[3:0]); + addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}]; + end + if (cyc==6) begin + if (addr !== 40'h4411334426) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_slice_cond.v b/SVIncCompil/Testcases/Verilator/t_slice_cond.v new file mode 100644 index 0000000..7e3be3c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_slice_cond.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + dataout, + // Inputs + clk, sel, d0, d1 + ); + + input clk; + input sel; + + logic [7:0] data [1:0][3:0]; + input [7:0] d0, d1; + + output wire [8*2*4-1:0] dataout; + + always_comb begin + for ( integer j = 0; j <= 1; j++ ) begin + if (sel) + data[j] = '{ d0, d1, 8'h00, 8'h00 }; + else + data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 }; + end + for ( integer j = 0; j <= 1; j++ ) begin + data[j] = sel + ? '{ d0, d1, 8'h00, 8'h00 } + : '{ 8'h00, 8'h00, 8'h00, 8'h00 }; + end + end + + assign dataout = {data[0][0], data[0][1], data[0][2], data[0][3], + data[1][0], data[1][1], data[1][2], data[1][3]}; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_slice_init.v b/SVIncCompil/Testcases/Verilator/t_slice_init.v new file mode 100644 index 0000000..828a914 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_slice_init.v
@@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk, d0, d1 + ); + + input clk; + input [7:0] d0, d1; + + logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed }, + '{ '1, '1, 8'h11, 8'h22 }}; + logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed }, + '{ '1, '1, 8'h11, 8'h22 }}; + + logic [7:0] data [1:0][3:0]; + logic [7:0] datl [0:1][0:3]; + + initial begin + data = '{ '{ d0, d1, 8'hfe, 8'hed }, + '{ d1, d1, 8'h11, 8'h22 }}; + data[0] = '{ d0, d1, 8'h19, 8'h39 }; + + datl = '{ '{ d0, d1, 8'hfe, 8'hed }, + '{ d1, d1, 8'h11, 8'h22 }}; + datl[0] = '{ d0, d1, 8'h19, 8'h39 }; + +`ifdef TEST_VERBOSE + $display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]); + $display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]); + $display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]); + $display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]); +`endif + if (inia[0][0] !== 8'h22) $stop; + if (inia[0][1] !== 8'h11) $stop; + if (inia[1][0] !== 8'hed) $stop; + if (inia[1][1] !== 8'hfe) $stop; + + if (inil[0][2] !== 8'hfe) $stop; + if (inil[0][3] !== 8'hed) $stop; + if (inil[1][2] !== 8'h11) $stop; + if (inil[1][3] !== 8'h22) $stop; + + if (data[0][0] !== 8'h39) $stop; + if (data[0][1] !== 8'h19) $stop; + if (data[1][0] !== 8'hed) $stop; + if (data[1][1] !== 8'hfe) $stop; + + if (datl[0][2] !== 8'h19) $stop; + if (datl[0][3] !== 8'h39) $stop; + if (datl[1][2] !== 8'h11) $stop; + if (datl[1][3] !== 8'h22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_slice_struct_array_modport.v b/SVIncCompil/Testcases/Verilator/t_slice_struct_array_modport.v new file mode 100644 index 0000000..18c90a8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_slice_struct_array_modport.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Varun Koyyalagunta. + +typedef struct packed { + logic p; +} s_data; + +module m1 (output s_data data[1:0]); + assign data[0].p = 0; + assign data[1].p = 0; +endmodule + +module top (output s_data data[2:0]); + m1 m1_inst (.data(data[1:0])); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_static_elab.v b/SVIncCompil/Testcases/Verilator/t_static_elab.v new file mode 100644 index 0000000..213d7af --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_static_elab.v
@@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Simple static elaboration case +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +module t (/*AUTOARG*/); + + typedef struct packed { + logic [ 31 : 0 ] _five; + } five_t; + + typedef enum { + LOW_FIVE = 32'hdeadbeef, + HIGH_FIVE + } five_style_t; + + function five_t gimme_five (); + automatic five_t result; + + result._five = 5; + + return result; + endfunction + + function five_style_t gimme_high_five (); + automatic five_style_t result; + + result = HIGH_FIVE; + + return result; + endfunction + + localparam five_t FIVE = gimme_five(); + localparam five_style_t THE_HIGH_FIVE = gimme_high_five(); + + initial begin + if (FIVE._five != 5) begin + $display("%%Error: Got 0b%b instead of 5", FIVE._five); + $stop; + end + + if (THE_HIGH_FIVE != HIGH_FIVE) begin + $display("%%Error: Got 0b%b instead of HIGH_FIVE", THE_HIGH_FIVE); + $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_stop_bad.v b/SVIncCompil/Testcases/Verilator/t_stop_bad.v new file mode 100644 index 0000000..950a2d0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_stop_bad.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t; + initial begin + $write("Intentional stop\n"); + $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_stream.v b/SVIncCompil/Testcases/Verilator/t_stream.v new file mode 100644 index 0000000..e41a54a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_stream.v
@@ -0,0 +1,311 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Glen Gibb. + +//module t; +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + + // The 'initial' code block below tests compilation-time + // evaluation/optimization of the stream operator. All occurences of the stream + // operator within this block are replaced prior to generation of C code. + logic [3:0] dout; + logic [31:0] dout32; + logic [10:0] dout11; + + initial begin + + // Stream operator: << + // Location: rhs of assignment + // + // Test slice sizes from 1 - 5 + dout = { << {4'b0001}}; if (dout != 4'b1000) $stop; + dout = { << 2 {4'b0001}}; if (dout != 4'b0100) $stop; + dout = { << 3 {4'b0001}}; if (dout != 4'b0010) $stop; + dout = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; + + // Stream operator: >> + // Location: rhs of assignment + // + // Right-streaming operator on RHS does not reorder bits + dout = { >> {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { >> 2 {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { >> 3 {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { >> 4 {4'b0001}}; if (dout != 4'b0001) $stop; + dout = { >> 5 {4'b0001}}; if (dout != 4'b0001) $stop; + + // Stream operator: << + // Location: lhs of assignment + { << {dout}} = 4'b0001; if (dout != 4'b1000) $stop; + { << 2 {dout}} = 4'b0001; if (dout != 4'b0100) $stop; + { << 3 {dout}} = 4'b0001; if (dout != 4'b0010) $stop; + { << 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { << 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + + // Stream operator: >> + // Location: lhs of assignment + { >> {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { >> 2 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { >> 3 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { >> 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + { >> 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; + + // Stream operator: << + // Location: lhs of assignment + // RHS is *wider* than LHS + /* verilator lint_off WIDTH */ + { << {dout}} = 5'b00001; if (dout != 4'b1000) $stop; + { << 2 {dout}} = 5'b00001; if (dout != 4'b0100) $stop; + { << 3 {dout}} = 5'b00001; if (dout != 4'b0010) $stop; + { << 4 {dout}} = 5'b00001; if (dout != 4'b0001) $stop; + { << 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + /* verilator lint_on WIDTH */ + + // Stream operator: >> + // Location: lhs of assignment + // RHS is *wider* than LHS + /* verilator lint_off WIDTH */ + { >> {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + { >> 2 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + { >> 3 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + { >> 4 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + { >> 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; + /* verilator lint_on WIDTH */ + + // Stream operator: << + // Location: both sides of assignment + { << {dout}} = { << {4'b0001}}; if (dout != 4'b0001) $stop; + { << 2 {dout}} = { << 2 {4'b0001}}; if (dout != 4'b0001) $stop; + { << 3 {dout}} = { << 3 {4'b0001}}; if (dout != 4'b0100) $stop; + { << 4 {dout}} = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; + { << 5 {dout}} = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; + + // Stream operator: << + // Location: as an operand within a statement + // + // Test slice sizes from 1 - 5 + if (4'({ << {4'b0001}}) != 4'b1000) $stop; + if (4'({ << 2 {4'b0001}}) != 4'b0100) $stop; + if (4'({ << 3 {4'b0001}}) != 4'b0010) $stop; + if (4'({ << 4 {4'b0001}}) != 4'b0001) $stop; + if (4'({ << 5 {4'b0001}}) != 4'b0001) $stop; + + // case + dout32 = { << 3 { 32'b11010111000010100100010010010111 }}; if (dout32 != 32'he92910eb) $stop; + dout11 = { << 4 { 11'b10010010111 }}; if (dout11 != 11'h3cc) $stop; + end + + + // The two always blocks below test run-time evaluation of the stream + // operator in generated C code. + // + // Various stream operators are optimized away. Here's a brief summary: + // + // Stream op on RHS of assign + // -------------------------- + // X = { << a { Y } } --- C function evaluates stream operator + // -- if log2(a) == int --> "fast" eval func + // -- if log2(a) != int --> "slow" eval func + // X = { >> a { Y } } --- stream operator is optimized away + // + // Stream op on LHS of assign + // -------------------------- + // Note: if Y.width() > X.width, then the MSBs of Y are used, not the LSBs! + // { << a { X } } = Y --- stream operator is moved to RHS, eval as above + // { >> a { X } } = Y --- stream operator is optimized away + + logic [31:0] din_i; + logic [63:0] din_q; + logic [95:0] din_w; + + // Stream op on RHS, left-stream operator + logic [31:0] dout_rhs_ls_i; + logic [63:0] dout_rhs_ls_q; + logic [95:0] dout_rhs_ls_w; + + // Stream op on RHS, right-stream operator + logic [31:0] dout_rhs_rs_i; + logic [63:0] dout_rhs_rs_q; + logic [95:0] dout_rhs_rs_w; + + // Stream op on both sides, left-stream operator + logic [31:0] dout_bhs_ls_i; + logic [63:0] dout_bhs_ls_q; + logic [95:0] dout_bhs_ls_w; + + // Stream op on both sides, right-stream operator + logic [31:0] dout_bhs_rs_i; + logic [63:0] dout_bhs_rs_q; + logic [95:0] dout_bhs_rs_w; + + // Stream operator on LHS (with concatenation on LHS) + logic [3:0] din_lhs; + logic [1:0] dout_lhs_ls_a, dout_lhs_ls_b; + logic [1:0] dout_lhs_rs_a, dout_lhs_rs_b; + + // Addition operator on LHS, right-shift tests: + // Testing various shift sizes to exercise fast + slow funcs + logic [22:0] dout_rhs_ls_i_23_3; + logic [22:0] dout_rhs_ls_i_23_4; + + logic [36:0] dout_rhs_ls_q_37_3; + logic [36:0] dout_rhs_ls_q_37_4; + + always @* + begin + // Stream operator: << + // Location: rhs of assignment + // + // Test each data type (I, Q, W) + dout_rhs_ls_i = { << {din_i}}; + dout_rhs_ls_q = { << {din_q}}; + dout_rhs_ls_w = { << {din_w}}; + + // Stream operator: >> + // Location: rhs of assignment + dout_rhs_rs_i = { >> {din_i}}; + dout_rhs_rs_q = { >> {din_q}}; + dout_rhs_rs_w = { >> {din_w}}; + + // Stream operator: << + // Location: lhs of assignment + { << 2 {dout_lhs_ls_a, dout_lhs_ls_b}} = din_lhs; + + // Stream operator: >> + // Location: lhs of assignment + { >> 2 {dout_lhs_rs_a, dout_lhs_rs_b}} = din_lhs; + + // Stream operator: << + // Location: both sides of assignment + { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}}; + { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}}; + { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}}; + + // Stream operator: >> + // Location: both sides of assignment + { >> 5 {dout_bhs_rs_i}} = { >> 5 {din_i}}; + { >> 5 {dout_bhs_rs_q}} = { >> 5 {din_q}}; + { >> 5 {dout_bhs_rs_w}} = { >> 5 {din_w}}; + + // Stream operator: << + // Location: both sides of assignment + { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}}; + { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}}; + { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}}; + + // Stream operator: << + // Location: rhs of assignment + // + // Verify both fast and slow paths (fast: sliceSize = power of 2) + dout_rhs_ls_i_23_3 = { << 3 {din_i[22:0]}}; // SLOW + dout_rhs_ls_i_23_4 = { << 4 {din_i[22:0]}}; // FAST + + dout_rhs_ls_q_37_3 = { << 3 {din_q[36:0]}}; // SLOW + dout_rhs_ls_q_37_4 = { << 4 {din_q[36:0]}}; // FAST + end + + always @(posedge clk) + begin + if (cyc != 0) begin + cyc <= cyc + 1; + + if (cyc == 1) begin + din_i <= 32'h_00_00_00_01; + din_q <= 64'h_00_00_00_00_00_00_00_01; + din_w <= 96'h_00_00_00_00_00_00_00_00_00_00_00_01; + + din_lhs <= 4'b_00_01; + end + if (cyc == 2) begin + din_i <= 32'h_04_03_02_01; + din_q <= 64'h_08_07_06_05_04_03_02_01; + din_w <= 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01; + + din_lhs <= 4'b_01_11; + + if (dout_rhs_ls_i != 32'h_80_00_00_00) $stop; + if (dout_rhs_ls_q != 64'h_80_00_00_00_00_00_00_00) $stop; + if (dout_rhs_ls_w != 96'h_80_00_00_00_00_00_00_00_00_00_00_00) $stop; + + if (dout_rhs_rs_i != 32'h_00_00_00_01) $stop; + if (dout_rhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; + if (dout_rhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; + + if (dout_lhs_ls_a != 2'b_01) $stop; + if (dout_lhs_ls_b != 2'b_00) $stop; + + if (dout_lhs_rs_a != 2'b_00) $stop; + if (dout_lhs_rs_b != 2'b_01) $stop; + + if (dout_bhs_rs_i != 32'h_00_00_00_01) $stop; + if (dout_bhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; + if (dout_bhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; + + if (dout_bhs_ls_i != 32'h_00_00_00_10) $stop; + if (dout_bhs_ls_q != 64'h_00_00_00_00_00_00_01_00) $stop; + if (dout_bhs_ls_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_04) $stop; + + if (dout_rhs_ls_i_23_3 != 23'h_10_00_00) $stop; + if (dout_rhs_ls_i_23_4 != 23'h_08_00_00) $stop; + + if (dout_rhs_ls_q_37_3 != 37'h_04_00_00_00_00) $stop; + if (dout_rhs_ls_q_37_4 != 37'h_02_00_00_00_00) $stop; + end + if (cyc == 3) begin + // The values below test the strange shift-merge done at the end of + // the fast stream operators. + // All-1s in the bits being streamed should end up as all-1s. + din_i <= 32'h_00_7f_ff_ff; + din_q <= 64'h_00_00_00_1f_ff_ff_ff_ff; + + if (dout_rhs_ls_i != 32'h_80_40_c0_20) $stop; + if (dout_rhs_ls_q != 64'h_80_40_c0_20_a0_60_e0_10) $stop; + if (dout_rhs_ls_w != 96'h_80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; + + if (dout_rhs_rs_i != 32'h_04_03_02_01) $stop; + if (dout_rhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; + if (dout_rhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + + if (dout_bhs_ls_i != 32'h_40_30_00_18) $stop; + if (dout_bhs_ls_q != 64'h_06_00_c1_81_41_00_c1_80) $stop; + if (dout_bhs_ls_w != 96'h_30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; + + if (dout_bhs_rs_i != 32'h_04_03_02_01) $stop; + if (dout_bhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; + if (dout_bhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + + if (dout_lhs_ls_a != 2'b_11) $stop; + if (dout_lhs_ls_b != 2'b_01) $stop; + + if (dout_lhs_rs_a != 2'b_01) $stop; + if (dout_lhs_rs_b != 2'b_11) $stop; + + if (dout_rhs_ls_i_23_3 != 23'h_10_08_c0) $stop; + if (dout_rhs_ls_i_23_4 != 23'h_08_10_18) $stop; + + if (dout_rhs_ls_q_37_3 != 37'h_04_02_30_10_44) $stop; + if (dout_rhs_ls_q_37_4 != 37'h_02_04_06_08_0a) $stop; + end + if (cyc == 4) begin + if (dout_rhs_ls_i_23_3 != 23'h_7f_ff_ff) $stop; + if (dout_rhs_ls_i_23_4 != 23'h_7f_ff_ff) $stop; + + if (dout_rhs_ls_q_37_3 != 37'h_1f_ff_ff_ff_ff) $stop; + if (dout_rhs_ls_q_37_4 != 37'h_1f_ff_ff_ff_ff) $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_stream2.v b/SVIncCompil/Testcases/Verilator/t_stream2.v new file mode 100644 index 0000000..148b28e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_stream2.v
@@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [67:0] left; // From test of Test.v + wire [67:0] right; // From test of Test.v + // End of automatics + + wire [6:0] amt = crc[6:0]; + wire [67:0] in = {crc[3:0], crc[63:0]}; + + Test test (/*AUTOINST*/ + // Outputs + .left (left[67:0]), + .right (right[67:0]), + // Inputs + .amt (amt[6:0]), + .in (in[67:0])); + + wire [63:0] result = (left[63:0] ^ {60'h0, left[67:64]} + ^ right[63:0] ^ {60'h0, right[67:64]}); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x amt=%x left=%x right=%x\n", + $time, cyc, crc, result, amt, left, right); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h0da01049b480c38a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + left, right, + // Inputs + amt, in + ); + + input [6:0] amt; + input [67:0] in; + + // amt must be constant + output wire [67:0] left; + output wire [67:0] right; + assign right = { << 33 {in}}; + assign left = { >> 33 {in}}; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_stream3.v b/SVIncCompil/Testcases/Verilator/t_stream3.v new file mode 100644 index 0000000..ec0f4bc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_stream3.v
@@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + /*AUTOWIRE*/ + + generate + for (genvar width=1; width<=16; width++) begin + for (genvar amt=1; amt<=width; amt++) begin + Test #(.WIDTH(width), + .AMT(amt)) + test (.ins(crc[width-1:0])); + end + end + endgenerate + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x\n", + $time, cyc, crc); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Inputs + ins + ); + + parameter WIDTH = 1; + parameter AMT = 1; + + input [WIDTH-1:0] ins; + reg [WIDTH-1:0] got; + reg [WIDTH-1:0] expec; + int istart; + int bitn; + int ostart; + + always @* begin + got = { << AMT {ins}}; + + // Note always starts with right-most bit + expec = 0; + for (istart=0; istart<WIDTH; istart+=AMT) begin + ostart = WIDTH - AMT - istart; + if (ostart<0) ostart = 0; + for (bitn=0; bitn<AMT; bitn++) begin + if ((istart+bitn) < WIDTH + && (istart+bitn) >= 0 + && (ostart+bitn) < WIDTH + && (ostart+bitn) >= 0) begin + expec[ostart+bitn] = ins[istart+bitn]; + end + end + end + +`ifdef TEST_VERBOSE + $write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins); +`endif + `checkh(got, expec); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_string.v b/SVIncCompil/Testcases/Verilator/t_string.v new file mode 100644 index 0000000..3310728 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_string.v
@@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + reg [4*8:1] vstr; + const string s = "a"; // Check static assignment + string s2; + string s3; + reg eq; + + // Operators == != < <= > >= {a,b} {a{b}} a[b] + // a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr + // a.atoi, a.atohex, a.atooct, a.atobin, a.atoreal, + // a.itoa, a.hextoa, a.octoa, a.bintoa, a.realtoa + + initial begin + $sformat(vstr, "s=%s", s); + `checks(vstr, "s=a"); + `checks(s, "a"); + `checks({s,s,s}, "aaa"); + `checks({4{s}}, "aaaa"); + // Constification + `checkh(s == "a", 1'b1); + `checkh(s == "b", 1'b0); + `checkh(s != "a", 1'b0); + `checkh(s != "b", 1'b1); + `checkh(s > " ", 1'b1); + `checkh(s > "a", 1'b0); + `checkh(s >= "a", 1'b1); + `checkh(s >= "b", 1'b0); + `checkh(s < "a", 1'b0); + `checkh(s < "b", 1'b1); + `checkh(s <= " ", 1'b0); + `checkh(s <= "a", 1'b1); + end + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + s2 = "c0"; + end + else if (cyc==1) begin + $sformat(vstr, "s2%s", s2); + `checks(vstr, "s2c0"); + end + else if (cyc==2) begin + s3 = s2; + $sformat(vstr, "s2%s", s3); + `checks(vstr, "s2c0"); + end + else if (cyc==3) begin + s2 = "a"; + s3 = "b"; + end + else if (cyc==4) begin + `checks({s2,s3}, "ab"); + `checks({3{s3}}, "bbb"); + `checkh(s == "a", 1'b1); + `checkh(s == "b", 1'b0); + `checkh(s != "a", 1'b0); + `checkh(s != "b", 1'b1); + `checkh(s > " ", 1'b1); + `checkh(s > "a", 1'b0); + `checkh(s >= "a", 1'b1); + `checkh(s >= "b", 1'b0); + `checkh(s < "a", 1'b0); + `checkh(s < "b", 1'b1); + `checkh(s <= " ", 1'b0); + `checkh(s <= "a", 1'b1); + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_string_type_methods.v b/SVIncCompil/Testcases/Verilator/t_string_type_methods.v new file mode 100644 index 0000000..fb71cb0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_string_type_methods.v
@@ -0,0 +1,119 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + string s; + + integer cyc=0; + + // Check constification + initial begin + s="1234"; `checkh(s.len(),4); +`ifndef VERILATOR + s="1234"; s.putc(2, "z"); `checks(s, "12z4"); + s="1234"; `checkh(s.getc(2), "3"); + s="abCD"; `checks(s.toupper(), "ABCD"); + s="abCD"; `checks(s.tolower(), "abcd"); + s="b"; if (s.compare("a") <= 0) $stop; + s="b"; if (s.compare("b") != 0) $stop; + s="b"; if (s.compare("c") >= 0) $stop; + s="b"; if (s.icompare("A") < 0) $stop; + s="b"; if (s.icompare("B") != 0) $stop; + s="b"; if (s.icompare("C") >= 0) $stop; + s="101"; `checkh(s.atoi(), 'd101); + s="101"; `checkh(s.atohex(), 'h101); + s="101"; `checkh(s.atooct(), 'o101); + s="101"; `checkh(s.atobin(), 'b101); + s="1.23"; `checkg(s.atoreal(), 1.23); +`endif + s.itoa(123); `checks(s, "123"); + s.hextoa(123); `checks(s, "7b"); + s.octtoa(123); `checks(s, "173"); + s.bintoa(123); `checks(s, "1111011"); + s.realtoa(1.23); `checks(s, "1.23"); + end + + // Check runtime + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + s = "1234"; + end + else if (cyc==1) begin + `checkh(s.len(),4); + end +`ifndef VERILATOR + else if (cyc==2) begin + s.putc(2, "z"); + end + else if (cyc==3) begin + `checks(s, "12z4"); + `checkh(s.getc(2), "z"); + s="abCD"; + end + else if (cyc==4) begin + `checks(s.toupper(), "ABCD"); + `checks(s.tolower(), "abcd"); + s="b"; + end + else if (cyc==5) begin + if (s.compare("a") <= 0) $stop; + if (s.compare("b") != 0) $stop; + if (s.compare("c") >= 0) $stop; + if (s.icompare("A") < 0) $stop; + if (s.icompare("B") != 0) $stop; + if (s.icompare("C") >= 0) $stop; + s="101"; + end + else if (cyc==7) begin + `checkh(s.atoi(), 'd101); + `checkh(s.atohex(), 'h101); + `checkh(s.atooct(), 'o101); + `checkh(s.atobin(), 'b101); + s="1.23"; + end + else if (cyc==8) begin + `checkg(s.atoreal(), 1.23); + end +`endif + else if (cyc==9) begin + s.itoa(123); + end + else if (cyc==10) begin + `checks(s, "123"); + s.hextoa(123); + end + else if (cyc==11) begin + `checks(s, "7b"); + s.octtoa(123); + end + else if (cyc==12) begin + `checks(s, "173"); + s.bintoa(123); + end + else if (cyc==13) begin + `checks(s, "1111011"); + s.realtoa(1.23); + end + else if (cyc==14) begin + `checks(s, "1.23"); + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_anon.v b/SVIncCompil/Testcases/Verilator/t_struct_anon.v new file mode 100644 index 0000000..2287a58 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_anon.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// Anonymous +struct packed { + logic [31:0] val1; + logic [31:0] val2; +} struct1; + +struct packed { + logic [31:0] val3; + logic [31:0] val4; +} struct2; + +module t ( + output [63:0] s1, + output [63:0] s2 +); + initial struct1 = 64'h123456789_abcdef0; + always_comb s1 = struct1; + initial struct2 = 64'h123456789_abcdef0; + always_comb s2 = struct2; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_array.v b/SVIncCompil/Testcases/Verilator/t_struct_array.v new file mode 100644 index 0000000..614e537 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_array.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +package TEST_TYPES; + typedef struct packed { + logic stuff; + } a_struct_t; +endpackage // TEST_TYPES + +module t(clk); + input clk; + TEST_TYPES::a_struct_t [3:0] a_out; + sub sub (.a_out); + always @ (posedge clk) begin + if (a_out[0] != 1'b0) $stop; + if (a_out[1] != 1'b1) $stop; + if (a_out[2] != 1'b0) $stop; + if (a_out[3] != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub(a_out); + parameter n = 4; + output TEST_TYPES::a_struct_t [n-1:0] a_out; + always_comb begin + for (int i=0;i<n;i++) + a_out[i].stuff = i[0]; + end +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_init.v b/SVIncCompil/Testcases/Verilator/t_struct_init.v new file mode 100644 index 0000000..40408a5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_init.v
@@ -0,0 +1,127 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + + //Several simulators don't support this. + //typedef struct pack2; // Forward declaration + + typedef struct packed { // [3:0] + bit b3; + bit b2; + bit b1; + bit b0; + } b4_t; + + typedef struct packed { // [3:0] + b4_t x1; + b4_t x0; + } b4x2_t; + + typedef union packed { // [3:0] + bit [3:0] quad0; + b4_t quad1; + } q4_t; + + typedef struct packed { // [5:0] + bit msb; + q4_t four; + bit lsb; + } pack2_t; + + typedef union packed { // [5:0] + pack2_t pack2; + bit [6:1] pvec; + // Vector not allowed in packed structure, per spec: + // bit vec[6]; + // bit vec2d[2][3]; + } pack3_t; + + const b4_t b4_const_a = '{1'b1, 1'b0, 1'b0, 1'b1}; + + // Cast to a pattern - note bits are tagged out of order + const b4_t b4_const_b = b4_t'{ b1 : 1'b0, b0 : 1'b1, b3 : 1'b1, b2 : 1'b0 }; + + wire b4_t b4_wire; + assign b4_wire = '{1'b1, 1'b0, 1'b1, 1'b0}; + + pack2_t arr[2]; + +//`ifdef T_STRUCT_INIT_BAD +// const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1}; +//`endif + + initial begin + pack3_t tsu; + tsu = 6'b110110; + // 543210 + if (tsu!=6'b110110) $stop; + if (tsu[5:4]!=2'b11) $stop; + if (tsu[5:4] == tsu[1:0]) $stop; // Not a good extraction test if LSB subtraction doesn't matter + if (tsu.pvec!=6'b110110) $stop; + if (tsu.pvec[6:5]!=2'b11) $stop; + if (tsu.pack2[5:1] != 5'b11011) $stop; + if (tsu.pack2.msb != 1'b1) $stop; + if (tsu.pack2.lsb != 1'b0) $stop; + if (tsu.pack2.four.quad0 != 4'b1011) $stop; + if (tsu.pack2.four.quad1.b0 != 1'b1) $stop; + if (tsu.pack2.four.quad1.b1 != 1'b1) $stop; + if (tsu.pack2.four.quad1.b2 != 1'b0) $stop; + if (tsu.pack2.four.quad1.b3 != 1'b1) $stop; + // + // tsu = 1'b0 ? '0 : '{pvec: 6'b101011}; + if (tsu!=6'b101011) $stop; + // + arr[0] = 6'b101010; + arr[1] = 6'b010101; + if (arr[0].four !== 4'b0101) $stop; + if (arr[1].four !== 4'b1010) $stop; + // + // Initialization + begin + b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0}; + if (q != 4'b1100) $stop; + end + begin + b4_t q = '{3{1'b1}, 1'b0}; + if (q != 4'b1110) $stop; + end + begin + b4_t q = '{4{1'b1}}; // Repeats the {} + if (q != 4'b1111) $stop; + end + begin + b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}}; + if (m != 8'b10011011) $stop; + end + begin + b4_t q = '{default:1'b1}; + if (q != 4'b1111) $stop; + end + begin + b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0}; + if (q != 4'b1101) $stop; + end + begin + b4_t q = '{b2:1'b0, default:1'b1}; + if (q != 4'b1011) $stop; + end + + if (b4_const_a != 4'b1001) $stop; + if (b4_const_b != 4'b1001) $stop; + if (b4_wire != 4'b1010) $stop; + if (pat(4'b1100, 4'b1100)) $stop; + if (pat('{1'b1, 1'b0, 1'b1, 1'b1}, 4'b1011)) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + + function pat(b4_t in, logic [3:0] cmp); + if (in !== cmp) $stop; + pat = 1'b0; + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_nest.v b/SVIncCompil/Testcases/Verilator/t_struct_nest.v new file mode 100644 index 0000000..9059568 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_nest.v
@@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +typedef struct packed { + logic [1:0] b1; + logic [1:0] b2; + logic [1:0] b3; + logic [1:0] b4; +} t__aa_bbbbbbb_ccccc_dddddd_eee; + +typedef struct packed { + logic [31:0] a; + union packed { + logic [7:0] fbyte; + t__aa_bbbbbbb_ccccc_dddddd_eee pairs; + } b1; + logic [23:0] b2; + logic [7:0] c1; + logic [23:0] c2; + logic [31:0] d; +} t__aa_bbbbbbb_ccccc_dddddd; + +typedef struct packed { + logic [31:0] a; + logic [31:0] b; + logic [31:0] c; + logic [31:0] d; +} t__aa_bbbbbbb_ccccc_eee; + +typedef union packed { + t__aa_bbbbbbb_ccccc_dddddd dddddd; + t__aa_bbbbbbb_ccccc_eee eee; +} t__aa_bbbbbbb_ccccc; + + +module t ( + input t__aa_bbbbbbb_ccccc xxxxxxx_yyyyy_zzzz, + output logic [15:0] datao_pre +); + always_comb datao_pre = { xxxxxxx_yyyyy_zzzz.dddddd.b1.fbyte, xxxxxxx_yyyyy_zzzz.dddddd.c1 }; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_notfound_bad.v b/SVIncCompil/Testcases/Verilator/t_struct_notfound_bad.v new file mode 100644 index 0000000..b029ee6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_notfound_bad.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/); + + typedef struct packed { bit m; } struct_t; + struct_t s; + + initial begin + s.nfmember = 0; // Member not found + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_packed_sysfunct.v b/SVIncCompil/Testcases/Verilator/t_struct_packed_sysfunct.v new file mode 100644 index 0000000..da48372 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_packed_sysfunct.v
@@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_bg; // big endian structure + /* verilator lint_off LITENDIAN */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_lt; // little endian structure + /* verilator lint_on LITENDIAN */ + + integer cnt = 0; + + // event counter + always @ (posedge clk) + begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if (cnt==2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + always @ (posedge clk) + if (cnt==1) begin + // big endian + if ($bits (struct_bg ) != 15) $stop; + if ($bits (struct_bg.e0) != 1) $stop; + if ($bits (struct_bg.e1) != 2) $stop; + if ($bits (struct_bg.e2) != 4) $stop; + if ($bits (struct_bg.e3) != 8) $stop; + if ($increment (struct_bg, 1) != 1) $stop; + // little endian + if ($bits (struct_lt ) != 15) $stop; + if ($bits (struct_lt.e0) != 1) $stop; + if ($bits (struct_lt.e1) != 2) $stop; + if ($bits (struct_lt.e2) != 4) $stop; + if ($bits (struct_lt.e3) != 8) $stop; + if ($increment (struct_lt, 1) != 1) $stop; // Structure itself always big numbered + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_packed_value_list.v b/SVIncCompil/Testcases/Verilator/t_struct_packed_value_list.v new file mode 100644 index 0000000..308547a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_packed_value_list.v
@@ -0,0 +1,114 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam NO = 7; // number of access events + + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_bg; // big endian structure + /* verilator lint_off LITENDIAN */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_lt; // little endian structure + /* verilator lint_on LITENDIAN */ + + localparam WS = 15; // $bits(struct_bg) + + integer cnt = 0; + + // event counter + always @ (posedge clk) + begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'b0) + if (cnt[30:2]==0) struct_bg <= '0; + else if (cnt[30:2]==1) struct_bg <= '0; + else if (cnt[30:2]==2) struct_bg <= '0; + else if (cnt[30:2]==3) struct_bg <= '0; + else if (cnt[30:2]==4) struct_bg <= '0; + else if (cnt[30:2]==5) struct_bg <= '0; + else if (cnt[30:2]==6) struct_bg <= '0; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3}; + else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4}; + else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0}; + // verilator lint_off WIDTH + else if (cnt[30:2]==4) struct_bg <= '{default:13}; + else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1}; + else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; + // verilator lint_on WIDTH + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]==0) begin if (struct_bg !== 15'b0_00_0000_00000000) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'b0) + if (cnt[30:2]==0) struct_lt <= '0; + else if (cnt[30:2]==1) struct_lt <= '0; + else if (cnt[30:2]==2) struct_lt <= '0; + else if (cnt[30:2]==3) struct_lt <= '0; + else if (cnt[30:2]==4) struct_lt <= '0; + else if (cnt[30:2]==5) struct_lt <= '0; + else if (cnt[30:2]==6) struct_lt <= '0; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3}; + else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4}; + else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0}; + // verilator lint_off WIDTH + else if (cnt[30:2]==4) struct_lt <= '{default:13}; + else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1}; + else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; + // verilator lint_on WIDTH + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]==0) begin if (struct_lt !== 15'b0_00_0000_00000000) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_packed_write_read.v b/SVIncCompil/Testcases/Verilator/t_struct_packed_write_read.v new file mode 100644 index 0000000..3b689e9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_packed_write_read.v
@@ -0,0 +1,120 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam NO = 10; // number of access events + + // packed structures + struct packed { + logic e0; + logic [1:0] e1; + logic [3:0] e2; + logic [7:0] e3; + } struct_bg; // big endian structure + /* verilator lint_off LITENDIAN */ + struct packed { + logic e0; + logic [0:1] e1; + logic [0:3] e2; + logic [0:7] e3; + } struct_lt; // little endian structure + /* verilator lint_on LITENDIAN */ + + localparam WS = 15; // $bits(struct_bg) + + integer cnt = 0; + + // event counter + always @ (posedge clk) + begin + cnt <= cnt + 1; + end + + // finish report + always @ (posedge clk) + if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // big endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to 0) + if (cnt[30:2]==0) struct_bg <= '0; + else if (cnt[30:2]==1) struct_bg <= '0; + else if (cnt[30:2]==2) struct_bg <= '0; + else if (cnt[30:2]==3) struct_bg <= '0; + else if (cnt[30:2]==4) struct_bg <= '0; + else if (cnt[30:2]==5) struct_bg <= '0; + end else if (cnt[1:0]==2'd1) begin + // write value to structure + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) struct_bg <= '1; + else if (cnt[30:2]==2) struct_bg.e0 <= '1; + else if (cnt[30:2]==3) struct_bg.e1 <= '1; + else if (cnt[30:2]==4) struct_bg.e2 <= '1; + else if (cnt[30:2]==5) struct_bg.e3 <= '1; + end else if (cnt[1:0]==2'd2) begin + // check structure value + if (cnt[30:2]==0) begin if (struct_bg !== 15'b000000000000000) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_bg !== 15'b100000000000000) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_bg !== 15'b011000000000000) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_bg !== 15'b000111100000000) begin $display("%b", struct_bg); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_bg !== 15'b000000011111111) begin $display("%b", struct_bg); $stop(); end end + end else if (cnt[1:0]==2'd3) begin + // read value from structure (not a very good test for now) + if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'b0}}) $stop(); end + else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end + end + + // little endian + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaaults (all bits to 0) + if (cnt[30:2]==0) struct_lt <= '0; + else if (cnt[30:2]==1) struct_lt <= '0; + else if (cnt[30:2]==2) struct_lt <= '0; + else if (cnt[30:2]==3) struct_lt <= '0; + else if (cnt[30:2]==4) struct_lt <= '0; + else if (cnt[30:2]==5) struct_lt <= '0; + end else if (cnt[1:0]==2'd1) begin + // write value to structure + if (cnt[30:2]==0) begin end + else if (cnt[30:2]==1) struct_lt <= '1; + else if (cnt[30:2]==2) struct_lt.e0 <= '1; + else if (cnt[30:2]==3) struct_lt.e1 <= '1; + else if (cnt[30:2]==4) struct_lt.e2 <= '1; + else if (cnt[30:2]==5) struct_lt.e3 <= '1; + end else if (cnt[1:0]==2'd2) begin + // check structure value + if (cnt[30:2]==0) begin if (struct_lt !== 15'b000000000000000) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==2) begin if (struct_lt !== 15'b100000000000000) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==3) begin if (struct_lt !== 15'b011000000000000) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==4) begin if (struct_lt !== 15'b000111100000000) begin $display("%b", struct_lt); $stop(); end end + else if (cnt[30:2]==5) begin if (struct_lt !== 15'b000000011111111) begin $display("%b", struct_lt); $stop(); end end + end else if (cnt[1:0]==2'd3) begin + // read value from structure (not a very good test for now) + if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'b0}}) $stop(); end + else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end + else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end + else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end + else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end + else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_param.v b/SVIncCompil/Testcases/Verilator/t_struct_param.v new file mode 100644 index 0000000..604b2ee --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_param.v
@@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Matt Myers. + +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +package config_pkg; + typedef struct packed { + int UPPER0; + struct packed { + int USE_QUAD0; + int USE_QUAD1; + int USE_QUAD2; + } mac; + int UPPER2; + } config_struct; + + function automatic config_struct static_config(int selector); + config_struct return_config; + return_config = '0; + return_config.UPPER0 = 10; + return_config.UPPER2 = 20; + return_config.mac.USE_QUAD0 = 4; + return_config.mac.USE_QUAD2 = 6; + case (selector) + 1: return_config.mac.USE_QUAD1 = 5; + endcase + return (return_config); + endfunction +endpackage : config_pkg + +module t; + import config_pkg::*; + + localparam config_struct MY_CONFIG = static_config(1); + + struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I (); +endmodule : t + +module struct_submodule + import config_pkg::*; + #(parameter config_struct MY_CONFIG = '0); + + initial begin + `checkd(MY_CONFIG.UPPER0, 10); + `checkd(MY_CONFIG.mac.USE_QUAD0, 4); + `checkd(MY_CONFIG.mac.USE_QUAD1, 5); + `checkd(MY_CONFIG.mac.USE_QUAD2, 6); + `checkd(MY_CONFIG.UPPER2, 20); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule : struct_submodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_pat_width.v b/SVIncCompil/Testcases/Verilator/t_struct_pat_width.v new file mode 100644 index 0000000..398d1de --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_pat_width.v
@@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +module t (clk); + input clk; + typedef struct packed { + logic [2:0] _foo; + logic [2:0] _bar; + } struct_t; + + logic [2:0] meh; + struct_t param; + localparam integer twentyone = 21; + + // verilator lint_off WIDTH + assign param = '{ + _foo: twentyone % 8 + 1, + _bar: (twentyone / 8) + 1 + }; + assign meh = twentyone % 8 + 1; + // verilator lint_on WIDTH + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $display("param: %d, %d, %b, %d", param._foo, param._bar, param, meh); +`endif + if (param._foo != 6) $stop; + if (param._bar != 3) $stop; + if (param != 6'b110011) $stop; + if (meh != 6) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_port.v b/SVIncCompil/Testcases/Verilator/t_struct_port.v new file mode 100644 index 0000000..3ee634c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_port.v
@@ -0,0 +1,84 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +typedef struct packed { + bit b9; + byte b1; + bit b0; +} pack_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + pack_t in; + always @* in = crc[9:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + pack_t out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out), + // Inputs + .in (in)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {54'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h99c434d9b08c2a8a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test ( + input pack_t in, + output pack_t out); + + always @* begin + out = in; + out.b1 = in.b1 + 1; + out.b0 = 1'b1; + end +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_portsel.v b/SVIncCompil/Testcases/Verilator/t_struct_portsel.v new file mode 100644 index 0000000..d9bbb30 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_portsel.v
@@ -0,0 +1,106 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [19:0] in = crc[19:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [19:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[19:0]), + // Inputs + .in (in[19:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {44'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hdb7bc61592f31b99 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +typedef struct packed { + logic [7:0] cn; + logic vbfval; + logic vabval; +} rel_t; + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [19:0] in; + output [19:0] out; + + rel_t [1:0] i; // From ifb0 of ifb.v, ... + rel_t [1:0] o; // From ifb0 of ifb.v, ... + + assign i = in; + assign out = o; + + sub sub + ( + .i (i[1:0]), + .o (o[1:0])); +endmodule + +module sub (/*AUTOARG*/ + // Outputs + o, + // Inputs + i + ); + + input rel_t [1:0] i; + output rel_t [1:0] o; + assign o = i; +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_unaligned.v b/SVIncCompil/Testcases/Verilator/t_struct_unaligned.v new file mode 100644 index 0000000..9faf1ff --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_unaligned.v
@@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: +// Test an error where a shift amount was out of bounds and the compiler treats the +// value as undefined (Issue #803) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jeff Bush. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + struct packed { + logic flag; + logic [130:0] data; + } foo[1]; + + integer cyc=0; + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + foo[0].data <= 0; + foo[0].flag <= !foo[0].flag; + if (cyc==10) begin + if (foo[0].data != 0) begin + $display("bad data value %x", foo[0].data); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_unpacked.v b/SVIncCompil/Testcases/Verilator/t_struct_unpacked.v new file mode 100644 index 0000000..b499329 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_unpacked.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module x; + + // verilator lint_off UNPACKED + typedef struct { + int a; + } notpacked_t; + // verilator lint_on UNPACKED + + typedef struct packed { + notpacked_t b; + } ispacked_t; + + ispacked_t p; + + initial begin + p.b = 1; + if (p.b != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_struct_unpacked_bad.v b/SVIncCompil/Testcases/Verilator/t_struct_unpacked_bad.v new file mode 100644 index 0000000..a056070 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_struct_unpacked_bad.v
@@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module x; + + typedef struct { + int a; + } notpacked_t; + + typedef struct packed { + notpacked_t b; + } ispacked_t; + + ispacked_t p; + + initial begin + p.b = 1; + if (p.b != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux.v b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux.v new file mode 100644 index 0000000..f62c837 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux.v
@@ -0,0 +1,193 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// // +// This testbench contains a bus source and a bus drain. The source creates // +// address and data bus values, while the drain is the final destination of // +// such pairs. All source and drain transfers are logged into memories, which // +// are used at the end of simulation to check for data transfer correctness. // +// Inside the RLT wrapper there is a multiplexer and a demultiplexer, they // +// bus transfers into a 8bit data stream and back. Both stream input and // +// output are exposed, they are connected together into a loopback. // +// // +// ----------- --------------------- // +// | bso_mem | | wrap | // +// ----------- | | // +// ----------- | | ----------- | // +// | bsi src | ------------> | -> | mux | -> | -> - sto // +// ----------- | ----------- | \ // +// | | | loopback // +// ----------- | ----------- | / // +// | bso drn | <------------ | <- | demux | <- | <- - sti // +// ----------- | | ----------- | // +// ----------- | | // +// | bso_mem | | | // +// ----------- --------------------- // +// // +// PROTOCOL: // +// // +// The 'vld' signal is driven by the source to indicate valid data is // +// available, 'rdy' is used by the drain to indicate is is ready to accept // +// valid data. A data transfer only happens if both 'vld' & 'rdy' are active. // +// // +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + +// include RTL files +`include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv" +`include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv" +`include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv" +`include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + +input clk; + +parameter SIZ = 10; + +// system signals +//logic clk = 1'b1; // clock +logic rst = 1'b1; // reset +integer rst_cnt = 0; + +// input bus +logic bsi_vld; // valid (chip select) +logic [31:0] bsi_adr; // address +logic [31:0] bsi_dat; // data +logic bsi_rdy; // ready (acknowledge) +logic bsi_trn; // data transfer +logic [31:0] bsi_mem [SIZ]; +// output stream +logic sto_vld; // valid (chip select) +logic [7:0] sto_bus; // data bus +logic sto_rdy; // ready (acknowledge) + +// input stream +logic sti_vld; // valid (chip select) +logic [7:0] sti_bus; // data bus +logic sti_rdy; // ready (acknowledge) +// output bus +logic bso_vld; // valid (chip select) +logic [31:0] bso_adr; // address +logic [31:0] bso_dat; // data +logic bso_rdy; // ready (acknowledge) +logic bso_trn; // data transfer +logic [31:0] bso_mem [SIZ]; +integer bso_cnt = 0; + +//////////////////////////////////////////////////////////////////////////////// +// clock and reset +//////////////////////////////////////////////////////////////////////////////// + +// clock toggling +//always #5 clk = ~clk; + +// reset is removed after a delay +always @ (posedge clk) +begin + rst_cnt <= rst_cnt + 1; + rst <= rst_cnt <= 3; +end + +// reset is removed after a delay +always @ (posedge clk) +if (bso_cnt == SIZ) begin + if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end + else begin $display ("FAILED"); $stop(); end +end + +//////////////////////////////////////////////////////////////////////////////// +// input data generator +//////////////////////////////////////////////////////////////////////////////// + +// input data transfer +assign bsi_trn = bsi_vld & bsi_rdy; + +// valid (for SIZ transfers) +always @ (posedge clk, posedge rst) +if (rst) bsi_vld = 1'b0; +else bsi_vld = (bsi_adr < SIZ); + +// address (increments every transfer) +always @ (posedge clk, posedge rst) +if (rst) bsi_adr <= 32'h00000000; +else if (bsi_trn) bsi_adr <= bsi_adr + 'd1; + +// data (new random value generated after every transfer) +always @ (posedge clk, posedge rst) +if (rst) bsi_dat <= 32'h00000000; +else if (bsi_trn) bsi_dat <= $random(); + +// storing transferred data into memory for final check +always @ (posedge clk) +if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat; + +//////////////////////////////////////////////////////////////////////////////// +// RTL instance +//////////////////////////////////////////////////////////////////////////////// + +sv_bus_mux_demux_wrap wrap ( + // system signals + .clk (clk), + .rst (rst), + // input bus + .bsi_vld (bsi_vld), + .bsi_adr (bsi_adr), + .bsi_dat (bsi_dat), + .bsi_rdy (bsi_rdy), + // output stream + .sto_vld (sto_vld), + .sto_bus (sto_bus), + .sto_rdy (sto_rdy), + // input stream + .sti_vld (sti_vld), + .sti_bus (sti_bus), + .sti_rdy (sti_rdy), + // output bus + .bso_vld (bso_vld), + .bso_adr (bso_adr), + .bso_dat (bso_dat), + .bso_rdy (bso_rdy) +); + +// stream output from mux is looped back into stream input for demux +assign sti_vld = sto_vld; +assign sti_bus = sto_bus; +assign sto_rdy = sti_rdy; + +//////////////////////////////////////////////////////////////////////////////// +// output data monitor +//////////////////////////////////////////////////////////////////////////////// + +// input data transfer +assign bso_trn = bso_vld & bso_rdy; + +// output transfer counter used to end the test +always @ (posedge clk, posedge rst) +if (rst) bso_cnt <= 0; +else if (bso_trn) bso_cnt <= bso_cnt + 1; + +// storing transferred data into memory for final check +always @ (posedge clk) +if (bso_trn) bso_mem [bso_adr] <= bso_dat; + +// every output transfer against expected value stored in memory +always @ (posedge clk) +if (bso_trn && (bsi_mem [bso_adr] !== bso_dat)) +$display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat); + +// ready is active for SIZ transfers +always @ (posedge clk, posedge rst) +if (rst) bso_rdy = 1'b0; +else bso_rdy = 1'b1; + +endmodule : sv_bus_mux_demux_tb
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv new file mode 100644 index 0000000..c681946 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv
@@ -0,0 +1,29 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +// definition of data bus structure +package package_bus; + typedef struct packed { + logic [3:0] [7:0] adr; // address + logic [3:0] [7:0] dat; // data + } t_bus; +endpackage : package_bus + +// definition of streaming bus packet as an array +package package_str; + typedef logic [7:0][7:0] t_str; +endpackage : package_str + +// union of the structure and array representation +package package_uni; + import package_bus::*; + import package_str::*; + typedef union packed { + t_bus bus; + t_str str; + } t_uni; +endpackage : package_uni
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv new file mode 100644 index 0000000..4f214ae --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv
@@ -0,0 +1,68 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +import package_bus::*; +import package_str::*; + +module sv_bus_mux_demux_demux ( + // system signals + input logic clk, // clock + input logic rst, // reset + // output stream + input logic str_vld, // valid (chip select) + input logic [7:0] str_bus, // byte data bus + output logic str_rdy, // ready (acknowledge) + // input bus + output logic bus_vld, // valid (chip select) + output logic [31:0] bus_adr, // address + output logic [31:0] bus_dat, // data + input logic bus_rdy // ready (acknowledge) +); + +logic bus_trn; // bus data transfer +logic str_trn; // stream data transfer + +logic [2:0] pkt_cnt; // packet byte counter +logic pkt_end; // packet byte counter end + +t_str pkt_str; // transfer packet as a structure +t_bus pkt_bus; // transfer packet as an array + +// stream data transfer +assign str_trn = str_vld & str_rdy; + +// ready if pipe is empty or output is ready +assign str_rdy = ~bus_vld | bus_rdy; + +// packet byte counter +always @ (posedge clk, posedge rst) +if (rst) pkt_cnt <= 3'd0; +else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; + +// packet byte counter end +assign pkt_end = (&pkt_cnt); + +always @ (posedge clk) +if (str_trn) pkt_str [pkt_cnt] <= str_bus; + +// the input packed array is mapped onto the output structure +assign pkt_bus = pkt_str; + +// the output structure is mapped onto address/data outputs +assign bus_adr = pkt_bus.adr; +assign bus_dat = pkt_bus.dat; + +// output valid is set on the last input packed byte +// or cleared by each output transfer +always @ (posedge clk, posedge rst) +if (rst) bus_vld <= 1'b0; +else bus_vld <= str_trn & pkt_end | bus_vld & ~bus_rdy; + +// bus data transfer +assign bus_trn = bus_vld & bus_rdy; + +endmodule : sv_bus_mux_demux_demux
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv new file mode 100644 index 0000000..93e3200 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv
@@ -0,0 +1,70 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +import package_bus::*; +import package_str::*; +import package_uni::*; + +module sv_bus_mux_demux_mux ( + // system signals + input logic clk, // clock + input logic rst, // reset + // input bus + input logic bus_vld, // valid (chip select) + input logic [31:0] bus_adr, // address + input logic [31:0] bus_dat, // data + output logic bus_rdy, // ready (acknowledge) + // output stream + output logic str_vld, // valid (chip select) + output logic [7:0] str_bus, // byte data bus + input logic str_rdy // ready (acknowledge) +); + +logic bus_trn; // bus data transfer +logic str_trn; // stream data transfer + +logic [2:0] pkt_cnt; // packet byte counter +logic pkt_end; // packet byte counter end + +//t_bus pkt_bus; // transfer packet as a structure +//t_str pkt_str; // transfer packet as an array +t_uni pkt_uni; // transfer packet as an union + +// bus data transfer +assign bus_trn = bus_vld & bus_rdy; + +// ready if pipe is empty or output is ready +assign bus_rdy = ~str_vld | pkt_end; + +// writing input address/data into a structure +always @ (posedge clk) +if (bus_trn) begin + pkt_uni.bus.adr <= bus_adr; + pkt_uni.bus.dat <= bus_dat; +end + +// output valid is set by an input transfer +// or cleared by the last output transfer +always @ (posedge clk, posedge rst) +if (rst) str_vld <= 1'b0; +else str_vld <= bus_trn | (str_vld & ~pkt_end); + +// packet byte counter +always @ (posedge clk, posedge rst) +if (rst) pkt_cnt <= 4'd0; +else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; + +// packet byte counter end +assign pkt_end = str_rdy & (&pkt_cnt); + +// TODO, this should be a registered signal +assign str_bus = pkt_uni.str [pkt_cnt]; + +// stream data transfer +assign str_trn = str_vld & str_rdy; + +endmodule : sv_bus_mux_demux_mux
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv new file mode 100644 index 0000000..0715188 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv
@@ -0,0 +1,82 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// // +// This wrapper contains a bus multiplexer and a bus demultiplexer. Both // +// modules have all ports exposed an there are no signals connecting them. // +// // +// --------------------- // +// | wrap | // +// | | // +// | ----------- | // +// bsi -> | -> | mux | -> | -> sto // +// | ----------- | // +// | | // +// | ----------- | // +// bso <- | <- | demux | <- | <- sto // +// | ----------- | // +// | | // +// --------------------- // +// // +//////////////////////////////////////////////////////////////////////////////// + +module sv_bus_mux_demux_wrap ( + // system signals + input logic clk, + input logic rst, + // input bus + input logic bsi_vld, // valid (chip select) + input logic [31:0] bsi_adr, // address + input logic [31:0] bsi_dat, // data + output logic bsi_rdy, // ready (acknowledge) + // output stream + output logic sto_vld, + output logic [7:0] sto_bus, + input logic sto_rdy, + // input stream + input logic sti_vld, + input logic [7:0] sti_bus, + output logic sti_rdy, + // output bus + output logic bso_vld, // valid (chip select) + output logic [31:0] bso_adr, // address + output logic [31:0] bso_dat, // data + input logic bso_rdy // ready (acknowledge) +); + +sv_bus_mux_demux_mux mux ( + // system signals + .clk (clk), + .rst (rst), + // input bus + .bus_vld (bsi_vld), + .bus_adr (bsi_adr), + .bus_dat (bsi_dat), + .bus_rdy (bsi_rdy), + // output stream + .str_vld (sto_vld), + .str_bus (sto_bus), + .str_rdy (sto_rdy) +); + +sv_bus_mux_demux_demux demux ( + // system signals + .clk (clk), + .rst (rst), + // input stream + .str_vld (sti_vld), + .str_bus (sti_bus), + .str_rdy (sti_rdy), + // output bus + .bus_vld (bso_vld), + .bus_adr (bso_adr), + .bus_dat (bso_dat), + .bus_rdy (bso_rdy) +); + +endmodule : sv_bus_mux_demux_wrap
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_conditional.v b/SVIncCompil/Testcases/Verilator/t_sv_conditional.v new file mode 100644 index 0000000..71f19cd --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_conditional.v
@@ -0,0 +1,476 @@ +// DESCRIPTION: Verilator: System Verilog test of case and if +// +// This code instantiates and runs a simple CPU written in System Verilog. +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty. + +// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + /*AUTOWIRE*/ + + // ************************************************************************** + // Regs and Wires + // ************************************************************************** + + reg rst; + integer rst_count; + + + st3_testbench st3_testbench_i (/*AUTOINST*/ + // Inputs + .clk (clk), + .rst (rst)); + + // ************************************************************************** + // Reset Generation + // ************************************************************************** + + initial begin + rst = 1'b1; + rst_count = 0; + end + + always @( posedge clk ) begin + if (rst_count < 2) begin + rst_count++; + end + else begin + rst = 1'b0; + end + end + + // ************************************************************************** + // Closing message + // ************************************************************************** + + final begin + $write("*-* All Finished *-*\n"); + end + +endmodule + + +module st3_testbench (/*AUTOARG*/ + // Inputs + clk, rst + ); + + input clk; + input rst; + + logic clk; + logic rst; + logic [8*16-1:0] wide_input_bus; + logic decrementA; // 0=Up-counting, 1=down-counting + logic dual_countA; // Advance counter by 2 steps at a time + logic cntA_en; // Enable Counter A + logic decrementB; // 0=Up-counting, 1=down-counting + logic dual_countB; // Advance counter by 2 steps at a time + logic cntB_en; // Enable counter B + logic [47:0] selected_out; + integer i; + + + initial begin + decrementA = 1'b0; + dual_countA = 1'b0; + cntA_en = 1'b1; + decrementB = 1'b0; + dual_countB = 1'b0; + cntB_en = 1'b1; + wide_input_bus = {8'hf5, + 8'hef, + 8'hd5, + 8'hc5, + 8'hb5, + 8'ha5, + 8'h95, + 8'h85, + 8'ha7, + 8'ha6, + 8'ha5, + 8'ha4, + 8'ha3, + 8'ha2, + 8'ha1, + 8'ha0}; + i = 0; + end + + + simple_test_3 + simple_test_3_i + (// Outputs + .selected_out (selected_out[47:0]), + // Inputs + .wide_input_bus (wide_input_bus[8*16-1:0]), + .rst (rst), + .clk (clk), + .decrementA (decrementA), + .dual_countA (dual_countA), + .cntA_en (cntA_en), + .decrementB (decrementB), + .dual_countB (dual_countB), + .cntB_en (cntB_en)); + + + // Logic to print outputs and then finish. + always @(posedge clk) begin + if (i < 50) begin +`ifdef TEST_VERBOSE + $display("%x", simple_test_3_i.cntA_reg ,"%x", + simple_test_3_i.cntB_reg ," ", "%x", selected_out); +`endif + i <= i + 1; + end + else begin + $finish(); + end + end // always @ (posedge clk) + +endmodule + + +// Module testing: +// - Unique case +// - Priority case +// - Unique if +// - ++, --, =- and =+ operands. + +module simple_test_3 + (input logic [8*16-1:0] wide_input_bus, + input logic rst, + input logic clk, + // Counter A + input logic decrementA, // 0=Up-counting, 1=down-counting + input logic dual_countA, // Advance counter by 2 steps at a time + input logic cntA_en, // Enable Counter A + // Counter B + input logic decrementB, // 0=Up-counting, 1=down-counting + input logic dual_countB, // Advance counter by 2 steps at a time + input logic cntB_en, // Enable counter B + + // Outputs + output logic [47:0] selected_out); + + // Declarations + logic [3:0] cntA_reg; // Registered version of cntA + logic [3:0] cntB_reg; // Registered version of cntA + + + counterA + counterA_inst + (/*AUTOINST*/ + // Outputs + .cntA_reg (cntA_reg[3:0]), + // Inputs + .decrementA (decrementA), + .dual_countA (dual_countA), + .cntA_en (cntA_en), + .clk (clk), + .rst (rst)); + + counterB + counterB_inst + (/*AUTOINST*/ + // Outputs + .cntB_reg (cntB_reg[3:0]), + // Inputs + .decrementB (decrementB), + .dual_countB (dual_countB), + .cntB_en (cntB_en), + .clk (clk), + .rst (rst)); + + simple_test_3a + sta + (.wide_input_bus (wide_input_bus), + .selector (cntA_reg), + .selected_out (selected_out[7:0])); + + simple_test_3b + stb + (.wide_input_bus (wide_input_bus), + .selector (cntA_reg), + .selected_out (selected_out[15:8])); + + simple_test_3c + stc + (.wide_input_bus (wide_input_bus), + .selector (cntB_reg), + .selected_out (selected_out[23:16])); + + simple_test_3d + std + (.wide_input_bus (wide_input_bus), + .selector (cntB_reg), + .selected_out (selected_out[31:24])); + + simple_test_3e + ste + (.wide_input_bus (wide_input_bus), + .selector (cntB_reg), + .selected_out (selected_out[39:32])); + + simple_test_3f + stf + (.wide_input_bus (wide_input_bus), + .selector (cntB_reg), + .selected_out (selected_out[47:40])); + + +endmodule // simple_test_3 + + +module counterA + (output logic [3:0] cntA_reg, // Registered version of cntA + input logic decrementA, // 0=Up-counting, 1=down-counting + input logic dual_countA, // Advance counter by 2 steps at a time + input logic cntA_en, // Enable Counter A + input logic clk, // Clock + input logic rst); // Synchronous reset + + + + logic [3:0] cntA; // combinational count variable. + + // Counter A + // Sequential part of counter CntA + always_ff @(posedge clk) + begin + cntA_reg <= cntA; + end + + // Combinational part of counter + // Had to be split up to test C-style update, as there are no + // non-blocking version like -<= + always_comb + if (rst) + cntA = 0; + else begin + cntA = cntA_reg; // Necessary to avoid latch + if (cntA_en) begin + if (decrementA) + if (dual_countA) + //cntA = cntA - 2; + cntA -= 2; + else + //cntA = cntA - 1; + cntA--; + else + if (dual_countA) + //cntA = cntA + 2; + cntA += 2; + else + //cntA = cntA + 1; + cntA++; + end // if (cntA_en) + end +endmodule // counterA + + +module counterB + (output logic [3:0] cntB_reg, // Registered version of cntA + input logic decrementB, // 0=Up-counting, 1=down-counting + input logic dual_countB, // Advance counter by 2 steps at a time + input logic cntB_en, // Enable counter B + input logic clk, // Clock + input logic rst); // Synchronous reset + + // Counter B - tried to write sequential only, but ended up without + // SystemVerilog. + + always_ff @(posedge clk) begin + if (rst) + cntB_reg <= 0; + else + if (cntB_en) begin + if (decrementB) + if (dual_countB) + cntB_reg <= cntB_reg - 2; + else + cntB_reg <= cntB_reg - 1; + // Attempts to write in SystemVerilog: + else + if (dual_countB) + cntB_reg <= cntB_reg + 2; + else + cntB_reg <= cntB_reg + 1; + // Attempts to write in SystemVerilog: + end + end // always_ff @ +endmodule + + +// A multiplexor in terms of look-up +module simple_test_3a + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb + selected_out = {wide_input_bus[selector*8+7], + wide_input_bus[selector*8+6], + wide_input_bus[selector*8+5], + wide_input_bus[selector*8+4], + wide_input_bus[selector*8+3], + wide_input_bus[selector*8+2], + wide_input_bus[selector*8+1], + wide_input_bus[selector*8]}; + +endmodule // simple_test_3a + + +// A multiplexer in terms of standard case +module simple_test_3b + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin + case (selector) + 4'h0: selected_out = wide_input_bus[ 7: 0]; + 4'h1: selected_out = wide_input_bus[ 15: 8]; + 4'h2: selected_out = wide_input_bus[ 23: 16]; + 4'h3: selected_out = wide_input_bus[ 31: 24]; + 4'h4: selected_out = wide_input_bus[ 39: 32]; + 4'h5: selected_out = wide_input_bus[ 47: 40]; + 4'h6: selected_out = wide_input_bus[ 55: 48]; + 4'h7: selected_out = wide_input_bus[ 63: 56]; + 4'h8: selected_out = wide_input_bus[ 71: 64]; + 4'h9: selected_out = wide_input_bus[ 79: 72]; + 4'ha: selected_out = wide_input_bus[ 87: 80]; + 4'hb: selected_out = wide_input_bus[ 95: 88]; + 4'hc: selected_out = wide_input_bus[103: 96]; + 4'hd: selected_out = wide_input_bus[111:104]; + 4'he: selected_out = wide_input_bus[119:112]; + 4'hf: selected_out = wide_input_bus[127:120]; + endcase // case (selector) + + end + +endmodule // simple_test_3b + + +// A multiplexer in terms of unique case +module simple_test_3c + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin + unique case (selector) + 4'h0: selected_out = wide_input_bus[ 7: 0]; + 4'h1: selected_out = wide_input_bus[ 15: 8]; + 4'h2: selected_out = wide_input_bus[ 23: 16]; + 4'h3: selected_out = wide_input_bus[ 31: 24]; + 4'h4: selected_out = wide_input_bus[ 39: 32]; + 4'h5: selected_out = wide_input_bus[ 47: 40]; + 4'h6: selected_out = wide_input_bus[ 55: 48]; + 4'h7: selected_out = wide_input_bus[ 63: 56]; + 4'h8: selected_out = wide_input_bus[ 71: 64]; + 4'h9: selected_out = wide_input_bus[ 79: 72]; + 4'ha: selected_out = wide_input_bus[ 87: 80]; + 4'hb: selected_out = wide_input_bus[ 95: 88]; + 4'hc: selected_out = wide_input_bus[103: 96]; + 4'hd: selected_out = wide_input_bus[111:104]; + 4'he: selected_out = wide_input_bus[119:112]; + 4'hf: selected_out = wide_input_bus[127:120]; + endcase // case (selector) + + end + +endmodule // simple_test_3c + + +// A multiplexer in terms of unique if +module simple_test_3d + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin + unique if (selector == 4'h0) selected_out = wide_input_bus[ 7: 0]; + else if (selector == 4'h1) selected_out = wide_input_bus[ 15: 8]; + else if (selector == 4'h2) selected_out = wide_input_bus[ 23: 16]; + else if (selector == 4'h3) selected_out = wide_input_bus[ 31: 24]; + else if (selector == 4'h4) selected_out = wide_input_bus[ 39: 32]; + else if (selector == 4'h5) selected_out = wide_input_bus[ 47: 40]; + else if (selector == 4'h6) selected_out = wide_input_bus[ 55: 48]; + else if (selector == 4'h7) selected_out = wide_input_bus[ 63: 56]; + else if (selector == 4'h8) selected_out = wide_input_bus[ 71: 64]; + else if (selector == 4'h9) selected_out = wide_input_bus[ 79: 72]; + else if (selector == 4'ha) selected_out = wide_input_bus[ 87: 80]; + else if (selector == 4'hb) selected_out = wide_input_bus[ 95: 88]; + else if (selector == 4'hc) selected_out = wide_input_bus[103: 96]; + else if (selector == 4'hd) selected_out = wide_input_bus[111:104]; + else if (selector == 4'he) selected_out = wide_input_bus[119:112]; + else if (selector == 4'hf) selected_out = wide_input_bus[127:120]; + end + +endmodule // simple_test_3d + + +// Test of priority case +// Note: This does NOT try to implement the same function as above. +module simple_test_3e + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin + priority case (1'b1) + selector[0]: selected_out = wide_input_bus[ 7: 0]; // Bit 0 has highets priority + selector[2]: selected_out = wide_input_bus[ 39: 32]; // Note 2 higher priority than 1 + selector[1]: selected_out = wide_input_bus[ 23: 16]; // Note 1 lower priority than 2 + selector[3]: selected_out = wide_input_bus[ 71: 64]; // Bit 3 has lowest priority + default: selected_out = wide_input_bus[127:120]; // for selector = 0. + endcase // case (selector) + + end + +endmodule // simple_test_3e + + +// Test of "inside" +// Note: This does NOT try to implement the same function as above. +// Note: Support for "inside" is a separate Verilator feature request, so is +// not used inside a this version of the test. +module simple_test_3f + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin +/* -----\/----- EXCLUDED -----\/----- + if ( selector[3:0] inside { 4'b?00?, 4'b1100}) // Matching 0000, 0001, 1000, 1100, 1001 + // if ( selector[3:2] inside { 2'b?0, selector[1:0]}) + selected_out = wide_input_bus[ 7: 0]; + else + -----/\----- EXCLUDED -----/\----- */ + /* verilator lint_off CASEOVERLAP */ + priority casez (selector[3:0]) + 4'b0?10: selected_out = wide_input_bus[ 15: 8]; // Matching 0010 and 0110 + 4'b0??0: selected_out = wide_input_bus[ 23: 16]; // Overlap: only 0100 remains (0000 in "if" above) + 4'b0100: selected_out = wide_input_bus[ 31: 24]; // Overlap: Will never occur + default: selected_out = wide_input_bus[127:120]; // Remaining 0011,0100,0101,0111,1010,1011,1101,1110,1111 + endcase // case (selector) + /* verilator lint_on CASEOVERLAP */ + end + +endmodule // simple_test_3f
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu.v b/SVIncCompil/Testcases/Verilator/t_sv_cpu.v new file mode 100644 index 0000000..efa0449 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu.v
@@ -0,0 +1,146 @@ +// DESCRIPTION: Verilator: System Verilog test of a complete CPU +// +// This code instantiates and runs a simple CPU written in System Verilog. +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty. + +// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + /*AUTOWIRE*/ + + // ************************************************************************** + // Regs and Wires + // ************************************************************************** + + reg rst; + integer rst_count; + integer clk_count; + + + testbench testbench_i (/*AUTOINST*/ + // Inputs + .clk (clk), + .rst (rst)); + + + // ************************************************************************** + // Reset Generation + // ************************************************************************** + + initial begin + rst = 1'b1; + rst_count = 0; + end + + always @( posedge clk ) begin + if (rst_count < 2) begin + rst_count++; + end + else begin + rst = 1'b0; + end + end + + + // ************************************************************************** + // Drive simulation for 500 clock cycles + // ************************************************************************** + + initial begin +`ifdef TEST_VERBOSE + $display( "[testbench] - Start of simulation ----------------------- " ); +`endif + clk_count = 0; + end + + always @( posedge clk ) begin + if (90 == clk_count) begin + $finish (); + end + else begin + clk_count++; + end + end + + final begin +`ifdef TEST_VERBOSE + $display( "[testbench] - End of simulation ------------------------- " ); +`endif + $write("*-* All Finished *-*\n"); + end + + +endmodule + + +module testbench (/*AUTOARG*/ + // Inputs + clk, rst + ); + + input clk; + input rst; + + // ************************************************************************** + // Local parameters + // ************************************************************************** + + localparam + NUMPADS = $size( pinout ); + + + // ************************************************************************** + // Regs and Wires + // ************************************************************************** + + // **** Pinout **** +`ifdef VERILATOR // see t_tri_array + wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}). +`else + wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}). +`endif + + + // ************************************************************************** + // Regs and Wires, Automatics + // ************************************************************************** + + /*AUTOWIRE*/ + + + // ************************************************************************** + // Includes (Testbench extensions) + // ************************************************************************** + + // N/A + + + // ************************************************************************** + // Chip Instance + // ************************************************************************** + + chip + i_chip + ( + /*AUTOINST*/ + // Inouts + .pad (pad[NUMPADS:1]), + // Inputs + .clk (clk), + .rst (rst)); + + +endmodule // test + +// Local Variables: +// verilog-library-directories:("." "t_sv_cpu_code") +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac.sv new file mode 100644 index 0000000..cfc23cb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac.sv
@@ -0,0 +1,70 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +module ac + #( parameter + ID = 1 ) + ( + // *************************************************************************** + // Module Interface (interfaces, outputs, and inputs) + // *************************************************************************** + + // **** Interfaces **** + genbus_if.slave dbus, + pads_if.mp_ana padsif, + + // - System - + input logic clk, + input logic rst + ); + + // *************************************************************************** + // Regs and Wires, Automatics + // *************************************************************************** + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic acenable; // From i_ac_dig of ac_dig.v + logic acout; // From i_ac_ana of ac_ana.v + // End of automatics + + + // *************************************************************************** + // Digital Control + // *************************************************************************** + + ac_dig + #( .ID(ID) ) + i_ac_dig + ( + .dbus (dbus), + /*AUTOINST*/ + // Outputs + .acenable (acenable), + // Inputs + .acout (acout), + .clk (clk), + .rst (rst)); + + + // *************************************************************************** + // Analog Model + // *************************************************************************** + + ac_ana + i_ac_ana + ( + .padsif (padsif), + /*AUTOINST*/ + // Outputs + .acout (acout), + // Inputs + .acenable (acenable), + .clk (clk), + .rst (rst)); + +endmodule // ac
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac_ana.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac_ana.sv new file mode 100644 index 0000000..b8fc092 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac_ana.sv
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +module ac_ana +// #( parameter +// ID = 1 ) + ( + // *************************************************************************** + // Module Interface (interfaces, outputs, and inputs) + // *************************************************************************** + + // **** Interfaces **** + pads_if.mp_ana padsif, + + + // **** Outputs **** + output logic acout, + + + // **** Inputs **** + input logic acenable, + + + // - System - + input logic clk, + input logic rst + ); + + // *************************************************************************** + // Analog Model + // *************************************************************************** + + assign acout = (padsif.ana[1] - padsif.ana[2]) & acenable; + + assign padsif.ana_override[1] = 1'b0; + assign padsif.ana_override[2] = 1'b0; + + +endmodule // ac_ana
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac_dig.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac_dig.sv new file mode 100644 index 0000000..ac71cb3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ac_dig.sv
@@ -0,0 +1,143 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +module ac_dig + #( parameter + ID = 1 ) + ( + // *************************************************************************** + // Module Interface (interfaces, outputs, and inputs) + // *************************************************************************** + + // **** Interfaces **** + genbus_if.slave dbus, + + + // **** Outputs **** + output logic acenable, + + + // **** Inputs **** + input logic acout, + + + // - System - + input logic clk, + input logic rst + ); + + // *************************************************************************** + // Regs and Wires + // *************************************************************************** + + // **** Internal Data Bus **** + logic [15:0] sdata; + logic ws; + logic [15:0] mdata; + logic [15:0] adr; + logic [1:0] we; + logic [1:0] re; + + + // **** User Registers **** + struct packed + { + logic [7:1] reserved; + logic enable; + } control; + + struct packed + { + logic [7:1] reserved; + logic acout; + } status; + + + // **** Internals **** + logic [1:0] sync; + + + // *************************************************************************** + // Assignments + // *************************************************************************** + + assign acenable = control.enable; + + + + // *************************************************************************** + // "dbus" Connection + // *************************************************************************** + + always_comb + begin +`ifdef VERILATOR //TODO + dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr ), .we(we), .re(re) ); +`else + dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr[1:0]), .we(we), .re(re) ); +`endif +// dbus.sConnect( ID, rst, sdata, ws, mdata, adr, we, re ); + end + + + + // *************************************************************************** + // Register Access + // *************************************************************************** + + // **** Register Write **** + always_ff @( posedge clk ) + begin + if ( rst ) + control <= 8'h00; + else if ( (adr[1:0] == 2'b00) & we[0] ) + control <= mdata[7:0]; + end + + + // **** Regiser Read **** + always_comb + begin: RegisterRead + // - Local Variables - + logic [7:0] data[0:3]; // Read access concatination. + + // - Setup read multiplexer - + data = '{ control, + status, + 8'h00, + 8'h00 }; + + // - Connect "genbusif" - + sdata = { 8'h00, data[ adr[1:0] ] }; + ws = 1'b0; + end + + + + // *************************************************************************** + // Status + // *************************************************************************** + + // **** Synchronization **** + always_ff @( posedge clk ) + begin + if ( rst ) + sync <= 2'b00; + else if ( control.enable ) + sync <= {sync[0], acout}; + end + + always_comb + begin + // - Defaults - + status = {$size(status){1'b0}}; + + // - Set register values - + status.acout = sync[1]; + end + +endmodule // ac_dig
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/adrdec.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/adrdec.sv new file mode 100644 index 0000000..acbbad2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/adrdec.sv
@@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +module adrdec + #( parameter + NSLAVES = 2 ) + ( + // *************************************************************************** + // Module Interface (interfaces, outputs, and inputs) + // *************************************************************************** + + // **** Interfaces **** + genbus_if.adrdec dbus + + ); + + // *************************************************************************** + // Address Decode + // *************************************************************************** + +// const logic [15:0] adrmap[1:2] = '{} + + always_comb + begin + logic sel [1:NSLAVES]; + sel[1] = (dbus.s_adr[1][7:4] == 4'h0); + sel[2] = (dbus.s_adr[2][7:4] == 4'h1); +// sel[3] = (dbus.s_adr[3][7:4] == 4'h2); + + dbus.s_sel = sel; +// for ( i = 1; i <= dbus.aNumSlaves; i++ ) +// begin +// dbus.s_sel[i] = (dbus.s_adr[i] == adrmap[i]); +// end + end + +endmodule // adrdec
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/chip.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/chip.sv new file mode 100644 index 0000000..50a5da6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/chip.sv
@@ -0,0 +1,134 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +// ***************************************************************************** +// Top level of System Verilog evalution (Full chip level) +// ***************************************************************************** + +module chip + #( parameter + NUMPADS = $size( pinout ) + ) + ( + // **** Pinout **** +`ifdef VERILATOR // see t_tri_array + inout wire [NUMPADS:1] pad, +`else + inout wire pad [1:NUMPADS], +`endif + + // **** Inputs !!!! **** + input logic clk, + input logic rst + ); + + // *************************************************************************** + // Local Parameters + // *************************************************************************** + + localparam + NSLAVES = 2; + + + + // *************************************************************************** + // PADS + // *************************************************************************** + + // **** Interface **** + pads_if + padsif(); + + + // **** Pad Instansiations **** + pads +// #( ) + i_pads + ( + /*AUTOINST*/ + // Interfaces + .padsif (padsif.mp_pads), + // Inouts + .pad (pad), + // Inputs + .clk (clk), + .rst (rst)); + + + + // *************************************************************************** + // "dbus" Interface + // *************************************************************************** + + genbus_if + #( .NSLAVES(NSLAVES) ) + dbus( .clk(clk), .rst(rst), .test_mode(1'b0) ); + + adrdec +// #( ) + i_adrdec + ( + /*AUTOINST*/ + // Interfaces + .dbus (dbus.adrdec)); + + + + // *************************************************************************** + // CPU ("dbus" Master) + // *************************************************************************** + + cpu + #( .ID(1) ) + i_cpu + ( + /*AUTOINST*/ + // Interfaces + .dbus (dbus.master), + // Inputs + .clk (clk), + .rst (rst)); + + + + // *************************************************************************** + // PORTS ("dbus" Slave #1) + // *************************************************************************** + + ports + #( .ID(1) ) + i_ports + ( + /*AUTOINST*/ + // Interfaces + .dbus (dbus.slave), + .padsif (padsif.mp_dig), + // Inputs + .clk (clk), + .rst (rst)); + + + + // *************************************************************************** + // Analog Comparator ("dbus" Slave #2) + // *************************************************************************** + + ac + #( .ID(2) ) + i_ac + ( + /*AUTOINST*/ + // Interfaces + .dbus (dbus.slave), + .padsif (padsif.mp_ana), + // Inputs + .clk (clk), + .rst (rst)); + + + +endmodule // chip
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/cpu.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/cpu.sv new file mode 100644 index 0000000..c4eced7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/cpu.sv
@@ -0,0 +1,231 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +module cpu + #( parameter + // ... + ID = 1 ) // Not used! + ( + // *************************************************************************** + // Module Interface (interfaces, outputs, and inputs) + // *************************************************************************** + + // **** Interfaces **** + genbus_if.master dbus, + + + // **** Outputs **** + // N/A + + + // **** Inputs **** + input logic clk, + input logic rst + ); + + // *************************************************************************** + // Regs and Wires + // *************************************************************************** + + // **** Program Memory **** + logic [15:0] rom_out; + + + // **** Register File (RF) **** + logic [7:0] rf[0:15]; + + + // **** Fetch Stage **** + logic [7:0] pc; // PC -> Program counter. + logic [15:0] ir; // IR -> Instruction Register. + + + // **** Decode **** + logic [3:0] idec_rd; + logic idec_rd_we; + logic [7:0] idec_rd_data; + logic [3:0] idec_rs; + + logic [7:0] idec_nextpc; // New PC if change of program flow. + + logic idec_coff; // Indicates a change of program flow. + + logic [7:0] idec_mem_adr; + logic idec_mem_re; + logic idec_mem_we; + + + // **** Memory **** + logic [7:0] mem_data; // Data from peripheral. + logic mem_ws; // Waitstate. + + + // *************************************************************************** + // Program Memory (ROM) Interface + // *************************************************************************** + + always_comb + begin: ROM + // - Local Variables - + integer i; + reg [15:0] irom [0:255]; + + // - Set default - + for ( i = 0; i < 256; i++ ) + begin + if ( i < $size(rom) ) + irom[i] = rom[i]; + else + irom[i] = 16'h0000; + end + + rom_out = irom[pc[7:0]]; + end + + + + // *************************************************************************** + // Register File (RF) + // *************************************************************************** + + always_ff @( posedge clk ) + begin: RegFile + // - Local Variables - + integer i; + + // - Register File - + for ( i = 0; i < 16; i++ ) + begin + if ( rst ) + rf[i][7:0] <= 8'h00; + else if ( idec_rd_we & (idec_rd == i[3:0]) ) + rf[i] <= idec_rd_data; + end + end + + + + // *************************************************************************** + // Fetch Stage + // *************************************************************************** + + // **** Program Counter (PC) / Instruction Register (IR) **** + always_ff @( posedge clk ) + begin + if ( rst ) + begin + pc <= 8'h00; + ir <= 16'h0000; + end + else //if ( ~mem_ws ) + begin + if ( ~idec_coff ) + begin + pc <= pc + 1; + ir <= rom_out; // Fetch Instruction. + end + else + begin + pc <= idec_nextpc; + ir <= 16'h0000; // Insert no operation (NOP). + end + end + end + + + + // *************************************************************************** + // Decode/Execute Stage + // *************************************************************************** + + always_comb + begin + // - Defaults - + idec_rd = 4'h0; + idec_rd_we = 1'b0; + idec_rd_data = 8'h00; + idec_rs = 4'h0; + + idec_nextpc = 8'h00; + idec_coff = 1'b0; + + idec_mem_adr = 8'h00; + idec_mem_re = 1'b0; + idec_mem_we = 1'b0; + + casez ( ir ) + 16'h0000:; // NOP (<=> Default) + + 16'h1???: // JMP imm + begin + idec_nextpc = ir[7:0]; + idec_coff = 1'b1; + end + + 16'h4???: // LDI rd, imm + begin + idec_rd = ir[8+:4]; + idec_rd_we = 1'b1; + idec_rd_data = ir[0+:8]; + end + + 16'h8???: + begin // STS imm, rs + idec_mem_adr = ir[0+:8]; + idec_mem_we = 1'b1; + idec_rs = ir[8+:4]; + end + + 16'h9???: + begin // LDS rd, imm + idec_mem_adr = ir[0+:8]; + idec_mem_we = 1'b1; + idec_rd = ir[8+:4]; + idec_rd_we = 1'b1; + idec_rd_data = mem_data[0+:8]; + end + endcase + end + + + + // *************************************************************************** + // Memory Access ("Stage") + // *************************************************************************** + + // **** Connect to "dbus" **** + always_comb + begin: Conntect + reg [15:0] sdata16; + + dbus.mConnect + ( ID, // ID + sdata16, // sdata + mem_ws, // ws + {2{rf[idec_rs]}}, // mdata + // adr + {8'h00, idec_mem_adr[7:1], 1'b0}, + // we + {idec_mem_adr[0],~idec_mem_adr[0]} & {2{idec_mem_we}}, + // re + {idec_mem_adr[0],~idec_mem_adr[0]} & {2{idec_mem_re}} + ); + + // - Connect 16-bit databus to 8-bit CPU - + mem_data = ( idec_mem_adr[0] ) ? sdata16[15:8] : sdata16[7:0]; + end + + + mPreAdrDecode_resp busproperty; + always_comb + begin: PreAdrDecode + // verilator lint_off WIDTH + busproperty = dbus.mPreAdrDecode( 0, idec_mem_adr ); + // verilator lint_on WIDTH + end + +endmodule // cpu
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/genbus_if.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/genbus_if.sv new file mode 100644 index 0000000..082a16a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/genbus_if.sv
@@ -0,0 +1,214 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +typedef struct packed + { + bit [1:0] size; + } mPreAdrDecode_resp; + + +interface genbus_if + #( parameter + DSIZE = 2, + SSIZE = DSIZE, + ASIZE = 16, + NMASTERS = 1, + NSLAVES = 1, + DMSB = (DSIZE<<3) - 1, + SMSB = SSIZE - 1, + AMSB = ASIZE - 1 + ) + ( + // **** Inputs **** + + // - System - + input logic clk, // Device Clock. + input logic rst, // Device Reset. + input logic test_mode // Test mode. + ); + + // *************************************************************************** + // Interface Variables + // *************************************************************************** + + // **** Master **** + logic [DMSB:0] m_sdata[1:NMASTERS]; // Slave data. + logic m_ws [1:NMASTERS]; // Slave wait state. + logic [DMSB:0] m_mdata[1:NMASTERS]; // Master data. + logic [AMSB:0] m_adr [1:NMASTERS]; // Address. + logic [SMSB:0] m_we [1:NMASTERS]; // Write enable. + logic [SMSB:0] m_re [1:NMASTERS]; // Read enable. + + + // **** Slave **** + logic [DMSB:0] s_sdata[1:NSLAVES]; // Slave data (from slave). + logic s_ws [1:NSLAVES]; // Slave wait state (from slave). + logic [DMSB:0] s_mdata[1:NSLAVES]; // Master data (to slave). + logic [AMSB:0] s_adr [1:NSLAVES]; // Address (to slave). + logic [SMSB:0] s_we [1:NSLAVES]; // Write enable (to slave). + logic [SMSB:0] s_re [1:NSLAVES]; // Read enable (to slave). + + + // **** Address Decoder **** + logic s_sel [1:NSLAVES]; // Slave select (to slave). + + + + // *************************************************************************** + // Modports + // *************************************************************************** + + modport master( + import mConnect, + import mPreAdrDecode, + input m_sdata, + input m_ws, + output m_mdata, + output m_adr, + output m_we, + output m_re + ); + + // - Slaves - + modport slave( + import sConnect, + output s_sdata, + output s_ws, + input s_mdata, + input s_adr, + input s_we, + input s_re, + input s_sel + ); + +// UNSUPPORTED +// for (genvar i = 1; i <= NSLAVES; i++ ) +// begin: mps +// modport slave( +// import sConnect, +// output .s_sdata( s_sdata[i] ), +// output .s_ws ( s_ws [i] ), +// input .s_mdata( s_mdata[i] ), +// input .s_adr ( s_adr [i] ), +// input .s_we ( s_we [i] ), +// input .s_re ( s_re [i] ), +// input .s_sel ( s_sel [i] ) +// ); +// end + +// blocks + + modport adrdec( + import aNumSlaves, + input s_adr, + output s_sel + ); + + + + // *************************************************************************** + // Bus Multiplexers + // *************************************************************************** + + always_comb + begin: busmux + // - Local Variables - + integer i; + + // - Defautls - + m_sdata[1] = {(DSIZE<<3){1'b0}}; + m_ws [1] = 1'b0; + + for ( i = 1; i <= NSLAVES; i++ ) + begin + m_sdata[1] |= s_sdata[i]; + m_ws [1] |= s_ws [i]; + + s_mdata[i] = m_mdata[1]; + s_adr [i] = m_adr [1]; + s_we [i] = m_we [1]; + s_re [i] = m_re [1]; + end + end + + + + // *************************************************************************** + // Master Functions and Tasks + // *************************************************************************** + + function automatic void mConnect( input integer id, + output logic [DMSB:0] sdata, + output logic ws, + input logic [DMSB:0] mdata, + input logic [AMSB:0] adr, + input logic [SMSB:0] we, + input logic [SMSB:0] re ); + begin + m_mdata[id] = mdata; + m_adr [id] = adr; + m_we [id] = we; + m_re [id] = re; + + sdata = m_sdata[id]; + ws = m_ws [id]; + end + endfunction + + + function automatic mPreAdrDecode_resp mPreAdrDecode( input integer id, + input logic [AMSB:0] adr ); + begin + // ToDo: Add parameterized address decoding!!!! + + // Example code: + if ( adr[0] ) + mPreAdrDecode.size = 2'b01; // Word (16-bit) memory. + else + mPreAdrDecode.size = 2'b10; // Double Word (32-bit) memory. + end + endfunction + + + + // *************************************************************************** + // Slave Functions and Tasks + // *************************************************************************** + + function automatic void sConnect( input integer id, + input logic rst, + input logic [DMSB:0] sdata, + input logic ws, + output logic [DMSB:0] mdata, + output logic [AMSB:0] adr, + output logic [SMSB:0] we, + output logic [SMSB:0] re ); + begin + s_sdata[id] = sdata & {(DSIZE<<3){s_sel[id]}}; + // verilator lint_off WIDTH + s_ws [id] = ws & {SSIZE{s_sel[id]}}; + // verilator lint_on WIDTH + + mdata = s_mdata[id] & {16{~rst}}; + adr = s_adr [id]; + we = (s_we [id] & {SSIZE{s_sel[id]}}) | {SSIZE{rst}}; + re = s_re [id] & {SSIZE{s_sel[id]}}; + end + endfunction + + + + // *************************************************************************** + // Address Decoder Functions and Tasks + // *************************************************************************** + + + function automatic integer aNumSlaves; + aNumSlaves = NSLAVES; + endfunction + +endinterface // genbus_if
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_gnd.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_gnd.sv new file mode 100644 index 0000000..c9481ed --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_gnd.sv
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +//***************************************************************************** +// PAD_GND - Ground Supply Pad (Dummy!!!!) +//***************************************************************************** + +module pad_gnd +#( parameter ID = 0 ) + ( + inout wire pad + ); + + assign pad = 1'b0; +endmodule // pad_gnd
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_gpio.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_gpio.sv new file mode 100644 index 0000000..18763de --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_gpio.sv
@@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +//***************************************************************************** +// PAD_GPIO - General Purpose I/O Pad (Dummy!!!!) +//***************************************************************************** + +module pad_gpio +#( parameter ID = 0 ) + ( + input logic pullup_en, + input logic pulldown_en, + input logic output_en, + input logic output_val, + input logic slew_limit_en, + input logic input_en, + output logic input_val, + + inout wire ana, + + inout wire pad + ); + + // **** Analog <-> pad connection **** +`ifndef VERILATOR //TODO alias + alias ana = pad; +`endif + + + // **** Digital driver <-> pad connection **** + assign pad = (output_en) ? output_val : 1'bz; + + + // **** Digital pull-up/pull-down <-> pad connection **** + // TO BE ADDED!!!! + + + // **** Digital input <-> pad connection **** + assign input_val = (input_en) ? pad : 1'b0; + + + +endmodule // pad_gpio
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_vdd.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_vdd.sv new file mode 100644 index 0000000..0096dbc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pad_vdd.sv
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +//***************************************************************************** +// PAD_VDD - VDD Supply Pad (Dummy!!!!) +//***************************************************************************** + +module pad_vdd +#( parameter ID = 0 ) + ( + inout wire pad + ); + + assign pad = 1'b1; +endmodule // pad_vdd
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads.sv new file mode 100644 index 0000000..d8ac363 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads.sv
@@ -0,0 +1,94 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +module pads + #( parameter + NUMPADS = $size( pinout ) + ) + ( + // *************************************************************************** + // Module Interface + // *************************************************************************** + + // **** Interfaces **** + pads_if.mp_pads padsif, + + + // **** Pinout **** +`ifdef VERILATOR // see t_tri_array + inout wire [NUMPADS:1] pad, +`else + inout wire pad [1:NUMPADS], +`endif + + // **** Inputs **** + input logic clk, + input logic rst + ); + + + // *************************************************************************** + // Code Section + // *************************************************************************** + +`ifdef VERILATOR // see t_tri_array + tri [NUMPADS:1] _anahack; +`endif + + + genvar i; + for ( i = 1; i <= NUMPADS; i++ ) + begin +`ifdef VCS + localparam t_padtype p_type = t_padtype'(pinout_wa[i][pinout_wa_padtype]); + localparam t_pinid p_id = t_pinid'(pinout_wa[i][pinout_wa_id]); +`else + localparam t_padtype p_type = pinout[i].padtype; + localparam t_pinid p_id = pinout[i].id; +`endif + + case ( p_type ) + PADTYPE_GPIO: + pad_gpio #( .ID( i ) ) + i_pad_gpio( + .pad (pad [i]), + // Outputs + .input_val (padsif.input_val [i]), + // Inouts +`ifdef VERILATOR // see t_tri_array + .ana (_anahack [i]), +`else + .ana (padsif.ana [i]), +`endif + // Inputs + .pullup_en (padsif.pullup_en [i]), + .pulldown_en (padsif.pulldown_en [i]), + .output_en (padsif.output_en [i]), + .output_val (padsif.output_val [i]), + .slew_limit_en (padsif.slew_limit_en[i]), + .input_en (padsif.input_en [i]) + /*AUTOINST*/); + + PADTYPE_VDD: + begin + pad_vdd #( .ID( i ) ) + i_pad_vdd( + .pad (pad[i]) + /*AUTOINST*/); +// Not SV standard, yet... assign padsif.input_val[i] = (); + end + + PADTYPE_GND: + begin + pad_gnd #( .ID( i ) ) + i_pad_gnd(.pad (pad[i]) + /*AUTOINST*/); + end + endcase + end + +endmodule // pads
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads_h.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads_h.sv new file mode 100644 index 0000000..a10ebc5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads_h.sv
@@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +`ifndef _PADS_H_SV_ + `define _PADS_H_SV_ + +// ***************************************************************************** +// +// ***************************************************************************** + +// **** Pin Identifiers **** +typedef enum int +{ + PINID_A0 = 32'd0, // MUST BE ZERO! + // - Standard Ports - + PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7, + PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7, + PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7, + PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7, + PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7, + PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7, + PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7, + PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7, +// PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1 + PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7, + PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7, + PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7, + PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7, + PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7, +// PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0 + PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7, + PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7, + PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7, + // - AUX Port (Custom) - + PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7, + // - PDI Port - + PINID_D2W_DAT, PINID_D2W_CLK, + // - Power Pins - + PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3, + PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3, + // - Maximum number of pins - + PINID_MAX + } t_pinid; + + + +// **** Pad types **** +typedef enum int +{ + PADTYPE_DEFAULT = 32'd0, + PADTYPE_GPIO, // General Purpose I/O Pad (GPIO). + PADTYPE_GPIO_ANA, // GPIO with Analog connection. Low noise GPIO. + PADTYPE_GPIO_HDS, // GPIO with High Drive Strength. + PADTYPE_VDD, // VDD Supply Pad + PADTYPE_GND // Ground Pad + } t_padtype; + + + +`endif // !`ifdef _PADS_H_SV_
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads_if.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads_if.sv new file mode 100644 index 0000000..81083a9 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pads_if.sv
@@ -0,0 +1,100 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + + +interface pads_if(); + + // *************************************************************************** + // Local Parameters + // *************************************************************************** + + localparam + NUMPADS = $size( pinout ); + + + // *************************************************************************** + // Interface Variables + // *************************************************************************** + + // - PADS Digital Interface - + logic pullup_en [1:NUMPADS];// Pull-up/down/bus-keeper enable. + logic pulldown_en [1:NUMPADS];// Pull direction (0:Pull-up; 1:Pull-down). + logic output_en [1:NUMPADS];// Digital output buffer enable. + logic output_val [1:NUMPADS];// Digital output value. + logic input_en [1:NUMPADS];// Digital input buffer enable. + logic slew_limit_en [1:NUMPADS];// Slew rate limiter enable. + logic input_val [1:NUMPADS];// Digital input value. + + // - PADS Analog Interface - + logic ana_override [1:NUMPADS];// Disables digital output when driving analog output. + wire ana [1:NUMPADS]; + + + + // *************************************************************************** + // Modports + // *************************************************************************** + + modport mp_pads( + input pullup_en, + input pulldown_en, + input output_en, + input output_val, + input slew_limit_en, + input input_en, + output input_val, + input ana_override, + inout ana ); + + modport mp_dig( + import IsPad, + import IsPort, + import Init, + output pullup_en, + output pulldown_en, + output output_en, + output output_val, + output slew_limit_en, + output input_en, + input input_val ); + + modport mp_ana( + import IsPad, + output ana_override, + inout ana ); + + + + // *************************************************************************** + // Check for which pins exists + // *************************************************************************** + + bit [PINID_D7:PINID_A0] exists; + + function automatic void Init( ); + exists = {(PINID_D7+1){1'b0}}; + for ( int i = 1; i <= $size( pinout ); i++ ) + if ( PINID_D7 >= pinout[i].id ) + exists[pinout[i].id] = 1'b1; + endfunction + + + // *************************************************************************** + // Functions and Tasks + // *************************************************************************** + + function automatic bit IsPad( integer i ); + IsPad = exists[i]; + endfunction + + function automatic bit IsPort( integer i ); + IsPort = |exists[8*i+:8]; + endfunction + + + +endinterface // pads_if
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pinout_h.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pinout_h.sv new file mode 100644 index 0000000..0828897 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/pinout_h.sv
@@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +`ifndef _PINOUT_H_SV_ + `define _PINOUT_H_SV_ + +// ***************************************************************************** +// Structs/Unions +// ***************************************************************************** + +// **** Pin Descriptor **** + +// - Pin Descriptor - +typedef struct packed +{ + t_pinid id; + t_padtype padtype; + int aux; +} t_pin_descriptor; + + + +// ***************************************************************************** +// Pinout +// ***************************************************************************** + +// **** Preferred Solution !!!! **** +localparam t_pin_descriptor + pinout[ 1: 6] + = '{ + '{default:0, id:PINID_A0, padtype:PADTYPE_GPIO, aux:1}, + '{default:0, id:PINID_A1, padtype:PADTYPE_GPIO}, + '{default:0, id:PINID_A2, padtype:PADTYPE_GPIO}, + '{default:0, id:PINID_D0, padtype:PADTYPE_GPIO}, + '{default:0, id:PINID_VDD0, padtype:PADTYPE_VDD}, + '{default:0, id:PINID_GND0, padtype:PADTYPE_GND} + }; + + +// **** Workaround !!!! **** +typedef enum int +{ + pinout_wa_id = 1, + pinout_wa_padtype, + pinout_wa_aux + } t_pinout_wa; + +localparam int pinout_size = 6; +localparam int pinout_wa[1:pinout_size][pinout_wa_id:pinout_wa_aux] = +'{ + '{PINID_A0, PADTYPE_GPIO, 0}, + '{PINID_A1, PADTYPE_GPIO, 0}, + '{PINID_A2, PADTYPE_GPIO, 0}, + '{PINID_D0, PADTYPE_GPIO, 0}, + '{PINID_VDD0, PADTYPE_VDD, 0}, + '{PINID_GND0, PADTYPE_GND , 0} + }; + + + +`endif // `ifndef _PINOUT_H_SV_ + +// **** End of File ****
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ports.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ports.sv new file mode 100644 index 0000000..6a84f75 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ports.sv
@@ -0,0 +1,167 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +`ifdef VERILATOR //TODO + `define PACKED packed +`else + `define packed +`endif + +module ports + #( parameter + ID = 1 ) + ( + // *************************************************************************** + // Module Interface (interfaces, outputs, and inputs) + // *************************************************************************** + + genbus_if.slave dbus, + pads_if.mp_dig padsif, + + // - System - + input logic clk, + input logic rst + ); + + // *************************************************************************** + // Regs and Wires + // *************************************************************************** + + // **** Internal Data Bus **** + logic [15:0] sdata; + logic ws; + logic [15:0] mdata; + logic [15:0] adr; + logic [1:0] we; + logic [1:0] re; + + + // **** Interal Registers **** + struct `PACKED + { + logic [7:0][1:0] in; + logic [7:0] dir; + logic [7:0] out; + struct `PACKED + { + logic [7:2] reserved; + logic pullupen; + logic slewlim; + } cfg; + } port [PORTID_A:PORTID_D]; + + // *************************************************************************** + // "dbus" Connection + // *************************************************************************** + + always_comb + begin: dbus_Connect + dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr), .we(we), .re(re) ); + end + + + + // *************************************************************************** + // Register Access + // For PORTA...PORTD (Excluding I and O) + // +0x00 DIR + // +0x01 OUT + // +0x02 IN + // +0x03 CFG + // *************************************************************************** + + always_comb begin padsif.Init(); end + + // **** Register Write **** + always_ff @( posedge clk ) + begin + // - Local Variables - + integer i, j; + + // **** Setup Port Registers **** + for ( j = PORTID_A; j <= PORTID_D; j++ ) + begin + if ( padsif.IsPort( j ) ) + begin + if ( ((adr[3:2] == j[1:0]) && (adr[1] == 1'b0)) | rst ) + begin + if ( we[0] ) + port[j].dir <= mdata[7:0]; + if ( we[1] ) + port[j].out <= mdata[15:8]; + end + end + else + begin + port[j].dir <= 8'h00; + port[j].out <= 8'h00; + end + end + end + + + // **** Regiser Read **** + always_comb + begin: RegisterRead + // - Local Variables - + integer i, j; + logic [7:0] data [PORTID_D:PORTID_A][3:0]; + + + // **** Output to "dbus" **** + + // - Setup read multiplexer - + for ( j = PORTID_A; j <= PORTID_D; j++ ) + begin + if ( padsif.IsPort( j ) ) + data[j] = '{ port[j].dir, port[j].out, 8'h00, 8'h00 }; + else + data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 }; + end + + // - Connect "genbusif" - + sdata = { 8'h00, data[ adr[3:2] ][ adr[1:0] ] }; + ws = 1'b0; + end + + + + // *************************************************************************** + // Output + // *************************************************************************** + + always_comb + begin + // - Local Variables - + integer i, j; + + + // **** Defaults **** + for ( i = 1; i <= $size( pinout ); i++ ) + begin + padsif.pullup_en [i] = 1'b0; + padsif.pulldown_en [i] = 1'b0; + padsif.output_en [i] = 1'b0; + padsif.output_val [i] = 1'b0; + padsif.slew_limit_en[i] = 1'b0; + padsif.input_en [i] = 1'b0; + end + + + // **** Connect to Pads **** + for ( i = 1; i <= $size( pinout ); i++ ) + begin + j = pinout[i].id; + if ( PINID_D7 >= j ) + begin + padsif.output_en [i] = port[j[4:3]].dir[j[2:0]]; + padsif.output_val[i] = port[j[4:3]].out[j[2:0]]; + end + end + end + +endmodule // ports
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ports_h.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ports_h.sv new file mode 100644 index 0000000..6a6c970 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/ports_h.sv
@@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +`ifndef _PORTS_H_SV_ + `define _PORTS_H_SV_ + +// ***************************************************************************** +// +// ***************************************************************************** + +// !!!! Incomplete! +localparam int str_pinid [0:15] = +'{ + "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" + }; + + +// **** Port Identifiers **** +typedef enum int +{ + PORTID_A = 32'd0, // MUST BE ZERO! + PORTID_B, + PORTID_C, + PORTID_D, + PORTID_E, + PORTID_F, + PORTID_G, + PORTID_H, + // PORTID_I, -> DO NOT USE! + PORTID_J, + PORTID_K, + PORTID_L, + PORTID_M, + PORTID_N, + // PORTID_O, -> DO NOT USE! + PORTID_P, + PORTID_Q, + PORTID_R + } t_portid; + + + +`endif // !`ifdef _PORTS_H_SV_ + +// **** End of File ****
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/program_h.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/program_h.sv new file mode 100644 index 0000000..33ab17b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/program_h.sv
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +`ifndef _PROGRAM_H_V_ + `define _PROGRAM_H_V_ + +// ***************************************************************************** +// Assembly Mnemonic Defines +// ***************************************************************************** + +typedef enum reg [3:0] { R0,R1,R2,R3,R4,R5,R6,R7, + R8,R9,R10,R11,R12,R13,R14,R15 } cpu_registers; + +`define NOP 16'h0000, +`define JMP( k8 ) {4'h1, 4'h0, 8'h k8}, +`define LDI( rd, k8 ) {4'h4, rd, 8'h k8}, +`define STS( k8, rs ) {4'h8, rs, 8'h k8}, +`define LDS( rd, k8 ) {4'h9, rd, 8'h k8}, +`define EOP 16'h0000 + + + +// ***************************************************************************** +// Include ROM +// ***************************************************************************** + +`include "rom.sv" + +`endif // !`ifdef _PROGRAM_H_V_
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/rom.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/rom.sv new file mode 100644 index 0000000..6e5c05a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/rom.sv
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +// ***************************************************************************** +// Code ROM +// +// IMPORTANT! +// Array size must be uppdated according to program size. +// ***************************************************************************** + +const + logic [15:0] rom[0:13] + = '{ + `LDI( R0, 11 ) + `LDI( R1, 22 ) + `LDI( R2, 33 ) + `LDI( R3, 44 ) + + `STS( 0, R0 ) + `STS( 1, R1 ) + `STS( 2, R2 ) + `STS( 3, R3 ) + + `LDS( R4, 0 ) + `LDS( R5, 1 ) + `LDS( R6, 0 ) + `LDS( R7, 0 ) + + `JMP( 00 ) + + `EOP // End of Program (NOP) + };
diff --git a/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/timescale.sv b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/timescale.sv new file mode 100644 index 0000000..1bb5010 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sv_cpu_code/timescale.sv
@@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Large test for SystemVerilog + +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. + +// Contributed by M W Lund, Atmel Corporation. + +// **** Set simulation time scale **** +`timescale 1ns/1ps
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_file_basic.v b/SVIncCompil/Testcases/Verilator/t_sys_file_basic.v new file mode 100644 index 0000000..c4fc6f0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_file_basic.v
@@ -0,0 +1,245 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +`include "verilated.v" + +`define STRINGIFY(x) `"x`" +`define ratio_error(a,b) (((a)>(b) ? ((a)-(b)) : ((b)-(a))) /(a)) +`define checkr(gotv,expv) do if (`ratio_error((gotv),(expv))>0.0001) begin $write("%%Error: %s:%0d: got=%g exp=%g\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t; + integer file; + + integer chars; + reg [1*8:1] letterl; + reg [8*8:1] letterq; + reg [16*8:1] letterw; + reg [16*8:1] letterz; + real r; + string s; + + reg [7:0] v_a,v_b,v_c,v_d; + reg [31:0] v_worda; + reg [31:0] v_wordb; + +`ifdef TEST_VERBOSE + `define verbose 1'b1 +`else + `define verbose 1'b0 +`endif + + initial begin + // Display formatting +`ifdef verilator + if (file != 0) $stop; + $fwrite(file, "Never printed, file closed\n"); + if (!$feof(file)) $stop; +`endif + +`ifdef AUTOFLUSH + // The "w" is required so we get a FD not a MFD + file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_autoflush.log"},"w"); +`else + // The "w" is required so we get a FD not a MFD + file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_basic_test.log"},"w"); +`endif + if ($feof(file)) $stop; + + $fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667); + $fwrite(file, "[%0t] %s\n", $time, "Hello2"); + $fflush(file); + + $fclose(file); +`ifdef verilator + if (file != 0) $stop(1); // Also test arguments to stop + $fwrite(file, "Never printed, file closed\n"); +`endif + + begin + // Check for opening errors + // The "r" is required so we get a FD not a MFD + file = $fopen("DOES_NOT_EXIST","r"); + if (|file) $stop; // Should not exist, IE must return 0 + end + + begin + // Check quadword access; a little strange, but it's legal to open "." + file = $fopen(".","r"); + $fclose(file); + end + + begin + // Check read functions w/string + s = "t/t_sys_file_basic_input.dat"; + file = $fopen(s,"r"); + if ($feof(file)) $stop; + $fclose(file); + end + + begin + // Check read functions + file = $fopen("t/t_sys_file_basic_input.dat","r"); + if ($feof(file)) $stop; + + // $fgetc + if ($fgetc(file) != "h") $stop; + if ($fgetc(file) != "i") $stop; + if ($fgetc(file) != "\n") $stop; + + // $fgets + chars = $fgets(letterl, file); + if (`verbose) $write("c=%0d l=%s\n", chars, letterl); + if (chars != 1) $stop; + if (letterl != "l") $stop; + + chars = $fgets(letterq, file); + if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline + if (chars != 5) $stop; + if (letterq != "\0\0\0quad\n") $stop; + + letterw = "5432109876543210"; + chars = $fgets(letterw, file); + if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline + if (chars != 10) $stop; + if (letterw != "\0\0\0\0\0\0widestuff\n") $stop; + + // $sscanf + if ($sscanf("x","")!=0) $stop; + if ($sscanf("z","z")!=0) $stop; + + chars = $sscanf("blabcdefghijklmnop", + "%s", letterq); + if (`verbose) $write("c=%0d sa=%s\n", chars, letterq); + if (chars != 1) $stop; + if (letterq != "ijklmnop") $stop; + + chars = $sscanf("xa=1f xb=12898971238912389712783490823_abcdef689_02348923", + "xa=%x xb=%x", letterq, letterw); + if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw); + if (chars != 2) $stop; + if (letterq != 64'h1f) $stop; + if (letterw != 128'h389712783490823_abcdef689_02348923) $stop; + + chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ", + "ba=%b bb=%b%s", letterq, letterw, letterz); + if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz); + if (chars != 3) $stop; + if (letterq != 64'h2) $stop; + if (letterw != 128'hd2a55) $stop; + if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop; + + chars = $sscanf("oa=23 ob=125634123615234123681236", + "oa=%o ob=%o", letterq, letterw); + if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw); + if (chars != 2) $stop; + if (letterq != 64'h13) $stop; + if (letterw != 128'h55ce14f1a9c29e) $stop; + + chars = $sscanf("r=0.1 d=-236123", + "r=%g d=%d", r, letterq); + if (`verbose) $write("c=%0d d=%d\n", chars, letterq); + if (chars != 2) $stop; + `checkr(r, 0.1); + if (letterq != 64'hfffffffffffc65a5) $stop; + + // Cover quad and %e/%f + chars = $sscanf("r=0.2", + "r=%e", r); + if (`verbose) $write("c=%0d r=%e\n", chars, r); + `checkr(r, 0.2); + + chars = $sscanf("r=0.3", + "r=%f", r); + if (`verbose) $write("c=%0d r=%f\n", chars, r); + `checkr(r, 0.3); + + s = "r=0.2 d=-236124"; + chars = $sscanf(s, "r=%g d=%d", r, letterq); + if (`verbose) $write("c=%0d d=%d\n", chars, letterq); + if (chars != 2) $stop; + `checkr(r, 0.2); + if (letterq != 64'hfffffffffffc65a4) $stop; + + // $fscanf + if ($fscanf(file,"")!=0) $stop; + + if (!sync("*")) $stop; + chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw); + if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw); + if (chars != 2) $stop; + if (letterq != 64'h1f) $stop; + if (letterw != 128'h23790468902348923) $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz); + if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz); + if (chars != 3) $stop; + if (letterq != 64'h2) $stop; + if (letterw != 128'hd2a55) $stop; + if (letterz != "\0\0\0\0note_the_two") $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw); + if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw); + if (chars != 2) $stop; + if (letterq != 64'h13) $stop; + if (letterw != 128'h1573) $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "d=%d", letterq); + if (`verbose) $write("c=%0d d=%0x\n", chars, letterq); + if (chars != 1) $stop; + if (letterq != 64'hfffffffffffc65a5) $stop; + + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "%c%s", letterl, letterw); + if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw); + if (chars != 2) $stop; + if (letterl != "f") $stop; + if (letterw != "\0\0\0\0\0redfishblah") $stop; + + chars = $fscanf(file, "%c", letterl); + if (`verbose) $write("c=%0d l=%x\n", chars, letterl); + if (chars != 1) $stop; + if (letterl != "\n") $stop; + + // msg1229 + v_a = $fgetc(file); + v_b = $fgetc(file); + v_c = $fgetc(file); + v_d = $fgetc(file); + v_worda = { v_d, v_c, v_b, v_a }; + if (v_worda != "4321") $stop; + + v_wordb[7:0] = $fgetc(file); + v_wordb[15:8] = $fgetc(file); + v_wordb[23:16] = $fgetc(file); + v_wordb[31:24] = $fgetc(file); + if (v_wordb != "9876") $stop; + + if ($fgetc(file) != "\n") $stop; + + $fclose(file); + end + + $write("*-* All Finished *-*\n"); + $finish(0); // Test arguments to finish + end + + function sync; + input [7:0] cexp; + reg [7:0] cgot; + begin + cgot = $fgetc(file); + if (`verbose) $write("sync=%x='%c'\n", cgot,cgot); + sync = (cgot == cexp); + end + endfunction + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_file_scan.v b/SVIncCompil/Testcases/Verilator/t_sys_file_scan.v new file mode 100644 index 0000000..e3c51bb --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_file_scan.v
@@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`include "verilated.v" + +`define STRINGIFY(x) `"x`" + +module t; + integer infile, outfile; + integer count, a; + + initial begin + infile = $fopen("t/t_sys_file_scan_input.dat", "r"); + outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_scan_test.log"}, "w"); + + count = 1234; +`ifdef TEST_VERBOSE + $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); +`endif + count = $fscanf(infile, "%d\n", a); +`ifdef TEST_VERBOSE + // Ifdefing this out gave bug248 + $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); +`endif + if (count == 0) $stop; + $fwrite(outfile, "# a\n"); + $fwrite(outfile, "%d\n", a); + $fclose(infile); + $fclose(outfile); + + $write("*-* All Finished *-*\n"); + $finish(0); // Test arguments to finish + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_fread.v b/SVIncCompil/Testcases/Verilator/t_sys_fread.v new file mode 100644 index 0000000..9f44ce0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_fread.v
@@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +`define STRINGIFY(x) `"x`" +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +//====================================================================== + +module t; + integer file; + integer r_i; + byte r_upb[20:10]; + byte r_dnb[20:10]; + reg [13:0] r_ups[20:10]; + reg [13:0] r_dns[10:20]; + reg [30:0] r_upi[20:10]; + reg [30:0] r_dni[10:20]; + reg [61:0] r_upq[20:10]; + reg [61:0] r_dnq[10:20]; + reg [71:0] r_upw[20:10]; + reg [71:0] r_dnw[10:20]; + + task clear; + // Initialize memories to zero, + // avoid differences between 2-state and 4-state. + r_i = ~0; + foreach (r_upb[i]) r_upb[i] = ~0; + foreach (r_dnb[i]) r_dnb[i] = ~0; + foreach (r_ups[i]) r_ups[i] = ~0; + foreach (r_dns[i]) r_dns[i] = ~0; + foreach (r_upi[i]) r_upi[i] = ~0; + foreach (r_dni[i]) r_dni[i] = ~0; + foreach (r_upq[i]) r_upq[i] = ~0; + foreach (r_dnq[i]) r_dnq[i] = ~0; + foreach (r_upw[i]) r_upw[i] = ~0; + foreach (r_dnw[i]) r_dnw[i] = ~0; + + // Open file + $fclose(file); + file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r"); + if ($feof(file)) $stop; + endtask + + task dump; + $write("Dump:"); + $write("\n r_i:"); $write(" %x",r_i); + $write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]); + $write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]); + $write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]); + $write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]); + $write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]); + $write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]); + $write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]); + $write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]); + $write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]); + $write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]); + $write("\n\n"); + endtask + + integer code; + + initial begin + clear; + code = $fread(r_i, file); `checkd(code, 4); + code = $fread(r_upb, file); `checkd(code, 11); + code = $fread(r_dnb, file); `checkd(code, 11); + code = $fread(r_ups, file); `checkd(code, 22); + code = $fread(r_dns, file); `checkd(code, 22); + code = $fread(r_upi, file); `checkd(code, 44); + code = $fread(r_dni, file); `checkd(code, 44); + code = $fread(r_upq, file); `checkd(code, 88); + code = $fread(r_dnq, file); `checkd(code, 88); + code = $fread(r_upw, file); `checkd(code, 99); + code = $fread(r_dnw, file); `checkd(code, 99); + dump; + + clear; + code = $fread(r_upb, file, 15); `checkd(code, 6); + code = $fread(r_ups, file, 15, 2); `checkd(code, 4); + dump; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_plusargs.v b/SVIncCompil/Testcases/Verilator/t_sys_plusargs.v new file mode 100644 index 0000000..8de3437 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_plusargs.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + + integer p_i; + reg [7*8:1] p_str; + string sv_str; + reg [7*8:1] p_in; + string sv_in; + + initial begin + if ($test$plusargs("PLUS")!==1) $stop; + if ($test$plusargs("PLUSNOT")!==0) $stop; + if ($test$plusargs("PL")!==1) $stop; + //if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer + if ($test$plusargs("NOTTHERE")!==0) $stop; + + p_i = 10; + if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop; + if (p_i !== 10) $stop; + + p_i = 0; + if ($value$plusargs("INT=%d", p_i)!==1) $stop; + if (p_i !== 32'd1234) $stop; + + p_i = 0; + if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also + if (p_i !== 32'h1234) $stop; + + p_i = 0; + // Check octal and WIDTH + if (!$value$plusargs("INT=%o", p_i)) $stop; + if (p_i !== 32'o1234) $stop; + + p_str = "none"; + if ($value$plusargs("IN%s", p_str)!==1) $stop; + $display("str='%s'",p_str); + if (p_str !== "T=1234") $stop; + + sv_str = "none"; + if ($value$plusargs("IN%s", sv_str)!==1) $stop; + $display("str='%s'",sv_str); + if (sv_str != "T=1234") $stop; + + sv_str = "none"; + $value$plusargs("IN%s", sv_str); + $display("str='%s'",sv_str); + if (sv_str != "T=1234") $stop; + + p_in = "IN%s"; +`ifdef VERILATOR + p_in = $c(p_in); // Prevent constant propagation +`endif + sv_str = "none"; + if ($value$plusargs(p_in, sv_str)!==1) $stop; + $display("str='%s'",sv_str); + if (sv_str != "T=1234") $stop; + + sv_in = "INT=%d"; +`ifdef VERILATOR + if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation +`endif + p_i = 0; + if ($value$plusargs(sv_in, p_i)!==1) $stop; + $display("i='%d'",p_i); + if (p_i !== 32'd1234) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_plusargs_bad.v b/SVIncCompil/Testcases/Verilator/t_sys_plusargs_bad.v new file mode 100644 index 0000000..d3a149b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_plusargs_bad.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + + integer p_i; + + initial begin + // BAD: Missing argument + if ($value$plusargs("NOTTHERE", p_i)!==0) $stop; + + // BAD: Bad letter + if ($value$plusargs("INT=%z", p_i)!==0) $stop; + + // BAD: Multi letter + if ($value$plusargs("INT=%x%x", p_i)!==0) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_rand.v b/SVIncCompil/Testcases/Verilator/t_sys_rand.v new file mode 100644 index 0000000..80287fe --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_rand.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + + reg [31:0] lastrand; + reg [31:0] thisrand; + + integer same = 0; + integer i; + +`define TRIES 20 + + initial begin + // There's a 1^32 chance of the numbers being the same twice, + // so we'll allow one failure + lastrand = $random; + for (i=0; i<`TRIES; i=i+1) begin + thisrand = $random; +`ifdef TEST_VERBOSE + $write("Random = %x\n", thisrand); +`endif + if (thisrand == lastrand) same=same+1; + lastrand = thisrand; + end + if (same > 1) begin + $write("%%Error: Too many similar numbers: %d\n", same); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_readmem.v b/SVIncCompil/Testcases/Verilator/t_sys_readmem.v new file mode 100644 index 0000000..66d1a79 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_readmem.v
@@ -0,0 +1,170 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + + // verilator lint_off LITENDIAN + reg [5:0] binary_string [2:15]; + reg [5:0] binary_nostart [2:15]; + reg [5:0] binary_start [0:15]; + reg [175:0] hex [0:15]; + reg [(32*6)-1:0] hex_align [0:15]; + string fns; + +`ifdef WRITEMEM_READ_BACK + reg [5:0] binary_string_tmp [2:15]; + reg [5:0] binary_nostart_tmp [2:15]; + reg [5:0] binary_start_tmp [0:15]; + reg [175:0] hex_tmp [0:15]; + reg [(32*6)-1:0] hex_align_tmp [0:15]; + string fns_tmp; +`endif + // verilator lint_on LITENDIAN + + integer i; + + initial begin + begin + // Initialize memories to zero, + // avoid differences between 2-state and 4-state. + for (i=0; i<16; i=i+1) begin + binary_start[i] = 6'h0; + hex[i] = 176'h0; + hex_align[i] = {32*6{1'b0}}; +`ifdef WRITEMEM_READ_BACK + binary_start_tmp[i] = 6'h0; + hex_tmp[i] = 176'h0; + hex_align_tmp[i] = {32*6{1'b0}}; +`endif + end + for (i=2; i<16; i=i+1) begin + binary_string[i] = 6'h0; + binary_nostart[i] = 6'h0; +`ifdef WRITEMEM_READ_BACK + binary_string_tmp[i] = 6'h0; + binary_nostart_tmp[i] = 6'h0; +`endif + end + end + + begin +`ifdef WRITEMEM_READ_BACK + $readmemb("t/t_sys_readmem_b.mem", binary_nostart_tmp); + // Do a round-trip $writememh and $readmemh cycle. + // This covers $writememh and ensures we can read our + // own memh output file. + `ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP1); + `endif + $writememh(`OUT_TMP1, binary_nostart_tmp); + $readmemh(`OUT_TMP1, binary_nostart); +`else + $readmemb("t/t_sys_readmem_b.mem", binary_nostart); +`endif +`ifdef TEST_VERBOSE + for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]); +`endif + if (binary_nostart['h2] != 6'h02) $stop; + if (binary_nostart['h3] != 6'h03) $stop; + if (binary_nostart['h4] != 6'h04) $stop; + if (binary_nostart['h5] != 6'h05) $stop; + if (binary_nostart['h6] != 6'h06) $stop; + if (binary_nostart['h7] != 6'h07) $stop; + if (binary_nostart['h8] != 6'h10) $stop; + if (binary_nostart['hc] != 6'h14) $stop; + if (binary_nostart['hd] != 6'h15) $stop; + end + + begin +`ifdef WRITEMEM_READ_BACK + $readmemb("t/t_sys_readmem_b_8.mem", binary_start_tmp, 4, 4+7); + `ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP2); + `endif + $writememh(`OUT_TMP2, binary_start_tmp, 4, 4+7); + $readmemh(`OUT_TMP2, binary_start, 4, 4+7); +`else + $readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7); +`endif +`ifdef TEST_VERBOSE + for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]); +`endif + if (binary_start['h04] != 6'h10) $stop; + if (binary_start['h05] != 6'h11) $stop; + if (binary_start['h06] != 6'h12) $stop; + if (binary_start['h07] != 6'h13) $stop; + if (binary_start['h08] != 6'h14) $stop; + if (binary_start['h09] != 6'h15) $stop; + if (binary_start['h0a] != 6'h16) $stop; + if (binary_start['h0b] != 6'h17) $stop; + end + + begin + // The 'hex' array is a non-exact multiple of word size + // (possible corner case) +`ifdef WRITEMEM_READ_BACK + $readmemh("t/t_sys_readmem_h.mem", hex_tmp, 0); + `ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP3); + `endif + $writememh(`OUT_TMP3, hex_tmp, 0); + $readmemh(`OUT_TMP3, hex, 0); +`else + $readmemh("t/t_sys_readmem_h.mem", hex, 0); +`endif +`ifdef TEST_VERBOSE + for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]); +`endif + if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop; + if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop; + if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop; + if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop; + end + + begin + // The 'hex align' array is similar to 'hex', but it is an + // exact multiple of word size -- another possible corner case. +`ifdef WRITEMEM_READ_BACK + $readmemh("t/t_sys_readmem_align_h.mem", hex_align_tmp, 0); + `ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP4); + `endif + $writememh(`OUT_TMP4, hex_align_tmp, 0); + $readmemh(`OUT_TMP4, hex_align, 0); +`else + $readmemh("t/t_sys_readmem_align_h.mem", hex_align, 0); +`endif +`ifdef TEST_VERBOSE + for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex_align[i]); +`endif + if (hex_align['h04] != 192'h77554004_37654321_27654321_17654321_07654321_abcdef10) $stop; + if (hex_align['h0a] != 192'h7755400a_37654321_27654321_17654321_07654321_abcdef11) $stop; + if (hex_align['h0b] != 192'h7755400b_37654321_27654321_17654321_07654321_abcdef12) $stop; + if (hex_align['h0c] != 192'h7755400c_37654321_27654321_17654321_07654321_abcdef13) $stop; + end + + begin + fns = "t/t_sys_readmem_b.mem"; +`ifdef WRITEMEM_READ_BACK + fns_tmp = `OUT_TMP5; + $readmemb(fns, binary_string_tmp); + `ifdef TEST_VERBOSE + $display("-Writing %s", `OUT_TMP5); + `endif + $writememh(fns_tmp, binary_string_tmp); + $readmemh(fns_tmp, binary_string); +`else + $readmemb(fns, binary_string); +`endif +`ifdef TEST_VERBOSE + for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_string[i]); +`endif + if (binary_string['h2] != 6'h02) $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_addr.v b/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_addr.v new file mode 100644 index 0000000..1d2306e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_addr.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + reg [175:0] hex [15:0]; + + initial begin + $readmemh("t/t_sys_readmem_bad_addr.mem", hex); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_digit.v b/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_digit.v new file mode 100644 index 0000000..ca56812 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_digit.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + + reg [175:0] hex [15:0]; + + initial begin + $readmemb("t/t_sys_readmem_bad_digit.mem", hex); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_end.v b/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_end.v new file mode 100644 index 0000000..26c5269 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_end.v
@@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + + reg [175:0] hex [15:0]; + + integer i; + + initial begin + $readmemh("t/t_sys_readmem_bad_end.mem", hex, 0, 15); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_notfound.v b/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_notfound.v new file mode 100644 index 0000000..d44ba3e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_readmem_bad_notfound.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + + reg [175:0] hex [15:0]; + + initial begin + $readmemh("t/t_sys_readmem_bad_NOTFOUND.mem", hex); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_sformat.v b/SVIncCompil/Testcases/Verilator/t_sys_sformat.v new file mode 100644 index 0000000..6d09904 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_sformat.v
@@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`include "verilated.v" + +module t; + + // Note $sscanf already tested elsewhere + + reg [3:0] n; + reg [63:0] q; + reg [16*8:1] wide; + + reg [8:1] ochar; + reg [48*8:1] str; + reg [48*8:1] str2; + string str3; + + + real r; + + initial begin + n = 4'b1100; + q = 64'h1234_5678_abcd_0123; + wide = "hello-there12345"; + $sformat(str, "n=%b q=%d w=%s", n, q, wide); +`ifdef TEST_VERBOSE $display("str=%0s",str); `endif + if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; + + q = {q[62:0],1'b1}; + $swrite(str2, "n=%b q=%d w=%s", n, q, wide); +`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif + if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; + + str3 = $sformatf("n=%b q=%d w=%s", n, q, wide); +`ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif + if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; + + $swrite(str2, "e=%e", r); + $swrite(str2, "e=%f", r); + $swrite(str2, "e=%g", r); + + r = 0.01; + $swrite(str2, "e=%e f=%f g=%g", r, r, r); +`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif + if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop; + + $swrite(str2, "mod=%m"); +`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif + if (str2 !== "mod=top.t") $stop; + + $swrite(str2, "lib=%l"); +`ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif + if (str2 !== "lib=t") $stop; + + str3 = $sformatf("u=%u", {"a","b","c","d"}); // Value selected so is printable +`ifdef TEST_VERBOSE $display("chku %s %s",str3,str3); `endif + if (str3 !== "u=dcba") $stop; + + str3 = $sformatf("v=%v", {"a","b","c","d"}); // Value selected so is printable +`ifdef TEST_VERBOSE $display("chkv %s %s",str3,str3); `endif + + $sformat(ochar,"%s","c"); + if (ochar != "c") $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_system.v b/SVIncCompil/Testcases/Verilator/t_sys_system.v new file mode 100644 index 0000000..612797f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_system.v
@@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t; + + integer i; + + initial begin +`ifndef VERILATOR + `ifndef VCS + `ifndef NC + $system(); // Legal per spec, but not supported everywhere and nonsensical + `endif + `endif +`endif + $system("exit 0"); + $system("echo hello"); +`ifndef VCS + i = $system("exit 0"); + if (i!==0) $stop; + i = $system("exit 10"); + if (i!==10) $stop; + i = $system("exit 20"); // Wide + if (i!==20) $stop; +`endif + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_sys_time.v b/SVIncCompil/Testcases/Verilator/t_sys_time.v new file mode 100644 index 0000000..19f2800 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_sys_time.v
@@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + reg [63:0] time64; + + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + end + else if (cyc<10) begin + end + else if (cyc<90) begin + time64 = $time; + if ($stime != time64[31:0]) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_table_fsm.v b/SVIncCompil/Testcases/Verilator/t_table_fsm.v new file mode 100644 index 0000000..1ac617f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_table_fsm.v
@@ -0,0 +1,159 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + reg reset; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire myevent; // From test of Test.v + wire myevent_pending; // From test of Test.v + wire [1:0] state; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .state (state[1:0]), + .myevent (myevent), + .myevent_pending (myevent_pending), + // Inputs + .clk (clk), + .reset (reset)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, myevent_pending,myevent,state}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n",$time, cyc, crc, result, myevent, myevent_pending); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + reset <= (cyc<2); + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4e93a74bd97b25ef + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + state, myevent, myevent_pending, + // Inputs + clk, reset + ); + input clk; + input reset; + output [1:0] state; + output myevent; + output myevent_pending; + + reg [5:0] count = 0; + always @ (posedge clk) + if (reset) count <= 0; + else count <= count + 1; + + reg myevent = 1'b0; + always @ (posedge clk) + myevent <= (count == 6'd27); + + reg myevent_done; + reg hickup_ready; + reg hickup_done; + + localparam STATE_ZERO = 0; + localparam STATE_ONE = 1; + localparam STATE_TWO = 2; + + reg [1:0] state = STATE_ZERO; + reg state_start_myevent = 1'b0; + reg state_start_hickup = 1'b0; + reg myevent_pending = 1'b0; + always @ (posedge clk) begin + state <= state; + myevent_pending <= myevent_pending || myevent; + state_start_myevent <= 1'b0; + state_start_hickup <= 1'b0; + case (state) + STATE_ZERO: + if (myevent_pending) begin + state <= STATE_ONE; + myevent_pending <= 1'b0; + state_start_myevent <= 1'b1; + end else if (hickup_ready) begin + state <= STATE_TWO; + state_start_hickup <= 1'b1; + end + + STATE_ONE: + if (myevent_done) + state <= STATE_ZERO; + + STATE_TWO: + if (hickup_done) + state <= STATE_ZERO; + + default: + ; /* do nothing */ + endcase + end + + reg [3:0] myevent_count = 0; + always @ (posedge clk) + if (state_start_myevent) + myevent_count <= 9; + else if (myevent_count > 0) + myevent_count <= myevent_count - 1; + + initial myevent_done = 1'b0; + always @ (posedge clk) + myevent_done <= (myevent_count == 0); + + reg [4:0] hickup_backlog = 2; + always @ (posedge clk) + if (state_start_myevent) + hickup_backlog <= hickup_backlog - 1; + else if (state_start_hickup) + hickup_backlog <= hickup_backlog + 1; + + initial hickup_ready = 1'b1; + always @ (posedge clk) + hickup_ready <= (hickup_backlog < 3); + + reg [3:0] hickup_count = 0; + always @ (posedge clk) + if (state_start_hickup) + hickup_count <= 10; + else if (hickup_count > 0) + hickup_count <= hickup_count - 1; + + initial hickup_done = 1'b0; + always @ (posedge clk) + hickup_done <= (hickup_count == 1); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_threads_counter.v b/SVIncCompil/Testcases/Verilator/t_threads_counter.v new file mode 100644 index 0000000..dabcf0a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_threads_counter.v
@@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc!=0) begin + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_array.v b/SVIncCompil/Testcases/Verilator/t_trace_array.v new file mode 100644 index 0000000..6cf6ce8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_array.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (clk); + input clk; + integer cyc=0; + + // Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk + + typedef struct packed { + logic [1024*1024:0] d; + } s1_t; // 128 b + + s1_t biggie; + + always @ (posedge clk) begin + cyc <= cyc + 1; + biggie [ cyc +: 32 ] <= 32'hfeedface; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_cat.v b/SVIncCompil/Testcases/Verilator/t_trace_cat.v new file mode 100644 index 0000000..f9c6d1f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_cat.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t + ( + input wire clk + ); + + integer cyc; initial cyc = 0; + + always @ (posedge clk) begin + cyc <= cyc + 1; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_complex.v b/SVIncCompil/Testcases/Verilator/t_trace_complex.v new file mode 100644 index 0000000..eb75887 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_complex.v
@@ -0,0 +1,103 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +bit global_bit; + +module t (clk); + input clk; + integer cyc=0; + + typedef struct packed { + bit b1; + bit b0; + } strp_t; + + typedef struct packed { + strp_t x1; + strp_t x0; + } strp_strp_t; + + typedef union packed { + strp_t x1; + strp_t x0; + } unip_strp_t; + + typedef bit [2:1] arrp_t; + typedef arrp_t [4:3] arrp_arrp_t; + + typedef strp_t [4:3] arrp_strp_t; + + typedef bit arru_t [2:1]; + typedef arru_t arru_arru_t [4:3]; + typedef arrp_t arru_arrp_t [4:3]; + typedef strp_t arru_strp_t [4:3]; + + strp_t v_strp; + strp_strp_t v_strp_strp; + unip_strp_t v_unip_strp; + arrp_t v_arrp; + arrp_arrp_t v_arrp_arrp; + arrp_strp_t v_arrp_strp; + arru_t v_arru; + arru_arru_t v_arru_arru; + arru_arrp_t v_arru_arrp; + arru_strp_t v_arru_strp; + + real v_real; + real v_arr_real [2]; + string v_string; + + typedef struct packed { + logic [31:0] data; + } str32_t; + str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0 + initial v_str32x2[0] = 32'hff; + initial v_str32x2[1] = 0; + + typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t; + enumed_t v_enumed; + enumed_t v_enumed2; + typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t; + enumb_t v_enumb; + + p #(.PARAM(2)) p2 (); + p #(.PARAM(3)) p3 (); + + always @ (posedge clk) begin + cyc <= cyc + 1; + v_strp <= ~v_strp; + v_strp_strp <= ~v_strp_strp; + v_unip_strp <= ~v_unip_strp; + v_arrp_strp <= ~v_arrp_strp; + v_arrp <= ~v_arrp; + v_arrp_arrp <= ~v_arrp_arrp; + v_real <= v_real + 0.1; + v_string <= cyc[0] ? "foo" : "bar"; + v_arr_real[0] <= v_arr_real[0] + 0.2; + v_arr_real[1] <= v_arr_real[1] + 0.3; + v_enumed <= v_enumed + 1; + v_enumed2 <= v_enumed2 + 2; + v_enumb <= v_enumb - 1; + for (integer b=3; b<=4; b++) begin + v_arru[b] <= ~v_arru[b]; + v_arru_strp[b] <= ~v_arru_strp[b]; + v_arru_arrp[b] <= ~v_arru_arrp[b]; + for (integer a=3; a<=4; a++) begin + v_arru_arru[a][b] = ~v_arru_arru[a][b]; + end + end + v_str32x2[0] <= v_str32x2[0] - 1; + v_str32x2[1] <= v_str32x2[1] + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module p; + parameter PARAM = 1; + initial global_bit = 1; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_decoration.v b/SVIncCompil/Testcases/Verilator/t_trace_decoration.v new file mode 100644 index 0000000..80f511d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_decoration.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (clk); + input clk; + integer a_very_long_name_which_we_will_hash_eventually=0; + + always @ (posedge clk) begin + a_very_long_name_which_we_will_hash_eventually <= a_very_long_name_which_we_will_hash_eventually + 1; + if (a_very_long_name_which_we_will_hash_eventually == 5) begin + fin(); + end + end + + task fin; + $write("*-* All Finished *-*\n"); + $finish; + endtask + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_ena.v b/SVIncCompil/Testcases/Verilator/t_trace_ena.v new file mode 100644 index 0000000..b47e3d6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_ena.v
@@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=1; + // verilator tracing_off + integer b_trace_off; + // verilator tracing_on + integer c_trace_on; + real r; + + // verilator tracing_off + sub sub (); + // verilator tracing_on + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + b_trace_off <= cyc; + c_trace_on <= b_trace_off; + r <= r + 0.1; + if (cyc==4) begin + if (c_trace_on != 2) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module sub; + integer inside_sub = 0; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_fst.v b/SVIncCompil/Testcases/Verilator/t_trace_fst.v new file mode 100644 index 0000000..6d3ff0b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_fst.v
@@ -0,0 +1,96 @@ +// This file ONLY is placed into the Public Domain, for any use, +// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw + +module t (/*AUTOARG*/ + // Outputs + state, + // Inputs + clk + ); + + input clk; + + int cyc; + reg rstn; + output [4:0] state; + + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; + + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; + + Test test (/*AUTOINST*/ + // Outputs + .state (state[4:0]), + // Inputs + .clk (clk), + .rstn (rstn)); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + rstn <= ~'1; + end + else if (cyc<10) begin + rstn <= ~'1; + end + else if (cyc<90) begin + rstn <= ~'0; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test ( + input clk, + input rstn, + output logic [4:0] state + ); + + logic [4:0] state_w; + logic [4:0] state_array [3]; + assign state = state_array[0]; + + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end + + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) + state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) + state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_packed_struct.v b/SVIncCompil/Testcases/Verilator/t_trace_packed_struct.v new file mode 100644 index 0000000..1c800d0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_packed_struct.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Andrew Bardsley. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + int cnt; + + // This won't compile with tracing as an incorrect declaration is made for + // the temp variables used to represent the elements of localparam v + typedef struct packed { + logic [2:0][31:0] a; + } t; + + localparam t v[2:0] = '{ + '{'{32'h10000002, 32'h10000001, 32'h10000000}}, + '{'{32'h20000002, 32'h20000001, 32'h20000000}}, + '{'{32'h30000002, 32'h30000001, 32'h30000000}} + }; + + initial cnt = 0; + always@(posedge clk) begin + if (cnt < 3) begin + cnt = cnt + 1; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_param.v b/SVIncCompil/Testcases/Verilator/t_trace_param.v new file mode 100644 index 0000000..8f81eec --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_param.v
@@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jonathon Donaldson. + +package my_funcs; + function automatic int simple_func (input int value); + begin + simple_func = value; + end + endfunction +endpackage + +package my_module_types; + import my_funcs::*; + + localparam MY_PARAM = 3; + localparam MY_PARAM2 /*verilator public*/ = simple_func(12); +endpackage + +module t + import my_module_types::*; + ( + input i_clk, + input [MY_PARAM-1:0] i_d, + output logic [MY_PARAM-1:0] o_q + ); + + always_ff @(posedge i_clk) + o_q <= i_d; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_primitive.v b/SVIncCompil/Testcases/Verilator/t_trace_primitive.v new file mode 100644 index 0000000..00fb855 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_primitive.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jie Xu. + +module t + ( + clk + ); + + input clk; + integer cyc; initial cyc = 0; + + reg a; + reg b; + reg z; + sub_t sub_t_i (z, a, b); + + always @ (posedge clk) begin + cyc <= cyc + 1; + a <= cyc[0]; + b <= cyc[1]; + + if (cyc > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +primitive CINV (a, b); +output b; +input a; +assign b = ~a; +endprimitive + + +module sub_t (z, x, y); +input x, y; +output z; + +assign z = x & y; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_public.v b/SVIncCompil/Testcases/Verilator/t_trace_public.v new file mode 100644 index 0000000..1f848a8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_public.v
@@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t ( + input wire CLK, + output reg RESET + ); + + neg neg (.clk(CLK)); + little little (.clk(CLK)); + glbl glbl (); + + // A vector + logic [2:1] vec [4:3]; + + integer val = 0; + always @ (posedge CLK) begin + if (RESET) val <= 0; + else val <= val + 1; + vec[3] <= val[1:0]; + vec[4] <= val[3:2]; + end + + initial RESET = 1'b1; + always @ (posedge CLK) + RESET <= glbl.GSR; + +endmodule + +module glbl(); +`ifdef PUB_FUNC + reg GSR; + task setGSR; + /* verilator public */ + input value; + GSR = value; + endtask +`else + reg GSR /*verilator public*/; +`endif +endmodule + +module neg ( + input clk + ); + + reg [0:-7] i8; initial i8 = '0; + reg [-1:-48] i48; initial i48 = '0; + reg [63:-64] i128; initial i128 = '0; + + always @ (posedge clk) begin + i8 <= ~i8; + i48 <= ~i48; + i128 <= ~i128; + end +endmodule + +module little ( + input clk + ); + + // verilator lint_off LITENDIAN + reg [0:7] i8; initial i8 = '0; + reg [1:49] i48; initial i48 = '0; + reg [63:190] i128; initial i128 = '0; + // verilator lint_on LITENDIAN + + always @ (posedge clk) begin + i8 <= ~i8; + i48 <= ~i48; + i128 <= ~i128; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_scstruct.v b/SVIncCompil/Testcases/Verilator/t_trace_scstruct.v new file mode 100644 index 0000000..0993f0f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_scstruct.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +// verilator lint_off UNUSED +// verilator lint_off UNDRIVEN + +//bug858 + +typedef struct packed { + logic m_1; + logic m_2; +} struct_t; + +typedef struct packed { + logic [94:0] m_1; + logic m_2; +} struct96_t; + +module t + ( + input struct_t test_input, + input struct96_t t96 + ); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_string.v b/SVIncCompil/Testcases/Verilator/t_trace_string.v new file mode 100644 index 0000000..9f3fb8d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_string.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"}; + + initial begin + $display("%s", SVEC[3'd1]); + $write("*-* All Finished *-*\n"); + $finish; + end + + localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"}; + + function string regx (logic [5-1:0] r, bit abi=1'b0); + regx = abi ? REGX[r] : $sformatf("x%0d", r); + endfunction: regx + + function string dis32 (logic [32-1:0] op); + casez (op) + 32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop"); + 32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-"); + 32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr %s, 0x%03x (%s)", + regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0])); + default: dis32 = "illegal"; + endcase + endfunction: dis32 + + always @(posedge clk) begin + for (int unsigned i=0; i<32; i++) + $display("REGX: %s", regx(i[4:0])); + $display("OP: %s", dis32(32'h00000000)); + $finish(); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_trace_timescale.v b/SVIncCompil/Testcases/Verilator/t_trace_timescale.v new file mode 100644 index 0000000..f9c6d1f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_trace_timescale.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t + ( + input wire clk + ); + + integer cyc; initial cyc = 0; + + always @ (posedge clk) begin + cyc <= cyc + 1; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_array.v b/SVIncCompil/Testcases/Verilator/t_tri_array.v new file mode 100644 index 0000000..a110a37 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_array.v
@@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + parameter NPAD = 4; + + tri pad [NPAD-1:0]; // Array + wire [NPAD-1:0] data0 = crc[0 +: 4]; + wire [NPAD-1:0] data1 = crc[8 +: 4]; + wire [NPAD-1:0] en = crc[16 +: 4]; + + for (genvar g=0; g<NPAD; ++g) begin : gpad + Pad pad1 (.pad(pad[g]), + .ena(en[g]), + .data(data1[g])); + Pad pad0 (.pad(pad[g]), + .ena(!en[g]), + .data(data0[g])); + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {60'h0, pad[3], pad[2], pad[1], pad[0]} + ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'he09fe6f2dfd7a302 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Pad + (inout pad, + input ena, + input data); + assign pad = ena ? data : 1'bz; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_array_bufif.v b/SVIncCompil/Testcases/Verilator/t_tri_array_bufif.v new file mode 100644 index 0000000..e767fac --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_array_bufif.v
@@ -0,0 +1,116 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + parameter DW = 4; + wire [3:0] drv_a = crc[3:0]; + wire [3:0] drv_b = crc[7:4]; + wire [3:0] drv_e = crc[19:16]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [DW-1:0] drv; // To/From test1 of Test1.v + wire [DW-1:0] drv2; // From test2 of Test2.v + // End of automatics + + Test1 test1 (/*AUTOINST*/ + // Inouts + .drv (drv[DW-1:0]), + // Inputs + .drv_a (drv_a[DW-1:0]), + .drv_b (drv_b[DW-1:0]), + .drv_e (drv_e[DW-1:0])); + Test2 test2 (/*AUTOINST*/ + // Outputs + .drv2 (drv2[DW-1:0]), + // Inputs + .drv_a (drv_a[DW-1:0]), + .drv_b (drv_b[DW-1:0]), + .drv_e (drv_e[DW-1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, drv}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + if (drv2 != drv) $stop; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hd95d216c5a2945d0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test1 #( + parameter DW = 4 +)( + input wire [DW-1:0] drv_a, + input wire [DW-1:0] drv_b, + input wire [DW-1:0] drv_e, + inout wire [DW-1:0] drv +); + + wire drv_0, drv_1, drv_2, drv_3; + bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]); + bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]); + bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]); + bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]); + bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]); + bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]); + bufif1 bufa3 (drv_3, drv_a[3], drv_e[3]); + bufif1 bufb3 (drv_3, drv_b[3], ~drv_e[3]); + assign drv = {drv_3,drv_2,drv_1,drv_0}; + +endmodule + +module Test2 #( + parameter DW = 4 +)( + input wire [DW-1:0] drv_a, + input wire [DW-1:0] drv_b, + input wire [DW-1:0] drv_e, + inout wire [DW-1:0] drv2 +); + + wire [DW-1:0] drv_all; + bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e); + // Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e); + bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]}, + {drv_b[3], drv_b[2], drv_b[1], drv_b[0]}, + {~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]}); + assign drv2 = drv_all; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_array_pull.v b/SVIncCompil/Testcases/Verilator/t_tri_array_pull.v new file mode 100644 index 0000000..e1ce8e2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_array_pull.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Rod Steward. + +module IOBUF ( input T, input I, output O, inout IO ); + assign O = IO; + assign IO = T ? 1'bz : I; +endmodule + +module t + ( + input [7:0] inlines, + output [7:0] outlines, + inout [7:0] iolines, + + input inctrl + ); + + generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D + IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) ); + pullup d_pup (iolines[i]); + end + endgenerate + + IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) ); + pullup d_0_pup (iolines[0]); + + IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) ); + pullup d_1_pup (iolines[1]); + + IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) ); + pullup d_2_pup (iolines[2]); + + IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) ); + pullup d_3_pup (iolines[3]); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_dangle.v b/SVIncCompil/Testcases/Verilator/t_tri_dangle.v new file mode 100644 index 0000000..030aa65 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_dangle.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inouts + AVDD, AVSS + ); + inout AVDD; + inout AVSS; + + sub sub (/*AUTOINST*/ + // Inouts + .AVDD (AVDD), + .AVSS (AVSS)); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub (/*AUTOARG*/ + // Inouts + AVDD, AVSS + ); + // verilator no_inline_module + inout AVDD; + inout AVSS; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_eqcase.v b/SVIncCompil/Testcases/Verilator/t_tri_eqcase.v new file mode 100644 index 0000000..ca86c34 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_eqcase.v
@@ -0,0 +1,128 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [3:0] drv_a = crc[3:0]; + wire [3:0] drv_b = crc[7:4]; + wire [3:0] drv_e = crc[19:16]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [8:0] match1; // From test1 of Test1.v + wire [8:0] match2; // From test2 of Test2.v + // End of automatics + + Test1 test1 (/*AUTOINST*/ + // Outputs + .match1 (match1[8:0]), + // Inputs + .drv_a (drv_a[3:0]), + .drv_e (drv_e[3:0])); + Test2 test2 (/*AUTOINST*/ + // Outputs + .match2 (match2[8:0]), + // Inputs + .drv_a (drv_a[3:0]), + .drv_e (drv_e[3:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {39'h0, match2, 7'h0, match1}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n",$time, cyc, crc, match1, match2, drv_e,drv_a,drv_b); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test1 + ( + input wire [3:0] drv_a, + input wire [3:0] drv_e, + output wire [8:0] match1 + ); + + wire [2:1] drv_all; + bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]); + +`ifdef VERILATOR + // At present Verilator only allows comparisons with Zs + assign match1[0] = (drv_a[2:1]== 2'b00 && drv_e[2:1]==2'b11); + assign match1[1] = (drv_a[2:1]== 2'b01 && drv_e[2:1]==2'b11); + assign match1[2] = (drv_a[2:1]== 2'b10 && drv_e[2:1]==2'b11); + assign match1[3] = (drv_a[2:1]== 2'b11 && drv_e[2:1]==2'b11); +`else + assign match1[0] = drv_all === 2'b00; + assign match1[1] = drv_all === 2'b01; + assign match1[2] = drv_all === 2'b10; + assign match1[3] = drv_all === 2'b11; +`endif + assign match1[4] = drv_all === 2'bz0; + assign match1[5] = drv_all === 2'bz1; + assign match1[6] = drv_all === 2'bzz; + assign match1[7] = drv_all === 2'b0z; + assign match1[8] = drv_all === 2'b1z; +endmodule + +module Test2 + ( + input wire [3:0] drv_a, + input wire [3:0] drv_e, + output wire [8:0] match2 + ); + + wire [2:1] drv_all; + bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]); + +`ifdef VERILATOR + assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1]!=2'b11); + assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1]!=2'b11); + assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1]!=2'b11); + assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1]!=2'b11); +`else + assign match2[0] = drv_all !== 2'b00; + assign match2[1] = drv_all !== 2'b01; + assign match2[2] = drv_all !== 2'b10; + assign match2[3] = drv_all !== 2'b11; +`endif + assign match2[4] = drv_all !== 2'bz0; + assign match2[5] = drv_all !== 2'bz1; + assign match2[6] = drv_all !== 2'bzz; + assign match2[7] = drv_all !== 2'b0z; + assign match2[8] = drv_all !== 2'b1z; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_gate.v b/SVIncCompil/Testcases/Verilator/t_tri_gate.v new file mode 100644 index 0000000..7209f35 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_gate.v
@@ -0,0 +1,44 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks + +module top (input SEL, input[1:0] A, output W, output X, output Y, output Z); + mux mux2 (.A(A), .SEL(SEL), .Z(W)); + + pass mux1 (.A(A), .SEL(SEL), .Z(X)); + + tbuf mux0[1:0] (.A(A), .OE({SEL,!SEL}), .Z(Y)); + + assign Z = ( SEL) ? A[1] : 1'bz; + tbuf tbuf (.A(A[0]), .OE(!SEL), .Z(Z)); +endmodule + +module pass (input[1:0] A, input SEL, output Z); + tbuf tbuf1 (.A(A[1]), .OE(SEL), .Z(Z)); + tbuf tbuf0 (.A(A[0]), .OE(!SEL),.Z(Z)); +endmodule + +module tbuf (input A, input OE, output Z); +`ifdef T_BUFIF0 + bufif0 (Z, A, !OE); +`elsif T_BUFIF1 + bufif1 (Z, A, OE); +`elsif T_NOTIF0 + notif0 (Z, !A, !OE); +`elsif T_NOTIF1 + notif1 (Z, !A, OE); +`elsif T_PMOS + pmos (Z, A, !OE); +`elsif T_NMOS + nmos (Z, A, OE); +`elsif T_COND + assign Z = (OE) ? A : 1'bz; +`else + `error "Unknown test name" +`endif +endmodule + +module mux (input[1:0] A, input SEL, output Z); + assign Z = (SEL) ? A[1] : 1'bz; + assign Z = (!SEL)? A[0] : 1'bz; + assign Z = 1'bz; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_gen.v b/SVIncCompil/Testcases/Verilator/t_tri_gen.v new file mode 100644 index 0000000..9fa7a3d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_gen.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + tri z0; + tri z1; + + updown #(0) updown0 (.z(z0)); + updown #(1) updown1 (.z(z1)); + + always @ (posedge clk) begin + if (z0 !== 0) $stop; + if (z1 !== 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module updown #(parameter UP=0) + (inout z); + generate + if (UP) begin + t_up sub (.z); + end + else begin + t_down sub (.z); + end + endgenerate +endmodule + +module t_up (inout tri1 z); +endmodule + +module t_down (inout tri0 z); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_graph.v b/SVIncCompil/Testcases/Verilator/t_tri_graph.v new file mode 100644 index 0000000..fde1953 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_graph.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Unsupported tristate constructur error +// +// This is a compile only regression test of tristate handling for bug514 +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [11:0] ck; + + assign ck[1:0] = {1'bz,{1{1'b0}}}; + + test i_test (.clk (ck[1:0])); + +endmodule + + +module test (clk); + + output wire [1:0] clk; + +endmodule // test
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_ifbegin.v b/SVIncCompil/Testcases/Verilator/t_tri_ifbegin.v new file mode 100644 index 0000000..3be9c2a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_ifbegin.v
@@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + tri pad_io_h; + tri pad_io_l; + + sub sub (.*); + +endmodule + + +module sub (/*AUTOARG*/ + // Inouts + pad_io_h, pad_io_l + ); + + parameter USE = 1'b1; + parameter DIFFERENTIAL = 1'b1; + parameter BIDIR = 1'b1; + + inout pad_io_h; + inout pad_io_l; + + wire [31:0] dqs_out_dtap_delay; + + generate + if (USE) begin: output_strobe + wire aligned_os_oe; + wire aligned_strobe; + + if (BIDIR) begin + reg sig_h_r = 1'b0; + reg sig_l_r = 1'b0; + always @* begin + sig_h_r = ~aligned_os_oe ? aligned_strobe : 1'bz; + if (DIFFERENTIAL) + sig_l_r = ~aligned_os_oe ? ~aligned_strobe : 1'bz; + end + assign pad_io_h = sig_h_r; + if (DIFFERENTIAL) + assign pad_io_l = sig_l_r; + end + end + endgenerate + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_inout.v b/SVIncCompil/Testcases/Verilator/t_tri_inout.v new file mode 100644 index 0000000..7322cf4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_inout.v
@@ -0,0 +1,19 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks + +module top (input A, input B, input SEL, output Y1, output Y2, output Z); + io io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1)); + pass io2(.A(B), .OE(!SEL), .Z(Z), .Y(Y2)); + assign Z = 1'bz; +endmodule + +module pass (input A, input OE, inout Z, output Y); + io io(.A(A), .OE(OE), .Z(Z), .Y(Y)); + assign Z = 1'bz; +endmodule + +module io (input A, input OE, inout Z, output Y); + assign Z = (OE) ? A : 1'bz; + assign Y = Z; + assign Z = 1'bz; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_inout2.v b/SVIncCompil/Testcases/Verilator/t_tri_inout2.v new file mode 100644 index 0000000..a7b6698 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_inout2.v
@@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [2:0] in; + + + wire a,y,y_fixed; + wire b = in[0]; + wire en = in[1]; + + + pullup(a); + + ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) ); + + initial in=0; + + // Test loop + always @ (posedge clk) begin + + + in <= in + 1; + + $display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed); + if (en) begin + // driving b + // a should be b + // y and yfix should also be b + if (a!=b || y != b || y_fixed != b) begin + $display ( "Expected a %d y %b yfix %b" , a, y, y_fixed); + $stop; + end + + end else begin + // not driving b + // a should be 1 (pullup) + // y and yfix shold be 1 + if (a!=1 || y != 1 || y_fixed != 1) begin + $display( "Expected a,y,yfix == 1"); + $stop; + end + end + + if (in==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module ChildA(inout A, input B, input en, output Y, output Yfix); + + // workaround + wire a_in = A; + + ChildB childB(.A(A), .Y(Y)); + assign A = en ? B : 1'bz; + + + ChildB childBfix(.A(a_in),.Y(Yfix)); + + +endmodule + +module ChildB(input A, output Y); + assign Y = A; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_inz.v b/SVIncCompil/Testcases/Verilator/t_tri_inz.v new file mode 100644 index 0000000..6baa8e6 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_inz.v
@@ -0,0 +1,15 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder + +module top + (input d, + output ext0, + output ext1, + output extx, + output extz); + + assign ext0 = (d === 1'b0); + assign ext1 = (d === 1'b1); + assign extx = (d === 1'bx); + assign extz = (d === 1'bz); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_public.v b/SVIncCompil/Testcases/Verilator/t_tri_public.v new file mode 100644 index 0000000..f18f980 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_public.v
@@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Unsupported tristate constructur error +// +// This is a compile only regression test of tristate handling for bug514 +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Rob Stoddard. + +module t (/*AUTOARG*/ + // Outputs + out, + // Inputs + data, up_down, clk, reset + ); + + //----------Output Ports-------------- + output [7:0] out; + //------------Input Ports-------------- + //input [7:0] data ; + input [7:0] data; + input up_down, clk, reset; + //------------Internal Variables-------- + reg [7:0] out; + logic [7:0] q_out; + + //-------------Code Starts Here------- + always @(posedge clk) + if (reset) begin // active high reset + out <= 8'b0 ; + end else if (up_down) begin + out <= out + 1; + end else begin + out <= q_out; + end + + // verilator lint_off PINMISSING + sub_mod sub_mod + ( + .clk(clk), + .data(data), + .reset(reset), + .q(q_out) + ); + // verilator lint_on PINMISSING + +endmodule + +module sub_mod (/*AUTOARG*/ + // Outputs + q, test_out, + // Inouts + test_inout, + // Inputs + data, clk, reset + ); + + //-----------Input Ports--------------- + + input [7:0] data /*verilator public*/; + input clk, reset; + inout test_inout; // Get rid of this, the problem goes away. + + //-----------Output Ports--------------- + output [7:0] q; + output test_out; // Not assigned, no problem. + + logic [7:0] que; + + // Uncomment this line, the error goes away. + //assign test_inout = que; + + assign q = que; + always @ ( posedge clk) + if (~reset) begin + que <= 8'b0; + end else begin + que <= data; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_pull01.v b/SVIncCompil/Testcases/Verilator/t_tri_pull01.v new file mode 100644 index 0000000..e38765f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_pull01.v
@@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Test: + tri t; + bufif1 (t, crc[1], cyc[1:0]==2'b00); + bufif1 (t, crc[2], cyc[1:0]==2'b10); + + tri0 t0; + bufif1 (t0, crc[1], cyc[1:0]==2'b00); + bufif1 (t0, crc[2], cyc[1:0]==2'b10); + + tri1 t1; + bufif1 (t1, crc[1], cyc[1:0]==2'b00); + bufif1 (t1, crc[2], cyc[1:0]==2'b10); + + tri t2; + t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00)); + bufif1 (t2, crc[2], cyc[1:0]==2'b10); + + tri t3; + t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00)); + bufif1 (t3, crc[2], cyc[1:0]==2'b10); + + wire [63:0] result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h04f91df71371e950 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module t_tri2 (/*AUTOARG*/ + // Outputs + t2, + // Inputs + d, oe + ); + output t2; + input d; + input oe; + tri1 t2; + bufif1 (t2, d, oe); +endmodule + +module t_tri3 (/*AUTOARG*/ + // Outputs + t3, + // Inputs + d, oe + ); + output tri1 t3; + input d; + input oe; + bufif1 (t3, d, oe); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_pull2_bad.v b/SVIncCompil/Testcases/Verilator/t_tri_pull2_bad.v new file mode 100644 index 0000000..26080ae --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_pull2_bad.v
@@ -0,0 +1,21 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Lane Brooks. + +module t (clk); + input clk; + + wire A; + + pullup p1(A); + + child child(/*AUTOINST*/ + // Inouts + .A (A)); + +endmodule + +module child(inout A); + + pulldown p2(A); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_pull_bad.v b/SVIncCompil/Testcases/Verilator/t_tri_pull_bad.v new file mode 100644 index 0000000..8241a7a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_pull_bad.v
@@ -0,0 +1,12 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Lane Brooks. + +module t (clk); + input clk; + + wire A; + + pullup p1(A); + pulldown p2(A); + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_pullup.v b/SVIncCompil/Testcases/Verilator/t_tri_pullup.v new file mode 100644 index 0000000..68617da --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_pullup.v
@@ -0,0 +1,26 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks + +module top (input A, input OE, output X, output Y, output Z); + + pullup p1(Z); + assign Z = OE ? A : 1'bz; + + pulldown p2(Y); + assign Y = OE ? A : 1'bz; + + pass pass(.A(A), .OE(OE), .X(X)); + pullup_module p(X); +endmodule + +module pass (input A, input OE, inout X); + io io(.A(A), .OE(OE), .X(X)); +endmodule + +module io (input A, input OE, inout X); + assign X = (OE) ? A : 1'bz; +endmodule + +module pullup_module (output X); + pullup p1(X); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_pullvec_bad.v b/SVIncCompil/Testcases/Verilator/t_tri_pullvec_bad.v new file mode 100644 index 0000000..c0724c4 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_pullvec_bad.v
@@ -0,0 +1,19 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder + +module t (clk); + input clk; + + tri [3:0] w; + + pullup p0 (w[0]); + pulldown p1 (w[1]); + pulldown p2 (w[2]); + pullup p3 (w[3]); + + always_ff @ (posedge clk) begin + if (w != 4'b1001) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_select.v b/SVIncCompil/Testcases/Verilator/t_tri_select.v new file mode 100644 index 0000000..48714cf --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_select.v
@@ -0,0 +1,41 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks + +`define WIDTH 2 + +module top ( + input OE1, + input OE2, + input [`WIDTH-1:0] A1, + input [`WIDTH-1:0] A2, + output [`WIDTH-1:0] Y1, + output [`WIDTH-1:0] Y2, + output [`WIDTH-1:0] Y3, + output [`WIDTH**2-1:0] W); + + assign W[A1] = (OE2) ? A2[0] : 1'bz; + assign W[A2] = (OE1) ? A2[1] : 1'bz; + + // have 2 different 'chips' drive the PAD to act like a bi-directional bus + wire [`WIDTH-1:0] PAD; + io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD)); + io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD)); + + assign Y3 = PAD; + + pullup p1(PAD); +// pulldown p1(PAD); + + + wire [5:0] fill = { 4'b0, A1 }; + +endmodule + +module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD); + io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD)); +endmodule + +module io (input OE, input I, output O, inout PAD); + assign O = PAD; + assign PAD = OE ? I : 1'bz; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_select_unsized.v b/SVIncCompil/Testcases/Verilator/t_tri_select_unsized.v new file mode 100644 index 0000000..f626d28 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_select_unsized.v
@@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Test of selection with unsized Z. +// +// Test selecting Z when size is not explicit. Issue 510. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [1:0] b; + wire [1:0] c; + wire [0:0] d; // Explicit width due to issue 508 + wire [0:0] e; + + // This works if we use 1'bz, or 1'bx, but not with just 'bz or 'bx. It + // does require the tri-state Z. Since we get the same effect if b is + // dimensioned [0:0], this may be connected to issue 508. + assign b[1:0] = clk ? 2'bx : 'bz; + assign c[1:0] = clk ? 2'bz : 'bx; + assign d = clk ? 1'bx : 'bz; + assign e = clk ? 1'bz : 'bx; + +endmodule // t
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_unconn.v b/SVIncCompil/Testcases/Verilator/t_tri_unconn.v new file mode 100644 index 0000000..d90db96 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_unconn.v
@@ -0,0 +1,124 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + wire one = '1; + wire z0 = 'z; + wire z1 = 'z; + wire z2 = 'z; + wire z3 = 'z; + wire tog = cyc[0]; + + // verilator lint_off PINMISSING + t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing + t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn()); + t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0)); + t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); + t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); + t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect + t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one)); + t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one)); + t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); + t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); + + t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing + t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn()); + t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1)); + t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); + t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect + t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); + t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one)); + t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one)); + t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); + t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); + + t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing + t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn()); + t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2)); + t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); + t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); + t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); + t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one)); + t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one)); + t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); + t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); + + t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing + t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn()); + t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3)); + t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); + t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); + t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); + t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one)); + t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one)); + t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); + t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); + // verilator lint_on PINMISSING + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module t_tri0 + (line, expval, tn); + input integer line; + input expval; + input tn; // Illegal to be inout; spec requires net connection to any inout + tri0 tn; + wire clk = t.clk; + always @(posedge clk) if (tn !== expval) begin + $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; + end +endmodule + +module t_tri1 + (line, expval, tn); + input integer line; + input expval; + input tn; + tri1 tn; + wire clk = t.clk; + always @(posedge clk) if (tn !== expval) begin + $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; + end +endmodule + +module t_tri2 + (line, expval, tn); + input integer line; + input expval; + input tn; + pulldown(tn); + wire clk = t.clk; + always @(posedge clk) if (tn !== expval) begin + $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; + end +endmodule + +module t_tri3 + (line, expval, tn); + input integer line; + input expval; + input tn; + pullup(tn); + wire clk = t.clk; + always @(negedge clk) if (tn !== expval) begin + $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_tri_various.v b/SVIncCompil/Testcases/Verilator/t_tri_various.v new file mode 100644 index 0000000..945130d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_tri_various.v
@@ -0,0 +1,210 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks + +module t (clk); + input clk; + + reg [31:0] state; initial state=0; + + wire A = state[0]; + wire OE = state[1]; + wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9; + wire [3:0] Z10; + wire Z11; + + Test1 test1(/*AUTOINST*/ + // Inouts + .Z1 (Z1), + // Inputs + .OE (OE), + .A (A)); + + Test2 test2(/*AUTOINST*/ + // Inouts + .Z2 (Z2), + // Inputs + .OE (OE), + .A (A)); + + Test3 test3(/*AUTOINST*/ + // Inouts + .Z3 (Z3), + // Inputs + .OE (OE), + .A (A)); + + Test4 test4(/*AUTOINST*/ + // Outputs + .Z4 (Z4), + // Inouts + .Z5 (Z5)); + + Test5 test5(/*AUTOINST*/ + // Inouts + .Z6 (Z6), + .Z7 (Z7), + .Z8 (Z8), + .Z9 (Z9), + // Inputs + .OE (OE)); + + Test6 test6(/*AUTOINST*/ + // Inouts + .Z10 (Z10[3:0]), + // Inputs + .OE (OE)); + + Test7 test7(/*AUTOINST*/ + // Outputs + .Z11 (Z11), + // Inputs + .state (state[2:0])); + + always @(posedge clk) begin + state <= state + 1; +`ifdef TEST_VERBOSE + $write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n", + $time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11); +`endif + + if(state == 0) begin + if(Z1 !== 1'b1) $stop; // tests pullups + if(Z2 !== 1'b1) $stop; + if(Z3 !== 1'b1) $stop; +`ifndef VERILATOR + if(Z4 !== 1'b1) $stop; +`endif + if(Z5 !== 1'b1) $stop; + if(Z6 !== 1'b1) $stop; + if(Z7 !== 1'b0) $stop; + if(Z8 !== 1'b0) $stop; + if(Z9 !== 1'b1) $stop; + if(Z10 !== 4'b0001) $stop; + if(Z11 !== 1'b0) $stop; + end + else if(state == 1) begin + if(Z1 !== 1'b1) $stop; // tests pullup + if(Z2 !== 1'b1) $stop; + if(Z3 !== 1'b1) $stop; +`ifndef VERILATOR + if(Z4 !== 1'b1) $stop; +`endif + if(Z5 !== 1'b1) $stop; + if(Z6 !== 1'b1) $stop; + if(Z7 !== 1'b0) $stop; + if(Z8 !== 1'b0) $stop; + if(Z9 !== 1'b1) $stop; + if(Z10 !== 4'b0001) $stop; + if(Z11 !== 1'b1) $stop; + end + else if(state == 2) begin + if(Z1 !== 1'b0) $stop; // tests output driver low + if(Z2 !== 1'b0) $stop; + if(Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts +`ifndef VERILATOR + if(Z4 !== 1'b1) $stop; +`endif + if(Z5 !== 1'b1) $stop; + if(Z6 !== 1'b0) $stop; + if(Z7 !== 1'b1) $stop; + if(Z8 !== 1'b1) $stop; + if(Z9 !== 1'b0) $stop; + if(Z10 !== 4'b0010) $stop; + //if(Z11 !== 1'bx) $stop; // Doesn't matter + end + else if(state == 3) begin + if(Z1 !== 1'b1) $stop; // tests output driver high + if(Z2 !== 1'b1) $stop; + if(Z3 !== 1'b1) $stop; +`ifndef VERILATOR + if(Z4 !== 1'b1) $stop; +`endif + if(Z5 !== 1'b1) $stop; + if(Z6 !== 1'b0) $stop; + if(Z7 !== 1'b1) $stop; + if(Z8 !== 1'b1) $stop; + if(Z9 !== 1'b0) $stop; + if(Z10 !== 4'b0010) $stop; + if(Z11 !== 1'b1) $stop; + end + else if(state == 4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + pullup(Z1); + pullup(Z2); + pullup(Z3); + pullup(Z4); + pullup(Z5); + pullup(Z6); + pulldown(Z7); + pullup(Z8); + pulldown(Z9); + pulldown pd10[3:0] (Z10); +endmodule + + +module Test1(input OE, input A, inout Z1); + assign Z1 = (OE) ? A : 1'bz; +endmodule + +module Test2(input OE, input A, inout Z2); + assign Z2 = (OE) ? A : 1'bz; +endmodule + + +// mixed low-Z and tristate +module Test3(input OE, input A, inout Z3); + assign Z3 = (OE) ? A : 1'bz; + assign Z3 = 1'b1; +endmodule + + +// floating output and inout +`ifndef VERILATOR +// Note verilator doesn't know to make Z4 a tristate unless marked an inout +`endif +module Test4(output Z4, inout Z5); +endmodule + + +// AND gate tristates +module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9); + assign Z6 = (OE) ? 1'b0 : 1'bz; + assign Z7 = (OE) ? 1'b1 : 1'bz; + assign Z8 = (OE) ? 1'bz : 1'b0; + assign Z9 = (OE) ? 1'bz : 1'b1; +endmodule + +// AND gate tristates +module Test6(input OE, inout [3:0] Z10); + wire [1:0] i; + Test6a a (.OE(OE), .Z({Z10[0],Z10[1]})); + Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]})); +endmodule + +module Test6a(input OE, inout [1:0] Z); + assign Z = (OE) ? 2'b01 : 2'bzz; +endmodule + +module Test7(input [2:0] state, output reg Z11); + always @(*) begin + casez (state) + 3'b000: Z11 = 1'b0; + 3'b0?1: Z11 = 1'b1; + default: Z11 = 1'bx; + endcase + end +endmodule + +// This is not implemented yet +//module Test3(input OE, input A, inout Z3); +// always @(*) begin +// if(OE) begin +// Z3 = A; +// end else begin +// Z3 = 1'bz; +// end +// end +//endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_type_param.v b/SVIncCompil/Testcases/Verilator/t_type_param.v new file mode 100644 index 0000000..b2bf986 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_type_param.v
@@ -0,0 +1,111 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Todd Strader. + +module foo + #(parameter type bar = logic) + (output int bar_size); + + localparam baz = $bits(bar); + + assign bar_size = baz; +endmodule + +module foo_wrapper + #(parameter bar_bits = 9) + (output int bar_size); + + foo #(.bar (logic[bar_bits-1:0])) foo_inst (.bar_size (bar_size)); + +endmodule + +module t(); + logic [7:0] qux1; + int bar_size1; + + foo #(.bar (logic [ $bits(qux1) - 1 : 0])) + foo_inst1 (.bar_size (bar_size1)); + + logic [7:0] qux2; + int bar_size2; + + foo #(.bar (logic [ $bits(qux2) - 1 : 0])) + foo_inst2 (.bar_size (bar_size2)); + + logic [7:0] qux3; + int bar_size3; + + foo #(.bar (logic [ $bits(qux3) - 1 : 0])) + foo_inst3 (.bar_size (bar_size3)); + + localparam bar_bits = 13; + int bar_size_wrapper; + + foo_wrapper #(.bar_bits (bar_bits)) + foo_wrapper_inst (.bar_size (bar_size_wrapper)); + + initial begin + if ($bits(qux1) != foo_inst1.baz) begin + $display("%m: bits of qux1 != bits of foo_inst1.baz (%0d, %0d)", + $bits(qux1), foo_inst1.baz); + $stop(); + end + if ($bits(qux2) != foo_inst2.baz) begin + $display("%m: bits of qux2 != bits of foo_inst2.baz (%0d, %0d)", + $bits(qux2), foo_inst2.baz); + $stop(); + end + if ($bits(qux3) != foo_inst3.baz) begin + $display("%m: bits of qux3 != bits of foo_inst3.baz (%0d, %0d)", + $bits(qux3), foo_inst3.baz); + $stop(); + end + if (bar_bits != foo_wrapper_inst.foo_inst.baz) begin + $display("%m: bar_bits != bits of foo_wrapper_inst.foo_inst.baz (%0d, %0d)", + bar_bits, foo_wrapper_inst.foo_inst.baz); + $stop(); + end + if (bar_size1 != $bits(qux1)) begin + $display("%m: bar_size1 != bits of qux1 (%0d, %0d)", + bar_size1, $bits(qux1)); + $stop(); + end + if (bar_size2 != $bits(qux2)) begin + $display("%m: bar_size2 != bits of qux2 (%0d, %0d)", + bar_size2, $bits(qux2)); + $stop(); + end + if (bar_size3 != $bits(qux3)) begin + $display("%m: bar_size3 != bits of qux3 (%0d, %0d)", + bar_size3, $bits(qux3)); + $stop(); + end + if (bar_size_wrapper != bar_bits) begin + $display("%m: bar_size_wrapper != bar_bits (%0d, %0d)", + bar_size_wrapper, bar_bits); + $stop(); + end + end + + genvar m; + generate + for (m = 1; m <= 8; m+=1) begin : gen_m + initial begin + if (m != foo_inst.baz) begin + $display("%m: m != bits of foo_inst.baz (%0d, %0d)", + m, foo_inst.baz); + $stop(); + end + end + + foo #(.bar (logic[m-1:0])) foo_inst (.bar_size ()); + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_typedef.v b/SVIncCompil/Testcases/Verilator/t_typedef.v new file mode 100644 index 0000000..58ccd88 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_typedef.v
@@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +program t; + parameter SIZE = 5; + + typedef reg [SIZE-1:0] vec_t ; + vec_t a; initial a =0; + + typedef bit [SIZE-1:0] vec_bit_t ; + vec_bit_t b; initial b =0; + + typedef int array [3]; + typedef array array2 [2]; + array2 ar [1]; + + // Define before use + // Not sure how well supported this is elsewhere + //UNSUP typedef preuse; + //UNSUP preuse p; + //UNSUP typedef int preuse; + +//reg [SIZE-1:0] a; initial a =0; +//reg [SIZE-1:0] b; initial b =0; + + initial begin + typedef logic [3:0][7:0] instr_mem_t; + instr_mem_t a; + a[0] = 8'h12; + if (a[0] != 8'h12) $stop; + end + + integer j; + initial begin + for (j=0;j<=(1<<SIZE);j=j+1) begin + a = a + 1; + b = b + 1; + //$write("a=%d \t b=%d \n", a,b); + end + + if (a != 1 ) begin + $write("a=%d \n", a); + $stop; + end + if (b != 1 ) begin + $write("b=%d \n", b); + $stop; + end + + ar[0][0][0] = 0; + ar[0][0][2] = 2; + ar[0][1][0] = 3; + ar[0][1][2] = 5; + if (ar[0][0][0] !== 0) $stop; + if (ar[0][0][2] !== 2) $stop; + if (ar[0][1][0] !== 3) $stop; + if (ar[0][1][2] !== 5) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endprogram
diff --git a/SVIncCompil/Testcases/Verilator/t_typedef_array.v b/SVIncCompil/Testcases/Verilator/t_typedef_array.v new file mode 100644 index 0000000..cabcf3b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_typedef_array.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by James Pallister. + +typedef logic logic_alias_t; + +module t; + logic_alias_t [6:1] signal; + // verilator lint_off LITENDIAN + logic_alias_t [1:6] signal2; + // verilator lint_on LITENDIAN + + initial begin + signal[6:1] = 'b100001; + signal[3] = 'b1; + signal2[1:6] = 'b100001; + signal2[4] = 'b1; + + if (signal != 'b100101) $stop; + if (signal2 != 'b100101) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_typedef_circ_bad.v b/SVIncCompil/Testcases/Verilator/t_typedef_circ_bad.v new file mode 100644 index 0000000..5c20752 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_typedef_circ_bad.v
@@ -0,0 +1,6 @@ +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder + +typedef a_t; +typedef a_t b_t; +typedef b_t a_t;
diff --git a/SVIncCompil/Testcases/Verilator/t_typedef_param.v b/SVIncCompil/Testcases/Verilator/t_typedef_param.v new file mode 100644 index 0000000..4cbba8f --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_typedef_param.v
@@ -0,0 +1,107 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +typedef reg [2:0] threeansi_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [2:0] in = crc[2:0]; + + localparam type three_t = reg [2:0]; + + three_t outna; + three_t outa; + + TestNonAnsi #( .p_t (reg [2:0]) ) + test (// Outputs + .out (outna), + /*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[2:0])); + + TestAnsi #( .p_t (reg [2:0])) + testa (// Outputs + .out (outa), + /*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[2:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, outna, 1'b0, outa}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h018decfea0a8828a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module TestNonAnsi (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + parameter type p_t = shortint; + + input clk; + input p_t in; + output p_t out; + + always @(posedge clk) begin + out <= ~in; + end +endmodule + +module TestAnsi + #( parameter type p_t = shortint ) + ( + input clk, + input p_t in, + output p_t out + ); + always @(posedge clk) begin + out <= ~in; + end +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_typedef_port.v b/SVIncCompil/Testcases/Verilator/t_typedef_port.v new file mode 100644 index 0000000..0bc6514 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_typedef_port.v
@@ -0,0 +1,106 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +typedef reg [2:0] threeansi_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + typedef reg [2:0] three_t; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [2:0] in = crc[2:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + threeansi_t outa; // From testa of TestAnsi.v + three_t outna; // From test of TestNonAnsi.v + // End of automatics + + TestNonAnsi test (// Outputs + .out (outna), + /*AUTOINST*/ + // Inputs + .clk (clk), + .in (in)); + + TestAnsi testa (// Outputs + .out (outa), + /*AUTOINST*/ + // Inputs + .clk (clk), + .in (in)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, outna, 1'b0, outa}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h018decfea0a8828a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module TestNonAnsi (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + typedef reg [2:0] three_t; + + input clk; + input three_t in; + output three_t out; + + always @(posedge clk) begin + out <= ~in; + end +endmodule + +module TestAnsi ( + input clk, + input threeansi_t in, + output threeansi_t out + ); + always @(posedge clk) begin + out <= ~in; + end +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_typedef_signed.v b/SVIncCompil/Testcases/Verilator/t_typedef_signed.v new file mode 100644 index 0000000..2432f94 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_typedef_signed.v
@@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +//bug456 + +typedef logic signed [34:0] rc_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [34:0] rc = crc[34:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic o; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .o (o), + // Inputs + .rc (rc), + .clk (clk)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, o}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h7211d24a17b25ec9 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test( output logic o, + input rc_t rc, + input logic clk); + + localparam RATIO = 2; + + rc_t rc_d[RATIO:1]; + + always_ff @(posedge clk) begin + integer k; + + rc_d[1] <= rc; + + for( k=2; k<RATIO+1; k++ ) begin + rc_d[k] <= rc_d[k-1]; + end + end // always_ff @ + + assign o = rc_d[RATIO] < 0; + +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End:
diff --git a/SVIncCompil/Testcases/Verilator/t_udp.v b/SVIncCompil/Testcases/Verilator/t_udp.v new file mode 100644 index 0000000..e946fd8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_udp.v
@@ -0,0 +1,144 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + + // Async clears must not race with clocks if we want repeatable results + reg set_l = in[20]; + reg clr_l = in[21]; + always @ (negedge clk) begin + set_l <= in[20]; + clr_l <= in[21]; + end + + //====== Mux + wire [1:0] qm; + // delay z a b sel + udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]); + udp_mux2 #0.1 m1 (qm[1], in[1], in[3], in[4]); + +`define verilatorxx +`ifdef verilatorxx + reg [1:0] ql; + reg [1:0] qd; + + // No sequential tables, yet +// always @* begin +// if (!clk) ql = in[13:12]; +// end + always @(posedge clk or negedge set_l or negedge clr_l) begin + if (!set_l) qd <= ~2'b0; + else if (!clr_l) qd <= 2'b0; + else qd <= in[17:16]; + end +`else + //====== Latch +// wire [1:0] ql; +// // q clk d +// udp_latch l0 (ql[0], !in[8], in[12]); +// udp_latch l1 (ql[1], !in[8], in[13]); + + //====== DFF + wire [1:0] qd; + //always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]); + // q clk d set_l clr_l + udp_dff d0 (qd[0], in[8], in[16], set_l, clr_l); + udp_dff d2 (qd[1], in[8], in[17], set_l, clr_l); +`endif + + // Aggregate outputs into a single result vector + wire [63:0] result = {52'h0, 2'b0,qd, 4'b0, 2'b0,qm}; +// wire [63:0] result = {52'h0, 2'b0,qd, 2'b0,ql, 2'b0,qm}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + // Note not all simulators agree about the latch result. Maybe have a race? +`define EXPECTED_SUM 64'hb73acf228acaeaa3 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +primitive udp_mux2 (z, a, b, sel); + output z; + input a, b, sel; + table + //a b s o + ? 1 1 : 1 ; + ? 0 1 : 0 ; + 1 ? 0 : 1 ; + 0 ? 0 : 0 ; + 1 1 x : 1 ; + 0 0 x : 0 ; + endtable +endprimitive + +primitive udp_latch (q, clk, d); + output q; reg q; + input clk, d; + table + //clk d q q' + 0 1 : ? : 1; + 0 0 : ? : 0; + 1 ? : ? : -; + endtable +endprimitive + +primitive udp_dff (q, clk, d, set_l, clr_l); + output q; + input clk, d, set_l, clr_l; + reg q; + table + //ck d s c : q : q' + r 0 1 ? : ? : 0 ; + r 1 ? 1 : ? : 1 ; + * 1 ? 1 : 1 : 1 ; + * 0 1 ? : 0 : 0 ; + f ? ? ? : ? : - ; + b * ? ? : ? : - ; + ? ? 0 ? : ? : 1 ; + b ? * 1 : 1 : 1 ; + x 1 * 1 : 1 : 1 ; + ? ? 1 0 : ? : 0 ; + b ? 1 * : 0 : 0 ; + x 0 1 * : 0 : 0 ; + endtable +endprimitive
diff --git a/SVIncCompil/Testcases/Verilator/t_udp_noname.v b/SVIncCompil/Testcases/Verilator/t_udp_noname.v new file mode 100644 index 0000000..4ac1986 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_udp_noname.v
@@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg a; + wire o; + udp (o, a); + + integer cyc; initial cyc=0; + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + a <= cyc[0]; + if (cyc==0) begin + end + else if (cyc<90) begin + if (a != !cyc[0]) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +primitive udp(o,a); + output o; + input a; +`ifdef verilator + wire o = ~a; +`else + table + //o a + 0 : 1; + 1 : 0; + endtable +`endif +endprimitive
diff --git a/SVIncCompil/Testcases/Verilator/t_uniqueif.v b/SVIncCompil/Testcases/Verilator/t_uniqueif.v new file mode 100644 index 0000000..7700eb5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_uniqueif.v
@@ -0,0 +1,111 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc=1; + integer a, b, c, d, e, f, g, h, i, j, k, l; + + always @ (posedge clk) begin + cyc <= cyc + 1; + + //==================== + // Positive test cases + //==================== + + // Single if, which is untrue sometimes + unique0 if (cyc > 5) + a <= 17; + + // single if with else + unique0 if (cyc < 3) + b <= 17; + else + b <= 19; + + // multi if, some cases may not be true + unique0 if (cyc < 3) + c <= 17; + else if (cyc > 3) + c <= 19; + + // multi if with else, else clause hit in some cases + unique0 if (cyc < 3) + d <= 17; + else if (cyc > 3) + d <= 19; + else + d <= 21; + + // single if with else + unique if (cyc < 3) + f <= 17; + else + f <= 19; + + // multi if + unique if (cyc < 3) + g <= 17; + else if (cyc >= 3) + g <= 19; + + // multi if with else, else clause hit in some cases + unique if (cyc < 3) + h <= 17; + else if (cyc > 3) + h <= 19; + else + h <= 21; + + //==================== + // Negative test cases + //==================== +`ifdef FAILING_ASSERTION1 + $display("testing fail 1: %d", cyc); + // multi if, multiple cases true + unique0 if (cyc < 3) + i <= 17; + else if (cyc < 5) + i <= 19; +`endif + +`ifdef FAILING_ASSERTION2 + // multi if, multiple cases true + unique if (cyc < 3) + j <= 17; + else if (cyc < 5) + j <= 19; +`endif + +`ifdef FAILING_ASSERTION3 + // multi if, no cases true + unique if (cyc > 1000) + k <= 17; + else if (cyc > 2000) + k <= 19; +`endif + +`ifdef FAILING_ASSERTION4 + // Single if, which is untrue sometimes. + // The LRM states: "A software tool shall also issue an error if it determines that no condition' + // is true, or it is possible that no condition is true, and the final if does not have a + // corresponding else." In this case, the final if is the only if, but I think the clause + // still applies. + unique if (cyc > 5) + l <= 17; +`endif + + + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unopt_array.v b/SVIncCompil/Testcases/Verilator/t_unopt_array.v new file mode 100644 index 0000000..ab2faed --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unopt_array.v
@@ -0,0 +1,90 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h458c2de282e30f8b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + output wire [31:0] out; + + reg [31:0] stage [3:0]; + + genvar g; + + generate + for (g=0; g<4; g++) begin + always_comb begin + if (g==0) stage[g] = in; + else stage[g] = {stage[g-1][30:0],1'b1}; + end + end + endgenerate + + assign out = stage[3]; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unopt_bound.v b/SVIncCompil/Testcases/Verilator/t_unopt_bound.v new file mode 100644 index 0000000..ba60499 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unopt_bound.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jue Xu. + +// bug630 + +module t ( clk, out ); + input clk; + output out; + + reg a; + reg b; + + typedef struct packed { + logic config_a; + logic config_b; + } param_t; + // verilator lint_off UNOPTFLAT + param_t conf [1:2] ; + // verilator lint_on UNOPTFLAT + + always @ (posedge clk) begin + conf[2].config_b <= a; + $write("*-* All Finished *-*\n"); + $finish; + end + always @ (posedge conf[2].config_b) begin + a = conf[2].config_a; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unopt_combo.v b/SVIncCompil/Testcases/Verilator/t_unopt_combo.v new file mode 100644 index 0000000..f923d97 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unopt_combo.v
@@ -0,0 +1,134 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] b; // From file of file.v + wire [31:0] c; // From file of file.v + wire [31:0] d; // From file of file.v + // End of automatics + + file file (/*AUTOINST*/ + // Outputs + .b (b[31:0]), + .c (c[31:0]), + .d (d[31:0]), + // Inputs + .crc (crc[31:0])); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {b, d} + ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h649ee1713d624dd9) $stop; + $finish; + end + end + +endmodule + +module file (/*AUTOARG*/ + // Outputs + b, c, d, + // Inputs + crc + ); + + input [31:0] crc; +`ifdef ISOLATE + output reg [31:0] b /* verilator isolate_assignments*/; +`else + output reg [31:0] b; +`endif + + output reg [31:0] c; + output reg [31:0] d; + + always @* begin + // Note that while c and b depend on crc, b doesn't depend on c. + casez (crc[3:0]) + 4'b??01: begin + b = {crc[15:0],get_31_16(crc)}; + d = c; + end + 4'b??00: begin + b = {crc[15:0],~crc[31:16]}; + d = {crc[15:0],~c[31:16]}; + end + default: begin + set_b_d(crc, c); + end + endcase + end + + function [31:16] get_31_16 /* verilator isolate_assignments*/; + input [31:0] t_crc /* verilator isolate_assignments*/; + get_31_16 = t_crc[31:16]; + endfunction + + task set_b_d; +`ifdef ISOLATE + input [31:0] t_crc /* verilator isolate_assignments*/; + input [31:0] t_c /* verilator isolate_assignments*/; +`else + input [31:0] t_crc; + input [31:0] t_c; +`endif + begin + b = {t_crc[31:16],~t_crc[23:8]}; + d = {t_crc[31:16], ~t_c[23:8]}; + end + endtask + + always @* begin + // Any complicated equation we can't optimize + casez (crc[3:0]) + 4'b00??: begin + c = {b[29:0],2'b11}; + end + 4'b01??: begin + c = {b[30:1],2'b01}; + end + 4'b10??: begin + c = {b[31:2],2'b10}; + end + 4'b11??: begin + c = {b[31:2],2'b00}; + end + endcase + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unopt_converge.v b/SVIncCompil/Testcases/Verilator/t_unopt_converge.v new file mode 100644 index 0000000..fc2e235 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unopt_converge.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + x, + // Inputs + clk + ); + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + input clk; + output x; // Avoid eliminating x + + reg x; + always @* begin + x = ~x; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unopt_converge_initial.v b/SVIncCompil/Testcases/Verilator/t_unopt_converge_initial.v new file mode 100644 index 0000000..7806042 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unopt_converge_initial.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + x, + // Inputs + clk + ); + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + input clk; + output [31:0] x; // Avoid eliminating x + + reg [31:0] x; + always @* begin + x = x ^ $random; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unoptflat_simple.v b/SVIncCompil/Testcases/Verilator/t_unoptflat_simple.v new file mode 100644 index 0000000..f3e5be0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unoptflat_simple.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Simple demonstration of an UNOPTFLAT combinatorial loop, using just 2 bits. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [1:0] x = { x[0], clk }; + + initial begin + x = 0; + end + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write("x = %x\n", x); +`endif + + if (x[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unoptflat_simple_2.v b/SVIncCompil/Testcases/Verilator/t_unoptflat_simple_2.v new file mode 100644 index 0000000..d3b50d3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unoptflat_simple_2.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Simple demonstration of an UNOPTFLAT combinatorial loop, using 3 bits. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [2:0] x; + + assign x[1:0] = { x[0], clk }; + assign x[2:1] = { clk, x[1] }; + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write("x = %x\n", x); +`endif + + if (x[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule // t
diff --git a/SVIncCompil/Testcases/Verilator/t_unoptflat_simple_3.v b/SVIncCompil/Testcases/Verilator/t_unoptflat_simple_3.v new file mode 100644 index 0000000..d8a4691 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unoptflat_simple_3.v
@@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Demonstration of an UNOPTFLAT combinatorial loop using 3 bits and looping +// through 2 sub-modules. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [2:0] x; + + initial begin + x = 3'b000; + end + + test1 test1i ( .clk (clk), + .xvecin (x[1:0]), + .xvecout (x[2:1])); + + test2 test2i ( .clk (clk), + .xvecin (x[2:1]), + .xvecout (x[1:0])); + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write("x = %x\n", x); +`endif + + if (x[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule // t + + +module test1 + (/*AUTOARG*/ + // Inputs + clk, + xvecin, + // Outputs + xvecout + ); + + input clk; + input wire [1:0] xvecin; + + output wire [1:0] xvecout; + + assign xvecout = {xvecin[0], clk}; + +endmodule // test + + +module test2 + (/*AUTOARG*/ + // Inputs + clk, + xvecin, + // Outputs + xvecout + ); + + input clk; + input wire [1:0] xvecin; + + output wire [1:0] xvecout; + + assign xvecout = {clk, xvecin[1]}; + +endmodule // test
diff --git a/SVIncCompil/Testcases/Verilator/t_unpacked_array_order.v b/SVIncCompil/Testcases/Verilator/t_unpacked_array_order.v new file mode 100644 index 0000000..ea1c67a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unpacked_array_order.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Duraid Madina. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter logic [1:0] t0 [ 2][ 2] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; + parameter logic [1:0] t1 [0:1][0:1] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; + parameter logic [1:0] t2 [1:0][1:0] = '{'{2'd3, 2'd2}, '{2'd1, 2'd0}}; + + always @ (posedge clk) begin + if (t0[0][0] != t1[0][0]) $stop; + if (t0[0][1] != t1[0][1]) $stop; + if (t0[1][0] != t1[1][0]) $stop; + if (t0[1][1] != t1[1][1]) $stop; + if (t0[0][0] != t2[0][0]) $stop; + if (t0[0][1] != t2[0][1]) $stop; + if (t0[1][0] != t2[1][0]) $stop; + if (t0[1][1] != t2[1][1]) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unroll_complexcond.v b/SVIncCompil/Testcases/Verilator/t_unroll_complexcond.v new file mode 100644 index 0000000..49592a5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unroll_complexcond.v
@@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This files is used to generated the BLKLOOPINIT error which +// is actually caused by not being able to unroll the for loop. +// +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jie Xu. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [3:0] tmp [3:0]; + + initial begin + tmp[0] = 4'b0000; + tmp[2] = 4'b0010; + tmp[3] = 4'b0011; + end + + // Test loop + always @ (posedge clk) begin + int i; + int j; + for (i = 0;(i < 4) && (i > 1); i++) begin + tmp[i] <= tmp[i-i]; + end + if (tmp[0] != 4'b0000) $stop; + if (tmp[3] != 4'b0011) $stop; + + j = 0; for (i=$c32("1"); i<3; ++i) j++; + if (j!=2) $stop; + j = 0; for (i=1; i<$c32("3"); ++i) j++; + if (j!=2) $stop; + j = 0; for (i=1; i<3; i=i+$c32("1")) j++; + if (j!=2) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unroll_forfor.v b/SVIncCompil/Testcases/Verilator/t_unroll_forfor.v new file mode 100644 index 0000000..fee7b8c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unroll_forfor.v
@@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This files is used to generated the following error: +// %Error: Internal Error: t/t_unroll_forfor.v:27: ../V3Simulate.h:177: No value found for node. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Jan Egil Ruud. + +module t (/*AUTOARG*/ + // Inputs + clk, in + ); + input clk; + input [71:0] in; + + reg [71:0] in_tmp; + + localparam [71:0] TEST_PARAM = {72{1'b0}}; + + // Test loop + always @* + begin: testmap + byte i, j; + // bug1044 + for ( i = 0; i < 9; i = i + 1 ) + for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1 ) + begin + // verilator lint_off WIDTH + in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; + // verilator lint_on WIDTH + end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unroll_genf.v b/SVIncCompil/Testcases/Verilator/t_unroll_genf.v new file mode 100644 index 0000000..776f1b3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unroll_genf.v
@@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +//bug830 +module sub(); +endmodule + +function integer cdiv(input integer x); + begin + cdiv = 10; + end +endfunction + +module t (/*AUTOARG*/); + + genvar j; + generate + for (j = 0; j < cdiv(10); j=j+1) + sub sub(); + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_unroll_signed.v b/SVIncCompil/Testcases/Verilator/t_unroll_signed.v new file mode 100644 index 0000000..45f9956 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_unroll_signed.v
@@ -0,0 +1,151 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Check empty blocks + task EmptyFor; + /* verilator public */ + integer i; + begin + for (i = 0; i < 2; i = i+1) + begin + end + end + endtask + + // Check look unroller + reg signed signed_tests_only = 1'sb1; + integer total; + + integer i; + reg [31:0] iu; + reg [31:0] dly_to_insure_was_unrolled [1:0]; + reg [2:0] i3; + + integer cyc; initial cyc=0; + always @ (posedge clk) begin + cyc <= cyc + 1; + case (cyc) + 1: begin + // >= signed + total = 0; + for (i=5; i>=0; i=i-1) begin + total = total - i -1; + dly_to_insure_was_unrolled[i] <= i; + end + if (total != -21) $stop; + end + 2: begin + // > signed + total = 0; + for (i=5; i>0; i=i-1) begin + total = total - i -1; + dly_to_insure_was_unrolled[i] <= i; + end + if (total != -20) $stop; + end + 3: begin + // < signed + total = 0; + for (i=1; i<5; i=i+1) begin + total = total - i -1; + dly_to_insure_was_unrolled[i] <= i; + end + if (total != -14) $stop; + end + 4: begin + // <= signed + total = 0; + for (i=1; i<=5; i=i+1) begin + total = total - i -1; + dly_to_insure_was_unrolled[i] <= i; + end + if (total != -20) $stop; + end + // UNSIGNED + 5: begin + // >= unsigned + total = 0; + for (iu=5; iu>=1; iu=iu-1) begin + total = total - iu -1; + dly_to_insure_was_unrolled[iu] <= iu; + end + if (total != -20) $stop; + end + 6: begin + // > unsigned + total = 0; + for (iu=5; iu>1; iu=iu-1) begin + total = total - iu -1; + dly_to_insure_was_unrolled[iu] <= iu; + end + if (total != -18) $stop; + end + 7: begin + // < unsigned + total = 0; + for (iu=1; iu<5; iu=iu+1) begin + total = total - iu -1; + dly_to_insure_was_unrolled[iu] <= iu; + end + if (total != -14) $stop; + end + 8: begin + // <= unsigned + total = 0; + for (iu=1; iu<=5; iu=iu+1) begin + total = total - iu -1; + dly_to_insure_was_unrolled[iu] <= iu; + end + if (total != -20) $stop; + end + //=== + 9: begin + // mostly cover a small index + total = 0; + for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin + total = total - {29'd0,i3} -1; + dly_to_insure_was_unrolled[i3[0]] <= 0; + end + if (total != -28) $stop; + end + //=== + 10: begin + // mostly cover a small index + total = 0; + for (i3=0; i3<3'd7; i3=i3+3'd1) begin + total = total - {29'd0,i3} -1; + dly_to_insure_was_unrolled[i3[0]] <= 0; + end + if (total != -28) $stop; + end + //=== + 11: begin + // width violation on <, causes extend + total = 0; + for (i3=3'd0; i3<7; i3=i3+1) begin + total = total - {29'd0,i3} -1; + dly_to_insure_was_unrolled[i3[0]] <= 0; + end + if (total != -28) $stop; + end + //=== + // width violation on <, causes extend signed + // Unsupported as yet + //=== + 19: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_vams_basic.v b/SVIncCompil/Testcases/Verilator/t_vams_basic.v new file mode 100644 index 0000000..e7caa96 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_vams_basic.v
@@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +`begin_keywords "VAMS-2.3" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + task check (integer line, real got, real expec); + real delta; + delta = got-expec; + if (delta > 0.001) begin + $display("Line%d: Got %g Exp %g\n", line, got, expec); + $stop; + end + endtask + + wreal wr; + assign wr = 1.1; + + sub sub (.*); + + initial begin + check(`__LINE__, sqrt(2.0) , 1.414); + check(`__LINE__, pow(2.0,2.0) , 4.0); + check(`__LINE__, ln(2.0) , 0.693147); + check(`__LINE__, log(2.0) , 0.30103); + check(`__LINE__, floor(2.5) , 2.0); + check(`__LINE__, exp(2.0) , 7.38906); + check(`__LINE__, ceil(2.5) , 3.0); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub ( + input wreal wr + ); + initial begin + if (wr != 1.1) $stop; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_vams_wreal.v b/SVIncCompil/Testcases/Verilator/t_vams_wreal.v new file mode 100644 index 0000000..e7b5d03 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_vams_wreal.v
@@ -0,0 +1,136 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +`begin_keywords "VAMS-2.3" + +module t (/*autoarg*/ + // Inputs + clk, in + ); + + input clk; + + input [15:0] in; + wreal aout; + + integer cyc=0; + + real vin; + wreal vpass; + through through (.vin, .vpass); + + real gnd; + wire out; + within_range within_range (/*AUTOINST*/ + // Interfaces + .vpass (vpass), + .gnd (gnd), + // Outputs + .out (out)); + + // wreal bus declaration + wreal vin_upper_bus[1:0]; + + // wreal nets declaration + wreal vout_split_0; + wreal vout_split_1; + + wreal_bus wreal_bus( .vin_bus(vin_upper_bus[1:0]), + .vout_split_0(vout_split_0), + .vout_split_1(vout_split_1)); + + + // implicit declaration of wreal +`ifdef VERILATOR + wreal wreal_implicit_net; // implicit declaration of wreal not supported yet +`endif + // verilator lint_off IMPLICIT + first_level first_level(.in(cyc[0]), .out(wreal_implicit_net)); + // verilator lint_on IMPLICIT + + parameter real lsb = 1; + // verilator lint_off WIDTH + assign aout = $itor(in) * lsb; + // verilator lint_on WIDTH + + always @ (posedge clk) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n",$time, cyc, out, vin, gnd, within_range.in_int); +`endif + if (cyc==0) begin + // Setup + gnd = 0.0; + vin = 0.2; + end + else if (cyc==2) begin + if (out != 0) $stop; + end + else if (cyc==3) begin + gnd = 0.0; + vin = 0.6; + end + else if (cyc==4) begin + if (out != 1) $stop; + end + else if (cyc==5) begin + gnd = 0.6; + vin = 0.8; + end + else if (cyc==6) begin + if (out != 0) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module through + (input wreal vin, + output wreal vpass); + assign vpass = vin; +endmodule + +module within_range + (input wreal vpass, + input wreal gnd, + output out); + + parameter real V_MIN = 0.5; + parameter real V_MAX = 10; + + wreal in_int = vpass - gnd; + assign out = (V_MIN <= in_int && in_int <= V_MAX); +endmodule + + +module wreal_bus + (input wreal vin_bus [1:0], + output wreal vout_split_0, + output wreal vout_split_1); + assign vout_split_0 = vin_bus[0]; + assign vout_split_1 = vin_bus[1]; +endmodule + +module first_level + (input in, +`ifdef VERILATOR + output wreal out +`else + output out // Implicity becomes real +`endif +); + second_level second_level(.in(in), .out(out)); +endmodule + +module second_level(in, out); + input in; + output out; + wreal out; + assign out = in ? 1.23456: 7.8910; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_assign_landr.v b/SVIncCompil/Testcases/Verilator/t_var_assign_landr.v new file mode 100644 index 0000000..28323e2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_assign_landr.v
@@ -0,0 +1,102 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Use this file as a template for submitting bugs, etc. +// This module takes a single clock input, and should either +// $write("*-* All Finished *-*\n"); +// $finish; +// on success, or $stop. +// +// The code as shown applies a random vector to the Test +// module, then calculates a CRC on the Test module's outputs. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by ____YOUR_NAME_HERE____. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [255:0] sum; + + // Take CRC data and apply to testblock inputs + wire [127:0] in = {~crc[63:0], crc[63:0]}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [127:0] o1; // From test of Test.v + wire [127:0] o2; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .o1 (o1[127:0]), + .o2 (o2[127:0]), + // Inputs + .in (in[127:0])); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x %x\n",$time, cyc, crc, o1, o2); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + o1, o2, + // Inputs + in + ); + + input [127:0] in; + output logic [127:0] o1; + output logic [127:0] o2; + + always_comb begin: b_test + logic [127:0] tmpp; + logic [127:0] tmp; + tmp = '0; + tmpp = '0; + + tmp[63:0] = in[63:0]; + tmpp[63:0] = in[63:0]; + + tmpp[63:0] = {tmp[0+:32], tmp[32+:32]}; + tmp[63:0] = {tmp[0+:32], tmp[32+:32]}; + + o1 = tmp; + o2 = tmpp; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_bad_hide.v b/SVIncCompil/Testcases/Verilator/t_var_bad_hide.v new file mode 100644 index 0000000..9597101 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_bad_hide.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + + // Check that the lint_on is obeyed. + // verilator lint_off VARHIDDEN + // verilator lint_on VARHIDDEN + + integer top; + + task x; + output top; + begin end + endtask + + initial begin + begin: lower + integer top; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_bad_hide2.v b/SVIncCompil/Testcases/Verilator/t_var_bad_hide2.v new file mode 100644 index 0000000..1ae2317 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_bad_hide2.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + + // Arguable, but we won't throw a hidden warning on tcp_port + parameter tcp_port = 5678; + import "DPI-C" function int dpii_func ( input integer tcp_port, + output longint obj ); + // 't' is hidden: + integer t; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_bad_sameas.v b/SVIncCompil/Testcases/Verilator/t_var_bad_sameas.v new file mode 100644 index 0000000..d09fe4a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_bad_sameas.v
@@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t; + + integer varfirst; + sub varfirst (); // Error: Cell hits var + task varfirst; begin end endtask // Error: Task hits var + + sub cellfirst (); + integer cellfirst; // Error: Var hits cell + task cellfirst; begin end endtask // Error: Task hits cell + + task taskfirst; begin end endtask + integer taskfirst; // Error: Var hits task + sub taskfirst (); // Error: Cell hits task + +endmodule + +module sub; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_bad_sv.v b/SVIncCompil/Testcases/Verilator/t_var_bad_sv.v new file mode 100644 index 0000000..f3fb61a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_bad_sv.v
@@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + reg do; + mod mod (.do(bar)); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_const.v b/SVIncCompil/Testcases/Verilator/t_var_const.v new file mode 100644 index 0000000..2eebf5b --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_const.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + const logic [2:0] five = 3'd5; + + const logic unsigned [31:0] var_const = 22; + logic [7:0] res_const; + assign res_const = var_const[7:0]; // bug693 + + always @ (posedge clk) begin + if (five !== 3'd5) $stop; + if (res_const !== 8'd22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_const_bad.v b/SVIncCompil/Testcases/Verilator/t_var_const_bad.v new file mode 100644 index 0000000..f37a582 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_const_bad.v
@@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + const logic [2:0] five = 3'd5; + + always @ (posedge clk) begin + five = 3'd4; + if (five !== 3'd5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_dotted.v b/SVIncCompil/Testcases/Verilator/t_var_dotted.v new file mode 100644 index 0000000..e693d26 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_dotted.v
@@ -0,0 +1,173 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + // verilator lint_off MULTIDRIVEN + + wire [31:0] outb0c0; + wire [31:0] outb0c1; + wire [31:0] outb1c0; + wire [31:0] outb1c1; + + reg [7:0] lclmem [7:0]; + + ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1), + .outb1c0(outb1c0), .outb1c1(outb1c1) + ); + + global_mod #(32'hf00d) global_cell (); + global_mod #(32'hf22d) global_cell2 (); + + input clk; + integer cyc=1; + always @ (posedge clk) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1); +`endif + if (cyc==2) begin + if (global_cell.globali != 32'hf00d) $stop; + if (global_cell2.globali != 32'hf22d) $stop; + if (outb0c0 != 32'h00) $stop; + if (outb0c1 != 32'h01) $stop; + if (outb1c0 != 32'h10) $stop; + if (outb1c1 != 32'h11) $stop; + end + if (cyc==3) begin + // Can we scope down and read and write vars? + ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100; + ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100; + ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100; + ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100; + end + if (cyc==4) begin + // Can we do dotted's inside array sels? + ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12; + lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24; + if (outb0c0 != 32'h100) $stop; + if (outb0c1 != 32'h101) $stop; + if (outb1c0 != 32'h110) $stop; + if (outb1c1 != 32'h111) $stop; + end + if (cyc==5) begin + if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop; + if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop; + if (outb0c0 != 32'h1100) $stop; + if (outb0c1 != 32'h2101) $stop; + if (outb1c0 != 32'h2110) $stop; + if (outb1c1 != 32'h3111) $stop; + end + if (cyc==6) begin + if (outb0c0 != 32'h31100) $stop; + if (outb0c1 != 32'h02101) $stop; + if (outb1c0 != 32'h42110) $stop; + if (outb1c1 != 32'h03111) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +`ifdef USE_INLINE_MID + `define INLINE_MODULE /*verilator inline_module*/ + `define INLINE_MID_MODULE /*verilator no_inline_module*/ +`else + `ifdef USE_INLINE + `define INLINE_MODULE /*verilator inline_module*/ + `define INLINE_MID_MODULE /*verilator inline_module*/ + `else + `define INLINE_MODULE /*verilator public_module*/ + `define INLINE_MID_MODULE /*verilator public_module*/ + `endif +`endif + +module global_mod; + `INLINE_MODULE + parameter INITVAL = 0; + integer globali; + initial globali = INITVAL; +endmodule + +module ma ( + output wire [31:0] outb0c0, + output wire [31:0] outb0c1, + output wire [31:0] outb1c0, + output wire [31:0] outb1c1 + ); + `INLINE_MODULE + + reg [7:0] rmtmem [7:0]; + + mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1)); + mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1)); +endmodule + +module mb ( + output wire [31:0] outc0, + output wire [31:0] outc1 + ); + `INLINE_MID_MODULE + parameter P2 = 0; + mc #(P2,0) mc0 (.out(outc0)); + mc #(P2,1) mc1 (.out(outc1)); + global_mod #(32'hf33d) global_cell2 (); + + wire reach_up_clk = t.clk; + always @(reach_up_clk) begin + if (P2==0) begin // Only for mb0 + if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances + if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances + if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances + if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances + if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances + if (outc0 !== mc0.out) $stop; // Lower instances + + if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances + if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances + if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances + if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances + if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances + if (outc1 !== mc1.out) $stop; // Lower instances + end + end +endmodule + +module mc (output reg [31:0] out); + `INLINE_MODULE + parameter P2 = 0; + parameter P3 = 0; + initial begin + out = {24'h0,P2[3:0],P3[3:0]}; + //$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out); + end + + // Can we look from the top module name down? + wire [31:0] reach_up_cyc = t.cyc; + + always @ (posedge t.clk) begin + //$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc); + if (reach_up_cyc==2) begin + if (global_cell.globali != 32'hf00d) $stop; + if (global_cell2.globali != 32'hf33d) $stop; + end + if (reach_up_cyc==4) begin + out[15:12] <= {P2[3:0]+P3[3:0]+4'd1}; + end + if (reach_up_cyc==5) begin + // Can we set another instance? + if (P3==1) begin // Without this, there are two possible correct answers... + mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}; + $display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2); + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_dup2.v b/SVIncCompil/Testcases/Verilator/t_var_dup2.v new file mode 100644 index 0000000..142dfb8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_dup2.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +// Legal with ANSI Verilog 2001 style ports +module t + ( + output wire ok_ow, + output reg ok_or); + + wire ok_o_w; + reg ok_o_r; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_dup2_bad.v b/SVIncCompil/Testcases/Verilator/t_var_dup2_bad.v new file mode 100644 index 0000000..7ae8bc3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_dup2_bad.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +// Illegal with ANSI Verilog 2001 style ports +module t + ( + output bad_o_w, + output bad_o_r); + + wire bad_o_w; + reg bad_o_r; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_dup3.v b/SVIncCompil/Testcases/Verilator/t_var_dup3.v new file mode 100644 index 0000000..38375af --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_dup3.v
@@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +// Legal with Verilog 1995 style ports + +module t + (/*AUTOARG*/ + // Outputs + ok_o_w, ok_o_r, ok_o_ra, ok_or, ok_ow, ok_owa + ); + + output ok_o_w; + wire ok_o_w; + + output ok_o_r; + reg ok_o_r; + + output [1:0] ok_o_ra; + reg [1:0] ok_o_ra; + + output reg ok_or; + + output wire ok_ow; + + output wire [1:0] ok_owa; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_dup_bad.v b/SVIncCompil/Testcases/Verilator/t_var_dup_bad.v new file mode 100644 index 0000000..06b7ad0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_dup_bad.v
@@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t + ( + /*AUTOARG*/ + // Outputs + o, oi, og, org, + // Inputs + i, oi + ); + + reg a; + reg a; + + integer l; + integer l; + + bit b; + bit b; + + output o; + output o; + + input i; + input i; + + output oi; + input oi; + + output og; + reg og; + reg og; + + output reg org; + output reg org; + + sub0 sub0(.*); + sub1 sub1(.*); + sub2 sub2(.*); + sub3 sub3(.*); +endmodule + +module sub0 + ( + bad_duport, + bad_duport + ); + output bad_duport; +endmodule + +module sub1 + ( + bad_mixport, + output bad_mixport + ); +endmodule + +module sub2 + ( + output bad_reout_port + ); + output bad_reout_port; +endmodule + +module sub3 + (output wire bad_rewire, + output reg bad_rereg + ); + wire bad_rewire; + reg bad_rereg; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_escape.v b/SVIncCompil/Testcases/Verilator/t_var_escape.v new file mode 100644 index 0000000..4d063ec --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_escape.v
@@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + \escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done , + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=1; + + output \escaped_normal ; + wire \escaped_normal = cyc[0]; + + output double__underscore ; + wire double__underscore = cyc[0]; + + // C doesn't allow leading non-alpha, so must escape + output \9num ; + wire \9num = cyc[0]; + + output \bra[ket]slash/dash-colon:9backslash\done ; + wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0]; + wire \wire = cyc[0]; + + wire \check_alias = cyc[0]; + wire \check:alias = cyc[0]; + wire \check;alias = !cyc[0]; + + // These are *different entities*, bug83 + wire [31:0] \a0.cyc = ~a0.cyc; + wire [31:0] \other.cyc = ~a0.cyc; + + sub a0 (.cyc(cyc)); + + sub \mod.with_dot (.cyc(cyc)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (escaped_normal != cyc[0]) $stop; + if (\escaped_normal != cyc[0]) $stop; + if (double__underscore != cyc[0]) $stop; + if (\9num != cyc[0]) $stop; + if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop; + if (\wire != cyc[0]) $stop; + if (\check_alias != cyc[0]) $stop; + if (\check:alias != cyc[0]) $stop; + if (\check;alias != !cyc[0]) $stop; + if (\a0.cyc != ~cyc) $stop; + if (\other.cyc != ~cyc) $stop; + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub ( + input [31:0] cyc + ); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_in_assign.v b/SVIncCompil/Testcases/Verilator/t_var_in_assign.v new file mode 100644 index 0000000..ed7475a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_in_assign.v
@@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + integer v; + + reg i; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire oa; // From a of a.v + wire oz; // From z of z.v + // End of automatics + + a a (.*); + z z (.*); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz); +`endif + cyc <= cyc + 1; + i <= cyc[0]; + if (cyc==0) begin + v = 3; + if (v !== 3) $stop; + if (assignin(v) !== 2) $stop; + if (v !== 3) $stop; // Make sure V didn't get changed + end + else if (cyc<10) begin + if (cyc==11 && oz!==1'b0) $stop; + if (cyc==12 && oz!==1'b1) $stop; + if (cyc==12 && oa!==1'b1) $stop; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + function integer assignin(input integer i); + i = 2; + assignin = i; + endfunction + +endmodule + +module a (input i, output oa); + // verilator lint_off ASSIGNIN + assign i = 1'b1; + assign oa = i; +endmodule + +module z (input i, output oz); + assign oz = i; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_in_assign_bad.v b/SVIncCompil/Testcases/Verilator/t_var_in_assign_bad.v new file mode 100644 index 0000000..a3f5ae5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_in_assign_bad.v
@@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + value + ); + input [3:0] value; + assign value = 4'h0; + sub sub(.valueSub(value[3:0])); +endmodule + +module sub (/*AUTOARG*/ + // Inputs + valueSub + ); + input [3:0] valueSub; + assign valueSub = 4'h0; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_init.v b/SVIncCompil/Testcases/Verilator/t_var_init.v new file mode 100644 index 0000000..5775167 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_init.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + parameter [31:0] p2=2, p3=3; + integer i2=2, i3=3; + reg [31:0] r2=2, r3=3; + wire [31:0] w2=2, w3=3; + + always @ (posedge clk) begin + if (p2 !== 2) $stop; + if (p3 !== 3) $stop; + if (i2 !== 2) $stop; + if (i3 !== 3) $stop; + if (r2 !== 2) $stop; + if (r3 !== 3) $stop; + if (w2 !== 2) $stop; + if (w3 !== 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_life.v b/SVIncCompil/Testcases/Verilator/t_var_life.v new file mode 100644 index 0000000..2a4520d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_life.v
@@ -0,0 +1,104 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + // Life analysis checks + reg [15:0] life; + + // Ding case + reg [7:0] din; + reg [15:0] fixin; + always @* begin + fixin = {din[7:0],din[7:0]}; + case (din[1:0]) + 2'b00: begin + fixin = {fixin[14:0], 1'b1}; + if (cyc==101) $display("Prevent ?: optimization a"); + end + 2'b01: begin + fixin = {fixin[13:0], 2'b11}; + if (cyc==101) $display("Prevent ?: optimization b"); + end + 2'b10: begin + fixin = {fixin[12:0], 3'b111}; + if (cyc==101) $display("Prevent ?: optimization c"); + end + 2'b11: begin + fixin = {fixin[11:0], 4'b1111}; + if (cyc==101) $display("Prevent ?: optimization d"); + end + endcase + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + if (cyc==1) begin + life = 16'h8000; // Dropped + life = 16'h0010; // Used below + if (life != 16'h0010) $stop; + // + life = 16'h0020; // Used below + if ($time < 10000) + if (life != 16'h0020) $stop; + // + life = 16'h8000; // Dropped + if ($time > 100000) begin + if ($time != 0) $stop; // Prevent conversion to ?: + life = 16'h1030; + end + else + life = 16'h0030; + if (life != 16'h0030) $stop; + // + life = 16'h0040; // Not dropped, no else below + if ($time > 100000) + life = 16'h1040; + if (life != 16'h0040) $stop; + // + life = 16'h8000; // Dropped + if ($time > 100000) begin + life = 16'h1050; + if (life != 0) $stop; // Ignored, as set is first + end + else begin + if ($time > 100010) + life = 16'h1050; + else life = 16'h0050; + end + if (life != 16'h0050) $stop; + end + if (cyc==2) begin + din <= 8'haa; + end + if (cyc==3) begin + din <= 8'hfb; + if (fixin != 16'h5557) $stop; + end + if (cyc==4) begin + din <= 8'h5c; + if (fixin != 16'hbfbf) $stop; + end + if (cyc==5) begin + din <= 8'hed; + if (fixin != 16'hb8b9) $stop; + end + if (cyc==6) begin + if (fixin != 16'hb7b7) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_local.v b/SVIncCompil/Testcases/Verilator/t_var_local.v new file mode 100644 index 0000000..543bf1a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_local.v
@@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + + integer top; + integer top_assign=1; + + task automatic tsk; + integer task_assign = 1; + if (task_assign != 1) $stop; + task_assign = 2; + if (task_assign != 2) $stop; + endtask + + initial begin + begin : a + integer lower; + integer lower_assign=1; + lower = 1; + top = 1; + if (lower != 1) $stop; + if (lower_assign != 1) $stop; + begin : aa + integer lev2; + lev2 = 1; + lower = 2; + lower_assign = 2; + top = 2; + end + if (lower != 2) $stop; + if (lower_assign != 2) $stop; + end + begin : b + integer lower; + lower = 1; + top = 2; + begin : empty + begin : empty + end + end + end + tsk; + tsk; // Second time to insure we reinit the initial value + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_nonamebegin.v b/SVIncCompil/Testcases/Verilator/t_var_nonamebegin.v new file mode 100644 index 0000000..03a2536 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_nonamebegin.v
@@ -0,0 +1,74 @@ +module t (/*AUTOARG*/ + // Inputs + clk, reset_l + ); + + input clk; + input reset_l; + + reg inmod; + + generate + if (1) begin + // Traces as genblk1.ingen + integer ingen; + initial $display("ingen: {mod}.genblk1 %m"); + end + endgenerate + + integer rawmod; + + initial begin + begin + integer upa; + begin : d3nameda + // %m='.d3nameda' var=_unnamed#.d3nameda.b1 + integer d3a; + $display("d3a: {mod}.d3nameda %m"); + end + end + end + initial begin + integer b2; + $display("b2: {mod} %m"); + begin : b3named + integer b3n; + $display("b3n: {mod}.b3named: %m"); + end + if (1) begin + integer b3; + $display("b3: {mod} %m"); + if (1) begin + begin + begin + begin + integer b4; + $display("b4: {mod} %m"); + end + end + end + end + else begin + integer b4; + $display("bb %m"); + end + end + else begin + integer b4; + $display("b4 %m"); + end + tsk; + $write("*-* All Finished *-*\n"); + $finish; + end + + task tsk; + integer t1; + $display("t1 {mod}.tsk %m"); + begin + integer t2; + $display("t2 {mod}.tsk %m"); + end + endtask + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_notfound_bad.v b/SVIncCompil/Testcases/Verilator/t_var_notfound_bad.v new file mode 100644 index 0000000..41f6677 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_notfound_bad.v
@@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/); + + integer i; + integer a_var; + + sub sub (); + + task nottask(); endtask + function int notfunc(); return 0; endfunction + + initial begin + nf = 0; // z not found + sub.subsubz.inss = 0; // subsub not found + i = nofunc(); // nofunc not found + i = sub.nofuncs(); // nofuncs not found + notask(); // notask not found + a_var(); // Calling variable as task + $finish; + end +endmodule + +module sub; + subsub subsub (); + function int notfuncs(); return 0; endfunction +endmodule + +module subsub; + integer inss; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_outoforder.v b/SVIncCompil/Testcases/Verilator/t_var_outoforder.v new file mode 100644 index 0000000..752a2d7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_outoforder.v
@@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [125:0] a; + wire q; + + sub sub ( + .q (q), + .a (a), + .clk (clk)); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 126'b1000; + end + if (cyc==2) begin + a <= 126'h1001; + end + if (cyc==3) begin + a <= 126'h1010; + end + if (cyc==4) begin + a <= 126'h1111; + if (q !== 1'b0) $stop; + end + if (cyc==5) begin + if (q !== 1'b1) $stop; + end + if (cyc==6) begin + if (q !== 1'b0) $stop; + end + if (cyc==7) begin + if (q !== 1'b0) $stop; + end + if (cyc==8) begin + if (q !== 1'b0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module sub ( + input clk, + input [125:0] a, + output reg q + ); + + // verilator public_module + + reg [125:0] g_r; + + wire [127:0] g_extend = { g_r, 1'b1, 1'b0 }; + + reg [6:0] sel; + wire g_sel = g_extend[sel]; + + always @ (posedge clk) begin + g_r <= a; + sel <= a[6:0]; + q <= g_sel; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_overcmp.v b/SVIncCompil/Testcases/Verilator/t_var_overcmp.v new file mode 100644 index 0000000..b04f0ba --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_overcmp.v
@@ -0,0 +1,145 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, rstn, dval0, dval1, dbgsel_w + ); + + input clk; + input rstn; + input [7:0] dval0; + input [7:0] dval1; + input [7:0] dbgsel_w; + output [7:0] dout; + + wire [7:0] dout = dout0 | dout1; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] dout0; // From sub0 of sub0.v + wire [7:0] dout1; // From sub1 of sub1.v + // End of automatics + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + + reg [7:0] dbgsel_msk; + always_comb begin + reg [7:0] mask; + mask = 8'hff; + dbgsel_msk = (dbgsel_w & mask); + end + + reg [7:0] dbgsel; + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel <= 0; + end + else begin + dbgsel <= dbgsel_msk; + end + end + + sub0 sub0 (/*AUTOINST*/ + // Outputs + .dout0 (dout0[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); + sub1 sub1 (/*AUTOINST*/ + // Outputs + .dout1 (dout1[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); + +endmodule + +module sub0 + ( + /*AUTOARG*/ + // Outputs + dout0, + // Inputs + rstn, clk, dval1, dbgsel + ); + + input rstn; + input clk; + input [7:0] dval1; + input [7:0] dbgsel; + output reg [7:0] dout0; + + reg [7:0] dbgsel_d1r; + + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin + // verilator lint_on WIDTH + dout0 = dval1; + end + else begin + dout0 = 0; + end + end + + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end + +endmodule + +module sub1 + ( + /*AUTOARG*/ + // Outputs + dout1, + // Inputs + rstn, clk, dval1, dbgsel + ); + + input rstn; + input clk; + input [7:0] dval1; + input [7:0] dbgsel; + output reg [7:0] dout1; + + reg [7:0] dbgsel_d1r; + + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 334) && (dbgsel_d1r < 365))) begin + // verilator lint_on WIDTH + dout1 = dval1; + end + else begin + dout1 = 0; + end + end + + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_overwidth_bad.v b/SVIncCompil/Testcases/Verilator/t_var_overwidth_bad.v new file mode 100644 index 0000000..52fe460 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_overwidth_bad.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_overzero.v b/SVIncCompil/Testcases/Verilator/t_var_overzero.v new file mode 100644 index 0000000..559f5d0 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_overzero.v
@@ -0,0 +1,172 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, rstn, dval0, dval1 + ); + + input clk; + input rstn; + output wire [7:0] dout; + + input [7:0] dval0; + input [7:0] dval1; + wire [7:0] dbgsel_w = '0; + + tsub tsub (/*AUTOINST*/ + // Outputs + .dout (dout[7:0]), + // Inputs + .clk (clk), + .rstn (rstn), + .dval0 (dval0[7:0]), + .dval1 (dval1[7:0]), + .dbgsel_w (dbgsel_w[7:0])); + +endmodule + +module tsub (/*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, rstn, dval0, dval1, dbgsel_w + ); + + input clk; + input rstn; + input [7:0] dval0; + input [7:0] dval1; + input [7:0] dbgsel_w; + output [7:0] dout; + + wire [7:0] dout = dout0 | dout1; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] dout0; // From sub0 of sub0.v + wire [7:0] dout1; // From sub1 of sub1.v + // End of automatics + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + + reg [7:0] dbgsel_msk; + always_comb begin + reg [7:0] mask; + mask = 8'hff; + dbgsel_msk = (dbgsel_w & mask); + end + + // TODO this should optimize away, but presently does not because + // V3Gate constifies then doesn't see all other input edges have disappeared + reg [7:0] dbgsel; + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel <= 0; + end + else begin + dbgsel <= dbgsel_msk; + end + end + + sub0 sub0 (/*AUTOINST*/ + // Outputs + .dout0 (dout0[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval0 (dval0[7:0]), + .dbgsel (dbgsel[7:0])); + sub1 sub1 (/*AUTOINST*/ + // Outputs + .dout1 (dout1[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); + +endmodule + +module sub0 + ( + /*AUTOARG*/ + // Outputs + dout0, + // Inputs + rstn, clk, dval0, dbgsel + ); + + input rstn; + input clk; + input [7:0] dval0; + input [7:0] dbgsel; + output reg [7:0] dout0; + + reg [7:0] dbgsel_d1r; + + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin + // verilator lint_on WIDTH + dout0 = dval0; + end + else begin + dout0 = 0; + end + end + + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end + +endmodule + +module sub1 + ( + /*AUTOARG*/ + // Outputs + dout1, + // Inputs + rstn, clk, dval1, dbgsel + ); + + input rstn; + input clk; + input [7:0] dval1; + input [7:0] dbgsel; + output reg [7:0] dout1; + + reg [7:0] dbgsel_d1r; + + always_comb begin + if (((dbgsel_d1r >= 84) && (dbgsel_d1r < 95))) begin + dout1 = dval1; + end + else begin + dout1 = 0; + end + end + + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_pinsizes.v b/SVIncCompil/Testcases/Verilator/t_var_pinsizes.v new file mode 100644 index 0000000..89aa944 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_pinsizes.v
@@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +// Also check that SystemC is ordering properly +// verilator lint_on IMPERFECTSCH + +module t (/*AUTOARG*/ + // Outputs + o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, + // Inputs + clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16 + ); + + input clk; + + input i1; + input [7:0] i8; + input [15:0] i16; + input [31:0] i32; + input [63:0] i64; + input [64:0] i65; + input [127:0] i128; + input [512:0] i513; + input i1a2 [1:0]; + input [93:0] i94a3 [2:0]; + + output o1; + output [7:0] o8; + output [15:0] o16; + output [31:0] o32; + output [63:0] o64; + output [64:0] o65; + output [127:0] o128; + output [512:0] o513; + output o1a2 [1:0]; + output [93:0] o94a3 [2:0]; + + input [0:0] ibv1 /*verilator sc_bv*/; + input [15:0] ibv16 /*verilator sc_bv*/; + + output [0:0] obv1 /*verilator sc_bv*/; + output [15:0] obv16 /*verilator sc_bv*/; + + always @ (posedge clk) begin + o1 <= i1; + o8 <= i8; + o16 <= i16; + o32 <= i32; + o64 <= i64; + o65 <= i65; + o128 <= i128; + o513 <= i513; + obv1 <= ibv1; + obv16 <= ibv16; + o1a2 <= i1a2; + o94a3 <= i94a3; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_port2_bad.v b/SVIncCompil/Testcases/Verilator/t_var_port2_bad.v new file mode 100644 index 0000000..e059fdc --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_port2_bad.v
@@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (portwithoin); + input portwithin; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_port_bad.v b/SVIncCompil/Testcases/Verilator/t_var_port_bad.v new file mode 100644 index 0000000..75d4691 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_port_bad.v
@@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + subok subok (.a(1'b1), .b(1'b0)); + sub sub (.a(1'b1), .b(1'b0)); +endmodule + +module subok (input a,b); +endmodule + +module sub (a); + input a, b; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_ref.v b/SVIncCompil/Testcases/Verilator/t_var_ref.v new file mode 100644 index 0000000..27c216e --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_ref.v
@@ -0,0 +1,94 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));; end while(0); + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + int cyc; + + int vr; + int va[2]; + +`ifdef T_NOINLINE + // verilator no_inline_module +`endif + + //==== + + task fun(ref int r, const ref int c); +`ifdef T_NOINLINE + // verilator no_inline_task +`endif + `checkh(c, 32'h1234); + r = 32'h4567; + endtask + + initial begin + int ci; + int ri; + ci = 32'h1234; + fun(ri, ci); + `checkh(ri, 32'h4567); + end + + //==== + + task fun_array(ref int af[2], const ref int cf[2]); +`ifdef T_NOINLINE + // verilator no_inline_task +`endif + `checkh(cf[0], 32'h1234); + `checkh(cf[1], 32'h2345); + af[0] = 32'h5678; + af[1] = 32'h6789; + endtask + // Not checkint - element of unpacked array + + initial begin + int ca[2]; + int ra[2]; + ca[0] = 32'h1234; + ca[1] = 32'h2345; + fun_array(ra, ca); + `checkh(ra[0], 32'h5678); + `checkh(ra[1], 32'h6789); + end + + //==== + + sub sub(.clk, .vr, .va); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + vr <= 32'h789; + va[0] <= 32'h89a; + va[1] <= 32'h9ab; + end + else if (cyc == 2) begin + `checkh(vr, 32'h987); + `checkh(va[0], 32'ha98); + `checkh(va[1], 32'ha9b); + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub(input clk, ref int vr, ref int va[2]); + + always @(posedge clk) begin + vr <= 32'h987; + va[0] <= 32'ha98; + va[1] <= 32'ha9b; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_ref_bad1.v b/SVIncCompil/Testcases/Verilator/t_var_ref_bad1.v new file mode 100644 index 0000000..0d2258a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_ref_bad1.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +// Make sure type errors aren't suppressable +// verilator lint_off WIDTH + +module t(/*AUTOARG*/); + + bit bad_parent; + sub sub + (.bad_sub_ref(bad_parent)); // Type mismatch + +endmodule + +module sub(ref real bad_sub_ref); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_ref_bad2.v b/SVIncCompil/Testcases/Verilator/t_var_ref_bad2.v new file mode 100644 index 0000000..e4d3dc1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_ref_bad2.v
@@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +// Make sure type errors aren't suppressable +// verilator lint_off WIDTH + +module t(/*AUTOARG*/); + + task checkset(const ref int bad_const_set); + bad_const_set = 32'h4567; // Bad setting const + endtask + + task checkset2(ref int int_ref); + endtask + + initial begin + int i; + byte bad_non_int; + checkset(i); + checkset2(bad_non_int); // Type mismatch + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_ref_bad3.v b/SVIncCompil/Testcases/Verilator/t_var_ref_bad3.v new file mode 100644 index 0000000..5fbf8b3 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_ref_bad3.v
@@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +// Make sure type errors aren't suppressable +// verilator lint_off WIDTH + +module t(ref int bad_primary_ref + /*AUTOARG*/); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_rsvd.v b/SVIncCompil/Testcases/Verilator/t_var_rsvd.v new file mode 100644 index 0000000..e4ea140 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_rsvd.v
@@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +// verilator lint_off SYMRSVDWORD + +module t (/*AUTOARG*/ + // Inputs + bool + ); + + input bool; // BAD + + reg vector; // OK, as not public + reg switch /*verilator public*/; // Bad + + typedef struct packed { + logic [31:0] vector; // OK, as not public + } test; + test t; + + // global is a 1800-2009 reserved word, but we allow it when possible. + reg global; + + initial begin + t.vector = 1; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_rsvd_port.v b/SVIncCompil/Testcases/Verilator/t_var_rsvd_port.v new file mode 100644 index 0000000..615bba5 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_rsvd_port.v
@@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + bool + ); + + input bool; // BAD + + reg vector; // OK, as not public + reg switch /*verilator public*/; // Bad + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_set_link.v b/SVIncCompil/Testcases/Verilator/t_var_set_link.v new file mode 100644 index 0000000..c12cf79 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_set_link.v
@@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + state, + // Inputs + clk + ); + input clk; + + // Gave "Internal Error: V3Broken.cpp:: Broken link in node" + output [1:0] state; + reg [1:0] state = 2'b11; + always @ (posedge clk) begin + state <= state; + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_static.v b/SVIncCompil/Testcases/Verilator/t_var_static.v new file mode 100644 index 0000000..ad8f2a8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_static.v
@@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + function int f_no_no (); + int st = 2; st++; return st; + endfunction + function int f_no_st (); + static int st = 2; st++; return st; + endfunction + function int f_no_au (); + automatic int st = 2; st++; return st; + endfunction + + function static int f_st_no (); + int st = 2; st++; return st; + endfunction + function static int f_st_st (); + static int st = 2; st++; return st; + endfunction + function static int f_st_au (); + automatic int st = 2; st++; return st; + endfunction + + function automatic int f_au_no (); + int st = 2; st++; return st; + endfunction + function automatic int f_au_st (); + static int st = 2; st++; return st; + endfunction + function automatic int f_au_au (); + automatic int st = 2; st++; return st; + endfunction + + initial begin + if (f_no_no() != 3) $stop; + if (f_no_no() != 4) $stop; + if (f_no_st() != 3) $stop; + if (f_no_st() != 4) $stop; + if (f_no_au() != 3) $stop; + if (f_no_au() != 3) $stop; + // + if (f_st_no() != 3) $stop; + if (f_st_no() != 4) $stop; + if (f_st_st() != 3) $stop; + if (f_st_st() != 4) $stop; + if (f_st_au() != 3) $stop; + if (f_st_au() != 3) $stop; + // + if (f_au_no() != 3) $stop; + if (f_au_no() != 3) $stop; + if (f_au_st() != 3) $stop; + if (f_au_st() != 4) $stop; + if (f_au_au() != 3) $stop; + if (f_au_au() != 3) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_suggest_bad.v b/SVIncCompil/Testcases/Verilator/t_var_suggest_bad.v new file mode 100644 index 0000000..90685dd --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_suggest_bad.v
@@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + reg foobar; + + task boobar; endtask + + initial begin + if (foobat) $stop; + boobat; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_tieout.v b/SVIncCompil/Testcases/Verilator/t_var_tieout.v new file mode 100644 index 0000000..efdf8f2 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_tieout.v
@@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +// bug291 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer out18; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire out1; // From test of Test.v + wire out19; // From test of Test.v + wire out1b; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out1 (out1), + .out18 (out18), + .out1b (out1b), + .out19 (out19)); + + // Test loop + always @ (posedge clk) begin + if (out1 !== 1'b1) $stop; + if (out18 !== 32'h18) $stop; + if (out1b !== 1'b1) $stop; + if (out19 !== 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module Test ( + output wire out1 = 1'b1, + output integer out18 = 32'h18, + output var out1b = 1'b1, + output var logic out19 = 1'b1 + ); +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_types.v b/SVIncCompil/Testcases/Verilator/t_var_types.v new file mode 100644 index 0000000..9d3bd81 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_types.v
@@ -0,0 +1,221 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/); + + // IEEE: integer_atom_type + byte d_byte; + shortint d_shortint; + int d_int; + longint d_longint; + integer d_integer; + time d_time; + chandle d_chandle; + + // IEEE: integer_atom_type + bit d_bit; + logic d_logic; + reg d_reg; + + bit [1:0] d_bit2; + logic [1:0] d_logic2; + reg [1:0] d_reg2; + + // IEEE: non_integer_type + //UNSUP shortreal d_shortreal; + real d_real; + realtime d_realtime; + + // Declarations using var + var byte v_b; +`ifndef VCS + var [2:0] v_b3; + var signed [2:0] v_bs; +`endif + + // verilator lint_off WIDTH + localparam p_implicit = {96{1'b1}}; + localparam [89:0] p_explicit = {96{1'b1}}; + localparam byte p_byte = {96{1'b1}}; + localparam shortint p_shortint = {96{1'b1}}; + localparam int p_int = {96{1'b1}}; + localparam longint p_longint = {96{1'b1}}; + localparam integer p_integer = {96{1'b1}}; + localparam reg p_reg = {96{1'b1}}; + localparam bit p_bit = {96{1'b1}}; + localparam logic p_logic = {96{1'b1}}; + localparam reg [0:0] p_reg1 = {96{1'b1}}; + localparam bit [0:0] p_bit1 = {96{1'b1}}; + localparam logic [0:0] p_logic1= {96{1'b1}}; + localparam reg [1:0] p_reg2 = {96{1'b1}}; + localparam bit [1:0] p_bit2 = {96{1'b1}}; + localparam logic [1:0] p_logic2= {96{1'b1}}; + // verilator lint_on WIDTH + + byte v_byte[2]; + shortint v_shortint[2]; + int v_int[2]; + longint v_longint[2]; + integer v_integer[2]; + time v_time[2]; + chandle v_chandle[2]; + bit v_bit[2]; + logic v_logic[2]; + reg v_reg[2]; + real v_real[2]; + realtime v_realtime[2]; + + // We do this in two steps so we can check that initialization inside functions works properly + // verilator lint_off WIDTH + function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction + function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction + function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction + function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction + function int f_int; int lv_int; f_int = lv_int; endfunction + function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction + function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction + function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction + function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction + function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction + function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction + function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction + function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction + function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction + function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction + function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction + function time f_time; time lv_time; f_time = lv_time; endfunction + function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction + // verilator lint_on WIDTH + +`ifdef verilator + // For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default! + `define XINIT 1'b1 + `define ALL_TWOSTATE 1'b1 +`else + `define XINIT 1'bx + `define ALL_TWOSTATE 1'b0 +`endif + +`define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \ + if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \ + begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \ + name = {96{1'b1}}; \ + if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ + if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \ + name = {96{1'bx}}; \ + if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \ + begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \ + + initial begin + // verilator lint_off WIDTH + // verilator lint_off UNSIGNED + // name b sign twost 0init + `CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1); + `CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1); + `CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1); + `CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1); + `CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0); + `CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0); + `CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1); + `CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1); + `CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0); + // verilator lint_on WIDTH + // verilator lint_on UNSIGNED + + // Can't CHECK_ALL(d_chandle), as many operations not legal on chandles +`ifdef VERILATOR // else indeterminate + if ($bits(d_chandle) !== 64) $stop; +`endif + +`define CHECK_P(name,nbits) \ + if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ + + // name b + `CHECK_P(p_implicit ,96); + `CHECK_P(p_implicit[0] ,1 ); + `CHECK_P(p_explicit ,90); + `CHECK_P(p_explicit[0] ,1 ); + `CHECK_P(p_byte ,8 ); + `CHECK_P(p_byte[0] ,1 ); + `CHECK_P(p_shortint ,16); + `CHECK_P(p_shortint[0] ,1 ); + `CHECK_P(p_int ,32); + `CHECK_P(p_int[0] ,1 ); + `CHECK_P(p_longint ,64); + `CHECK_P(p_longint[0] ,1 ); + `CHECK_P(p_integer ,32); + `CHECK_P(p_integer[0] ,1 ); + `CHECK_P(p_bit ,1 ); + `CHECK_P(p_logic ,1 ); + `CHECK_P(p_reg ,1 ); + `CHECK_P(p_bit1 ,1 ); + `CHECK_P(p_logic1 ,1 ); + `CHECK_P(p_reg1 ,1 ); + `CHECK_P(p_bit1[0] ,1 ); + `CHECK_P(p_logic1[0] ,1 ); + `CHECK_P(p_reg1[0] ,1 ); + `CHECK_P(p_bit2 ,2 ); + `CHECK_P(p_logic2 ,2 ); + `CHECK_P(p_reg2 ,2 ); + +`define CHECK_B(varname,nbits) \ + if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \ + + `CHECK_B(v_byte[1] ,8 ); + `CHECK_B(v_shortint[1] ,16); + `CHECK_B(v_int[1] ,32); + `CHECK_B(v_longint[1] ,64); + `CHECK_B(v_integer[1] ,32); + `CHECK_B(v_time[1] ,64); + //`CHECK_B(v_chandle[1] + `CHECK_B(v_bit[1] ,1 ); + `CHECK_B(v_logic[1] ,1 ); + `CHECK_B(v_reg[1] ,1 ); + //`CHECK_B(v_real[1] ,64); // $bits not allowed + //`CHECK_B(v_realtime[1] ,64); // $bits not allowed + +`define CHECK_F(fname,nbits,zeroinit) \ + if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \ + + // name b 0init + `CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96 + `CHECK_F(f_explicit ,90,1'b0); + `CHECK_F(f_byte ,8 ,1'b1); + `CHECK_F(f_shortint ,16,1'b1); + `CHECK_F(f_int ,32,1'b1); + `CHECK_F(f_longint ,64,1'b1); + `CHECK_F(f_integer ,32,1'b0); + `CHECK_F(f_time ,64,1'b0); +`ifdef VERILATOR // else indeterminate + `CHECK_F(f_chandle ,64,1'b0); +`endif + `CHECK_F(f_bit ,1 ,1'b1); + `CHECK_F(f_logic ,1 ,1'b0); + `CHECK_F(f_reg ,1 ,1'b0); + `CHECK_F(f_bit1 ,1 ,1'b1); + `CHECK_F(f_logic1 ,1 ,1'b0); + `CHECK_F(f_reg1 ,1 ,1'b0); + `CHECK_F(f_bit2 ,2 ,1'b1); + `CHECK_F(f_logic2 ,2 ,1'b0); + `CHECK_F(f_reg2 ,2 ,1'b0); + + // For unpacked types we don't want width warnings for unsized numbers that fit + d_byte = 2; + d_shortint= 2; + d_int = 2; + d_longint = 2; + d_integer = 2; + + // Special check + d_time = $time; + if ($time !== d_time) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_types_bad.v b/SVIncCompil/Testcases/Verilator/t_var_types_bad.v new file mode 100644 index 0000000..e67cd76 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_types_bad.v
@@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/); + + // IEEE: integer_atom_type + byte d_byte; + shortint d_shortint; + int d_int; + longint d_longint; + integer d_integer; + time d_time; + chandle d_chandle; + + // IEEE: integer_atom_type + bit d_bit; + logic d_logic; + reg d_reg; + + bit [0:0] d_bit1; + logic [0:0] d_logic1; + reg [0:0] d_reg1; + + bit d_bitz; + logic d_logicz; + reg d_regz; + + // IEEE: non_integer_type + //UNSUP shortreal d_shortreal; + real d_real; + realtime d_realtime; + + initial begin + // below errors might cause spurious warnings + // verilator lint_off WIDTH + d_bitz[0] = 1'b1; // Illegal range + d_logicz[0] = 1'b1; // Illegal range + d_regz[0] = 1'b1; // Illegal range + +`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now + d_chandle[0] = 1'b1; // Illegal +`endif + d_real[0] = 1'b1; // Illegal + d_realtime[0] = 1'b1; // Illegal + // verilator lint_on WIDTH + + d_byte[0] = 1'b1; // OK + d_shortint[0] = 1'b1; // OK + d_int[0] = 1'b1; // OK + d_longint[0] = 1'b1; // OK + d_integer[0] = 1'b1; // OK + d_time[0] = 1'b1; // OK + + d_bit1[0] = 1'b1; // OK + d_logic1[0] = 1'b1; // OK + d_reg1[0] = 1'b1; // OK + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_vec_sel.v b/SVIncCompil/Testcases/Verilator/t_var_vec_sel.v new file mode 100644 index 0000000..22e1354 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_vec_sel.v
@@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// bug601 + +module t ( + input clk, + input [3:0] in3, // worky + input [0:0] in2 [3:0], // worky + input in1 [3:0], // no worky + input [1:0] sel, + output reg out1, + output reg out2, + output reg out3 + ); + + always @(posedge clk) begin + out3 <= in3[sel] ? in3[sel] : out3; + out2 <= in2[sel] ? in2[sel] : out2; + out1 <= in1[sel] ? in1[sel] : out1; // breaks + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_var_xref_gen.v b/SVIncCompil/Testcases/Verilator/t_var_xref_gen.v new file mode 100644 index 0000000..ac15a24 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_var_xref_gen.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This is to test the handling of VarXRef when the referenced VAR is +// under a generate construction. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Jie Xu and Roland Kruse. + +module t (/*AUTOARG*/ + // Inputs + clk, addr, res + ); + + input clk; + + input [31:0] addr; + output [15:0] res; + + memory i_mem(.addr(addr),.dout(res)); + + assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0; + +endmodule + + + +module memory(addr, dout); + parameter CM_XROWSIZE = 256; + parameter CM_NUMXROWS = 2; + + input [31:0] addr; + output [15:0] dout; + + generate + genvar g_cx; + for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++) + begin: cxrow_inst + reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1]; + end + endgenerate + + assign dout = cxrow_inst[0].cmem_xrow[addr]; +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_verilated_all.v b/SVIncCompil/Testcases/Verilator/t_verilated_all.v new file mode 100644 index 0000000..8746bff --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_verilated_all.v
@@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc!=0) begin + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); + + export "DPI-C" function dpix_f_int; + function int dpix_f_int (); + return cyc; + endfunction +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_verilated_debug.v b/SVIncCompil/Testcases/Verilator/t_verilated_debug.v new file mode 100644 index 0000000..d90fb77 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_verilated_debug.v
@@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Test loop + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_vlt_warn.v b/SVIncCompil/Testcases/Verilator/t_vlt_warn.v new file mode 100644 index 0000000..315e086 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_vlt_warn.v
@@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +// Try inline config +`ifdef verilator + `verilator_config + lint_off -msg CASEX -file "t/t_vlt_warn.v" + `verilog +`endif + + + + + +module t; + reg width_warn_var_line18 = 2'b11; // Width warning - must be line 18 + reg width_warn2_var_line19 = 2'b11; // Width warning - must be line 19 + reg width_warn3_var_line20 = 2'b11; // Width warning - must be line 20 + + initial begin + casex (1'b1) + 1'b0: $stop; + endcase + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_vpi_get.v b/SVIncCompil/Testcases/Verilator/t_vpi_get.v new file mode 100644 index 0000000..4bc4740 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_vpi_get.v
@@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef USE_VPI_NOT_DPI +//We call it via $c so we can verify DPI isn't required - see bug572 +`else +import "DPI-C" context function integer mon_check(); +`endif + +module t (/*AUTOARG*/ + // Inputs + input clk /*verilator public_flat_rd */, + + // test ports + input [15:0] testin /*verilator public_flat_rd */, + output [23:0] testout /*verilator public_flat_rw @(posedge clk) */ + + ); + +`ifdef VERILATOR +`systemc_header +extern "C" int mon_check(); +`verilog +`endif + + reg onebit /*verilator public_flat_rw @(posedge clk) */; + reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; + reg onetwo [1:2] /*verilator public_flat_rw @(posedge clk) */; + reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; + + integer status; + +`ifdef iverilog + // stop icarus optimizing signals away + wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3]; +`endif + + wire subin /*verilator public_flat_rd*/; + wire subout /*verilator public_flat_rd*/; + sub sub(.*); + + // Test loop + initial begin +`ifdef VERILATOR + status = $c32("mon_check()"); +`endif +`ifdef iverilog + status = $mon_check(); +`endif +`ifndef USE_VPI_NOT_DPI + status = mon_check(); +`endif + if (status!=0) begin + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule : t + +module sub ( + input subin /*verilator public_flat_rd*/, + output subout /*verilator public_flat_rd*/ +); +endmodule : sub
diff --git a/SVIncCompil/Testcases/Verilator/t_vpi_memory.v b/SVIncCompil/Testcases/Verilator/t_vpi_memory.v new file mode 100644 index 0000000..ea16810 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_vpi_memory.v
@@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef USE_VPI_NOT_DPI +//We call it via $c so we can verify DPI isn't required - see bug572 +`else +import "DPI-C" context function integer mon_check(); +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + +`ifdef VERILATOR +`systemc_header +extern "C" int mon_check(); +`verilog +`endif + + input clk; + + reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */; + integer i, status; + + // Test loop + initial begin +`ifdef VERILATOR + status = $c32("mon_check()"); +`endif +`ifdef iverilog + status = $mon_check(); +`endif +`ifndef USE_VPI_NOT_DPI + status = mon_check(); +`endif + if (status!=0) begin + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; + end + for (i = 16; i > 0; i--) + if (mem0[i] !== i) begin + $write("%%Error: %d : GOT = %d EXP = %d\n", i, mem0[i], i); + status = 1; + end + if (status!=0) begin + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule : t
diff --git a/SVIncCompil/Testcases/Verilator/t_vpi_sc.v b/SVIncCompil/Testcases/Verilator/t_vpi_sc.v new file mode 100644 index 0000000..99e6af8 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_vpi_sc.v
@@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t; + + // bug1081 - We don't use VPI, just need SC with VPI + + initial begin + $write("%0t: Hello\n", $time); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule : t
diff --git a/SVIncCompil/Testcases/Verilator/t_vpi_unimpl.v b/SVIncCompil/Testcases/Verilator/t_vpi_unimpl.v new file mode 100644 index 0000000..f562708 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_vpi_unimpl.v
@@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VERILATOR +//We call it via $c so we can verify DPI isn't required - see bug572 +`else +import "DPI-C" context function integer mon_check(); +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + +`ifdef VERILATOR +`systemc_header +extern "C" int mon_check(); +`verilog +`endif + + input clk; + + reg onebit /*verilator public_flat_rw @(posedge clk) */; + + integer status; + + // Test loop + initial begin +`ifdef VERILATOR + status = $c32("mon_check()"); +`else + status = mon_check(); +`endif + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule : t
diff --git a/SVIncCompil/Testcases/Verilator/t_vpi_var.v b/SVIncCompil/Testcases/Verilator/t_vpi_var.v new file mode 100644 index 0000000..dfa61ec --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_vpi_var.v
@@ -0,0 +1,129 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef USE_VPI_NOT_DPI +//We call it via $c so we can verify DPI isn't required - see bug572 +`else +import "DPI-C" context function integer mon_check(); +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + +`ifdef VERILATOR +`systemc_header +extern "C" int mon_check(); +`verilog +`endif + + input clk; + + reg onebit /*verilator public_flat_rw @(posedge clk) */; + reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; + reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; + + reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */; + + reg [31:0] count /*verilator public_flat_rd */; + reg [31:0] half_count /*verilator public_flat_rd */; + + reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; + reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; + reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; + reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; + reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; + + integer status; + + sub sub(); + + // Test loop + initial begin + count = 0; + onebit = 1'b0; + fourthreetwoone[3] = 0; // stop icarus optimizing away + text_byte = "B"; + text_half = "Hf"; + text_word = "Word"; + text_long = "Long64b"; + text = "Verilog Test module"; +`ifdef VERILATOR + status = $c32("mon_check()"); +`endif +`ifdef iverilog + status = $mon_check(); +`endif +`ifndef USE_VPI_NOT_DPI + status = mon_check(); +`endif + if (status!=0) begin + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("%%Info: Checking results\n"); + if (onebit != 1'b1) $stop; + if (quads[2] != 62'h12819213_abd31a1c) $stop; + if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; + if (text_byte != "A") $stop; + if (text_half != "T2") $stop; + if (text_word != "Tree") $stop; + if (text_long != "44Four44") $stop; + if (text != "lorem ipsum") $stop; + end + + always @(posedge clk) begin + count <= count + 2; + if (count[1]) + half_count <= half_count + 2; + + if (count == 1000) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + genvar i; + generate + for (i=1; i<=128; i=i+1) begin : arr + arr #(.LENGTH(i)) arr(); + end endgenerate + +endmodule : t + +module sub; + reg subsig1 /*verilator public_flat_rd*/; + reg subsig2 /*verilator public_flat_rd*/; +`ifdef iverilog + // stop icarus optimizing signals away + wire redundant = subsig1 | subsig2; +`endif +endmodule : sub + +module arr; + + parameter LENGTH = 1; + + reg [LENGTH-1:0] sig /*verilator public_flat_rw*/; + reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/; + + reg check /*verilator public_flat_rw*/; + reg verbose /*verilator public_flat_rw*/; + + initial begin + sig = {LENGTH{1'b0}}; + rfr = {LENGTH{1'b0}}; + end + + always @(posedge check) begin + if (verbose) $display("%m : %x %x", sig, rfr); + if (check && sig != rfr) $stop; + check <= 0; + end + +endmodule : arr
diff --git a/SVIncCompil/Testcases/Verilator/t_wire_beh_bad.v b/SVIncCompil/Testcases/Verilator/t_wire_beh_bad.v new file mode 100644 index 0000000..b6478af --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_wire_beh_bad.v
@@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Wilson Snyder. + +module t (/*AUTOARG*/); + + wire w; + reg r; + + assign r = 1'b1; + always @ (r) w = 1'b0; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_wire_types.v b/SVIncCompil/Testcases/Verilator/t_wire_types.v new file mode 100644 index 0000000..7145c35 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_wire_types.v
@@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%g exp=%g\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + + // IEEE: integer_atom_type + wire byte w_byte; + wire shortint w_shortint; + wire int w_int; + wire longint w_longint; + wire integer w_integer; + + // IEEE: integer_atom_type + wire bit w_bit; + wire logic w_logic; + + wire bit [1:0] w_bit2; + wire logic [1:0] w_logic2; + + // IEEE: non_integer_type + //UNSUP shortreal w_shortreal; + wire real w_real; + + assign w_byte = 8'h12; + assign w_shortint = 16'h1234; + assign w_int = -123456; + assign w_longint = -1234567; + assign w_integer = -123456; + + assign w_bit = 1'b1; + assign w_logic = 1'b1; + + assign w_bit2 = 2'b10; + assign w_logic2 = 2'b10; + + assign w_real = 3.14; + + always @ (posedge clk) begin + `checkh(w_byte, 8'h12); + `checkh(w_shortint, 16'h1234); + `checkh(w_int, -123456); + `checkh(w_longint, -1234567); + `checkh(w_integer, -123456); + `checkh(w_bit, 1'b1); + `checkh(w_logic, 1'b1); + `checkh(w_bit2, 2'b10); + `checkh(w_logic2, 2'b10); + `checkr(w_real, 3.14); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_xml_first.v b/SVIncCompil/Testcases/Verilator/t_xml_first.v new file mode 100644 index 0000000..cf58091 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_xml_first.v
@@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + q, + // Inputs + clk, d + ); + input clk; + input [3:0] d; + output wire [3:0] q; + + logic [3:0] between; + + mod1 cell1 (.q(between), + /*AUTOINST*/ + // Inputs + .clk (clk), + .d (d[3:0])); + + mod2 cell2 (.d(between), + /*AUTOINST*/ + // Outputs + .q (q[3:0]), + // Inputs + .clk (clk)); + +endmodule + +module mod1 + ( + input clk, + input [3:0] d, + output logic [3:0] q + ); + always @(posedge clk) + q <= d; + +endmodule + +module mod2 + ( + input clk, + input [3:0] d, + output wire [3:0] q + ); + + assign q = d; + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_xml_tag.v b/SVIncCompil/Testcases/Verilator/t_xml_tag.v new file mode 100644 index 0000000..0310d1a --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_xml_tag.v
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Chris Randall. + +interface ifc; + integer value; + modport out_modport (output value); +endinterface + +module m + ( + input clk_ip, // verilator tag clk_ip + input rst_ip, + output foo_op); // verilator tag foo_op + + // This is a comment + + typedef struct packed { + logic clk; /* verilator tag this is clk */ + logic k; /* verilator lint_off UNUSED */ + logic enable; // verilator tag enable + logic data; // verilator tag data + } my_struct; // verilator tag my_struct + + // This is a comment + + ifc itop(); + + my_struct this_struct [2]; // verilator tag this_struct + + wire [31:0] dotted = itop.value; + + function f(input string m); + $display("%s", m); + endfunction + + initial begin + // Contains all 256 characters except 0 (null character) + f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/t_xml_tag.v~ b/SVIncCompil/Testcases/Verilator/t_xml_tag.v~ new file mode 100644 index 0000000..1126c80 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/t_xml_tag.v~
@@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Chris Randall. + +interface ifc; + integer value; + modport out_modport (output value); +endinterface + +module m + ( + input clk_ip, // verilator tag clk_ip + input rst_ip, + output foo_op); // verilator tag foo_op + + // This is a comment + + typedef struct packed { + logic clk; /* verilator tag this is clk */ + logic k; /* verilator lint_off UNUSED */ + logic enable; // verilator tag enable + logic data; // verilator tag data + } my_struct; // verilator tag my_struct + + // This is a comment + + ifc itop(); + + my_struct this_struct [2]; // verilator tag this_struct + + wire [31:0] dotted = itop.value; + + function f(input string m); + $display("%s", m); + endfunction + + initial begin + // Contains all 256 characters except 0 (null character) + f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); + end + +endmodule
diff --git a/SVIncCompil/Testcases/Verilator/tog b/SVIncCompil/Testcases/Verilator/tog new file mode 100644 index 0000000..5b5ede1 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/tog
@@ -0,0 +1,2172 @@ +******************************************** +* SURELOG System Verilog Compiler/Linter * +******************************************** + +[INFO :CM0023] Creating log file ./slpp_unit/surelog.log. + +[INFO :CM0024] Executing with 4 threads. + +[INFO :CM0020] Separate compilation-unit mode is on. + +[INFO :PP0122] Preprocessing source file "../../dist/Release/GNU-Linux/../sv/builtin.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac_ana.sv". + +[INFO :PP0122] Preprocessing source file "t_sv_cpu_code/ac_dig.sv". + +[INFO :PP0122] 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Preprocessing source file "t_param_up_bad.v". + +[INFO :PP0122] Preprocessing source file "t_param.v". + +[INFO :PP0122] Preprocessing source file "t_tri_dangle.v". + +[INFO :PP0122] Preprocessing source file "t_tri_gate.v". + +[INFO :PP0122] Preprocessing source file "t_past_unsup_bad.v". + +[INFO :PP0122] Preprocessing source file "t_pipe_filter.v". + +[INFO :PP0122] Preprocessing source file "t_tri_graph.v". + +[INFO :PP0122] Preprocessing source file "t_pp_lib_library.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inout.v". + +[INFO :PP0122] Preprocessing source file "t_pp_lib.v". + +[INFO :PP0122] Preprocessing source file "t_pp_pragmas.v". + +[INFO :PP0122] Preprocessing source file "t_tri_public.v". + +[INFO :PP0122] Preprocessing source file "t_tri_select.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_inc_bad.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_noline.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_persist2.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_persist_inc.v". + +[INFO :PP0122] Preprocessing source file "t_preproc_undefineall.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_circ_bad.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_param.v". + +[INFO :PP0122] Preprocessing source file "t_repeat.v". + +[INFO :PP0122] Preprocessing source file "t_runflag_seed.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_signed.v". + +[INFO :PP0122] Preprocessing source file "t_struct_anon.v". + +[INFO :PP0122] Preprocessing source file "t_runflag.v". + +[INFO :PP0122] Preprocessing source file "t_savable.v". + +[INFO :PP0122] Preprocessing source file "t_struct_array.v". + +[INFO :PP0122] Preprocessing source file "t_uniqueif.v". + +[INFO :PP0122] Preprocessing source file "t_struct_init.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_combo.v". + +[INFO :PP0122] Preprocessing source file "t_select_bad_range3.v". + +[INFO :PP0122] Preprocessing source file "t_select_bad_range.v". + +[INFO :PP0122] Preprocessing source file "t_select_bound2.v". + +[INFO :PP0122] Preprocessing source file "t_var_assign_landr.v". + +[INFO :PP0122] Preprocessing source file "t_struct_param.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup2_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup3.v". + +[INFO :PP0122] Preprocessing source file "t_var_in_assign_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_in_assign.v". + +[INFO :PP0122] Preprocessing source file "t_select_little_pack.v". + +[INFO :PP0122] Preprocessing source file "t_select_little.v". + +[INFO :PP0122] Preprocessing source file "t_var_nonamebegin.v". + +[INFO :PP0122] Preprocessing source file "t_struct_pat_width.v". + +[INFO :PP0122] Preprocessing source file "t_var_overcmp.v". + +[INFO :PP0122] Preprocessing source file "t_struct_portsel.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref.v". + +[INFO :PP0122] Preprocessing source file "t_select_negative.v". + +[INFO :PP0122] Preprocessing source file "t_struct_unpacked_bad.v". + +[INFO :PP0122] Preprocessing source file "t_sv_conditional.v". + +[INFO :PP0122] Preprocessing source file "t_select_runtime_range.v". + +[INFO :PP0122] Preprocessing source file "t_var_types.v". + +[INFO :PP0122] Preprocessing source file "t_slice_init.v". + +[INFO :PP0122] Preprocessing source file "t_stream.v". + +[INFO :PP0122] Preprocessing source file "t_trace_fst.v". + +[INFO :PP0122] Preprocessing source file "t_tri_array.v". + +[INFO :PP0122] Preprocessing source file "t_tri_gen.v". + +[INFO :PP0122] Preprocessing source file "t_tri_ifbegin.v". + +[INFO :PP0122] Preprocessing source file "t_struct_unaligned.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inz.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull01.v". + +[INFO :PP0122] Preprocessing source file "t_sv_bus_mux_demux.v". + +[INFO :PP0122] Preprocessing source file "t_tri_various.v". + +[INFO :PP0122] Preprocessing source file "t_udp.v". + +[INFO :PP0122] Preprocessing source file "t_sys_plusargs_bad.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_addr.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_digit.v". + +[INFO :PP0122] Preprocessing source file "t_sys_readmem_bad_notfound.v". + +[INFO :PP0122] Preprocessing source file "t_sys_sformat.v". + +[INFO :PP0122] Preprocessing source file "t_unpacked_array_order.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_forfor.v". + +[INFO :PP0122] Preprocessing source file "t_vams_wreal.v". + +[INFO :PP0122] Preprocessing source file "t_var_const.v". + +[INFO :PP0122] Preprocessing source file "t_var_escape.v". + +[INFO :PP0122] Preprocessing source file "t_var_local.v". + +[INFO :PP0122] Preprocessing source file "t_var_notfound_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_outoforder.v". + +[INFO :PP0122] Preprocessing source file "t_var_pinsizes.v". + +[INFO :PP0122] Preprocessing source file "t_var_ref_bad3.v". + +[INFO :PP0122] Preprocessing source file "t_var_rsvd.v". + +[INFO :PP0122] Preprocessing source file "t_var_static.v". + +[INFO :PP0122] Preprocessing source file "t_var_xref_gen.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_get.v". + +[INFO :PP0122] Preprocessing source file "t_wire_beh_bad.v". + +[INFO :PP0122] Preprocessing source file "t_threads_counter.v". + +[INFO :PP0122] Preprocessing source file "t_xml_first.v". + +[INFO :PP0122] Preprocessing source file "t_trace_array.v". + +[INFO :PP0122] Preprocessing source file "t_trace_cat.v". + +[INFO :PP0122] Preprocessing source file "t_trace_complex.v". + +[INFO :PP0122] Preprocessing source file "t_trace_ena.v". + +[INFO :PP0122] Preprocessing source file "t_trace_primitive.v". + +[INFO :PP0122] Preprocessing source file "t_trace_timescale.v". + +[INFO :PP0122] Preprocessing source file "t_tri_array_bufif.v". + +[INFO :PP0122] Preprocessing source file "t_tri_inout2.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull2_bad.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pull_bad.v". + +[INFO :PP0122] Preprocessing source file "t_tri_pullup.v". + +[INFO :PP0122] Preprocessing source file "t_tri_select_unsized.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_array.v". + +[INFO :PP0122] Preprocessing source file "t_typedef_port.v". + +[INFO :PP0122] Preprocessing source file "t_typedef.v". + +[INFO :PP0122] Preprocessing source file "t_udp_noname.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_array.v". + +[INFO :PP0122] Preprocessing source file "t_unopt_converge_initial.v". + +[INFO :PP0122] Preprocessing source file "t_unoptflat_simple_2.v". + +[INFO :PP0122] Preprocessing source file "t_unoptflat_simple.v". + +[INFO :PP0122] Preprocessing source file "t_unroll_complexcond.v". + +[INFO :PP0122] Preprocessing source file "t_vams_basic.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_hide2.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_hide.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_sameas.v". + +[INFO :PP0122] Preprocessing source file "t_var_bad_sv.v". + +[INFO :PP0122] Preprocessing source file "t_var_const_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup2.v". + +[INFO :PP0122] Preprocessing source file "t_var_dup_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_init.v". + +[INFO :PP0122] Preprocessing source file "t_var_life.v". + +[INFO :PP0122] Preprocessing source file "t_var_overwidth_bad.v". + +[INFO :PP0122] Preprocessing source file "t_var_overzero.v". + +[INFO :PP0122] Preprocessing source file "t_var_types_bad.v". + +[INFO :PP0122] Preprocessing source file "t_verilated_all.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_memory.v". + +[INFO :PP0122] Preprocessing source file "t_vpi_var.v". + +[ERROR:PP0102] t_sv_cpu_code/ports.sv, line 44, col 9: Unknown macro "PACKED". + +[ERROR:PP0102] t_sv_cpu_code/ports.sv, line 49, col 11: Unknown macro "PACKED". + +[INFO :PP0123] Preprocessing include file "rom.sv". + +[ERROR:PP0101] t_sv_cpu_code/program_h.sv, line 31: Cannot open include file "rom.sv". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 18, col 6: Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 19, col 6: Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 20, col 6: Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 21, col 6: Unknown macro "LDI". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 23, col 6: Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 24, col 6: Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 25, col 6: Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 26, col 6: Unknown macro "STS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 28, col 6: Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 29, col 6: Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 30, col 6: Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 31, col 6: Unknown macro "LDS". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 33, col 6: Unknown macro "JMP". + +[ERROR:PP0102] t_sv_cpu_code/rom.sv, line 35, col 6: Unknown macro "EOP". + +[INFO :PP0123] Preprocessing include file "verilated.v". + +[ERROR:PP0101] t_case_write1_tasks.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0101] t_case_write1.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0102] t_case_write1.v, line 37, col 43: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_case_write1.v, line 38, col 36: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_case_write2_tasks.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0101] t_case_write2.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0102] t_case_write2.v, line 37, col 43: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_case_write2.v, line 38, col 36: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0106] t_clk_2in.v, line 26, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif + ^-- line 26, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 87, col 20: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif + ^-- line 87, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 108, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif + ^-- line 108, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 112, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif + ^-- line 112, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 116, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif + ^-- line 116, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 121, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif + ^-- line 121, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 125, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif + ^-- line 125, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 129, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif + ^-- line 129, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 135, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif + ^-- line 135, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 139, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif + ^-- line 139, t_clk_2in.v. + +[ERROR:PP0106] t_clk_2in.v, line 143, col 20: Syntax error: extraneous input '`display_counts' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE `display_counts("or vec"); `endif + ^-- line 143, t_clk_2in.v. + +[ERROR:PP0107] t_clk_2in.v, line 62: Too many arguments (4) for macro "t2", +t_clk_2in.v, line 59: macro definition takes 0. + +[ERROR:PP0106] t_clk_gen.v, line 79, col 17: Syntax error: extraneous input '`else' expecting {One_line_comment, Spaces, CR}, +`ifdef verilator `else // V3.2 races... technically legal + ^-- line 79, t_clk_gen.v. + +[ERROR:PP0118] t_display_esc_bad.v, line 8, col 19: Unknown escaped sequence '\y'. + +[ERROR:PP0118] t_display_esc_bad.v, line 8, col 21: Unknown escaped sequence '\z'. + +[ERROR:PP0118] t_display.v, line 13, col 39: Unknown escaped sequence '\2'. + +[ERROR:PP0118] t_display.v, line 134, col 30: Unknown escaped sequence '\r'. + +[INFO :PP0123] Preprocessing include file "t_dpi_accessors_macros_inc.vh". + +[INFO :PP0123] Preprocessing include file "t_dpi_accessors_inc.vh". + +[ERROR:PP0102] t_dpi_display.v, line 11, col 3: Unknown macro "error". + +[ERROR:PP0102] t_dpi_sys.v, line 15, col 3: Unknown macro "error". + +[ERROR:PP0102] t_dpi_threads.v, line 19, col 3: Unknown macro "error". + +[ERROR:PP0102] t_dpi_var.v, line 66: Unknown macro "systemc_imp_header". + +[ERROR:PP0102] t_dpi_var.v, line 69: Unknown macro "verilog". + +[ERROR:PP0102] t_extend_class.v, line 48, col 1: Unknown macro "systemc_header". + +[ERROR:PP0102] t_extend_class.v, line 50, col 1: Unknown macro "systemc_interface". + +[ERROR:PP0102] t_extend_class.v, line 52, col 1: Unknown macro "systemc_ctor". + +[ERROR:PP0102] t_extend_class.v, line 54, col 1: Unknown macro "systemc_dtor". + +[ERROR:PP0102] t_extend_class.v, line 56, col 1: Unknown macro "verilog". + +[INFO :PP0123] Preprocessing include file "t_flag_f_tsub_inc.v". + +[ERROR:PP0101] t_flag_f.v, line 3: Cannot open include file "t_flag_f_tsub_inc.v". + +[ERROR:PP0106] t_func_dotted.v, line 104, col 18: Syntax error: extraneous input '#1' expecting {One_line_comment, Spaces, CR}, +`ifndef verilator #1; `endif + ^-- line 104, t_func_dotted.v. + +[ERROR:PP0106] t_func_dotted.v, line 129, col 18: Syntax error: extraneous input '#1' expecting {One_line_comment, Spaces, CR}, +`ifndef verilator #1; `endif + ^-- line 129, t_func_dotted.v. + +[NOTE :PP0105] t_func_flip.v, line 7: Multiply defined macro "INT_RANGE", + t_func_flip.v, line 6: previous definition. + +[ERROR:PP0102] t_gen_missing.v, line 13, col 1: Unknown macro "error". + +[INFO :PP0123] Preprocessing include file "t_initial_inc.vh". + +[ERROR:PP0106] t_initial_inc.vh, line 8, col 12: Syntax error: extraneous input '`else' expecting {One_line_comment, Spaces, CR}, + `ifdef baz `else + ^-- line 8, t_initial_inc.vh. + +[ERROR:PP0106] t_inst_dtree.v, line 62, col 20: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif + ^-- line 62, t_inst_dtree.v. + +[ERROR:PP0106] t_interface2.v, line 25, col 17: Syntax error: extraneous input 'counter_ansi' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + ^-- line 25, t_interface2.v. + +[ERROR:PP0106] t_interface2.v, line 25, col 36: Syntax error: extraneous input 'counter_nansi' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + ^-- line 25, t_interface2.v. + +[ERROR:PP0102] t_interface_down_gen.v, line 75: Unknown macro "error". + +[ERROR:PP0106] t_interface_modport.v, line 42, col 17: Syntax error: extraneous input 'counter_ansi' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + ^-- line 42, t_interface_modport.v. + +[ERROR:PP0106] t_interface_modport.v, line 42, col 36: Syntax error: extraneous input 'counter_nansi' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi `else counter_nansi `endif + ^-- line 42, t_interface_modport.v. + +[ERROR:PP0106] t_interface_modport.v, line 49, col 17: Syntax error: extraneous input 'counter_ansi_m' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif + ^-- line 49, t_interface_modport.v. + +[ERROR:PP0106] t_interface_modport.v, line 49, col 38: Syntax error: extraneous input 'counter_nansi_m' expecting {One_line_comment, Spaces, CR}, +`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif + ^-- line 49, t_interface_modport.v. + +[ERROR:PP0120] t_lint_implicit_def_bad.v, line 21: Illegal directive in design element "`resetall". + +[INFO :PP0123] Preprocessing include file "/dev/null". + +[INFO :PP0123] Preprocessing include file "t_lint_in_inc_bad_1.vh". + +[INFO :PP0123] Preprocessing include file "t_lint_in_inc_bad_2.vh". + +[ERROR:PP0102] t_lint_unused.v, line 31, col 35: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_lint_unused.v, line 34, col 34: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0107] t_math_clog2.v, line 26: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 27: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 28: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 29: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 46: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 47: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 48: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 49: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 50: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 51: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 52: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 53: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 54: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 55: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 56: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 57: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[ERROR:PP0107] t_math_clog2.v, line 58: Too many arguments (1) for macro "CLOG2", +t_math_clog2.v, line 9: macro definition takes 0. + +[WARNI:PP0113] t_math_signed5.v, line 11, col 9: Unused macro argument "vs". + +[INFO :PP0123] Preprocessing include file "t_pipe_filter_inc.vh". + +[ERROR:PP0115] t_pp_circdef_bad.v, line 9: Recursive macro definition for "SEL_NUM_BITS", + t_pp_circdef_bad.v, line 9: macro used in macro "SEL_NUM_BITS". + +[ERROR:PP0102] t_pp_circdef_bad.v, line 9, col 7: Unknown macro "SEL_NUM_BITS". + +[ERROR:PP0102] t_pp_circdef_bad.v, line 9, col 24: Unknown macro "SEL_NUM_BITS". + +[WARNI:PP0113] t_pp_display.v, line 20, col 8: Unused macro argument "left". + +[ERROR:PP0109] t_pp_display.v, line 34: Macro instantiation omits argument 1 (x) for "thru", +t_pp_display.v, line 17: No default value for argument 1 (x) in macro definition. + +[NOTE :PP0105] t_pp_dupdef.v, line 9: Multiply defined macro "DUP", + t_pp_dupdef.v, line 8: previous definition. + +[NOTE :PP0105] t_pp_dupdef.v, line 12: Multiply defined macro "DUPP", + t_pp_dupdef.v, line 11: previous definition. + +[ERROR:PP0102] t_pp_lib_library.v, line 7, col 10: Unknown macro "WIDTH". + +[INFO :PP0123] Preprocessing include file "t_pp_lib_inc.vh". + +[ERROR:PP0102] t_pp_misdef_bad.v, line 10, col 3: Unknown macro "NDEFINED". + +[ERROR:PP0102] t_pp_misdef_bad.v, line 13, col 5: Unknown macro "imescale". + +[ERROR:PP0102] t_pp_pragmas.v, line 7: Unknown macro "verilog". + +[ERROR:PP0102] t_pp_pragmas.v, line 40: Unknown macro "remove_gatenames". + +[ERROR:PP0102] t_pp_pragmas.v, line 42: Unknown macro "remove_netnames". + +[ERROR:PP0112] t_preproc_def09.v, line 60, col 19: Illegal space in between macro name "MACROPAREN" and open parenthesis. + +[ERROR:PP0106] t_preproc_ifdef.v, line 17, col 9: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef A $display("1A"); num = num + 1; + ^-- line 17, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 18, col 10: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `ifdef C $stop; + ^-- line 18, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 19, col 10: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `elsif A $display("2A"); num = num + 1; + ^-- line 19, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 20, col 11: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `ifdef C $stop; + ^-- line 20, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 21, col 11: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `elsif B $stop; + ^-- line 21, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 22, col 9: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `else $display("3A"); num = num + 1; + ^-- line 22, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 24, col 8: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `else $stop; + ^-- line 24, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 26, col 10: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `elsif B $stop; + ^-- line 26, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 27, col 11: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `ifdef A $stop; + ^-- line 27, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 28, col 11: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, + `elsif A $stop; + ^-- line 28, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 31, col 9: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`elsif C $stop; + ^-- line 31, t_preproc_ifdef.v. + +[ERROR:PP0106] t_preproc_ifdef.v, line 32, col 7: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`else $stop; + ^-- line 32, t_preproc_ifdef.v. + +[INFO :PP0123] Preprocessing include file "t_preproc_inc_inc_bad.vh". + +[INFO :PP0123] Preprocessing include file "this_file_is_not_found.vh". + +[ERROR:PP0101] t_preproc_inc_notfound_bad.v, line 6: Cannot open include file "this_file_is_not_found.vh". + +[INFO :PP0123] Preprocessing include file "t_preproc_persist_inc.v". + +[ERROR:PP0106] t_preproc_undefineall.v, line 9, col 28: Syntax error: extraneous input '`error' expecting {One_line_comment, Spaces, CR}, +`ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif + ^-- line 9, t_preproc_undefineall.v. + +[ERROR:PP0106] t_preproc_undefineall.v, line 13, col 13: Syntax error: extraneous input '`error' expecting {One_line_comment, Spaces, CR}, +`ifdef UDALL `error "undefineall failed" `endif + ^-- line 13, t_preproc_undefineall.v. + +[ERROR:PP0106] t_preproc_undefineall.v, line 14, col 28: Syntax error: extraneous input '`error' expecting {One_line_comment, Spaces, CR}, +`ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif + ^-- line 14, t_preproc_undefineall.v. + +[ERROR:PP0102] t_preproc_undefineall.v, line 9, col 28: Unknown macro "error". + +[ERROR:PP0102] t_preproc_undefineall.v, line 14, col 28: Unknown macro "error". + +[ERROR:PP0106] t_preproc.v, line 23, col 19: Syntax error: extraneous input '1'b1 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A3 1'b1 `else 1'b0 `endif , + ^-- line 23, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 23, col 30: Syntax error: extraneous input '1'b0 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A3 1'b1 `else 1'b0 `endif , + ^-- line 23, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 23, col 42: Syntax error: no viable alternative at input '`endif ,', + `ifdef DEF_A3 1'b1 `else 1'b0 `endif , + ^-- line 23, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 24, col 19: Syntax error: extraneous input '1'b1 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A2 1'b1 `else 1'b0 `endif , + ^-- line 24, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 24, col 30: Syntax error: extraneous input '1'b0 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A2 1'b1 `else 1'b0 `endif , + ^-- line 24, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 24, col 42: Syntax error: no viable alternative at input '`endif ,', + `ifdef DEF_A2 1'b1 `else 1'b0 `endif , + ^-- line 24, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 25, col 19: Syntax error: extraneous input '1'b1 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A1 1'b1 `else 1'b0 `endif , + ^-- line 25, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 25, col 30: Syntax error: extraneous input '1'b0 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A1 1'b1 `else 1'b0 `endif , + ^-- line 25, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 25, col 42: Syntax error: no viable alternative at input '`endif ,', + `ifdef DEF_A1 1'b1 `else 1'b0 `endif , + ^-- line 25, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 26, col 19: Syntax error: extraneous input '1'b1 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A0 1'b1 `else 1'b0 `endif + ^-- line 26, t_preproc.v. + +[ERROR:PP0106] t_preproc.v, line 26, col 30: Syntax error: extraneous input '1'b0 ' expecting {One_line_comment, Spaces, CR}, + `ifdef DEF_A0 1'b1 `else 1'b0 `endif + ^-- line 26, t_preproc.v. + +[INFO :PP0123] Preprocessing include file "t_preproc_inc2.vh". + +[INFO :PP0123] Preprocessing include file "<t_preproc_inc3.vh>". + +[ERROR:PP0101] t_preproc_inc2.vh, line 6: Cannot open include file "<t_preproc_inc3.vh>". + +[ERROR:PP0112] t_preproc.v, line 74, col 16: Illegal space in between macro name "noparam" and open parenthesis. + +[NOTE :PP0105] t_preproc.v, line 99: Multiply defined macro "msg", + t_preproc.v, line 77: previous definition. + +[ERROR:PP0109] t_preproc.v, line 110: Macro instantiation omits argument 1 (x) for "thru", +t_preproc.v, line 97: No default value for argument 1 (x) in macro definition. + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv". + +[INFO :PP0123] Preprocessing include file "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv". + +[ERROR:PP0101] t_sys_file_basic.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0102] t_sys_file_basic.v, line 46, col 32: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0101] t_sys_file_scan.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0102] t_sys_file_scan.v, line 16, col 35: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0102] t_sys_fread.v, line 42, col 32: Unknown macro "TEST_OBJ_DIR". + +[ERROR:PP0106] t_sys_sformat.v, line 29, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("str=%0s",str); `endif + ^-- line 29, t_sys_sformat.v. + +[ERROR:PP0106] t_sys_sformat.v, line 34, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif + ^-- line 34, t_sys_sformat.v. + +[ERROR:PP0106] t_sys_sformat.v, line 38, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif + ^-- line 38, t_sys_sformat.v. + +[ERROR:PP0106] t_sys_sformat.v, line 47, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif + ^-- line 47, t_sys_sformat.v. + +[ERROR:PP0106] t_sys_sformat.v, line 51, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif + ^-- line 51, t_sys_sformat.v. + +[ERROR:PP0106] t_sys_sformat.v, line 55, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif + ^-- line 55, t_sys_sformat.v. + +[ERROR:PP0106] t_sys_sformat.v, line 59, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("chku %s %s",str3,str3); `endif + ^-- line 59, t_sys_sformat.v. + +[ERROR:PP0106] t_sys_sformat.v, line 63, col 21: Syntax error: extraneous input '$' expecting {One_line_comment, Spaces, CR}, +`ifdef TEST_VERBOSE $display("chkv %s %s",str3,str3); `endif + ^-- line 63, t_sys_sformat.v. + +[ERROR:PP0101] t_sys_sformat.v, line 6: Cannot open include file "verilated.v". + +[ERROR:PP0102] t_tri_gate.v, line 36, col 1: Unknown macro "error". + +[WARNI:PP0113] t_var_types.v, line 182, col 8: Unused macro argument "zeroinit". + +[ FATAL] : 0 +[ ERROR] : 143 +[WARNING] : 3 +[ NOTE] : 4 + +******************************************** +* End SURELOG SVerilog Compiler/Linter * +******************************************** +
diff --git a/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub.v b/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub.v new file mode 100644 index 0000000..04329e7 --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub.v
@@ -0,0 +1,3 @@ +// DESCRIPTION: Verilator: Verilog Test module + +`define GOT_DEF6
diff --git a/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub.vc b/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub.vc new file mode 100644 index 0000000..aa7e76c --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub.vc
@@ -0,0 +1,5 @@ +// DESCRIPTION: Verilator: Verilog Test module + ++define+GOT_DEF4=1 ++incdir+. +t_flag_f_tsub.v
diff --git a/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub_inc.v b/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub_inc.v new file mode 100644 index 0000000..840561d --- /dev/null +++ b/SVIncCompil/Testcases/Verilator/tsub/t_flag_f_tsub_inc.v
@@ -0,0 +1,3 @@ +// DESCRIPTION: Verilator: Verilog Test module + +`define GOT_DEF5