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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[INFO :CP0300] Compilation...

[INFO :CP0303] cam_bram.vh:32 Compile module "work@cam_bram".

[INFO :CP0303] cam_bram_top.v:32 Compile module "work@cam_bram_top".

[INFO :CP0303] cam_srl.vh:32 Compile module "work@cam_srl".

[INFO :CP0303] cam_srl_top.v:32 Compile module "work@cam_srl_top".

[INFO :CP0303] priority_encoder.vh:32 Compile module "work@priority_encoder".

[INFO :CP0303] ram_dp.vh:32 Compile module "work@ram_dp".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] cam_bram_top.v:32 Top level module "work@cam_bram_top".

[NOTE :EL0503] cam_srl_top.v:32 Top level module "work@cam_srl_top".

[NOTE :EL0504] Multiple top level modules in design.

[NOTE :EL0508] Nb Top level modules: 2.

[NOTE :EL0509] Max instance depth: 4.

[NOTE :EL0510] Nb instances: 6.

[NOTE :EL0511] Nb leaf instances: 0.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 7

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*   End SURELOG SVerilog Compiler/Linter   *
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2.05user 0.02system 0:02.10elapsed 98%CPU (0avgtext+0avgdata 62300maxresident)k
56inputs+656outputs (0major+12935minor)pagefaults 0swaps