| commit | d064da95cdcb55238fe7af7576ff5f7c9b7c46a0 | [log] [tgz] |
|---|---|---|
| author | Alain Dargelas <5085492+alainmarcel@users.noreply.github.com> | Sun Nov 17 00:13:56 2019 -0800 |
| committer | GitHub <noreply@github.com> | Sun Nov 17 00:13:56 2019 -0800 |
| tree | 62d07bd877dd6836c11e827a7d82be687b3437e5 | |
| parent | 28b991cf880c0cec9bc74d2d04a4b5da9f4e5c4d [diff] | |
| parent | cc85bcd42b8a7539f596b696b5cc095635221bdd [diff] |
Merge pull request #63 from alainmarcel/alainmarcel-patch-1 fixed typo and non-standard path
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.
The executable is located here:
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
`default_nettype in pre-processor's output