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*  SURELOG System Verilog Compiler/Linter  *
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Copyright (c) 2017-2019 ACE Cloud,
Authorized used only.

VERSION: 0.05
BUILT  : Oct  7 2019
DATE   : 2019-10-07.11:40:37
COMMAND: /home/alain/root_symbiflow/sv-tests/tests/chapter-12/12.5.2--case_const.sv -writepp -parse -mt max -l /home/alain/root_symbiflow/sv-tests/tests/chapter-12/12.5.2--case_const.sv.log -nostdout -verbose +define+DIGITS=10 +define+WIDTH=2

[INFO :CM0023] Creating log file /home/alain/root_symbiflow/sv-tests/tests/chapter-12/12.5.2--case_const.sv.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :PP0122] Preprocessing source file "/home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv".

[INFO :PP0122] Preprocessing source file "/home/alain/root_symbiflow/sv-tests/tests/chapter-12/12.5.2--case_const.sv".

[INFO :PA0201] Parsing source file "/home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv".

[INFO :PA0201] Parsing source file "/home/alain/root_symbiflow/sv-tests/tests/chapter-12/12.5.2--case_const.sv".

[WARNI:PA0205] /home/alain/root_symbiflow/sv-tests/tests/chapter-12/12.5.2--case_const.sv, line 7: No timescale set for "case_tb".

[INFO :CP0300] Compilation...

[INFO :CP0303] /home/alain/root_symbiflow/sv-tests/tests/chapter-12/12.5.2--case_const.sv, line 7: Compile module "work@case_tb".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 33: Compile class "work@process".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 4: Compile class "work@mailbox".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 58: Compile class "work@semaphore".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] /home/alain/root_symbiflow/sv-tests/tests/chapter-12/12.5.2--case_const.sv, line 7: Top level module "work@case_tb".

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 1.

[NOTE :EL0510] Nb instances: 1.

[NOTE :EL0511] Nb leaf instances: 0.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 1
[   NOTE] : 5

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*   End SURELOG SVerilog Compiler/Linter   *
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