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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[WARNI:PP0103] ./rtl/openMSP430_undefines.v:249 Undefining an unknown macro "PMEM_CUSTOM_AWIDTH".

[WARNI:PP0103] ./rtl/openMSP430_undefines.v:250 Undefining an unknown macro "PMEM_CUSTOM_SIZE".

[WARNI:PP0103] ./rtl/openMSP430_undefines.v:251 Undefining an unknown macro "DMEM_CUSTOM_AWIDTH".

[WARNI:PP0103] ./rtl/openMSP430_undefines.v:252 Undefining an unknown macro "DMEM_CUSTOM_SIZE".

[WARNI:PP0103] ./rtl/openMSP430_undefines.v:253 Undefining an unknown macro "PER_CUSTOM_AWIDTH".

[WARNI:PP0103] ./rtl/openMSP430_undefines.v:254 Undefining an unknown macro "PER_CUSTOM_SIZE".

[ERROR:PP0102] ./rtl/openMSP430_defines.v:626 Unknown macro "PER_SIZE".

[ERROR:PP0102] ./rtl/openMSP430_defines.v:629 Unknown macro "PMEM_AWIDTH".

[ERROR:PP0102] ./rtl/openMSP430_defines.v:630 Unknown macro "DMEM_AWIDTH".

[ERROR:PP0102] ./rtl/openMSP430_defines.v:631 Unknown macro "PER_AWIDTH".

[ERROR:PP0102] ./rtl/openMSP430_defines.v:813 Unknown macro "DBG_DCO_FREQ".

[ERROR:PP0102] ./rtl/openMSP430_defines.v:813 Unknown macro "DBG_UART_BAUD".

[WARNI:PP0103] rtl/openMSP430_undefines.v:249 Undefining an unknown macro "PMEM_CUSTOM_AWIDTH".

[WARNI:PP0103] rtl/openMSP430_undefines.v:250 Undefining an unknown macro "PMEM_CUSTOM_SIZE".

[WARNI:PP0103] rtl/openMSP430_undefines.v:251 Undefining an unknown macro "DMEM_CUSTOM_AWIDTH".

[WARNI:PP0103] rtl/openMSP430_undefines.v:252 Undefining an unknown macro "DMEM_CUSTOM_SIZE".

[WARNI:PP0103] rtl/openMSP430_undefines.v:253 Undefining an unknown macro "PER_CUSTOM_AWIDTH".

[WARNI:PP0103] rtl/openMSP430_undefines.v:254 Undefining an unknown macro "PER_CUSTOM_SIZE".

[ERROR:PA0207] sim/sieve.v:1 Syntax error: missing {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier} at '[',
pmem[ 512] = 16'h4031;
    ^-- ./slpp_unit/work/sim/sieve.v:1 col:4.

[WARNI:PA0205] rtl/omsp_alu.v:46 No timescale set for "omsp_alu".

[WARNI:PA0205] rtl/omsp_and_gate.v:44 No timescale set for "omsp_and_gate".

[WARNI:PA0205] rtl/omsp_clock_gate.v:44 No timescale set for "omsp_clock_gate".

[WARNI:PA0205] rtl/omsp_clock_module.v:46 No timescale set for "omsp_clock_module".

[WARNI:PA0205] rtl/omsp_clock_mux.v:44 No timescale set for "omsp_clock_mux".

[WARNI:PA0205] rtl/omsp_dbg.v:46 No timescale set for "omsp_dbg".

[WARNI:PA0205] rtl/omsp_dbg_hwbrk.v:46 No timescale set for "omsp_dbg_hwbrk".

[WARNI:PA0205] rtl/omsp_dbg_i2c.v:46 No timescale set for "omsp_dbg_i2c".

[WARNI:PA0205] rtl/omsp_dbg_uart.v:46 No timescale set for "omsp_dbg_uart".

[WARNI:PA0205] rtl/omsp_execution_unit.v:46 No timescale set for "omsp_execution_unit".

[WARNI:PA0205] rtl/omsp_frontend.v:46 No timescale set for "omsp_frontend".

[WARNI:PA0205] rtl/omsp_mem_backbone.v:46 No timescale set for "omsp_mem_backbone".

[WARNI:PA0205] rtl/omsp_multiplier.v:46 No timescale set for "omsp_multiplier".

[WARNI:PA0205] rtl/omsp_register_file.v:46 No timescale set for "omsp_register_file".

[WARNI:PA0205] rtl/omsp_scan_mux.v:44 No timescale set for "omsp_scan_mux".

[WARNI:PA0205] rtl/omsp_sfr.v:47 No timescale set for "omsp_sfr".

[WARNI:PA0205] rtl/omsp_sync_cell.v:44 No timescale set for "omsp_sync_cell".

[WARNI:PA0205] rtl/omsp_sync_reset.v:44 No timescale set for "omsp_sync_reset".

[WARNI:PA0205] rtl/omsp_wakeup_cell.v:46 No timescale set for "omsp_wakeup_cell".

[WARNI:PA0205] rtl/omsp_watchdog.v:46 No timescale set for "omsp_watchdog".

[WARNI:PA0205] rtl/openMSP430.v:46 No timescale set for "openMSP430".

[INFO :CP0300] Compilation...

[INFO :CP0303] rtl/omsp_alu.v:46 Compile module "work@omsp_alu".

[INFO :CP0303] rtl/omsp_and_gate.v:44 Compile module "work@omsp_and_gate".

[INFO :CP0303] rtl/omsp_clock_gate.v:44 Compile module "work@omsp_clock_gate".

[INFO :CP0303] rtl/omsp_clock_module.v:46 Compile module "work@omsp_clock_module".

[INFO :CP0303] rtl/omsp_clock_mux.v:44 Compile module "work@omsp_clock_mux".

[INFO :CP0303] rtl/omsp_dbg.v:46 Compile module "work@omsp_dbg".

[INFO :CP0303] rtl/omsp_dbg_hwbrk.v:46 Compile module "work@omsp_dbg_hwbrk".

[INFO :CP0303] rtl/omsp_dbg_i2c.v:46 Compile module "work@omsp_dbg_i2c".

[INFO :CP0303] rtl/omsp_dbg_uart.v:46 Compile module "work@omsp_dbg_uart".

[INFO :CP0303] rtl/omsp_execution_unit.v:46 Compile module "work@omsp_execution_unit".

[INFO :CP0303] rtl/omsp_frontend.v:46 Compile module "work@omsp_frontend".

[INFO :CP0303] rtl/omsp_mem_backbone.v:46 Compile module "work@omsp_mem_backbone".

[INFO :CP0303] rtl/omsp_multiplier.v:46 Compile module "work@omsp_multiplier".

[INFO :CP0303] rtl/omsp_register_file.v:46 Compile module "work@omsp_register_file".

[INFO :CP0303] rtl/omsp_scan_mux.v:44 Compile module "work@omsp_scan_mux".

[INFO :CP0303] rtl/omsp_sfr.v:47 Compile module "work@omsp_sfr".

[INFO :CP0303] rtl/omsp_sync_cell.v:44 Compile module "work@omsp_sync_cell".

[INFO :CP0303] rtl/omsp_sync_reset.v:44 Compile module "work@omsp_sync_reset".

[INFO :CP0303] rtl/omsp_wakeup_cell.v:46 Compile module "work@omsp_wakeup_cell".

[INFO :CP0303] rtl/omsp_watchdog.v:46 Compile module "work@omsp_watchdog".

[INFO :CP0303] rtl/openMSP430.v:46 Compile module "work@openMSP430".

[INFO :CP0303] sim/bench.v:6 Compile module "work@testbench".

[NOTE :CP0309] rtl/omsp_alu.v:49 Implicit port type (wire) for "alu_out",
there are 3 more instances of this message.

[NOTE :CP0309] rtl/omsp_and_gate.v:47 Implicit port type (wire) for "y".

[NOTE :CP0309] rtl/omsp_clock_gate.v:47 Implicit port type (wire) for "gclk".

[NOTE :CP0309] rtl/omsp_clock_module.v:49 Implicit port type (wire) for "aclk",
there are 14 more instances of this message.

[NOTE :CP0309] rtl/omsp_clock_mux.v:47 Implicit port type (wire) for "clk_out".

[NOTE :CP0309] rtl/omsp_dbg.v:49 Implicit port type (wire) for "dbg_cpu_reset",
there are 9 more instances of this message.

[NOTE :CP0309] rtl/omsp_dbg_hwbrk.v:49 Implicit port type (wire) for "brk_halt",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/omsp_dbg_i2c.v:50 Implicit port type (wire) for "dbg_din".

[NOTE :CP0309] rtl/omsp_dbg_uart.v:50 Implicit port type (wire) for "dbg_din",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/omsp_execution_unit.v:49 Implicit port type (wire) for "cpuoff",
there are 11 more instances of this message.

[NOTE :CP0309] rtl/omsp_frontend.v:50 Implicit port type (wire) for "decode_noirq",
there are 11 more instances of this message.

[NOTE :CP0309] rtl/omsp_mem_backbone.v:49 Implicit port type (wire) for "dbg_mem_din",
there are 15 more instances of this message.

[NOTE :CP0309] rtl/omsp_multiplier.v:49 Implicit port type (wire) for "per_dout".

[NOTE :CP0309] rtl/omsp_register_file.v:49 Implicit port type (wire) for "cpuoff",
there are 9 more instances of this message.

[NOTE :CP0309] rtl/omsp_scan_mux.v:47 Implicit port type (wire) for "data_out".

[NOTE :CP0309] rtl/omsp_sfr.v:50 Implicit port type (wire) for "cpu_id",
there are 5 more instances of this message.

[NOTE :CP0309] rtl/omsp_sync_cell.v:47 Implicit port type (wire) for "data_out".

[NOTE :CP0309] rtl/omsp_sync_reset.v:47 Implicit port type (wire) for "rst_s".

[NOTE :CP0309] rtl/omsp_watchdog.v:49 Implicit port type (wire) for "per_dout",
there are 3 more instances of this message.

[NOTE :CP0309] rtl/openMSP430.v:49 Implicit port type (wire) for "aclk",
there are 25 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] rtl/omsp_and_gate.v:44 Top level module "work@omsp_and_gate".

[NOTE :EL0503] rtl/omsp_clock_gate.v:44 Top level module "work@omsp_clock_gate".

[NOTE :EL0503] rtl/omsp_clock_mux.v:44 Top level module "work@omsp_clock_mux".

[NOTE :EL0503] rtl/omsp_dbg_hwbrk.v:46 Top level module "work@omsp_dbg_hwbrk".

[NOTE :EL0503] rtl/omsp_dbg_i2c.v:46 Top level module "work@omsp_dbg_i2c".

[NOTE :EL0503] rtl/omsp_scan_mux.v:44 Top level module "work@omsp_scan_mux".

[NOTE :EL0503] rtl/omsp_wakeup_cell.v:46 Top level module "work@omsp_wakeup_cell".

[NOTE :EL0503] sim/bench.v:6 Top level module "work@testbench".

[NOTE :EL0504] Multiple top level modules in design.

[NOTE :EL0508] Nb Top level modules: 8.

[NOTE :EL0509] Max instance depth: 5.

[NOTE :EL0510] Nb instances: 27.

[NOTE :EL0511] Nb leaf instances: 17.

[  FATAL] : 0
[  ERROR] : 7
[WARNING] : 33
[   NOTE] : 33

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*   End SURELOG SVerilog Compiler/Linter   *
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6.90user 0.12system 0:07.05elapsed 99%CPU (0avgtext+0avgdata 218144maxresident)k
728inputs+1512outputs (0major+51879minor)pagefaults 0swaps