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foss-fpga-tools/third_party/Surelog/d4d9deb8d36dfed0db4b721389484504809444ea/./SVIncCompil/Testcases/YosysTests/backends/write_verilog_latch
tree: fec6577d0b34e08d02498757480b20c667473328
  1. testbench.v
  2. top.v