| commit | 1c596881d1a7fc4baa7972b1f16b2e3d461aa200 | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Fri Nov 15 11:04:04 2019 -0800 |
| committer | Henner Zeller <h.zeller@acm.org> | Fri Nov 15 11:04:29 2019 -0800 |
| tree | 8be033b69952d3fe7986f9c00203937a25a28c47 | |
| parent | 76425fe9c1b685310008913d97503847d2f7f72e [diff] |
Don't use const for integral return types. It is confusing and doesn't do anything. Signed-off-by: Henner Zeller <h.zeller@acm.org>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.