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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[WARNI:PP0103] sim/bench.v:5 Undefining an unknown macro "WRITE_FRAMES_PPM".

[WARNI:PA0205] rtl/front_rom.v:1 No timescale set for "font_rom".

[WARNI:PA0205] rtl/text_graph.v:1 No timescale set for "text_graph".

[WARNI:PA0205] rtl/vga_sync.v:1 No timescale set for "vga_sync".

[WARNI:PA0205] sim/bench.v:7 No timescale set for "testbench".

[INFO :CP0300] Compilation...

[INFO :CP0303] rtl/debounce.v:2 Compile module "work@debounce".

[INFO :CP0303] rtl/front_rom.v:1 Compile module "work@font_rom".

[INFO :CP0303] rtl/pong_graph.v:2 Compile module "work@pong_graph".

[INFO :CP0303] sim/bench.v:7 Compile module "work@testbench".

[INFO :CP0303] rtl/vga_sync.v:1 Compile module "work@vga_sync".

[INFO :CP0303] rtl/top.v:2 Compile module "work@top".

[INFO :CP0303] rtl/text_graph.v:1 Compile module "work@text_graph".

[NOTE :CP0309] rtl/top.v:6 Implicit port type (wire) for "vsync".

[NOTE :CP0309] rtl/pong_graph.v:8 Implicit port type (wire) for "hit_left",
there are 2 more instances of this message.

[NOTE :CP0309] rtl/vga_sync.v:4 Implicit port type (wire) for "vsync",
there are 3 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] sim/bench.v:7 Top level module "work@testbench".

[WARNI:EL0505] rtl/data.v:1 Multiply defined module "work@font_rom",
               rtl/front_rom.v:1 previous definition.

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 4.

[NOTE :EL0510] Nb instances: 10.

[NOTE :EL0511] Nb leaf instances: 1.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 6
[   NOTE] : 8

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*   End SURELOG SVerilog Compiler/Linter   *
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5.21user 0.14system 0:02.76elapsed 193%CPU (0avgtext+0avgdata 132012maxresident)k
440inputs+832outputs (0major+32257minor)pagefaults 0swaps
sh: 2: -mt: not found