| commit | f33d931eea28829181d41a9058bcee033331a6dc | [log] [tgz] |
|---|---|---|
| author | Alain <alainmarcel@yahoo.com> | Sat Nov 16 07:41:35 2019 -0800 |
| committer | Alain <alainmarcel@yahoo.com> | Sat Nov 16 07:42:10 2019 -0800 |
| tree | d11529c251f6e95f4c3b5073e5cd9f68f1e77776 | |
| parent | 9a89f880d5afa02b13d200a98b278e782a7cafff [diff] |
added temporarily tests to noisy list Signed-off-by: Alain <alainmarcel@yahoo.com>
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).
This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.
INSTALLmake
For more build/test options and system requirements for building see src/README file.
The executable is located here
STANDARD VERILOG COMMAND LINE:
Defines a macro and optionally its value
FLOWS OPTIONS:
compilation unit (under slpp_unit/ if -writepp used)
separate compilation units to perform diffs
if "max" is given, the program will use one thread
per core on the host
TRACES OPTIONS:
OUTPUT OPTIONS:
(all compilation units will override this file)
units will generate files under slpp_all/ or slpp_unit/)
`default_nettype in pre-processor's output