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*  SURELOG System Verilog Compiler/Linter  *
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Copyright (c) 2017-2019 ACE Cloud,
Authorized used only.

VERSION: 0.05
BUILT  : Oct  1 2019
DATE   : 2019-10-01.09:14:39
COMMAND: tests/chapter-5/5.7.2-real-constants-illegal.sv -writepp -parse -mt max -l tests/chapter-5/5.7.2-real-constants-illegal.sv.log -nostdout -verbose +define+DIGITS=10 +define+WIDTH=2

[INFO :CM0023] Creating log file tests/chapter-5/5.7.2-real-constants-illegal.sv.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :PP0122] Preprocessing source file "/home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv".

[INFO :PP0122] Preprocessing source file "tests/chapter-5/5.7.2-real-constants-illegal.sv".

[INFO :PA0201] Parsing source file "tests/chapter-5/5.7.2-real-constants-illegal.sv".

[INFO :PA0201] Parsing source file "/home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv".

[ERROR:PA0207] tests/chapter-5/5.7.2-real-constants-illegal.sv, line 11, col 8: Syntax error: no viable alternative at input 'module top();\n  logic [31:0] a;\n\n  initial begin;\n    a = .',
    a = .12;
        ^-- line 11, ./slpp_all/work/tests/chapter-5/5.7.2-real-constants-illegal.sv.

[WARNI:PA0205] tests/chapter-5/5.7.2-real-constants-illegal.sv, line 7: No timescale set for "MODULE NAME UNKNOWN".

[INFO :CP0300] Compilation...

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 33: Compile class "work@process".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 4: Compile class "work@mailbox".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 58: Compile class "work@semaphore".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] tests/chapter-5/5.7.2-real-constants-illegal.sv, line 7: Top level module "work@MODULE NAME UNKNOWN".

[NOTE :EL0508] Nb Top level modules: 0.

[NOTE :EL0509] Max instance depth: 0.

[NOTE :EL0510] Nb instances: 0.

[NOTE :EL0511] Nb leaf instances: 0.

[  FATAL] : 0
[  ERROR] : 1
[WARNING] : 1
[   NOTE] : 5

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*   End SURELOG SVerilog Compiler/Linter   *
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