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foss-fpga-tools/third_party/Surelog/f013e089f9bd4fcbc5ef193ac9a2a69df4c92505/./SVIncCompil/Testcases/YosysBigSim/reed_solomon_decoder/sim
tree: 1415ba8037d5d5f8df65459b1517f4da8c68d66e
  1. input.txt
  2. output.txt
  3. RS_dec_tb.v
  4. settings.sh