********************************************
*  SURELOG System Verilog Compiler/Linter  *
********************************************

[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PP0101] fastfir_dynamictaps.v:20 Cannot open include file "fastfir.vh".

[ERROR:PP0101] fastfir_dynamictaps.v:21 Cannot open include file "firtap.vh".

[ERROR:PP0101] fastfir_fixedtaps.v:20 Cannot open include file "fastfir.vh".

[ERROR:PP0101] fastfir_fixedtaps.v:21 Cannot open include file "firtap.vh".

[ERROR:PP0101] slowfil_fixedtaps.v:21 Cannot open include file "slowfil.vh".

[WARNI:PA0205] dspswitch.v:40 No timescale set for "dspswitch".

[WARNI:PA0205] fastfir_dynamictaps.v:1 No timescale set for "fastfir_dynamictaps".

[WARNI:PA0205] fastfir_fixedtaps.v:1 No timescale set for "fastfir_fixedtaps".

[WARNI:PA0205] delayw.v:42 No timescale set for "delayw".

[WARNI:PA0205] fastfir.v:44 No timescale set for "fastfir".

[WARNI:PA0205] genericfir.v:41 No timescale set for "genericfir".

[WARNI:PA0205] firtap.v:55 No timescale set for "firtap".

[WARNI:PA0205] lfsr_gal.v:41 No timescale set for "lfsr_gal".

[WARNI:PA0205] slowfil_fixedtaps.v:1 No timescale set for "slowfil_fixedtaps".

[WARNI:PA0205] iiravg.v:41 No timescale set for "iiravg".

[WARNI:PA0205] boxcar.v:74 No timescale set for "boxcar".

[WARNI:PA0205] lfsr_fib.v:41 No timescale set for "lfsr_fib".

[WARNI:PA0205] slowfil.v:46 No timescale set for "slowfil".

[WARNI:PA0205] slowfil_srl.v:49 No timescale set for "slowfil_srl".

[WARNI:PA0205] lfsr.v:43 No timescale set for "lfsr".

[WARNI:PA0205] slowsymf.v:45 No timescale set for "slowsymf".

[WARNI:PA0205] shalfband.v:41 No timescale set for "shalfband".

[WARNI:PA0205] smplfir.v:47 No timescale set for "smplfir".

[WARNI:PA0205] slowfil_srl_fixedtaps.v:1 No timescale set for "slowfil_srl_fixedtaps".

[INFO :CP0300] Compilation...

[INFO :CP0303] boxcar.v:74 Compile module "work@boxcar".

[INFO :CP0303] delayw.v:42 Compile module "work@delayw".

[INFO :CP0303] dspswitch.v:40 Compile module "work@dspswitch".

[INFO :CP0303] fastfir.v:44 Compile module "work@fastfir".

[INFO :CP0303] fastfir_dynamictaps.v:1 Compile module "work@fastfir_dynamictaps".

[INFO :CP0303] fastfir_fixedtaps.v:1 Compile module "work@fastfir_fixedtaps".

[INFO :CP0303] firtap.v:55 Compile module "work@firtap".

[INFO :CP0303] genericfir.v:41 Compile module "work@genericfir".

[INFO :CP0303] lfsr.v:43 Compile module "work@lfsr".

[INFO :CP0303] iiravg.v:41 Compile module "work@iiravg".

[INFO :CP0303] lfsr_fib.v:41 Compile module "work@lfsr_fib".

[INFO :CP0303] lfsr_gal.v:41 Compile module "work@lfsr_gal".

[INFO :CP0303] slowfil.v:46 Compile module "work@slowfil".

[INFO :CP0303] shalfband.v:41 Compile module "work@shalfband".

[INFO :CP0303] slowfil_fixedtaps.v:1 Compile module "work@slowfil_fixedtaps".

[INFO :CP0303] slowfil_srl.v:49 Compile module "work@slowfil_srl".

[INFO :CP0303] slowsymf.v:45 Compile module "work@slowsymf".

[INFO :CP0303] smplfir.v:47 Compile module "work@smplfir".

[INFO :CP0303] slowfil_srl_fixedtaps.v:1 Compile module "work@slowfil_srl_fixedtaps".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] dspswitch.v:40 Top level module "work@dspswitch".

[NOTE :EL0503] fastfir_dynamictaps.v:1 Top level module "work@fastfir_dynamictaps".

[NOTE :EL0503] fastfir_fixedtaps.v:1 Top level module "work@fastfir_fixedtaps".

[NOTE :EL0503] delayw.v:42 Top level module "work@delayw".

[NOTE :EL0503] genericfir.v:41 Top level module "work@genericfir".

[NOTE :EL0503] lfsr_gal.v:41 Top level module "work@lfsr_gal".

[NOTE :EL0503] slowfil_fixedtaps.v:1 Top level module "work@slowfil_fixedtaps".

[NOTE :EL0503] iiravg.v:41 Top level module "work@iiravg".

[NOTE :EL0503] boxcar.v:74 Top level module "work@boxcar".

[NOTE :EL0503] lfsr_fib.v:41 Top level module "work@lfsr_fib".

[NOTE :EL0503] lfsr.v:43 Top level module "work@lfsr".

[NOTE :EL0503] slowsymf.v:45 Top level module "work@slowsymf".

[NOTE :EL0503] shalfband.v:41 Top level module "work@shalfband".

[NOTE :EL0503] smplfir.v:47 Top level module "work@smplfir".

[NOTE :EL0503] slowfil_srl_fixedtaps.v:1 Top level module "work@slowfil_srl_fixedtaps".

[WARNI:EL0505] slowfil_srl.vh:49 Multiply defined module "work@slowfil_srl",
               slowfil_srl.v:49 previous definition.

[NOTE :EL0504] Multiple top level modules in design.

[NOTE :EL0508] Nb Top level modules: 15.

[NOTE :EL0509] Max instance depth: 4.

[NOTE :EL0510] Nb instances: 403.

[NOTE :EL0511] Nb leaf instances: 3.

[  FATAL] : 0
[  ERROR] : 5
[WARNING] : 20
[   NOTE] : 20

********************************************
*   End SURELOG SVerilog Compiler/Linter   *
********************************************

8.54user 0.12system 0:02.68elapsed 323%CPU (0avgtext+0avgdata 124148maxresident)k
272inputs+2000outputs (0major+28395minor)pagefaults 0swaps