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SURELOG YOSYS FRONTEND BEGIN
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> Converting file "scripts/synth.ys"
read_verilog rtl/or1200_alu.v
read_verilog rtl/or1200_amultp2_32x32.v
read_verilog rtl/or1200_cfgr.v
read_verilog rtl/or1200_cpu.v
read_verilog rtl/or1200_ctrl.v
read_verilog rtl/or1200_dc_fsm.v
read_verilog rtl/or1200_dc_ram.v
read_verilog rtl/or1200_dc_tag.v
read_verilog rtl/or1200_dc_top.v
read_verilog rtl/or1200_defines.v
read_verilog rtl/or1200_dmmu_tlb.v
read_verilog rtl/or1200_dmmu_top.v
read_verilog rtl/or1200_dpram_256x32.v
read_verilog rtl/or1200_dpram_32x32.v
read_verilog rtl/or1200_dpram.v
read_verilog rtl/or1200_du.v
read_verilog rtl/or1200_except.v
read_verilog rtl/or1200_fpu_addsub.v
read_verilog rtl/or1200_fpu_arith.v
read_verilog rtl/or1200_fpu_div.v
read_verilog rtl/or1200_fpu_fcmp.v
read_verilog rtl/or1200_fpu_intfloat_conv_except.v
read_verilog rtl/or1200_fpu_intfloat_conv.v
read_verilog rtl/or1200_fpu_mul.v
read_verilog rtl/or1200_fpu_post_norm_addsub.v
read_verilog rtl/or1200_fpu_post_norm_div.v
read_verilog rtl/or1200_fpu_post_norm_intfloat_conv.v
read_verilog rtl/or1200_fpu_post_norm_mul.v
read_verilog rtl/or1200_fpu_pre_norm_addsub.v
read_verilog rtl/or1200_fpu_pre_norm_div.v
read_verilog rtl/or1200_fpu_pre_norm_mul.v
read_verilog rtl/or1200_fpu.v
read_verilog rtl/or1200_freeze.v
read_verilog rtl/or1200_genpc.v
read_verilog rtl/or1200_gmultp2_32x32.v
read_verilog rtl/or1200_ic_fsm.v
read_verilog rtl/or1200_ic_ram.v
read_verilog rtl/or1200_ic_tag.v
read_verilog rtl/or1200_ic_top.v
read_verilog rtl/or1200_if.v
read_verilog rtl/or1200_immu_tlb.v
read_verilog rtl/or1200_immu_top.v
read_verilog rtl/or1200_iwb_biu.v
read_verilog rtl/or1200_lsu.v
read_verilog rtl/or1200_mem2reg.v
read_verilog rtl/or1200_mult_mac.v
read_verilog rtl/or1200_operandmuxes.v
read_verilog rtl/or1200_pic.v
read_verilog rtl/or1200_pm.v
read_verilog rtl/or1200_qmem_top.v
read_verilog rtl/or1200_reg2mem.v
read_verilog rtl/or1200_rfram_generic.v
read_verilog rtl/or1200_rf.v
read_verilog rtl/or1200_sb_fifo.v
read_verilog rtl/or1200_sb.v
read_verilog rtl/or1200_spram_1024x32_bw.v
read_verilog rtl/or1200_spram_1024x32.v
read_verilog rtl/or1200_spram_1024x8.v
read_verilog rtl/or1200_spram_128x32.v
read_verilog rtl/or1200_spram_2048x32_bw.v
read_verilog rtl/or1200_spram_2048x32.v
read_verilog rtl/or1200_spram_2048x8.v
read_verilog rtl/or1200_spram_256x21.v
read_verilog rtl/or1200_spram_32_bw.v
read_verilog rtl/or1200_spram_32x24.v
read_verilog rtl/or1200_spram_512x20.v
read_verilog rtl/or1200_spram_64x14.v
read_verilog rtl/or1200_spram_64x22.v
read_verilog rtl/or1200_spram_64x24.v
read_verilog rtl/or1200_spram.v
read_verilog rtl/or1200_sprs.v
read_verilog rtl/or1200_top.v
read_verilog rtl/or1200_tpram_32x32.v
read_verilog rtl/or1200_tt.v
read_verilog rtl/or1200_wb_biu.v
read_verilog rtl/or1200_wbmux.v
read_verilog rtl/or1200_xcv_ram32x8d.v
> Ignoring hierarchy
> Converting file "../scripts/generic.ys"
> Ignoring hierarchy
> Ignoring yosys_proc
> Ignoring opt
> Ignoring memory
> Ignoring opt
> Ignoring techmap
> Ignoring opt
> Ignoring abc
> Ignoring opt
> Ignoring write_verilog
> Executing: surelog -mt max -parse  -writepp +incdir+.+rtl rtl/or1200_alu.v rtl/or1200_amultp2_32x32.v rtl/or1200_cfgr.v rtl/or1200_cpu.v rtl/or1200_ctrl.v rtl/or1200_dc_fsm.v rtl/or1200_dc_ram.v rtl/or1200_dc_tag.v rtl/or1200_dc_top.v rtl/or1200_defines.v rtl/or1200_dmmu_tlb.v rtl/or1200_dmmu_top.v rtl/or1200_dpram_256x32.v rtl/or1200_dpram_32x32.v rtl/or1200_dpram.v rtl/or1200_du.v rtl/or1200_except.v rtl/or1200_fpu_addsub.v rtl/or1200_fpu_arith.v rtl/or1200_fpu_div.v rtl/or1200_fpu_fcmp.v rtl/or1200_fpu_intfloat_conv_except.v rtl/or1200_fpu_intfloat_conv.v rtl/or1200_fpu_mul.v rtl/or1200_fpu_post_norm_addsub.v rtl/or1200_fpu_post_norm_div.v rtl/or1200_fpu_post_norm_intfloat_conv.v rtl/or1200_fpu_post_norm_mul.v rtl/or1200_fpu_pre_norm_addsub.v rtl/or1200_fpu_pre_norm_div.v rtl/or1200_fpu_pre_norm_mul.v rtl/or1200_fpu.v rtl/or1200_freeze.v rtl/or1200_genpc.v rtl/or1200_gmultp2_32x32.v rtl/or1200_ic_fsm.v rtl/or1200_ic_ram.v rtl/or1200_ic_tag.v rtl/or1200_ic_top.v rtl/or1200_if.v rtl/or1200_immu_tlb.v rtl/or1200_immu_top.v rtl/or1200_iwb_biu.v rtl/or1200_lsu.v rtl/or1200_mem2reg.v rtl/or1200_mult_mac.v rtl/or1200_operandmuxes.v rtl/or1200_pic.v rtl/or1200_pm.v rtl/or1200_qmem_top.v rtl/or1200_reg2mem.v rtl/or1200_rfram_generic.v rtl/or1200_rf.v rtl/or1200_sb_fifo.v rtl/or1200_sb.v rtl/or1200_spram_1024x32_bw.v rtl/or1200_spram_1024x32.v rtl/or1200_spram_1024x8.v rtl/or1200_spram_128x32.v rtl/or1200_spram_2048x32_bw.v rtl/or1200_spram_2048x32.v rtl/or1200_spram_2048x8.v rtl/or1200_spram_256x21.v rtl/or1200_spram_32_bw.v rtl/or1200_spram_32x24.v rtl/or1200_spram_512x20.v rtl/or1200_spram_64x14.v rtl/or1200_spram_64x22.v rtl/or1200_spram_64x24.v rtl/or1200_spram.v rtl/or1200_sprs.v rtl/or1200_top.v rtl/or1200_tpram_32x32.v rtl/or1200_tt.v rtl/or1200_wb_biu.v rtl/or1200_wbmux.v rtl/or1200_xcv_ram32x8d.v
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SURELOG YOSYS FRONTEND END
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